M28W320FST70ZA1 [NUMONYX]
Flash, 2MX16, 70ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64;
| 型号： | M28W320FST70ZA1 |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 2MX16, 70ns, PBGA64, 10 X 13 MM, 1 MM PITCH, TBGA-64 内存集成电路 闪存 |
| 文件： | 总76页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28W320FST M28W320FSB M28W320FSU
M28W640FST M28W640FSB M28W640FSU
32 Mbit (2 Mb ×16) and 64 Mbit (4 Mb ×16)
3 V supply, Boot Block and Uniform Block, Secure Flash memories
Features
■ Supply voltage
BGA
– V = 2.7 V to 3.6 V core supply voltage
DD
– V
= 2.7 V to 3.6 V Input/Output voltage
DDQ
– V = 12 V Fast Program voltage (optional)
PP
TBGA64 (ZA)
10 × 13 mm
■ Access time: 70 ns
■ Programming time:
– 10 µs typical
– Double Word Programming option
– Quadruple Word Programming option
FBGA
■ Common Flash Interface
■ Boot Block devices:
TFBGA47 (ZB)
6.39 x 6.37 mm
– Parameter Blocks (top or bottom location)
– Main Blocks
(1)
■ 64-KWord Uniform Block devices:
– M28W320FSU: 32 Blocks
– M28W640FSU: 64 Blocks
1. Only available in 32 Mbit devices.
■ Electronic signature
– Manufacturer Code: 20h
■ Hardware Protection
– Device Codes:
– V pin for write protect of all blocks
PP
M28W320FSU: 880Ch
M28W640FSU: 8857h
M28W320FST: 880Ah,
M28W320FSB: 880Bh
M28W640FST: 8858h,
M28W640FSB: 8859h
■ Security features
– 128 bit User-programmable OTP segment
– 64 bit Unique Device Identifier
– KRYPTO Features:
Modify Protection,
Read Protection,
■ ECOPACK® packages available
Device Authentication
■ Automatic Standby mode
■ Program and Erase Suspend
– 100 000 Program/Erase cycles per block
December 2006
Rev 3
1/76
www.st.com
1
Contents
M28WxxxFS, M28WxxxFSU
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Address Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
V
PP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
V
2.11 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.5
3.6
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
5
6
Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1
6.2
6.3
6.4
Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/76
M28WxxxFS, M28WxxxFSU
Contents
6.5
6.6
6.7
6.8
6.9
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.12 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9
10
11
Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Appendix D Command Interface and Program/Erase Controller state . . . . . . . 72
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3/76
List of tables
M28WxxxFS, M28WxxxFSU
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
M28W320FS and M28W640FS memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Protection Register and Protection Register Lock . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program/Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write ac characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power-Up and Reset ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TBGA64 - 10 × 13 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . 40
TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, package mechanical data. . . . . . . . . . 41
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Top Boot Block addresses, M28W320FST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Bottom Boot Block addresses, M28W320FSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Top Boot Block Addresses, M28W640FST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bottom Boot Block addresses, M28W640FSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Block addresses, M28W320FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Block addresses, M28W640FSU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 9.
Table 10.
Table 11.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
4/76
M28WxxxFS, M28WxxxFSU
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
M28W320FS logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M28W640FS logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M28W320FSU logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M28W640FSU logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TBGA64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TFBGA47 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M28W320FST and M28W320FSB block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M28W640FST and M28W640FSB block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M28W320FSU and M28W640FSU block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12. Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Power-Up and Reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. TBGA64 - 10 × 13 active ball array, 1 mm pitch, bottom view package outline . . . . . . . . . 40
Figure 17. TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, view through package. . . . . . . . . . . . . 41
Figure 18. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 19. Double Word Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20. Quadruple Word Program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 21. Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22. Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 23. Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24. Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 71
5/76
Description
M28WxxxFS, M28WxxxFSU
1
Description
The M28W320FST, M28W320FSB, and M28W320FSU are 32 Mbit (2 Mbit × 16) Secure
Flash memories; while the M28W640FST, M28W640FSB, and M28W640FSU are 64 Mbit
(4 Mbit × 16). In the present datasheet, the M28W320FST and M28W320FSB will be
referred to as M28W320FS, and the M28W640FST and M28W640FSB as M28W640FS.
The devices can be erased electrically at block level and programmed in-system on a Word-
by-Word basis using a 2.7 V to 3.6 V V supply for the circuitry and a 2.7 V to 3.6 V V
DD
DDQ
supply for the Input/Output pins. An optional 12 V V power supply is provided to speed up
PP
customer programming.
The M28W320FS and M28W640FS are boot block Flash memories. They have an
asymmetrical block architecture with 4 KWord Parameter Blocks and 32 KWord Main
Blocks. The M28W320FST and M28W640FST have the Parameter Blocks at the top of the
memory address space while the M28W320FSB and M28W640FSB locate the Parameter
Blocks starting from the bottom. Refer to Table 1, Figure 7, Figure 8 and Figure 9 for a
detailed description of the devices memory architecture and map.
The M28W320FSU and M28W640FSU are uniform block Flash memories. They are divided
into thirty-two and sixty-four 64-KWord Uniform blocks, respectively. Refer to Figure 7 for a
detailed description of the devices memory architecture and map.
All devices are equipped with hardware and software block protection features to avoid
unwanted program/erase (modify) or read of the Flash memory content:
■
Hardware Protection:
When V ≤V
–
all blocks are protected against program or erase.
PPLK
PP
■
Software Protection thanks to Krypto™ Security Features:
–
–
Modify Protection: volatile and non-volatile.
Read Protection.
The Krypto Security features are described in a dedicated Application Note. Please contact
STMicroelectronics for further details.
Two registers are available for protection purpose:
■
■
The Protection Register
The Krypto Protection Register.
The Protection Register is a 192 bit Protection Register to increase the protection of a
system design. The Protection Register is divided into a 64 bit segment and a 128 bit
segment. The 64 bit segment contains a unique device number written by ST, while the
second one is one-time-programmable by the user. The user programmable segment can
be permanently protected. Figure 10, shows the Protection Register Memory Map.
The Krypto Protection Register is used to manage the Modify and Read protection modes. It
also features a Device Authentication mechanism. The Krypto Protection Register is
described in a dedicated Application Note. Please contact STMicroelectronics for further
details.
Each block can be erased separately. Erase can be suspended in order to perform either
read or program in any other block and then resumed. Program can be suspended to read
data in any other block and then resumed. Each block can be programmed and erased over
100,000 cycles.
6/76
M28WxxxFS, M28WxxxFSU
Description
Program and Erase commands are written to the Command Interface of the memory. An on-
chip Program/Erase Controller takes care of the timings necessary for program and erase
operations. The end of a program or erase operation can be detected and any error
conditions identified. The command set required to control the memory is consistent with
JEDEC standards.
All the devices are offered in TBGA64 (10 × 13mm) packages. 32 Mbit devices are also
delivered in TFBGA47 (6.39 × 6.37mm) packages.
®
In order to meet environmental requirements, ST offers the devices in ECOPACK
packages. ECOPACK packages are Lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
All devices are supplied with all the bits erased (set to ’1’).
Table 1.
Device
M28W320FS and M28W640FS memory architecture
Parameter Blocks Main Blocks
No. of Blocks
Block Size(1)
No. of Blocks
Block Size
M28W320FS
M28W640FS
8
8
4 KWords
4 KWords
63
32 KWords
32 KWords
127
1. Erasable Block size.
Table 2.
Signal names
M28W640FST,
M28W320FST,
M28W320FSB,
M28W320FSU
M28W640FSB,
M28W640FSU
Signal names
A0-A20
A0-A21
Address Inputs
DQ0-DQ15
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
E
G
W
RP
VDD
VDDQ
VPP
VSS
VSSQ
NC
Core Power Supply
Power Supply for Input/Output
Optional Supply Voltage for Fast Program & Erase
Ground
Ground Input/Output supply
Not Connected Internally
7/76
Description
M28WxxxFS, M28WxxxFSU
Figure 1.
M28W320FS logic diagram
V
V
V
DD DDQ PP
21
16
A0-A20
DQ0-DQ15
W
E
M28W320FST
M28W320FSB
G
RP
V
V
SS SSQ
AI09925b
Figure 2.
M28W640FS logic diagram
V
V
V
DD DDQ PP
22
16
A0-A21
DQ0-DQ15
W
E
M28W640FST
M28W640FSB
G
RP
V
V
SS SSQ
AI09909b
8/76
M28WxxxFS, M28WxxxFSU
Description
Figure 3.
M28W320FSU logic diagram
V
V
V
DD DDQ PP
21
16
A0-A20
DQ0-DQ15
W
E
M28W320FSU
G
RP
V
V
SSQ
SS
AI10659b
Figure 4.
M28W640FSU logic diagram
V
V
V
DD DDQ PP
22
16
A0-A21
DQ0-DQ15
W
E
M28W640FSU
G
RP
V
V
SSQ
SS
AI10660b
9/76
Description
M28WxxxFS, M28WxxxFSU
Figure 5.
TBGA64 connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A0
A1
A5
A7
A8
V
A12
A13
V
A17
A18
A21
NC
A20
A16
NC
G
PP
E
DD
V
NC
NC
SS
A2
A6
A9
A11
RP
A14
A19
A3
A4
DQ1
DQ0
NC
A10
DQ9
DQ10
DQ2
NC
NC
A15
DQ8
NC
NC
NC
DQ3
DQ11
DQ4
DQ12
DQ5
DQ13
NC
DQ15
NC
NC
G
H
V
DQ6
DQ14
DQ7
W
DDQ
NC
V
V
V
NC
DD
SSQ
SS
AI09910b
1. The above figure gives the TBGA connections for the M28W640FST, M28W640FSB and M28W640FSU.
On the M28W320FST, M28W320FSB and M28W320FSU, A21 is NC.
10/76
M28WxxxFS, M28WxxxFSU
Description
Figure 6.
TFBGA47 connections (top view through package)
1
2
3
4
5
6
7
8
V
A19
A17
A
B
C
D
E
F
A13
A14
A15
A16
A11
A10
A8
W
V
A7
A5
A4
A2
A1
A0
DDQ
PP
RP
A18
A20
DQ2
DQ3
A12
A9
A6
A3
DQ11
DQ12
DQ4
DQ14
DQ15
DQ7
DQ5
DQ6
DQ13
DQ8
DQ9
DQ10
E
V
DQ0
DQ1
V
DDQ
SSQ
V
V
SS
DD
G
AI13203
1. The two VDDQ balls (balls A5 and E1) must be connected to the power supply.
2. Only 32 Mbit devices are delivered in the TFBGA47 package.
11/76
Description
M28WxxxFS, M28WxxxFSU
Figure 7.
M28W320FST and M28W320FSB block addresses
M28W320FST
M28W320FSB
Top Boot Block Addresses
Bottom Boot Block Addresses
1FFFFF
1FF000
1FFFFF
4 KWords
32 KWords
32 KWords
1F8000
1F7FFF
Total of 8
4 KWord Blocks
1F0000
Total of 63
32 KWord Blocks
1F8FFF
4 KWords
1F8000
1F7FFF
32 KWords
1F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 63
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
32 KWords
008000
007FFF
000FFF
000000
4 KWords
000000
AI09931
1. Also see Appendix A, Table 22 and Table 23 for a full listing of the Block Addresses.
Figure 8.
M28W640FST and M28W640FSB block addresses
M28W640FST
Top Boot Block Addresses
M28W640FSB
Bottom Boot Block Addresses
3FFFFF
3FF000
3FFFFF
4 KWords
32 KWords
32 KWords
3F8000
3F7FFF
Total of 8
4 KWord Blocks
3F0000
Total of 127
32 KWord Blocks
3F8FFF
4 KWords
3F8000
3F7FFF
32 KWords
3F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 127
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
32 KWords
008000
007FFF
000FFF
000000
4 KWords
000000
AI09911
1. Also see Appendix A, Table 24 and Table 25 for a full listing of the Block Addresses.
12/76
M28WxxxFS, M28WxxxFSU
Description
Figure 9.
M28W320FSU and M28W640FSU block addresses
M28W320FSU
M28W640FSU
Block Addresses
Block Addresses
1FFFFFh
3FFFFFh
64 KWords
64 KWords
64 KWords
64 KWords
1F0000h
1EFFFFh
3F0000h
3EFFFFh
1E0000h
3E0000h
Total of 32
Total of 64
1 Mbit Uniform Blocks
1 Mbit Uniform Blocks
01FFFFh
01FFFFh
64 KWords
64 KWords
64 KWords
64 KWords
010000h
00FFFFh
010000h
00FFFFh
000000h
000000h
AI10661
1. Also see Appendix A, Table 26 and Table 27 for a full listing of the Block Addresses.
Figure 10. Protection Register memory map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
Protection Register Lock
1
0
80h
AI05520b
13/76
Signal descriptions
M28WxxxFS, M28WxxxFSU
2
Signal descriptions
See Figure 1, Figure 2, Figure 3, and Figure 4, Logic Diagrams in conjunction with Table 2:
Signal names, for a brief overview of the signals connected to this devices.
2.1
Address Inputs
The Address Inputs select the cells in the memory array to access during Bus Read
operations. Address Inputs range from A0 to A20 for the M28W320FS and M28W320FSU.
The M28W640FS and M28W640FSU have an additional A21 address line. During Bus
Write operations they control the commands sent to the Command Interface of the internal
state machine.
2.2
2.3
Data Input/Output (DQ0-DQ15)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
or inputs a command or the data to be programmed during a Write Bus operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance and the power consumption is reduced to the stand-by level.
2.4
2.5
Output Enable (G)
The Output Enable controls data outputs during the Bus Read operation of the memory.
Write Enable (W)
The Write Enable controls the Bus Write operation of the memory’s Command Interface.
The data and address inputs are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first.
2.6
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
minimized. After Reset all blocks are in the Locked state only if the volatile protection is
activated. When Reset is at V , the device is in normal operation. Exiting reset mode the
IH
device enters read array mode, but a negative transition of Chip Enable or a change of the
address is required to ensure valid data outputs.
14/76
M28WxxxFS, M28WxxxFSU
Signal descriptions
2.7
2.8
2.9
VDD Supply Voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (Read, Program and Erase).
VDDQ Supply Voltage
V
provides the power supply to the I/O pins and enables all Outputs to be powered
DDQ
independently from V . V
can be tied to V or can use a separate supply.
DD DDQ
DD
VPP Program Supply Voltage
V
is both a control input and a power supply pin. The two functions are selected by the
PP
voltage range applied to the pin. The Supply Voltage V and the Program Supply Voltage
DD
V
can be applied in any order.
PP
If V is kept in a low voltage range (0V to 3.6V), V is seen as a control input. In this case
PP
PP
a voltage lower than V
gives an absolute protection against program or erase, while
PPLK
V
> V
enables these functions (see Table 14: DC characteristics, for the relevant
PP
PP1
values). V is only sampled at the beginning of a program or erase; a change in its value
PP
after the operation has started does not have any effect on Program or Erase.
If V is set to V
, it acts as a power supply pin. In this condition V must be stable until
PP
PP
PPH
the Program/Erase algorithm is completed (see Table 16 and Table 17). A Quadruple Word
Program command will be ignored if V is not set to V while a Double Word Program
PP
PPH
can be performed even if V is set to V
.
PP
DD
2.10
VSS Ground
V
is the reference for all voltage measurements.
SS
2.11
VSSQ Ground
V
ground is the reference for the input/output circuitry driven by V
. V
must be
SSQ
SSQ
DDQ
connected to V
.
SS
Note:
Each device in a system should have V , V
and V decoupled with a 0.1µF capacitor
DD DDQ PP
close to the pin. See Figure 11: AC measurement load circuit. The PCB track widths should
be sufficient to carry the required V program and erase currents.
PP
15/76
Bus operations
M28WxxxFS, M28WxxxFSU
3
Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby, Automatic Standby and Reset. See Table 3: Bus operations,
for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
3.1
Read
Read Bus operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at V in order to perform a read operation. The Chip Enable input
IL
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Section 6: Command Interface). See Figure 12: Read ac waveforms, and Table 15: Read ac
characteristics, for details of when the output becomes valid.
Read mode is the default state of the device when exiting Reset or after power-up.
3.2
Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A write operation is initiated when Chip Enable and Write Enable are at V
IL
with Output Enable at V . Commands, Input Data and Addresses are latched on the rising
IH
edge of Write Enable or Chip Enable, whichever occurs first.
See Figure 13 and Figure 14, Write AC Waveforms, and Table 16 and Table 17, Write AC
Characteristics, for details of the timing requirements.
3.3
3.4
Output Disable
The data outputs are high impedance when the Output Enable is at V .
IH
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in stand-by when Chip Enable is at V and the device is in
IH
read mode. The power consumption is reduced to the stand-by level and the outputs are set
to high impedance, independently from the Output Enable or Write Enable inputs. If Chip
Enable switches to V during a program or erase operation, the device enters Standby
IH
mode when finished.
16/76
M28WxxxFS, M28WxxxFSU
Bus operations
3.5
Automatic Standby
Automatic Standby provides a low power consumption state during Read mode. Following a
read operation, the device enters Automatic Standby after 150ns of bus inactivity even if
Chip Enable is Low, V , and the supply current is reduced to I
. The data Inputs/Outputs
IL
DD1
will still output data if a bus Read operation is in progress.
3.6
Reset
During Reset mode when Output Enable is Low, V , the memory is deselected and the
IL
outputs are high impedance. The memory is in Reset mode when Reset is at V . The power
IL
consumption is reduced to the Standby level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to V during a Program or Erase, this
SS
operation is aborted and the memory content is no longer valid.
(1)
Table 3.
Bus operations
Operation
E
G
W
RP
VPP
DQ0-DQ15
Bus Read
Bus Write
Output Disable
Standby
VIL
VIL
VIL
VIH
X
VIL
VIH
VIH
X
VIH
VIL
VIH
X
VIH
VIH
VIH
VIH
VIL
Don't Care
VDD or VPPH
Don't Care
Don't Care
Don't Care
Data Output
Data Input
Hi-Z
Hi-Z
Reset
X
X
Hi-Z
1. X = VIL or VIH, VPPH = 12V ± 5%.
17/76
Hardware Protection
M28WxxxFS, M28WxxxFSU
4
Hardware Protection
All devices feature hardware protection. Refer to Section 2: Signal descriptions for a detailed
description of these signals.
All the memory blocks are protected from program or erase operations when V is lower or
PP
equal to V
.
PPLK
5
Security features
The M28W320FS, M28W640FS, M28W320FSU and M28W640FSU, are equipped with
Krypto Security features performing software protection. They allow any block to be
protected from program/erase or read operations:
■
Modify Protection including Volatile Block Lock/Unlock, Non-Volatile Block Modify
Protection, Non-Volatile Password Modify Protection and Irreversible Protection.
■
Read Protection.
The Krypto features (Modify Protection mode, Read Protection mode and Device
Authentication mechanism) are not described in this Datasheet. For further details
concerning these additional protection modes please contact ST Sales Offices.
The devices also feature a 64 bit Unique Device Identifier and a 128 bit user-programmable
OTP segment (see Figure 10: Protection Register memory map and Section 6.12:
Protection Register Program command).
18/76
M28WxxxFS, M28WxxxFSU
Command Interface
6
Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. An internal
Program/Erase Controller handles all timings and verifies the correct execution of the
Program and Erase commands. The Program/Erase Controller provides a Status Register
whose output may be read at any time, to monitor the progress of the operation, or the
Program/Erase states. See Table 4: Command codes, for a summary of the commands and
see Appendix D, Table 34: Write State Machine Current/Next, sheet 1 of 2., for a summary
of the Command Interface.
The Command Interface is reset to Read mode when power is first applied, when exiting
from Reset or whenever V is lower than V
. Command sequences must be followed
DD
LKO
exactly. Any invalid combination of commands will reset the device to Read mode. Refer to
Table 5: Commands, in conjunction with the text descriptions below.
6.1
6.2
Read Memory Array command
The Read command returns the memory to its Read mode. One Bus Write cycle is required
to issue the Read Memory Array command and return the memory to Read mode.
Subsequent read operations will read the addressed location and output the data. When a
device Reset occurs, the memory defaults to Read mode.
Read Status Register command
The Status Register indicates when a program or erase operation is complete and the
success or failure of the operation itself. Issue a Read Status Register command to read the
Status Register’s contents. Subsequent Bus Read operations read the Status Register at
any address, until another command is issued. See Table 9: Status Register bits, for details
on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a
Program/Erase operation. Any Read attempt during a Program/Erase operation will
automatically output the content of the Status Register.
6.3
Read Electronic Signature command
The Read Electronic Signature command reads the Manufacturer and Device Codes, and
the Protection Register.
The Read Electronic Signature command consists of one write cycle, a subsequent read will
output the Manufacturer Code, the Device Code and the Protection Register. See Table 6,
and Table 7 for the valid address.
19/76
Command Interface
Table 4.
M28WxxxFS, M28WxxxFSU
Command codes
Hex Code
10h or 40h
Command
Program
20h
30h
50h
56h
70h
90h
98h
B0h
C0h
D0h
FFh
Erase
Double Word Program
Clear Status Register
Quadruple Word Program
Read Status Register
Read Electronic Signature
Read CFI Query
Program/Erase Suspend
Protection Register Program
Program/Erase Resume
Read Memory Array
6.4
Read CFI Query command
The Read Query Command is used to read data from the Common Flash Interface (CFI)
Memory Area, allowing programming equipment or applications to automatically match their
interface to the characteristics of the device. One Bus Write cycle is required to issue the
Read Query Command. Once the command is issued subsequent Bus Read operations
read from the Common Flash Interface Memory Area. See Appendix B: Common Flash
Interface (CFI), Table 28, Table 29, Table 30, Table 31, Table 32 and Table 33 for details on
the information contained in the Common Flash Interface memory area.
20/76
M28WxxxFS, M28WxxxFSU
Command Interface
6.5
Block Erase command
The Block Erase command can be used to erase a block. It sets all the bits within the
selected block to ’1’. All previous data in the block is lost. If the block is protected then the
Erase operation will abort, the data in the block will not be changed and the Status Register
will output the error.
Two Bus Write cycles are required to issue the command:
■
■
The first bus cycle sets up the Erase command.
The second latches the block address in the internal state machine and starts the
Program/Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are
set and the command aborts.
Erase aborts if Reset turns to V . As data integrity cannot be guaranteed when the Erase
IL
operation is aborted, the block must be erased again.
During Erase operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command, all other commands will be ignored. Typical Erase
times are given in Table 8: Program/Erase times and endurance cycles.
See Appendix C, Figure 22: Erase flowchart and pseudo code, for a suggested flowchart for
using the Erase command.
6.6
Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to
issue the Program Command:
■
■
The first bus cycle sets up the Program command.
The second latches the Address and the Data to be written and starts the
Program/Erase Controller.
During Program operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command. Typical Program times are given in Table 8:
Program/Erase times and endurance cycles.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Table 18: Program flowchart and pseudo code, for the flowchart for using
the Program command.
21/76
Command Interface
M28WxxxFS, M28WxxxFSU
6.7
Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two
adjacent words in parallel.The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command:
■
■
■
The first bus cycle sets up the Double Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 19: Double Word Program flowchart and pseudo code for the
flowchart for using the Double Word Program command.
6.8
Quadruple Word Program command
This feature is offered to improve the programming throughput, writing a page of four
adjacent words in parallel.The four words must differ only for the addresses A0 and A1.
A Quadruple word Program command will be ignored if V is not set to V
.
PP
PPH
Five bus write cycles are necessary to issue the Quadruple Word Program command:
■
■
■
■
■
The first bus cycle sets up the Quadruple Word Program Command.
The second bus cycle latches the Address and the Data of the first word to be written.
The third bus cycle latches the Address and the Data of the second word to be written.
The fourth bus cycle latches the Address and the Data of the third word to be written.
The fifth bus cycle latches the Address and the Data of the fourth word to be written
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to V . As data integrity cannot be guaranteed when the
IL
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 20: Quadruple Word Program flowchart and pseudo code, for the
flowchart for using the Quadruple Word Program command.
6.9
Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or
Erase command is issued. The error bits in the Status Register should be cleared before
attempting a new Program or Erase command.
22/76
M28WxxxFS, M28WxxxFSU
Command Interface
6.10
Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a Program or Erase operation.
One bus write cycle is required to issue the Program/Erase command and pause the
Program/Erase controller.
During Program/Erase Suspend the Command Interface will accept the Program/Erase
Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI
Query commands. Additionally, if the suspend operation was Erase then the Program,
Double Word Program, Quadruple Word Program or Block Lock commands will also be
accepted. The block being erased may be protected by issuing the Block Protect or Block
Lock commands. When the Program/Erase Resume command is issued the operation will
complete. Only the blocks not being erased may be read or programmed correctly.
During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by
taking Chip Enable to V . Program/Erase is aborted if Reset turns to V .
IH
IL
See Appendix C, Figure 21: Program Suspend & Resume flowchart and pseudo code, and
Figure 23: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Suspend command.
6.11
6.12
Program/Erase Resume command
The Program/Erase Resume command can be used to restart the Program/Erase Controller
after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to
issue the command. Once the command is issued subsequent Bus Read operations read
the Status Register.
See Appendix C, Figure 21: Program Suspend & Resume flowchart and pseudo code, and
Figure 23: Erase Suspend & Resume flowchart and pseudo code, for flowcharts for using
the Program/Erase Resume command.
Protection Register Program command
The Protection Register Program command is used to Program the 128 bit user One-Time-
Programmable (OTP) segment of the Protection Register. The segment is programmed 16
bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program
the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■
■
The first bus cycle sets up the Protection Register Program command.
The second latches the Address and the Data to be written to the Protection Register
and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see
Figure 10: Protection Register memory map). Attempting to program a previously protected
Protection Register will result in a Status Register error. The protection of the Protection
Register is not reversible.
The Protection Register Program cannot be suspended.
23/76
Command Interface
M28WxxxFS, M28WxxxFSU
Table 5.
Commands
Bus Write Operations(1)
3rd Cycle
Commands
1st Cycle
2nd Cycle
4th Cycle
5th Cycle
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
Read Memory
Array
1+ Write
1+ Write
1+ Write
X
X
X
FFh Read RA RD
70h Read SRD
Read Status
Register
X
Read Electronic
Signature
90h Read SA(2) IDh
Read CFI
Query
1+ Write
2 Write
2 Write
X
X
X
98h Read QA QD
20h Write BA D0h
Erase
40h or
Program
Write PA PD
10h
Double Word
Program(3)
3 Write
5 Write
X
X
30h Write PA1 PD1 Write PA2 PD2
Quadruple
Word
56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
Program(4)
Clear Status
Register
1 Write
1 Write
1 Write
X
X
X
50h
B0h
D0h
Program/Erase
Suspend
Program/Erase
Resume
Protection
Register
Program
2 Write
X
C0h Write PRA PRD
1. X = Don't Care, RA = Read Address, RD = Read Data, SRD = Status Register Data, ID = Identifier (Manufacture and Device
Code), QA = Query Address, QD = Query Data, BA = Block Address, PA = Program Address, PD = Program Data, PRA =
Protection Register Address, PRD = Protection Register Data.
2. The signature addresses are listed in Table 6 and Table 7.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
24/76
M28WxxxFS, M28WxxxFSU
Command Interface
DQ0-DQ7 DQ8-DQ15
Table 6.
Code(1)
Read Electronic Signature
A8-A20
A8-A21(2)
Device
E
G
W
A0
A1 A2-A7
Manufacture
Code
All
VIL
VIL
VIH
VIL
VIL
0
Don't Care
20h
00h
Device Code M28W320FST VIL
M28W320FSB VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH VIH
VIH VIH
VIH VIH
VIH VIH
VIH VIH
VIH VIH
VIL
VIL
VIL
VIL
VIL
VIL
0
0
0
0
0
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
0Ah
0Bh
58h
59h
0Ch
57h
88h
88h
88h
88h
88h
88h
M28W640FST VIL
Device Code M28W640FSB VIL
M28W320FSU VIL
M28W640FSU VIL
1. RP = VIH
.
2. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and the
M28W640FSU.
Table 7.
Word
Read Protection Register and Protection Register Lock
E
G
W
A0-A7 A8-A21(1)
DQ0
DQ1
DQ2
DQ3-DQ7 DQ8-DQ15
OTP Prot.
data
Lock
VIL VIL VIH
80h
Don't Care
0
0
00h
00h
Unique ID 0 VIL VIL VIH
Unique ID 1 VIL VIL VIH
Unique ID 2 VIL VIL VIH
Unique ID 3 VIL VIL VIH
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
Don't Care ID data
Don't Care ID data
Don't Care ID data
Don't Care ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
OTP 0
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
VIL VIL VIH
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
Don't Care OTP data OTP data OTP data OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
1. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and
the M28W640FSU.
25/76
Command Interface
M28WxxxFS, M28WxxxFSU
Table 8.
Program/Erase times and endurance cycles
Value
Unit
Parameter
Test Conditions
Min
Typ Max
Word Program
VPP = VDD
VPP = VPPH or VPP = VDD
VPP = VPPH
10
10
10
200
200
200
µs
µs
µs
Double Word Program
Quadruple Word Program
Using Word
Program command
VPP = VDD
0.32
0.16
s
s
Using Double Word
Program command
Main Block
Program
VPP = VPPH or VPP =VDD
5
4
5
Using Quadruple
Word Program
command
VPP = VPPH
0.08
s
Block Program
(M28W320FS,
M28W640FS)
Using Word
Program command
VPP = VDD
VPP = VPPH or VPP =VDD
0.04
0.02
s
s
Using Double Word
Program command
Parameter
Block Program
Using Quadruple
Word Program
command
VPP = VPPH
0.01
Using Word
Program command
VPP = VDD
0.64
0.32
s
s
Using Double Word
Program command
Block Program
VPP = VPPH or VPP = VDD
(M28W320FSU, M28W640FSU)
Using Quadruple
Word Program
command
VPP = VPPH
0.16
s
VPP = VDD
VPP = VPPH
VPP = VPPH
VPP = VDD
1
10
10
10
10
s
s
s
s
Main Block
Erase
Block Erase
1
(M28W320FS,
M28W640FS)
0.4
0.4
Parameter
Block Erase
Block Erase (M28W320FSU,
M28W640FSU)
VPP =VPPH or VPP = VDD
1
10
s
Program/Erase Cycles (per Block)
Data Retention
100,000
20
cycles
years
26/76
M28WxxxFS, M28WxxxFSU
Status Register
7
Status Register
The Status Register provides information on the current or previous Program or Erase
operation. The various bits convey information and errors on the operation. To read the
Status register the Read Status Register command can be issued, refer to Read Status
Register Command section. To output the contents, the Status Register is latched on the
falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable
or Output Enable returns to V . Either Chip Enable or Output Enable must be toggled to
IH
update the latched data.
Bus Read operations from any address always read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the following text descriptions.
7.1
Program/Erase Controller Status (Bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive. When the Program/Erase Controller Status bit is Low (set to ‘0’), the
Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase
Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, V Status and Block Lock Status bits should be tested for errors.
PP
7.2
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended. When the Erase Suspend Status bit is High (set to ‘1’), a
Program/Erase Suspend command has been issued and the memory is waiting for a
Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µs of
the Program/Erase Suspend command being issued therefore the memory may still
complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.
27/76
Status Register
M28WxxxFS, M28WxxxFSU
7.3
7.4
7.5
Erase Status (Bit 5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block
has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase
Controller has applied the maximum number of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Status bit should be read once the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive).
Once set High, the Erase Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
Program Status (Bit 4)
The Program Status bit is used to identify a Program failure. When the Program Status bit is
High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses
to the byte and still failed to verify that it has programmed correctly. The Program Status bit
should be read once the Program/Erase Controller Status bit is High (Program/Erase
Controller inactive).
Once set High, the Program Status bit can only be reset Low by a Clear Status Register
command or a hardware reset. If set High it should be reset before a new command is
issued, otherwise the new command will appear to fail.
VPP Status (Bit 3)
The V Status bit can be used to identify an invalid voltage on the V pin during Program
PP
PP
and Erase operations. The V pin is only sampled at the beginning of a Program or Erase
PP
operation. Indeterminate results can occur if V becomes invalid during an operation.
PP
When the V Status bit is Low (set to ‘0’), the voltage on the V pin was sampled at a valid
PP
PP
voltage; when the V Status bit is High (set to ‘1’), the V pin has a voltage that is below
PP
PP
the V Lockout Voltage, V
, the memory is protected and Program and Erase
PP
PPLK
operations cannot be performed.
Once set High, the V Status bit can only be reset Low by a Clear Status Register
PP
command or a hardware reset. If set High it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
7.6
Program Suspend Status (Bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended.
When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend
command has been issued and the memory is waiting for a Program/Erase Resume
command. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Bit 2 is set
within 5µs of the Program/Erase Suspend command being issued therefore the memory
may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns Low.
28/76
M28WxxxFS, M28WxxxFSU
Status Register
7.7
Block Protection Status (Bit 1)
The Block Protection Status bit can be used to identify if a Program or Erase operation has
tried to modify the contents of a locked block.
When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has
been attempted on a locked block.
Once set High, the Block Protection Status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set High it should be reset before a new
command is issued, otherwise the new command will appear to fail.
7.8
Reserved (Bit 0)
Bit 0 of the Status Register is reserved. Its value must be masked.
Note: Refer to Appendix C: Flowcharts and pseudo codes, for using the Status Register.
Table 9.
Bit
Status Register bits
Name
Logic Level (1)
Definition
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Ready
7
6
5
4
3
2
P/E.C. Status
Busy
Suspended
Erase Suspend Status
Erase Status
In progress or Completed
Erase Error
Erase Success
Program Error
Program Status
Program Success
VPP Invalid, Abort
VPP Status
VPP OK
Suspended
Program Suspend Status
In Progress or Completed
Program/Erase on protected Block, Abort
No operation to protected blocks
1
0
Block Protection Status
Reserved
1. Logic level '1' is High, '0' is Low.
29/76
Maximum rating
M28WxxxFS, M28WxxxFSU
8
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 10. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TA
Ambient Operating Temperature(1)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
– 40
– 40
– 55
– 0.6
– 0.6
– 0.6
85
125
°C
°C
°C
V
TBIAS
TSTG
155
(2)(3)
VIO
VDDQ+0.6
4.1
V
DD, VDDQ
V
VPP
Program Voltage
13
V
1. Depends on range.
2. The minimum Input/Output voltage may undershoot to – 2 V for less than 20 ns during transitions.
3. The maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions.
30/76
M28WxxxFS, M28WxxxFSU
DC and ac parameters
9
DC and ac parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 11: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 11. Operating and ac measurement conditions
Value
Parameter
Unit
Min
Max
VDD Supply Voltage
2.7
2.7
–40
3.6
3.6
85
V
V
VDDQ Supply Voltage (VDDQ ≤VDD
Ambient Operating Temperature
Load Capacitance (CL)
)
°C
pF
ns
V
50
Input Rise and Fall Times
Input Pulse Voltages
5
0 to VDDQ
VDDQ/2
Input and Output Timing Ref. Voltages
V
Table 12. AC measurement I/O waveform
V
DDQ
V
/2
DDQ
0V
AI00610
31/76
DC and ac parameters
M28WxxxFS, M28WxxxFSU
Figure 11. AC measurement load circuit
V
DDQ
V
DDQ
V
DD
25kΩ
DEVICE
UNDER
TEST
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI00609C
L
Table 13. Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test condition
Min
Max(1)
Unit
CIN
VIN = 0 V
6
pF
pF
COUT
VOUT = 0 V
12
1. Sampled only, not 100% tested.
32/76
M28WxxxFS, M28WxxxFSU
DC and ac parameters
Table 14. DC characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
ILI
Input Leakage Current
Output Leakage Current
0V ≤VIN ≤VDDQ
0V ≤VOUT ≤VDDQ
±1
µA
µA
ILO
±10
E = VSS, G = VIH,
f = 5 MHz
IDD
Supply Current (Read)
9
18
mA
Supply Current (Standby or
Automatic Stand-by)
E = VDDQ ± 0.2 V,
RP = VDDQ ± 0.2 V
IDD1
IDD2
15
15
5
50
50
10
µA
µA
Supply Current (Reset)
RP = VSS ± 0.2 V
Program in progress,
VPP = 12 V ± 5%
mA
IDD3
Supply Current (Program)
Program in progress, VPP = VDD
Erase in progress, VPP = 12 V ± 5%
Erase in progress, VPP = VDD
10
5
20
20
20
mA
mA
mA
IDD4
Supply Current (Erase)
10
Supply Current
(Program/Erase Suspend)
E = VDDQ ± 0.2 V,
Erase suspended
IDD5
IPP
IPP1
IPP2
15
50
µA
µA
Program Current (Read or
Standby)
VPP > VDD
400
Program Current (Read or
Standby)
VPP ≤VDD
1
1
1
1
3
5
5
µA
µA
Program Current (Reset)
RP = VSS ± 0.2 V
Program in progress,
VPP = 12 V ± 5%
10
5
mA
µA
IPP3
Program Current (Program)
Program in progress, VPP = VDD
Erase in progress
VPP = 12 V ± 5%
10
mA
IPP4
Program Current (Erase)
Erase in progress
VPP = VDD
1
5
µA
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
0.7VDDQ
VDDQ +0.4
IOL = 100 µA, VDD = VDDmin,
VDDQ = VDDQmin
VOL
VOH
Output Low Voltage
Output High Voltage
0.1
V
V
V
V
V
V
IOH = –100 µA, VDD = VDDmin,
VDDQ = VDDQmin
V
DDQ –0.1
Program Voltage (Program or
Erase operations)
VPP1
VPPH
VPPLK
VLKO
2.7
3.6
12.6
1
Program Voltage (Program or
Erase operations)
11.4
Program Voltage (Program
and Erase lock-out)
VDD Supply Voltage (Program
and Erase lock-out)
2
33/76
DC and ac parameters
M28WxxxFS, M28WxxxFSU
Figure 12. Read ac waveforms
tAVAV
VALID
(1)
A0-A20/A21
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQV
tGHQX
tGHQZ
tGLQX
VALID
DQ0-DQ15
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI09928
1. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and
M28W640FSU.
Table 15. Read ac characteristics
Symbol
Alt
Parameter
Value
Unit
tAVAV
tAVQV
tRC Address Valid to Next Address Valid
tACC Address Valid to Output Valid
Min
Max
Min
Min
Max
Max
Min
Min
Max
Max
Min
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAXQX
tOH Address Transition to Output Transition
tOH Chip Enable High to Output Transition
tHZ Chip Enable High to Output Hi-Z
tCE Chip Enable Low to Output Valid
tLZ Chip Enable Low to Output Transition
tOH Output Enable High to Output Transition
tDF Output Enable High to Output Hi-Z
tOE Output Enable Low to Output Valid
tOLZ Output Enable Low to Output Transition
(1)
tEHQX
0
(1)
tEHQZ
20
70
0
(2)
tELQV
(1)
tELQX
(1)
tGHQX
0
(1)
tGHQZ
20
20
0
(2)
tGLQV
(1)
tGLQX
1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV
.
34/76
M28WxxxFS, M28WxxxFSU
DC and ac parameters
Figure 13. Write ac waveforms, Write Enable controlled
1. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the
M29W640FS and M28W640FSU.
35/76
DC and ac parameters
M28WxxxFS, M28WxxxFSU
Table 16. Write ac characteristics, Write Enable controlled
Symbol
Alt
Parameter
Value
Unit
tAVAV
tAVWH
tDVWH
tELWL
tELQV
tWC Write cycle time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS Address Valid to Write Enable High
tDS Data Valid to Write Enable High
tCS Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
70
0
(1)(2)
tQVVPL
Output Valid to VPP Low
(1)
tVPHWH
tVPS VPP High to Write Enable High
tAH Write Enable High to Address Transition
tDH Write Enable High to Data Transition
tCH Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
tWPH Write Enable High to Write Enable Low
tWP Write Enable Low to Write Enable High
200
0
tWHAX
tWHDX
tWHEH
tWHEL
tWHGL
tWHWL
tWLWH
0
0
25
20
25
45
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
36/76
M28WxxxFS, M28WxxxFSU
DC and ac parameters
Figure 14. Write ac waveforms, Chip Enable controlled
Note:1.Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the
M29W640FS and M28W640FSU.
37/76
DC and ac parameters
M28WxxxFS, M28WxxxFSU
Table 17. Write ac characteristics, Chip Enable controlled
Symbol
Alt
Parameter
Value
Unit
tAVAV
tAVEH
tDVEH
tEHAX
tEHDX
tEHEL
tEHGL
tEHWH
tELEH
tELQV
tWC Write cycle time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
70
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS Address Valid to Chip Enable High
tDS Data Valid to Chip Enable High
tAH Chip Enable High to Address Transition
tDH Chip Enable High to Data Transition
tCPH Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
tWH Chip Enable High to Write Enable High
tCP Chip Enable Low to Chip Enable High
Chip Enable Low to Output Valid
0
25
25
0
45
70
0
(1)(2)
tQVVPL
Output Valid to VPP Low
(1)
tVPHEH
tWLEL
tVPS VPP High to Chip Enable High
tCS Write Enable Low to Chip Enable Low
200
0
1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
38/76
M28WxxxFS, M28WxxxFSU
DC and ac parameters
Figure 15. Power-Up and Reset ac waveforms
W, E, G
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
Reset
VDD, VDDQ
Power-Up
AI03537b
Table 18. Power-Up and Reset ac characteristics
Symbol
Parameter
Test condition
Value
Unit
During Program
tPHWL
tPHEL
tPHGL
Min
Min
50
µs
Reset High to Write Enable Low, Chip Enable Low,
Output Enable Low
and Erase
others
30
100
50
ns
ns
µs
(1)(2)
tPLPH
Reset Low to Reset High
Min
Min
(3)
tVDHPH
Supply Voltages High to Reset High
1. The device Reset is possible but not guaranteed if tPLPH < 100ns.
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
39/76
Package mechanical
M28WxxxFS, M28WxxxFSU
10
Package mechanical
Figure 16. TBGA64 - 10 × 13 active ball array, 1 mm pitch, bottom view package
outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 19. TBGA64 - 10 × 13 active ball array, 1 mm pitch, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.350
0.0472
0.0138
0.300
0.800
0.200
0.0118
0.0315
0.0079
0.350
9.900
–
0.500
0.0138
0.3898
–
0.0197
D
10.000
7.000
10.100
0.3937
0.2756
0.3976
D1
ddd
e
–
–
0.100
0.0039
1.000
13.000
7.000
1.500
3.000
0.500
0.500
–
–
0.0394
0.5118
0.2756
0.0591
0.1181
0.0197
0.0197
–
–
E
12.900
13.100
0.5079
0.5157
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40/76
M28WxxxFS, M28WxxxFSU
Package mechanical
Figure 17. TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, view through package
D
D1
FD
FE
SD
SE
E
E1
e
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z35
1. Drawing is not to scale.
Table 20. TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, package mechanical
data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
1.000
0.0394
0.400
6.390
5.250
0.350
6.290
–
0.450
0.0157
0.2516
0.2067
0.0138
0.2476
–
0.0177
D
6.490
0.2555
D1
ddd
E
–
–
0.100
0.0039
6.370
3.750
0.750
0.570
1.310
0.375
0.375
6.270
6.470
0.2508
0.1476
0.0295
0.0224
0.0516
0.0148
0.0148
0.2469
0.2547
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
41/76
Part numbering
M28WxxxFS, M28WxxxFSU
11
Part numbering
Table 21. Ordering information scheme
Example:
M28W320F S T 70 ZA 6 F
Device type
M28
Operating voltage
W = VDD = 2.7 V to 3.6 V; VDDQ = 2.7 V to 3.6 V
Density
320F = 32 Mbit (2 Mb x16)
640F = 64 Mbit (4 Mb x16)
Security
S = Krypto™ Flash
Memory block organization
T = Top boot
B = Bottom boot
U = Uniform
Speed
70 = 70ns
Package
ZA = TBGA64:10 × 13 mm, 1 mm pitch
ZB = TFBGA47, 6.39 × 6.37 mm, 0.75 mm pitch(1)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel Packing
1. Available with 32 Mbit devices only.
Note:
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the ST Sales Office nearest to you.
42/76
M28WxxxFS, M28WxxxFSU
Block address tables
Appendix A
Block address tables
Table 22. Top Boot Block addresses, M28W320FST
#
Size (KWord)
Address Range
0
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
43/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 22. Top Boot Block addresses, M28W320FST (continued)
#
Size (KWord)
Address Range
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F00000-F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
44/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 23. Bottom Boot Block addresses, M28W320FSB
#
Size (KWord)
Address Range
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
45/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 23. Bottom Boot Block addresses, M28W320FSB (continued)
#
Size (KWord)
Address Range
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
46/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 24. Top Boot Block Addresses, M28W640FST
#
Size (KWord)
Address Range
0
4
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
47/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 24. Top Boot Block Addresses, M28W640FST (continued)
#
Size (KWord)
Address Range
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
48/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 24. Top Boot Block Addresses, M28W640FST (continued)
#
Size (KWord)
Address Range
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
49/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 24. Top Boot Block Addresses, M28W640FST (continued)
#
Size (KWord)
Address Range
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
50/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 25. Bottom Boot Block addresses, M28W640FSB
#
Size (KWord)
Address Range
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
51/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 25. Bottom Boot Block addresses, M28W640FSB (continued)
#
Size (KWord)
Address Range
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
52/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 25. Bottom Boot Block addresses, M28W640FSB (continued)
#
Size (KWord)
Address Range
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
53/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 25. Bottom Boot Block addresses, M28W640FSB (continued)
#
Size (KWord)
Address Range
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
54/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 26. Block addresses, M28W320FSU
Block Number
Address Range
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
8
7
6
5
4
3
2
1
0
55/76
Block address tables
M28WxxxFS, M28WxxxFSU
Table 27. Block addresses, M28W640FSU
Block Number
Address Range
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3F0000h-3FFFFFh
3E0000h-3EFFFFh
3D0000h-3DFFFFh
3C0000h-3CFFFFh
3B0000h-3BFFFFh
3A0000h-3AFFFFh
390000h-39FFFFh
380000h-38FFFFh
370000h-37FFFFh
360000h-36FFFFh
350000h-35FFFFh
340000h-34FFFFh
330000h-33FFFFh
320000h-32FFFFh
310000h-31FFFFh
300000h-30FFFFh
2F0000h-2FFFFFh
2E0000h-2EFFFFh
2D0000h-2DFFFFh
2C0000h-2CFFFFh
2B0000h-2BFFFFh
2A0000h-2AFFFFh
290000h-29FFFFh
280000h-28FFFFh
270000h-27FFFFh
260000h-26FFFFh
250000h-25FFFFh
240000h-24FFFFh
230000h-23FFFFh
220000h-22FFFFh
210000h-21FFFFh
200000h-20FFFFh
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
56/76
M28WxxxFS, M28WxxxFSU
Block address tables
Table 27. Block addresses, M28W640FSU (continued)
Block Number
Address Range
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
8
7
6
5
4
3
2
1
0
57/76
Common Flash Interface (CFI)
M28WxxxFS, M28WxxxFSU
Appendix B
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the
data structure is read from the memory. Table 28, Table 29, Table 30, Table 31, Table 32 and
Table 33 show the addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Table 33: Security code area). This area can be accessed only in Read mode
by the final user. It is impossible to change the security number after it has been written by
ST. Issue a Read command to return to Read mode.
(1)
Table 28. Query structure overview
Offset
Sub-section Name
Reserved
Description
00h
10h
1Bh
27h
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
P
A
Alternate Algorithm-specific Extended Additional information specific to the Alternate
Query table Algorithm (optional)
1. Query data are always presented on the lowest order data outputs.
58/76
M28WxxxFS, M28WxxxFSU
Common Flash Interface (CFI)
(1)
Table 29. CFI query identification string
Offset
Data
Description
Value
00h
0020h Manufacturer Code
ST
8858h M28W640FST Device Code
880Ah M28W320FST Device Code
Top
8859h M28W640FSB Device Code
880Bh M28W320FSB Device Code
01h
Bottom
M28W320FSU Device Code
M28W640FSU Device Code
880Ch
8857h
Uniform
02h-0Fh reserved Reserved
10h
11h
12h
13h
14h
15h
16h
17h
0051h
"Q"
"R"
"Y"
0052h Query Unique ASCII String "QRY"
0059h
0003h
Primary Algorithm Command Set and Control Interface ID code
16 bit ID code defining a specific algorithm
Intel
compatible
0000h
0035h
0000h
Address for Primary Algorithm extended Query table (see
Table 31)
P = 35h
NA
0000h Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported (0000h means
0000h
18h
none exists)
19h
1Ah
0000h
0000h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
59/76
Common Flash Interface (CFI)
M28WxxxFS, M28WxxxFSU
Value
Table 30. CFI query system interface information
Offset
Data
Description
V
V
V
V
DD Logic Supply Minimum Program/Erase or Write voltage
1Bh
0027h
2.7V
3.6V
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100mV
DD Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100mV
1Ch
1Dh
1Eh
0036h
00B4h
00C6h
PP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV
11.4V
12.6V
PP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV
1Fh
20h
21h
22h
23h
0004h
0004h
000Ah
0000h
0005h
Typical time-out per single word program = 2n µs
Typical time-out for Double/Quadruple Word Program = 2n µs
Typical time-out per individual block erase = 2n ms
Typical time-out for full chip erase = 2n ms
16µs
16µs
1s
NA
Maximum time-out for Word program = 2n times typical
512µs
Maximum time-out for Double/Quadruple Word Program = 2n
times typical
24h
0005h
512µs
25h
26h
0003h
0000h
Maximum time-out per individual block erase = 2n times typical
Maximum time-out for chip erase = 2n times typical
8s
NA
60/76
M28WxxxFS, M28WxxxFSU
Common Flash Interface (CFI)
Table 31.
Device geometry definition
Offset Word Mode
Data
Description
Value
0016h
4 MByte
27h
Device Size = 2n in number of bytes
0017h
8 MByte
28h
29h
0001h
0000h
x16
Flash Device Interface Code description
Async.
2Ah
2Bh
0003h
0000h
Maximum number of bytes in multi-byte program or page
= 2n
8
1
Number of Erase Block Regions within the device.
0001h
0002h
It specifies the number of regions within the device
containing contiguous Erase Blocks of the same size.
2Ch
Number of Erase Block Regions within the device.
2
It specifies the number of regions within the device
containing contiguous Erase Blocks of the same size.
2Dh
2Eh
003Eh Region 1 Information
63
64 KByte
8
0000h Number of identical-size erase block = 003Eh+1
2Fh
30h
0000h Region 1 Information
0001h Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h Region 2 Information
0000h Number of identical-size erase block = 0007h+1
33h
34h
0020h Region 2 Information
8 KByte
8
0000h Block size in Region 2 = 0020h * 256 byte
2Dh
2Eh
0007h Region 1 Information
0000h Number of identical-size erase block = 0007h+1
2Fh
30h
0020h Region 1 Information
8 KByte
63
0000h Block size in Region 1 = 0020h * 256 byte
31h
32h
003Eh Region 2 Information
0000h Number of identical-size erase block = 003Eh+1
33h
34h
0000h Region 2 Information
64 KByte
0001h Block size in Region 2 = 0100h * 256 byte
61/76
Common Flash Interface (CFI)
M28WxxxFS, M28WxxxFSU
Table 31.
Device geometry definition
Offset Word Mode
Data
Description
Value
2Dh
2Eh
001Fh Region 1 Information
32
0000h Number of identical-size erase blocks = 001Fh+1
2Fh
30h
0000h Region 1 Information
128
KBytes
0002h Block size in Region 1 = 0200h * 256 byte
31h to
34h
Reserved
2Dh
2Eh
007Eh Region 1 Information
127
64 KByte
8
0000h Number of identical-size erase block = 007Eh+1
2Fh
30h
0000h Region 1 Information
0001h Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h Region 2 Information
0000h Number of identical-size erase block = 0007h+1
33h
34h
0020h Region 2 Information
8 KByte
8
0000h Block size in Region 2 = 0020h * 256 byte
2Dh
2Eh
0007h Region 1 Information
0000h Number of identical-size erase block = 0007h+1
2Fh
30h
0020h Region 1 Information
8 KByte
127
0000h Block size in Region 1 = 0020h * 256 byte
31h
32h
007Eh Region 2 Information
0000h Number of identical-size erase block = 007Eh+1
33h
34h
0000h Region 2 Information
64 KByte
64
0001h Block size in Region 2 = 0100h * 256 byte
2Dh
2Eh
003Fh Region 1 Information
0000h Number of identical-size erase blocks = 003Fh+1
2Fh
30h
0000h Region 1 Information
128
KBytes
0002h Block size in Region 1 = 0200h * 256 byte
31h to
34h
Reserved
62/76
M28WxxxFS, M28WxxxFSU
Common Flash Interface (CFI)
Table 32. Primary algorithm-specific extended query table
Offset
Data
Description
Value
P = 35h(1)
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
0050h
"P"
0052h Primary Algorithm extended Query table unique ASCII string “PRI”
0049h
"R"
"I"
0031h Major version number, ASCII
"1"
"0"
0030h Minor version number, ASCII
0066h Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
0000h
No
Yes
Yes
No
bit 0 Chip Erase supported (1 = Yes, 0 = No)
0000h
0000h
bit 1 Suspend Erase supported (1 = Yes, 0 = No)
bit 2 Suspend Program supported (1 = Yes, 0 = No)
bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)
bit 4 Queued Erase supported (1 = Yes, 0 = No)
bit 5 Instant individual block locking supported (1 = Yes, 0 = No)
bit 6 Protection bits supported (1 = Yes, 0 = No)
bit 7 Page mode read supported (1 = Yes, 0 = No)
bit 8 Synchronous read supported (1 = Yes, 0 = No)
bit 31 to 9 Reserved; undefined bits are ‘0’
No
Yes
Yes
No
(P+8)h = 3Dh
No
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
(P+9)h = 3Eh
(P+A)h = 3Fh
0001h
bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1 Reserved; undefined bits are ‘0’
Yes
0003h Block Lock Status
Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte
(P+B)h = 40h
(P+C)h = 41h
0000h
bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 =
No)
bit 15 to 1 Reserved for future use; undefined bits are ‘0’
Yes
Yes
VDD Logic Supply Optimum Program/Erase voltage (highest
performance)
0030h
3V
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV
VPP Supply Optimum Program/Erase voltage
(P+D)h = 42h
(P+E)h = 43h
00C0h
0001h
12V
01
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100mV
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
63/76
Common Flash Interface (CFI)
M28WxxxFS, M28WxxxFSU
Table 32. Primary algorithm-specific extended query table (continued)
Offset
Data
Description
Value
P = 35h(1)
(P+F)h = 44h
(P+10)h = 45h
0080h
0000h
80h
00h
Protection Field 1: Protection Description
8
(P+11)h = 46h
0003h
Bytes
This field describes user-available One Time Programmable (OTP)
Protection Register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection Register Lock byte, the section’s first byte.
8
0003h
The following bytes are factory pre-programmed and user-
programmable.
Bytes
bit 0 to 7 Lock/bytes JEDEC-plane physical low address
bit 8 to 15 Lock/bytes JEDEC-plane physical high address
bit 16 to 23 "n" such that 2n = factory pre-programmed bytes
bit 24 to 31 "n" such that 2n = user programmable bytes
(P+12)h
= 47h
16
Bytes
0004h
(P+13)h = 48h
Reserved
1. See Table 29, offset 15 for P pointer definition.
Table 33. Security code area
Offset
Data
Description
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Protection Register Lock
64 bits: unique device number
128 bits: User Programmable OTP
64/76
M28WxxxFS, M28WxxxFSU
Flowcharts and pseudo codes
Appendix C
Flowcharts and pseudo codes
Figure 18. Program flowchart and pseudo code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
Write 40h or 10h
/*or writeToFlash (any_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
NO
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
Program
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03538b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
65/76
Flowcharts and pseudo codes
M28WxxxFS, M28WxxxFSU
Figure 19. Double Word Program flowchart and pseudo code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03539b
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
66/76
M28WxxxFS, M28WxxxFSU
Flowcharts and pseudo codes
Figure 20. Quadruple Word Program flowchart and pseudo code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write 56h
Write Address 1
& Data 1 (3)
writeToFlash (any_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI06233
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
4. If an error is found, the Status Register must be cleared before further Program/Erase operations.
5. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
67/76
Flowcharts and pseudo codes
M28WxxxFS, M28WxxxFSU
Figure 21. Program Suspend & Resume flowchart and pseudo code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
b2 = 1
YES
Program Complete
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write FFh
Read Data
Write D0h
}
}
Program Continues
AI03540b
68/76
M28WxxxFS, M28WxxxFSU
Flowcharts and pseudo codes
Figure 22. Erase flowchart and pseudo code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
YES
NO
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
Error (1)
b3 = 0
YES
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
Command
Sequence Error (1)
b4, b5 = 1
NO
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
b5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03541b
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
69/76
Flowcharts and pseudo codes
M28WxxxFS, M28WxxxFSU
Figure 23. Erase Suspend & Resume flowchart and pseudo code
Start
erase_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
NO
} while (status_register.b7== 0) ;
b7 = 1
YES
if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
b6 = 1
YES
Erase Complete
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
Write D0h
Write FFh
Read Data
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Erase Continues
AI03542b
70/76
M28WxxxFS, M28WxxxFSU
Flowcharts and pseudo codes
Figure 24. Protection Register Program flowchart and pseudo code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;
Write C0h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI04381
1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation
or after a sequence.
6. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
71/76
Command Interface and Program/Erase Controller state
M28WxxxFS, M28WxxxFSU
Appendix D
Command Interface and Program/Erase
Controller state
(1)
Table 34. Write State Machine Current/Next, sheet 1 of 2.
Command Input (and Next State)
Data
When
Read
Current SR
Read Program Erase
Erase Prog/Ers Prog/Ers
Confirm Suspend Resume Status
Read
Clear
Status
(50h)
State
bit 7
Array
(FFh)
Setup
(10/40h)
Setup
(20h)
(D0h)
(B0h)
(D0h)
(70h)
Read
Array
Read
Array
Prog.
Setup
Read
Array
“1”
“1”
“1”
“1”
“1”
“0”
“1”
“1”
“0”
Array
Ers. Setup
Read Array
Read Sts.
Read
Status
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Status
Read Array
Read Array
Read Array
Read
Elect.Sg.
Electronic Read
Program
Setup
Erase
Setup
Read
Status
Read
Array
Signature
Array
Read CFI
Query
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
CFI
Prot. Prog.
Setup
Status
Status
Status
Status
Status
Protection Register Program
Prot. Prog.
(continue)
Protection Register Program continue
Prot. Prog.
(complete)
Read
Array
Program
Setup
Erase
Read
Status
Read
Array
Read Array
Setup
Prog.
Setup
Program
Program
(continue)
Prog. Sus
Read Sts
Program (continue)
Program (continue)
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Status
Program Suspend to Program
Program Prog. Sus
(continue) Read Sts
“1”
“1”
“1”
“1”
Status
Array
Read Array
(continue)
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Program Suspend to Program
Read Array (continue)
Program Prog. Sus
(continue) Read Sts
Prog. Sus
Read
Elect.Sg.
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Electronic
Signature
Program Suspend to Program
Read Array (continue)
Program Prog. Sus
(continue) Read Sts
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read
Array
Prog. Sus
Read CFI
Program Suspend to Program
Program Prog. Sus
(continue) Read Sts
CFI
Read Array
(continue)
Program
(complete)
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
“1”
“1”
“1”
Status
Status
Status
Read Array
Erase
Erase
Setup
Erase
Erase
Erase Command
Error
Erase Command Error
(continue) CmdError (continue)
Erase
Cmd.Error
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Read Array
72/76
M28WxxxFS, M28WxxxFSU
Command Interface and Program/Erase Controller state
(1)
Table 34. Write State Machine Current/Next, sheet 1 of 2. (continued)
Command Input (and Next State)
Data
When
Read
Current SR
Read Program Erase
Erase Prog/Ers Prog/Ers
Confirm Suspend Resume Status
Read
Clear
Status
(50h)
State
bit 7
Array
(FFh)
Setup
(10/40h)
Setup
(20h)
(D0h)
(B0h)
(D0h)
(70h)
Erase
SusRead
Sts
Erase
(continue)
“0”
“1”
“1”
“1”
Status
Status
Array
Erase (continue)
Erase (continue)
Erase Sus
Read
Erase Sus
Program
Read
Erase
SusRead
Array
Erase Sus
Read
Erase Sus
Read Sts
Erase
(continue)
Erase Erase Sus
(continue) Read Sts
Setup
Array
Array
Array
Erase Sus
Read
Array
Erase Sus
Read
Erase Sus
Program
Read
Erase
SusRead
Array
Erase Sus
Read
Erase
(continue)
Erase Erase Sus
(continue) Read Sts
Setup
Array
Array
Array
Erase Sus
Read
Elect.Sg.
Erase Sus
Read
Erase Sus
Program
Read
Erase
SusRead
Array
Erase Sus
Read
Electronic
Signature
Erase
(continue)
Erase Erase Sus
(continue) Read Sts
Setup
Array
Array
Array
Erase Sus
Read
Erase Sus
Program
Read
Erase
SusRead
Array
Erase Sus
Read
Erase Sus
Read CFI
Erase
(continue)
Erase Erase Sus
(continue) Read Sts
“1”
“1”
CFI
Setup
Array
Array
Array
Erase
(complete)
Read
Array
Program
Setup
Erase
Setup
Read
Status
Read
Array
Status
Read Array
1. Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
73/76
Command Interface and Program/Erase Controller state
M28WxxxFS, M28WxxxFSU
(1)
Table 35. Write State Machine Current/Next, sheet 2 of 2.
Command Input (and Next State)
Current State
Prot. Prog. Setup
Read Elect.Sg. (90h)
Read CFI Query (98h)
(C0h)
Read Array
Read Elect.Sg.
Read Elect.Sg.
Read Elect.Sg.
Read Elect.Sg.
Read CFI Query
Read CFI Query
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Read Status
Read Elect.Sg.
Read CFI Query
Read CFI Query
Prot. Prog. Setup
Prot. Prog. (continue)
Prot. Prog. (complete)
Prog. Setup
Read CFI Query
Protection Register Program
Protection Register Program (continue)
Read Elect.Sg.
Read CFI Query
Program
Prot. Prog. Setup
Program (continue)
Program (continue)
Prog. Suspend Read
Status
Prog. Suspend Read
Elect.Sg.
Prog. Suspend Read
CFI Query
Program Suspend
Read Array
Prog. Suspend Read
Array
Prog. Suspend Read
Elect.Sg.
Prog. Suspend Read
CFI Query
Program Suspend
Read Array
Prog. Suspend Read
Elect.Sg.
Prog. Suspend Read
Elect.Sg.
Prog. Suspend Read
CFI Query
Program Suspend
Read Array
Prog. Suspend Read
CFI
Prog. Suspend Read
Elect.Sg.
Prog. Suspend Read
CFI Query
Program Suspend
Read Array
Program (complete)
Erase Setup
Read Elect.Sg.
Read CFIQuery
Erase Command Error
Read CFI Query
Prot. Prog. Setup
Erase Cmd.Error
Erase (continue)
Read Elect.Sg.
Prot. Prog. Setup
Erase (continue)
Erase Suspend Read
Status
Erase Suspend Read
Elect.Sg.
Erase Suspend Read
CFI Query
Erase Suspend Read
Array
Erase Suspend Read
Array
Erase Suspend Read
Elect.Sg.
Erase Suspend Read
CFI Query
Erase Suspend Read
Array
Erase Suspend Read
Elect.Sg.
Erase Suspend Read
Elect.Sg.
Erase Suspend Read
CFI Query
Erase Suspend Read
Array
Erase Suspend Read
CFI Query
Erase Suspend Read
Elect.Sg.
Erase Suspend Read
CFI Query
Erase Suspend Read
Array
Erase (complete)
Read Elect.Sg.
Read CFI Query
Prot. Prog. Setup
1. Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
74/76
M28WxxxFS, M28WxxxFSU
Revision history
12
Revision history
Table 36. Document revision history
Date
Revision
Changes
Initial release. This datasheet is the merge of the M28WxxxFS
datasheet (revision 2.0) concerning the M28W320FS and
M28W640FS, and of the M28WxxxFSU datasheet (revision 1.0)
concerning the M28W320FSU and M28W640FSU.
25-Oct-2005
1.0
Small text changes.
VIH and VIL parameters corrected in Table 14: DC characteristics.
VSSQ added (see Table 2: Signal names and Section 2.11: VSSQ
Ground).
21-Sep-2006
2
TFBGA47 package added (see Section 10: Package mechanical).
Table 21: Ordering information scheme modified and Daisy Chain
ordering scheme removed.
Block protection state after Reset specified in Section 2.6: Reset (RP).
Command code 01h removed from Table 4: Command codes.
The Protection Register Program command is not accepted during
Program/Erase Suspend (see Section 6.10: Program/Erase Suspend
command).
15-Dec-2006
3
M28W640FSU added at address offset (P+12)h = 47h for data 004h in
Table 32: Primary algorithm-specific extended query table.
Small text changes.
75/76
M28WxxxFS, M28WxxxFSU
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