M29W320ET90N6E_技术文档

M29W320ET

M29W320EB

32 Mbit (4Mbx8 or 2Mbx16, Uniform Parameter Blocks, Boot Block)

3V supply Flash memory

Features

■ Supply voltage

– V = 2.7V to 3.6V for Program, Erase and

CC

Read

– V =12V for Fast Program (optional)

PP

■ Access times: 70, 90ns

■ Programming time

– 10µs per byte/word typical

– Double word/ Quadruple byte Program

TSOP48 (N)

12 x 20mm

■ Memory Blocks

– Memory Array: 63 Main Blocks

FBGA

– 8 Parameter Blocks (Top or Bottom

Location)

■ Erase Suspend and Resume modes

– Read and Program another Block during

Erase Suspend

TFBGA48 (ZE)

6 x 8mm

■ Unlock Bypass Program command

– Faster Production/Batch Programming

■ V /WP pin for fast Program and Write Protect

PP

■ Temporary Block Unprotection mode

■ Common Flash Interface

– 64 bit Security code

■ Extended memory Block

– Extra block used as security block or to

store additional information

■ Low power consumption

– Standby and Automatic Standby

■ 100,000 Program/Erase cycles per block

■ Electronic signature

– Manufacturer code: 0020h

– Top Device code M29W320ET: 2256h

– Bottom Device code M29W320EB: 2257h

®

■ ECOPACK packages available

March 2008

Rev 6

1/63

www.numonyx.com

1

Contents

M29W320ET, M29W320EB

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address Inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 13

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V_PP/Write Protect (V_PP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.11 Byte/word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.12

2.13

V

_CCSupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

_SSGround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

V

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1

3.2

3.3

3.4

3.5

3.6

Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6.1

3.6.2

Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4

Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1

4.2

4.3

4.4

Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/63

M29W320ET, M29W320EB

Contents

4.5

Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5.1

4.5.2

Quadruple byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Double word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.6

4.7

4.8

4.9

Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.10 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.11 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.12 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.13 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.14 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.15 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 25

5

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1

5.2

5.3

5.4

5.5

Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6

7

8

9

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Appendix C Extended memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.1

9.2

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3/63

Contents

M29W320ET, M29W320EB

Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

D.1

D.2

Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4/63

M29W320ET, M29W320EB

List of tables

Table 1.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2.

Table 3.

Bus operations, BYTE = V

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 4.

Commands, 16-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

IH

Table 5.

Commands, 8-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

IL

Table 6.

Table 7.

Table 8.

Table 9.

Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 28

Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Write ac characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Toggle and alternative Toggle bits ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Reset/Block Temporary Unprotect ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, package mechanical data . . . . . . . 42

TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, package mechanical data. . . . . . . . . . . 43

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Top Boot Block Addresses, M29W320ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Bottom Boot Block Addresses, M29W320EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Primary Algorithm-specific extended Query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Extended Block Address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Programmer technique Bus operations, BYTE = V or V

IH

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

List of figures

M29W320ET, M29W320EB

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC measurement Load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. Read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 12. Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 13. Toggle and alternative Toggle bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . 40

Figure 14. Toggle and alternative Toggle bits mechanism, Output Enable controlled. . . . . . . . . . . . . 40

Figure 15. Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 16. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, top view package outline. . . . . . . . 42

Figure 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, bottom view package outline . . . . . . . . 43

Figure 19. Programmer Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 20. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 21. In-system Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 22. In-system Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6/63

M29W320ET, M29W320EB

Description

1

Description

The M29W320E is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read,

erased and reprogrammed. These operations can be performed using a single low voltage

(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.

The device features an asymmetrical block architecture. The M29W320E has an array of 8

parameter and 63 main blocks. M29W320ET locates the Parameter Blocks at the top of the

memory address space while the M29W320EB locates the Parameter Blocks starting from

the bottom.

M29W320E has an extra 32 Kword (x16 mode) or 64 Kbyte (x8 mode) block, the Extended

Block, that can be accessed using a dedicated command. The Extended Block can be

protected and so is useful for storing security information. However the protection is

irreversible, once protected the protection cannot be undone.

Each block can be erased independently so it is possible to preserve valid data while old

data is erased. The blocks can be protected to prevent accidental Program or Erase

commands from modifying the memory. Program and Erase commands are written to the

Command interface of the memory. An on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by taking care of all of the special

operations that are required to update the memory contents. The end of a program or erase

operation can be detected and any error conditions identified. The command set required to

control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the

memory. They allow simple connection to most microprocessors, often without additional

logic.

The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch)

packages. In order to meet environmental requirements, Numonyx offers the M29W320E in

®

ECOPACK packages. ECOPACK packages are Lead-free. The category of second Level

Interconnect is marked on the package and on the inner box label, in compliance with

JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label.

The memory is supplied with all the bits erased (set to ’1’).

7/63

Description

M29W320ET, M29W320EB

Figure 1.

Logic diagram

V

/WP

CC PP

21

15

A0-A20

DQ0-DQ14

W

E

DQ15A–1

BYTE

RB

M29W320ET

M29W320EB

G

RP

V

SS

AI09346

Table 1.

Signal names

Address Inputs

A0-A20

DQ0-DQ7

Data Inputs/Outputs

DQ8-DQ14

DQ15A–1

Data Input/Output or Address Input

Chip Enable

E

G

Output Enable

W

Write Enable

RP

RB

BYTE

V_CC

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/word Organization Select

Supply voltage

V_PP/WP

V_PP/Write Protect

V_SS

NC

Ground

Not Connected Internally

8/63

M29W320ET, M29W320EB

Figure 2. TSOP connections

Description

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

A20

W

M29W320ET

M29W320EB

DQ12

DQ4

RP

NC

/WP

RB

A18

A17

A7

12

13

37

36

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

PP

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI09347

9/63

Description

Figure 3.

M29W320ET, M29W320EB

TFBGA48 connections (top view through package)

1

2

3

4

5

6

RB

W

RP

NC

A

B

A3

A4

A7

A17

A6

A9

A8

A13

A12

V

/WP

PP

A2

A1

A0

E

A18

A10

A14

C

D

A5

A20

A19

A11

A15

DQ2

DQ5

DQ0

DQ8

DQ9

DQ1

DQ7

DQ14

DQ13

DQ6

A16

E

F

BYTE

DQ10

DQ11

DQ3

DQ12

DQ15

A–1

G

V

G

H

CC

V

DQ4

V

SS

AI08084

10/63

M29W320ET, M29W320EB

Figure 4. Block Addresses (x8)

Description

Top Boot Block (x8)

Bottom Boot Block (x8)

Address lines A20-A0, DQ15A-1

000000h

64 KByte or

32 KWord

8 KByte or

4 KWord

00FFFFh

001FFFh

Total of 8

Parameter

(1)

Blocks

2F0000h

00E000h

64 KByte or

32 KWord

8 KByte or

4 KWord

Total of 63

Main Blocks

2FFFFFh

300000h

00FFFFh

010000h

64 KByte or

32 KWord

64 KByte or

32 KWord

30FFFFh

01FFFFh

3E0000h

0F0000h

64 KByte or

32 KWord

64 KByte or

32 KWord

Total of 63

Main Blocks

3EFFFFh

3F0000h

0FFFFFh

100000h

8 KByte or

4 KWord

64 KByte or

32 KWord

3F1FFFh

10FFFFh

Total of 8

Parameter

(1)

Blocks

3FE000h

3FFFFFh

3F0000h

3FFFFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

Note 1. Used as Extended Block Addresses in Extended Block mode.

1. See also Appendix A: Block Addresses, Table 20 and Table 21 for a full listing of the Block Addresses.

AI09348

11/63

Description

Figure 5.

M29W320ET, M29W320EB

Block Addresses (x16)

Top Boot Block (x16)

Address lines A20-A0

Bottom Boot Block (x16)

Address lines A20-A0

000000h

000FFFh

64 KByte or

32 KWord

8 KByte or

4 KWord

007FFFh

Total of 8

Parameter

(1)

Blocks

178000h

007000h

64 KByte or

32 KWord

8 KByte or

4 KWord

17FFFFh

180000h

Total of 63

Main Blocks

007FFFh

008000h

64 KByte or

32 KWord

64 KByte or

32 KWord

187FFFh

00FFFFh

078000h

1F0000h

64 KByte or

32 KWord

64 KByte or

32 KWord

1F7FFFh

1F8000h

07FFFFh

080000h

Total of 63

Main Blocks

8 KByte or

4 KWord

64 KByte or

32 KWord

1F8FFFh

087FFFh

Total of 8

Parameter

(1)

Blocks

1FF000h

1F8000h

1FFFFFh

8 KByte or

4 KWord

64 KByte or

32 KWord

1FFFFFh

Note 1. Used as Extended Block Addresses in Extended Block mode.

AI09349

1. See also Appendix A: Block Addresses, Table 20 and Table 21 for a full listing of the Block Addresses.

12/63

M29W320ET, M29W320EB

Signal descriptions

2

Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

2.2

2.3

Address Inputs (A0-A20)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

interface of the Program/Erase Controller.

Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.

During Bus Write operations they represent the commands sent to the Command interface

of the Program/Erase Controller.

Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation

when BYTE is High, V . When BYTE is Low, V , these pins are not used and are high

IH

IL

impedance. During Bus Write operations the Command Register does not use these bits.

When reading the Status register these bits should be ignored.

2.4

Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, V , this pin behaves as a Data Input/Output pin (as DQ8-DQ14).

IH

When BYTE is Low, V , this pin behaves as an address pin; DQ15A–1 Low will select the

IL

LSB of the addressed word, DQ15A–1 High will select the MSB. Throughout the text

consider references to the Data Input/Output to include this pin when BYTE is High and

references to the Address Inputs to include this pin when BYTE is Low except when stated

explicitly otherwise.

2.5

2.6

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, V , all other pins are ignored.

IH

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

13/63

Signal descriptions

M29W320ET, M29W320EB

2.7

2.8

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command interface.

V_PP/Write Protect (V_PP/WP)

The V /Write Protect pin provides two functions. The V function allows the memory to

PP

use an external high voltage power supply to reduce the time required for Program

operations. This is achieved by bypassing the unlock cycles and/or using the Double word or

Quadruple byte Program commands.

The Write Protect function provides a hardware method of protecting the two outermost boot

blocks. When V /Write Protect is Low, V , the memory protects the two outermost boot

PP

IL

blocks; Program and Erase operations in these blocks are ignored while V /Write Protect is

PP

Low, even when RP is at V .

ID

When V /Write Protect is High, V , the memory reverts to the previous protection status

PP

IH

of the two outermost boot blocks. Program and Erase operations can now modify the data

in these blocks unless the blocks are protected using Block Protection.

When V /Write Protect is raised to V the memory automatically enters the Unlock

PP

Bypass mode. When V /Write Protect returns to V or V normal operation resumes.

PP

IH

IL

During Unlock Bypass Program operations the memory draws I from the pin to supply the

PP

programming circuits. See the description of the Unlock Bypass command in the Command

interface section. The transitions from V to V and from V to V must be slower than

IH

PP

IH

t

, see Figure 16

VHVPP

Never raise V /Write Protect to V from any mode except Read mode, otherwise the

PP

memory may be left in an indeterminate state.

The V /Write Protect pin must not be left floating or unconnected or the device may

PP

become unreliable. A 0.1µF capacitor should be connected between the V /Write Protect

PP

pin and the V Ground pin to decouple the current surges from the power supply. The PCB

SS

track widths must be sufficient to carry the currents required during Unlock Bypass Program,

I .

PP

2.9

Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

Note that if V /WP is at V , then the two outermost boot blocks will remain protected even

PP

IL

if RP is at V .

ID

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V , for at

IL

least t

. After Reset/Block Temporary Unprotect goes High, V , the memory will be

PLPX

IH

ready for Bus Read and Bus Write operations after t

or t

, whichever occurs last.

RHEL

PHEL

See the Ready/Busy Output section, Table 16 and Figure 15: Reset/Block Temporary

Unprotect ac waveforms, for more details.

Holding RP at V will temporarily unprotect the protected Blocks in the memory. Program

ID

and Erase operations on all blocks will be possible. The transition from V to V must be

IH

ID

slower than t

.

PHPHH

14/63

M29W320ET, M29W320EB

Signal descriptions

2.10

Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is

performing a Program or Erase operation. During Program or Erase operations Ready/Busy

is Low, V . Ready/Busy is high-impedance during Read mode, Auto Select mode and

OL

Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy

becomes high-impedance. See Table 16 and Figure 15: Reset/Block Temporary Unprotect

ac waveforms.

The use of an open-drain output allows the Ready/Busy pins from several memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.11

2.12

Byte/word Organization Select (BYTE)

The byte/word Organization Select pin is used to switch between the x8 and x16 Bus modes

of the memory. When byte/word Organization Select is Low, V , the memory is in x8 mode,

IL

when it is High, V , the memory is in x16 mode.

IH

V_CCSupply voltage

V

provides the power supply for all operations (Read, Program and Erase).

CC

The Command interface is disabled when the V Supply voltage is less than the Lockout

CC

voltage, V

. This prevents Bus Write operations from accidentally damaging the data

LKO

during power up, power down and power surges. If the Program/Erase Controller is

programming or erasing during this time then the operation aborts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the V Supply voltage pin and the V

CC

SS

Ground pin to decouple the current surges from the power supply. The PCB track widths

must be sufficient to carry the currents required during Program and Erase operations, I

.

CC3

2.13

V_SSGround

V

is the reference for all voltage measurements. The device features two V pins which

SS

must be both connected to the system ground.

15/63

Bus operations

M29W320ET, M29W320EB

3

Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby and Automatic Standby.

See Table 2 and Table 3, Bus operations, for a summary. Typically glitches of less than 5ns

on Chip Enable or Write Enable are ignored by the memory and do not affect bus

operations.

3.1

3.2

Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write

Enable High, V . The Data Inputs/Outputs will output the value, see Figure 10: Read mode

ac waveforms, and Table 12: Read ac characteristics, for details of when the output

IL

IH

becomes valid.

Bus Write

Bus Write operations write to the Command interface. A valid Bus Write operation begins by

setting the desired address on the Address Inputs. The Address Inputs are latched by the

Command interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latched by the Command interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V ,

IH

during the whole Bus Write operation. See Figure 11 and Figure 12, Write ac waveforms,

and Table 13 and Table 14, Write ac characteristics, for details of the timing requirements.

3.3

3.4

Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V .

IH

Standby

When Chip Enable is High, V , the memory enters Standby mode and the Data

IH

Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to

the Standby Supply current, I

, Chip Enable should be held within V

0.2V. For the

CC2

CC

Standby current level see Table 11: DC characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply current, I , for Program or Erase operations until the operation completes.

CC3

16/63

M29W320ET, M29W320EB

Bus operations

3.5

Automatic Standby

If CMOS levels (V

0.2V) are used to drive the bus and the bus is inactive for 300ns or

CC

more the memory enters Automatic Standby where the internal Supply current is reduced to

the Standby Supply current, I . The Data Inputs/Outputs will still output data if a Bus

CC2

Read operation is in progress.

3.6

Special bus operations

Additional bus operations can be performed to read the Electronic signature and also to

apply and remove Block Protection. These bus operations are intended for use by

programming equipment and are not usually used in applications. They require V to be

ID

applied to some pins.

3.6.1

3.6.2

Electronic signature

The memory has two codes, the manufacturer code and the device code, that can be read

to identify the memory. These codes can be read by applying the signals listed in Table 2

and Table 3, Bus operations.

Block Protect and Chip Unprotect

Groups of blocks can be protected against accidental Program or Erase. The Protection

groups are shown in Appendix A: Block Addresses, Table 20 and Table 21, Block

Addresses. The whole chip can be unprotected to allow the data inside the blocks to be

changed.

The V /Write Protect pin can be used to protect the two outermost boot blocks. When

PP

V

/Write Protect is at V the two outermost boot blocks are protected and remain

PP

IL

protected regardless of the Block Protection Status or the Reset/Block Temporary

Unprotect pin status.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

17/63

Bus operations

M29W320ET, M29W320EB

Data Inputs/Outputs

(1)

Table 2.

Bus operations, BYTE = V

IL

Address Inputs

DQ15A–1, A0-A20

Operation

E

G

W

DQ14-

DQ7-DQ0

DQ8

Bus Read

Bus Write

Output Disable

Standby

V_IL

X

V_IL

V_IH

X

V_IHCell Address

Hi-Z

Data Output

Data Input

Hi-Z

V_ILCommand Address

V_IH

X

V_IH

Hi-Z

Read Manufacturer

code

A0 = V_IL, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

V_IL

V_IH

Hi-Z

20h

56h (M29W320ET)

57h (M29W320EB)

A0 = V_IH, A1 = V_IL,

A9 = V_ID, Others V_ILor V_IH

Read Device code

81h (factory locked)

Extended memory

Block Verify code

A0 = V_IH, A1 = V_IH, A6 = V_IL,

A9 = V_ID, Others V_ILor V_IH

01h (factory unlocked)

1. X = V_ILor V_IH

.

18/63

M29W320ET, M29W320EB

Bus operations

(1)

Table 3.

Bus operations, BYTE = V

IH

Address Inputs

A0-A20

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

Bus Read

Bus Write

Output Disable

Standby

V_IL

X

V_IL

V_IH

X

V_IHCell Address

Data Output

Data Input

Hi-Z

V_ILCommand Address

V_IH

X

V_IH

Hi-Z

Read Manufacturer

code

A0 = V_IL, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

V_IL

V_IH

0020h

2256h (M29W320ET)

2257h (M29W320EB)

A0 = V_IH, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

Read Device code

81h (factory locked)

Extended memory

Block Verify code

A0 = V_IH, A1 = V_IH, A6 = V_IL,

A9 = V_ID, Others V_ILor V_IH

01h (factory unlocked)

1. X = V_ILor V_IH

.

19/63

Command interface

M29W320ET, M29W320EB

4

Command interface

All Bus Write operations to the memory are interpreted by the Command interface.

Commands consist of one or more sequential Bus Write operations. Failure to observe a

valid sequence of Bus Write operations will result in the memory returning to Read mode.

The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-

bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being

used, for a summary of the commands.

4.1

Read/Reset command

The Read/Reset command returns the memory to its Read mode. It also resets the errors in

the Status register. Either one or three Bus Write operations can be used to issue the

Read/Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a

program or erase operation, to return the device to read mode. If the Read/Reset command

is issued during the time-out of a Block erase operation then the memory will take up to

10µs to abort. During the abort period no valid data can be read from the memory. The

Read/Reset command will not abort an Erase operation when issued while in Erase

Suspend.

4.2

Auto Select command

The Auto Select command is used to read the Manufacturer code, the Device code, the

Block Protection Status and the Extended memory Block Verify code. Three consecutive

Bus Write operations are required to issue the Auto Select command. The memory remains

in Auto Select mode until a Read/Reset or CFI Query command is issued.

In Auto Select mode the Manufacturer code can be read using a Bus Read operation with

A0 = V and A1 = V . The other address bits may be set to either V or V .

IL

IH

The Device code can be read using a Bus Read operation with A0 = V and A1 = V . The

IH

IL

other address bits may be set to either V or V .

IL

IH

The Block Protection Status of each block can be read using a Bus Read operation with A0

= V , A1 = V and A12-A20 specifying the block address. The other address bits may be

IL

IH

set to either V or V . If the addressed block is protected then 01h is output on Data

IL

IH

Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

20/63

M29W320ET, M29W320EB

Command interface

4.3

Read CFI Query command

The Read CFI Query Command is used to read data from the Common Flash Interface

(CFI) memory Area. This command is valid when the device is in the Read Array mode, or

when the device is in Auto Select mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the

command is issued subsequent Bus Read operations read from the Common Flash

Interface memory Area.

The Read/Reset command must be issued to return the device to the previous mode (the

Read Array mode or Auto Select mode). A second Read/Reset command would be needed

if the device is to be put in the Read Array mode from Auto Select mode.

See Appendix B: Common Flash Interface (CFI), Table 22, Table 23, Table 24, Table 25,

Table 26 and Table 27 for details on the information contained in the Common Flash

Interface (CFI) memory area.

4.4

Program command

The Program command can be used to program a value to one address in the memory array

at a time. The command requires four Bus Write operations, the final write operation latches

the address and data, and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data

remains unchanged. The Status register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to

issue any command to abort or pause the operation. After programming has started, Bus

Read operations output the Status register content. See Section 5: Status register for more

details. Typical program times are given in Table 6

After the program operation has completed the memory will return to the Read mode, unless

an error has occurred. When an error occurs Bus Read operations will continue to output

the Status register. A Read/Reset command must be issued to reset the error condition and

return to Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

21/63

Command interface

M29W320ET, M29W320EB

4.5

Fast Program commands

There are two Fast Program commands available to improve the programming throughput,

by writing several adjacent words or bytes in parallel. The Quadruple byte Program

command is available for x8 operations, while the Double word Program command is

available for x16 operations.

Fast Program commands should not be attempted when V WP is not at V . Care must

PP/

PP

be taken because applying a 12V V voltage to the VPP/WP pin will temporarily unprotect

PP

any protected block.

After programming has started, Bus Read operations output the Status register content.

After the program operation has completed the memory will return to the Read mode, unless

an error has occurred. When an error occurs Bus Read operations will continue to output

the Status register. A Read/Reset command must be issued to reset the error condition and

return to Read mode.

Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the

Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’

to ’1’.

Typical Program times are given in Table 6: Program, Erase times and Program, Erase

Endurance cycles

4.5.1

Quadruple byte Program command

The Quadruple byte Program command is used to write a page of four adjacent bytes in

parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles

are necessary to issue the Quadruple byte Program command.

1. The first bus cycle sets up the Quadruple byte Program command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and

starts the Program/Erase Controller.

4.5.2

Double word Program command

The Double word Program command is used to write a page of two adjacent words in

parallel. The two words must differ only for the address A0.

Three bus write cycles are necessary to issue the Double word Program command.

1. The first bus cycle sets up the Double word Program command.

2. The second bus cycle latches the Address and the Data of the first word to be written.

3. The third bus cycle latches the Address and the Data of the second word to be written

and starts the Program/Erase Controller.

22/63

M29W320ET, M29W320EB

Command interface

4.6

Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory faster than with the standard program commands. When

the cycle time to the device is long, considerable time saving can be made by using these

commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory enters Unlock Bypass

mode. The Unlock Bypass Program command can then be issued to program addresses or

the Unlock Bypass Reset command can be issued to return to Read mode. In Unlock

Bypass mode the memory can be read as if in Read mode.

When V is applied to the V /Write Protect pin the memory automatically enters the

PP

Unlock Bypass mode and the Unlock Bypass Program command can be issued

immediately. Care must be taken because applying a 12V V voltage to the VPP/WP pin

PP

will temporarily unprotect any protected block.

4.7

Unlock Bypass Program command

The Unlock Bypass Program command can be used to program one address in the memory

array at a time. The command requires two Bus Write operations, the final write operation

latches the address and data, and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass Program command behaves identically to

the Program operation using the Program command. The operation cannot be aborted, a

Bus Read operation outputs the Status register. See the Program command for details on

the behavior.

4.8

4.9

Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from

Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass

Reset command. Read/Reset command does not exit from Unlock Bypass mode.

Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations

are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all

of the blocks are protected the Chip Erase operation appears to start but will terminate

within about 100µs, leaving the data unchanged. No error condition is given when protected

blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase

Suspend command. It is not possible to issue any command to abort the operation. Typical

chip erase times are given in Table 6. All Bus Read operations during the Chip Erase

operation will output the Status register on the Data Inputs/Outputs. See the section on the

Status register for more details.

After the Chip Erase operation has completed the memory will return to the Read mode,

unless an error has occurred. When an error occurs the memory will continue to output the

23/63

Command interface

M29W320ET, M29W320EB

Status register. A Read/Reset command must be issued to reset the error condition and

return to Read mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All

previous data is lost.

4.10

Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. It sets all of

the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is

lost.

Six Bus Write operations are required to select the first block in the list. Each additional

block in the list can be selected by repeating the sixth Bus Write operation using the address

of the additional block. The Block Erase operation starts the Program/Erase Controller after

a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any more blocks. Each additional block must

therefore be selected within 50µs of the last block. The 50µs timer restarts when an

additional block is selected. After the sixth Bus Write operation a Bus Read operation will

output the Status register. See the Status register section for details on how to identify if the

Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks

are erased. If all of the selected blocks are protected the Block Erase operation appears to

start but will terminate within about 100µs, leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase

Suspend command and the Read/Reset command which is only accepted during the 50µs

time-out period. Typical block erase times are given in Table 6.

After the Erase operation has started all Bus Read operations will output the Status register

on the Data Inputs/Outputs. See the section on the Status register for more details.

After the Block Erase operation has completed the memory will return to the Read mode,

unless an error has occurred. When an error occurs Bus Read operations will continue to

output the Status register. A Read/Reset command must be issued to reset the error

condition and return to Read mode.

4.11

Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase

operation and return the memory to Read mode. The command requires one Bus Write

operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency time of the

Erase Suspend Command being issued. Once the Program/Erase Controller has stopped

the memory will be set to Read mode and the Erase will be suspended. If the Erase

Suspend command is issued during the period when the memory is waiting for an additional

block (before the Program/Erase Controller starts) then the Erase is suspended immediately

and will start immediately when the Erase Resume Command is issued. It is not possible to

select any further blocks to erase after the Erase Resume.

24/63

M29W320ET, M29W320EB

Command interface

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. If any

attempt is made to program in a protected block or in the suspended block then the Program

command is ignored and the data remains unchanged. The Status register is not read and

no error condition is given. Reading from blocks that are being erased will output the Status

register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands

during an Erase Suspend. The Read/Reset command must be issued to return the device to

Read Array mode before the Resume command will be accepted.

During Erase Suspend a Bus Read operation to the Extended Block will output the

Extended Block data.

4.12

4.13

Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller after an

Erase Suspend. The device must be in Read Array mode before the Resume command will

be accepted. An erase can be suspended and resumed more than once.

Enter Extended Block command

The M29W320E has an extra 64Kbyte block (Extended Block) that can only be accessed

using the Enter Extended Block command. Three Bus write cycles are required to issue the

Extended Block command. Once the command has been issued the device enters

Extended Block mode where all Bus Read or Program operations to the Boot Block

addresses access the Extended Block. The Extended Block (with the same address as the

boot block) cannot be erased, and can be treated as one-time programmable (OTP)

memory. In Extended Block mode the Boot Blocks are not accessible.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be

undone.

4.14

4.15

Exit Extended Block command

The Exit Extended Block command is used to exit from the Extended Block mode and return

the device to Read mode. Four Bus Write operations are required to issue the command.

Block Protect and Chip Unprotect commands

Groups of blocks can be protected against accidental Program or Erase. The Protection

groups are shown in Appendix A: Block Addresses, Table 20 and Table 21, Block

Addresses. The whole chip can be unprotected to allow the data inside the blocks to be

changed.

Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.

25/63

Command interface

M29W320ET, M29W320EB

(1)(2)

Table 4.

Commands, 16-bit mode, BYTE = V

IH

Bus Write operations

3rd 4th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command

1st

2nd

5th

6th

1

3

X

F0

Read/Reset

Auto Select

555

AA

2AA

55

X

F0

90

A0

(BA)

555

3

555

AA

Program

4

3

555

AA

50

555

PA

PD

Double word Program

Unlock Bypass

PA0 PD0 PA1 PD1

AA

2AA

PA

55

555

20

Unlock Bypass

Program

2

X

A0

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

1

3

4

BA

55

Read CFI Query

Enter Extended Block

Exit Extended Block

98

555

AA

2AA

55

555

88

90

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is V_ILor DQ15 when BYTE is V_IH

.

26/63

M29W320ET, M29W320EB

Command interface

(1)(2)

Table 5.

Commands, 8-bit mode, BYTE = V

IL

Bus Write operations

3rd 4th

Add Data Add Data Add Data Add Data Add Data Add Data

Command

1st

2nd

5th

6th

1

3

X

F0

Read/Reset

Auto Select

AAA

AA

555

55

X

F0

90

A0

(BA)

AAA

3

AAA

AA

Program

4

5

3

2

6

AAA

X

AA

55

AAA

PA1

AAA

PA

PD

Quadruple byte Program

Unlock Bypass

PA0 PD0

PD1 PA2 PD2 PA3 PD3

20

AA

A0

90

555

PA

55

PD

00

55

Unlock Bypass Program

Unlock Bypass Reset

Chip Erase

X

AAA

AA

B0

30

555

AAA

80

AAA AA

555

55 AAA 10

Block Erase

6+ AAA

55

BA

30

Erase Suspend

1

3

4

BA

Erase Resume

Read CFI Query

Enter Extended Block

Exit Extended Block

AA

98

AAA

AA

555

55

AAA

88

90

X

00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in

hexadecimal.

2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15

are Don’t Care. DQ15A–1 is A–1 when BYTE is V_ILor DQ15 when BYTE is V_IH

.

27/63

Command interface

M29W320ET, M29W320EB

Table 6.

Program, Erase times and Program, Erase Endurance cycles

Parameter

Min

Typ⁽¹⁾⁽²⁾

Max⁽²⁾

Unit

Chip Erase

40

200⁽³⁾

6⁽³⁾

s

Block Erase (64 Kbytes)

0.8

s

µs

Erase Suspend Latency time

Program (byte or word)

50⁽⁴⁾

10

40

20

10

200⁽⁴⁾

200⁽³⁾

100⁽³⁾

µs

Double word Program (byte or word)

Chip Program (byte by byte)

Chip Program (word by word)

Chip Program (Quadruple byte or Double word)

Program/Erase Cycles (per Block)

Data Retention

µs

s

100,000

20

cycles

years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V_CCafter 100,00 program/erase cycles.

4. Maximum value measured at worst case conditions for both temperature and V_CC

.

28/63

M29W320ET, M29W320EB

Status register

5

Status register

The M29W320E has one Status register. It provides information on the current or previous

Program or Erase operations. The various bits convey information and errors on the

operation. Bus Read operations from any address, always read the Status register during

Program and Erase operations. It is also read during Erase Suspend when an address

within a block being erased is accessed.

The bits in the Status register are summarized in Table 7: Status register bits.

5.1

Data Polling bit (DQ7)

The Data Polling bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling bit is output on DQ7 when the Status register is read.

During Program operations the Data Polling bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

mode.

In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the

Program/Erase Controller has suspended the Erase operation.

Figure 6: Data Polling flowchart, gives an example of how to use the Data Polling bit. A Valid

Address is the address being programmed or an address within the block being erased.

5.2

Toggle bit (DQ6)

The Toggle bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Toggle

bit is output on DQ6 when the Status register is read.

During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address. After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle bit will output when addressing a cell within a block

being erased. The Toggle bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure 7: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 13

and Figure 14 describe Toggle bit timing waveform.

29/63

Status register

M29W320ET, M29W320EB

5.3

Error bit (DQ5)

The Error bit can be used to identify errors detected by the Program/Erase Controller. The

Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the

correct data to the memory. If the Error bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit is output on DQ5 when the Status register

is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to

do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.

One of the Erase commands must be used to set all the bits in a block or in the whole

memory from ’0’ to ’1’.

5.4

5.5

Erase Timer bit (DQ3)

The Erase Timer bit can be used to identify the start of Program/Erase Controller operation

during a Block Erase command. Once the Program/Erase Controller starts erasing the

Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit

is set to ’0’ and additional blocks to be erased may be written to the Command interface.

The Erase Timer bit is output on DQ3 when the Status register is read.

Alternative Toggle bit (DQ2)

The alternative Toggle bit can be used to monitor the Program/Erase controller during Erase

operations. The alternative Toggle bit is output on DQ2 when the Status register is read.

During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’,

etc., with successive Bus Read operations from addresses within the blocks being erased. A

protected block is treated the same as a block not being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read operations from addresses within the blocks being erased. Bus Read

operations to addresses within blocks not being erased will output the memory cell data as if

in Read mode.

After an Erase operation that causes the Error bit to be set the alternative Toggle bit can be

used to identify which block or blocks have caused the error. The alternative Toggle bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses

within blocks that have not erased correctly. The alternative Toggle bit does not change if the

addressed block has erased correctly.

30/63

M29W320ET, M29W320EB

Status register

(1)

Table 7.

Status register bits

Address

Operation

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Program

Any Address

DQ7

Toggle

0

–

0

Program during

Erase Suspend

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

Erasing Block

DQ7

Toggle

1

0

–

1

0

–

Hi-Z

0

Toggle

0

Block Erase before

timeout

No

Toggle

Non-Erasing Block

Erasing Block

0

Toggle

0

1

0

Toggle

Block Erase

No

Toggle

Non-Erasing Block

No

Toggle

Erasing Block

1

0

–

Toggle

Hi-Z

Erase Suspend

Non-Erasing Block

Data read as normal

Good Block

Address

No

Toggle

0

Toggle

1

Erase Error

Faulty Block

Address

Toggle

Hi-Z

1. Unspecified data bits should be ignored.

31/63

Status register

Figure 6.

M29W320ET, M29W320EB

Data Polling flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

=

YES

DATA

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

DQ7

=

YES

DATA

NO

FAIL

PASS

AI90194

32/63

M29W320ET, M29W320EB

Figure 7. Toggle flowchart

Status register

START

READ DQ6

ADDRESS = BA

READ

DQ5 & DQ6

ADDRESS = BA

DQ6

=

NO

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

ADDRESS = BA

DQ6

=

NO

TOGGLE

YES

FAIL

PASS

AI08929b

1. BA = Address of Block being Programmed or Erased.

33/63

Maximum rating

M29W320ET, M29W320EB

6

Maximum rating

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability. These are stress ratings only and

operation of the device at these or any other conditions above those indicated in the

Operating sections of this specification is not implied. Refer also to the Numonyx SURE

Program and other relevant quality documents.

Table 8.

Symbol

Absolute maximum ratings

Parameter

Min

Max

Unit

T_BIAS

T_STG

V_IO

Temperature under Bias

Storage Temperature

Input or Output voltage ⁽¹⁾⁽²⁾

Supply voltage

–50

–65

125

150

°C

V

–0.6

V_CC+0.6

4

V_CC

V_ID

V

Identification voltage

Program voltage

13.5

V

(3)

V_PP

13.5

V

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V_CC+2V during transition and for less than 20ns during transitions.

3. V_PPmust not remain at 12V for more than a total of 80hrs.

34/63

M29W320ET, M29W320EB

DC and ac parameters

7

DC and ac parameters

This section summarizes the operating measurement conditions, and the dc and ac

characteristics of the device. The parameters in the dc and ac characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 9: Operating and ac measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Table 9.

Operating and ac measurement conditions

M29W320ET, M29W320EB

Parameter

70

90

Unit

Min

Max

Min

Max

V

_CCSupply voltage

2.7

3.6

85

2.7

3.6

85

V

°C

pF

ns

V

Ambient operating temperature

Load capacitance (C_L)

–40

30

Input Rise and Fall times

10

Input Pulse voltages

0 to V_CC

V_CC/2

0 to V_CC

V_CC/2

Input and Output Timing Ref. voltages

V

Figure 8.

AC measurement I/O waveform

V

CC

V

/2

CC

0V

AI05557

Figure 9.

AC measurement Load circuit

V

CC

PP

CC

25kΩ

DEVICE

UNDER

TEST

25kΩ

C

L

0.1µF

C

includes JIG capacitance

L

AI05558

35/63

DC and ac parameters

M29W320ET, M29W320EB

(1)

Table 10. Device capacitance

Symbol

Parameter

Test condition

Min

Max

Unit

C_IN

Input capacitance

Output capacitance

V_IN= 0V

6

pF

C_OUT

V_OUT= 0V

12

1. Sampled only, not 100% tested.

Table 11. DC characteristics

Symbol

Parameter

Test condition

Min

Max

Unit

I_LI

Input Leakage current

Output Leakage current

0V ≤V_IN≤V_CC

1

µA

I_LO

0V ≤V_OUT≤V_CC

E = V_IL, G = V_IH,

f = 6MHz

(1)

I_CC1

Supply current (Read)

10

100

20

mA

E = V_CC0.2V,

RP = V_CC0.2V

I_CC2

Supply current (Standby)

µA

mA

V_PP/WP =

V_ILor V_IH

Program/Erase

I_CC3

Supply current

(Program/Erase)

Controller

active

(2)(1)

V_PP/WP =

20

V_PP

V_IL

V_IH

Input Low voltage

Input High voltage

–0.5

0.8

V

0.7V_CC

V_CC+0.3

12.5

Voltage for V_PP/WP

Program Acceleration

V_PP

I_PP

V

_CC= 2.7V 10%

11.5

V

Current for V_PP/WP

Program Acceleration

V_CC= 2.7V 10%

15

mA

V_OL

V_OH

V_ID

Output Low voltage

Output High voltage

Identification voltage

I_OL= 1.8mA

0.45

V

I_OH= –100µA

V_CC–0.4

11.5

12.5

2.3

Program/Erase Lockout

Supply voltage

V_LKO

1.8

V

1. In Dual operations the Supply current will be the sum of I_CC1(read) and I_CC3(program/erase).

2. Sampled only, not 100% tested.

36/63

M29W320ET, M29W320EB

DC and ac parameters

Figure 10. Read mode ac waveforms

tAVAV

VALID

A0-A20/

A–1

tAVQV

tAXQX

E

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05559

Table 12. Read ac characteristics

M29W320ET, M29W320EB

Symbol

Alt

Parameter

Test Condition

Unit

70

90

E = V_IL,

Min

t_AVAV

t_AVQV

t_RCAddress Valid to Next Address Valid

t_ACCAddress Valid to Output Valid

70

90

ns

G = V_IL

E = V_IL,

Max

70

90

G = V_IL

(1)

t_ELQX

t_LZChip Enable Low to Output Transition

t_CEChip Enable Low to Output Valid

G = V_IL

Min

0

ns

t_ELQV

Max

70

90

Output Enable Low to Output

Transition

(1)

t_GLQX

t_OLZ

E = V_IL

Min

0

ns

t_GLQV

t_OEOutput Enable Low to Output Valid

t_HZChip Enable High to Output Hi-Z

t_DFOutput Enable High to Output Hi-Z

E = V_IL

G = V_IL

E = V_IL

Max

30

25

35

30

ns

(1)

t_EHQZ

(1)

t_GHQZ

t_EHQX

t_GHQX

Chip Enable, Output Enable or

t_OH

Min

0

5

0

5

ns

Address Transition to Output Transition

t_AXQX

t_ELBL

t_ELBH

t_BLQZ

t_BHQV

t_ELFL

Chip Enable to BYTE Low or High

t_ELFH

Max

t_FLQZBYTE Low to Output Hi-Z

t_FHQVBYTE High to Output Valid

Max

25

30

40

ns

1. Sampled only, not 100% tested.

37/63

DC and ac parameters

M29W320ET, M29W320EB

Figure 11. Write ac waveforms, Write Enable controlled

tAVAV

A0-A20/

VALID

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tDVWH

VALID

tWHDX

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05560

Table 13. Write ac characteristics, Write Enable controlled

M29W320ET, M29W320EB

Symbol

Alt

Parameter

Unit

70

90

t_AVAV

t_ELWL

t_WLWH

t_DVWH

t_WHDX

t_WHEH

t_WHWL

t_AVWL

t_WLAX

t_GHWL

t_WHGL

t_WC

t_CS

t_WP

t_DS

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

Max

Min

70

0

90

0

ns

µs

45

0

50

0

t_DH

t_CH

t_WPH

t_AS

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Program/Erase Valid to RB Low

0

30

0

30

0

t_AH

45

0

50

0

t_OEH

t_BUSY

t_VCS

0

(1)

t_WHRL

30

50

35

50

t_VCHEL

V_CCHigh to Chip Enable Low

1. Sampled only, not 100% tested.

38/63

M29W320ET, M29W320EB

DC and ac parameters

Figure 12. Write ac waveforms, Chip Enable controlled

tAVAV

A0-A20/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tDVEH

tEHDX

DQ0-DQ7/

DQ8-DQ15

VALID

V

CC

tVCHWL

RB

tEHRL

AI05561

Table 14. Write ac characteristics, Chip Enable controlled

M29W320ET, M29W320EB

Symbol

Alt

Parameter

Unit

70

90

t_AVAV

t_WLEL

t_ELEH

t_DVEH

t_EHDX

t_EHWH

t_EHEL

t_AVEL

t_ELAX

t_GHEL

t_EHGL

t_WC

t_WS

t_CP

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

Max

Min

70

0

90

0

ns

µs

45

0

50

0

t_DS

t_DH

t_WH

t_CPH

t_AS

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

Program/Erase Valid to RB Low

0

30

0

30

0

t_AH

45

0

50

0

t_OEH

t_BUSY

t_VCS

0

(1)

t_EHRL

30

50

35

50

t_VCHWL

V_CCHigh to Write Enable Low

1. Sampled only, not 100% tested.

39/63

DC and ac parameters

M29W320ET, M29W320EB

Figure 13. Toggle and alternative Toggle bits mechanism, Chip Enable controlled

A0-A20

VALID ADDRESS

tAXEL

E

G

tELQV

Alternative Toggle/

Toggle Bit

Alternative Toggle/

Toggle Bit

Data

(1)

(2)

DQ2 /DQ6

AI09350

1. The Toggle bit is output on DQ6.

2. The alternative Toggle bit is output on DQ2.

Figure 14. Toggle and alternative Toggle bits mechanism, Output Enable controlled

A0-A20

VALID ADDRESS

tAXGL

G

E

tGLQV

Alternative Toggle/

Toggle Bit

Alternative Toggle/

Toggle Bit

(1)

(2)

Data

DQ2 /DQ6

AI09351

1. The Toggle bit is output on DQ6.

2. The alternative Toggle bit is output on DQ2.

(1)

Table 15. Toggle and alternative Toggle bits ac characteristics

M29W320ET,

M29W320EB

Symbol

Alt

Parameter

Unit

70

90

t_AXEL

t_AXGL

Address Transition to Chip Enable Low

Address Transition to Output Enable Low

Min

10

ns

1. t_ELQVand t_GLQVvalues are presented in Table 12: Read ac characteristics.

40/63

M29W320ET, M29W320EB

DC and ac parameters

Figure 15. Reset/Block Temporary Unprotect ac waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX

RP

tPHPHH

tPLYH

AI02931B

Table 16. Reset/Block Temporary Unprotect ac characteristics

M29W320ET,

M29W320EB

Symbol

Alt

Parameter

Unit

70

90

(1)

t_PHWL

RP High to Write Enable Low, Chip Enable

Low, Output Enable Low

t_PHEL

t_RH

Min

50

ns

(1)

t_PHGL

(1)

t_RHWL

RB High to Write Enable Low, Chip Enable

Low, Output Enable Low

(1)

t_RHEL

t_RB

0

(1)

t_RHGL

t_PLPX

t_RP

RP Pulse Width

Min

Max

Min

500

50

500

50

ns

µs

ns

t_PLYH

t_READYRP Low to Read mode

(1)

t_PHPHH

t_VIDR

RP Rise time to V_ID

500

250

500

250

(1)

t_VHVPP

V_PPRise and Fall time

1. Sampled only, not 100% tested.

Figure 16. Accelerated Program Timing waveforms

V

PP

V

/WP

PP

V

or V

IH

IL

tVHVPP

AI05563

41/63

Package mechanical

M29W320ET, M29W320EB

8

Package mechanical

Figure 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, top view package outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

1. Drawing not to scale.

Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

B

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

α

0

5

0

5

42/63

M29W320ET, M29W320EB

Package mechanical

Figure 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, bottom view package outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

1. Drawing not to scale.

Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

43/63

Part numbering

M29W320ET, M29W320EB

9

Part numbering

Table 19. Ordering information scheme

Example:

M29W320EB

70

N

1

T

Device type

M29

Operating voltage

W = V_CC= 2.7 to 3.6V

Device function

320E = 32 Mbit (x8/x16), Uniform Parameter Blocks,

Boot Block

Array matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZE = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = standard packing

T = Tape & Reel packing

E = ECOPACK package, standard packing

F = ECOPACK package, Tape & Reel packing

Note:

This product is also available with the Extended Block factory locked. For further details and

ordering information contact your nearest Numonyx sales office.

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect

of this device, please contact the Numonyx Sales Office nearest to you.

44/63

M29W320ET, M29W320EB

Block Addresses

Appendix A Block Addresses

Table 20. Top Boot Block Addresses, M29W320ET

Block size

Protection Block

group

Block

(x8)

(x16)

(Kbytes/Kwords)

0

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

1

Protection group

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

45/63

Block Addresses

M29W320ET, M29W320EB

Table 20. Top Boot Block Addresses, M29W320ET (continued)

Block size

Protection Block

group

Block

(x8)

(x16)

(Kbytes/Kwords)

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

64/32

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

Protection group

46/63

M29W320ET, M29W320EB

Table 20. Top Boot Block Addresses, M29W320ET (continued)

Block Addresses

(x16)

Block size

Protection Block

group

Block

(x8)

(Kbytes/Kwords)

60

61

62

63

64

65

66

67

68

69

70

64/32

8/4

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

Protection group

3F0000h–3F1FFFh⁽¹⁾1F8000h–1F8FFFh⁽¹⁾

3F2000h–3F3FFFh⁽¹⁾1F9000h–1F9FFFh⁽¹⁾

3F4000h–3F5FFFh⁽¹⁾1FA000h–1FAFFFh⁽¹⁾

3F6000h–3F7FFFh⁽¹⁾1FB000h–1FBFFFh⁽¹⁾

3F8000h–3F9FFFh⁽¹⁾1FC000h–1FCFFFh⁽¹⁾

3FA000h–3FBFFFh⁽¹⁾1FD000h–1FDFFFh⁽¹⁾

3FC000h–3FDFFFh⁽¹⁾1FE000h–1FEFFFh⁽¹⁾

3FE000h–3FFFFFh⁽¹⁾1FF000h–1FFFFFh⁽¹⁾

8/4

1. Used as the Extended Block Addresses in Extended Block mode.

Table 21. Bottom Boot Block Addresses, M29W320EB

Block size

(Kbytes/Kwords)

Protection Block

group

Block

(x8)

(x16)

0

1

8/4

Protection group

000000h-001FFFh⁽¹⁾000000h–000FFFh⁽¹⁾

002000h-003FFFh⁽¹⁾001000h–001FFFh⁽¹⁾

004000h-005FFFh⁽¹⁾002000h–002FFFh⁽¹⁾

006000h-007FFFh⁽¹⁾003000h–003FFFh⁽¹⁾

008000h-009FFFh⁽¹⁾004000h–004FFFh⁽¹⁾

00A000h-00BFFFh⁽¹⁾005000h–005FFFh⁽¹⁾

00C000h-00DFFFh⁽¹⁾006000h–006FFFh⁽¹⁾

00E000h-00FFFFh⁽¹⁾007000h–007FFFh⁽¹⁾

2

8/4

3

8/4

4

8/4

5

8/4

6

8/4

7

8/4

8

64/32

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

9

Protection group

10

11

12

13

14

15

16

17

18

Protection group

47/63

Block Addresses

Block

M29W320ET, M29W320EB

(x16)

Table 21. Bottom Boot Block Addresses, M29W320EB (continued)

Block size

Protection Block

group

(x8)

(Kbytes/Kwords)

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

64/32

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

Protection group

48/63

M29W320ET, M29W320EB

Block Addresses

(x16)

Table 21. Bottom Boot Block Addresses, M29W320EB (continued)

Block size

(Kbytes/Kwords)

Protection Block

group

Block

(x8)

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

64/32

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Protection group

1. Used as the Extended Block Addresses in Extended Block mode.

49/63

Common Flash Interface (CFI)

M29W320ET, M29W320EB

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from

the Flash memory device. It allows a system software to query the device to determine various electrical

and timing parameters, density information and functions supported by the memory. The system can

interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI

Query Command is issued the device enters CFI Query mode and the data structure is read from the

memory. Table 22, Table 23, Table 24, Table 25, Table 26 and Table 27 show the addresses used to

retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number is written

(see Table 27: Security code area). This area can be accessed only in Read mode by the final user. It is

impossible to change the security number after it has been written by Numonyx.

(1)

Table 22. Query Structure Overview

Address

Sub-section name

Description

x16

x8

10h

1Bh

27h

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

61h

80h

C2h

Security code area

64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

(1)

Table 23. CFI Query Identification String

Address

Data

Description

Value

x16

x8

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

“Q”

"R"

"Y"

0052h Query unique ASCII string "QRY"

0059h

0002h

AMD

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

Compatible

0000h

0040h

Address for Primary Algorithm extended query table (see Table 26)

P = 40h

NA

0000h

Alternate Vendor Command Set and Control Interface ID code second

vendor - specified algorithm supported

0000h

Address for Alternate Algorithm extended Query table

0000h

NA

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

50/63

M29W320ET, M29W320EB

Common Flash Interface (CFI)

Table 24. CFI Query System Interface Information

Address

Data

0027h

0036h

00B5h

00C5h

Description

Value

x16

x8

V_CCLogic Supply Minimum Program/Erase voltage

1Bh

36h

bit 7 to 4BCD value in volts

2.7V

3.6V

bit 3 to 0BCD value in 100 mV

V_CCLogic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

1Ch

1Dh

1Eh

38h

3Ah

3Ch

bit 3 to 0BCD value in 100 mV

V_PP[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4HEX value in volts

11.5V

12.5V

bit 3 to 0BCD value in 100 mV

V

_PP[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4HEX value in volts

bit 3 to 0BCD value in 100 mV

1Fh

20h

21h

22h

23h

24h

25h

26h

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0004h

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

Typical timeout per single byte/word program = 2ⁿµs

Typical timeout for minimum size write buffer program = 2ⁿµs

Typical timeout per individual block erase = 2ⁿms

16µs

NA

1s

Typical timeout for full Chip Erase = 2ⁿms

NA

Maximum timeout for byte/word program = 2ⁿtimes typical

Maximum timeout for write buffer program = 2ⁿtimes typical

Maximum timeout per individual block erase = 2ⁿtimes typical

Maximum timeout for Chip Erase = 2ⁿtimes typical

256 µs

NA

8 s

NA

51/63

Common Flash Interface (CFI)

M29W320ET, M29W320EB

(1)

Table 25.

Device Geometry Definition

Address

Data

Description

Value

x16

x8

27h

4Eh

0016h

Device Size = 2ⁿin number of bytes

4 Mbyte

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface code description

2Ah

2Bh

54h

56h

0000h

Maximum number of bytes in multi-byte program or page = 2ⁿ

NA

2

Number of Erase Block regions. It specifies the number of

regions containing contiguous Erase Blocks of the same size.

2Ch

58h

0002h

2Dh

2Eh

5Ah

5Ch

0007h

0000h

Region 1 information

8

Number of Erase Blocks of identical size = 0007h+1

2Fh

30h

5Eh

60h

0020h

0000h

Region 1 information

8Kbyte

63

Block size in Region 1 = 0020h * 256 byte

31h

32h

62h

64h

003Eh

0000h

Region 2 information

Number of Erase Blocks of identical size = 003Eh+1

33h

34h

66h

68h

0000h

0001h

Region 2 information

64Kbyte

Block size in region 2 = 0100h * 256 byte

1. For the M29W320EB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to

1FFFFFh. For the M29W320ET, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses

000000h to 1F7FFFh.

Table 26. Primary Algorithm-specific extended Query table

Address

Data

Description

Value

x16

x8

40h

41h

42h

43h

44h

80h

82h

84h

86h

88h

0050h

"P"

"R"

"I"

0052h Primary Algorithm extended Query table unique ASCII string “PRI”

0049h

0031h Major version number, ASCII

0030h Minor version number, ASCII

"1"

"0"

Address Sensitive Unlock (bits 1 to 0)

0000h 00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

45h

8Ah

Yes

Erase Suspend

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

2

1

00 = not supported, 01 = Read only, 02 = Read and Write

Block Protection

0001h

00 = not supported, x = number of blocks in per group

Temporary Block Unprotect

0001h

Yes

04

00 = not supported, 01 = supported

Block Protect /Unprotect

0004h

04 = M29W320E

52/63

M29W320ET, M29W320EB

Common Flash Interface (CFI)

Table 26. Primary Algorithm-specific extended Query table (continued)

Address

Data

Description

Value

x16

x8

4Ah

4Bh

4Ch

94h

96h

98h

0000h Simultaneous operations, 00 = not supported

No

0000h Burst mode, 00 = not supported, 01 = supported

0000h Page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word

V_PPSupply Minimum Program/Erase voltage

4Dh

9Ah

00B5h bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

11.5V

V_PPSupply Maximum Program/Erase voltage

00C5h bit 7 to 4 HEX value in volts

4Eh

4Fh

9Ch

9Eh

12.5V

–

bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

000xh

02h = Bottom Boot device, 03h = Top Boot device

Table 27. Security code area

Address

Data

Description

x16

x8

61h

62h

63h

64h

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

53/63

Extended memory Block

M29W320ET, M29W320EB

Appendix C Extended memory Block

The M29W320E has an extra block, the Extended Block, that can be accessed using a

dedicated command.

This Extended Block is 32 Kwords in x16 mode and 64 Kbytes in x8 mode. It is used as a

security block (to provide a permanent security identification number) or to store additional

information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated

by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be

changed. When set to ‘1’, it indicates that the device is factory locked and the Extended

Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the

Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is

another security feature which ensures that a customer lockable device cannot be used

instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify code and a specific

procedure must be followed to read it. See “Extended memory Block Verify code” in Table 2

and Section Table 3. on page 19, Table 2: Bus operations, BYTE = V and Table 3: Bus

IL

operations, BYTE = V , respectively, for details of how to read bit DQ7.

IH

The Extended Block can only be accessed when the device is in Extended Block mode. For

details of how the Extended Block mode is entered and exited, refer to Section 4.13: Enter

Extended Block command and Section 4.14: Exit Extended Block command, and to Table 4

and Table 5, Table 4: Commands, 16-bit mode, BYTE = V and Table 5: Commands, 8-bit

IH

mode, BYTE = V , respectively.

IL

9.1

9.2

Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is

written to the Extended Block address space (see Table 28: Extended Block Address and

data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to

‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the

Extended Block but care must be taken because the protection of the Extended Block is not

reversible.

There are two ways of protecting the Extended Block:

●

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the In-system technique with RP either at V or at V (refer to Appendix D:

IH

ID

Block Protection, Section D.2: In-system technique and to the corresponding

flowcharts, Figure 21 and Figure 22, for a detailed explanation of the technique).

●

Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the Programmer technique (refer to Appendix D: Block Protection,

Section D.1: Programmer technique and to the corresponding flowcharts, Figure 19

and Figure 20, for a detailed explanation of the technique).

54/63

M29W320ET, M29W320EB

Extended memory Block

Once the Extended Block is programmed and protected, the Exit Extended Block command must be

issued to exit the Extended Block mode and return the device to Read mode.

Table 28. Extended Block Address and data

Address⁽¹⁾

Data

Device

x8

x16

Factory Locked

Customer Lockable

Security identification

number

3F0000h-3F000Fh

3F0010h-3FFFFFh

000000h-00000Fh

000010h-00FFFFh

1F8000h-1F8007h

1F8008h-1FFFFFh

000000h-000007h

000008h-007FFFh

Determined by

customer

M29W320ET

Unavailable

Security identification

number

Determined by

customer

M29W320EB

Unavailable

1. See Table 20 and Table 21, Top and Bottom Boot Block Addresses.

55/63

Block Protection

M29W320ET, M29W320EB

Appendix D Block Protection

Block protection can be used to prevent any operation from modifying the data stored in the

memory. The blocks are protected in groups, refer to Appendix A: Block Addresses,

Table 20 and Table 21. for details of the Protection groups. Once protected, Program and

Erase operations within the protected group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the

Programmer technique, the In-system technique and Temporary Unprotection. Temporary

Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is

described in the Signal Descriptions section.

D.1

Programmer technique

The Programmer technique uses high (V ) voltage levels on some of the bus pins. These

ID

cannot be achieved using a standard microprocessor bus, therefore the technique is

recommended only for use in programming equipment.

To protect a group of blocks follow the flowchart in Figure 19, Programmer Equipment Block

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all groups can be unprotected at the same time. To unprotect the chip follow Figure 20:

Programmer Equipment Chip Unprotect flowchart. Table 29: Programmer technique Bus

operations, BYTE = V or V , gives a summary of each operation.

IH

IL

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possible. Do not abort the procedure before

reaching the end. Chip Unprotect can take several seconds and a user message should be

provided to show that the operation is progressing.

D.2

In-system technique

The In-system technique requires a high voltage level on the Reset/Blocks Temporary

(1)

Unprotect pin, RP . This can be achieved without violating the maximum ratings of the

components on the microprocessor bus, therefore this technique is suitable for use after the

memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure 21: In-system Equipment Group

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all the groups can be unprotected at the same time. To unprotect the chip follow

Figure 22: In-system Equipment Chip Unprotect flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a

pause is specified, it is followed as closely as possible. Do not allow the microprocessor to

service interrupts that will upset the timing and do not abort the procedure before reaching

the end. Chip Unprotect can take several seconds and a user message should be provided

to show that the operation is progressing.

Note:

RP can be either at V or at V when using the In-system technique to protect the

IH ID

Extended Block.

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M29W320ET, M29W320EB

Block Protection

Table 29. Programmer technique Bus operations, BYTE = V or V

IH

IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A20

A9 = V_ID, A12-A20 Block Address

others = X

Block (group)

Protect⁽¹⁾

V_IL

V_IDV_ILPulse

X

A9 = V_ID, A12 = V_IH, A15 = V_IH

others = X

Chip Unprotect

V_IDV_IDV_ILPulse

A0 = V_IL, A1 = V_IH, A6 = V_IL, A9 = V_ID,

A12-A20 Block Address

Pass = XX01h

Retry = XX00h

Block (group)

Protection Verify

V_IL

V_IH

others = X

A0 = V_IL, A1 = V_IH, A6 = V_IH,

A9 = V_ID, A12-A20 Block Address

Retry = XX01h

Pass = XX00h

Block (group)

Unprotection Verify

V_IH

others = X

1. Block Protection groups are shown in Appendix A: Block Addresses, Table 20 and Table 21.

57/63

Block Protection

M29W320ET, M29W320EB

Figure 19. Programmer Equipment Group Protect flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A6 = V

A1 = V

,

IL

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

= 25

NO

A9 = V

E, G = V

IH

YES

PASS

A9 = V

IH

E, G = V

IH

AI05574

FAIL

1. Block Protection groups are shown in Appendix A: Block Addresses, Table 20 and Table 21.

58/63

M29W320ET, M29W320EB

Block Protection

Figure 20. Programmer Equipment Chip Unprotect flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1, A6 = V

IL

IH

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT GROUP

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

GROUP

NO

++n

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL

PASS

AI05575

1. Block Protection groups are shown in Appendix A: Block Addresses, Table 20 and Table 21.

59/63

Block Protection

M29W320ET, M29W320EB

Figure 21. In-system Equipment Group Protect flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 100µs

WRITE 40h

IL

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

Wait 4µs

READ DATA

ADDRESS = GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

DATA

NO

=

01h

YES

++n

= 25

NO

RP = V

IH

YES

ISSUE READ/RESET

COMMAND

RP = V

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI05576

1. Block Protection groups are shown in Appendix A: Block Addresses, Table 20 and Table 21.

2. RP can be either at V_IHor at V_IDwhen using the In-system technique to protect the Extended Block.

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M29W320ET, M29W320EB

Block Protection

Figure 22. In-system Equipment Chip Unprotect flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT GROUP

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

DATA

NO

YES

=

00h

++n

= 1000

NO

LAST

GROUP

YES

RP = V

IH

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI05577

1. Block Protection groups are shown in Appendix A: Block Addresses, Table 20 and Table 21.

61/63

Revision history

M29W320ET, M29W320EB

Revision history

Table 30. Document revision history

Date

Version

Changes

15-Apr-2004

1.0

First Issue.

Protection group for Blocks 0 to 3 and and Blocks 67 to 70 modifed in

Table 20: Top Boot Block Addresses, M29W320ET and Table 21:

Bottom Boot Block Addresses, M29W320EB, respectively.

18-Nov-2004

2.0

TFBGA48 Commercial code changed from ZA to ZE.

RB updated in Table 7: Status register bits.

14-Mar-2005

28-Mar-2006

3.0

4.0

Section 4.5: Fast Program commands restructured and updated.

Section 4.6: Unlock Bypass command updated.

Datasheet title modified.

ECOPACK text added.

Changed DQ7 to DQ7 for ‘Program’, ‘Program during Erase Suspend’,

and ‘Program Error’ in Table 7: Status register bits.

16-Jan-2007

26-Mar-2008

5

6

Applied Numonyx branding.

62/63

M29W320ET, M29W320EB

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Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

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Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

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Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

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*Other names and brands may be claimed as the property of others.

63/63


型号：	M29W320ET90N6E
厂家：	NUMONYX B.V
描述：	32 Mbit (4Mbx8 or 2Mbx16, Uniform Parameter Blocks, Boot Block) 3V supply Flash memory 32兆位（ 4Mbx8或2Mbx16 ，统一参数块，引导块） 3V供应闪存闪存存储内存集成电路光电二极管
文件：	总63页 (文件大小：1191K)
中文：	中文翻译
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M29W320ET90N6E [NUMONYX]

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