M36L0R7050U3ZAME [NUMONYX]
Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88;
| 型号： | M36L0R7050U3ZAME |
| 厂家： | 
NUMONYX B.V |
| 描述： | Memory Circuit, 8MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88 |
| 文件： | 总29页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36L0Rx0x0UL3
128- or 256-Mbit (mux I/O, multiple bank, multilevel, burst) flash
memory, and 32- or 64-Mbit PSRAM, 1.8 V supply MCP
Target Specification
Features
■ Multichip package
FBGA
– 1 die of 128 Mbits (8 Mbits x16) or 256
Mbits (16 Mbits x16), mux I/O multiple
bank, multilevel, burst flash memory
– 1 die of 32 or 64 Mbits mux I/O, burst
PSRAM
TFBGA56 (ZS)
8 x 6 mm
TFBGA88 (ZAM)
8 x 10 mm
■ Supply voltage
– V
– V
= V
= V = 1.7 to 1.95 V
DDQF
■ Security
DDF
PPF
DDP
= 9 V for fast program
– 64-bit unique device number
– 2112-bit user programmable OTP cells
■ Electronic signature
– Manufacturer code: 20h
■ Common flash interface (CFI)
– Device codes (top flash configuration):
M36L0R7050U3/M36L0R7060U3: 882Eh
M36L0R8050U3/M36L0R8060U3: 881Ch
■ 100,000 program/erase cycles per block
PSRAM
■ Access time: 70 ns
– Device codes (bottom flash configuration)
M36L0R7050L3/M36L0R7060L3: 882Fh
M36L0R8050L3/M36L0R8060L3: 881Dh
■ Synchronous modes:
– Synchronous write: continuous burst
Flash memory
– Synchronous read: continuous burst or
fixed length: 4, 8 or 16 words for 32-Mbit
devices; 4, 8, 16 or 32 words for 64-Mbit
devices
■ Synchronous/asynchronous read
– Synchronous burst read mode: 66 MHz
– Random access: 70 ns
– Maximum clock frequency: 83 MHz
■ Programming time
■ Low-power features
– 2.5 µs typical word program time using
buffer enhanced factory program command
– Partial array self-refresh (PASR)
– Deep power-down (DPD) mode
■ Memory organization
– Automatic temperature-compensated self-
refresh
– Multiple bank memory array: 8-Mbit banks
– Parameter blocks (top or bottom location)
Table 1.
Device summary
M36L0Rx0xoUL3
■ Dual operations
– Program/erase in one bank, read in others
■ Block locking
M36L0R7050U3
M36L0R7060U3
M36L0R8050U3
M36L0R8060U3
M36L0R7050L3
M36L0R7060L3
M36L0R8050L3
M36L0R8060L3
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for block lock-down
F
– Absolute write protection with V
= V
SS
PPF
March 2008
Rev 2
1/29
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.numonyx.com
1
M36L0Rx0x0UL3
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Signals common to both packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
Address inputs (ADQ0-ADQ15 and A16-A23) . . . . . . . . . . . . . . . . . . . . 11
Data inputs/outputs (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Chip Enable (E ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
F
Flash memory Write Protect (WP ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
F
Flash memory Reset (RP ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
F
PSRAM Chip Enable (E ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
2.1.10 PSRAM Upper Byte Enable (UB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
2.1.11 PSRAM Lower Byte Enable (LB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
2.1.12 PSRAM Configuration Register Enable (CR ) . . . . . . . . . . . . . . . . . . . . 13
P
2.1.13
2.1.14
2.1.15
V
V
V
flash memory program supply voltage . . . . . . . . . . . . . . . . . . . . . 13
PPF
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SSQ
2.2
2.3
Signals only in TFBGA56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDQ
Signals only in TFBGA88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
Flash memory Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
F
Flash memory Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
F
PSRAM Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
P
PSRAM Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
P
V
V
flash memory supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PSRAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDF
CCP
3
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M36L0Rx0x0UL3
5
6
7
8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M36L0Rx0x0UL3
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TFBGA56 package operating modes - standard asynchronous operation. . . . . . . . . . . . . 18
TFBGA88 package operating modes - standard asynchronous operation. . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Stacked TFBGA56 8 x 6 mm - 8 x 6 active ball array, 0.50 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package mechanical data . 26
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9.
Table 10.
Table 11.
4/29
M36L0Rx0x0UL3
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram - TFBGA56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram - TFBGA88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA56 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA88 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . 10
Functional block diagram - TFBGA56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional block diagram - TFBGA88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TFBGA56 8 x 6 mm, 8 x 6 ball array - 0.50 mm pitch, package outline . . . . . . . . . . . . . . . 23
Figure 10. Stacked TFBGA88 8 x 10 mm, 8 x 10 active ball array - 0.8 mm pitch, package outline . . 25
5/29
Description
M36L0Rx0x0UL3
1
Description
The M36L0R7050U3, M36L0R7050L3, M36L0R7060U3, M36L0R7060L3,
M36L0R8050U3, M36L0R8050L3, M36L0R8060U3, and M36L0R8060L3 combine two
memory devices in a multichip package:
●
a 128 or 256 Mbit, multiple bank flash memory, the M58LRxxxKCD
●
a 32 or 64 Mbit PSRAM, the M69KM048AA or M69KM096AA, respectively.
Collectively, this family of devices is referred to as the M36L0Rx0xoUL3.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58LRxxxKCD and
M69KM048AA or M69KM096AA datasheets, where all specifications required to operate
the flash memory and PSRAM components are fully detailed. These datasheets are
available from your local Numonyx distributor.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in either the stacked TFBGA56 (8 x 6 mm, 8 x 6 ball array, 0.5 mm
pitch) or the stacked TFBGA88 (8 x 10 mm, 8 x 10 ball array, 0.8 mm pitch) package.
Figure 1.
Logic diagram - TFBGA56 package
V
V
V
DD
DDQ
PPF
7 or 8
A16-A22 or A16-A23(1)
16
ADQ0-ADQ15
WAIT
E
F
G
W
RP
F
M36L0Rx0x0UL3
WP
F
L
DPD
K
E
P
CR
UB
P
P
LB
P
V
Ai14405g
V
SS
SSQ
1. A16-A22 for the M36L0R7050UL3 and M36L0R7060UL3, and A16-A23 for the M36L0R8050UL3 and
M36L0R8060UL3.
6/29
M36L0Rx0x0UL3
Figure 2.
Description
Logic diagram - TFBGA88 package
V
V
DDQF
PPF
V
V
DDF
DDP
7 or 8
A16-A22 or A16-A23(1)
16
ADQ0-ADQ15
WAIT
E
G
F
F
F
W
RP
F
F
M36L0Rx0x0UL3
WP
L
K
E
P
P
G
W
P
CR
P
UB
P
P
LB
V
Ai13541e
SS
1. A16-A22 for the M36L0R7050UL3 and M36L0R7060UL3, and A16-A23 for the M36L0R8050UL3 and
M36L0R8060UL3.
7/29
Description
M36L0Rx0x0UL3
Direction
Table 2.
Name
Common to both packages
Signal names
Function
A16-A23(1)
Address inputs
Inputs
Flash memory and PSRAM common data input/outputs, address
inputs or command inputs
ADQ0-ADQ15
Inputs/outputs
L
Flash memory and PSRAM Latch Enable input
Flash memory and PSRAM Burst Clock
Flash memory and PSRAM Wait Data in burst mode
Flash memory Chip Enable input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
K
WAIT
EF
WPF
RPF
EP
Flash memory Write Protect input
Flash memory Reset input
PSRAM Chip Enable input
UBP
LBP
CRP
VPPF
VSS
VSSQ
NC
PSRAM Upper Byte Enable input
PSRAM Lower Byte Enable input
PSRAM Configuration Register Enable input
Flash memory optional supply voltage for fast program and erase Power supply
Flash memory and PSRAM shared ground
Flash memory and PSRAM shared ground.
Not connected internally
Ground
Ground
Only in TFBGA56 package
DPD
G
Deep power-down
Input
Flash memory and PSRAM Output Enable input
Flash memory and PSRAM Write Enable input
Flash memory and PSRAM shared power supply
Flash memory and PSRAM shared power supply for I/O buffers
Input
W
Input
VDD
VDDQ
Power supply
Power supply
Only in TFBGA88 package
GF
Flash memory Output Enable input
Input
WF
Flash memory Write Enable input
PSRAM Output Enable input
Input
GP
Input
WP
PSRAM Write Enable input
Input
VDDF
VCCP
Flash memory power supply
Power supply
Power supply
PSRAM supply voltage is the core supply voltage.
1. In the TFBGA56 package, address inputs A16-A18 in the PSRAM are used in conjunction with ADQ0 to
ADQ15 to select the cells in the memory array that are accessed during read and write operations.
However, in the TFBGA88 package, it is is address inputs A16-A19.
8/29
M36L0Rx0x0UL3
Figure 3.
Description
TFBGA56 package connections (top view through package)
9/29
Description
M36L0Rx0x0UL3
TFBGA88 package connections (top view through package)
Figure 4.
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
NC
NC
NC
NC
NC
NC
DU
A21
DU
DU
NC
NC
NC
NC
A16
NC
NC
A18
A19
NC
NC
NC
V
V
NC
K
V
SS
SS
DDF
LB
P
NC
NC
A17
NC
V
W
P
E
P
NC
PPF
WP
L
A20
NC
NC
F
NC
UB
P
RP
W
F
NC
F
G
H
J
ADQ8
ADQ0
ADQ2
ADQ1
ADQ9
DU
ADQ10
ADQ3
ADQ11
NC
ADQ5
ADQ12
ADQ4
ADQ13
ADQ14
ADQ6
NC
WAIT
ADQ7
ADQ15
G
P
NC
G
F
V
DDQF
E
F
K
L
DU
V
V
CR
DDP
DDQF
P
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
Ai12838b
10/29
M36L0Rx0x0UL3
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram - TFBGA56 package and Table 2: Signal names for a brief
overview of the signals connected to this device.
2.1
Signals common to both packages
2.1.1
Address inputs (ADQ0-ADQ15 and A16-A23)
ADQ0-ADQ15 and A16-A20 (for the M36L0R7050UL3 and M36L0R8050UL3) or A16-A21
(for the M36L0R7060UL3 and M36L0R8060UL3) are common to the flash memory and
PSRAM components.
In the flash memory, the address inputs select the cells in the array to access during bus
read operations. During bus write operations they control the commands sent to the
command interface of the program/erase controller.
In the PSRAM, the address inputs A16-A20 (/A21) are used in conjunction with ADQ0 to
ADQ15 to select the cells in the memory array that are accessed during read and write
operations.
2.1.2
2.1.3
Data inputs/outputs (ADQ0-ADQ15)
The data inputs/outputs output the data stored at the selected address during a bus read
operation or input a command or the data to be programmed during a bus write operation.
Latch Enable (L)
The Latch Enable input is common to the flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KM048AA or M69KM096AA for the PSRAM and
M58LRxxxKCD for the flash memory.
2.1.4
2.1.5
Clock (K)
The Clock input is common to the flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxKCD
for the flash memory.
Wait (WAIT)
The Wait output is common to the flash memory and PSRAM components.
For details of how the WAIT signal behaves, please refer to the datasheets of the respective
memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxKCD
for the flash memory.
11/29
Signal descriptions
M36L0Rx0x0UL3
2.1.6
Flash memory Chip Enable (E )
F
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active
IL
IH
mode. When Chip Enable is at V the memory is deselected, the outputs are high
IH
impedance, and the power consumption is reduced to the standby level.
It is not allowed to set both E and E to V at the same time.
F
P
IL
2.1.7
2.1.8
Flash memory Write Protect (WP )
F
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is at V , the lock-down is enabled and the protection status of the locked-
IL
down blocks cannot be changed. When Write Protect is at V , the lock-down is disabled
and the locked-down blocks can be locked or unlocked (refer to the M58LRxxxKCD
datasheet).
IH
Flash memory Reset (RP )
F
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the reset supply current I
. Refer to the M58LRxxxKCD datasheet for the
DD2
value of I
After Reset all blocks are in the locked state and the Configuration Register is
DD2.
reset. When Reset is at V the device is in normal operation. Exiting reset mode the device
IH
enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is
required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied
to V
(refer to the M58LRxxxKCD datasheet).
RPH
2.1.9
PSRAM Chip Enable (E )
P
Chip Enable, E , activates the device when driven Low (asserted). When de-asserted (V ),
P
IH
the device is disabled and goes automatically in low-power standby mode or deep power-
down mode, according to the Refresh Configuration Register (RCR) settings.
It is not allowed to set both E and E to V at the same time.
F
P
IL
2.1.10
2.1.11
PSRAM Upper Byte Enable (UB )
P
The Upper Byte Enable, UB , gates the data on the upper byte of the address inputs/data
P
inputs/outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
PSRAM Lower Byte Enable (LB )
P
The Lower Byte Enable, LB , gates the data on the lower byte of the address inputs/data
P
input/outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB and UB are disabled (High), the device disables the data bus from receiving or
P
P
transmitting data. Although the device seems to be deselected, it remains in an active mode
as long as E remains Low.
P
12/29
M36L0Rx0x0UL3
Signal descriptions
2.1.12
PSRAM Configuration Register Enable (CR )
P
When this signal is driven High, V , bus read or write operations access either the value of
IH
the RCR or the Bus Configuration Register (BCR) according to the value of A19.
2.1.13
V
flash memory program supply voltage
PPF
V
is both a control input and a power supply pin. The two functions are selected by the
PPF
voltage range applied to the pin.
If V is kept in a low voltage range (0 V to V
) V is seen as a control input. In this
PPF
PPF
DDQF
case a voltage lower than V
gives absolute protection against program or erase, while
PPLK
V
in the V
range enables these functions (see the M58LRxxxKCD datasheet for the
PPF
PP1
relevant values). V
is only sampled at the beginning of a program or erase; a change in
PPF
its value after the operation has started does not have any effect and program or erase
operations continue.
If V
is in the range of V
it acts as a power supply pin. In this condition V
must be
PPF
PPH
PPF
stable until the program/erase algorithm is completed.
2.1.14
V
ground
SS
V
ground is the common flash memory and PSRAM ground. It is the reference for the
SS
core supplies. It must be connected to the system ground.
2.1.15
V
ground
SSQ
V
ground is the reference for the input/output circuitry driven by V
. V
must be
SSQ
DDQF SSQ
connected to V
.
SS
Note:
Each device in a system should have V , V
and V decoupled with a 0.1 µF
DDF DDQF PP
ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
should be as close as possible to the package). See Figure 8: AC measurement load circuit.
The PCB track widths should be sufficient to carry the required V program and erase
PP
currents.
2.2
Signals only in TFBGA56 package
2.2.1
Deep power-down (DPD)
The deep power-down input puts the device in deep power-down mode. When the device is
in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the
deep power-down input causes the memory to enter deep power-down mode.
When the device is in deep power-down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPD pin is determined by ECR14. The deep power-down input is active
Low by default.
13/29
Signal descriptions
M36L0Rx0x0UL3
2.2.2
Output Enable (G)
The Output Enable input is common to the Flash memory and PSRAM components. For
details on the Output Enable signal, please refer to the datasheets of the respective memory
components: M69KM024A or M69KM048AB for the PSRAM and M58WR0xxKUL for the
Flash memory.
2.2.3
Write Enable (W)
The Write Enable Input is common to the Flash memory and PSRAM components. For
details on the Write Enable signal, please refer to the datasheets of the respective memory
components: M69KM024A or M69KM048AB for the PSRAM and M58WR0xxKUL for the
Flash memory.
2.2.4
2.2.5
V
supply voltage
DD
V
is common to both Flash memory and PSRAM components and provides the power
DD
supply to the internal core. It is the main power supply for all memory operations (read,
program, and erase).
V
supply voltage
DDQ
V
is common to both Flash memory and PSRAM components and provides the power
DDQ
supply to the I/O pins. It enables all outputs to be powered independently of V . V
can
DD DDQ
be tied to V or use a separate supply.
DD
2.3
Signals only in TFBGA88 package
2.3.1
Flash memory Output Enable (G )
F
The Output Enable input controls data outputs during the bus read operation of the flash
memory.
2.3.2
Flash memory Write Enable (W )
F
The Write Enable input controls the bus write operation of the flash memory’s command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
2.3.3
2.3.4
PSRAM Output Enable (G )
P
When held Low, V , the Output Enable, G , enables the bus read operations of the
IL
P
memory.
PSRAM Write Enable (W )
P
Write Enable, W , controls the bus write operation of the memory. When asserted (V ), the
P
IL
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
14/29
M36L0Rx0x0UL3
Signal descriptions
2.3.5
V
flash memory supply voltage
DDF
V
provides the power supply to the internal core of the flash memory. It is the main
DDF
power supply for all flash memory operations (read, program and erase).
2.3.6
V
PSRAM supply voltage
CCP
The V
supply voltage is the core supply voltage.
CCP
15/29
Functional description
M36L0Rx0x0UL3
3
Functional description
The PSRAM and flash memory components have separate power supplies but share the
same grounds. They are distinguished by two Chip Enable inputs: E for the flash memory
F
and E for the PSRAM.
P
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is simultaneous read operations on one of the flash
memory and the PSRAM components which would result in a data bus contention.
Therefore, it is recommended to put the other devices in the high impedance state when
reading the selected device.
Figure 5.
Functional block diagram - TFBGA56 package
V
PPF
A21-A22(1) or A21- A23(2)
or A22(3) or A22-A23(4)
DPD
E
F
128-Mbit or
256-Mbit
flash
RP
F
WP
F
memory
WAIT
K
L
W
V
V
DDQ
DD
V
SS
G
A16- A20(1,2) or
A16-A21(3,4)
ADQ0-ADQ15
E
P
32-Mbit or
64-Mbit
V
SSQ
PSRAM
CR
P
UB
LB
P
P
AI14407
1. Address inputs corresponding to the M36L0R7050UL3 devices.
2. Address inputs corresponding to the M36L0R8050UL3 devices.
3. Address input corresponding to the M36L0R7060UL3 devices.
4. Address input corresponding to the M36L0R8060UL3 devices.
16/29
M36L0Rx0x0UL3
Figure 6.
Functional description
Functional block diagram - TFBGA88 package
V
V
V
PPF
DDQF
DDF
A21-A22(1) or A21- A23(2)
or A22(3) or A22-A23(4)
E
F
W
F
128- or 256-Mbit
flash
RP
F
WP
Memory
F
G
F
WAIT
K
L
V
V
CCP
SS
A16- A20(1,2) or
A16-A21(3,4)
ADQ0-ADQ15
E
P
32- or 64-Mbit
PSRAM
G
P
W
P
CR
P
UB
LB
P
P
AI12339d
1. Address inputs corresponding to the M36L0R7050UL3 devices.
2. Address inputs corresponding to the M36L0R8050UL3 devices.
3. Address input corresponding to the M36L0R7060UL3 devices.
4. Address input corresponding to the M36L0R8060UL3 devices.
17/29
Functional description
Table 3.
M36L0Rx0x0UL3
TFBGA56 package operating modes - standard asynchronous operation
WAIT
(3)
ADQ0- ADQ8
ADQ7 -ADQ15
Operation(1)(2)
UBP LBP CRP EP
EF
RPF
G
W
L
Bus read
Bus write
VIL
VIL
VIH
VIH
VIL VIH VIH
Data output
Data input
VIH VIL VIH Any PSRAM mode is
allowed.
Data output or
Hi-Z(4)
Address latch
VIL
VIH
VIH
X
VIL
Output disable
Standby
VIL
VIH
X
VIH
VIH
VIL
VIH VIH VIH
Hi-Z
Hi-Z
Hi-Z
Any PSRAM mode is
allowed.
Hi-Z
Hi-Z
X
X
X
X
X
X
Reset
Address in/ data
out valid
VIL VIL VIL
Word read
Word write
VIL VIH
VIH VIL
The Flash memory
must be disabled.
\_/
Address in/ data
in valid
VIL VIL VIL
VIL
Output
disable/no
operation
VIH
VIL
VIH
X
X
X
High-Z
Any Flash memory
mode is allowed.
Deep power-
down(5)
VIH
VIH
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
Standby
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = ‘don’t care’
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. See the M58WR0xxKUL datasheet.
5. The device enters deep power-down mode by driving the Chip Enable signal, E, from Low to High, with bit
4 of the RCR set to “0”. The device remains in deep power-down mode until E goes Low again and is held
Low for tELEH(DP)
.
18/29
M36L0Rx0x0UL3
Functional description
Table 4.
TFBGA88 package operating modes - standard asynchronous operation
Other
A19 A18 Address
WAIT
(3)
ADQ0- ADQ8-
ADQ7 ADQ15
Operation(1)(2)
EP WP GP UBP LBP CRP
EF GF WF RPF
L
inputs
Bus Read
Bus Write
VIL VIL VIH VIH
VIL VIH VIL VIH
VIH
VIH
VIL
Data output
Data input
The PSRAM must be disabled.
Address Latch VIL VIH
Output
Disable
Standby
Reset
X
VIH
Address input
VIL VIH VIH VIH
VIH
Hi-Z
Any PSRAM mode is allowed.
VIH
X
X
X
X
X
VIH Hi-Z
VIL Hi-Z
X
X
Hi-Z
Hi-Z
Address In/ Data
Out Valid
VIH VIL VIL VIL VIL
VIL VIH VIL VIL VIL
Word Read
Word Write
Address In Valid
Address In Valid
Address In/ Data In
Valid
\_/
Read
00(RCR)
Configuration
Register (CR
controlled
method)(4)
Address In/ BCR,
RCR or DIDR
Content Valid
The flash memory must
be disabled.
VIH VIL VIL VIL
10(BCR)
X
X1(DIDR)
VIL
VIH
Program
00(RCR)
BCR/
RCR
Data
Configuration
Register (CR
controlled)(5)
VIL
VIL VIH
10(BCR)
X
X
X
X
Address In Valid
High-Z
(6)
Output
Disable/No
operation
VIH
VIL
X
X
X
X
Any flash memory mode
is allowed.
X
Deep Power-
down(7)
VIH
VIH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
VIL
Standby
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = ‘don’t care’
3. In the flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. Operating mode available in the M36L0R7060UL3 and M36L0R8050UL3 only (see the M69KM096AA datasheet).
5. BCR and RCR only.
6. A18 and A19 are used to select the BCR, the RCR or the DIDR.
7. The device enters Deep Power-down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR
set to ‘0’. The device remains in Deep Power-down mode until E goes Low again and is held Low for tELEH(DP)
.
19/29
Maximum ratings
M36L0Rx0x0UL3
4
Maximum ratings
Stressing the device above the rating listed in Table 5: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TA
Ambient operating temperature
Temperature under bias
Storage temperature
–25
–25
–55
–0.2
–0.2
–0.2
85
85
°C
°C
TBIAS
TSTG
VIO
125
2.45
2.45
10
°C
Input or output voltage
V
VDDF, VDDQF, VCCP Core and input/output supply voltages
V
VPPF
IO
Flash program voltage
Output short circuit current
Time for VPPF at VPPFH
V
100
100
mA
hours
tVPPFH
20/29
M36L0Rx0x0UL3
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables are
derived from tests performed under the measurement conditions summarized in Table 6:
Operating and AC measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 6.
Operating and AC measurement conditions
Flash memory
Parameter
PSRAM
Unit
Min
Max
Min
Max
VDD supply voltage
VDDQ supply voltage
1.7
1.7
1.95
1.95
–
–
–
–
V
V
VPPF supply voltage (factory environment)
8.5
9.5
–
–
V
VPPF supply voltage (application environment)
Ambient operating temperature
Load capacitance (CL)
–0.4
–25
VDDQ +0.4
85
–
–
V
–25
85
°C
pF
kΩ
ns
V
30
30
Output circuit resistors (R1, R2)
Input rise and fall times
16.7
16.7
5
2
Input pulse voltages
0 to VDDQ
VDDQ/2
0 to VDD/2
VDD/2
Input and output timing ref. voltages
V
Figure 7.
AC measurement I/O waveform
V
DDQF
V
/2
DDQF
0 V
AI06161b
21/29
DC and AC parameters
Figure 8.
M36L0Rx0x0UL3
AC measurement load circuit
V
DDQF
V
V
DDQF
DDF
R
1
DEVICE
UNDER
TEST
C
L
0.1 µF
R
2
0.1 µF
C includes JIG capacitance
L
AI08364c
Table 7.
Symbol
Device capacitance
Parameter
Test Condition
Min
Max(1)
Unit
CIN
Input capacitance
Output capacitance
VIN = 0 V
14
18
pF
pF
COUT
VOUT = 0 V
1. Sampled only, not 100% tested.
Please refer to the M58LRxxxKCD and M69KM048AA or M69KM096AA datasheets for
further DC and AC characteristics values and illustrations.
22/29
M36L0Rx0x0UL3
Package mechanical
6
Package mechanical
To meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages, which have a lead-free second-level interconnect. In compliance with JEDEC
Standard JESD97, the category of second-level interconnect is marked on the package and
on the inner box label.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK specifications are available at: www.numonyx.com.
Figure 9.
TFBGA56 8 x 6 mm, 8 x 6 ball array - 0.50 mm pitch, package outline
D2
D1
A
SE
b
E
E1
FE
E2
BALL "A1"
FE1
e
A1
FD1
FD
SD
e
A2
ddd
JV_ME
1. Drawing is not to scale.
23/29
Package mechanical
Table 8.
M36L0Rx0x0UL3
Stacked TFBGA56 8 x 6 mm - 8 x 6 active ball array, 0.50 mm pitch,
package mechanical data
Millimeters
Inches
Min
Symbol
Typ
Min
Max
Typ
Max
A
A1
A2
b
1.20
0.047
0.15
0.006
0.79
0.30
8.00
4.50
6.50
0.031
0.012
0.315
0.177
0.256
0.25
7.90
0.35
8.10
0.010
0.311
0.014
0.319
D
D1
D2
ddd
E
0.08
6.10
0.003
0.240
6.00
2.50
4.50
0.50
1.75
0.75
1.75
0.75
5.90
–
0.236
0.098
0.177
0.020
0.069
0.030
0.069
0.030
0.232
–
E1
E2
e
–
–
FD
FD1
FE
FE1
24/29
M36L0Rx0x0UL3
Package mechanical
Figure 10. Stacked TFBGA88 8 x 10 mm, 8 x 10 active ball array - 0.8 mm pitch,
package outline
D
D1
e
b
SE
E
E2 E1
BALL "A1"
ddd
FE FE1
A
FD
SD
A2
A1
BGA-Z42
1. Drawing is not to scale.
25/29
Package mechanical
Table 9.
M36L0Rx0x0UL3
TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch, package
mechanical data
millimeters
inches
Min
Symbol
Typ
Min
Max
Typ
Max
A
A1
A2
b
1.200
0.047
0.200
0.008
0.850
0.350
8.000
5.600
0.033
0.014
0.315
0.220
0.300
7.900
0.400
8.100
0.012
0.311
0.016
0.319
D
D1
ddd
E
0.100
0.004
0.398
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.394
0.283
0.346
0.031
0.047
0.055
0.024
0.016
0.016
0.390
–
E1
E2
e
–
–
FD
FE
FE1
SD
SE
26/29
M36L0Rx0x0UL3
Part numbering
7
Part numbering
Table 10. Ordering information scheme
Example:
M36 L 0 R 8 0
5
0 L 3 ZS
F
Device type
M36 = multichip package (flash + RAM)
Flash 1 architecture
L = multilevel, multiple bank, burst mode
Flash 2 architecture
0 = no die
Operating voltage
R = VDDF = VDDP = VDDQF = 1.7 V to 1.95 V
Flash 1 density
7 = 128 Mbit
8 = 256 Mbit
Flash 2 density
0 = no die
RAM 1 density
5 = 32 Mbit
6 = 64 Mbit
RAM 2 density
0 = no die
Parameter block location
U = top boot block flash
L = bottom boot block flash
Product version
3 = 65 nm flash technology and multilevel design, 70 ns speed class;
RAM, 70 ns speed mux I/O
Package
ZAM = stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch
ZS = stacked TFBGA56 8 x 6 mm - 8 x 6 active ball array, 0.5 mm pitch
Packing option
E = Ecopack® package, standard packing
F = Ecopack® package, tape and reel packing
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest
Numonyx sales office.
27/29
Revision history
M36L0Rx0x0UL3
8
Revision history
Table 11. Document revision history
Date
Revision
Changes
07-Aug-2007
1
Initial release.
Added 256-Mbit density and all associated data throughout the
document. Applied Numonyx branding.
28-Mar-2008
2
28/29
M36L0Rx0x0UL3
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.
29/29
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