M36LLR8760T1ZAQE [NUMONYX]
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-88;型号: | M36LLR8760T1ZAQE |
厂家: | NUMONYX B.V |
描述: | SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-88 静态存储器 内存集成电路 |
文件: | 总19页 (文件大小:427K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M36LLR8760T1, M36LLR8760D1
M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY
■
MULTI-CHIP PACKAGE
Figure 1. Package
–
–
–
1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-Level, Burst) Flash Memory
FBGA
1 die of 64 Mbit (4Mb x16) Pseudo SRAM
■
■
SUPPLY VOLTAGE
–
V
1.95V
= V
= V
= V
= 1.7 to
DDQF
DDF1
DDF2
CCP
LFBGA88 (ZAQ)
8 x 10mm
–
V
= 9V for fast program (12V tolerant)
PPF
ELECTRONIC SIGNATURE
–
–
Manufacturer Code: 20h
Top Configuration (Top + Top)
M36LLR8760T1: 880Dh + 88C4h
Mixed Configuration (Bottom + Top)
M36LLR8760D1: 880Eh + 88C4h
Mixed Configuration (Top + Bottom)
M36LLR8760M1: 880Dh + 88C5h
■
■
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
–
–
–
■
DUAL OPERATIONS
–
program/erase in one Bank while read in
others
–
No delay between read and write
operations
Bottom Configuration (Bottom + Bottom)
M36LLR8760B1: 880Eh + 88C5h
■
■
SECURITY
■
PACKAGE
–
–
–
64 bit unique device number
2112 bit user programmable OTP Cells
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
BLOCK LOCKING
–
–
–
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
FLASH MEMORIES
■
SYNCHRONOUS / ASYNCHRONOUS READ
–
–
WP for Block Lock-Down
Absolute Write Protection with V
–
–
–
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
F
= V
SS
PPF
PSRAM
■
■
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
–
■
■
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
–
–
10µs typical Word program time using
Buffer Enhanced Factory Program
command
Page Size: 16 words
Subsequent read within page: 20ns
■
MEMORY ORGANIZATION
■
■
LOW POWER FEATURES
–
Multiple Bank Memory Array:
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
–
Temperature Compensated Refresh
(TCR)
–
–
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
–
Parameter Blocks (at Top or Bottom)
SYNCHRONOUS BURST READ/WRITE
July 2005
1/19
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable Inputs (E , E ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F1
F2
Flash Output Enable Inputs (G , G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F1
F2
Flash Write Enable (W ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
Flash Write Protect (WP ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
Flash Reset (RP ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
F
PSRAM Chip Enable input (E ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
PSRAM Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
PSRAM Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
PSRAM Upper Byte Enable (UB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
PSRAM Lower Byte Enable (LB ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
PSRAM Configuration Register Enable (CR ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
P
V
V
V
V
V
/V
Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDF1 DDF2
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CCP
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDQF
Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PPF
Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Flash 1 DC Characteristics - Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Flash 2 DC Characteristics - Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Flash 1 and Flash 2 DC Characteristics - Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15
Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SUMMARY DESCRIPTION
The
M36LLR8760T1,
M36LLR8760D1,
Recommended operating conditions do not allow
more than one memory to be active at the same
time.
M36LLR8760M1 and M36LLR8760B1 combine
three memory devices in a Multi-Chip Package:
■
■
■
a 256-Mbit, Multiple Bank Flash memory, the
M30L0R8000(T/B)0 (Flash 1)
a 128-Mbit, Multiple Bank Flash memory, the
M58LR128GT/B (Flash 2)
The memories are offered in a Stacked LFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
a 64-Mbit PseudoSRAM, the M69KB096AA.
For detailed information on how to use the memo-
ry components, refer to the M30L0R8000(T/B)0,
M58LR128GT/B and M69KB096AA datasheets
which are available from your local STMicroelec-
tronics distributor and should be read in conjunc-
tion with the M36LLR8760x1 datasheet.
The memory is supplied with all the bits erased
(set to ‘1’).
What differs between the M36LLR8760T1,
M36LLR8760D1 and M36LLR8760B1 is the con-
figuration of the two Flash memories:
■
in the M36LLR8760T1, Flash 1 and Flash 2
both have a Top Configuration (Parameter
Blocks located at the top of the address
space).
■
in the M36LLR8760D1, Flash 1 has a Bottom
Configuration (Parameter Blocks at the
bottom of the address space) and Flash 2 has
a Top Configuration.
■
■
In the M36LLR8760M1, Flash 1 has a Top
Configuration and Flash 2 has a Bottom
Configuration.
In the M36LLR8760B1, both Flash 1 and
Flash 2 have a Bottom Configuration.
4/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 2. Logic Diagram
Table 1. Signal Names
(1)
Address Inputs
A0-A23
V
V
PPF
DDQF
V
V
V
DQ0-DQ15 Common Data Input/Output
DDF1
DDF2
CCP
Common Flash and PSRAM Latch
Enable Input
24
16
DQ0-DQ15
L
A0-A23
K
Common Flash and PSRAM Burst Clock
E
F1
Wait Data in Burst Mode for both Flash
memories and PSRAM
WAIT
G
F1
E
F2
V
Flash 1 Power Supply
DDF1
G
F2
V
WAIT
Flash 2 Power Supply
DDF2
W
F
M36LLR8760T1
M36LLR8760D1
M36LLR8760M1
M36LLR8760B1
V
Common Flash Supply for I/O Buffers
DDQF
RP
F
WP
Common Flash Optional Supply Voltage
for Fast Program & Erase
F
V
PPF
L
V
V
Common, Ground
SS
K
E
PSRAM Power Supply
P
CCP
G
P
NC
DU
Not Connected Internally
Do Not Use as Internally Connected
W
P
CR
P
Flash Memory Signals
UB
LB
P
E
Flash 1 Chip Enable Input
Flash 1 Output Enable Input
Flash 2 Chip Enable Input
Flash 2 Output Enable Input
F1
P
G
E
F1
V
F2
SS
AI10908b
G
F2
Common Flash Memory Write Enable
Input
W
F
RP
Common Flash Memory Reset input
F
Common Flash Memory Write Protect
Input
WP
F
PSRAM Signals
E
Chip Enable Input
P
G
Output Enable Input
P
W
Write Enable Input
P
CR
UB
Configuration Register Enable Input
Upper Byte Enable Input
Lower Byte Enable Input
P
P
LB
P
Note: 1. A22 is an Address Input for the two Flash memories only.
A23 is for the 256Mb Flash memory component only.
5/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 3. LFBGA Connections (Top view through package)
A
B
C
D
E
F
DU
A4
A5
A3
A2
A1
A0
DU
A21
A22
A9
DU
DU
A11
A12
A13
A15
A16
A18
A19
A23
NC
V
V
V
V
SS
DDF2
DDF1
LB
P
NC
K
SS
A17
A7
V
W
P
E
P
PPF
NC
WP
L
A20
A8
A10
A14
WAIT
DQ7
DQ15
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
DU
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
E
F2
G
P
G
F2
NC
G
V
DDQF
F1
E
K
L
DU
V
V
V
CR
F1
CCP
DDF2
DDQF
P
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF1
SS
SS
SS
SS
DU
DU
M
DU
DU
AI10503b
Note: A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
6/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Wait (WAIT). WAIT is an output pin common to
the Flash memory and PSRAM components. How-
ever the WAIT signal does not behave in the same
way for the PSRAM and the Flash memories.
Address Inputs (A0-A23). Addresses A0-A21
are common inputs for the Flash memory and
PSRAM components. A22 is common to the two
Flash memory components whereas A23 is an ad-
dress input for the 256 Mbit Flash memory compo-
nent only.
For details of how it behaves, please refer to the
M69KB096AA datasheet for the PSRAM and to
the M30L0R8000T/B0 and M58LR128GT/B
datasheets for Flash 1 and Flash 2, respectively.
Flash Chip Enable Inputs (E , E ). The
F1
F2
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the
internal state machine. The Flash memories are
Flash Chip Enable inputs activate the control logic,
input buffers, decoders and sense amplifiers of the
Flash memory component selected (E is used to
F1
select Flash 1, E is used to select Flash 2).
F2
When Chip Enable is Low, V , and Reset is High,
IL
accessed through the Chip Enable signal (E ) and
V , the device is in active mode. When Chip En-
IH
F
through the Write Enable signal (W ), while the
PSRAM is accessed through the Chip Enable sig-
able is at V the corresponding Flash memory are
F
IH
deselected, the outputs are high impedance and
the power consumption is reduced to the standby
level.
nal (E ) and the Write Enable signal (W ).
P
P
It is not allowed to have E Low, and E Low at the
F
P
same time.
It is not allowed to have E at V , E at V and
F1 IL F2 IL
E at V at the same time. Only one memory com-
P
IL
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
ponent can be enabled at a time.
Flash Output Enable Inputs (G , G ). The
F1
F2
Output Enable pins control the data outputs during
Flash memory Bus Read operations.
For the PSRAM component, the upper Byte Data
Inputs/Outputs (DQ8-DQ15) carry the data to or
from the upper part of the selected address when
Flash Write Enable (W ). The Write Enable
F
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Upper Byte Enable (UB ) is driven Low. The lower
P
Byte Data Inputs/Outputs (DQ0-DQ7) carry the
data to or from the lower part of the selected ad-
dress when Lower Byte Enable (LB ) is driven
P
Flash Write Protect (WP ). Write Protect is an
input that gives an additional hardware protection
F
Low. When both UB and LB are disabled, the
P
P
Data Inputs/ Outputs are high impedance.
for each block. When Write Protect is Low, V ,
IL
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
Latch Enable (L). The Latch Enable pin is com-
mon to the Flash memory and PSRAM compo-
nents.
For details of how the Latch Enable signal be-
haves, please refer to the datasheets of the re-
spective memory components: M69KB096AA for
the PSRAM and M30L0R8000(T/B)0 and
M58LR128GT/B for Flash 1 and Flash 2, respec-
tively.
When Write Protect is at High, V , Lock-Down is
IH
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30L0R8000(T/B)0 and M58LR128GT/B
datasheets).
Flash Reset (RP ). The Reset input provides a
F
hardware reset of the Flash memories. When Re-
set is at V , the memory is in Reset mode: the out-
puts are high impedance and the current
consumption is reduced to the Reset Supply Cur-
IL
Clock (K). The Clock input pin is common to the
Flash memory and PSRAM components.
For details of how the Clock signal behaves,
please refer to the datasheets of the respective
memory components: M69KB096AA for the
rent I
. Refer to Table 6., Flash 1 DC Character-
DD2
istics - Currents, for the value of I
. After Reset
DD2
all blocks are in the Locked state and the Configu-
PSRAM
and
M30L0R8000(T/B)0
and
ration Register is reset. When Reset is at V , the
IH
M58LR128GT/B for Flash 1 and Flash 2, respec-
tively.
device is in normal operation. Exiting Reset mode
the device enters Asynchronous Read mode, but
7/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
a negative transition of Chip Enable or Latch En-
able is required to ensure valid data outputs.
cores of Flash 1 and Flash 2, respectively. It is the
main power supply for all Flash memory opera-
tions (Read, Program and Erase).
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
(refer to Table 8., Flash 1 and Flash 2 DC Charac-
teristics - Voltages).
RPH
V
Supply Voltage. V
provides the power
CCP
CCP
supply to the internal core of the PSRAM device. It
is the main power supply for all PSRAM opera-
tions.
PSRAM Chip Enable input (E ). The Chip En-
P
able input activates the PSRAM when driven Low
V
Supply Voltage. V
provides the
DDQF
DDQF
(asserted). When deasserted (V ), the device is
IH
power supply for the Flash memory. This allows all
Outputs to be powered independently of the Flash
memory and SRAM core power supplies, V
disabled, and goes automatically in low-power
Standby mode or Deep Power-down mode.
DDF
and V
.
CCP
PSRAM Write Enable (W ). Write Enable, W ,
P
P
controls the Bus Write operation of the PSRAM.
V
Program Supply Voltage. V
is both a
PPF
PPF
When asserted (V ), the device is in Write mode
IL
control input and a power supply pin for the Flash
memories. The two functions are selected by the
voltage range applied to the pin.
and Write operations can be performed either to
the configuration registers or to the memory array.
PSRAM Output Enable (G ). Output
G , provides a high speed tri-state control, allow-
P
Enable,
If V
is kept in a low voltage range (0V to V
is seen as a control input. In this case a volt-
)
DDQF
P
PPF
V
PPF
ing fast read/write cycles to be achieved with the
common I/O data bus.
age lower than V
against Program or Erase, while V
gives an absolute protection
PPLK
> V
en-
PPF
PP1
ables these functions (see Tables 6 and 8, DC
Characteristics for the relevant values). V is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
PSRAM Upper Byte Enable (UB ). The Upper
P
PPF
Byte En-able, UB , gates the data on the Upper
P
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
If V
is in the range of V
it acts as a power
PPH
PPF
PSRAM Lower Byte Enable (LB ). The Lower
P
supply pin. In this condition V
until the Program/Erase algorithm is completed.
must be stable
PPF
Byte Enable, LB , gates the data on the Lower
P
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
V
Ground. V is the common ground refer-
SS
SS
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips. It must
be connected to the system ground.
Note: Each Flash memory device in a system
should have their supply voltage (V
If both LB and UB are disabled (High) during an
P
P
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
) and
DDF
mode as long as E remains Low.
P
the program supply voltage V
decoupled
PPF
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance ca-
pacitors should be as close as possible to the
package). See Figure 6., AC Measurement
Load Circuit. The PCB track widths should be
PSRAM Configuration Register Enable (CR ).
P
When this signal is driven High, V , Write opera-
IH
tions load either the value of the Refresh Configu-
ration Register (RCR) or the Bus configuration
register (BCR).
sufficient to carry the required V
and erase currents.
program
PPF
V
V
/V
Supply Voltages. V
and
DDF1 DDF2
DDF1
provide the power supply to the internal
DDF2
8/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
FUNCTIONAL DESCRIPTION
The PSRAM and Flash memory components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
most common example is simultaneous read oper-
ations on one of the Flash memories and the
PSRAM which would result in a data bus conten-
tion. Therefore it is recommended to put the other
devices in the high impedance state when reading
the selected device.
able inputs: E and E for Flash 1 and Flash 2,
F1
F2
respectively, and E for the PSRAM.
P
Recommended operating conditions do not allow
more than one device to be active at a time. The
Figure 4. Functional Block Diagram
V
DDF1
A23
Flash 1
E
F1
F1
G
256 Mbit
Flash
Memory
A22
RP
F
V
V
PPF
V
DDF2
DDQF
WP
F
W
F
A0-A21
Flash 2
E
F2
F2
DQ0-DQ15
G
WAIT
128 Mbit
Flash
L
Memory
K
V
SS
V
CCP
E
P
G
64 Mbit
PSRAM
P
W
P
CR
P
UB
LB
P
P
AI10909b
9/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 2. Main Operating Modes
(5)
(5)
(4)
L
RP
E
CR
G
W
LB ,UB
P P
W
Operation
Flash Read
Flash Write
DQ15-DQ0
G
E
WAIT
F
F
F
P
P
P
P
F
F
F
(2)
V
V
V
IH
V
IH
Flash Data Out
V
IL
IL
IL
IL
PSRAM must be disabled.
(2)
V
V
V
IL
V
IH
Flash Data In
IH
V
IL
Only one Flash memory can be
enabled at a time.
Flash Data Out
Flash Address
Latch
V
IL
V
IH
V
IL
V
IH
X
(3)
or Hi-Z
Flash Output
Disable
V
V
V
V
V
V
X
Hi-Z
IL
IH
IH
IH
Any PSRAM mode is allowed.
Both Flash memories must be
disabled.
Flash Standby
Flash Reset
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
IH
V
X
X
X
IL
PSRAM data
out
V
V
V
V
V
V
V
V
PSRAM Read
PSRAM Write
IL
IL
IL
IL
IH
IL
V
V
X
PSRAM data in
IL
IL
IL
IL
Both Flash memories must be disabled
PSRAM Write
Configuration
Register
V
IL
V
IH
V
X
PSRAM data in
IH
PSRAM
Standby
V
V
X
X
X
X
Hi-Z
Hi-Z
IH
IH
IL
Any Flash memory mode is allowed. Only
one Flash memory can be enabled at a time
PSRAM Deep
Power-Down
V
X
X
X
Note: 1. X = Don't care.
2. L can be tied to V if the valid address has been previously latched.
F
IH
3. Depends on G .
F
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000(T/B)0 and
M30L0R8000(T/B)0 datasheets for details.
5. E is either E or E , and G is either G or G according to the Flash memory enabled. Only one Flash memory can be enabled
F
F1
F2
F
F1
F2
at a time.
10/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–25
–25
–65
Max
85
T
Ambient Operating Temperature
Temperature Under Bias
°C
°C
°C
°C
V
A
T
85
BIAS
T
Storage Temperature
125
STG
(1)
T
Lead Temperature During Soldering
Input or Output Voltage
LEAD
V
IO
–0.5
–0.2
–0.2
3.6
V
V
, V
DDF1
,
DDF2
Core and Input/Output Supply Voltages
2.45
V
, V
DDQF CCP
V
PPF
Flash Program Voltage
12.6
100
100
V
I
O
Output Short Circuit Current
mA
t
Time for V
at V
PPF PPFH
hours
VPPFH
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Flash Memories
PSRAM
Parameter
Unit
Min
1.7
–
Max
1.95
–
Min
–
Max
–
V
V
V
/V
Supply Voltages
V
V
V
V
DDF1 DDF2
Supply Voltage
1.7
–
1.95
–
CCP
Supply Voltage
1.7
8.5
1.95
9.5
DDQF
V
V
Supply Voltage (Factory environment)
Supply Voltage (Application environment)
–
–
PPF
PPF
V
+0.4
–0.4
–25
–
–
V
°C
pF
kΩ
ns
V
DDQF
Ambient Operating Temperature
85
–25
85
Load Capacitance (C )
30
16.7
30
L
Output Circuit Resistors (R , R )
16.7
1
2
Input Rise and Fall Times
Input Pulse Voltages
5
0 to V
0 to V
DDQF
DDQF
V
DDQF
/2
V
/2
DDQF
Input and Output Timing Ref. Voltages
V
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VDDQF
V
DDQF
VDDF
VDDQF
V
/2
DDQF
R1
0V
DEVICE
UNDER
TEST
AI06161b
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364c
Table 5. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
14
Unit
C
V
IN
= 0V
= 0V
Input Capacitance
Output Capacitance
pF
pF
IN
C
V
OUT
18
OUT
Note: Sampled only, not 100% tested.
12/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 6. Flash 1 DC Characteristics - Currents
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Typ
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
IN
DDQF
I
LO
0V ≤ V ≤ V
OUT DDQF
±1
µA
Supply Current
Asynchronous Read (f=5MHz)
E
F1
= V , G = V
IL F1 IH
13
15
mA
4 Word
8 Word
16
18
23
25
18
20
25
27
mA
mA
mA
mA
I
DD1
Supply Current
Synchronous Read (f=54MHz)
16 Word
Continuous
Supply Current
(Reset)
I
RP = V ± 0.2V
50
110
µA
DD2
F
SS
I
I
E
E
= V
± 0.2V
Supply Current (Standby)
50
50
8
110
110
20
µA
µA
DD3
F1
DDF1
= V , G = V
IH
Supply Current (Automatic Standby)
DD4
F1
IL
F1
V
PPF
= V
PPH
mA
mA
mA
mA
Supply Current (Program)
Supply Current (Erase)
V
= V
DDF1
10
8
25
PPF
(1)
I
DD5
V
PPF
= V
= V
20
PPH
V
10
25
PPF
DDF1
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
40
mA
Supply Current
(Dual Operations)
(1,2)
(1)
I
DD6
Program/Erase in one Bank,
Synchronous Read (Continuous
f=54MHz) in another Bank
35
50
52
mA
µA
Supply Current Program/ Erase
Suspended (Standby)
E
F1
= V
± 0.2V
110
I
DDF1
DD7
V
= V
2
5
5
5
5
5
5
mA
µA
mA
µA
µA
µA
PPF
PPH
V
V
Supply Current (Program)
Supply Current (Erase)
PPF
V
= V
DDF1
0.2
2
PPF
(1)
I
PP1
V
= V
= V
PPF
PPF
PPF
PPH
PPF
V
V
V
0.2
0.2
0.2
DDF1
DDF1
I
V
V
Supply Current (Read)
≤ V
≤ V
PP2
PPF
(1)
Supply Current (Standby)
I
PPF
PPF
DDF1
PP3
Note: 1. Sampled only, not 100% tested.
2. V Dual Operation current is the sum of read and program or erase currents.
DDF1
13/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 7. Flash 2 DC Characteristics - Currents
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Typ
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
IN
DDQF
I
LO
0V ≤ V ≤ V
OUT DDQF
±1
µA
Supply Current
Asynchronous Read (f=5MHz)
E = V , G = V
13
15
mA
IL
IH
4 Word
8 Word
16
18
23
25
18
20
25
27
mA
mA
mA
mA
I
DD1
Supply Current
Synchronous Read (f=54MHz)
16 Word
Continuous
Supply Current
(Reset)
I
RP = V ± 0.2V
25
25
70
70
µA
µA
DD2
SS
E = V
± 0.2V
DDQF
I
I
Supply Current (Standby)
DD3
K=V
SS
E = V , G = V
Supply Current (Automatic Standby)
25
8
70
20
25
20
25
µA
mA
mA
mA
mA
DD4
IL
IH
V
= V
PPH
PP
Supply Current (Program)
Supply Current (Erase)
V
= V
= V
10
8
PP
DD
(1)
I
DD5
V
PP
PPH
V
= V
DD
10
PP
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
40
mA
Supply Current
(Dual Operations)
(1,2)
(1)
I
DD6
Program/Erase in one Bank,
Synchronous Read (Continuous
f=54MHz) in another Bank
35
25
52
70
mA
µA
E = V
± 0.2V
Supply Current Program/ Erase
Suspended (Standby)
DDQF
I
I
DD7
K=V
SS
V
= V
2
5
5
5
5
5
5
mA
µA
mA
µA
µA
µA
PP
PPH
V
V
Supply Current (Program)
Supply Current (Erase)
PP
V
= V
0.2
2
PP
DD
(1)
PP1
V
= V
PP
PPH
PP
V
= V
0.2
0.2
0.2
PP
PP
PP
DD
DD
DD
I
V
V
Supply Current (Read)
V
≤ V
≤ V
PP2
PP
(1)
Supply Current (Standby)
V
I
PP
PP3
Note: 1. Sampled only, not 100% tested.
2. V Dual Operation current is the sum of read and program or erase currents.
DDF2
14/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 8. Flash 1 and Flash 2 DC Characteristics - Voltages
Symbol
Parameter
Input Low Voltage
Test Condition
Min
Typ
Max
Unit
V
IL
0
0.4
V
V
V
–
–
V
+
DDQF
0.4
DDQF
0.4
V
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
IH
V
OL
I
= 100µA
0.1
OL
DDQF
0.1
V
OH
I
= –100µA
OH
V
V
Program Voltage-Logic
Program, Erase
Program, Erase
1.1
8.5
1.8
9.0
3.3
9.5
0.4
1
V
V
V
V
V
PP1
PPF
V
PPH
V
Program Voltage Factory
PPF
V
PPLK
Program or Erase Lockout
V Lock Voltage
DDF1/F2
V
LKO
V
RPH
RP pin Extended High Voltage
F
3.3
Table 9. PSRAM DC Characteristics
Symbo
Uni
t
Parameter
l
Test Condition
70ns
70ns
Min.
Typ
Max.
25
Operating Current: Asynchronous Random
Read/Write
(1)
mA
I
CC1
I
CC1P
(1)
Operating Current: Asynchronous Page Read
15
mA
80MHz
66MHz
80MHz
66MHz
80MHz
66MHz
35
30
18
15
35
30
mA
mA
mA
mA
mA
mA
V
=V or V ,
E = V ,
IL
Operating Current:
Initial Access, Burst Read/Write
CC
IH
IL
(1)
I
CC2
I
= 0mA
OUT
Operating Current:
Continuous Burst Read
(1)
I
CC3R
(1
Operating Current:
Continuous Burst Write
I
CC3W
)
V
CC
= V
E = V
or 0V,
CCQ
(2)
V
Standby Current
CC
120
µA
I
SB
IH
I
0V ≤ V ≤ V
IN CC
Input Leakage Current
Output Leakage Current
Deep-Power Down Current
1
1
µA
µA
µA
LI
I
LO
G = V or E = V
IH IH
I
V
= V or V
IN IH IL
10
ZZ
V
+
CCQ
0.2
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.4
V
V
V
V
IH
V
−0.2
0.4
IL
0.8V
CC
V
OH
I
= −0.2mA
OH
Q
V
OL
I
= 0.2mA
0.2V
CCQ
OL
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to
drive the output capacitance expected in the actual system.
2. I (Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temper-
SB
ature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to V
CCQ
or V
.
SS
3. The Operating Temperature is +25°C.
15/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PACKAGE MECHANICAL
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline
D
D1
e
SE
E
E2 E1
b
e
BALL "A1"
ddd
FE1 FE
FD
A
SD
A2
A1
BGA-Z45
Note: Drawing is not to scale.
Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.400
0.0551
0.200
0.0079
1.000
0.350
8.000
5.600
0.0394
0.0138
0.3150
0.2205
0.300
7.900
–
0.400
0.0118
0.3110
–
0.0157
D
8.100
0.3189
D1
ddd
E
–
–
0.100
0.0039
10.000
7.200
8.800
0.800
1.200
1.400
0.400
0.400
0.600
9.900
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0157
0.0157
0.0236
0.3898
0.3976
E1
E2
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
FE1
16/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M36 L
L
R 8
7
6
0 T 1 ZAQ T
Device Type
M36 = Multi-Chip Package (Multiple Flash + RAM)
Flash 1 Architecture
L = Multi-Level, Multiple Bank, Burst mode
Flash 2 Architecture
L = Multi-Level, Multiple Bank, Burst mode
Operating Voltage
R = V
= V
= V
= 1.7 to 1.95V
DDQF
DDF
CCP
Flash 1 Density
8 = 256 Mbits
Flash 2 Density
7 = 128 Mbits
RAM 1 Density
6 = 64 Mbits
RAM 0 Density
0 = No Die
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
D = Mixed (Flash 1 Bottom, Flash 2 Top)
M = Mixed (Flash 1 Top, Flash 2 Bottom)
Product Version
1 = 0.13µm Flash technology (2 Chip Enable inputs, one for each Flash memory), 85ns speed;
0.11µm PSRAM, 70ns speed, burst mode
Package
ZAQ = Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free and RoHS Standard packing
F = Lead-free and RoHS Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-
Microelectronics Sales Office nearest to you.
17/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
REVISION HISTORY
Table 12. Document Revision History
Date
Version
0.1
Revision Details
29-Apr-2004
01-Feb-2005
First Issue
Part Number M69KB096A changed to M69KB096AA throughout document.
changed to V throughout the document. Table 6., Table 7., Table 8. and
0.2
V
DDQ
DDQF
13-July-2005
0.3
Table 9. modified.
18/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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相关型号:
M36LLR8760TT
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
STMICROELECTR
M36LLR876B0
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
STMICROELECTR
M36LLR876B0E
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
STMICROELECTR
M36LLR8860B1ZAQE
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88
STMICROELECTR
M36LLR8860B1ZAQF
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88
STMICROELECTR
M36LLR8860D1ZAQE
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88
STMICROELECTR
M36LLR8860D1ZAQF
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88
STMICROELECTR
M36LLR8860M1ZAQE
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.8 MM PITCH, ROHS COMPLIANT, LFBGA-88
STMICROELECTR
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