M36W0R604040B1ZAQE [NUMONYX]

64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 16 Mbit (1 Mb 】16) PSRAM, multi-chip package; 64兆位（ 4兆】 16 ，多银行，连拍），闪存和16兆位（ 1兆】 16 ） PSRAM ，多芯片封装


型号：	M36W0R604040B1ZAQE
厂家：	NUMONYX B.V
描述：	64 Mbit (4 Mb 】16, Multiple Bank, Burst) Flash memory and 16 Mbit (1 Mb 】16) PSRAM, multi-chip package 64兆位（ 4兆】 16 ，多银行，连拍），闪存和16兆位（ 1兆】 16 ） PSRAM ，多芯片封装闪存静态存储器
文件：	总22页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M36W0R6040T1

M36W0R604BT1

64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory

and 16 Mbit (1 Mb ×16) PSRAM, multi-chip package

Features

■ Multi-chip package

– 1 die of 64 Mbit (4 Mb x 16) Flash memory

– 1 die of 16 Mbit (1 Mb x 16) Pseudo SRAM

FBGA

■ Supply voltage

– V

= V

= 1.7 V to 1.95 V

DDQ

DDF

DDP

Stacked TFBGA88 (ZAQ)

8 × 10 mm

■ Low power consumption

■ Electronic signature

– Manufacturer Code: 20h

– Device Code (top flash configuration),

M36W0R6040T1: 8810h

– Device Code (bottom flash configuration),

M36W0R604BT1: 8811h

■ Block locking

– All blocks locked at Power-up

– Any combination of blocks can be locked

■ ECOPACK® packages available

– WP for Block Lock-Down

■ Security

Flash memory

– 128-bit user programmable OTP cells

– 64-bit unique device number

■ Programming time

– 8 µs by Word typical for Fast Factory

Program

■ Common Flash Interface (CFI)

– Double/Quadruple Word Program option

– Enhanced Factory Program options

■ 100 000 program/erase cycles per block

PSRAM

■ Memory blocks

■ Access time: 70 ns

– Multiple Bank Memory Array: 4 Mbit Banks

– Parameter Blocks (Top or Bottom location)

■ Low standby current: 110 µA

■ Deep power down current: 10 µA

■ Synchronous / Asynchronous Read

– Synchronous Burst Read mode: 66 MHz

– Asynchronous/ Synchronous Page Read

mode

– Random Access: 70 ns

■ Dual operations

– Program Erase in one Bank while Read in

others

– No delay between Read and Write

operations

November 2007

Rev 0.3

1/22

www.numonyx.com

Contents

M36W0R6040T1, M36W0R604BT1

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address Inputs (A0-A19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A20-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Chip Enable (E_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Output Enable (G_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash Write Enable (W_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash Write Protect (WP_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash Reset (RP_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash Latch Enable (L_{F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11}

2.10 Flash Clock (K_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 Flash Wait (WAIT_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.12 PSRAM Chip Enable (E1_{P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12}

2.13 PSRAM Chip Enable (E2_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.14 PSRAM Output Enable (G_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.15 PSRAM Write Enable (W_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.16 PSRAM Upper Byte Enable (UB_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.17 PSRAM Lower Byte Enable (LB_P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.18 V_DDFsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.19

2.20

_DDPsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

_DDQsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.21 V_PPFprogram supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.22 _SSground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/22

M36W0R6040T1, M36W0R604BT1

Contents

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/22

List of tables

M36W0R6040T1, M36W0R604BT1

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7.

Table 8.

4/22

M36W0R6040T1, M36W0R604BT1

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package outline. . 19

5/22

Description

M36W0R6040T1, M36W0R604BT1

Description

The M36W0R6040T1 and M36W0R604BT1 combine two memory devices in a multi-chip

package:

●

a 64-Mbit, Multiple Bank Flash memories, the M58WR064HT/B

●

a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating conditions do not

allow more than one memory to be active at the same time.

The purpose of this document is to describe how the two memory components operate with

respect to each other. It must be read in conjunction with the M58WR064HTB and

M69AR024B datasheets, where all specifications required to operate the Flash memory and

PSRAM components are fully detailed.

The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch)

package.

In order to meet environmental requirements, Numonyx offers the M36W0R6040T1 and

M36W0R604BT1 in ECOPACK® packages. These packages have a Lead-free second-level

interconnect. The category of Second-Level Interconnect is marked on the package and on

the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

The memory is supplied with all the bits erased (set to ‘1’).

6/22

M36W0R6040T1, M36W0R604BT1

Figure 1. Logic diagram

Description

PPF

DDQ

DDF

DDP

DQ0-DQ15

A0-A21

WAIT

M36W0R6040T1

M36W0R6040B1

Ai11080b

7/22

Description

M36W0R6040T1, M36W0R604BT1

Table 1.

Signal names

Common Address Inputs

A0-A19

DQ0-DQ15

V_DDF

V_DDQ

V_PPF

V_SS

Common Data Input/Output

Flash Memory Power Supply

Common Flash and PSRAM Power Supply for I/O Buffers

Common Flash Optional Supply Voltage for Fast Program & Erase

Ground

V_DDP

PSRAM Power Supply

Not Connected Internally

Do Not Use as Internally Connected

Flash memory control functions

A21-A20

L_F

Address Inputs for the Flash memory only

Latch Enable input

Chip Enable input

Output Enable input

Write Enable input

Reset input

E_F

G_F

W_F

RP_F

WP_F

K_F

Write Protect input

Burst Clock

WAIT_F

Wait Data in Burst Mode

PSRAM control functions

E1_P

G_P

Chip Enable input

Output Enable input

Write Enable input

W_P

E2_P

UB_P

LB_P

Power-down input

Upper Byte Enable input

Lower Byte Enable input

8/22

M36W0R6040T1, M36W0R604BT1

Description

Figure 2.

TFBGA connections (top view through package)

A21

A11

A12

A13

A15

A16

A18

A19

DDF

A17

PPF

A20

A10

A14

WAIT

DQ8

DQ0

DQ2

DQ1

DQ9

DQ10

DQ3

DQ11

DQ5

DQ12

DQ4

DQ13

DQ14

DQ6

DQ7

DQ15

DDQ

DDP

DDQ

DDF

AI08525

9/22

Signal descriptions

M36W0R6040T1, M36W0R604BT1

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connect-ed to this device.

2.1

Address Inputs (A0-A19)

Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The

Address Inputs select the cells in the memory array to access during Bus Read operations.

During Bus Write operations they control the commands sent to the Command Interface of

the Flash memory Program/Erase Controller, and they select the cells to access in the

PSRAM.

The Flash memory is accessed through the Chip Enable signal (^E) and through the Write

Enable (W_F) signal, while the PSRAM is accessed through two Chip Enable signals (E1

and E2 ) and the Write Enable signal (W ).

2.2

2.3

Address Inputs (A20-A21)

Addresses A20-A21 are inputs for the Flash memory component only. The Flash memory is

accessed through the Chip Enable signals (^E) and through the Write Enable (W_F) signal.

Data Input/Output (DQ0-DQ15)

For the Flash memory, the Data I/O outputs the data stored at the selected address during a

Bus Read operation or inputs a command or the data to be programmed during a Write Bus

operation.

For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper

part of the selected address during a Write or Read operation, when Upper Byte Enable

(UB ) is driven Low.

Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the

selected address during a Write or Read operation, when Lower Byte Enable (LB ) is driven

Low.

2.4

Flash Chip Enable (E_F)

The Chip Enable inputs activate the memory control logics, input buffers, decoders and

sense amplifiers. When Chip Enable is Low, V , and Reset is High, V , the device is in

active mode. When Chip Enable is at V the Flash memory is deselected, the outputs are

high impedance and the power consumption is reduced to the standby level.

2.5

Flash Output Enable (G_F)

The Output Enable pins control data outputs during Flash memory Bus Read operations.

10/22

M36W0R6040T1, M36W0R604BT1

Signal descriptions

2.6

Flash Write Enable (W_F)

The Write Enable controls the Bus Write operation of the Flash memories’ Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.7

Flash Write Protect (WP_F)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is Low, V , Lock-Down is enabled and the protection status of the Locked-

Down blocks cannot be changed. When Write Protect is at High, V , Lock-Down is disabled

and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in

M58WR064HT/B datasheet).

2.8

Flash Reset (RP_F)

The Reset input provides a hardware reset of the memory. When Reset is at V , the

memory is in Reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current I

. Refer to the M58WR064HT/B datasheet, for the

DD2

value of I

. After Reset all blocks are in the Locked state and the Configuration Register is

DD2

reset. When Reset is at V , the device is in normal operation. Exiting Reset mode the

device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch

Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied

to V

(refer to the M58WR064HT/B datasheet).

RPH

2.9

Flash Latch Enable (L_F

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is Low, V , and it is inhibited when Latch Enable is High, V . Latch

Enable can be kept Low (also at board level) when the Latch Enable function is not required

or supported.

2.10

2.11

Flash Clock (K_F)

The Clock input synchronizes the Flash memory to the microcontroller during synchronous

read operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at V . Clock is don't care during Asynchronous

Read and in write operations.

Flash Wait (WAIT_F)

WAIT is a Flash output signal used during Synchronous Read to indicate whether the data

on the output bus are valid. This output is high impedance when Flash Chip Enable is at V

or Flash Reset is at V . It can be configured to be active during the wait cycle or one clock

cycle in advance. The WAIT signal is not gated by Output Enable.

11/22

Signal descriptions

M36W0R6040T1, M36W0R604BT1

2.12

PSRAM Chip Enable (E1_P

When asserted (Low), the Chip Enable, E1 , activates the memory state machine, address

buffers and decoders, allowing Read and Write operations to be performed. When de-

asserted (High), all other pins are ignored, and the device is put, automatically, in low-power

Standby mode.

2.13

2.14

PSRAM Chip Enable (E2_P)

The Chip Enable, E2 , puts the device in Deep Power-down mode when it is driven Low.

This is the lowest power mode.

PSRAM Output Enable (G_P)

The Output Enable, G , provides a high speed tri-state control, allowing fast read/write

cycles to be achieved with the common I/O data bus.

2.15

2.16

PSRAM Write Enable (W_P)

The Write Enable, W , controls the Bus Write operation of the memory.

PSRAM Upper Byte Enable (UB_P)

The Upper Byte Enable, UB , gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a Write or Read operation.

2.17

2.18

2.19

PSRAM Lower Byte Enable (LB_P)

The Lower Byte Enable, LB , gates the data on the Lower Byte Data Inputs/Outputs (DQ0-

DQ7) to or from the lower part of the selected address during a Write or Read operation.

V_DDFsupply voltage

provides the power supply to the internal core of the Flash memory component. It is

DDF

the main power supplies for all Flash memory operations (Read, Program and Erase).

V_DDPsupply voltage

The V

Supply Voltage supplies the power for all operations (Read or Write) and for

DDP

driving the refresh logic, even when the device is not being accessed.

12/22

M36W0R6040T1, M36W0R604BT1

Signal descriptions

2.20

V_DDQsupply voltage

provides the power supply for the Flash Memory and PSRAM I/O pins. This allows all

DDQ

Outputs to be powered independently of the Flash Memory and PSRAM core power

supplies: V and V , respectively.

DDF

DDP

2.21

V_PPFprogram supply voltage

is both a Flash Memory control input and a Flash Memory power supply pin. The two

PPF

functions are selected by the voltage range applied to the pin.

If V is kept in a low voltage range (0V to V ) V is seen as a control input. In this

PPF

DDQ

PPF

case a voltage lower than V

gives an absolute protection against Program or Erase,

PPLKF

while V

> V

enables these functions (see the M58WR064HT/B datasheet for the

PPF

PP1F

relevant values). V

is only sampled at the beginning of a Program or Erase; a change in

PPF

its value after the operation has started does not have any effect and Program or Erase

operations continue.

If V

is in the range of V

it acts as a power supply pin. In this condition V

must be

PPF

PPHF

PPF

stable until the Program/Erase algorithm is completed.

2.22

V_SSground

is the common ground reference for all voltage measurements in the Flash (core and

I/O Buffers) and PSRAM chips.

Note:

Each Flash memory device in a system should have its supply voltage (V

) and the

DDF

program supply voltage V

decoupled with a 0.1µF ceramic capacitor close to the pin

PPF

(high frequency, inherently low inductance capacitors should be as close as possible to the

package). See Figure 5: AC measurement load circuit. The PCB track widths should be

sufficient to carry the required V

program and erase currents.

PPF

13/22

Functional description

M36W0R6040T1, M36W0R604BT1

Functional description

The Flash memory and PSRAM components have separate power supplies but share the

same grounds. They are distinguished by three Chip Enable inputs: E for the Flash

memory and E1 and E2 for the PSRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is simultaneous read operations on the Flash memory and

the PSRAM which would result in a data bus contention. Therefore it is recommended to put

the other devices in the high impedance state when reading the selected device.

Figure 3.

Functional block diagram

DDQ

DDF

PPF

A20-A21

64 Mbit

Flash

Memory

WAIT

A0-A19

DQ0-DQ15

DDP

16 Mbit

PSRAM

AI08449

14/22

M36W0R6040T1, M36W0R604BT1

Functional description

(1)

Table 2.

Main operating modes

E_FG_PW_PL_F

(2)

Operation

RP_FWAIT_F

E1_PE2_PG_PW_PUB_PLB_P

DQ15-DQ0

(3)

Flash Read

Flash Write

V_ILV_ILV_IHV_IL

V_ILV_IHV_ILV_IL

V_IH

Flash Data Out

Flash Data In

(3)

PSRAM must be disabled

Flash Address

Latch

Flash Data Out

or Hi-Z⁽⁴⁾

V_IL

V_IH

V_IL

V_IH

Flash Output

Disable

V_ILV_IHV_IH

Flash Hi-Z

Any PSRAM mode is allowed

Flash Standby

Flash Reset

V_IH

V_IL

Hi-Z

Flash Hi-Z

PSRAM Read

PSRAM Write

Output Disable

PSRAM Standby

V_ILV_IHV_ILV_IHV_ILV_ILPSRAM data out

V_ILV_IHV_IHV_ILV_ILV_ILPSRAM data in

Flash Memory must be disabled

V_ILV_IHV_IHV_IH

PSRAM Hi-Z

V_IHV_IH

V_IL

Any Flash mode is allowed.

PSRAM Deep

Power-Down

PSRAM Hi-Z

1. X = Don't care.

2. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for

details.

3. L_Fcan be tied to V_IHif the valid address has been previously latched.

4. Depends on G_F.

15/22

Maximum rating

M36W0R6040T1, M36W0R604BT1

Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 3.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

Min

Max

T_A

T_BIAS

T_STG

V_IO

Ambient Operating Temperature

Temperature Under Bias

–30

–40

°C

125

155

Storage Temperature

–65

Input or Output Voltage

–0.5

–0.2

V_DDQ+0.6

2.45

3.3

V_DDF

V_DDQ

V_DDP

V_PPF

I_O

Flash Memory Core Supply Voltage

Input/Output Supply Voltage

PSRAM Supply Voltage

Flash Memory Program Voltage

Output Short Circuit Current

Time for V_PPFat V_PPFH

100

hours

t_VPPFH

100

16/22

M36W0R6040T1, M36W0R604BT1

DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

<Blue>Table 4., Operating and AC measurement conditions. Designers should check that

the operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Table 4.

Operating and AC measurement conditions

Flash memory

Parameter

PSRAM

Unit

Min

Max

Min

Max

V_DDFSupply Voltage

V_DDPSupply Voltage

1.7

–

1.95

–

1.7

–

1.95

–

V_DDQSupply Voltage

1.7

11.4

–0.4

–40

1.95

V_PPFSupply Voltage (Factory environment)

V_PPFSupply Voltage (Application environment)

Ambient Operating Temperature

Load Capacitance (C_L)

12.6

–

V_DDQ+0.4

–

–30

°C

Input Rise and Fall Times

Input Pulse Voltages

0 to V_DDQ

V_DDQ/2

0 to V_DDP

V_DDP/2

Input and Output Timing Ref. Voltages

Figure 4.

AC measurement I/O waveform

DDQ

AI06161

17/22

DC and AC parameters

Figure 5.

M36W0R6040T1, M36W0R604BT1

AC measurement load circuit

V_DDQ

V_DDF

V_DDQ

16.7kΩ

DEVICE

UNDER

TEST

C_L

0.1µF

16.7kΩ

0.1µF

C_Lincludes JIG capacitance

AI08364

(1)

Table 5.

Symbol

Device capacitance

Parameter

Test condition

Min

Max

Unit

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V

C_OUT

V_OUT= 0V

1. Sampled only, not 100% tested.

Please refer to the M58WR064HT/B and M69AR024B datasheets for further DC and AC

characteristics values and illustrations.

18/22

M36W0R6040T1, M36W0R604BT1

Package mechanical

Figure 6.

Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,

package outline

E2 E1

BALL "A1"

ddd

FE FE1

BGA-Z42

1. Drawing is not to scale.

Table 6.

Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package

mechanical data

millimeters

inches

Symbol

Typ

Min

Max

Typ

Min

Max

1.200

0.0472

0.200

0.0079

0.850

0.350

8.000

5.600

0.0335

0.0138

0.3150

0.2205

0.300

7.900

0.400

8.100

0.0118

0.3110

0.0157

0.3189

ddd

0.100

0.0039

0.3976

10.000

7.200

8.800

0.800

1.200

1.400

0.600

0.400

9.900

–

10.100

0.3937

0.2835

0.3465

0.0315

0.0472

0.0551

0.0236

0.0157

0.3898

–

FE1

19/22

Part numbering

M36W0R6040T1, M36W0R604BT1

Part numbering

Table 7.

Ordering information scheme

Example:

M36 W 0 R 6 0 4 0 T 1 ZAQ E

Device type

M36 = Multi-chip package (Multiple Flash + RAM)

Flash 1 architecture

W = Multiple Bank, Burst mode

Flash 2 architecture

0 = none present

Operating voltage

R = V_DDF= V_DDQ=V_DDP= 1.7 V to 1.95 V

Flash 1 density

6 = 64 Mbit

Flash 2 density

0 = none present

RAM 1 density

4 = 16 Mbit

RAM 0 density

0 = none present

Parameter blocks location

T = Top Boot Block Flash

B = Bottom Boot Block Flash

Product version

1 = 90 nm Flash technology, 70 ns;

0.18 µm RAM, 70 ns speed

Package

ZAQ = Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch

Option

E = ECOPACK® Package, Standard Packing

F = ECOPACK® Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this

device, please contact the Numonyx Sales Office nearest to you.

20/22

M36W0R6040T1, M36W0R604BT1

Revision history

Table 8.

Date

Document revision history

Version

Revision Details

08-June-2005

18-Jan-2007

14-Nov-2007

0.1

First Issue.

Document status promoted from Target Specification to full

Datasheet.

Package is ECOPACK® compliant.

DC characteristics of Flash memory and PSRAM components

removed (for further details please refer to the M58WR064HT/B

and M69AR024B datasheets. Small text changes.

0.2

0.3

Applied Numonyx branding.

21/22

M36W0R6040T1, M36W0R604BT1

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

22/22

M36W0R604040B1ZAQE [NUMONYX]

相关型号：

M36W0R604040B1ZAQF

M36W0R604040T0ZAQE

M36W0R604040T0ZAQF

M36W0R604040T1ZAQE

M36W0R604040T1ZAQF

M36W0R6040B3

M36W0R6040B3ZAQE

M36W0R6040B3ZAQF

M36W0R6040L4ZAMF

M36W0R6040L4ZSE

M36W0R6040L4ZSF

M36W0R6040T0