M36W0R6040L4ZAMF [NUMONYX]
Memory Circuit, Flash+PSRAM, 4MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88;
| 型号： | M36W0R6040L4ZAMF |
| 厂家： | 
NUMONYX B.V |
| 描述： | Memory Circuit, Flash+PSRAM, 4MX16, CMOS, PBGA88, 8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36W0Rx0x0UL4
32- or 64-Mbit (mux I/O, multiple bank, multilevel, burst) flash
memory, 16- or 32-Mbit PSRAM, 1.8 V supply MCP
Features
■ Multichip package
– 1 die of 32 Mbit (2 Mbit x 16) or 64 Mbit
(4 Mbit x 16) mux I/O multiple bank,
multilevel, burst) flash memory
TFBGA88 (ZAM)
8 x 10 mm
TFBGA56 (ZS)
8 x 6 mm
– 1 die of 16/32 Mbit mux I/O, burst PSRAM
■ Supply voltage
– WP for block lock-down
■ Security
– V = V
= 1.7 to 1.95 V
DD
DDQ
– V
= 9 V for fast programming
PPF
– 128 bit user programmable OTP cells
– 64 bit unique device number
■ Electronic signature
– Manufacturer code: 20h
■ 100 000 program/erase cycles per block
– 32 Mbit flash device codes:
Top - M36W0R5040U4: 8828h
Bottom - M36W0R5040L4: 8829h
PSRAM
■ Asynchronous modes
– 64 Mbit flash device codes:
Top - M36W0R6040U4 and
M36W0R6050U4: 88C0h
Bottom - M36W0R6040L4 and
M36W0R6050L4: 88C1h
– Random read 70 ns access time
– Asynchronous write
■ Synchronous mode:
– NOR flash
Flash memory
– Full synchronous (burst read and write)
■ Synchronous/asynchronous read
– Synchronous burst read mode: 66 MHz
– Random access: 70 ns
■ Burst read/write operations
– 4-, 8- and 16-word
– Clock frequency: 83 MHz
■ Synchronous burst read suspend
■ Low power consumption
– Active current: < 20 mA
– Standby current: 70 µA
■ Programming time
– 10 µs by word typical for factory program
– Double/quadruple word program option
■ Low power features
– Partial array self-refresh (PASR)
– Deep power-down (DPD) mode
■ Memory blocks
– Multiple bank memory array: 4 Mbit banks
– Parameter blocks (top or bottom location)
– Automatic temperature-compensated self-
Refresh (ATSR)
■ Dual operations
– Program erase in 1 bank, read in others
– No delay between read and write
Table 1.
Device summary
M36W0Rx0x0UL4
■ Common flash interface (CFI)
M36W0R5040U4
M36W0R6040U4
M36W0R6050U4
M36W0R5040L4
M36W0R6040L4
M36W0R6050L4
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
July 2008
Rev 6
1/28
www.numonyx.com
1
Contents
M36W0Rx0x0UL4
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Common signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
Data inputs/outputs (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Chip Enable (E ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
F
Flash memory Write Protect (WP ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
F
Flash memory Reset (RP ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
F
PSRAM Chip Enable (E ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
PSRAM Upper Byte Enable (UB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
2.1.10 PSRAM Lower Byte Enable (LB ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
P
2.1.11 PSRAM Configuration Register Enable (CR ) . . . . . . . . . . . . . . . . . . . . 12
P
2.1.12
2.1.13
2.1.14
V
V
V
flash memory program supply voltage . . . . . . . . . . . . . . . . . . . . . 13
PPF
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SS
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SSQ
2.2
TFBGA56 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
TFBGA56 address inputs (ADQ0-ADQ15 and A16-A21) . . . . . . . . . . . 13
Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDQ
2.3
TFBGA88 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
TFBGA88 address inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash memory Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
F
Flash memory Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
F
V
V
flash memory supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PSRAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDF
CCP
PSRAM Output Enable (G ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
P
PSRAM Write Enable (W ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
P
2/28
M36W0Rx0x0UL4
Contents
3
4
5
6
7
8
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/28
List of tables
M36W0Rx0x0UL4
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TFBGA56 package operating modes - standard asynchronous operation. . . . . . . . . . . . . 18
TFBGA88 package operating modes - standard asynchronous operation. . . . . . . . . . . . . 19
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TFBGA56 8 × 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, package data . . . . . . . . . . . . 24
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package data . . . 25
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4/28
M36W0Rx0x0UL4
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram - TFBGA56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic diagram - TFBGA88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA56 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA88 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . 10
Functional block diagram - TFBGA56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional block diagram - TFBGA88 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TFBGA56 8 × 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, bottom view package outline 23
Figure 10. TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, bottom view package outline. . . . 24
5/28
Description
M36W0Rx0x0UL4
1
Description
The M36W0R5040U4, M36W0R5040L4, M36W0R6040U4, M36W0R6040L4,
M36W0R6050U4, and M36W0R6050L4 each combine two memory devices in a multichip
package:
●
a 32-Mbit or 64-Mbit, multiple bank flash memory, the M58WR0xxKUL
●
either:
–
–
a 16-Mbit pseudo SRAM, the M69KM024A
a 32-Mbit pseudo SRAM, the M69KM048A.
Collectively, these four devices are referred to in this document as the M36W0Rx0x0UL4.
The purpose of this document is to describe how the two memory components operate with
respect to each other. It must be read in conjunction with the M58WR0xxKUL, and
M69KM024A or M69KM048A datasheets, which detail all the specifications required to
operate the flash memory and PSRAM components. These datasheets are available from
your local Numonyx distributor.
The memory is offered in two stacked packages:
●
TFBGA56 (8 x 6 mm, 10 x 6 ball array, 0.5 mm pitch) package
TFBGA88 (8 x 10 mm, 8 x 10 ball array, 0.8 mm pitch) package
●
Recommended operating conditions do not allow more than one memory to be active at the
same time.
Figure 1.
Logic diagram - TFBGA56 package
V
V
V
DD
DDQ
PPF
6
16
A16-A21
ADQ0-ADQ15
WAIT
E
F
G
W
RP
F
M36W0Rx0x0UL4
WP
F
L
DPD
K
E
P
CR
UB
P
P
LB
P
V
Ai14405f
V
SS
SSQ
6/28
M36W0Rx0x0UL4
Description
Figure 2.
Logic diagram - TFBGA88 package
V
V
PPF
DDQF
V
V
DDF
DDP
6
16
A16-A21
ADQ0-ADQ15
WAIT
E
G
F
F
F
W
RP
WP
L
F
F
M36W0Rx0x0UL4
K
E
P
P
G
W
P
CR
P
UB
LB
P
P
V
Ai13541d
SS
7/28
Description
M36W0Rx0x0UL4
Direction
Table 2.
Name
Common to both packages
Signal names
Function
A16-A21(1)
Address inputs
Inputs
Flash memory and PSRAM common data input/outputs, address
inputs or command inputs
ADQ0-ADQ15
Inputs/outputs
L
Flash memory and PSRAM Latch Enable input
Flash memory and PSRAM Burst Clock
Flash memory and PSRAM Wait Data in burst mode
Flash memory Chip Enable input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
K
WAIT
EF
WPF
RPF
EP
Flash memory Write Protect input
Flash memory Reset input
PSRAM Chip Enable input
UBP
LBP
CRP
VPPF
VSS
VSSQ
NC
PSRAM Upper Byte Enable input
PSRAM Lower Byte Enable input
PSRAM Configuration Register Enable input
Flash memory optional supply voltage for fast program and erase Power supply
Flash memory and PSRAM shared ground
Flash memory and PSRAM shared ground.
Not connected internally
Ground
Ground
Only in TFBGA56 package
DPD
G
Deep power-down
Input
Flash memory and PSRAM Output Enable input
Flash memory and PSRAM Write Enable input
Flash memory and PSRAM shared power supply
Flash memory and PSRAM shared power supply for I/O buffers
Input
W
Input
VDD
VDDQ
Power supply
Power supply
Only in TFBGA88 package
GF
Flash memory Output Enable input
Input
WF
Flash memory Write Enable input
PSRAM Output Enable input
Input
GP
Input
WP
PSRAM Write Enable input
Input
VDDF
VCCP
Flash memory power supply
Power supply
Power supply
PSRAM supply voltage is the core supply voltage.
1. In the TFBGA56 package, address inputs A16-A18 in the PSRAM are used in conjunction with ADQ0 to
ADQ15 to select the cells in the memory array that are accessed during read and write operations.
However, in the TFBGA88 package, it is is address inputs A16-A19.
8/28
M36W0Rx0x0UL4
Description
Figure 3.
TFBGA56 package connections (top view through package)
9/28
Description
M36W0Rx0x0UL4
Figure 4.
TFBGA88 package connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
NC
NC
NC
NC
NC
NC
DU
A21
DU
DU
NC
NC
NC
NC
A16
NC
NC
A18
A19
NC
NC
NC
V
V
NC
K
V
SS
SS
DDF
LB
P
NC
NC
A17
NC
V
W
P
E
P
NC
PPF
WP
L
A20
NC
NC
F
NC
UB
P
RP
W
F
NC
F
G
H
J
ADQ8
ADQ0
ADQ2
ADQ1
ADQ9
DU
ADQ10
ADQ3
ADQ11
NC
ADQ5
ADQ12
ADQ4
ADQ13
ADQ14
ADQ6
NC
WAIT
ADQ7
ADQ15
G
P
NC
G
F
V
DDQF
E
F
K
L
DU
V
V
CR
DDP
DDQF
P
V
V
V
V
V
V
V
V
SS
SS
DDQF
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
Ai12838b
10/28
M36W0Rx0x0UL4
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram - TFBGA56 package and Table 2: Signal names for a brief
overview of the signals connected to this device.
There are some signals that are not common to both device packages and are, therefore,
explained separately.
2.1
Common signals
The following are the signals that are the same for the TFBGA56 package and the
TFBGA88 package.
2.1.1
2.1.2
Data inputs/outputs (ADQ0-ADQ15)
The data I/O output the data stored at the selected address during a bus read operation, or
they input a command or the data to be programmed during a bus write operation.
Latch Enable (L)
The Latch Enable input is common to the flash memory and PSRAM components.
For more details on the Latch Enable signal, please refer to the datasheets of the respective
memory components: M69KM024A or M69KM048A for the PSRAM and M58WR0xxKUL for
the flash memory.
2.1.3
2.1.4
2.1.5
Clock (K)
The Clock input is common to the flash memory and PSRAM components.
For more details on the Clock signal, please refer to the datasheets of the respective
memory components: M69KM024A or M69KM048A for the PSRAM and M58WR0xxKUL for
the flash memory.
Wait (WAIT)
The Wait output is common to the flash memory and PSRAM components.
For details on the Wait signal, please refer to the datasheets of the respective memory
components:M69KM024A or M69KM048A for the PSRAM and M58WR0xxKUL for the flash
memory.
Flash memory Chip Enable (E )
F
The flash memory Chip Enable input activates the memory control logic, input buffers,
decoders and sense amplifiers. When Chip Enable is at V and Reset is at V the device is
IL
IH
in active mode. When flash memory Chip Enable is at V the memory is deselected, the
IH
outputs are high impedance and the power consumption is reduced to the standby level.
It is not allowed to set both E and E to V at the same time.
F
P
IL
11/28
Signal descriptions
M36W0Rx0x0UL4
2.1.6
Flash memory Write Protect (WP )
F
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is at V , the lock-down is enabled and the protection status of the locked-
IL
down blocks cannot be changed. When Write Protect is at V , the lock-down is disabled
IH
and the locked-down blocks can be locked or unlocked (refer to the M58WR0xxKUL
datasheet).
2.1.7
Flash memory Reset (RP )
F
The Reset input provides a hardware reset of the memory. When Reset is at V , the
IL
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current I
. Refer to the M58WR0xxKUL datasheet for the
DD2
value of I
After Reset all blocks are in the locked state and the Configuration Register is
DD2.
reset. When Reset is at V , the device is in normal operation. When the device exits reset
IH
mode it enters asynchronous read mode. However, a negative transition of Chip Enable or
Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be tie
to V
(refer to the M58WR0xxKUL datasheet).
RPH
2.1.8
PSRAM Chip Enable (E )
P
Chip Enable, E , activates the PSRAM device when driven Low (asserted). When de-
P
asserted (V ), the device is disabled and goes automatically into low-power standby mode
IH
or deep power-down mode, according to the RCR settings.
It is not allowed to set both E and E to V at the same time.
F
P
IL
2.1.9
PSRAM Upper Byte Enable (UB )
P
The Upper Byte Enable, UB , gates the data on the upper byte of the address inputs/data
P
inputs/outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
2.1.10
PSRAM Lower Byte Enable (LB )
P
The Lower Byte Enable, LB , gates the data on the lower byte of the address inputs/data
P
input/outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB and UB are disabled (High), the device prevents the data bus from receiving or
P
P
transmitting data. Although the device seems to be deselected, it remains in an active mode
as long as E remains Low.
P
2.1.11
PSRAM Configuration Register Enable (CR )
P
When this signal is driven High, V , bus read or write operations access either the value of
IH
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR),
according to the value of A19.
12/28
M36W0Rx0x0UL4
Signal descriptions
2.1.12
V
flash memory program supply voltage
PPF
V
is both a control input and a power supply pin. The two functions are selected by the
PPF
voltage range applied to the pin.
If V is kept in a low voltage range (0 V to V
), V acts as a control input. In this case
PPF
PPF
DDQ
a voltage lower than V
gives absolute protection against program or erase, while V
PPLK
PPF
in the V
range enables these functions (see the M58WR0xxKUL datasheet for the
PP1
relevant values).
V
is only sampled at the beginning of a program or erase; a change in its value after the
PPF
operation has started does not have any effect and program or erase operations continue.
If V is in the range of V it acts as a power supply pin. In this condition V must be
PPF
PPH
PPF
stable until the program/erase algorithm is completed.
2.1.13
V
ground
SS
V
ground is the common flash memory and PSRAM ground. It is the reference for the
SS
core supplies and must be connected to the system ground.
2.1.14
V
ground
SSQ
V
ground is the reference for the input/output circuitry driven by V
. V
must be
SSQ
DDQF SSQ
connected to V
SS
Note:
Each device in a system should have V , V
and V decoupled with a 0.1µF
DDF DDQF PP
ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors
should be as close as possible to the package). See Figure 8: AC measurement load circuit.
The PCB track widths should be sufficient to carry the required V program and erase
PP
currents.
2.2
TFBGA56 signals
2.2.1
TFBGA56 address inputs (ADQ0-ADQ15 and A16-A21)
The following address inputs are common to the flash memory and PSRAM components:
●
●
●
ADQ0-ADQ15, and
A16-A19 when stacked with a 16-Mbit PSRAM, or
A16-A20 when stacked with a 32-Mbit PSRAM.
In the flash memory, the address inputs select the cells in the array to access during bus
read operations. During bus write operations they control the commands sent to the
command interface of the Program/Erase Controller.
In the PSRAM, the address following inputs are used in conjunction with ADQ0 to ADQ15 to
select the cells in the memory array that are accessed during read and write operations:
●
A16-A19 when stacked with a 16-Mbit PSRAM, or
A16-A20 when stacked with a 32-Mbit PSRAM.
●
A21 is an address input for the 64-Mbit flash memory device only.
13/28
Signal descriptions
M36W0Rx0x0UL4
2.2.2
Deep power-down (DPD)
The deep power-down input puts the device in deep power-down mode. When the device is
in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the
deep power-down input causes the memory to enter deep power-down mode.
When the device is in deep power-down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPD pin is determined by ECR14. The deep power-down input is active
Low by default.
2.2.3
2.2.4
Output Enable (G)
The Output Enable input is common to the flash memory and PSRAM components. For
details on the Output Enable signal, please refer to the datasheets of the respective memory
components: M69KM024A or M69KM048A for the PSRAM and M58WR0xxKUL for the
flash memory.
Write Enable (W)
The Write Enable Input is common to the flash memory and PSRAM components. For
details on the Write Enable signal, please refer to the datasheets of the respective memory
components: M69KM024A or M69KM048A for the PSRAM and M58WR0xxKUL for the
flash memory.
2.2.5
2.2.6
V
supply voltage
DD
V
is common to both flash memory and PSRAM components and provides the power
DD
supply to the internal core. It is the main power supply for all memory operations (read,
program, and erase).
V
supply voltage
DDQ
V
is common to both flash memory and PSRAM components and provides the power
DDQ
supply to the I/O pins. It enables all outputs to be powered independently of V . V
can
DD DDQ
be tied to V or use a separate supply.
DD
2.3
TFBGA88 signals
2.3.1
TFBGA88 address inputs
The following address inputs are common to the flash memory and PSRAM components:
●
●
●
ADQ0-ADQ15, and
A16-A19 when stacked with a 16-Mbit PSRAM, or
A16-A20 when stacked with a 32-Mbit PSRAM.
A21 is an address input for the 64-Mbit flash memory component only.
14/28
M36W0Rx0x0UL4
Signal descriptions
In the PSRAM, the address following inputs are used in conjunction with ADQ0 to ADQ15 to
select the cells in the memory array that are accessed during read and write operations:
●
A16-A19 when stacked with a 16-Mbit PSRAM, or
A16-A20 when stacked with a 32-Mbit PSRAM.
●
In the flash memory, the address inputs select the cells in the array to access during bus
read operations. During bus write operations they control the commands sent to the
command interface of the Program/Erase Controller.
2.3.2
2.3.3
Flash memory Output Enable (G )
F
The Output Enable input controls data outputs during the bus read operation of the flash
memory.
Flash memory Write Enable (W )
F
The Write Enable input controls the bus write operation of the flash memory’s command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
2.3.4
V
flash memory supply voltage
DDF
V
provides the power supply to the internal core of the flash memory. It is the main
DDF
power supply for all flash memory operations (read, program, and erase).
2.3.5
2.3.6
V
PSRAM supply voltage
CCP
The V
supply voltage is the core supply voltage.
CCP
PSRAM Output Enable (G )
P
When held Low, V , the Output Enable, G , enables the bus read operations of the
IL
P
memory.
2.3.7
PSRAM Write Enable (W )
P
Write Enable, W , controls the bus write operation of the memory. When asserted (V ), the
P
IL
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
15/28
Functional description
M36W0Rx0x0UL4
3
Functional description
The PSRAM and flash memory components share the same power supplies and the same
grounds. They are distinguished by two Chip Enable inputs: E for the flash memory and E
F
P
for the PSRAM.
Recommended operating conditions do not allow more than one device to be active at a
time, such as simultaneous read operations on the flash memory and the PSRAM
component, which would result in a data bus contention.
Therefore, it is recommended to put the other device in the high impedance state when
reading the selected device.
Figure 5 outlines the functional block diagram for the TFBGA56 package, while Figure 6
outlines the one for TFBGA88 package.
Figure 5.
Functional block diagram - TFBGA56 package
V
PPF
A20 or A20-A21
or A21(1)
DPD
E
F
32 or 64 Mbit
Flash
RP
F
WP
memory
F
WAIT
K
L
W
V
V
DDQ
DD
V
SS
G
ADQ0-ADQ15
A16-Amax (2)
E
P
16 or 32 Mbit
PSRAM
V
SSQ
CR
P
UB
LB
P
P
AI14407f
1. A20 for the M36W0R5040x4, A20-A21 for the M36W0R6040x4, and A21 for the M36W0R6050x4.
2. Amax is equal to A19 when stacked with a 16-Mbit PSRAM, or A20 when stacked with a 32-Mbit PSRAM.
16/28
M36W0Rx0x0UL4
Functional description
Figure 6.
Functional block diagram - TFBGA88 package
V
V
V
PPF
DDQF
DDF
A20 or A20-A21
or A21(1)
E
F
W
F
32 or 64 Mbit
Flash
RP
F
WP
Memory
F
G
F
WAIT
K
L
V
V
CCP
SS
A16-Amax (2)
ADQ0-ADQ15
E
P
16 or 32 Mbit
PSRAM
G
P
W
P
CR
P
UB
LB
P
P
AI12339c
1. A20 for the M36W0R5040x4, A20-A21 for the M36W0R6040x4, and A21 for the M36W0R6050x4.
2. Amax is equal to A19 when stacked with a 16-Mbit PSRAM, or A20 when stacked with a 32-Mbit PSRAM.
17/28
Functional description
Table 3.
M36W0Rx0x0UL4
TFBGA56 package operating modes - standard asynchronous operation
WAIT
(3)
ADQ0- ADQ8
ADQ7 -ADQ15
Operation(1)(2)
UBP LBP CRP EP
EF
RPF
G
W
L
Bus read
Bus write
VIL
VIL
VIH
VIH
VIL VIH VIH
Data output
Data input
VIH VIL VIH Any PSRAM mode is
allowed.
Data output or
Hi-Z(4)
Address latch
VIL
VIH
VIH
X
VIL
Output disable
Standby
VIL
VIH
X
VIH
VIH
VIL
VIH VIH VIH
Hi-Z
Hi-Z
Hi-Z
Any PSRAM mode is
allowed.
Hi-Z
Hi-Z
X
X
X
X
X
X
Reset
Address in/ data
out valid
VIL VIL VIL
Word read
Word write
VIL VIH
VIH VIL
The flash memory
must be disabled.
\_/
Address in/ data
in valid
VIL VIL VIL
VIL
Output
VIH
VIL
disable/no
operation
VIH
X
X
X
High-Z
Any flash memory
mode is allowed.
Deep power-
down(5)
VIH
VIH
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
Standby
1. The Clock signal, K, must remain Low when the PSRAM is operating in asynchronous mode.
2. X = ‘don’t care’
3. In the flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. See the M58WR0xxKUL datasheet.
5. The device enters deep power-down mode by driving the Chip Enable signal, E, from Low to High, with bit
4 of the RCR set to “0”. The device remains in deep power-down mode until E goes Low again and is held
Low for tELEH(DP)
.
18/28
M36W0Rx0x0UL4
Functional description
(1)
Table 4.
TFBGA88 package operating modes - standard asynchronous operation
WAIT
(3)
A16- ADQ0- ADQ8-
A18 ADQ7 ADQ15
Operation(2) EF GF WF RPF
LP EP WP GP UBP LBP CRP
A19
Bus read
Bus write
VIL VIL VIH VIH
VIL VIH VIL VIH
VIH
Data output
Data input
VIH
VIL
The PSRAM must be disabled
Any PSRAM mode is allowed
Address latch VIL VIH
X
VIH
Address input
Output
VIL VIH VIH VIH
VIH
Hi-Z
disable
Standby
Reset
VIH
X
X
X
X
X
VIH Hi-Z
VIL Hi-Z
X
X
Hi-Z
Hi-Z
Address in/data
Word read
Word write
VIH VIL VIL VIL VIL Address in valid
VIL VIH VIL VIL VIL Address in valid
out valid
\_/
Address in/ data
in valid
VIL
Output
disable/no
operation
VIH
X
X
X
VIL
X
X
High-Z
X
Deep power-
down(4)
VIH
VIH
X
X
X
X
X
X
X
X
X
X
High-Z
High-Z
Standby
VIL
X
1. X = ‘don’t care’
2. The Clock signal, K, must remain Low in asynchronous operating mode.
3. In the flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. The device enters deep power-down mode by driving the Chip Enable signal, E, from Low to High, with bit 4 of the RCR set
to ‘0’. The device remains in deep power-down mode until E goes Low again and is held Low for tELEH(DP)
.
19/28
Maximum ratings
M36W0Rx0x0UL4
4
Maximum ratings
Stressing the device above the ratings listed in Table 5: Absolute maximum ratings may
cause permanent damage to the device. These are only stress ratings and operating the
device at these or any other conditions above those indicated in the operating sections of
this specification is not suggested. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Min
Max
TA
Ambient operating temperature
Temperature under bias
Storage temperature
–30
–30
–55
–0.2
85
85
°C
°C
°C
V
TBIAS
TSTG
VIO
125
2.45
Input or output voltage
Flash and PSRAM core and
input/output supply voltages
VDD, VDDQ
–0.2
–0.2
2.45
V
VPPF
IO
Flash program voltage
Output short circuit current
Time for VPPF at VPPFH
10
V
100
100
mA
tVPPFH
hours
20/28
M36W0Rx0x0UL4
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 6: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 6.
Operating and AC measurement conditions
Flash memory
Parameter
PSRAM
Unit
Min
Max
Min
Max
VDD supply voltage
VDDQ supply voltage
1.7
1.7
1.95
1.95
–
–
–
–
V
V
VPPF supply voltage (factory environment)
8.5
9.5
–
–
V
VPPF supply voltage (application environment)
Ambient operating temperature
Load capacitance (CL)
–0.4
–30
VDDQ +0.4
85
–
–
V
–30
85
°C
pF
kΩ
ns
V
30
30
Output circuit resistors (R1, R2)
Input rise and fall times
16.7
16.7
5
2
Input pulse voltages
0 to VDDQ
VDDQ/2
0 to VDD/2
VDD/2
Input and output timing ref. voltages
V
Figure 7.
AC measurement I/O waveform
V
DDQ
V
/2
DDQ
0 V
AI06161
21/28
DC and AC parameters
Figure 8.
M36W0Rx0x0UL4
AC measurement load circuit
V
DDQ
V
V
DDQ
DD
R
1
DEVICE
UNDER
TEST
C
L
0.1 µF
R
2
0.1 µF
C
includes JIG capacitance
L
AI08364E
Table 7.
Symbol
Device capacitance
Parameter
Test condition
Min
Max(1)
Unit
CIN
Input capacitance
Output capacitance
VIN = 0 V
14
18
pF
pF
COUT
VOUT = 0 V
1. Sampled only, not 100% tested.
Please refer to the M58WR0xxKUL and the M69KM024A or M69KM048A datasheets for
further DC and AC characteristics values and illustrations.
22/28
M36W0Rx0x0UL4
Package mechanical
6
Package mechanical
To meet environmental requirements Numonyx offers these devices in ECOPACK®
packages, which have a lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK specifications are available at: www.numonyx.com.
Figure 9.
TFBGA56 8 × 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, bottom view
package outline
D
D2
D1
A
SE
b
E
E1
FE
E2
BALL "A1"
FE1
e
A1
FD1
FD
SD
e
A2
ddd
JV_ME
1. Drawing is not to scale.
23/28
Package mechanical
M36W0Rx0x0UL4
Table 8.
Symbol
TFBGA56 8 × 6 x 1.2 mm, 10 x 6 ball array - 0.5 mm pitch, package data
Millimeters
Min
Inches
Min
Typ
Max
Typ
Max
A
A1
A2
b
1.20
0.047
0.15
0.0006
0.79
0.30
6.00
4.50
4.00
2.50
0.50
0.75
0.75
0.25
0.031
0.012
0.236
0.177
0.157
0.098
0.020
0.030
0.030
0.010
0.25
5.90
0.35
6.10
0.010
0.232
0.014
0.240
D
D1
E
3.90
4.10
0.154
0.161
E1
e
FD
FE
SD
Figure 10. TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, bottom view
package outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
1. Drawing is not to scale.
24/28
M36W0Rx0x0UL4
Package mechanical
Table 9.
Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch,
package data
Millimeters
Inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
–
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
–
E1
E2
e
–
–
FD
FE
FE1
SD
SE
25/28
Part numbering
M36W0Rx0x0UL4
7
Part numbering
Table 10. Ordering information scheme
Example:
M36 W 0 R 5 0
4
0 U 4 ZS
F
Device type
M36 = multichip package (flash + RAM)
Flash 1 architecture
W = multiple bank, burst mode
Flash 2 architecture
0 = no die
Operating voltage
R = VDD = VDDQ = 1.7 V to 1.95 V
Flash 1 density
5 = 32 Mbit
6 = 64 Mbit
Flash 2 density
0 = no die
RAM 1 density
4 = 16 Mbit
5 = 32 Mbit
RAM 2 density
0 = no die
Parameter block location
U = top block flash
L = bottom block flash
Product version
4 = 65 nm flash technology and multilevel design, 70 ns speed class;
RAM, 70 ns speed mux I/O
Package
ZS = stacked TFBGA56 8 x 6 mm - 10 x 6 active ball array, 0.50 mm pitch
ZAM = stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch
Packing option
E = ECOPACK® package, standard packing
F = ECOPACK® package, tape and reel packing
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
“1”. For further information on any aspect of this device, please contact your nearest
Numonyx sales office.
26/28
M36W0Rx0x0UL4
Revision history
8
Revision history
Table 11. Document revision history
Date
Revision
Changes
24-Oct-2007
30-Oct-2007
1
2
Initial release.
Modified the device codes on page 1.
Added the M36W0R5040U4 and M36W0R5040L4 root part numbers
and all their associated data throughout this document. Applied
Numonxy branding.
26-Mar-2008
3
Replaced the M69KM048AB with M69KM048A everywhere in the
document. Corrected the product version in Table 10: Ordering
information scheme.
29-Apr-2008
20-May-2008
17-Jul-2008
4
5
6
Changed the maximum flash frequency from 86 MHz to 66 MHz on
page 1.
Changed the ambient operating temperature from -25 to -30 in
Table 5: Absolute maximum ratings and Table 6: Operating and AC
measurement conditions.
27/28
M36W0Rx0x0UL4
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
28/28
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