M39P0R9070E2ZADF_技术文档

M39P0R8070E2

M39P0R9070E2

256 or 512Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory

128 Mbit Low Power SDRAM, 1.8V supply, Multi-Chip Package

Feature summary

■ Multi-Chip Package

– 1 die of 256 (16Mb x 16) or 512 Mbit (32Mb

FBGA

x 16, Multiple Bank, Multi-Level, Burst)

Flash memory

– 1 die of 128 Mbit (4 Banks of 2Mb x16) Low

Power Synchronous Dynamic RAM

TFBGA105 (ZAD)

9 x 11mm

■ Supply voltage

– V

= V

= 1.7 to 1.95V

DDQ

DDF

PPF

DDS

= 9V for fast program

■ 100,000 program/erase cycles per block

■ Electronic signature

■ Security

– Manufacturer Code: 20h

– 256 Mbit Device Code: 8818

– 512 Mbit Device Code: 8819

– 64-bit unique device number

– 2112-bit user programmable OTP Cells

■ Block locking

■ Package

– All Blocks locked at power-up

– Any combination of Blocks can be locked

with zero latency

– ECOPACK® (RoHS compliant)

Flash memory

– WP for Block Lock-Down

– Absolute Write Protection with V

F

■ Synchronous / Asynchronous Read

= V

SS

PPF

– Synchronous Burst Read mode:

108MHz, 66MHz

■ Common Flash Interface (CFI)

– Asynchronous Page Read mode

– Random Access: 96ns

LPSDRAM

■ 128 Mbit Synchronous Dynamic RAM

■ Programming time

– Organized as 4 Banks of 2 MWords, each

16 bits wide

– 4.2µs typical Word program time using

Buffer Enhanced Factory Program

command

■ Synchronous Burst Read and Write

– Fixed burst lengths: 1, 2, 4, 8 Words or Full

Page

■ Memory organization

– Burst Types: Sequential and Interleaved

– Maximum Clock frequency: 104MHz

– Multiple Bank memory array: 32 Mbit

Banks (256Mb devices); 64 Mbit Banks

(512Mb devices)

■ Automatic and controlled Precharge

– Four Extended Flash Array (EFA) Blocks of

64 Kbits

■ Low power features:

– Partial Array Self Refresh (PASR)

– Automatic Temperature Compensated Self

Refresh (TCSR)

■ Dual operations

– program/erase in one Bank while read in

others

– Driver Strength (DS)

– No delay between read and write

operations

– Deep Power-Down Mode

■ Auto Refresh and Self Refresh

November 2007

Rev 2

1/24

www.numonyx.com

1

Contents

M39P0R8070E2, M39P0R9070E2

Contents

1

2

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash memory Chip Enable Input (E_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Flash memory Output Enable (G_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash memory Write Enable (W_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash memory Write Protect input (WP_F) . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash memory Reset (RP_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Flash memory Deep Power-Down (DPD_F) . . . . . . . . . . . . . . . . . . . . . . . . 11

2.10 Flash memory Latch Enable (L_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.11 Flash memory Clock (K_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.12 Flash memory Wait (WAIT_F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.13 LPSDRAM Chip Select (E_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.14 LPSDRAM Column Address Strobe (CAS_S) . . . . . . . . . . . . . . . . . . . . . . 12

2.15 LPSDRAM Row Address Strobe (RAS_S) . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.16 LPSDRAM Write Enable (W_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.17 LPSDRAM Clock input (K_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.18 LPSDRAM Clock Enable (KE_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.19 LPSDRAM Lower/Upper Data Input/Output Mask (LDQM_S/UDQM_S) . . . 13

2.20 Flash memory V_DDFsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.21 LPSDRAM V_DDSsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.22

V_DDQsupply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.23 Flash memory V_PPFProgram supply voltage . . . . . . . . . . . . . . . . . . . . . . 14

2.24 V_SSground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

4

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/24

M39P0R8070E2, M39P0R9070E2

Contents

5

6

7

8

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/24

List of tables

M39P0R8070E2, M39P0R9070E2

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data . . . . . . . . . . 21

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4/24

M39P0R8070E2, M39P0R9070E2

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 20

5/24

Summary description

M39P0R8070E2, M39P0R9070E2

1

Summary description

The M39P0R8070E2 and M39P0R9070E2 combine two memory devices in a Multi-Chip

Package:

●

256-Mbit (M58PR256J) or 512-Mbit (M58PR512J) Multiple Bank Flash memory

●

128-Mbit Low Power Synchronous DRAM (the M65KA128AE)

The purpose of this document is to describe how the two memory components operate with

respect to each other. It should be read in conjunction with the M58PRxxxJ and

M65KA128AE datasheets, where all specifications required to operate the Flash memory

and LPSDRAM components are fully detailed. These datasheets are available from your

local Numonyx distributor.

Recommended operating conditions do not allow more than one memory to be active at the

same time.

The memory is offered in a Stacked TFBGA105 package. It is supplied with all the bits

erased (set to ‘1’).

6/24

M39P0R8070E2, M39P0R9070E2

Figure 1. Logic diagram

Summary description

V

DDS

DDF

V

PPF

DDQ

16

A0-Amax⁽¹⁾

BA0-BA1

DQ0-DQ15

2

E

F

WAIT

F

G

F

W

F

RP

F

WP

F

L

F

M39P0R8070E2

M39P0R9070E2

K

F

DPD

F

E

S

W

S

KE

S

K

S

RAS

CAS

S

UDQM

S

LDQM

S

V

SS

Ai12813

1. Amax is A23 in the M39P0R8070E2 and A24 in the M39P0R9070E2.

7/24

Summary description

M39P0R8070E2, M39P0R9070E2

Table 1.

Signal names

A0-Amax⁽¹⁾

Address Inputs

DQ0-DQ15

V_DDQ

Common Data Input/Output

Common Flash and LPSDRAM Power Supply for I/O Buffers

Flash Memory Optional Supply Voltage for Fast Program & Erase

Flash Memory Power Supply

V_PPF

V_DDF

LPSDRAM Power Supply

V

DDS

V_SS

NC

DU

Ground

Not Connected Internally

Do Not Use as Internally Connected

Flash Memory

E_F

Chip Enable input

Output Enable Input

Write Enable input

Reset input

G_F

W_F

RP_F

WP_F

Write Protect input

Latch Enable input

Burst Clock

L_F

K_F

WAIT_F

Wait Output

DPD_F

Deep Power-Down

Low Power SDRAM

E_S

Chip Enable Input

W_S

Write Enable input

K_S

LPSDRAM Clock input

KE_S

LPSDRAM Clock Enable input

Column Address Strobe Input

Row Address Strobe Input

Bank Select Inputs

CAS_S

RAS_S

BA0, BA1

UDQM_S

LDQM_S

Upper Data Input/Output Mask

Lower Data Input/Output Mask

1. A12-A23 (in the M39P0R8070E2) or A12-A24 (in the M39P0R9070E2) are Address Inputs for the Flash

memory component only.

8/24

M39P0R8070E2, M39P0R9070E2

Summary description

Figure 2.

TFBGA connections (top view through package)

1

2

3

4

5

6

7

8

9

A24/

NC

A

B

C

D

E

F

DU

A2

A4

A3

A6

A5

A7

A19

A18

A23

NC

DU

A16

A15

A14

A13

A12

A11

(1)

A17

DPD

A22

F

V

A1

SS

DDS

NC

SS

DDS

SS

V

L

F

V

A0

NC

DDF

DDS

A21

A20

WP

NC

A10

NC

W

F

NC

E

S

CAS

RAS

S

NC

A9

A8

S

KE

W

NC

E

F

RP

F

G

H

J

BA0

S

UDQM

LDQM

S

G

F

NC

BA1

S

V

K

S

V

WAIT

F

PPF

DQ2

DQ1

DU

DDQ

DDF

DDQ

V

K

F

V

SS

K

L

DQ13

DQ14

SS

DQ6

DQ4

SS

DQ3

DQ5

DQ7

DQ8

DQ9

DQ11

DQ12

M

DQ0

NC

DQ10

NC

DQ15

DU

AI12814

1. Ball A7 is NC in the M39P0R8070E2 and it is A24 in the M39P0R9070E2.

9/24

Signal descriptions

M39P0R8070E2, M39P0R9070E2

2

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connect-ed to this device.

2.1

Address inputs (A0-Amax)

Amax is equal to A23 in the M39P0R8070E2 and, to A24 in the M39P0R9070E2.

A0-A11 are common to the Flash memory and LPSDRAM components. A12-AMax are

Address Inputs for the Flash memory component only. In the Flash memory, the Address

Inputs select the cells in the memory array to access during Bus Read operations. During

Bus Write operations they control the commands sent to the Command Interface of the

Program/Erase Controller. In the LPSDRAM, the A0-A11 Address Inputs are used to select

the row or column to be made active. If a row is selected, all A0-A11 Address Inputs are

used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are

used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set

to ‘1’) during Read or Write, the Read or Write operation includes an Auto Precharge cycle.

If A10 is Low (set to ‘0’) during Read or Write, the Read or Write cycle does not include an

Auto Precharge cycle.

2.2

2.3

2.4

LPSDRAM Bank Select Address Inputs (BA0-BA1)

The BA0 and BA1 Bank Select Address Inputs are used by the LPSDRAM to select the

bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RASS,

must be Low, V , the Column Address Strobe, CAS , and W must be High, V , when

IL

S

IH

selecting the addresses. The address inputs are latched on the rising edge of the clock

signal, K .

S

Data Inputs/Outputs (DQ0-DQ15)

In the Flash memory, the Data I/O output the data stored at the selected address during a

Bus Read operation or input a command or the data to be programmed during a Bus Write

operation. In the LPSDRAM, the Data Inputs/Outputs are common to all memory

components. They output the data stored at the selected address during a Read operation,

or are used to input the data during a write operation.

Flash memory Chip Enable Input (E_F)

The Chip Enable input activates the memory control logic, input buffers, decoders and

sense amplifiers. When Chip Enable is at V and Reset is at V the device is in active

IL

IH

mode. When Chip Enable is at V the memory is deselected, the outputs are high

IH

impedance and the power consumption is reduced to the standby level. It is not allowed to

have EF and ES all at VIL at the same time, only one memory component should be enabled

at a time.

10/24

M39P0R8070E2, M39P0R9070E2

Signal descriptions

2.5

Flash memory Output Enable (G_F)

The Output Enable input controls data outputs during the Bus Read operation of the

memory.

2.6

Flash memory Write Enable (W_F)

The Write Enable input controls the Bus Write operation of the Flash memory’s Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

2.7

2.8

Flash memory Write Protect input (WP_F)

Write Protect is an input that gives an additional hardware protection for each block. When

Write Protect is at V , the Lock-Down is enabled and the protection status of the Locked-

IL

Down blocks cannot be changed. When Write Protect is at V , the Lock-Down is disabled

and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for

details).

IH

Flash memory Reset (RP_F)

The Reset input provides a hardware reset of the memory. When

Reset is at V , the memory is in reset mode: the outputs are high impedance and the

IL

current consumption is reduced to the Reset Supply Current

IDD2 (Refer to the M58PRxxxJ datasheet, for the value of IDD2). After Reset all blocks are in

the Locked state and the Configuration Register is reset. When Reset is at V , the device is

IH

in normal operation. Exiting reset mode the device enters asynchronous read mode, but a

negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied

to VRPH (refer to M58PRxxxJ datasheet).

2.9

Flash memory Deep Power-Down (DPD_F)

The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode.

When the Flash memory is in Standby mode and the Enhanced Configuration Register bit

ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the

Deep Power-Down mode.

When the device is in the Deep Power-Down mode, the memory cannot be modified and the

data is protected.

The polarity of the DPD pin is determined by ECR14. The Deep Power-Down input is active

F

Low by default.

11/24

Signal descriptions

M39P0R8070E2, M39P0R9070E2

2.10

2.11

2.12

Flash memory Latch Enable (L_F)

The Latch Enable input latches the address bits on its rising edge. The address latch is

transparent when Latch Enable is at V and it is inhibited when Latch Enable is at V . Latch

IL

IH

Enable can be kept Low (also at board level) when the Latch Enable function is not required

or supported.

Flash memory Clock (K_F)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at V . Clock is ignored during asynchronous

IL

read and in write operations.

Flash memory Wait (WAIT_F)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at V , Output

IH

Enable is at V , or Reset is at V . It can be configured to be active during the wait cycle or

IH

IL

one data cycle in advance.

2.13

2.14

2.15

LPSDRAM Chip Select (E_S)

The Chip Select input E activates the LPSDRAM state machine, address buffers and

S

decoders when driven Low, V . When High, V , the device is not selected.

IL

IH

LPSDRAM Column Address Strobe (CAS_S)

The Column Address Strobe, CAS , is used in conjunction with Address Inputs A8-A0 and

S

BA1-BA0, to select the starting column location prior to a Read or Write.

LPSDRAM Row Address Strobe (RAS_S)

The Row Address Strobe, RAS , is used in conjunction with Address Inputs A11-A0 and

S

BA1-BA0, to select the starting address location prior to a Read or Write.

2.16

2.17

LPSDRAM Write Enable (W_S)

The Write Enable input, W , controls writing to the LPSDRAM.

S

LPSDRAM Clock input (K_S)

The Clock signal, K , is used to clock the Read and Write cycles. During normal operation,

S

the Clock Enable pin, KES, is High, V . The clock signal K can be suspended to switch the

IH

S

device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KE Low,

S

V .

IL

12/24

M39P0R8070E2, M39P0R9070E2

Signal descriptions

2.18

LPSDRAM Clock Enable (KE_S)

The Clock Enable, KE , pin is used to control the synchronizing of the signals with Clock

S

signal K . If KE is High, V , the next Clock rising edge is valid. When KE is Low, V , the

S

IH

S

IL

signals are no longer clocked and data Read and Write cycles are extended. KE is also

S

involved in switching the device to the Self-Refresh, Power-Down and Deep Power-Down

modes.

2.19

LPSDRAM Lower/Upper Data Input/Output Mask

(LDQM_S/UDQM_S)

Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals

used to mask the Read or Write data. The DQM latency is two clock cycles for read

operations and there is no latency for write operations.

2.20

2.21

2.22

Flash memory V_DDFsupply voltage

V

provides the power supply to the internal core of the Flash memory component. It is

DDF

the main power supply for all operations (Read, Program and Erase).

LPSDRAM V_DDSsupply voltage

V

provides the power supply to the internal core of the LPSDRAM component. It is the

DDS

main power supply for all operations (Read and Write).

V_DDQsupply voltage

VDDQ is common to the Flash memory and LPSDRAM memory components. It provides the

power supply to the I/O pins and enables all Outputs to be powered independently of V

DDF

for the Flash memory, or V

use a separate supply.

for the LPSDRAM. V

can be tied to V

or V

, or can

DDS

DDQ

DDF

DDS

13/24

Signal descriptions

M39P0R8070E2, M39P0R9070E2

2.23

Flash memory V_PPFProgram supply voltage

VPPF is both a control input and a power supply pin. The two functions are selected by the

voltage range applied to the pin. If V is kept in a low voltage range (0V to V

) V is

PP

DDQ

PP

seen as a control input. In this case a voltage lower than V

gives an absolute protection

PPLK

against program or erase, while V > V

enables these functions (see M58PRxxxJ

PP

PP1

datasheet for the relevant values). V is only sampled at the beginning of a program or

PP

erase; a change in its value after the operation has started does not have any effect and

program or erase operations continue. If V is in the range of V

it acts as a power

PP

PPH

supply pin. In this condition V must be stable until the Program/Erase algorithm is

PP

completed.

2.24

V_SSground

V

ground is common to the LPSDRAM and Flash memory components. It is the reference

SS

for the core supply. It must be connected to the system ground.

Each device in a system should have V ,V , V and V decoupled with a 0.1µF

PPH

Note:

DDF DDS

DDQ

ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors

should be as close as possible to the package). See Figure 5: AC measurement load circuit

The PCB track widths should be sufficient to carry the required V

currents.

program and erase

PPF

14/24

M39P0R8070E2, M39P0R9070E2

Functional description

3

Functional description

The LPSDRAM and Flash memory components have separate power supplies but share the

same grounds. They are distinguished by two Chip Enable inputs: E for Flash and E for

F

S

the LPSDRAM.

Recommended operating conditions do not allow more than one device to be active at a

time. The most common example is a simultaneous read operations on the Flash memory

and the LPSDRAM which would result in a data bus contention. Therefore it is

recommended to put the other devices in the high impedance state when reading the

selected device.

Figure 3.

Functional block diagram

V

PPF DDF

A12-Amax⁽¹⁾

E

F

WP

W

256 Mbit

or 512 Mbit

WAIT

F

Flash memory

K

A0-A11

G

F

RP

L

DQ0-DQ15

F

DPD

F

V

DDQ

V

DDS

BA0-BA1

E

S

W

K

S

128 Mbit

LPSDRAM

KE

S

CAS

RAS

UDQM

LDQM

S

Ai12815

V

SS

1. Amax is A23 in the M39P0R8070E2 and A24 in the M39P0R9070E2.

15/24

Functional description

M39P0R8070E2, M39P0R9070E2

Table 2.

Bus operations

A9,

A11

BA0-

BA1

(1)

(2)

Operation

E

G

W

L

RP

WAIT

KE n-1 KE n

E

RAS

CAS

W A10

S

A0-A8

DQ15-DQ0

F

S

V_IL

Data

Output

Bus Read

Bus Write

V_ILV_ILV_IH

V_ILV_IHV_IL

V_IH

(4)

(4

V_I₎_L

Data

Input

The SDRAM must be disabled.

Data

Output

Address Latch

V_ILX V_IHV_ILV_IH

or Hi-Z

(5)

Output Disable

Standby

V_ILV_IHV_IH

X

V_IHHi-Z

Hi-Z

V_IH

X

Any SDRAM operation mode is allowed.

SCA BS

Reset

V_IL

Hi-Z

Deep Power-

Down

V_IH

X

V_IHHi-Z

Hi-Z

Data

Output

Burst Read

Burst Write

V_IH

X

V_ILV_IH

V_ILV_IHV_IL

V

(6)

(7)

SCA BS

Data

Input

The Flash memory must be

disabled.

X

V_ILV_IH

V_ILV_ILV_IL

V

(6)

(7)

Self Refresh

Auto Refresh

V_IH

V_ILV_ILV_IL

V_IHV_ILV_IL

V_ILV_IH

X

–

X

V_ILV_IHV_IHV_IH

Power-Down

with Precharge

V_IH

V_IL

X

–

V_IH

X

Any Flash memory operation

mode is allowed.

Deep Power-

Down

V_ILV_ILV_IHV_IHV_IL

X

Device Deselect

No Operation

V_IH

X

V_IH

X

–

V_ILV_IHV_IHV_IH

1. X = Don't care, V = Valid.

2. WAIT_Fsignal polarity is configured using the Set Configuration Register command.

3. For further details, refer to the M58PRxxxJ and M65KA128AE datasheets.

4. L_Fcan be tied to V_IHif the valid address has been previously latched.

5. Depends on G_F

6. SCA = Start Column Address.

7. BS = Bank Select.

16/24

M39P0R8070E2, M39P0R9070E2

Maximum rating

4

Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the Numonyx SURE Program

and other relevant quality documents.

Table 3.

Symbol

Absolute maximum ratings

Parameter

Value

Unit

Min

Max

T_A

T_J

Ambient Operating Temperature

–25

85

°C

SDRAM Operating Junction

Temperature

–25

85

T_BIAS

T_STG

V_IO

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

–25

–55

85

125

2.3

°C

V

–0.5

–1.0

–0.5

–1.0

V_DDF

V_DDS

V_DDQ

V_PPF

I_O

3.0

V

LPSDRAM Supply Voltage

Input/Output Supply Voltage

Program Voltage

2.3

V

2.3

V

11.5

100

V

Output Short Circuit Current

Time for V_PPat V_PPH

mA

hours

t_VPPH

17/24

DC and AC parameters

M39P0R8070E2, M39P0R9070E2

5

DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 4: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Table 4.

Operating and AC measurement conditions

Flash memory

Parameter⁽¹⁾

LPSDRAM

Unit

Min

Max

Min

Max

V_DDFSupply Voltage

V_DDSSupply Voltage

1.7

–

1.95

–

V

1.7

–

1.95

–

V

_DDQSupply Voltage

V_PPFSupply Voltage (Factory environment)

_PPFSupply Voltage (Application

1.7

8.5

1.95

9.5

V

–0.4

–25

V_DDQ+0.4

85

–

V

environment)

Ambient Operating Temperature

Load Capacitance (C_L)

–25

85

°C

pF

Ω

30

Output Impedance (Z₀)

50

Output Circuit Protection Resistance (R)

Input Rise and Fall Times

Input Pulse Voltages

Ω

3

0.5

–

ns

V

0 to V_DDQ

0.3V_DDQ0.7V_DDQ

Output Timing Ref. Voltages

1. All voltages are referenced to V_SS= 0V.

V_DDQ/2

V

Figure 4.

AC measurement I/O waveform

V

DDQ

0V

V

/2

DDQ

AI06161

18/24

M39P0R8070E2, M39P0R9070E2

Figure 5. AC measurement load circuit

DC and AC parameters

V

/2

DD

R

DEVICE

UNDER

TEST

OUT

Z

0

C

L

C

includes probe capacitance

AI12818

L

(1)

Table 5.

Symbol

Capacitance

Parameter

Test Condition

Min

Max

Unit

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V

–

12

15

pF

C_OUT

V_OUT= 0V

1. Sampled only, not 100% tested.

Please refer to the M65KA128AE and M58PRxxxJ datasheets for further DC and AC

characteristic values and illustrations.

19/24

Package mechanical

M39P0R8070E2, M39P0R9070E2

6

Package mechanical

In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®

packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

Figure 6.

TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline

D

D1

FD

e

ddd

SE

E

E1

BALL "A1"

FE

A2

e

b

A

A1

BGA-Z79

1. Drawing is not to scale.

20/24

M39P0R8070E2, M39P0R9070E2

Package mechanical

Table 6.

Symbol

TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data

millimeters

Min

inches

Min

Typ

Max

Typ

Max

A

1.20

0.047

A1

A2

b

0.20

0.008

0.80

0.35

9.00

6.40

0.031

0.014

0.354

0.252

0.30

8.90

0.40

9.10

0.012

0.350

0.016

0.358

D

D1

ddd

E

0.10

0.004

0.437

11.00

8.80

0.80

1.30

1.10

0.40

10.90

–

11.10

0.433

0.346

0.031

0.051

0.043

0.016

0.429

–

E1

e

–

FD

FE

SE

21/24

Part numbering

M39P0R8070E2, M39P0R9070E2

7

Part numbering

Table 7.

Example:

Ordering information scheme

M39

P

0

R

9

0

7

0

E

2

ZAD E

Device Type

M39 = Multi-Chip Package (Flash + LPSDRAM)

Flash 1 Architecture

P = Multi-Level, Multiple Bank, Large Buffer

Flash 2 Architecture

0 = No Die

Operating Voltage

R = V_DDF= V_DDS= V_DDQ= 1.7 to 1.95V

Flash 1 Density

8 = 256 Mbits

9 = 512 Mbits

Flash 2 Density

0 = No Die

RAM 1 Density

7 = 128 Mbit

RAM 0 Density

0 = No Die

Parameter Blocks Location

E = Even Block Flash Memory Configuration

Product Version

2 = 90nm Flash technology, 96ns speed; LPSDRAM

Package

ZAD = stacked TFBGA105 D stacked footprint.

Option

E = ECOPACK® Package, Standard packing

F = ECOPACK® Package, Tape & Reel packing

Note:

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of

available options (Speed, Package, etc.) or for further information on any aspect of this

device, please contact the Numonyx Sales Office nearest to you.

22/24

M39P0R8070E2, M39P0R9070E2

Revision history

8

Revision history

Table 8.

Date

Document revision history

Revision

Changes

03-Apr-2006

14-Sep-2006

30-Nov-2007

0.1

Initial release.

Document status promoted from Target specification to full

Datasheet.

1

2

LPSDRAM Power-up removed from Table 2: Bus operations.

Applied Numonyx branding.

23/24

M39P0R8070E2, M39P0R9070E2

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

24/24


型号：	M39P0R9070E2ZADF
厂家：	NUMONYX B.V
描述：	256 or 512Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 128 Mbit Low Power SDRAM, 1.8V supply, Multi-Chip Package 256或512Mbit的（ X16 ，多银行，多层次，突发）闪存128兆位低功耗SDRAM的1.8V电源，多芯片封装闪存存储内存集成电路动态存储器
文件：	总24页 (文件大小：479K)
中文：	中文翻译
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M39P0R9070E2ZADF [NUMONYX]

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