M58BF008D90T3 [NUMONYX]
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| 型号： | M58BF008D90T3 |
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NUMONYX B.V |
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M58BF008
8 Mbit (256Kb x32, Burst) Flash Memory
TARGET SPECIFICATION
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 5V for Program, Erase and Read
DD
– V
= 3.3V for I/O Buffers
DDQ
– V = 12V for fast Program (optional)
PP
■ CONFIGURABLE OPTIONS
– Synchronous or Asynchronous write mode
– Burst Wrap
BGA
– Critical Word X (3 or 4) and Burst Word
Y (1 or 2) latency times
LBGA80 (ZA)
10 x 8 solder balls
PQFP80 (T)
■ ACCESS TIME
– Synchronous X-Y-Y-Y Burst Read
up to 40MHz
– Asynchronous Read: 90ns
■ PROGRAMMING TIME: 10µs typical
■ MEMORY BLOCKS
Figure 2. Logic Diagram
V
V
V
DD DDQ PP
– 32 equal Main blocks of 256 Kbit
– One Overlay block of 256 Kbit
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F0h
18
32
A17-A0
DQ31-DQ0
CLK
RP
E
– Version Code: 0-7h
G
M58BF008
GD
W
LBA
WR
BAA
V
V
SSQ
SS
AI02656B
January 2001
1/39
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
M58BF008
DESCRIPTION
The M58BF008 is a family of 8 Mbit non-volatile
Flash memories that can be erased electrically at
the blocklevel and programmed in-system. Family
members are configured during product testing for
a specific Synchronous or Asynchronous Write
mode, a Burst Wrap and for Critical Word X = 3 or
4 and Burst Word Y = 1 or 2 latency times. The
Main memory array matrix allows each of the 32
equal blocks of 256 Kbit to be erased separately
and re-programmed without affecting other blocks.
The memory features a 256 Kbit Overlay block
having the same address space as the Main block
0. The Overlay block provides a secure storage
area that is controlled by special Instructions and
- Program Main memory or Overlay memory
- Program Erase Suspend or Resume
Toggle:
– Asynchronous/Synchronous Read
– Overlay Block Read Enable/Disable
The M58BF008 devices are offered in PQFP80
and LBGA80 1.0mm ball pitch packages.
Table 1. Signal Names
A0-A17
DQ0-DQ31
CLK
RP
Address Inputs
Data Input/Output
System Clock
an external input. A separate supply V
allows
DDQ
the Input/Output signals to be at 3.3V levels, while
the main supply V is 5V.
DD
Reset/Power-down
Chip Enable
When the V supply is at V this prevents pro-
PP
SS
gramming and erasure of the memory blocks and,
in addition, it prevents reading of the Overlay
E
block. When the V
supply is at 5V it enables
PP
G
Output Enable
Output Disable
Write Enable
both in-system program/erase and read access to
the Overlay block. For a limited time and number
GD
of program/erase cycles the V supply may be
PP
raised to 12V to provide fast program and erase
W
times.
LBA
WR
Load Burst Address
Write/Read
A Command Interface decodes the Instructions
written to the memory to access or modify the
memory content, to toggle the enable/disable of
read access to the Overlay block, to toggle the
Synchronous or Asynchronous Read mode. A
Program/Erase Controller (P/E.C.) executes the
algorithms taking care of the timings necessary for
program and erase operations. The P/E.C. also
takes care of verification to unburden the system
microprocessor, while a Status Register tracks the
status of each operation.
BAA
Burst Address Advance
Supply Voltage
V
DD
Supply Voltage for Input/Output
Buffers
V
DDQ
Optional Supply Voltage for Fast
Program and fast Erase Operations
V
PP
The following Instructions are executed by the
memory in either Asynchronous or Synchronous
mode.
Access or modify memory content:
- Read Array
- Read or Clear Status Register
- Read Electronic Signature
- Erase Main memory block or Overlay block
V
V
Ground
SS
Input/Output Ground
Don’t Use as Internally Connected
Not Connected Internally
SSQ
DU
NC
2/39
M58BF008
Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A16
A15
A13
A11
A9
A8
A4
A3
A17
DQ1
A14
DQ2
DQ3
DQ5
DQ6
DQ9
DQ12
DQ13
RP
A12
A10
A7
A6
A0
A1
A5
A2
DQ0
V
V
DQ31
DQ28
DQ27
DQ25
DQ24
DQ19
DQ17
DQ16
DD
SS
DQ4
V
DU
DU
DU
V
V
DQ30
DQ29
DQ26
DQ23
DQ201
DQ21
DU
DDQ
PP
DDQ
DQ7
V
DU
DU
DU
V
V
V
SSQ
DDQ
SSQ
SSQ
DQ8
V
G
H
J
DQ10
DQ11
DQ14
DQ15
V
V
DDQ
SSQ
DDQ
BAA
CLK
LBA
V
V
DQ22
SS
DD
G
W
DQ18
GD
K
E
WR
AI02668
3/39
M58BF008
Figure 4. PQFP Connections
73
DQ16
DQ17
DQ18
DQ19
1
DQ15
DQ14
DQ13
DQ12
V
V
SSQ
DDQ
V
V
SSQ
DDQ
DQ20
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
12
M58BF008
53
V
V
SSQ
DDQ
V
SSQ
V
DDQ
DQ28
DQ3
DQ2
DQ1
DQ0
NC
DQ29
DQ30
DQ31
DU
A0
NC
A1
A17
A16
A2
32
AI02661
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
T
–40 to 125
–40 to 125
–55 to 150
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input Output Voltage
Supply Voltage
T
BIAS
T
STG
V
–0.6 to V
+0.6
IO
DDQ
–0.6 to 7
V
, V
DD DDQ
V
V
Program Voltage
–0.6 to 13.5
V
PP
Note: 1. Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device.
4/39
M58BF008
ORGANIZATION
The M58BF008 has a data path width of 32 bit
(Double-Word) and is organised as a Main memo-
ry array of 32 blocks of 256 Kbit plus an Overlay
block of 256 Kbit having the same address space
as the Main block 0. The memory map is shown in
Table 3.
The memory is addressed by A0-A17 which are
static for Asynchronous or latched for Synchro-
nous operation. Data Input/Output is static or
latched on DQ0-DQ31, these signals output data,
status orsignatures read from the memory, or they
input data to be programmed or Instruction com-
mands to the Command Interface.
Table 3. Block Addresses
Size
(Kbit)
#
Address Range
31
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
3E000-3FFFF
3C000-3DFFF
3A000-3BFFF
38000-39FFF
36000-37FFF
34000-35FFF
32000-33FFF
30000-31FFF
2E000-2FFFF
2C000-2DFFF
2A000-2BFFF
28000-29FFF
26000-27FFF
24000-25FFF
22000-23FFF
20000-21FFF
1E000-1FFFF
1C000-1DFFF
1A000-1BFFF
18000-19FFF
16000-17FFF
14000-15FFF
12000-13FFF
10000-11FFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
00000-01FFF
30
29
28
27
26
25
Asynchronous mode
Memory control is provided by Chip Enable E, Out-
put Enable G, Output Disable GD and Write En-
able W for read and write operations.
24
23
Synchronous mode
22
Memory control is provided by Load Burst Address
LBA which loads a read or write address. A Syn-
chronous Single Read or a Synchronous Burst
Read is performed under control of Output Enable
G and Output Disable GD. Synchronous Write is
controlled by Write/Read Enable WR, Load Burst
Address LBA and Write Enable W. Internal ad-
vance of the burst address is controlled by Burst
Address Advance BAA.
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Overlay Block
5/39
M58BF008
SIGNAL DESCRIPTIONS
See Figure 2 and Table 1.
Reset/Power-down has a weak pull-up resistor to
V
and will assume a high level if not externally
DDQ
connected.
Address Inputs (A0-A17). The address signal
A17 is the MSB and A0 the LSB.
In the Asynchronous mode the addresses must be
stable before Chip Enable E and Write Enable W
Chip Enable (E). When the Chip Enable E input
is at V it activates the memory control logic, input
IL
buffers, decoders and sense amplifiers. When
go to V . They must remain stable during the read
IL
Chip Enable E is at V the memory is deselected
IH
or write cycle.
and the power consumption is reduced to the
standby level.
In the Synchronous modes, the addresses are
latched by the rising edge of the System Clock
CLK when both Latch Burst Address LBA and
Output Enable (G). Output Enable G controls the
data output buffers with the combination of GD
(see Table 4). In the Asynchronous mode data is
Chip Enable E are at V . The addresses are
IL
latched for a read operation if Write/Read WR is at
output when Output Enable G is at V . In the Syn-
IL
V
or for a write operation when it is at V .
IH
IL
chronous mode, Output Enable G is sampled on
the rising edge of the System Clock CLK. If Output
Data Input/Output (DQ0-DQ31). The data signal
DQ31 is the MSB and DQ0 the LSB. Commands
are input on DQ0-DQ7.
Enable E is at V then valid output data on DQ0-
IL
DQ31 can be read at the next rising edge of the
Data input is a Double-Word to be programmed in
the memory or an Instruction command to the
Command Interface. Data is read from the Main or
Overlay memory blocks, the Status Register or the
Electronic Signature.
System Clock CLK.
Table 4. Data Output Contol
G
GD
DQ0-DQ31
Hi-Z
In the Asynchronous mode data is read when the
addresses are stable and Chip Enable E and Out-
V
V
IH
IH
put Enable G are at V and Output Disable GD is
V
V
V
Active
Hi-Z
IL
IL
IH
at V . Commands or address/data are written
IH
V
IH
IL
when Chip Enable E and Write W are at V .
IL
In the Synchronous mode, after addresses are
latched, data is read on a rising edge of the Sys-
V
V
Hi-Z
IL
IL
tem Clock CLK when Chip Enable E is at V and
IL
if Output Enable was at V on the previous rising
clock edge. Data is written on a rising edge of the
System Clock CLK when Chip Enable E and Write
IL
Output Disable (GD). In
mode the data outputs DQ0-DQ31 are high imped-
ance when Output Disable GD is at V , irrespec-
the
Asynchronous
IL
Enable W are at V .
IL
tive of the state of Output Enable G. In
Synchronous mode Output Disable GD is sam-
pled, together with Output Enable G, on the rising
edge of the System Clock CLK. If Output Disable
The outputs are high impedance when Chip En-
able E or Output Enable G are at V , or when Out-
IH
put Disable GD is at V . Outputs are also high
IL
impedance when System Reset RP is at V .
is at V then the data outputs DQ0-DQ31 are high
IL
IL
impedance at the next rising edge of the System
Clock CLK, irrespective of the state of Output En-
able G.
System Clock (CLK). During synchronous read/
write modes, signals are input and output relative
to the System Clock. Input signals must respect
the set-up and hold times relative to the System
Clock rising edge.
Output Disable has a weak pull-up resistor to
V
DDQ
and will assume a high level if not externally
connected.
Reset/Power-down (RP). The
down RP input provides a hardware reset for the
memory. When Reset/Power-down RP is at V
the memory is reset and in the Power-down mode.
In this mode the outputs are high impedance and
the current consumption is minimised. When Re-
Reset/Power-
Write Enable (W). The Write Enable W input
controls the writing of commands or input data. In
the Asynchronous Write mode commands or data
are written when Chip Enable E and Write Enable
IL
W are at V . In the Synchronous Write mode with
IL
set/Power-down RP is at V the memory is in the
Chip Enable E at V , input data is sampled if Write
IH
IL
normal operating mode. When leaving the Power-
down mode the memory enters the Asynchronous
Read Array mode and the VPP voltage level is
sampled to decide if the overlay block is enabled.
Enable W is at V onthe rising edge of the System
Clock CLK.
IL
6/39
M58BF008
Load Burst Address (LBA). In the Asynchro-
nous read/write mode Load Burst Address LBA is
Don’t Care (but if it falls during an asynchronous
read then a new read cycle is started). In the Syn-
chronous mode Load Burst Address LBA enables
latching of the burst starting address for Synchro-
nous read or write. The address is latched on the
rising edge of the System Clock CLK if Load Burst
V
Input/Output Supply Voltage. The Input/
DDQ
Output supply V
provides the power for the in-
DDQ
put/outputs of the memory, independent from the
supply V . The Input/Output supply V may
be connected to the V
separate supply of 3.0 to 3.6V.
DD
DDQ
supply or it can use a
DD
V
PP
Program/Erase Supply Voltage. The Pro-
gram/Erase supply V is used for programming
PP
Address LBA is at V .
IL
and erase operations. The memory normally exe-
cutes program and erase operations at the supply
Write/Read (WR). Write/Read WR is used to
control the synchronous write or read mode oper-
V
PP1
voltage levels.
ations. If Load Burst Address LBA is at V and
IL
In a manufacturing environment, programming
may be speeded up by applying a higher V lev-
Write/Read is at V then the rising edge of the
IL
PPH
System Clock CLK latches a write address. If
el to the V Program/Erase Supply. This is not in-
PP
Write/Read is at V then a read address is
IH
tended for extended use. The V
supply may be
PPH
latched. In asynchronous read and write mode WR
doesn’t affect the status of the device.
applied for a total of 80 hours maximum and during
program and erase for a maximum of 1000 cycles.
Stressing the device beyond these limits could
damage the device.
Write/Read has a weak pull-up resistor to V
DDQ
and will assume a high level if not externally con-
nected.
When V
Program/Erase supply is at V
all
SS
PP
Burst Address Advance (BAA). When
Burst
blocks are protected from programming or erase.
Address Advance BAA is at V , the rising edge of
Leaving V floating is equivalent to connecting it
IL
PP
the System Clock CLK advances the burst ad-
to V due to an internal pull-down circuit.
The overlay block can be entered in read mode
SS
dress. When Burst Address Advance BAA isat V
IH
the advance is suspended.
only if V is in the range from V
to V
.
PP
PPL
PPH
V
Supply Voltage. The supply V provides
DD
DD
Ground (V and V
). The Ground V is the
SS
SS
SSQ
the power to the internal circuits of the memory.
reference for the internal supply voltage V . The
DD
The V supply voltage is 4.5 to 5.5V.
DD
Ground V
is the reference for the Input/Output
SSQ
supply V
.
DDQ
DEVICE OPERATIONS
See Table 5 for Asynchronous or Synchronous
Bus Operations.
Read. Read operations are used to output the
contents of the memory, the Electronic Signature
or the Status Register. The data read depends on
the previous Instruction given to the memory.
Read operations can be Asynchronous or Syn-
chronous, witha single or burst read. On power-up
the device is in Asynchronous read mode, the In-
struction Asynchronous/Synchronous Read Tog-
gle ART can be used to enter the Synchronous
read mode.
In the Asynchronous read/write mode the memory
is selected with Chip Enable E Low. The data out-
puts are enabled by Output Enable G Low or dis-
abled by Output Disable GD Low. Data is input by
Write Enable W Low.
In the Synchronous read/write mode the memory
latches addresses and data (input or output) on
the rising edge of the System Clock CLK. Burst ad-
dress latching is enabled by Load Burst Address
LBA Low with Write/Read WR Low for a write cy-
cle or High for a read cycle.
Data outputs are enabled for reading on the rising
edge of the System Clock CLK when Output En-
able G is low. Data is input on the rising edge of
the System Clock CLK when Write Enable W is
Low.
– Asynchronous Read. To read a data Double-
Word in Asynchronous mode the address inputs
must be stable and Chip Enable E must be Low
during the read cycle. Output Enable G must be
Low and Output Disable GD High. The Load
Burst Address LBA is Don’t Care, but its falling
edge will start a new read cycle.
– Synchronous Single Read. To read a single
data Double-Word in Synchronous mode Chip
Enable E must be Low. Load Burst Address
LBA must be Low for one System Clock CLKris-
ing edge with Write/Read WR High. This latches
the read address, after which the address bus
inputs are Don’t Care. The Output Enable G is
The memory is deselected and in standby mode
when Chip Enable E is High, and it is reset or in
power-down mode when Reset/Power-Down RP
is Low.
7/39
M58BF008
Low for a single System Clock CLK cycle. The
Double-Word of valid data is output on the next
System Clock CLK rising edge.
The Overlay Block Status bit OBS monitors the
Program/Erase supply and will be set to ’1’
V
PP
when in the range V
or V
. The Overlay
PP1
PPH
block is enabled with OBEB at ’1’ but will not be
read unless OBS status bit is also at ’1’. If it is not
then a read operation will read the contents of the
Main block 0 at the same address.
When the Overlay block is enabled for reading,
only this one block of 256 Kbit is accesible and
none of the other Main blocks may be accessed,
the address signals A13-A17 are Don’t Care.
Read Electronic Signature. The memory con-
tains three Electronic Signature codes identifying
the manufacturer, device and version, which can
be read after giving the Instruction RSIG. The
manufacturer code 00000020h is read when the
– Synchronous Burst Read. To read a burst of
four Double-Words in Synchronous mode Chip
Enable E must be Low. Load Burst Address
LBA must be Low for one System Clock CLK ris-
ing edgewith Write/Read WR High. This latches
the first address of the burst sequence, after
which the address bus inputs are Don’t Care.
The Output Enable G is driven Low before the
burst output sequence. Four Double-Words of
data are output on the subsequent System
Clock CLK rising edges if Burst Address Ad-
vance BAA is maintained Low. The address ad-
vance for synchronous burst read is suspended
if Burst Address Advance BAA goes High and
the output data remains constant. The data bus
will go high impedance on the rising edge of the
System Clock CLK after Output Enable G goes
High or GD goes Low.
address inputs A0 and A1 are at V . The device
IL
code 000000F0h is read when A0 is at V and A1
IH
is at V . The version code 0000000xh is read
IL
when A0 is at V and A1 is at V . The codes are
IL
IH
read on DQ0-DQ31, all other address signal inputs
The burst timing depends on the device config-
uration for the Critical Word X and Burst Word Y
latency times. The operation burst wrap is
shown in Table 12. The wrap sequence uses
only the address bits A0 and A1 and does not
repeat after the last Double-Word has been out-
put.
Critical Word X (3 or 4) is defined as the number
of clock periods that occours from the address
latching to the data strobe.
are Don’t Care. See Table 6.
Write. Write operations are used to give com-
mands to the memory that latch input data and ad-
dresses to program or block addresses to erase.
– Asynchronous Write. To write data in the
Asynchronous mode the address inputs must
be stable and Chip Enable E must be Low dur-
ing the write cycle. Write W must be Low and in-
put data valid on the rising edge of Write W.
Burst Word Y (1 or 2) is the number of clock pe-
riod(s) occourring from one data valid to the
next (see Figure 5).
– Synchronous Write. To write input data in
Synchronous mode Chip Enable E must be
Low. Load Burst Address LBA must be Low for
one System Clock CLK rising edge with Write/
Read WR Low. This latches the write address,
after which the address bus inputs are Don’t
Care. When Write Enable W is Low input data is
latched on the next System Clock CLK rising
edge.
Read Overlay Block. The Overlay block can be
read, as for a Main block, after it has been en-
abled. To enable the Overlay block the Overlay
Block Enable bit OBEB and the Overlay Block Sta-
tus bit OBS in the Status Register must be set to
’1’ (see Table 10).
Output Disable. The data outputs are high im-
pedance when the Output Enable G is High or
when the Output Disable GD is Low, independent
of the level on Output Enable G.
Standby. The memory is in standby when the P/
E.C. is not running, the memory is in read mode
and Chip Enable E is High. The power consump-
tion is reduced to the standby level and the outputs
are high impedance, independent of the Output
Enable G or Write Enable W inputs.
The Overlay Block Enable bit OBEB can be set to
’1’ in three ways (see Table 11):
– By Toggling the Reset/Power-Down signal RP
with the V Program/Erase supply in the range
PP
V
or V
. V out of range will reset the
PP1
PPH PP
OBEB bit to ’0’.
– By a leaving power-on reset with V Program/
PP
Erase supply in the range V
orV
. V out
PPH PP
PP1
of range will reset the OBEB bit to ’0’.
– By giving the Overlay Block Enable/Disable for
Read Instruction OBT.
If Chip Enable goes High during a program or
erase operation the device enters the standby
mode when the internal algorithm has finished.
8/39
M58BF008
Reset/Power-down. During power-down all in-
ternal circuits are switched off, the memory is de-
selected and the outputs are high impedance. The
memory isin Power-down mode when Reset/Pow-
er-down RP is Low. The power consumption is re-
duced to the power-down level, independent of the
Chip Enable E, Load Burst Address LBA, Output
Enable G or Write Enable W inputs.
If Reset/Power-down RP is pulled Low during a
program or erase operation this is aborted and the
memory content is no longer valid.
(1,2)
Table 5. Bus Operations
Operation
Asynchronous Read
Asynchronous Write
RP
CLK
X
E
LBA
X
WR
X
W
GD
G
DQ0-DQ31
Data Output
Data Input
V
V
V
V
V
IH
IL
IL
IH
IH
IL
V
V
V
V
V
V
X
X
X
IH
IL
IH
IH
V
V
V
V
V
V
Synchronous Read
X
Data Output
X
IH
IL
IL
IH
IH
IH
IL
Synchronous Address latch
Read
V
V
V
V
V
X
X
IH
IL
IH
IH
IH
IH
Synchronous Address latch
Write
V
V
V
V
V
V
V
X
IH
IL
IL
IL
IL
IH
V
V
V
V
V
V
V
Synchronous Data Write
Data Input
IH
IH
IH
IL
IH
IH
IH
V
V
V
V
V
Output Disabled by G
Output Disabled by GD
Standby
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
IL
IL
IH
V
V
X
IH
IL
V
X
X
X
X
IH
IH
Reset / Power-down
V
X
IL
Note: 1. See Device Operations, Instructions and Commands, sections for more details.
2. X=V or V
IL
IH.
Table 6. Read Electronic Signature
Code
Manufacturer
Device
RP
E
G
W
A0
A1
A2-A17
DQ0-DQ31
00000020h
000000F0h
(Note 1)
V
V
V
V
V
V
Don’t Care
Don’t Care
Don’t Care
IH
IL
IL
IL
IL
IL
IL
IH
IH
IH
IL
IL
V
V
V
V
V
V
V
V
V
IH
IH
IL
V
V
V
Version
IH
IL
IH
Note: ”x” = version level. The first version is ”0” and it can have a value up to ”7”.
1. Version code from 0h to 7h.
9/39
M58BF008
Figure 5. Burst Latencies 3-1-1-1 and 4-1-1-1
10/39
M58BF008
INSTRUCTIONS AND COMMANDS
The Instructions are listed in Tables 7 and 8. They
may be broadly divided into two types, those that
access or modify the memory content and those
that toggle a mode or function.
Read Memory Array at power-up, when exiting
from power-down. Any invalid sequence of com-
mands will also reset the Command Interface to
Read Memory Array.
A Program/Erase Controller (P/E.C.) handles all
the timing and verifies the correct execution of the
Program or Erase instructions. The P/E.C. has a
Status Register which monitors the operations and
which may be read at any time during program or
erase. The Status Register bits indicate the oper-
ation and exit status of the internal algorithms.
Table 7. Commands
Code
Command
02h
Overlay Block Erase Set-up
Overlay Block Program Set-up
04h
The V Program and Erase Supply Voltage must
PP
Overlay Block Read Enable/
Disable
06h
be within the range V
orV
for programming
PP1
PPH
or erasure. If V
out of range, the program or
PP
erase algorithms do not start and Status Register
0Dh
20h
40h
50h
Overlay Block Erase Confirm
Erase Set-up
bit V Status V will be set to ’1’.
PP
PPS
Read Memory Array (RD). The Read Memory
Array instruction consists of one write cycle giving
the command FFh at the address 00000h. Subse-
quent read operations will read the addressed lo-
cation and output the memory data. The data can
be read from the Main memory Array or the Over-
lay memory block if it is enabled.
Program Set-up
Clear Status Register
Asynchronous/Synchronous
Read Toggle
60h
Read Status Register (RSR). The Read Status
Register instruction consists of one write cycle giv-
ing the command 70h at the address 00000h. Sub-
sequent read operations will output the Status
Register contents. See Table 9 for an explanation
of the Status Register bits. The Status Register in-
dicates when a program or Erase operation is
complete and its success or failure. The Status
Register also indicates if the Overlay block is ac-
cessible for reading. The Read Status Register in-
struction may be given at any time, including while
a program or erase operation in progress.
Clear Status Register (CLRS). The Clear Status
Register instruction consists of one write cycle giv-
ing the command 50h at the address 00000h. The
Clear Status Register command clears the bits 3,
4 and 5 of the Status Registerif they have been set
to ’1’ by the P/E.C. operation. The Clear Status
Register command should be given after an error
has been detected and before any new operation
is attempted. A Read Memory Array command
should also be given before data can be read from
the memory array.
70h
90h
B0h
Read Status Register
Read Electronic Signature
Program/Erase Suspend
Program/Erase Resume or
Erase Confirm
D0h
FFh
Read Memory Array
The Instructions that access or modify the memory
content include:
– Read Memory Array (RD)
– Read Status Register (RSR) and Clear Status
Register (CLRS)
– Read Electronic Signature (RSIG)
– Erase (EE) and Overlay Block Erase (OBEE)
– Program (PG) and Overlay Block Program (OB-
PG)
– Program or Erase Suspend (PES) and Program
or Erase Resume (PER)
Read Electronic Signature (RSIG). The Read
Electronic Signature instruction consists of a first
write cycle giving the command 90h at the address
00000h. This is followed by three read operations
at addresses xxxx0h, xxxx1h and xxxx2h which
output the manufacturer, device and version
codes respectively.
The Instructions that toggle a mode or function in-
clude:
– Asynchronous/Synchronous Read mode Tog-
gle (ART)
– Overlay Block Enable/Disable function Toggle
(OBT)
Instructions are written, in one or more write cy-
cles, to the memory Command Interface (C.I.) for
decoding. The Command Interface is reset to
Erase (EE). The Erase instruction consists of two
write cycles, the first is the erase set-up command
20h at the address 00000h. This is followed by the
11/39
M58BF008
Erase Confirm command D0h written to an ad-
dress within the block to be erased. If the second
is not the Erase Confirm command the Status
Register bits 4 and 5 are set to ’1’ and the instruc-
tion aborts. While erasing is in progress only the
Read Status Registerand Erase Suspend instruc-
tions are valid.
Blocks are erased one at a time. An erase opera-
tion sets all bits in a block to ’1’. The erase algo-
rithm automatically programs all bits to ’0’ before
erasing the block to all ’1’s.
Register bit 7 is ’0’ while programming is in
progress and is set to ’1’ when it is completed. Af-
ter completion the Status Register bit 4 is set to ’1’
if there has been a programming failure.
Programming should not be attempted when the
V
Program/Erase Supply Voltage is out of the
PP
range V
or V
as the results will be uncer-
PP1
PPH
tain. The Status Register bit 3 is set to ’1’if V is
PP
not within the allowed ranges when programming
is attempted or if it falls out of the ranges during
program execution.
Read operations output the Status Register after
the erase operation has started. The Status Reg-
ister bit 7 is ’0’ while the erase is in progress and is
set to ’1’ when it is completed. After completion the
Status Register bit 5 is set to ’1’ if there has been
an erase failure.
The program operation aborts if V drops out of
PP
the allowed ranges or if Reset/Power-Down RP
falls to V . As data integrity cannot be guaranteed
IL
when the program operation is aborted, the mem-
ory block must be erased and programming re-
peated.
Erasure should not be attempted when the V
A Clear Status Register instruction must be given
to clear the Status Register bits.
PP
Program/Erase Supply Voltage is out of the range
or V as the results will be uncertain. The
V
PP1
PPH
Overlay Block Program (OBPG). The Overlay
Block Program instruction consists of two write cy-
cles, the first is the program set-up command 04h
at the address 00000h. This is followed by a sec-
ond write cycle to latch the address and data to be
programmed. This second command starts the P/
E.C.
Status Register bit 3 is set to ’1’ if V is not within
the allowed ranges when erasing is attempted or if
PP
it falls out of the ranges during erase execution.
The erase operation aborts if V drops out of the
PP
allowed range or if Reset/Power-down RP falls to
V . As data integrity cannot be guaranteed when
IL
the erase operation is aborted, the erase must be
repeated.
A Clear Status Register instruction must be given
to clear the Status Register bits.
The operation is executed as described for the
Program (PG) instruction of the Main memory ar-
ray.
While programming of the Overlay block in
progress only the Read Status Register instruction
is valid.
Overlay Block Erase (OBEE). The Overlay Block
Erase instruction consists of two write cycles, the
first is the Overlay block erase set-up command
02h at the address 00000h. This is followed by the
Overlay Block Erase Confirm command 0Dh writ-
ten to an address within the Overlay block. If the
second is not the Overlay Block Erase Confirm
command the Status Register bit 5 is set to ’1’ and
the instruction aborts. While erasing is in progress
only the Read Status Register instruction is valid.
Program/Erase Suspend (PES). As
memory
erasure takes of the order of seconds to complete
and programming a few microseconds, a Pro-
gram/Erase Suspend instruction is implemented.
Program/Erase Suspend interrupts the operations
to allow reading or programming in a block other
than one in which program or erase is suspended.
A Program/Erase Suspend instruction is accepted
only during a Program or Erase instruction. When
the Program/Erase Suspend command is written
to the Command Interface, the P/E.C. freezes the
program or erase operation. The suspended pro-
gram or erase operation may be restarted by using
the Program/Erase Resume instruction. Program/
Erase Suspend is not allowed during the Overlay
block program/erase operation and the command
is ignored.
The operation is executed as described for the
Erase (EE) instruction of the Main memory array.
A Clear Status Register instruction must be given
to clear the Status Register bits.
Program (PG). The Program instruction consists
of two write cycles, the first is the program set-up
command 40h at the address 00000h. This is fol-
lowed by a second write cycle to latch the address
and data to be programmed. This second com-
mand starts the P/E.C. A program operation can
be aborted by writing FFFFFFFFh to any address
after the program set-up command has been giv-
en. While programming is in progress only the
Read Status Register and Program Suspend in-
structions are valid.
The Program/Erase Suspend instruction consists
of one write cycle giving the command B0h at the
address 00000h.
If a program operation is in progress when the in-
struction is given, the Status Register bits 4 and 6
are set to ’1’ after it has been suspended. If an
erase operation is in progress when theinstruction
Read operations output the Status Register after
the program operation has started. The Status
12/39
M58BF008
is given, the Status Register bits 5 and 6 are set to
’1’ after it has been suspended.
resume operations are shown in Figures 13, 14,
15 and 16.
The valid instructions that may be given to the
memory while programing is suspended are
– Read Memory Array (RD)
Asynchronous/Synchronous Read Toggle (ART).
Asynchronous Read Memory Array is the memory
default at power-up or when returning from Power-
Down. To read data in Synchronous mode, either
single or burst, the Asynchronous/Synchronous
Read Toggle instruction must be used.
The Asynchronous/Synchronous Read Toggle in-
struction consists of one write cycle giving the
command 60h at the address 00000h. Two con-
secutive instructions are not recognised and an-
other Instruction, for example the Read Memory
Array, must be given before another Asynchro-
nous/Synchronous Read Toggle will be recogn-
ised.
Overlay Block Read Enable/Disable Toggle
(OBT). Read operations in the Overlay block can
be enabled or disabled using the Overlay Block
Read Enable/Disable Toggle instruction. This tog-
gle instruction consists of one write cycle giving
the command 06h at the address 00000h. Two
consecutive instructions are not recognised.
– Read Status Register (RSR)
– Read Electronic Signature (RSIG)
– Program/Erase Resume (PER)
In addition, while erasure is suspended, the Pro-
gram (PG) instruction may be given.
In Program/Erase Suspend mode the memory can
be placed in a pseudo-standby mode by taking
Chip Enable /E to VIH to reduce power consump-
tion.
Program/Erase Resume (PER). If a Program/
Erase Suspend instruction has previously been
executed, then the operation may be resumed by
giving the command D0h at the address 00000h.
The Status Register bits 4, 5 and 6 are cleared
when program or erase resumes. A Read Memory
Array instruction will output the Status Register af-
ter program or erase is resumed.
The Status Register bit 1 (OBEB) is set to ’1’ when
the Overlay block is enabled. Refer to Table 10, 11
for Overlay block access conditions.
Suggested flow charts for software that uses pro-
gramming, erasure and program/erase suspend/
13/39
M58BF008
Table 8. Instructions
1st Cycle
Address
2nd Cycle
Address.
Mne-
Instruction
monic
Cycles
Operation
Data
Operation
Data
Read Memory
RD
1+
1+
1
Write
00000h
00000h
00000h
FFh
Read Address Data Output
Read
Array
Read Status
Register
Status
RSR
Write
Write
70h
50h
Read
X
Register
Clear Status
CLRS
Register
Read Electronic
RSIG
Signature
Address
Electronic
Signature
1+++
Write
Write
Write
00000h
00000h
00000h
90h
20h
02h
Read
Write
Write
Signature
EE
Erase
2
2
Block Address
D0h
0Dh
Overlay Block
Erase
Overlay Block
Address
OBEE
Program
Address
PG
Program
2
2
Write
Write
00000h
00000h
40h
04h
Write
Write
Data Input
Data Input
Overlay Block
Program
Address
Overlay Block
Program
OBPG
Program/Erase
Suspend
PES
PER
ART
1
1
1
Write
Write
Write
00000h
00000h
00000h
B0h
D0h
60h
Program/Erase
Resume
Asynch/Synch
Read Toggle
Overlay Block
Read En/Dis
Toggle
OBT
1+
Write
00000h
06h
Read
Read Address Data Output
14/39
M58BF008
Table 9. Status Register Bits
Mne-
Logic
Level
Bit
Name
Definition
Ready
Note
monic
’1’
’0’
‘1’
Indicates the P/E.C. status, check during
Program or Erase
P/ECS
7
P/E.C. Status
Busy
Suspend
On Program/Erase Suspend instruction both
P/ECS and PESS bits are set to ‘1’.
Either ES bit or PS bit is set to ‘1’.
PESS and either ES or PS bits remain at ‘1’
until Erase Resume instruction is given.
Program/Erase
Suspend Status
PESS
ES
6
5
In Progress or
Completed
‘0’
’1’
Erase Error or
Erase Suspend
ES bit is set to ‘1’ if either PESS instruction is
given or Erase operation fails. If ES bit is ‘1’,
check PESS bit.
Erase Status
’0’
’1’
Erase Success
Program Error or
Program Suspend
PS bit is set to ‘1’ if either PESS instruction is
given or Program operation fails. If PS bit is ‘1’,
check PESS bit.
PS
4
3
Program Status
’0’
’1’
Program Success
V
V
Invalid
OK
VPPS bit is set to ‘1’ if initially V is not V
PPH
PP
PP
PP
V
Status
VPPS
nor V
are executed.
, when Program or Erase Instruction
PP
PP1
’0’
Reserved
OBEB
2
1
’1’
’0’
’1’
’0’
Enabled
Overlay Block
Enable Bit
OBEB bit is set to ‘1’ when Overlay Block is
Enabled.
Disabled
Activated
Not Activated
OBS bit is set to ‘1’ when OBEB is ‘1’ and V
Overlay Block
Status
PP
OBS
0
is in the range V
or V
.
PPH
PP1
Table 10. Read Access to Overlay Block or Main Block
V
OBEB Status Bit
OBS Status Bit
Read Access
PP
1
In the range V
or V
1
0
Overlay Block
PP1
PPH
Out of the range
1
Main Block
V
or V
PP1
PPH
0
1
X
0
Main Block
Unknown
Unknown
Not guaranteed
15/39
M58BF008
Table 11. Overlay Block Enable/Disable Bit (OBEB)
Method
OBEB Status Bit
V
PP
Prior state of
Next state of
OBEB
OBEB
In the range
or V
X
1
0
1
0
V
PP1
PPH
(1)
Toggle RP
Out of the range
or V
X
X
X
V
PP1
PPH
In the range
or V
V
PP1
PPH
Power-on-reset
Out of the range
V
or V
PP1
PPH
–
0
1
1
0
Overlay Block Read Enable/Disable instruction OBT
–
Note: 1. Toggle H-L-H for t
minimum.
PLPH
CONFIGURATION
The M58BF008 is configured during testing which
sets the default for the write and burst interface.
The settings are:
Synchronous read and back using the Asynchro-
nous/Synchronous Read Toggle Instruction.
Critical Word and Burst Word Latency Times.
Write Interface. The write interface permanently
configured at factory level to either Asynchronous
or Synchronous. Note that the read interface is not
affected by this configuration and defaults to Asyn-
chronous read at power-up, it can be toggled to
The Critical Word and Burst Word latency times
can be set permanently to
– Critical Word Latency Time X = 3 or 4
– Burst Word Latency Time Y = 1 or 2
A burst sequence is described as X-Y-Y-Y.
Table 12. Wrap Burst Sequence
First Burst Address A1-A0
Data Wrap
00
01
10
11
Double-Word 0
Double-Word 1
Double-Word 2
Double-Word 3
1
2
3
0
2
3
0
1
3
0
1
2
16/39
M58BF008
POWER CONSUMPTION
The M58BF008 places itself in one of three differ-
ent modes depending on the status of the control
signals which define decreasing levels of current
consumption. This minimises the memory power
consumption, allowing an overall decrease in the
system power consumption without affecting per-
formance. A different recovery time is, however,
linked to the different modes - see the AC timing
tables.
Power Up. The V Supply Voltage, V
Input/
Program/
DD
DDQ
Output Supply Voltage and the V
PP
Erase Supply Voltage can be applied in any order.
The memory Command Interface is reset on pow-
er-up to Read Memory Array, but a negative tran-
sition on Chip Enable E or a change of the
addresses is required to ensure valid data is out-
put.
Care must be taken to avoid writes to the memory
Active Power mode. When Chip Enable E is at
when the V Supply Voltage is above V
PP
and
DD
LKO
V and Reset/Power-Down RP is at V the mem-
V
Program/Erase Supply Voltage powers-up
IL
IH
ory is in Active Power mode. The DC characteris-
tics tables show the current consumption figures.
first. Writes can be inhibited by driving either Write
Enable W or Write/Read WR to V .
IH
Standby mode. Refer to the Device Operating
section
The memory is disabled until Reset/Power-Down
RP is up to V .
IH
Power-Down mode. Refer to the Device Operat-
ing section.
SUPPLY RAILS
Normal precautions must be taken for supply rail
decoupling. Each device in a system should have
track widths should be sufficient to carry the re-
quired program and erase currents on the V
supply.
PP
the V , V
and V
rails decoupled with a
DD
DDQ
PP
0.1µF capacitor close to the package pins. PCB
17/39
M58BF008
DC AND AC PARAMETERS
Table 13. AC Measurement Conditions
Figure 7. AC Testing Load Circuit
Input Rise and Fall Times
≤ 10ns
V
/2
DDQ
0 to V
V
Input Pulse Voltages
DDQ
/2
DDQ
1N914
Input and Output Timing Ref. Voltages
Figure 6. AC Testing Input Output Waveform
3.3kΩ
DEVICE
UNDER
TEST
V
DDQ
OUT
V
/2
DDQ
C
= 80pF
L
0V
AI00610
C
includes JIG capacitance
L
AI02657
(1)
Table 14. Capacitance (T = 25 °C, f = 1MHz)
A
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
IN
V
= 0V
= 0V
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
18/39
M58BF008
Table 15. DC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
A
DD
DDQ
Symbol
Parameter
Test Condition
0V≤ V ≤ V
Min
Max
±1
Unit
µA
I
Input Leakage Current
LI
IN
DDQ
I
0V≤ V
≤V
Output Leakage Current
±10
–600
200
25
µA
LO
OUT
DDQ
DDQ
I
0V≤ V ≤ V
IN
Input Leakage Current pull-up
Input Leakage Current pull-down
Supply Current (Async. Read)
Supply Current (Burst Read)
Supply Current (Standby)
Supply Current (Power-down)
–20
µA
LT1
I
0≤ V ≤ 12.6
PP
µA
LIVPP
I
E = V , G = V , f = 5MHz
mA
mA
µA
CC
IL
IL
I
E = V , G = V , f = 40MHz
IL IL
25
CCB
I
E = V , RP = V
10
CC1
IH
IH
I
RP = V
10
µA
CC2
IL
V
V
= V
= V
= V
= V
≥ V
≤ V
25
mA
mA
mA
mA
µA
PP
PP1
PPH
PP1
PPH
PP1
PP1
Supply Current (Program)
Program in Progress
I
CC3
25
PP
V
25
PP
Supply Current (Erase)
Erase in Progress
I
CC4
V
25
PP
I
V
V
Program Current (Read or Standby)
Program Current (Read or Standby)
Program Current (Power-down)
200
±15
5
PP
PP
PP
I
µA
PP1
PP2
I
RP = V
IL
µA
Program Current (Program)
Program in Progress
V
V
= V
= V
= V
= V
15
mA
PP
PP1
I
PP3
PP4
25
15
25
0.8
mA
mA
mA
V
PP
PPH
V
PP
PP
PP1
PPH
Program Current (Erase)
Erase in Progress
I
V
V
V
Input Low Voltage
Input High Voltage
–0.3
2
IL
V
DDQ
+0.3
V
V
IH
I
OL
= 100µA,
= V min,
DD
V
V
V
V
Output Low Voltage
Output High Voltage
0.2
OL
DD
= V
min
DDQ
DDQ
I
V
= –100µA,
OL
DD
= V min,
V
–0.2
DDQ
V
OH
DD
V
= V
min
DDQ
DDQ
Program Voltage
(Program or Erase operations)
V
V
4.5
5.5
V
V
PP1
Program Voltage
(Program or Erase operations)
11.4
12.6
PPH
V
V
Supply Voltage Lock-out
DD
1.5
1.5
V
V
LKO
V
Program Voltage Lock-out
PPLK
19/39
M58BF008
Figure 8. Asynchronous Read AC Waveforms
tAVAV
VALID
A0-A17
tAVQV
E, LBA
tELQV
tELQX
tEHQX
tEHQZ
tAXQX
G
tGLQX
tGLQV
tGHQX
tGHQZ
VALID
DQ0-DQ31
tPHQV
RP
AI03571
(1)
Table 16. Asynchronous Read AC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
DDQ
A
DD
Alt
Symbol
Parameter
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
Max
Unit
ns
t
t
RC
90
AVAV
t
t
ACC
90
ns
AVQV
(2)
t
t
Address Transition to Output Transition
Chip Enable High to Output Transition
Chip Enable Low to Output Valid
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
OH
OH
AXQX
(2)
t
EHQX
(2, 3)
t
90
20
t
CE
ELQV
(2)
t
Chip Enable Low to Output Transition
Chip Enable High to Output Hi-Z
0
0
t
LZ
HZ
ELQX
(2)
(2)
(2)
(2)
t
t
t
EHQZ
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
t
OH
GHQX
t
25
28
t
DF
GHQZ
t
t
OE
GLQV
t
0
t
OLZ
GLQX
Note: 1. See AC Testing Measurements Conditions for timing measurements.
2. Sampled only, not 100% tested.
3. G may be delayed up to t
-t
after falling edge of E without increasing t
.
ELQV
ELQV GLQV
20/39
M58BF008
Figure 9. Synchronous Single Read AC Waveforms
1
CLK
tAVCH
tCHAX
tCHCH2
A0-A17
LBA
VALID
VALID
tBLCH
tCHBH
G
E
tEHQX
tGLCH
tCHGH
tEHQZ
tELCH
tCHQV
tCHQX1
tCHQZ
tCHQX2
DQ0-DQ31
RP
VALID
tPHBL
tWRHCH
WR
AI04400
Note: 1. Add one clock period when using 4-1-1-1 read configuration.
2. If GD is at V G control is overridden and the data outputs are in HiZ.
IL
3. GD timings are t
and t
CHGDL
GDHCH.
21/39
M58BF008
Figure 10. Synchronous Burst Read AC Waveforms
Note: 1. Add one clock period when using 4-1-1-1 read configuration.
22/39
M58BF008
(1)
Table 17. Synchronous Read AC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
A
DD
DDQ
Symbol
Parameter
Min
Max
Unit
DC
System Clock Duty Cycle
45
55
%
CLK
(2)
Address Valid to System Clock High
8
8
ns
ns
ns
ns
t
AVCH
t
Burst Address Advance Low to System Clock High
Load Burst Address Low to System Clock High
System Clock High to Address Transition
BALCH
(2)
8
t
BLCH
CHAX
CHBH
(2)
(2)
3
t
System Clock High to Load Burst Address High
System Clock Data Strobe to Next Address Valid
System Clock Fall Time
3
ns
ns
ns
t
t
25
CHCH2
t
5
CHCL
(2)
System Clock High to Output Disable High
System Clock High to Output Enable High
System Clock High to Data Valid
5
5
ns
ns
ns
ns
ns
ns
t
CHGDL
(2)
t
CHGH
(2)
(2)
(2)
(2)
18
t
CHQV
System Clock High to Data Transition
System Clock High to Data Transition
System Clock High to Data Hi-Z
0
5
t
t
CHQX1
CHQX2
20
5
t
CHQZ
t
System Clock Rise Time
ns
ns
ns
CLCH
t
t
System Clock Period
25
8
CLCL
Chip Enable Low to System Clock High
ELCH
(2)
Output Disable Low to System Clock High
10
ns
t
GDHCH
(2)
Output Enable Low to System Clock High
Reset/Power-down High to Load Burst Address Low
Write/Read High to System Clock High
10
20
8
ns
ns
ns
t
GLCH
t
PHBL
t
WRHCH
Note: 1. See AC Testing Measurement Conditions for timing measurements.
2. Sampled only, not 100% tested.
23/39
M58BF008
Figure 11. Asynchronous Write AC Waveforms
tAVAV
VALID
A0-A17
00000h
tWHAX
tAVWH
G
E
tELWL
tWLWH
tWHEH
tWHWL
W
tWHQV1,2
tDVWH
tWHDX
COMMAND
or DATA
STATUS
REGISTER
DQ0-DQ31
COMMAND
tVPHWH
tQVVPL
V
PP
tPHWL
RP
WR
WRITE
WRITE
READ
AI02660
24/39
M58BF008
(1)
Table 18. Asynchronous Write AC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
A
DD
DDQ
Symbol
Alt
Parameter
Min
70
70
70
0
Max
Unit
ns
t
t
WC
Write Cycle Time
AVAV
t
t
AS
Address Valid to Write Enable High
Data Valid to Write Enable High
ns
AVWH
t
t
DS
ns
DVWH
t
t
CS
Chip Enable Low to Write Enable Low
Reset/Power-down High to Write Enable Low
ns
ELWL
t
t
70
ns
PHWL
PS
(2)
(2)
Output Valid to V out of the range V
or V
PPH
0
ns
t
PP
PP1
QVVPL
t
V
High to Write Enable High
PP
200
0
ns
ns
ns
ns
µs
t
VPS
VPHWH
t
t
Write Enable High to Address Transition
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Output Valid, Program
WHAX
AH
t
t
0
WHDX
DH
t
t
0
WHEH
CH
(3)
10
t
WHQV1
(3)
Write Enable High to Output Valid, Erase
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
2.1
30
70
sec
ns
t
WHQV2
t
t
WPH
WHWL
t
t
ns
WLWH
WP
Note: 1. See AC Testing Measurement conditions for timing measurements.
2. Sampled only, not 100% tested.
3. Time is measured to Status Register Read giving bit b7 = ’1’.
25/39
M58BF008
Figure 12. Synchronous Write AC Waveforms
CLK
tAVCH
tCHAX
A17-A0
LBA
00000h
VALID
tBLCH
tCHBH
WR
W
tWRLCH
tCHWRH
tWLCH
tQVCH
tCHWH
tCHQX
tWHQV1,2
COMMAND
or DATA
STATUS
REGISTER
DQ31-DQ0
RP
COMMAND
tPHCB
tCH1CH2
tVPHCH
V
PP
tELCH
E
WRITE
WRITE
READ
AI02659
26/39
M58BF008
(1)
Table 19. Synchronous Write AC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
A
DD
DDQ
Symbol
Parameter
Min
Max
Unit
DC
System Clock Duty Cycle
45
55
%
CLK
(2)
Address Valid to System Clock High
Load Burst Address Low to System Clock High
Command to Command
8
8
ns
ns
ns
ns
ns
ns
µs
t
t
AVCH
BLCH
(2)
t
100
3
CH1CH2
(2)
System Clock High to Address Transition
System Clock High to Load Burst Address High
System Clock Fall Time
t
CHAX
(2)
3
t
CHBH
t
5
CHCL
(3)
(3)
(2)
(2)
(2)
System Clock High to Output Valid, Program
10
2.1
5
t
t
CHQV1
CHQV2
System Clock High to Output Valid, Erase
System Clock High to Data Transition
System Clock High to Write/Read High
sec
ns
t
CHQX
3
ns
t
CHWH
System Clock High to Write Enable High
System Clock Rise Time
3
ns
ns
ns
ns
ns
ns
t
CHWRH
t
5
CLCH
t
System Clock Period
25
8
CLCL
t
Chip Enable Low to System Clock High
Reset/Power-down High to System Clock High
Data Valid to System Clock High
ELCH
t
200
PHCH
(2)
8
0
t
QVCH
(2)
(2)
(2)
(2)
Output Valid to V out of range V
or V
PPH
ns
ns
ns
ns
t
PP
PP1
QVVPL
VPHCH
V
High to System Clock High
PP
200
8
t
Write Enable Low to System Clock High
Write/Read Low to System Clock High
t
WLCH
8
t
WRLCH
Note: 1. See AC Testing Measurement conditions for timing measurements.
2. Sampled only, not 100% tested.
3. Time is measured to Status Register Read giving bit b7 = ’1’.
27/39
M58BF008
Figure 13. Reset/Power-down AC Waveforms
Reset during Read Mode
tPLPH
RP
tPHQV
tPHBL1
Reset during Program with tPLPH ≤ tPLRH
Abort
Complete
tPHWL
tPHEL
tPLRH
tPLPH
tPHBL1
RP
Reset during Program/Erase with tPLPH > tPLRH
Abort
Complete Down
tPLRH
Power
tPHWL
tPHEL
tPHBL2
tPLPH
RP
AI00624
Table 20. Reset/Power-down AC Characteristics
(T = –40 to 125°C; V = 5V ± 10% and V
= 3.3V ± 0.3V)
A
DD
DDQ
Mode
Symbol
Parameter
Min
Max
Unit
ns
t
Reset/Power-down High to Chip Enable Low
Reset/Power-down High to Output Valid
Reset/Power-down High to Write Enable Low
Reset/Power-down Pulse Width
70
PHEL
t
100
ns
PHQV
t
70
ns
Async
PHWL
(1)
100
ns
µs
ns
µs
t
PLPH
t
Reset/Power-down Low to Program Erase Abort
22
22
PLRH
t
t
Reset/Power-down High to Load Burst Address Low
Reset/Power-down High to Load Burst Address Low
20
PHBL1
PHBL2
Sync
Note: 1. The device Reset is possible but not guaranteed if t
< 100ns.
PLPH
A Reset will complete within 100ns if RP is Low while not in Program or Erase.
28/39
M58BF008
Table 21. Program, Erase Times and Program/Erase Endurance Cycles
(T = –40 to 125°C; V = 5V ± 10% and V = 3.3V ± 0.3V)
A
DD
DDQ
Test Conditions
= V
Parameter
Min
Max
Unit
Typ
0.14
0.18
0.21
0.33
V
1.4
1.8
2.1
3.3
sec
sec
PP
PPH
Main/Overlay Block Program Time
Main/Overlay Block Erase Time
Program/Erase Cycles (per Block)
V
V
= V
= V
PP
PP1
sec
PP
PPH
V
= V
sec
PP
PP
PP1
V
= V
= V
1,000
cycles
cycles
PPH
V
10,000
PP
PP1
Figure 14. Program Flowchart and Pseudo Code
Start
Write 40h/04h
Command
PG/OBPG instructions:
– write 40h/04h command
– write Address & Data
(memory enters read status
state after the PG instruction)
Write Address
& Data
Read Status
Register
do:
– read status register
(E or G must be toggled)
NO
b7 = 1
while b7 = 1
YES
NO
NO
V
Invalid
Error (1)
If b3 = 1, V
invalid error:
PP
PP
– error handler
b3 = 0
YES
Program
Error (1)
If b4 = 1, Program error:
– error handler
b4 = 0
YES
End
AI02663
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
29/39
M58BF008
Figure 15. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
Write 70h
Command
PES instruction (note 1):
– write B0h command
(memory enters read register
state after the PES instruction)
do:
Read Status
Register
– read status register
(E or G must be toggled)
NO
NO
NO
b7 = 1
YES
while b7 = 1
b6 = 1
YES
If b4 = 0, Program completed
(at this point the memory will
accept only the RD or PER instruction)
b4 = 1
YES
Program Complete
Write FFh
Command
RD instruction:
– write FFh command
– one or more data reads
from another block
Read data from
another block
Write D0h
Command
Write FFh
Command
PER instruction:
– write D0h command
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase suspend
was not issued).
Read Data
Program Continues
AI02664
Note: 1. PES instruction is not allowed during OBPG operation.
30/39
M58BF008
Figure 16. Erase Flowchart and Pseudo Code
Start
Write 20h/02h
Command
EE/OBEE instructions:
– write 20h/02h command
– write Block Address
(A12-A17) & command D0h/0Dh
(memory enters read status
state after the EE instruction)
Write Block Address
& D0h Command
do:
Read Status
Register
– read status register
(E or G must be toggled)
NO
b7 = 1
while b7 = 1
YES
NO
NO
NO
V
Invalid
If b3 = 1, V
invalid error:
PP
Error (1)
PP
– error handler
b3 = 0
YES
Command
Sequence Error
If b4, b5 = 1, Command Sequence error:
– error handler
b4, b5 = 0
YES
Erase
Error (1)
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
End
AI02680
Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.
31/39
M58BF008
Figure 17. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Command
Write 70h
Command
PES instruction (note 1):
– write B0h command
(memory enters read register
state after the PES instruction)
do:
Read Status
Register
– read status register
(E or G must be toggled)
NO
NO
NO
b7 = 1
YES
while b7 = 1
b6 = 1
YES
If b6 = 0, Erase completed
(at this point the memory wich
accept only the RD or PER instruction)
b5 = 1
YES
Erase Complete
Write FFh
Command
RD instruction:
– write FFh command
– one o more data reads
from another block
Read data from
another block
or Program
PG instruction:
– write 40h command
– write Address & Data
PER instruction:
– write D0h command
to resume erasure
Write D0h
Command
Write FFh
Command
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase suspend
was not issued).
Read Data
Program Continues
AI02681
Note: 1. PES instruction is not allowed during OBEE operation.
32/39
M58BF008
Figure 18. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE (1)
NO
90h
READ
ARRAY
YES
READ
SIGNATURE
NO
06h
YES
OBEB
TOGGLE
NO
70h
YES
READ
STATUS
NO
60h
YES
ASYNCHR./
SYNCHR.
READ MODE
TOGGLE
NO
50h
YES
CLEAR
STATUS
NO
04h
YES
PROGRAM
OB SET-UP
NO
02h
YES
ERASE
A
NO
OB SET-UP
YES
PROGRAM
OB
READY
NO
0Dh
READ
STATUS
ERASE
COMMAND
ERROR
NO
YES
ERASE
OB
READY
D
B
AI04137
Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or
if V falls below V , the Command Interface defaults to Read Array mode.
DD
LKO
2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
33/39
M58BF008
Figure 19. Command Interface and Program Erase Controller Flowchart (b)
A
C
B
NO
40h
YES
PROGRAM
SET UP
PROGRAM
(READ STATUS)
YES
READY
(2)
NO
NO
B0h
YES
READ
STATUS
PROGRAM
SUSPEND
YES
READY
(2)
NO
NO
PROGRAM
SUSPENDED
READ
STATUS
YES
YES
READ
STATUS
70h
NO
YES
NO
READ
SIGNATURE
90h
NO
YES
READ
ARRAY
READ
STATUS
D0h
(PROGRAM RESUME)
AI02684
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
34/39
M58BF008
Figure 20. Command Interface and Program Erase Controller Flowchart (c)
C
D
B
20h
NO
FFh
YES
ERASE
SET-UP
NO
D0h
ERASE
COMMAND
ERROR
YES
ERASE
(READ STATUS)
YES
READY
(2)
NO
NO
B0h
YES
READ
STATUS
ERASE
SUSPEND
ERASE
SUSPENDED
NO
YES
READY
(2)
YES
NO
YES
YES
YES
READ
STATUS
READ
70h
NO
STATUS
READ
SIGNATURE
90h
NO
PROGRAM
SET-UP
40h or
10h
c
NO
NO
YES
READ
ARRAY
READ
STATUS
D0h
(ERASE RESUME)
AI02683
Note: 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.
35/39
M58BF008
PART NUMBERING
Table 22. Ordering Information Scheme
Example:
M58BF008B
100 ZA
3
T
Device Type
M58
Architecture
B = Burst Mode
Operating Voltage
F = V = 5V ± 10%; V
= 3.0V or 3.6V
DDQ
DD
Device Function
008 = 8 Mbit (256Kb x 32), Burst
Configuration
B = Synchronous Write, Burst Wrap,
Critical Word Latency = 3
Burst Word Latency = 1
D = Synchronous Write, Burst Wrap,
Critical Word Latency = 4
Burst Word Latency = 1
Speed
90 = 90ns
Package
T = PQFP80
ZA = LBGA80: 1.0 mm pitch
Temperature Range
3 = –40 to 125 °C
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Configuration, Package, etc...) or for further information on any aspect of
this device, please contact the STMicroelectronics Sales Office nearest to you.
36/39
M58BF008
PACKAGE MECHANICAL
Figure 21. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
D
D1
D2
A2
e
b
Ne
E2 E1 E
N
1
Nd
A
CP
L1
c
A1
α
L
QFP-A
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.40
0.1339
0.25
2.55
0.30
0.11
–
0.0098
2.80
3.05
0.45
0.23
–
0.1102
0.1004
0.1201
0.0118
0.0177
c
0.0043
0.0091
D
23.90
20.00
0.80
0.9409
0.7874
0.0315
0.7047
0.5512
0.0346
3.5 °
–
–
–
D1
e
–
–
–
–
–
–
–
–
E
17.90
14.00
0.88
–
–
–
E1
L
–
–
–
–
0.73
0 °
80
1.03
7 °
0.0287
0 °
80
24
16
0.0406
7 °
α
3.5 °
N
Nd
Ne
CP
24
16
0.250
0.0098
37/39
M58BF008
Figure 22. LBGA80 - 10 x 8 balls, 1mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1 BALL ”A1”
ddd
e
e
b
A
A2
A1
BGA-Z05
Note: Drawing is not to scale.
Table 24. LBGA80 - 10 x 8 balls, 1mm pitch, Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
Max
1.700
0.450
Typ
Max
A
A1
A2
b
0.0669
0.0177
0.400
1.100
0.500
10.000
7.000
0.350
0.0157
0.0433
0.0197
0.3937
0.2756
0.0138
–
–
–
–
–
–
–
–
D
–
–
D1
ddd
e
–
–
0.150
0.0059
1.000
12.000
9.000
1.500
1.500
0.500
0.500
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.0394
0.4724
0.3543
0.0591
0.0591
0.0197
0.0197
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E
E1
FD
FE
SD
SE
38/39
M58BF008
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
39/39
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