M59DR016D100ZB6_技术文档

M59DR016C

M59DR016D

16 Mbit (1Mb x16, Dual Bank, Page)

1.8V Supply Flash Memory

PRODUCT PREVIEW

■ SUPPLY VOLTAGE

– V = V = 1.65V to 2.2V for Program,

DD

DDQ

Erase and Read

– V = 12V for fast Program (optional)

PP

■ ASYNCHRONOUS PAGE MODE READ

– Page Width: 4 words

BGA

– Page Access: 35ns

– Random Access: 100ns

TFBGA48 (ZB)

8 x 6 balls array

■ PROGRAMMING TIME

– 10µs by Word typical

– Double Word Programming Option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4 Mbit - 12 Mbit

– Parameter Blocks (Top or Bottom location)

Figure 1. Logic Diagram

■ DUAL BANK OPERATIONS

– Read within one Bank while Program or

Erase within the other

– No delay between Read and Write operations

■ BLOCK PROTECTION/UNPROTECTION

– All Blocks protected at Power Up

V

DD DDQ PP

20

16

– Any combination of Blocks can be protected

■ COMMON FLASH INTERFACE (CFI)

■ 64 bit SECURITY CODE

A0-A19

DQ0-DQ15

W

E

■ ERASE SUSPEND and RESUME MODES

M59DR016C

M59DR016D

■ 100,000 PROGRAM/ERASE CYCLES per

G

BLOCK

RP

WP

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M59DR016C: 2293h

– Bottom Device Code, M59DR016D: 2294h

V

SS

AI04106

March 2001

1/37

This is preliminary information on a new product now in development. Details are subject to change without notice.

M59DR016C, M59DR016D

Figure 2. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

A18

NC

A19

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

NC

A12

A9

A6

A3

DQ11

DQ12

DQ4

DQ2

DQ3

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI04113

Table 1. Signal Names

DESCRIPTION

The M59DR016 is a 16 Mbit non-volatile Flash

memory that may be erased electrically at block

level and programmed in-system on a Word-by-

A0-A19

Address Inputs

DQ0-DQ15

Data Input/Outputs, Command Inputs

Chip Enable

Word basis using a 1.65V to 2.2V V

supply for

DD

the circuitry. For Program and Erase operations

the necessary high voltages are generated inter-

nally. The device supports asynchronous page

mode from all the blocks of the memory array.

The array matrix organization allows each block to

be erased and reprogrammed without affecting

other blocks. All blocks are protected against pro-

gramming and erase at Power Up. Blocks can be

unprotected to make changes in the application

and then reprotected.

E

G

Output Enable

W

Write Enable

RP

WP

Reset/Power Down

Write Protect

V

DD

Supply Voltage

Instructions for Read/Reset, Auto Select, Write

Configuration Register, Programming, Block

Erase, Bank Erase, Erase Suspend, Erase Re-

sume, Block Protect, Block Unprotect, Block Lock-

ing, CFI Query, are written to the memory through

a Command Interface using standard micropro-

cessor write timings.

Supply Voltage for Input/Output

Buffers

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

V

PP

Ground

SS

The device is offered in TFBGA48 (0.75 mm pitch)

packages and it is supplied with all the bits erased

(set to ‘1’).

NC

Not Connected Internally

2/37

M59DR016C, M59DR016D

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(2)

T

–40 to 85

–40 to 125

–55 to 155

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

BIAS

T

STG

(3)

–0.5 to V

+0.5

Input or Output Voltage

V

DDQ

–0.5 to 2.7

–0.5 to 13

IO

V

, V

DD DDQ

Supply Voltage

V

Program Voltage

PP

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Depends on range.

3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Organization

Bank A, read operations are possible into Bank B

or vice versa. The memory also features an erase

suspend allowing to read or program in another

block within the same bank. Once suspended the

erase can be resumed. The Bank Size and Sector-

ization are summarized in Table 7. Parameter

Blocks are located at the top of the memory ad-

dress space for the M59DR016C, and at the bot-

tom for the M59DR016D. The memory maps are

shown in Tables 3, 4, 5 and 6.

The Program and Erase operations are managed

automatically by the P/E.C. Block protection

against Program or Erase provides additional data

security. All blocks are protected at Power Up. In-

structions are provided to protect or unprotect any

block in the application. A second register locks

the protection status while WP is low (see Block

Locking description). The Reset command does

not affect the configuration of unprotected blocks

and the Configuration Register status.

The M59DR016 is organized as 1Mb x16 bits. A0-

A19 are the address lines, DQ0-DQ15 are the

Data Input/Output. Memory control is provided by

Chip Enable E, Output Enable G and Write Enable

W inputs.

Reset RP is used to reset all the memory circuitry

and to set the chip in power down mode if this

function is enabled by a proper setting of the Con-

figuration Register. Erase and Program operations

are controlled by an internal Program/Erase Con-

troller (P/E.C.). Status Register data output on

DQ7 provides a Data Polling signal, DQ6 and DQ2

provide Toggle signals and DQ5 provides error bit

to indicate the state of the P/E.C operations.

Memory Blocks

The device features asymmetrically blocked archi-

tecture. M59DR016 has an array of 39 blocks and

is divided into two banks A and B, providing Dual

Bank operations. While programming or erasing in

3/37

M59DR016C, M59DR016D

Table 3. Bank A, Top Boot Block Addresses

M59DR016C

Table 5. Bank B, Bottom Boot Block Addresses

M59DR016D

Size

(KWord)

Size

#

Address Range

#

Address Range

(KWord)

32

14

13

12

11

10

9

4

0FF000h-0FFFFFh

0FE000h-0FEFFFh

0FD000h-0FDFFFh

0FC000h-0FCFFFh

0FB000h-0FBFFFh

0FA000h-0FAFFFh

0F9000h-0F9FFFh

0F8000h-0F8FFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

4

8

4

7

4

6

32

5

4

3

2

1

0

8

Table 4. Bank B, Top Boot Block Addresses

M59DR016C

7

6

Size

5

#

Address Range

(KWord)

32

4

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

3

2

1

0

Table 6. Bank A, Bottom Boot Block Addresses

M59DR016D

Size

(KWord)

#

Address Range

14

13

12

11

10

9

32

4

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

8

7

6

4

5

4

3

4

2

4

1

4

0

4

4/37

M59DR016C, M59DR016D

Table 7. Bank Size and Sectorization

Bank Size

Parameter Blocks

Main Blocks

Bank A

Bank B

4 Mbit

8 blocks of 4 KWord

-

7 blocks of 32 KWord

24 blocks of 32 KWord

12 Mbit

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A19). The address inputs

for the memory array are latched during a write op-

eration on the falling edge of Chip Enable E or

Write Enable W, whichever occurs last.

and the reset recovery will take a maximum ot

. The memory will recover from Power

t

PLQ7V

Down (when enabled) in t

after the rising

PHQ7V2

edge of RP. See Tables 25, 26 and Figure 9.

V

and V Supply Voltage (1.65V to 2.2V).

DD

DDQ

The main power supply for all operations (Read,

Program and Erase). V

the same voltage.

and V

must be at

DD

DDQ

Data Input/Output (DQ0-DQ15). The Input is

data to be programmed in the memory array or a

command to be written to the Command Interface

(C.I.) Both input data and commands are latched

on the rising edge of Write Enable W. The Ouput

is data from the Memory Array, the Common Flash

Interface, the Electronic Signature Manufacturer

or Device codes, the Block Protection status, the

Configuration Register status or the Status Regis-

ter Data Polling bit DQ7, the Toggle Bits DQ6 and

DQ2, the Error bit DQ5. The data bus is high im-

pedance when the chip is deselected, Output En-

V

Programming Voltage (11.4V to 12.6V). Used

PP

to provide high voltage for fast factory program-

ming. High voltage on V pin is required to use

the Double Word Program instruction. It is also

possible to perform word program or erase instruc-

PP

tions with V pin grounded.

PP

V

Ground. V is the reference for all the volt-

SS

age measurements.

DEVICE OPERATIONS

able G is at V , or RP is at V .

IH

IL

The following operations can be performed using

the appropriate bus cycles: Read Array (Random,

and Page Modes), Write command, Output Dis-

able, Standby, Reset/Power Down and Block

Locking. See Table 8.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E at V deselects

IH

the memory and reduces the power consumption

to the standby level. E can also be used to control

writing to the command register and to the memo-

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register, the CFI, the Block

Protection Status or the Configuration Register

status. Read operation of the memory array is per-

formed in asynchronous page mode, that provides

fast access time. Data is internally read and stored

in a page buffer. The page has a size of 4 words

and is addressed by A0-A1 address inputs. Read

operations of the Electronic Signature, the Status

Register, the CFI, the Block Protection Status, the

Configuration Register status and the Security

Code are performed as single asyncronous read

cycles (Random Read). Both Chip Enable E and

Output Enable G must be at V in order to read the

output of the memory.

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch Input

Data to be programmed. A write operation is initi-

ated when Chip Enable E and Write Enable W are

ry array, while W remains at V .

IL

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is at V the outputs are High im-

IH

pedance.

Write Enable (W). This input controls writing to

the Command Register and Data latches. Data are

latched on the rising edge of W.

Write Protect (WP). This input gives an addition-

al hardware protection level against program or

erase when pulled at V , as described in the Block

IL

Lock instruction description.

IL

Reset/Power Down Input (RP). The RP input

provides hardware reset of the memory (without

affecting the Configuration Register status), and/

or Power Down functions, depending on the Con-

figuration Register status. Reset/Power Down of

the memory is achieved by pulling RP to V for at

IL

at V with Output Enable G at V . Addresses are

IL

IH

least t

. When the reset pulse is given, if the

PLPH

latched on the falling edge of W or E whichever oc-

curs last. Commands and Input Data are latched

on the rising edge of W or E whichever occurs first.

Noise pulses of less than 5ns typical on E, W and

G signals do not start a write cycle.

memory is in Read, Erase Suspend Read or

Standby, it will output new valid data in t af-

PHQ7V1

ter the rising edge of RP. If the memory is in Erase

or Program modes, the operation will be aborted

5/37

M59DR016C, M59DR016D

Table 8. User Bus Operations

(1)

Operation

E

G

W

RP

WP

DQ15-DQ0

Data Input

Hi-Z

V

IH

V

IL

V

IH

V

IH

Write

IL

V

IH

V

IH

V

IH

V

IH

Output Disable

Standby

V

IH

V

IH

X

Hi-Z

IH

V

Reset / Power Down

X

Hi-Z

IL

IH

V

IH

V

Block Locking

X

IL

Note: 1. X = Don’t care.

Table 9. Read Electronic Signature (AS and Read CFI instructions)

Other

Addresses

Code

Device

E

G

W

A0

A1 A7-A2

DQ15-DQ8 DQ7-DQ0

V

IL

V

IL

V

IL

Manufacturer Code

0

Don’t Care

00h

22h

20h

93h

94h

IL

IH

IL

V

IH

M59DR016C

M59DR016D

Device Code

V

IH

Table 10. Read Block Protection (AS and Read CFI instructions)

Other

Addresses

Block Status

E

G

W

A0 A1

A19-A12

A7-A2

DQ0 DQ1 DQ15-DQ2

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

Protected Block

Unprotected Block

Locked Block

Block Address

0

Don’t Care

1

0

X

0

1

0000h

IL

IH

V

Table 11. Read Configuration Register (AS and Read CFI instructions)

DQ9-DQ0

DQ15-DQ11

RP Function

E

G

W

A0

A1 A7-A2 Other Addresses

DQ10

V

Reset

Reset/Power Down

0

Don’t Care

0

1

Don’t Care

IL

IH

V

IL

V

IL

V

IH

Dual Bank Operations. The Dual Bank allows to

read data from one bank of memory while a pro-

gram or erase operation is in progress in the other

bank of the memory. Read and Write cycles can

be initiated for simultaneous operations in different

banks without any delay. Status Register during

Program or Erase must be monitored using an ad-

dress within the bank being modified.

Automatic Standby. When in Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus.

Power Down. The memory is in Power Down

when the Configuration Register is set for Power

Output Disable. The data outputs are high im-

Down and RP is at V . The power consumption is

IL

pedance when the Output Enable G is at V with

reduced to the Power Down level, and Outputs are

in high impedance, independent of the Chip En-

able E, Output Enable G or Write Enable W inputs.

IH

Write Enable W at V .

IH

Standby. The memory is in standby when Chip

Enable E is at V and the P/E.C. is idle. The pow-

Block Locking. Any combination of blocks can

be temporarily protected against Program or

Erase by setting the lock register and pulling WP

IH

er consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable G or Write Enable W inputs.

to V (see Block Lock instruction).

IL

6/37

M59DR016C, M59DR016D

INSTRUCTIONS AND COMMANDS

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded Cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read.

CFI Query (RCFI) Instruction. Common Flash

Interface Query mode is entered writing 98h at ad-

dress 55h. The CFI data structure gives informa-

tion on the device, such as the sectorization, the

command set and some electrical specifications.

Tables 15, 19, 20 and 21 show the addresses

used to retrieve each data. The CFI data structure

contains also a security area; in this section, a 64

bit unique security number is written, starting at

address 80h. This area can be accessed only in

read mode by the final user and there are no ways

of changing the code after it has been written by

ST. Write a read instruction (RD) to return to Read

mode.

Seventeen instructions are defined (see Table

14), and the internal P/E.C. automatically handles

all timing and verification of the Program and

Erase operations. The Status Register Data Poll-

ing, Toggle, Error bits can be read at any time, dur-

ing programming or erase, to monitor the progress

of the operation.

Instructions, made up of one or more commands

written in cycles, can be given to the Program/

Erase Controller through a Command Interface

(C.I.). The C.I. latches commands written to the

memory. Commands are made of address and

data sequences. Two Coded Cycles unlock the

Command Interface. They are followed by an input

command or a confirmation command. The Coded

Sequence consists of writing the data AAh at the

address 555h during the first cycle and the data

55h at the address 2AAh during the second cycle.

Instructions are composed of up to six cycles. The

first two cycles input a Coded Sequence to the

Command Interface which is common to all in-

structions (see Table 14). The third cycle inputs

the instruction set-up command. Subsequent cy-

cles output the addressed data, Electronic Signa-

ture, Block Protection, Configuration Register

Status or CFI Query for Read operations. In order

to give additional data protection, the instructions

for Block Erase and Bank Erase require further

command inputs. For a Program instruction, the

fourth command cycle inputs the address and data

to be programmed. For a Double Word Program-

ming instruction, the fourth and fifth command cy-

cles input the address and data to be

programmed. For a Block Erase and Bank Erase

instructions, the fourth and fifth cycles input a fur-

ther Coded Sequence before the Erase confirm

command on the sixth cycle. Any combination of

blocks of the same memory bank can be erased.

Erasure of a memory block may be suspended, in

order to read data from another block or to pro-

gram data in another block, and then resumed.

When power is first applied the command interface

is reset to Read Array.

Table 12. Commands

Hex Code

00h

Command

Bypass Reset

10h

Bank Erase Confirm

Unlock Bypass

20h

30h

Block Erase Resume/Confirm

Double Word Program

40h

Block Protect, or

Block Unprotect, or

Block Lock, or

60h

Write Configuration Register

80h

90h

Set-up Erase

Read Electronic Signature, or

Block Protection Status, or

Configuration Register Status

98h

A0h

B0h

F0h

CFI Query

Command sequencing must be followed exactly.

Any invalid combination of commands will reset

the device to Read Array. The increased number

of cycles has been chosen to ensure maximum

data security.

Program

Erase Suspend

Read Array/Reset

7/37

M59DR016C, M59DR016D

Auto Select (AS) Instruction. This instruction

uses two Coded Cycles followed by one write cy-

cle giving the command 90h to address 555h for

command set-up. A subsequent read will output

the Manufacturer or the Device Code (Electronic

Signature), the Block Protection status or the Con-

figuration Register status depending on the levels

of A0 and A1 (see Tables 9, 10 and 11). A7-A2

(XBY) and Program or Double Word Program in

Bypass mode (PGBY, DPGBY) commands. The

Bypass mode allows to reduce the overall pro-

gramming time when large memory arrays need to

be programmed.

Exit Bypass Mode (XBY) Instruction. This in-

struction uses two write cycles. The first inputs to

the memory the command 90h and the second in-

puts the Exit Bypass mode confirm (00h). After the

XBY instruction, the device resets to Read Memo-

ry Array mode.

Program in Bypass Mode (PGBY) Instruc-

tion. This instruction uses two write cycles. The

Program command A0h is written to any Address

on the first cycle and the second write cycle latch-

es the Address on the falling edge of W or E and

the Data to be written on the rising edge and starts

the P/E.C. Read operations within the same bank

output the Status Register bits after the program-

ming has started. Memory programming is made

only by writing '0' in place of '1'. Status bits DQ6

and DQ7 determine if programming is on-going

and DQ5 allows verification of any possible error.

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write operation latches the

Address and the Data to be written and starts the

P/E.C. Read operations within the same bank out-

put the Status Register bits after the programming

has started. Memory programming is made only

by writing '0' in place of '1'. Status bits DQ6 and

DQ7 determine if programming is on-going and

DQ5 allows verification of any possible error. Pro-

gramming at an address not in blocks being

erased is also possible during erase suspend.

must be at V , while other address input are ig-

IL

nored. The bank address is don’t care for this in-

struction. The Electronic Signature can be read

from the memory allowing programming equip-

ment or applications to automatically match their

interface to the characteristics of M59DR016. The

Manufacturer Code is output when the address

lines A0 and A1 are at V , the Device Code is out-

IL

put when A0 is at V with A1 at V .

IH

IL

The codes are output on DQ0-DQ7 with DQ8-

DQ15 at 00h. The AS instruction also allows the

access to the Block Protection Status. After giving

the AS instruction, A0 is set to V with A1 at V ,

IL

IH

while A12-A19 define the address of the block to

be verified. A read in these conditions will output a

01h if the block is protected and a 00h if the block

is not protected.

The AS Instruction finally allows the access to the

Configuration Register status if both A0 and A1

are set to V . If DQ10 is '0' only the Reset function

IH

is active as RP is set to V (default at power-up).

IL

If DQ10 is '1' both the Reset and the Power Down

functions will be achieved by pulling RP to V . The

IL

other bits of the Configuration Register are re-

served and must be ignored. A reset command

puts the device in read array mode.

Write Configuration Register (CR) Instruc-

tion. This instruction uses two Coded Cycles fol-

lowed by one write cycle giving the command 60h

to address 555h. A further write cycle giving the

command 03h writes the contents of address bits

A0-A15 to the 16 bits configuration register. Bits

written by inputs A0-A9 and A11-A15 are reserved

for future use. Address input A10 defines the sta-

tus of the Reset/Power Down functions. It must be

Double Word Program (DPG) Instruction. This

feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. High voltage (11.4V to 12.6V) on V

PP

pin is required. This instruction uses five write cy-

cles. The double word program command 40h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write cycle latches the ad-

dress and data to be written to the first location. A

fifth write cycle latches the new data to be written

to the second location and starts the P/E.C.. Note

that the two locations must have the same address

except for the address bit A0. The Double Word

Program can be executed in Bypass mode (DPG-

BY) to skip the two coded cycles at the beginning

of each command.

set to V to enable only the Reset function and to

IL

V

to enable also the Power Down function. At

IH

Power Up all the Configuration Register bits are

reset to '0'.

Enter Bypass Mode (EBY) Instruction. This in-

struction uses the two Coded cycles followed by

one write cycle giving the command 20h to ad-

dress 555h for mode set-up. Once in Bypass

mode, the device will accept the Exit Bypass

8/37

M59DR016C, M59DR016D

(1)

Table 13. Protection States

(3)

(2)

Next State After Event

Program/Erase

Allowed

Current State

(WP, DQ1, DQ0)

Protect

101

Unprotect

100

Lock

111

011

WP transition

100

101

110

111

000

001

011

yes

no

000

001

011

100

101

100

yes

no

111

110

111

110

yes

no

001

000

001

000

(4)

no

011

111 or 110

Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by

DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = V and A0 = V .

IH

IL

3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed

its logic value.

4. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

Block Protect (BP), Block Unprotect (BU),

Block Lock (BL) Instructions. All blocks are

protected at power-up. Each block of the array has

two levels of protection against program or erase

operation. The first level is set by the Block Protect

instruction; a protected block cannot be pro-

grammed or erased until a Block Unprotect in-

struction is given for that block. A second level of

protection is set by the Block Lock instruction, and

requires the use of the WP pin, according to the

following scheme:

Additional block Erase Confirm commands and

block addresses can be written subsequently to

erase other blocks in parallel, without further Cod-

ed cycles. All blocks must belong to the same

bank of memory; if a new block belonging to the

other bank is given, the operation is aborted. The

erase will start after an erase timeout period of

100µs. Thus, additional Erase Confirm commands

for other blocks must be given within this delay.

The input of a new Erase Confirm command will

restart the timeout period. The status of the inter-

nal timer can be monitored through the level of

DQ3, if DQ3 is '0' the Block Erase Command has

been given and the timeout is running, if DQ3 is '1',

the timeout has expired and the P/E.C. is erasing

the Block(s). If the second command given is not

an erase confirm or if the Coded cycles are wrong,

the instruction aborts, and the device is reset to

Read Array. It is not necessary to program the

block with 00h as the P/E.C. will do this automati-

cally before erasing to FFh. Read operations with-

in the same bank, after the sixth rising edge of W

or E, output the status register bits.

During the execution of the erase by the P/E.C.,

the memory accepts only the Erase Suspend ES

instruction; the Read/Reset RD instruction is ac-

cepted during the 100µs time-out period. Data

Polling bit DQ7 returns '0' while the erasure is in

progress and '1' when it has completed. The Tog-

gle bit DQ6 toggles during the erase operation,

and stops when erase is completed.

After completion the Status Register bit DQ5 re-

turns '1' if there has been an erase failure. In such

a situation, the Toggle bit DQ2 can be used to de-

termine which block is not correctly erased. In the

case of erase failure, a Read/Reset RD instruction

is necessary in order to reset the P/E.C.

– when WP is at V , the Lock status is overridden

IH

and all blocks can be protected or unprotected;

– when WP is at V , Lock status is enabled; the

IL

locked blocks are protected, regardless of their

previous protect state, and protection status

cannot be changed. Blocks that are not locked

can still change their protection status, and pro-

gram or erase accordingly;

– the lock status is cleared for all blocks at power

up; once a block has been locked state can be

cleared only with a reset command. The protec-

tion and lock status can be monitored for each

block using the Autoselect (AS) instruction. Pro-

tected blocks will output a ‘1’ on DQ0 and locked

blocks will output a ‘1’ on DQ1.

Refer to Table 13 for a list of the protection states.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 555h

on third cycle after the two Coded cycles. The

Block Erase Confirm command 30h is similarly

written on the sixth cycle after another two Coded

cycles and an address within the block to be

erased is given and latched into the memory.

9/37

M59DR016C, M59DR016D

Bank Erase (BKE) Instruction. This instruction

uses six write cycles and is used to erase all the

blocks belonging to the selected bank. The Erase

Set-up command 80h is written to address 555h

on the third cycle after the two Coded cycles. The

Bank Erase Confirm command 10h is similarly

written on the sixth cycle after another two Coded

cycles at an address within the selected bank. If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts and the device is reset to Read Array.

It is not necessary to program the array with 00h

first as the P/E.C. will automatically do this before

erasing it to FFh. Read operations within the same

bank after the sixth rising edge of W or E output

the Status Register bits. During the execution of

the erase by the P/E.C., Data Polling bit DQ7 re-

turns ’0’, then ’1’ on completion. The Toggle bit

DQ6 toggles during erase operation and stops

when erase is completed. After completion the

Status Register bit DQ5 returns ’1’ if there has

been an Erase Failure.

progress. It is also possible to program data in

blocks not being erased.

The Erase Suspend instruction consists of writing

the command B0h without any specific address.

No Coded Cycles are required. Erase suspend is

accepted only during the Block Erase instruction

execution. The Toggle bit DQ6 stops toggling

when the P/E.C. is suspended within 15µs after

the Erase Suspend (ES) command has been writ-

ten. The device will then automatically be set to

Read Memory Array mode. When erase is sus-

pended, a Read from blocks being erased will out-

put DQ2 toggling and DQ6 at '1'. A Read from a

block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in DQ6 toggling when the data

is being programmed.

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at an address within the bank be-

ing erased and without any Coded Cycle.

Erase Suspend (ES) Instruction. In a dual bank

memory the Erase Suspend instruction is used to

read data within the bank where erase is in

10/37

M59DR016C, M59DR016D

(1,2)

Table 14. Instructions

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

(3)

X

Addr.

Data

1+

Read Memory Array until a new write cycle is initiated.

F0h

Read/Reset

Memory Array

(4)

RD

Addr.

Data

555h

AAh

55h

2AAh

55h

555h

F0h

Read Memory Array until a new

write cycle is initiated.

3+

1+

Addr.

Data

RCFI CFI Query

Read CFI data until a new write cycle is initiated.

98h

Addr.

555h

2AAh

55h

555h

90h

Read electronic Signature or

Block Protection or Configuration

Register Status until a new cycle

is initiated.

(4)

Auto Select

3+

4

AS

Data

AAh

Configura-

tion Data

Addr.

Data

555h

AAh

2AAh

55h

555h

60h

Configuration

Register Write

CR

03h

Program

Address

Addr.

555h

2AAh

555h

Read Data Polling or

Toggle Bit until

Program completes.

PG

Program

4

5

Program

Data

Addr.

Data

AAh

555h

AAh

55h

2AAh

55h

A0h

555h

40h

Program Program

Address 1 Address 2

Double Word

Program

DPG

Note 6, 7

Program Program

Data 1

Data 2

Addr.

Data

Addr.

Data

555h

AAh

X

2AAh

55h

X

555h

20h

Enter Bypass

Mode

EBY

XBY

3

2

Exit Bypass

Mode

90h

00h

Program

Address

Addr.

Data

Addr.

Data

X

A0h

X

Program in

Bypass Mode

Read Data Polling or Toggle Bit until Program

completes.

PGBY

2

3

Program

Data

Program Program

Address 1 Address 2

Double Word

DPGBY Program in

Note 6, 7

Program Program

Bypass Mode

40h

Data 1

2AAh

55h

Data 2

555h

60h

Block

Address

Addr.

Data

Addr.

Data

555h

AAh

555h

AAh

BP

BU

Block Protect

4

1

01h

Block

Address

2AAh

55h

555h

60h

Block Unprotect

D0h

11/37

M59DR016C, M59DR016D

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.

Block

Address

Addr.

Data

Addr.

Data

Addr.

Data

555h

AAh

2AAh

55h

555h

60h

BL

Block Lock

4

2Fh

Block

Address

555h

AAh

2AAh

55h

555h

80h

555h

AAh

555h

AAh

2AAh

55h

BE

Block Erase

6+

30h

Bank

Address

555h

2AAh

55h

555h

80h

2AAh

55h

BKE Bank Erase

6

1

AAh

X

10h

(3)

Addr.

Data

Read until Toggle stops, then read all the data needed

from any Blocks not being erased then Resume Erase.

ES

ER

Erase Suspend

Erase Resume

B0h

Bank

Address

Addr.

Read Data Polling or Toggle Bits until Erase completes or

Erase is suspended another time

Data

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. For Coded cycles address inputs A11-A19 are don’t care.

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

6. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0.

7. High voltage on V (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.

PP

12/37

M59DR016C, M59DR016D

(1)

Table 15. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase block

in Erase Suspend.

’1’

’0’

Indicates the P/E.C. status, check

during Program or Erase, and on

completion before checking bits DQ5

for Program or Erase Success.

Erase On-going

Data

Polling

7

Program Complete or data of

non erase block during Erase

Suspend.

DQ

(2)

DQ

’-1-0-1-0-1-0-1-’

DQ

Program On-going

Erase or Program On-going

Program Complete

Successive reads output

complementary data on DQ6 while

Programming or Erase operations are

on-going. DQ6 remains at constant

level when P/E.C. operations are

completed or Erase Suspend is

acknowledged.

6

Toggle Bit

Erase Complete or Erase

Suspend on currently addressed

block

’-1-1-1-1-1-1-1-’

’1’

’0’

Program or Erase Error

This bit is set to ’1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started.

Only possible command entry is Erase

Suspend (ES)

’1’

’0’

Erase Timeout Period Expired

Erase Timeout Period On-going

Erase Time

Bit

3

An additional block to be erased in

parallel can be entered to the P/E.C:

Erase Suspend read in the

Erase Suspended Block.

Erase Error due to the currently

addressed block (when DQ5 =

’1’).

’-1-0-1-0-1-0-1-’

Indicates the erase status and allows

to identify the erased block.

2

Toggle Bit

Program on-going or Erase

Complete.

1

Erase Suspend read on non

Erase Suspend block.

DQ

1

0

Reserved

Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

2. In case of double word program DQ7 refers to the last word input.

13/37

M59DR016C, M59DR016D

Table 16. Polling and Toggle Bits

Suspend mode, DQ7 will output ’1’ if the read is at-

tempted on a block being erased and the data val-

ue on other blocks. During Program operation in

Erase Suspend Mode, DQ7 will have the same be-

haviour as in the normal program execution out-

side of the suspend mode.

Mode

DQ7

0

DQ6

DQ2

1

Program

Erase

Toggle

N/A

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

or E when G is at V . The operation is completed

IL

Erase Suspend Read

(outside Erase Suspend

block)

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a ’1’ after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. DQ6 will be set to ’1’ if a

Read operation is attempted on an Erase Suspend

block. When erase is suspended DQ6 will toggle

during programming operations in a block different

from the block in Erase Suspend. Either E or G

toggling will cause DQ6 to toggle. See Figure 13

for Toggle Bit flowchart and Figure 11 for Toggle

Bit waveforms.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. During Erase Sus-

pend a read from a block being erased will cause

DQ2 to toggle. A read from a block not being

erased will output data. DQ2 will be set to ’1’ during

program operation and to ‘0’ in Erase operation.

After erase completion and if the error bit DQ5 is

set to '1', DQ2 will toggle if the faulty block is ad-

dressed.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming or block

erase, that results in invalid data in the memory

block. In case of an error in block erase or pro-

gram, the block in which the error occurred or to

which the programmed data belongs, must be dis-

carded. Other Blocks may still be used. The error

bit resets after a Read/Reset (RD) instruction. In

case of success of Program or Erase, the error bit

will be set to '0'.

Erase Timer Bit (DQ3). This bit is set to ‘0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, DQ3 returns to ‘1’, in the range

of 80µs to 120µs.

DQ7

DQ6

DQ2

1

Erase Suspend Program

Toggle

STATUS REGISTER BITS

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 bits. Any read attempt within

the Bank being modified and during Program or

Erase command execution will automatically out-

put these five Status Register bits. The P/E.C. au-

tomatically sets bits DQ2, DQ5, DQ6 and DQ7.

Other bits (DQ0, DQ1 and DQ4) are reserved for

future use and should be masked (see Tables 15

and 16). Read attemps within the bank not being

modified will output array data.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7. In

case of a double word program operation, the

complement is done on DQ7 of the last word writ-

ten to the command interface, i.e. the data written

in the fifth cycle. During Erase operation, it outputs

a ’0’. After completion of the operation, DQ7 will

output the bit last programmed or a ’1’ after eras-

ing. Data Polling is valid and only effective during

P/E.C. operation, that is after the fourth W pulse

for programming or after the sixth W pulse for

erase. It must be performed at the address being

programmed or at an address within the block be-

ing erased. See Figure 12 for the Data Polling

flowchart and Figure 10 for the Data Polling wave-

forms. DQ7 will also flag the Erase Suspend mode

by switching from ’0’ to ’1’ at the start of the Erase

Suspend. In order to monitor DQ7 in the Erase

Suspend mode an address within a block being

erased must be provided. For a Read Operation in

14/37

M59DR016C, M59DR016D

Table 17. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70°C; V = V = 1.65V to 2.2V, V = V unless otherwise specified)

A

DD

DDQ

PP

DD

M59DR016

Parameter

Unit

Typical after

100k W/E Cycles

(1)

Min

Typ

Max

Parameter Block (4 KWord) Erase (Preprogrammed)

Main Block (32 KWord) Erase (Preprogrammed)

Bank Erase (Preprogrammed, Bank A)

2.5

10

0.15

1

0.4

3

s

2

6

Bank Erase (Preprogrammed, Bank B)

10

30

(2)

20

10

25

s

Chip Program

(2)

Chip Program (DPG, V = 12V)

PP

(3)

200

10

µs

Word Program

Double Word Program

200

10

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

3. Same timing value if V = 12V.

PP

POWER CONSUMPTION

Power Down

The memory provides Reset/Power Down control

input RP. The Power Down function can be acti-

vated only if the relevant Configuration Register bit

is set to ’1’. In this case, when the RP signal is

Power Up

The memory Command Interface is reset on Pow-

er Up to Read Array. Either E or W must be tied to

V

during Power Up to allow maximum security

IH

and the possibility to write a command on the first

rising edge of W.

pulled at V the supply current drops to typically

Supply Rails

SS

I

(see Table 22), the memory is deselected and

CC2

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

the outputs are in high impedance.If RP is pulled

to V during a Program or Erase operation, this

operation is aborted in t

content is no longer valid (see Reset/Power Down

input description).

SS

have the V

itor close to the V , V

rails decoupled with a 0.1µF capac-

DD

and the memory

PLQ7V

and V pins. The PCB

DD DDQ

SS

trace widths should be sufficient to carry the re-

quired V program and erase currents.

DD

15/37

M59DR016C, M59DR016D

COMMON FLASH INTERFACE (CFI)

The CFI data structure gives information on the

device, such as the sectorization, the command

set and some electrical specifications. Tables 18,

19, 20 and 21 show the addresses used to retrieve

each data. The CFI data structure contains also a

security area; in this section, a 64 bit unique secu-

rity number is written, starting at address 81h. This

area can be accessed only in read mode and there

are no ways of changing the code after it has been

written by ST. Write a read instruction to return to

Read mode. Refer to the CFI Query instruction to

understand how the M59DR016 enters the CFI

Query mode.

The Common Flash Interface (CFI) specification is

a JEDEC approved, standardised data structure

that can be read from the Flash memory device.

CFI allows a system software to query the flash

device to determine various electrical and timing

parameters, density information and functions

supported by the device. CFI allows the system to

easily interface to the Flash memory, to learn

about its features and parameters, enabling the

software to configure itself when necessary.

Tables 18, 19, 20 and 21 show the address used

to retrieve each data.

Table 18. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailled in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs.

Table 19. CFI Query Identification String

Offset

Data

Description

00h

0020h

Manufacturer Code

Device Code

Reserved

2293h - top

2294h - bottom

01h

02h-0Fh

10h

reserved

0051h

Query Unique ASCII String "QRY"

11h

0052h

12h

0059h

13h

0002h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

14h

0000h

15h

offset = P = 0040h

0000h

Address for Primary Algorithm extended Query table

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code second vendor

- specified algorithm supported (note: 0000h means none exists)

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

note: 0000h means none exists

1Ah

Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

16/37

M59DR016C, M59DR016D

Table 20. CFI Query System Interface Information

Offset

Data

Description

V

DD

V

DD

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

0022h

0000h

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

Note: This value must be 0000h if no V pin is present

PP

V

PP

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

1Eh

00C0h

Note: This value must be 0000h if no V pin is present

PP

n

Typical timeout per single byte/word program (multi-byte program count = 1), 2 µs

(if supported; 0000h = not supported)

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0000h

000Ah

0000h

0004h

0000h

0004h

0000h

n

Typical timeout for maximum-size multi-byte program or page write, 2 µs

(if supported; 0000h = not supported)

n

Typical timeout per individual block erase, 2 ms

(if supported; 0000h = not supported)

n

Typical timeout for full chip erase, 2 ms

(if supported; 0000h = not supported)

n

Maximum timeout for byte/word program, 2 times typical (offset 1Fh)

(0000h = not supported)

n

Maximum timeout for multi-byte program or page write, 2 times typical (offset 20h)

(0000h = not supported)

n

Maximum timeout per individual block erase, 2 times typical (offset 21h)

(0000h = not supported)

n

Maximum timeout for chip erase, 2 times typical (offset 22h)

(0000h = not supported)

17/37

M59DR016C, M59DR016D

Table 21. Device Geometry Definition

Offset Word

Data

Description

Mode

n

27h

28h

29h

2Ah

2Bh

2Ch

0015h

0001h

0000h

0002h

Device Size = 2 in number of bytes

Flash Device Interface Code description: Asynchronous x16

Maximum number of bytes in multi-byte program or page = 2

n

Number of Erase Block Regions within device

bit 7 to 0 = x = number of Erase Block Regions

Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."

2. x specifies the number of regions within the device containing one or more con-

tiguous Erase Blocks of the same size. For example, a 128KB device (1Mb)

having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered

to have 5 Erase Block Regions. Even though two regions both contain 16KB

blocks, the fact that they are not contiguous means they are separate Erase

Block Regions.

3. By definition, symmetrically block devices have only one blocking region.

M59DR016C M59DR016C Erase Block Region Information

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

001Eh

0000h

0001h

0007h

0000h

0020h

0000h

bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in

size. The value z = 0 is used for 128 byte block size.

e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K

bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase

Block Region:

e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]

y = 0 means no blocking (# blocks = y+1 = "1 block")

Note: y = 0 value must be used with number of block regions of one as indicated

by (x) = 0

M59DR016D M59DR016D

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

0007h

0000h

0020h

0000h

001Eh

0000h

0001h

18/37

M59DR016C, M59DR016D

Table 22. AC Measurement Conditions

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times

≤ 4ns

V

/ 2

DDQ

0 to V

Input Pulse Voltages

DDQ

1N914

V

/2

Input and Output Timing Ref. Voltages

DDQ

3.3kΩ

Figure 3. Testing Input/Output Waveforms

DEVICE

UNDER

TEST

OUT

V

DDQ

C

= 30pF

L

V

/2

DDQ

0V

C

includes JIG capacitance

L

AI02315

AI02316

(1)

Table 23. Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: 1. Sampled only, not 100% tested.

19/37

M59DR016C, M59DR016D

Table 24. DC Characteristics

(TA = 0 to 70°C or –40 to 85°C; V = V

= 1.65V to 2.2V)

DD

DDQ

Test Condition

0V ≤ V ≤ V

Symbol

Parameter

Min

Typ

Max

±1

Unit

µA

I

Input Leakage Current

Output Leakage Current

LI

IN

DD

I

LO

0V ≤ V

≤ V

OUT DD

±5

µA

Supply Current

(Read Mode)

I

E = V , G = V , f = 6MHz

IL IH

10

20

mA

CC1

Supply Current

(Power Down)

I

RP = V ± 0.2V

2

10

50

20

µA

CC2

SS

I

E = V ± 0.2V

Supply Current (Standby)

15

10

CC3

DD

Supply Current

(Program or Erase)

Word Program, Block Erase

in progress

(1)

mA

I

CC4

Program/Erase in progress

in one Bank, Read in the

other Bank

Supply Current

(Dual Bank)

(1)

20

5

40

10

mA

I

CC5

V

Supply Current

PP

I

V

= 12V ± 0.6V

PP1

PP

(Program or Erase)

V

≤ V

CC

0.2

5

µA

V

PP

V

Supply Current

PP

I

PP2

(Standby or Read)

V

= 12V ± 0.6V

100

400

0.4

PP

V

Input Low Voltage

Input High Voltage

Output Low Voltage

–0.5

IL

V

–0.4

V

+ 0.4

V

IH

DDQ

V

I

= 100µA

0.1

V

OL

Output High Voltage

CMOS

V

I

= –100µA

OH

–0.1

V

OH

DDQ

V

+ 0.4

–0.4

11.4

V

DD

V

Supply Voltage

PP

(2,3)

V

PP

(Program or Erase)

Double Word Program

12.6

Note: 1. Sampled only, not 100% tested.

2. V may be connected to 12V power supply for a total of less than 100 hrs.

PP

3. For standard program/erase operation V is don’t care.

PP

20/37

M59DR016C, M59DR016D

Table 25. Read AC Characteristics

(TA = 0 to 70°C or –40 to 85°C; V = V

= 1.65V to 2.2V)

DDQ

DD

M59DR016

Symbol

Alt

Parameter

Test Condition

100

120

Unit

Min

Max

Min

Max

Address Valid to Next

Address Valid

t

E = V , G = V

100

120

ns

µs

AVAV

RC

IL

Address Valid to Output

Valid (Random)

t

E = V , G = V

100

35

120

45

AVQV

ACC

IL

Address Valid to Output

Valid (Page)

t

E = V , G = V

AVQV1

PAGE

IL

Chip Enable Low to Output

Transition

(1)

t

G = V

0

t

LZ

IL

ELQX

Chip Enable Low to Output

Valid

(2)

t

G = V

100

25

120

35

t

CE

IL

ELQV

Output Enable Low to

Output Transition

(1)

t

E = V

t

OLZ

IL

GLQX

Output Enable Low to

Output Valid

(2)

t

E = V

t

OE

IL

GLQV

Chip Enable High to Output

Transition

t

G = V

EHQX

OH

IL

Chip Enable High to Output

Hi-Z

(1)

t

G = V

25

35

t

HZ

IL

EHQZ

Output Enable High to

Output Transition

t

E = V

GHQX

OH

IL

Output Enable High to

Output Hi-Z

(1)

t

E = V

25

35

t

DF

IL

GHQZ

Address Transition to

Output Transition

t

E = V , G = V

AXQX

OH

IL

RP High to Data Valid

(Read Mode)

t

150

50

150

50

PHQ7V1

RP High to Data Valid

(Power Down enabled)

t

PHQ7V2

RP Low to Reset Complete

During Program/Erase

t

15

µs

ns

PLQ7V

t

RP Pulse Width

100

PLPH

RP

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

21/37

M59DR016C, M59DR016D

Figure 5. Random Read AC Waveforms

22/37

M59DR016C, M59DR016D

Figure 6. Page Read AC Waveforms

23/37

M59DR016C, M59DR016D

Table 26. Write AC Characteristics, Write Enable Controlled

(T = 0 to 70 °C or –40 to 85 °C; V = V

= 1.65V to 2.2V)

A

DD

DDQ

M59DR016

Symbol

Alt

Parameter

100

120

Unit

Min

100

0

Max

Min

Max

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

120

0

ns

µs

ns

AVAV

t

CS

ELWL

t

WP

50

0

50

0

WLWH

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

WHDX

t

0

WHEH

t

30

0

30

0

WHWL

WPH

t

AS

AVWL

t

50

0

50

0

WLAX

AH

t

GHWL

t

V

DD

High to Chip Enable Low

50

30

50

30

VDHEL

VCS

t

Write Enable High to Output Enable Low

WHGL

OEH

RP Low to Reset Complete During

Program/Erase

t

15

µs

PLQ7V

24/37

M59DR016C, M59DR016D

Table 27. Write AC Characteristics, Chip Enable Controlled

(T = 0 to 70 °C or –40 to 85 °C; V = V

= 1.65V to 2.2V)

A

DD

DDQ

M59DR016

Symbol

Alt

Parameter

100

120

Unit

Min

100

0

Max

Min

120

0

Max

t

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

ns

µs

ns

AVAV

WC

t

WLEL

WS

t

50

0

50

0

ELEH

CP

DS

DH

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

EHDX

t

WH

0

EHWH

t

CPH

30

0

30

0

EHEL

t

AVEL

AS

t

50

0

50

0

ELAX

AH

t

GHEL

t

V

DD

High to Write Enable Low

50

30

50

30

VDHWL

VCS

t

Chip Enable High to Output Enable Low

EHGL

OEH

RP Low to Reset Complete During

Program/Erase

t

15

µs

PLQ7V

25/37

M59DR016C, M59DR016D

Figure 7. Write AC Waveforms, W Controlled

tAVAV

VALID

A0-A19

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ15

V

DD

tVDHEL

AI04109

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

26/37

M59DR016C, M59DR016D

Figure 8. Write AC Waveforms, E Controlled

tAVAV

VALID

A0-A19

tELAX

tAVEL

tEHWH

tEHGL

W

tWLEL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ15

V

DD

tVDHWL

AI04110

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

27/37

M59DR016C, M59DR016D

(1)

Table 28. Data Polling and Toggle Bits AC Characteristics

(T = 0 to 70 °C or –40 to 85 °C; V = V

= 1.65V to 2.2V)

A

DD

DDQ

M59DR016

Max

Symbol

Parameter

Unit

Min

10

1

Write Enable High to DQ7 Valid (Program, W Controlled)

Write Enable High to DQ7 Valid (Block Erase, W Controlled)

Chip Enable High to DQ7 Valid (Program, E Controlled)

Chip Enable High to DQ7 Valid (Block Erase, E Controlled)

Q7 Valid to Output Valid (Data Polling)

200

10

µs

s

t

WHQ7V

10

1

200

10

µs

s

t

EHQ7V

Q7VQV

t

0

ns

µs

s

Write Enable High to Output Valid (Program)

10

1

200

10

t

WHQV

Write Enable High to Output Valid (Block Erase)

Chip Enable High to Output Valid (Program)

10

1

200

10

µs

s

t

EHQV

Chip Enable High to Output Valid (Block Erase)

Note: 1. All other timings are defined in Read AC Characteristics table.

28/37

M59DR016C, M59DR016D

Figure 9. Read and Write AC Characteristics, RP Related

29/37

M59DR016C, M59DR016D

Figure 10. Data Polling DQ7 AC Waveforms

30/37

M59DR016C, M59DR016D

Figure 11. Data Toggle DQ6, DQ2 AC Waveforms

31/37

M59DR016C, M59DR016D

Figure 12. Data Polling Flowchart

Figure 13. Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

DQ6

NO

=

DQ7

=

DATA

YES

TOGGLES

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ6

DQ7

=

DATA

YES

DQ6

=

NO

TOGGLES

NO

YES

FAIL

PASS

FAIL

PASS

AI02574

AI02626

32/37

M59DR016C, M59DR016D

Table 29. Ordering Information Scheme

Example:

M59DR016C

100 ZB

6

T

Device Type

M59

Architecture

D = Dual Bank Page Mode

Operating Voltage

R = 1.8V

Device Function

016C = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot

016D = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot

Random Speed

100 = 100 ns

120 = 120 ns

Package

ZB = TFBGA48: 0.75mm pitch

Temperature Range

1 = 0 to 70°C

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 30. Daisy Chain Ordering Scheme

Example:

M59DR016

-ZB T

Device Type

M59DR016

Daisy Chain

-ZB = TFBGA48: 0.75mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

33/37

M59DR016C, M59DR016D

Table 31. Revision History

Date

Version

Revision Details

March 2001

-01

First Issue

34/37

M59DR016C, M59DR016D

Table 32. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.350

0.350

1.000

0.550

7.100

–

Typ

Max

A

A1

A2

b

0.0531

0.300

0.200

0.0118

0.0079

0.0138

0.0394

0.300

6.900

–

0.0118

0.2717

–

0.0217

D

7.000

5.250

0.2756

0.2795

D1

ddd

E

0.2067

–

0.100

12.100

–

0.0039

12.000

3.750

0.750

0.375

4.125

0.875

11.900

0.4724

0.1476

0.0295

0.0148

0.1624

0.0344

0.4685

0.4764

E1

e

–

SD

SE

FE

FD

–

Figure 14. TFBGA48 - 8 x 6 balls array, 0.75 mm pitch, Package Outline

D

D1

FD

SD

FE

SE

E1

E

ddd

BALL "A1"

A

A2

e

b

A1

BGA-Z03

Drawing is not to scale.

35/37

M59DR016C, M59DR016D

Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI03079

Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI03080

36/37

M59DR016C, M59DR016D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

www.st.com

37/37


型号：	M59DR016D100ZB6
厂家：	NUMONYX B.V
描述：	1MX16 FLASH 1.8V PROM, 100ns, PBGA48, 0.75 MM PITCH, TFBGA-48 可编程只读存储器内存集成电路闪存
文件：	总37页 (文件大小：240K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M59DR016D100ZB6 [NUMONYX]

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