NAND02GW3B2DZA6E [NUMONYX]
2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories; 2千兆位， 2112字节/ 1056字的页面多平面架构， 1.8 V或3V时， NAND快闪存储器
| 型号： | NAND02GW3B2DZA6E |
| 厂家： | 
NUMONYX B.V |
| 描述： | 2-Gbit, 2112-byte/1056-word page multiplane architecture, 1.8 V or 3 V, NAND flash memories |
| 文件： | 总69页 (文件大小：1812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND02G-B2D
2-Gbit, 2112-byte/1056-word page
multiplane architecture, 1.8 V or 3 V, NAND flash memories
Preliminary Data
Features
■ High density NAND flash memory
– Up to 2 Gbits of memory array
– Cost-effective solution for mass storage
applications
■ NAND interface
– x8 or x16 bus width
– Multiplexed address/data
TSOP48 12 x 20 mm (N)
■ Supply voltage: 1.8 V or 3.0 V device
FBGA
■ Page size
– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words
VFBGA63 9.5 x 12 mm (ZA)
■ Block size
■ Status register
– x8 device: (128 K + 4 K spare) bytes
– x16 device: (64 K + 2 K spare) words
■ Electronic signature
■ Chip Enable ‘don’t care’
■ Serial number option
■ Data protection:
■ Multiplane architecture
– Array split into two independent planes
– Program/erase operations can be
performed on both planes at the same time
– Hardware program/erase disabled during
power transitions
■ Page read/program
– Non-volatile protection option
– Random access: 25 µs (max)
– Sequential access: 25 ns (min)
– Page program time: 200 µs (typ)
■ ONFI 1.0 compliant command set
■ Data integrity
– Multiplane page program time (2 pages):
200 µs (typ)
– 100,000 program/erase cycles (with ECC)
– 10 years data retention
■ Copy back program with automatic EDC (error
®
■ ECOPACK packages
detection code)
■ Cache read mode
Table 1.
Device summary
Part number
■ Fast block erase
Reference
– Block erase time: 1.5 ms (typ)
NAND02GR3B2D
NAND02GW3B2D
NAND02GR4B2D(1)
NAND02GW4B2D(1)
– Multiblock erase time (2 blocks): 1.5 ms
(typ)
NAND02G-B2D
1. x 16 organization only available for MCP products.
April 2008
Rev 3
1/69
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.numonyx.com
1
Contents
NAND02G-B2D
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
V
DD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
4.2
4.3
4.4
4.5
4.6
Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
6
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1
6.1.2
Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/69
NAND02G-B2D
Contents
6.3
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3.1
6.3.2
Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4
6.5
6.6
6.7
6.8
6.9
Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11.2 P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 36
6.11.3 P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.4 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.5 SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.12 Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.13 Read EDC status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.14 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.15 Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.16 Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7
8
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1
8.2
8.3
8.4
8.5
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10
3/69
Contents
NAND02G-B2D
11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1 Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 63
11.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12
13
14
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4/69
NAND02G-B2D
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address insertion (x 8 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address insertion (x 16 devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address definition (x 8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address definition (x 16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
EDC status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DC characteristics (1.8 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DC characteristics (3 V devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
AC Characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65
VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical
data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
5/69
List of figures
NAND02G-B2D
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 connections for NAND02G-B2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VFBGA63 connections for NAND02G-B2D devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cache read (random) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Multiplane page program waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Copy back program (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. Copy back program (with readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Block erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. Page organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 51
Figure 24. Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 25. Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 26. Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 27. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 28. Sequential data output after read AC waveforms (EDO mode) . . . . . . . . . . . . . . . . . . . . . 56
Figure 29. Read Status register or read EDC Status register AC waveform . . . . . . . . . . . . . . . . . . . . 57
Figure 30. Read status enhanced waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 31. Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 32. Read ONFI signature waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 33. Page read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 34. Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 35. Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 36. Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 37. Program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 38. Program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 39. Read parameter page waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 40. Ready/busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 41. Ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 42. Resistor value versus waveform timings for ready/busy signal . . . . . . . . . . . . . . . . . . . . . 64
Figure 43. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 44. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 65
Figure 45. VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline . . . . . . . 66
6/69
NAND02G-B2D
Description
1
Description
The NAND02G-B2D devices are part of the NAND flash 2112-byte/1056-word page family
of non-volatile flash memories. They use NAND cell technology and have a density of
2 Gbits.
These devices have a memory array that is split into 2 planes of 1024 blocks each. This
multiplane architecture makes it possible to program 2 pages at a time (one in each plane),
or to erase 2 blocks at a time (one in each plane). This feature reduces the average program
and erase times by 50%.
The NAND02G-B2D devices operate from a 1.8 V or 3 V voltage supply. Depending on
whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare)
or 1056 words (1024 + 32 spare), respectively.
The address lines are multiplexed with the data input/output signals on a multiplexed x 8
input/output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles with ECC (error correction
code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is
mandatory.
A write protect pin is available to provide hardware protection against program and erase
operations.
The devices feature an open-drain ready/busy output that identifies if the P/E/R
(program/erase/read) controller is currently active. The use of an open-drain output allows
the ready/busy pins from several memories to connect to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a page program operation fails, the data can be programmed in another page
without having to resend the data to be programmed. An embedded error detection code is
automatically executed after each copy back operation: 1 error bit can be detected for every
528 bits. With this feature it is no longer necessary to use an external 2-bit ECC to detect
copy back operation errors.
The devices have a cache read feature that improves the read throughput for large files.
During cache reading, the device loads the data in a Cache register while the previous data
is transferred to the I/O buffers to be read.
The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly
downloaded by a microcontroller. This is possible because Chip Enable transitions during
the latency time do not stop the read operation.
The NAND02G-B2D devices support the ONFI 1.0 specification.
7/69
Description
NAND02G-B2D
Two further features are available as options:
■
■
Extra non-volatile protection
An individual serial number that acts as an unique identifier.
More information is available, upon completion of an NDA (non-disclosure agreement), and
are, therefore, not described in this datasheet. For more details of this option contact your
nearest Numonyx sales office.
The devices are available in the TSOP48 (12 x 20 mm) and VFBGA63 (9.5 x 12 mm)
packages.
For information on how to order these options, refer to Table 31: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
Table 2: Product description lists the part numbers and other information for all the devices
in the family.
Table 2.
Product description
Timings
Bus
width
Page
size
Block
size
Memory Operating
Part number
Density
Package
Sequential
access
Random
access
Page
Program Erase
Block
array
voltage
time (min) time (max)
(typ)
(typ)
1.7 to
1.95 V
NAND02GR3B2D
NAND02GW3B2D
NAND02GR4B2D
NAND02GW4B2D
45 ns
VFBGA63
2048+64 128 K+4 K
x8
bytes
bytes
2.7 to
3.6 V
25 ns
25 µs
45 ns
64 pages
x 2048
blocks
2 Gb
200 µs
1.5 ms
1.7 to
1.95 V
TSOP48
VFBGA63
1024+
32 words
64 K+2 K
words
x16
2.7 to
3.6 V
25 ns
8/69
NAND02G-B2D
Description
Figure 1.
Logic block diagram
Address
Register/Counter
AL
CL
W
NAND Flash
Memory Array
P/E/R Controller,
High Voltage
Generator
Command
Interface
Logic
E
WP
R
Page Buffer
Cache Register
Y Decoder
Command Register
I/O Buffers & Latches
RB
I/O0-I/O7 (x8/x16)
I/O8-I/O15 (x16)
AI13166b
Figure 2.
Logic diagram
V
DD
I/O0-I/O7 (x8/x16)
E
I/O8-I/O15 (x16)
R
W
NAND FLASH
RB
AL
CL
WP
V
SS
AI13167b
9/69
Description
NAND02G-B2D
Table 3.
Signal
Signal names
Function
Direction
Data input/outputs, address inputs, or command inputs (x8/x16
devices)
I/O0-7
Input/output
I/O8-15
AL
Data input/outputs (x16 devices)
Address Latch Enable
Command Latch Enable
Chip Enable
Input/output
Input
CL
Input
E
Input
R
Read Enable
Input
RB
W
Ready/Busy (open-drain output)
Write Enable
Output
Input
WP
VDD
VSS
NC
DU
Write Protect
Input
Supply voltage
Power supply
Ground
N/A
Ground
Not connected internally
Do not use
N/A
10/69
NAND02G-B2D
Description
Figure 3.
TSOP48 connections for NAND02G-B2D
NC
NC
NC
NC
NC
NC
RB
R
1
48
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
E
NC
NC
NC
NC
V
12
13
37
36
V
V
DD
DD
SS
NAND FLASH
V
SS
NC
NC
CL
AL
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
W
WP
NC
NC
NC
NC
NC
NC
NC
NC
NC
24
25
AI13168b
11/69
Description
NAND02G-B2D
Figure 4.
VFBGA63 connections for NAND02G-B2D devices
1
2
3
4
5
6
7
8
9
10
DU
DU
DU
A
B
DU
DU
DU
DU
AL
V
SS
C
WP
E
W
RB
D
E
F
NC
NC
NC
NC
R
CL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O3
NC
NC
G
H
J
NC
NC
NC
NC
I/O0
I/O1
I/O2
NC
V
DD
V
I/O5
I/O6
I/O7
DD
V
K
L
I/O4
V
SS
SS
DU
DU
DU
DU
DU
DU
DU
DU
M
AI13103
12/69
NAND02G-B2D
Memory array organization
2
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series. It
is organized into blocks where each block contains 64 pages. The array is split into two
areas, the main area and the spare area. The main area of the array is used to store data,
and the spare area typically stores error correction codes, software flag, or bad block
identification.
In x 8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes.
In x 16 devices, the pages are split into a 1024-word main area and a spare area of
32 words. Refer to Figure 5: Memory array organization.
Bad blocks
In the x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad
blocks, which are blocks that contain one or more invalid bits whose reliability is not
guaranteed. Additional bad blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 8.1: Bad block
management for more details).
There are a minimum of 2008 and a maximum of 2048 valid blocks. These numbers include
both the bad blocks that are present when the device is shipped and the bad blocks that
could develop later on.
These blocks need to be managed using bad blocks management, block replacement, or
error correction codes (refer to Section 8: Software algorithms).
13/69
Memory array organization
NAND02G-B2D
Figure 5.
Memory array organization
x 8 bus width
Plane = 1024 blocks, block = 64 pages, page = 2112 bytes (2048 + 64)
First plane
Second plane
Main area
Main area
Block
Page
8 bits
2048 bytes
2048 bytes
64
bytes
64
bytes
Page buffer, 2112 bytes
64
Page buffer, 2112 bytes
64
2048 bytes
2048 bytes
bytes
bytes
8 bits
2-page buffer, 2 x 2112 bytes
x 16 bus width
plane = 2048 blocks, block = 64 pages, page = 1056 words (1024 + 32)
First plane
Second plane
Main area
Main area
Block
Page
16 bits
1024 words
1024 words
32
words
32
words
Page buffer, 1056 bytes
32
Page buffer, 1056 bytes
32
1024 words
1024 words
words
words
16 bits
2-page buffer, 2 x 1056 bytes
AI13170C
14/69
NAND02G-B2D
Signal descriptions
3
Signal descriptions
See Figure 2: Logic diagram, and Table 3: Signal names for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x 16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
3.4
3.5
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
Chip Enable (E)
The Chip Enable input, E, activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V , the device is selected. If Chip Enable goes
IL
High, V , while the device is busy, the device remains selected and does not go into
IH
standby mode.
3.6
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid t
after the falling edge of R. The falling edge of R also increments the internal
RLQV
column address counter by one.
15/69
Signal descriptions
NAND02G-B2D
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
high during the recovery time.
3.8
3.9
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V , the device does not accept any
program or erase operations.
IL
It is recommended to keep the Write Protect pin Low, V , during power-up and power-down.
IL
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain outputs that can be used to identify if the
P/E/R controller is currently active.
When Ready/Busy is Low, V , a read, program or erase operation is in progress. When the
OL
operation completes, Ready/Busy goes High, V
.
OH
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the RB signal is Low,
V
.
OL
Refer to Section 11.1: Ready/busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V is below V
(see
LKO
DD
Table 26) to protect the device from any involuntary program/erase during power transitions.
Each device in a system should have V decoupled with a 0.1 µF capacitor. The PCB track
DD
widths should be sufficient to carry the required program and erase currents.
3.11
VSS ground
Ground, V
ground.
is the reference for the power supply. It must be connected to the system
SS,
16/69
NAND02G-B2D
Bus operations
4
Bus operations
There are six standard bus operations that control the memory, as described in this section.
See Table 4: Bus operations for a summary of these operations.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable, and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations give commands to the memory.
Commands are accepted when Chip Enable is Low, Command Latch Enable is High,
Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge
of the Write Enable signal.
Only I/O0 to I/O7 input commands.
See Figure 24 and Table 27 for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to Table 5: Address insertion (x 8 devices) and Table 6: Address
insertion (x 16 devices)).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input addresses.
See Figure 25 and Table 27 for details of the timings requirements.
4.3
4.4
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 26 and Table 27 and Table 28 for details of the timings requirements.
Data output
Data output bus operations read the data in the memory array, the Status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
17/69
Bus operations
NAND02G-B2D
If the Read Enable pulse frequency is lower then 33 MHz (t
higher than 30 ns), the
RLRL
output data is latched on the rising edge of Read Enable signal (see Figure 27).
For higher frequencies (t lower than 30 ns), the EDO (extended data out) mode must be
RLRL
used. In this mode, Data Output bus operations are valid on the input/output bus for a time
of t after the falling edge of Read Enable signal (see Figure 28).
RLQX
See Table 28 for details on the timings requirements.
4.5
4.6
Write protect
Write protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low, the device does not accept program or
erase operations, and, therefore, the contents of the memory array cannot be altered. The
Write Protect signal is not latched by Write Enable to ensure protection, even during power-
up.
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled, and power consumption is reduced.
Table 4.
Bus operation
Command input VIL
Bus operations
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
VIL
VIH
VIL
VIL
X
VIH
VIL
VIL
VIL
X
VIH
VIH
VIH
Falling
X
Rising
Rising
Rising
VIH
X(2)
X
Command
Address
Data input
Data output
X
X
Address input
Data input
VIL
VIL
VIL
X
X
VIH
Data input
Data output
Write protect
Standby
X
Data output
X
VIL
X
X
VIH
X
X
X
X
VIL/VDD
X
1. Only for x 16 devices.
2. WP must be VIH when issuing a Program or Erase command.
Table 5.
Address insertion (x 8 devices)
Bus
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
cycle(1)
1st
2nd
3rd
4th
5th
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
A11
A15
A23
VIL
A2
A10
A14
A22
VIL
A1
A9
A0
A8
A19
A27
VIL
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A13
A21
VIL
A12
A20
A28
1. Any additional address input cycles are ignored.
18/69
NAND02G-B2D
Bus operations
Table 6.
Address insertion (x 16 devices)
Bus
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
cycle(1)
1st
2nd
3rd
4th
5th
A7
VIL
A6
VIL
A5
VIL
A4
VIL
A3
VIL
A2
A10
A13
A21
VIL
A1
A9
A0
A8
A18
A26
VIL
A17
A25
VIL
A16
A24
VIL
A15
A23
VIL
A14
A22
VIL
A12
A20
VIL
A11
A19
A27
1. Any additional address input cycles are ignored.
Table 7.
Address definition (x 8 devices)
Address
Definition
A0 - A11
A12 - A17
A18 - A28
A18 = 0
Column address
Page address
Block address
First plane
A18 = 1
Second plane
Table 8.
Address definition (x 16 devices)
Address
Definition
A0 - A10
A11 - A16
A17 - A27
A17 = 0
Column address
Page address
Block address
First plane
A17 = 1
Second plane
19/69
Command set
NAND02G-B2D
5
Command set
All bus write operations sent to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the command Latch Enable signal is High. Device operations are selected by writing specific
commands to the Command register. The two-step command sequences for program and
erase operations are imposed to maximize data security.
Table 9 summarizes the commands.
Table 9.
Commands
Command(1)
Bus write operations
Commands
accepted
during busy
1st cycle 2nd cycle 3rd cycle 4th cycle
Read
00h
05h
31h
00h
3Fh
30h
E0h
–
–
–
–
–
–
–
–
–
–
–
Random Data Output
Cache Read (sequential)
Enhanced Cache Read (random)
Exit Cache Read
31h
–
Yes(2)
Page Program
80h
10h
–
–
(sequential input default)
Random Data Input
85h
80h
80h
00h
85h
85h
85h
60h
60h
60h
FFh
90h
70h
78h
ECh
7Bh
–
11h
11h
35h
10h
11h
11h
D0h
60h
D1h
–
–
81h
80h
–
–
10h
10h
–
Multiplane Page Program(3)
Multiplane Page Program
Copy Back Read
Copy Back Program
–
–
Multiplane Copy Back Program(3)
Multiplane Copy Back Program
Block Erase
81h
85h
–
10h
10h
–
Multiplane Block Erase(3)
Multiplane Block Erase
Reset
D0h
60h
–
–
D0h
–
Yes
Read Electronic Signature
Read Status register
Read Status Enhanced
Read Parameter Page
Read EDC Status register
–
–
–
–
–
–
Yes
Yes
–
–
–
–
–
–
–
–
–
1. Commands in bold are referring to ONFI 1.0 specifications.
2. Only during cache read busy.
3. Command maintained for backward compatibility.
20/69
NAND02G-B2D
Device operations
6
Device operations
This section provides details of the device operations.
6.1
Read memory array
At power-up the device defaults to read mode. To enter read mode from another mode, the
read command must be issued (see Table 9: Commands).
6.1.1
6.1.2
Random read
Each time the read command is issued, the first read is random read.
Page read
After the first random read access, the page data (2112 bytes or 1056 words) is transferred
to the page buffer in a time of t
(see Table 28). Once the transfer is complete, the
WHBH
Ready/Busy signal goes High. The data can then be read sequentially (from selected
column address to last column address) by pulsing the Read Enable signal.
The devices can output random data in a page, instead of consecutive sequential data, by
issuing a Random Data Output command. The Random Data Output command can be used
to skip some data during a sequential data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command. The Random
Data Output command can be issued as many times as required within a page.
The Random Data Output command is not accepted during cache read operations.
21/69
Device operations
NAND02G-B2D
Figure 6.
Read operations
CL
E
W
AL
R
tBLBH1
30h
RB
I/O
Address Input
00h
Data Output (sequentially)
Command
Code
Command
Code
Busy
ai12469
22/69
NAND02G-B2D
Device operations
Figure 7.
Random data output during sequential data output
tBLBH1
(Read Busy time)
RB
Busy
tRHWL
W
R
Address
Address
Inputs
30h
E0h
I/O
00h
05h
Data Output
Data Output
Inputs
Cmd
Cmd
Cmd
Cmd
Code
Code
Code
Code
5 Add cycles
2 Add cycles
Col Add 1,2
Row Add 1,2,3 Col Add 1,2
Spare
Area
Spare
Area
Main Area
Main Area
ai08658b
6.2
Cache read
The cache read operation improves the read throughput by reading data using the Cache
register. As soon as the user starts to read one page, the device automatically loads the
next page into the Cache register.
A Read Page command, as defined in Section 6.1.1: Random read, is issued prior to the
first Cache Read command in a cache read sequence. Once the Read Page command
execution is terminated, the Cache Read command can be issued as follows:
1. Issue a Sequential Cache Read command to copy the next page in sequential order to
the Cache register
2. Issue a Random Cache Read command to copy the page addressed in this command
to the Cache register.
The two commands can be used interchangeably, in any order. When there are no more
pages to be read, the final page is copied into the Cache register by issuing the Exit Cache
Read command. A Read Cache command must not be issued after the last page of the
device is read. Data output only starts after issuing the 31h command for the first time.
See Figure 8: Cache read (sequential) operation and Figure 9: Cache read (random)
operation for examples of the two sequences.
23/69
Device operations
NAND02G-B2D
After the Sequential Cache Read or Random Cache Read command has been issued, the
Ready/Busy signal goes Low and the Status register bits are set to SR5 =' 0' and SR6 ='0'.
This is for a period of Cache Read busy time, t
into the Cache register.
while the device copies the next page
RCBSY
After the Cache Read busy time has passed, the Ready/Busy signal goes High and the
Status register bits are set to SR5 = '0' and SR6 = '1', signifying that the Cache register is
ready to download new data. Data of the previously read page can be output from the page
buffer by toggling the Read Enable signal. Data output always begins at column address
00h, but the Random Data Output command is also supported.
Figure 8.
Cache read (sequential) operation
tBLBH1
tRCBSY
tRCBSY
(Read Busy time)
(Read Cache Busy time)
(Read Cache Busy time)
RB
R
Busy
Data
Data
Outputs
Address
Inputs
31h
I/O0-7
30h
00h
3Fh
Exit
Cache
Read
Code
Outputs
Read
Setup
Code
Read
Code
Cache
Read
Sequential
Code
ai13176b
Repeat as many times as ncessary.
Figure 9.
Cache read (random) operation
tBLBH1
tRCBSY
tRCBSY
(Read Busy time)
(Read Cache Busy time)
(Read Cache Busy time)
RB
R
Busy
Address
31h
Data
Outputs
Address
Data
Outputs
00h
3Fh
Exit
Cache
Read
Code
I/O0-7
30h
00h
Inputs
Inputs
Read
Setup
Code
Read
Code
Read
Setup
Code
Enhanced
Cache
Read
(random)
Code
ai13176c
Repeat as many times as ncessary.
24/69
NAND02G-B2D
Device operations
6.3
Page program
The page program operation is the standard operation to program data to the memory array.
Generally, the page is programmed sequentially, however, the device does support random
input within a page.
It is recommended to address pages sequentially within a given block.
The memory array is programmed by page, however, partial page programming is allowed
where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed.
The maximum number of consecutive, partial-page program operations allowed in the same
page is four. After exceeding four operations, a Block Erase command must be issued
before any further program operations can take place in that page.
6.3.1
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input each page program operation consists of the following five steps:
1. One bus cycle is required to set up the Page Program (sequential input) command (see
Table 9: Commands)
2. Five bus cycles are then required to input the program address (refer to Table 5:
Address insertion (x 8 devices) and Table 6: Address insertion (x 16 devices))
3. The data is then loaded into the Data registers
4. One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R controller only starts if the data has been loaded in step 3.
5. The P/E/R controller then programs the data into the array.
See Figure 10: Page program operation for more information.
6.3.2
Random data input in page
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address by issuing a Random Data Input command. The following
two steps are required to issue the command:
1. One bus cycle is required to set up the Random Data Input command (see Table 9:
Commands)
2. Two bus cycles are then required to input the new column address (refer to Table 5:
Address insertion (x 8 devices))
Random data input can be repeated as often as required in any given page.
Once the program operation has started, the Status register can be read using the Read
Status register command. During program operations the Status register only flags errors for
bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
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Device operations
NAND02G-B2D
Figure 10. Page program operation
tBLBH2
(Program Busy time)
RB
I/O
Busy
Data Input
10h
Address Inputs
80h
70h
SR0
Confirm
Code
Read Status Register
Page Program
Setup Code
ai08659
Figure 11. Random data input during sequential data input
tBLBH2
(Program Busy time)
RB
Busy
Address
Inputs
Address
Inputs
I/O
80h
85h
10h
Data Intput
Data Input
70h
SR0
Cmd
code
Cmd
code
Confirm
code
Read Status register
2 Add cycles
Col Add 1,2
5 Add cycles
Row Add 1,2,3 Col Add 1,2
Spare
area
Spare
area
Main area
Main area
ai08664
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NAND02G-B2D
Device operations
6.4
Multiplane page program
The devices support multiplane page program operations, which enables the programming
of two pages in parallel, one in each plane.
A multiplane page program operation requires the following two steps:
1. The first step serially loads up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
1 clock cycle to set up the Page Program command (see Section 6.3.1: Sequential
input)
–
5 bus write cycles to input the first page address and data. The address of the first
page must be within the first plane (A18 = 0 for x 8 devices, A17 = 0 for x 16
devices)
–
–
1 bus write cycle to issue the page program confirm code. After this, the device is
busy for a time of t
IPBSY
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the 2nd page address (5 write
cycles) and data. The address of the second page must be within the second
plane (A18 = 1 for x 8 devices, A17 = 1 for x 16 devices)
2. Parallel programming of both pages starts after the issue of Page Confirm command.
Refer to Figure 12: Multiplane page program waveform for differences between ONFI
and traditional sequences.
As for standard page program operation, the device supports random data input during both
data loading phases.
Once the multiplane page program operation has started, that is during a delay of t
Status register can be read using the Read Status register command.
, the
IPBSY
Once the multiplane page program operation has completed, the P/E/R controller bit SR6 is
set to ‘1’ and the Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the Status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 12 provides a description of the multiplane operation while showing the restrictions
related to the multiplane page program and the differences between ONFI 1.0 and
traditional sequences.
27/69
Device operations
NAND02G-B2D
Figure 12. Multiplane page program waveform
tIPBSY
tBLBH2
(Program Busy time)
RB
Busy
Busy
1
I/O
2
Data input
11h
Data input
10h
Address inputs
A0-A11 = Valid
Address inputs
A0-A11 = Valid
80h
81h
70h
SR0
Confirm
code
Confirm
code
Multiplane Page
Program setup
code
Read Status register
Page Program
setup code
A12-A17 = set to 'Low'
A18 = set to 'Low'
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
A19-A28 = set to 'Low'
1) The same row address, except for A18, is applied to the two blocks.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
11h
10h
80h
81h
Data
input
First plane
Second plane
(1024 block)
(1024 block)
Block 0
Block 1
Block 2
Block 3
.
.
.
.
Block 2044
Block 2046
Block 2045
Block 2047
a) Traditional protocol
CL
W
AL
R
I/O
80h C1A C2A R1A R2A R3A
D0A D1A ... DnA
11h
... DnB
10h
80h C1B C2B R1B R2B R3B
D0B D1B
tIPBSY
tBLBH2
(Program Busy time)
RB
Busy
b) ONFI 1.0 protocol
Busy
ai13171c
1. This address scheme refers to x 8 devices. Please, remember to use the appropriate scheme for x 16 devices.
6.5
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
28/69
NAND02G-B2D
Device operations
The NAND02G-B2D device features automatic EDC (error detection code) during a copy
back operation. Consequently, external ECC is no longer required. The errors detected
during copy back operations can be read by performing a read EDC Status register
operation (see Section 6.13: Read EDC status register). See also Section 6.9 for details of
EDC operations.
The copy back program operation requires the following four steps:
1. The first step reads the source page. The operation copies all 2112 bytes from the
page into the data buffer. It requires:
–
–
–
1 bus write cycle to set up the command
5 bus write cycles to input the source page address
1 bus write cycle to issue the confirm command code
2. When the device returns to the ready state (Ready/Busy High), optional data readout is
allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus
cycles to input the target page address. The address A18 in x 8 devices (A17 in x 16
devices) must be the same for the source and target page
3. Then, the confirm command is issued to start the P/E/R controller.
To see the data input cycle for modifying the source page and an example of the copy back
program operation, refer to Figure 13: Copy back program (without readout of data).
Figure 15: Page copy back program with random data input shows a data input cycle to
modify a portion or a multiple distant portion of the source page.
Figure 13. Copy back program (without readout of data)
Source
Add Inputs
Target
Add Inputs
I/O
10h
70h
SR0
35h
85h
00h
Read
Code
Copy Back
Code
Read Status Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858b
1. Copy back program is only permitted between odd address pages or even address pages.
Figure 14. Copy back program (with readout of data)
Source
Add Inputs
Target
Add Inputs
I/O
10h
70h
SR0
35h
85h
00h
Data Outputs
Read
Code
Copy Back
Code
Read Status
Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858c
29/69
Device operations
NAND02G-B2D
Figure 15. Page copy back program with random data input
2 Cycle
Add Inputs
Target
Add Inputs
Source
Add Inputs
I/O
35h
SR0
00h
85h
Data 85h
Data 10h
70h
Read
Code
Copy Back
Code
Unlimited number of repetitions
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai11001
6.6
Multiplane copy back program
In addition to multiplane page program, the NAND02G-B2D device supports multiplane
copy back program.
A Multiplane Copy Back Program command requires exactly the same steps as a multiplane
page program and must satisfy the same time constraints (see Section 6.4: Multiplane page
program).
Prior to executing the multiplane copy back program, two single page read operations must
be executed to copy back the first page from the first plane and the second page from the
second plane.
Two different sequences are allowed for the multiplane copy back operation:
1. A traditional one (85h command, address insertion for the first plane, 11h command,
81h command, address insertion for the second plane, 10h command)
2. ONFI 1.0 (85h command, address insertion for the first plane, 11h command, 85h
command, address insertion for the second plane, 10h command).
The EDC check is also performed during the multiplane copy back program. Errors during
multiplane copy back operations can be detected by performing a read EDC Status register
operation (see Section 6.13: Read EDC status register).
If the multiplane copy back program fails, an error is signaled on bit SR0 of the Status
register. To know which page of the two planes failed, the Read Status Enhanced command
must be executed twice, once for each plane (see Section 6.12). Figure 16 provides a
description of multiplane copy back program waveforms.
30/69
NAND02G-B2D
Device operations
Figure 16. Multiplane copy back program
Copy back
code
Copy back
code
Read Status Register
Read
code
Read
code
2
Add. 5
cycles
Add. 5
cycles
Add. 5
cycles
Add. 5
cycles
I/O
35h
10h
70h SR0
35h
00h
85h
11h
81h
00h
Col. Add. 1, 2
Col. Add. 1, 2
Col. Add. 1, 2
Col. Add. 1, 2
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Source address on 1st plane
Source address on 2nd plane
Destination address
A0-A11 = set to 'Low'
A12-A17 = set to 'Low'
A18 = set to 'Low'
Destination address
A0-A11 = set to 'Low'
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
A19-A28 = set to 'Low'
tBLBH1
tBLBH1
tIPBSY
tBLBH2
(Read Busy time)
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
Busy
Busy
Second plane
First plane
Source page
Source page
Target page
(1): Read for copy back on first plane
(2): Read for copy back on second plane
(3): Two-plane copy back program
Target page
(1)
(3)
(2)
(3)
Main area
a) Traditional sequence.
Main area
Spare area
Spare area
CL
W
AL
R
O 0-7
60h R1A R2A R3A D1h
tIPBSY
60h R1B R2B R3B
D0h
tBLBH2
(Program Busy time)
RB
Busy
Busy
b) ONFI 1.0 sequence.
ai13172c
1. This address scheme refers to x 8 devices. Please, remember to use the appropriate scheme for x 16 devices.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
31/69
Device operations
NAND02G-B2D
6.7
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of the following three steps (refer to Figure 17: Block erase):
1. One bus cycle is required to set up the Block Erase command. Only addresses A18-
A28 are used; the other address inputs are ignored
2. Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 7: Address definition (x 8 devices) for the block addresses of each device
3. One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 17. Block erase
tBLBH3
(Erase Busy time)
RB
Busy
Block address
inputs
I/O
60h
D0h
70h
SR0
Confirm
code
Read Status Register
Block erase
setup code
ai07593
32/69
NAND02G-B2D
Device operations
6.8
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane.
This operation consists of the following three steps (refer to Figure 18: Multiplane block
erase):
1. 10 bus cycles are required to set up the Block Erase command and load the addresses
of the blocks to be erased. The Setup command followed by the address of the block to
be erased must be issued for each block. t
busy time is required between the
IEBSY
insertion of first and the second block addresses. As for multiplane page program, the
address of the first and second page must be within the first plane (A18 = 0 for x8
devices, A17 = 0 for x16 devices) and second plane (A18 = 1 for x8 devices, A17 = 1 for
x16 devices), respectively
2. one bus cycle is then required to issue the Multiplane Block Erase Confirm command
and start the P/E/R controller
If the multiplane block erase fails, an error is signaled on bit SR0 of the Status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 18. Multiplane block erase
tBLBH3
(Erase Busy time)
RB
Busy
Block address
inputs
Block address
inputs
I/O
60h
60h
D0h
70h
SR0
A18=1
A12-A17=0
A17-A29=valid
A18=0
A12-A17=0
A17-A29=0
Block Erase
Setup code
Confirm
code
Read Status
register
Block Erase
Setup code
a) Traditional sequence
CL
W
AL
R
I/O 0-7
60h R1A R2A R3A D1h
tIPBSY
60h R1B R2B R3B
D0h
tBLBH2
(Program Busy time)
RB
Busy
Busy
b) ONFI 1.0 sequence.
ai13173c
1. This address scheme refers to x 8 devices. Please remember to use the appropriate scheme for x 16 devices.
33/69
Device operations
NAND02G-B2D
6.9
Error detection code (EDC)
The EDC is performed automatically during all copy back operations. It starts immediately
after the device becomes busy.
The EDC detects 1 single bit error per EDC unit. Each EDC unit has a density of 528 bytes
(or 264 words), split into 512 bytes of main area and 16 bytes of spare area (or 256 + 8
words). Refer to Table 10 and Figure 19 for EDC unit addresses definition. EDC results can
only be retrieved during copy back program and multiplane copy back operations using the
Read EDC Status Register command (see Section 6.13).
To properly use the EDC, the following conditions apply:
■
■
Page program operations must be performed on a whole page, or on whole EDC unit(s)
The modification of the content of an EDC unit using a random data input before the
copy back program, must be performed on the whole EDC unit. It can only be done
once per EDC unit. Any partial modification of the EDC unit results in the corruption of
the on-chip EDCs.
Figure 19. Page organization
Page = 4 EDC units
Main area (2048 bytes/1024 words)
Spare area (64 bytes/32 words)
A area
B area
C area
D area
E area
F area
G area
H area
(512 bytes/ (512 bytes/ (512 bytes/ (512 bytes/ (16 bytes/ (16 bytes/ (16 bytes/ (16 bytes/
256 words) 256 words) 256 words) 256 words) 8 words)
8 words) 8 words)
8 words)
AI13179b
Table 10. Address definition for EDC units (x8 devices)
Main area
EDC unit
Spare area
Area name
Column address
Area name
Column address
1st 528-byte EDC unit
2nd 528-byte EDC unit
3rd 528-byte EDC unit
4th 528-byte EDC unit
A
B
C
D
0 to 511
E
F
2048 to 2063
2064 to 2079
2080 to 2095
2096 to 2111
512 to 1023
1024 to1535
1536 to 2047
G
H
34/69
NAND02G-B2D
Device operations
Table 11. Address definition for EDC units (x16 devices)
Main area
EDC unit
Spare area
Area name
Column address
Area name
Column address
1st 264-word EDC unit
2nd 264-word EDC unit
3rd 264-word EDC unit
4th 264-word EDC unit
A
B
C
D
0 to 255
256 to 511
512 to 767
768 to 1023
E
F
1024 to 1031
1032 to 1039
1040 to 1047
1048 to 1055
G
H
6.10
Reset
The Reset command is used to reset the command interface and Status register. If the
Reset command is issued during any operation, the operation is aborted. If the aborted
operation is a program or erase operation, the contents of the memory locations being
modified are no longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for t
after the Reset command is issued. The value
BLBH4
of t
depends on the operation that the device was performing when the command was
BLBH4
issued. Refer to Table 28 for the values.
6.11
Read status register
The devices contain a Status register that provides information on the current or previous
program or erase operation. The various bits in the Status register convey information and
errors on the operation.
The Status register is read by issuing the Read Status Register command. The Status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the Status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a Random Read cycle, a new Read command must be issued to
continue with a Page Read operation.
The Status register bits are summarized in Table 12: Status register bits. Refer to Table 12
in conjunction with the following sections.
6.11.1
Write protection bit (SR7)
The Write Protection bit identifies if the device is protected or not. If the Write Protection bit
is set to ‘1’ the device is not protected and program or erase operations are allowed. If the
Write Protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
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Device operations
NAND02G-B2D
6.11.2
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache operations, SR6 acts as a Cache Ready/Busy bit, which indicates whether the
Cache register is ready to accept new data. When SR6 is set to '0', the Cache register is
busy, and when SR6 is set to '1', the Cache register is ready to accept new data.
During all other operations, SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
6.11.3
P/E/R controller bit (SR5)
The Program/Erase/Read controller bit indicates whether the P/E/R controller is active or
inactive during cache operations. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
Note:
This bit is only valid for cache operations.
6.11.4
Error bit (SR0)
The Error bit is used to identify if any errors have been detected by the P/E/R controller. The
Error bit is set to ’1’ when a program or erase operation has failed to write the correct data to
the memory. If the Error bit is set to ‘0’ the operation has completed successfully.
6.11.5
SR4, SR3, SR2 and SR1 are reserved
Table 12. Status register bits
Bit
Name
Logic level
Definition
'1'
'0'
'1'
'0'
'1'
'0'
Not protected
Protected
SR7
Write protection
P/E/R controller inactive, device ready
P/E/R controller active, device busy
P/E/R controller inactive, device ready
P/E/R controller active, device busy
Program/Erase/Read
controller
SR6
SR5
Program/Erase/Read
controller(1)
SR4, SR3,
SR2, SR1
Reserved
Don’t care
‘1’
‘0’
Error – operation failed
SR0
Generic error
No error – operation successful
1. Only valid for cache operations.
36/69
NAND02G-B2D
Device operations
6.12
Read status enhanced
In NAND flash devices with multiplane architecture, it is possible to independently read the
status register of a single plane using the Read Status Enhanced command. If the error bit
of the Status register, SR0, reports an error during or after a multiplane operation, the Read
Status Enhanced command is used to know which of the two planes contains the page that
failed the operation. Three address cycles are required to address the selected block and
page (A12-A28 for x 8 devices and A11-A27 for x 16 devices).
The output of the Read Status Enhanced command has the same coding as the Read
Status command. See Table 12 for a full description and Figure 30 for the Read Status
Enhanced waveform.
6.13
Read EDC status register
The devices contain an EDC Status register, which provides information on the errors that
occurred during the read cycles of the copy back and multiplane copy back operations. In
the case of multiplane copy back program it is not possible to distinguish which of the two
read operations caused the error.
The EDC Status register is read by issuing the Read EDC Status Register command.
After issuing the Read EDC Status Register command, a read cycle outputs the content of
the EDC Status register to the I/O pins on the falling edge of Chip Enable or Read Enable
signals, whichever occurs last. The operation is similar to the Read Status Register
command.
Table 13: EDC status register bits summarizes the EDC Status register bits. See Figure 29
for a description of register EDC Status register waveforms.
Table 13. EDC status register bits
Bit
Name
Logic level
Definition
Copy back or multiplane copy back
operation failed
‘1’
0
Pass/Fail
Copy back or multiplane copy back
operation succeeded
‘0’
‘1’
Error
1
2
EDC status
EDC validity
‘0’
No error
Valid
‘1’
‘0’
Invalid
-
3
4
Reserved
Reserved
‘Don’t care’
‘Don’t care’
-
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
Ready
Busy
5
6
7
Ready/Busy(1)
Ready/Busy(1)
Write Protect
Ready
Busy
Not protected
Protected
1. See Table 12: Status register bits for a description of SR5 and SR6 bits.
37/69
Device operations
NAND02G-B2D
6.14
Read electronic signature
The devices contain a manufacturer code and device code. The following three steps are
required to read these codes:
1. One bus write cycle to issue the Read Electronic Signature command (90h)
2. One bus write cycle to input the address (00h)
3. Five bus read cycles to sequentially output the data (as shown in Table 14: Electronic
signature).
The device remains in this state until a new command is issued
Table 14. Electronic signature
Byte 3
Byte 4
Byte 5
Root part number
Byte 1
Byte 2
(see Table 15)
(see Table 16)
(see Table 17)
NAND02GR3B2D
NAND02GW3B2D
NAND02GR4B2D
NAND02GW4B2D
20h
20h
AAh
DAh
BAh
CAh
10h
10h
10h
10h
15h
95h
55h
D5h
44h
44h
44h
44h
0020h
0020h
Table 15. Electronic signature byte 3
I/O
Definition
Value
Description
0 0
0 1
1 0
1 1
1
2
4
8
I/O1-I/O0
Internal chip number
Cell type
0 0
0 1
1 0
1 1
2-level cell
4-level cell
8-level cell
I/O3-I/O2
I/O5-I/O4
16-level cell
0 0
0 1
1 0
1 1
1
2
4
8
Number of simultaneously
programmed pages
0
1
Not supported
Supported
Interleaved programming
between multiple devices
I/O6
I/O7
0
1
Not supported
Supported
Cache program
38/69
NAND02G-B2D
Device operations
Description
Table 16. Electronic signature byte 4
I/O
Definition
Value
0 0
0 1
1 0
1 1
1 Kbytes
2 Kbytes
4 Kbytes
8 Kbytes
Page size
I/O1-I/O0
(without spare area)
Spare area size
(byte/512 byte)
0
1
8
I/O2
16
0 0
1 0
0 1
1 1
30/50 ns
25 ns
Minimum sequential access
time
I/O7, I/O3
Reserved
Reserved
0 0
0 1
1 0
1 1
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
Block size
I/O5-I/O4
I/O6
(without spare area)
0
1
x8
Organization
x16
Table 17. Electronic signature byte 5
I/O
Definition
Value
Description
I/O1 - I/O0
Reserved
0 0
0 0
0 1
1 0
1 1
1 plane
2 planes
4 planes
8 planes
I/O3 - I/O2
Plane number
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
64 Mbits
128 Mbits
256 Mbits
512 Mbits
1 Gb
Plane size
I/O6 - I/O4
(without spare area)
2 Gb
4 Gb
8 Gb
I/O7
Reserved
0
39/69
Device operations
NAND02G-B2D
6.15
Read ONFI signature
To recognize NAND flash devices that are compatible with the ONFI 1.0 command set, the
Read Electronic Signature command can be issued, followed by an address of 20h. The
next four bytes output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word.
Reading beyond four bytes produces indeterminate values. The device remains in this state
until a new command is issued.
Figure 32 provides a description of the read ONFI signature waveform and Table 18
provides the definition of the output bytes.
Table 18. Read ONFI signature
Value
ASCII character
1st byte
2nd byte
3rd byte
4th byte
5th byte
4Fh
4Eh
O
N
46h
F
49h
I
Undefined
Undefined
6.16
Read parameter page
The Read Parameter Page command retrieves the data structure that describes the NAND
flash organization, features, timings and other behavioral parameters. This data structure
enables the host processor to automatically recognize the NAND flash configuration of a
device. The whole data structure is repeated at least five times.
See Figure 39 for a description of the read parameter page waveform.
The Random Data Read command can be issued during execution of the read parameter
page to read specific portions of the parameter page.
The Read Status command may be used to check the status of read parameter page during
execution. After completion of the Read Status command, 00h is issued by the host on the
command line to continue with the data output flow for the Read Parameter Page command.
Read status enhanced is not be used during execution of the Read Parameter Page
command.
Table 19 defines the parameter page data structure. For parameters that span multiple
bytes, the least significant byte of the parameter corresponds to the first byte.
Values are reported in the parameter page in bytes when referring to items related to the
size of data access (as in an x 8 data access device). For example, the chip returns how
many data bytes are in a page. For a device that supports x 16 data access, the host is
required to convert byte values to word values for its use. Unused fields are set to 0h.
For more detailed information about parameter page data bits, refer to ONFI Specification
1.0 section 5.4.1.
40/69
NAND02G-B2D
Device operations
Table 19. Parameter page data structure
Byte
O/M(1)
Description
Parameter page signature
– Byte 0: 4Fh, ‘O’
– Byte 1: 4Eh, ‘N’
– Byte 2: 46h, ‘F’
0-3
M
– Byte 3: 49h, ‘I’
Revision number
Bit 2 to bit 15 Reserved (0)
4-5
M
Bit 1
Bit 0
1 = supports ONFI version 1.0
Reserved (0)
Features supported
Bit 5 to bit 15 Reserved (0)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 = supports odd to even page copy back
1 = supports interleaved operations
6-7
M
1 = supports non-sequential page programming
1 = supports multiple LUN operations
1 = supports 16-bit data bus width
Optional commands supported
Bit 6 to bit 15 Reserved (0)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 = supports read unique ID
1 = supports copy back
8-9
M
1 = supports read status enhanced
1 = supports get features and set features
1 = supports read cache commands
1 = supports page cache program command
Reserved (0)
10-31
32-43
44-63
64
M
M
M
O
Device manufacturer (12 ASCII characters)
Device model (20 ASCII characters)
JEDEC manufacturer ID
65-66
67-79
80-83
84-85
86-89
90-91
92-95
Date code
Reserved (0)
M
M
M
M
M
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
41/69
Device operations
NAND02G-B2D
Table 19. Parameter page data structure (continued)
Byte
O/M(1)
Description
96-99
100
M
M
Number of blocks per logical unit (LUN)
Number of logical units (LUNs)
Number of address cycles
101
M
Bit 4 to bit 7
Bit 0 to bit 3
Column address cycles
Row address cycles
102
103-104
105-106
107
M
M
M
M
M
M
Number of bits per cell
Bad blocks maximum per LUN
Block endurance
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
108-109
110
Partial programming attributes
Bit 5 to bit 7
4
Reserved
1 = partial page layout is partial page data followed by
partial page spare
111
M
Bit 1 to bit 3
0
Reserved
1 = partial page programming has constraints
Number of bits ECC correctability
112
113
M
M
Number of interleaved address bits
Bit 4 to bit 7
Bit 0 to bit 3
Reserved (0)
Number of interleaved address bits
Interleaved operation attributes
Bit 4 to bit 7
Bit 3
Reserved (0)
Address restrictions for program cache
1 = program cache supported
1 = no block address restrictions
Overlapped / concurrent interleaving support
Reserved (0)
114
O
M
Bit 2
Bit 1
Bit 0
115-127
128
I/O pin capacitance
42/69
NAND02G-B2D
Device operations
Table 19. Parameter page data structure (continued)
Byte
O/M(1)
Description
Timing mode support
Bit 6 to bit 15 Reserved (0)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0, shall be 1
129-130
M
Program cache timing mode support
Bit 6 to bit 15 Reserved (0)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0
tPROG maximum page program time (µs)
131-132
O
133-134
135-136
137-138
139-163
164-165
166-253
254-255
256-511
512-767
M
M
M
M
M
M
M
M
M
tBERS maximum block erase time (µs)
tR maximum page read time (µs)
Reserved (0)
Vendor specific revision number
Vendor specific
Integrity CRC
Value of bytes 0-255
Value of bytes 0-255
768+
O
Additional redundant parameter pages
1. O = optional, M = mandatory.
43/69
Data protection
NAND02G-B2D
7
Data protection
The devices feature a Write Protect, WP, pin, which protects the device against program and
erase operations. It is recommended to keep WP at V during power-up and power-down.
IL
8
Software algorithms
This section provides information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunnelling using
high voltage. Exposing the device to high voltage for extended periods damages the oxide
layer.
To extend the number of program and erase cycles and increase the data retention, the:
■
Number of program and erase cycles is limited (see Table 21: Program erase times and
program erase endurance cycles for the values)
■
Implementation of a garbage collection, a wear-leveling algorithm and an error
correction code is recommended.
To help integrate a NAND memory into an application, Numonyx provides a file system OS
native reference software, which supports the basic commands of file management.
Contact the nearest Numonyx sales office for more details.
8.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices that have all valid blocks. A bad block does not affect the
performance of valid blocks because it is isolated from the bit and common source lines by a
select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st and 6th bytes or the
1st word in the spare area of the 1st page, does not contain FFh, is a bad block.
The bad block information must be read before any erase is attempted as the bad block
Information may be erased. For the system to be able to recognize the bad blocks based on
the original information, the creation of a bad block table following the flowchart shown in
Figure 20: Bad block management flowchart is recommended.
44/69
NAND02G-B2D
Software algorithms
8.2
NAND flash memory failure modes
Over the lifetime of the device bad blocks may develop. To implement a highly reliable
system, the possible failure modes must be considered.
■
Program/erase failure
In this case, the block has to be replaced by copying the data to a valid block. These
additional bad blocks can be identified because attempts to program or erase them
gives errors in the Status register. As the failure of a page program operation does not
affect the data in other pages in the same block, the block can be replaced by
reprogramming the current data and copying the rest of the replaced block to an
available valid block. The Copy Back Program command copies the data to a valid
block. See Section 6.5: Copy back program for more details.
■
Read failure
In this case, ECC correction must be implemented. To efficiently use the memory
space, the recovery of a single-bit error in read by ECC, without replacing the whole
block, is recommended.
Refer to Table 20: Block failure for the recommended procedure to follow if an error occurs
during an operation.
Table 20. Block failure
Operation
Procedure
Erase
Program
Read
Block replacement
Block replacement
ECC
Figure 20. Bad block management flowchart
START
Block Address =
Block 0
Increment
Block Address
Update
Bad Block table
Data
= FFh?
NO
NO
YES
Last
block?
YES
END
AI07588C
45/69
Software algorithms
NAND02G-B2D
8.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page,
resulting in the previous page being marked as invalid. After several updates it is necessary
to remove invalid pages to free memory space.
To free this memory space and allow further program operations, the implementation of a
garbage collection algorithm is recommended. In garbage collection software, the valid
pages are copied into a free area and the block containing the invalid pages is erased as
show in Figure 21.
Figure 21. Garbage collection
Old area
New area (After GC)
Valid
page
Invalid
page
Free
page
(Erased)
AI07599B
8.4
Wear-leveling algorithm
For write-intensive applications, the implementation of a wear-leveling algorithm is
recommended to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm, not all blocks get used at the same
rate. The wear-leveling algorithm insures that equal use is made of all the available write
cycles for each block. There are two wear-leveling levels:
■
First level wear-leveling, where new data is programmed to the free blocks that have
had the fewest write cycles
■
Second level wear-leveling, where long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
46/69
NAND02G-B2D
Software algorithms
8.5
Error correction code
The user must implement an error correction code (ECC) to identify and correct errors in the
data stored in the NAND flash memories. For every 2048 bits in the device, the
implementation of 22 bits of ECC (16 bits for line parity plus 6 bits for column parity) is
required.
Figure 22. Error detection
New ECC generated
during read
XOR previous ECC
with new ECC
NO
NO
>1 bit
= zero?
All results
= zero?
YES
YES
22 bit data = 0
11 bit data = 1
1 bit data = 1
ECC Error
Correctable
Error
No Error
ai08332
47/69
Program and erase times and endurance cycles
NAND02G-B2D
9
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Table 21.
Table 21. Program erase times and program erase endurance cycles
NAND flash
Parameters
Unit
Min
Typ
Max
Page program time
200
200
250
1.5
1.5
2
700
700
800
2
µs
µs
3.0 V
1.8 V
Multiplane program time
Block erase time
µs
ms
3.0 V
1.8 V
2
ms
Multiplane block erase time
Multiplane program busy time (tIPBSY
2.5
1
ms
)
0.5
0.5
3
µs
Multiplane erase busy time (tIEBSY
)
1
µs
Cache read busy time (tRCBSY
)
tR
µs
Program/erase cycles per block (with ECC)
Data retention
100,000
10
cycles
years
48/69
NAND02G-B2D
Maximum ratings
10
Maximum ratings
Stressing the device above the ratings listed in Table 22: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 22. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
TSTG
Temperature under bias
– 50
– 65
– 0.6
– 0.6
125
150
4.6
°C
°C
V
Storage temperature
Input or output voltage
Supply voltage
(1)
VIO
VDD
4.6
V
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
49/69
DC and AC parameters
NAND02G-B2D
11
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the following DC and AC characteristics
tables are derived from tests performed under the measurement conditions summarized in
Table 23. Designers should check that the operating conditions in their circuit match the
measurement conditions when relying on the quoted parameters.
Table 23. Operating and AC measurement conditions
NAND flash
Parameter
Units
Min
Max
1.8 V device
3.0 V device
Grade 1
1.7
2.7
0
1.95
3.6
70
Supply voltage (VDD
)
V
°C
°C
pF
pF
V
Ambient temperature (TA)
Grade 6
–40
30
50
0
85
1.8 V device
3.0 V device
Load capacitance (CL) (1 TTL GATE
and CL)
Input pulses voltages
VDD
Input and output timing ref. voltages
Output circuit resistor Rref
Input rise and fall times
V
DD/2
V
8.35
5
kΩ
ns
(1)
Table 24. Capacitance
Symbol
Parameter
Test condition
Typ
Max
Unit
CIN
Input capacitance
VIN = 0 V
10
pF
Input/output
CI/O
VIL = 0 V
10
pF
capacitance(2)
1.
TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double in stacked devices.
50/69
NAND02G-B2D
DC and AC parameters
Figure 23. Equivalent testing circuit for AC characteristics measurement
V
DD
2R
ref
NAND Flash
C
L
2R
ref
GND
GND
Ai11085
Table 25. DC characteristics (1.8 V devices)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
Read
IDD1
-
10
20
mA
E=VIL, OUT = 0 mA
I
Operating
current
IDD2
IDD3
Program
Erase
-
-
-
-
10
10
20
20
mA
mA
E=VDD-0.2,
WP=0/VDD
IDD5
Standby current (CMOS(1)
-
10
50
µA
ILI
ILO
Input leakage current(1)
Output leakage current(1)
Input high voltage
VIN= 0 to VDDmax
VOUT= 0 to VDDmax
-
-
-
-
-
-
-
-
-
±10
µA
µA
V
-
±10
VIH
0.8 * VDD
VDD + 0.3
VIL
Input low voltage
-
-0.3
0.2 * VDD
V
VOH
VOL
Output high voltage level
Output low voltage level
Output low current (RB)
IOH = -100 µA
IOL = 100 µA
VOL = 0.1 V
VDD - 0.1
-
0.1
4
V
-
V
IOL (RB)
3
mA
VDD supply voltage (erase and
program lockout)
VLKO
-
-
-
1.1
V
1. Leakage current and standby current double in stacked devices.
51/69
DC and AC parameters
NAND02G-B2D
Table 26. DC characteristics (3 V devices)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
tRLRL minimum
Sequential
read
IDD1
-
15
30
mA
E=VIL, OUT = 0 mA
I
Operating
current
IDD2
IDD3
Program
Erase
-
-
-
-
15
15
30
30
1
mA
mA
mA
I
Standby current (TTL)(1)
E=VIH, WP=0/VDD
DD4
E=VDD-0.2,
WP=0/VDD
IDD5
Standby current (CMOS)(1)
-
10
50
µA
ILI
ILO
Input leakage current(1)
Output leakage current(1)
Input high voltage
VIN= 0 to VDDmax
VOUT= 0 to VDDmax
-
-
-
-
-
-
-
-
-
±10
±10
µA
µA
V
-
VIH
0.8 VDD
VDD+0.3
0.2 VDD
-
VIL
Input low voltage
-
-0.3
2.4
-
V
VOH
VOL
Output high voltage level
Output low voltage level
Output low current (RB)
IOH = -400 µA
IOL = 2.1 mA
VOL = 0.4 V
V
0.4
V
IOL (RB)
8
10
mA
VDD supply voltage (erase and
program lockout)
VLKO
-
-
-
1.8
V
1. Leakage current and standby current double in stacked devices.
Table 27. AC characteristics for command, address, data input
Alt.
Symbol
Parameter
1.8 V
25
3 V
12
Unit
ns
symbol
tALLWH
tALHWH
tCLHWH
tCLLWH
tDVWH
tELWH
Address Latch Low to Write Enable High
Address Latch High to Write Enable High
Command Latch High to Write Enable High
Command Latch Low to Write Enable High
Data Valid to Write Enable High
tALS
AL setup time
CL setup time
Min
tCLS
Min
25
12
ns
tDS
tCS
Data setup time
E setup time
AL hold time
Min
Min
Min
20
35
10
12
20
5
ns
ns
ns
Chip Enable Low to Write Enable High
Write Enable High to Address Latch High
Write Enable High to Command Latch High
Write Enable High to Command Latch Low
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Write Enable Low to Write Enable Low
tWHALH
tWHCLH
tWHCLL
tWHDX
tWHEH
tWHWL
tWLWH
tWLWL
tALH
tCLH
CL hold time
Min
10
5
ns
tDH
tCH
tWH
tWP
tWC
Data hold time
E hold time
Min
Min
10
10
15
25
45
5
ns
ns
ns
ns
ns
5
W high hold time Min
10
12
25
W pulse width
Min
Min
Write cycle time
52/69
NAND02G-B2D
DC and AC parameters
(1)
Table 28. AC Characteristics for operations
Alt.
Symbol
Parameter
1.8 V
3 V
Unit
symbol
tALLRL1
tALLRL2
tBHRL
Read electronic signature
Read cycle
Min
Min
10
10
20
25
700
2
10
10
20
25
700
2
ns
ns
ns
µs
µs
ms
µs
µs
µs
µs
ns
ns
ns
Address Latch Low to
Read Enable Low
tAR
tRR
Ready/Busy High to Read Enable Low
Read Busy time
Min
tBLBH1
tBLBH2
tBLBH3
Max
Max
Max
Max
Max
Max
Max
Min
tPROG
tBERS
Program Busy time
Erase Busy time
Ready/Busy Low to
Ready/Busy High
Reset Busy time, during ready
5
5
Reset Busy time, during read
Reset Busy time, during program
Reset Busy time, during erase
5
5
tBLBH4
tRST
10
500
10
0
10
500
10
0
tCLLRL
tDZRL
tCLR
tIR
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Min
tEHQZ
tEHALX
tEHCLX
tRHQZ
tELQV
tCHZ
Chip Enable High to Output Hi-Z
Max
30
30
Chip Enable High to Address Latch ‘don’t care’
Chip Enable High to Command Latch ‘don’t care’
Read Enable High to Output Hi-z
tCSD
Min
10
10
ns
tRHZ
tCEA
Max
Max
100
45
100
25
ns
ns
Chip Enable Low to Output Valid
Read Enable High to
Read Enable High Hold time
Read Enable Low
tRHRL
tREH
tCOH
Min
15
10
ns
tEHQX
tRHQX
tRLQX
Chip Enable high to Output Hold
Min
Min
Min
15
15
5
15
15
5
ns
ns
ns
tRHOH Read Enable High to Output Hold
tRLOH Read Enable Low to Output Hold (EDO mode)
Read Enable Low to
tRLRH
tRLRL
tRP
Read enable pulse width
Min
Min
25
45
12
25
ns
ns
Read Enable High
Read Enable Low to
Read Enable Low
tRC
Read cycle time
Read enable access time
Read ES Access time(2)
Read Enable Low to
Output Valid
tRLQV
tREA
Max
Max
30
25
20
25
ns
µs
Write Enable High to
Ready/Busy High
tWHBH
tR
Read Busy time
tWHBL
tWHRL
tRHWL
tWB
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
Max
Min
Min
100
60
100
60
ns
ns
ns
tWHR
tRHW Read Enable High to Write Enable Low
100
100
Last address latched to data loading time during program
operations
(3)
tWHWH
tADL
Min
Min
100
100
70
ns
ns
tVHWH
tVLWH
(4)
tWW
Write Protection time
100
1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 40, Figure 41 and
Figure 42.
53/69
DC and AC parameters
NAND02G-B2D
2. ES = electronic signature.
3. tADL is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
4. During a program/erase enable operation, tWW is the delay from WP high to W High. During a program/erase disable
operation, tWW is the delay from WP Low to W High.
Figure 24. Command latch AC waveforms
CL
tCLHWH
tWHCLL
(CL Setup time)
(CL Hold time)
tWHEH
(E Hold time)
tELWH
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
I/O
tDVWH
(Data Setup time)
tWHDX
(Data Hold time)
Command
ai12470b
54/69
NAND02G-B2D
DC and AC parameters
Figure 25. Address latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tELWH
(E Setup time)
tWLWL
tWLWL
tWLWL
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tWHALL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
I/O
tDVWH
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
(Data Setup time)
tWHDX
tWHDX
tWHDX
ai12471
(Data Hold time)
Adrress
cycle 3
Adrress
cycle 2
Adrress
cycle 4
Adrress
cycle 5
Adrress
cycle 1
Figure 26. Data input latch AC waveforms
tWHCLH
(CL Hold time)
CL
E
tWHEH
(E Hold time)
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tWHDX
tDVWH
tWHDX
(Data Setup time)
tWHDX
(Data Hold time)
Data In
Last
I/O
Data In 0
Data In 1
ai12472
1. The last data input is the 2112th.
55/69
DC and AC parameters
NAND02G-B2D
Figure 27. Sequential data output after read AC waveforms
tRLRL
(Read Cycle time)
E
tEHQX
tEHQZ
tRHRL
(R High Holdtime)
R
tRHQZ
tRHQZ
(2)
tRHQX
tRLQV
tRLQV
tRLQV
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai13174
1. CL = Low, AL = Low, W = High.
2. tRHQX is applicable for frequencies lower than 33 MHz (for instance, tRLRL higher than 30 ns).
Figure 28. Sequential data output after read AC waveforms (EDO mode)
tRLRL
E
tEHQX
tEHQZ
tRLRH
tRLQV
tRHRL
R
tRHQZ
tELQV
tRLQX
tRLQV
(2)
tRHQX
(R Accesstime)
I/O
RB
Data Out
Data Out
Data Out
tBHRL
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH
.
2. tRLQX is applicable for frequencies high than 33 MHz (for instance, tRLRL lower than 30 ns).
56/69
NAND02G-B2D
DC and AC parameters
Figure 29. Read Status register or read EDC Status register AC waveform
tCLLRL
CL
tWHCLL
tCLHWH
tWHEH
E
tELWH
tWLWH
W
R
tELQV
tEHQZ
tWHRL
tEHQX
tDZRL
tRHQZ
tRHQX
tDVWH
(Data Setup time)
tWHDX
tRLQV
(Data Hold time)
Status Register
Output
I/O
70h or 7Bh
ai13177
Figure 30. Read status enhanced waveform
CL
tWHRL
W
tALLRL2
AL
R
I/O 0-7
Status Register
output
78h
Address 1
Address 2
Address 3
ai14408b
57/69
DC and AC parameters
NAND02G-B2D
Figure 31. Read electronic signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
00h
Byte1
Byte2
Byte3
Byte4
Byte5
Man.
code
Device
code
Read Electronic 1st Cycle
see Note.1
Signature
Command
Address
ai13178
1. Refer to Table 14 for the values of the manufacturer and device codes, and to Table 15, Table 16, and Table 17 for the
information contained in byte 3, byte 4, and byte 5.
Figure 32. Read ONFI signature waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES access time)
I/O
90h
20h
4Fh
4Eh
46h
49h
XXh
Read Electronic 1st cycle
Signature
command
address
ai13178b
58/69
NAND02G-B2D
DC and AC parameters
Figure 33. Page read operation AC waveform
tEHALX
tEHCLX
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
Data
N
Data
N+1
Data
N+2
Data
Last
Add.N Add.N Add.N Add.N
cycle 1 cycle 2 cycle 3 cycle 4
Add.N
cycle 5
I/O
30h
00h
Data Output
from Address N to Last Byte or Word in Page
Command Address N Input
Code
Busy
ai12474b
59/69
DC and AC parameters
NAND02G-B2D
Figure 34. Page program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHBL
tWHWH
tWHRL
tBLBH2
(Program Busy time)
AL
R
Add.N Add.N
cycle 4 cycle 5
Add.N
Add.N
Add.N
I/O
RB
80h
Last
N
10h
70h
SR0
cycle 1 cycle 2
cycle 3
Confirm
Code
Page Program
Setup Code
Page
Program
Address Input
Data Input
Read Status Register
ai12475b
60/69
NAND02G-B2D
DC and AC parameters
Figure 35. Block erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
AL
R
tBLBH3
tWHBL
(Erase Busy time)
tWHRL
Add.
Add.
Add.
I/O
RB
70h
SR0
60h
D0h
cycle 1 cycle 2
cycle 3
Block Erase
Setup Command
Confirm
Code
Block Erase
Read Status Register
Block Address Input
ai08038c
Figure 36. Reset AC waveform
W
AL
CL
R
I/O
RB
FFh
tBLBH4
(Reset Busy time)
ai08043
61/69
DC and AC parameters
NAND02G-B2D
Figure 37. Program/erase enable waveform
W
W
tVHWH
tVHWH
WP
RB
WP
RB
I/O
80h
I/O
60h
Program setup
Erase setup
ai12477b
Figure 38. Program/erase disable waveform
W
W
tVLWH
tVLWH
WP
RB
WP
High
High
RB
I/O
60h
I/O
80h
Program disable
Erase disable
ai12478b
Figure 39. Read parameter page waveform
CL
W
AL
R
I/O0-7
R/B
ECh
00h
P0
P1
...
P0
1
P1
1
...
0
0
tBLBH1
ai14409
62/69
NAND02G-B2D
DC and AC parameters
11.1
Ready/busy signal electrical characteristics
Figure 41, Figure 40 and Figure 42 show the electrical characteristics for the ready/busy
signal. The value required for the resistor R can be calculated using the following equation:
P
(
–
)
V
V
DDmax
OLmax
R min= -------------------------------------------------------------
P
+ I
I
L
OL
This is an example for 3 V devices:
3.2V
R min= ---------------------------
P
+
8mA
I
L
where I is the sum of the input currents of all the devices tied to the ready/busy signal. R
L
P
max is determined by the maximum value of t .
r
Figure 40. Ready/busy AC waveform
ready V
DD
V
OH
V
OL
busy
t
t
f
r
AI07564B
Figure 41. Ready/busy load circuit
ibusy
R
P
V
DD
DEVICE
RB
Open Drain Output
V
SS
AI07563B
63/69
DC and AC parameters
NAND02G-B2D
Figure 42. Resistor value versus waveform timings for ready/busy signal
V
= 3.3 V, C = 100 pF
V
= 1.8 V, C = 30 pF
L
DD
L
DD
400
300
200
4
3
2
400
300
4
3
2
400
300
2.4
200
1.7
200
1.2
120
1
90
100
0
1
100
30
0.8
3.6
0.85
100
3.6
0.57
0.6
3.6
0.43
1.7
60
1.7
3.6
1.7
0
1.7
1
2
3
4
1
2
3
4
R
(KΩ)
R
(KΩ)
P
P
t
f
t
r
ibusy
ai13640b
1. T = 25 °C.
11.2
Data protection
The Numonyx NAND devices are designed to guarantee data protection during power
transitions.
A V detection circuit disables all NAND operations, if V is below the V threshold.
LKO
DD
DD
In the V range from V
to the lower limit of nominal range, the WP pin should be kept
DD
LKO
low (V ) to guarantee hardware protection during power transitions as shown in the below
IL
figure.
Figure 43. Data protection
Nominal range
V
DD
V
LKO
Locked
Locked
W
Ai11086
64/69
NAND02G-B2D
Package mechanical
12
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second level interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 44. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
1. Drawing is not to scale.
Table 29. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.20
0.15
1.05
0.27
0.21
0.08
12.10
20.20
18.50
–
0.047
0.006
0.041
0.011
0.008
0.003
0.476
0.795
0.728
0.10
1.00
0.22
0.05
0.95
0.17
0.10
0.004
0.039
0.009
0.002
0.037
0.007
0.004
C
CP
D1
E
12.00
20.00
18.40
0.50
0.60
0.80
3°
11.90
19.80
18.30
–
0.472
0.787
0.724
0.020
0.024
0.031
3°
0.468
0.779
0.720
–
E1
e
L
0.50
0.70
0.020
0.028
5°
L1
a
0°
5°
0°
65/69
Package mechanical
NAND02G-B2D
Figure 45. VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline
D
D2
D1
FD1
SD
FD
e
e
SE
E
E2 E1
ddd
BALL "A1"
FE1
FE
e
b
A
A2
A1
BGA-Z67
1. Drawing is not to scale
Table 30. VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical
data
Millimeters
Inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
b
1.05
0.041
0.25
0.010
0.70
0.50
9.60
0.028
0.020
0.378
0.45
9.50
4.00
7.20
0.40
9.40
0.018
0.374
0.157
0.283
0.016
0.370
D
D1
D2
ddd
E
0.10
0.004
0.476
12.00
5.60
8.80
0.80
2.75
1.15
3.20
1.60
0.40
0.40
11.90
–
12.10
0.472
0.220
0.346
0.031
0.108
0.045
0.126
0.063
0.016
0.016
0.468
–
E1
E2
e
–
–
FD
FD1
FE
FE1
SD
SE
66/69
NAND02G-B2D
Ordering information
13
Ordering information
Table 31. Ordering information scheme
Example:
NAND02GW3B2D N
6
E
Device type
NAND flash memory
Density
02 G = 2 Gb
Operating voltage
W = VDD = 2.7 to 3.6 V
R = VDD = 1.7 to 1.95 V
Bus width
3 = x8
4 = x16(1)
Family identifier
B = 2112-byte page
Device options
2 = Chip Enable ‘don't care’ enabled
Product version
D = Fourth version
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA63 9.5 x 12 x 1 mm, 0.8 mm pitch
Temperature range
6 = –40 to 85 °C
Option
E = ECOPACK package, standard packing
F = ECOPACK package, tape and reel packing
1. x16 organization only available for MCP products.
Note:
Devices are shipped from the factory with the memory content bits, in valid blocks, erased to
’1’. For further information on any aspect of this device, please contact your nearest
Numonyx sales office.
67/69
Revision history
NAND02G-B2D
14
Revision history
Table 32. Document revision history
Date
Revision
Changes
07-Sep-2007
1
Initial release.
Document status promoted from target specification to
preliminary data.
Modified: Figure 12: Multiplane page program waveform,
Figure 16: Multiplane copy back program, Figure 18: Multiplane
block erase, Figure 30: Read status enhanced waveform,
Figure 37: Program/erase enable waveform, Figure 38:
Program/erase disable waveform, Figure 42: Resistor value
versus waveform timings for ready/busy signal, Section 6.4:
Multiplane page program, Section 8.5: Error correction code,
Table 8: Address definition (x 16 devices), Table 21: Program
erase times and program erase endurance cycles, Table 23:
Operating and AC measurement conditions.
13-Feb-2008
03-Apr-2008
2
3
Minor text changes.
Applied Numonyx branding.
68/69
NAND02G-B2D
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
69/69
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