NAND16GAH0PZA5F [NUMONYX]
Flash, 2GX8, PBGA169, 12 X 16 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LFBGA-169;
| 型号： | NAND16GAH0PZA5F |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 2GX8, PBGA169, 12 X 16 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LFBGA-169 内存集成电路 |
| 文件： | 总32页 (文件大小：697K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND16GAH0P
NAND32GAH0P NAND64GAH0P
2-Gbyte, 4-Gbyte, 8-Gbyte, 1.8 V/3.3 V supply,
NAND flash memories with MultiMediaCard™ interface
Preliminary Data
Features
■ Packaged NAND flash memory with
MultiMediaCard interface
■ 2, 4 and 8 Gbytes of formatted data storage
LFBGA169
■ eMMC/MultiMediaCard system specification,
compliant with V4.3
■ Full backward compatibility with previous
MultiMediaCard system specification
■ Bus mode
LFBGA169 12 x 16 x 1.4 mm (ZA)
– High-speed MultiMediaCard protocol
– Three different data bus widths:1 bit, 4 bits,
8 bits
■ Error free memory access
– Data transfer rate: up to 52 Mbyte/s
– Internal error correction code
■ Operating voltage range:
– Internal enhanced data management
algorithm (wear levelling, bad block
management, garbage collection)
– V
=1.8 V/3.3 V
CCQ
– V = 3.3 V
CC
■ Multiple block read (x8 at 52 MHz):
– Possibility for the host to make sudden
power failure safe-update operations for
data content
up to 29 Mbyte/s
■ Multiple block write (x8 at 52 MHz):
up to 19 Mbyte/s
■ Security
■ Power dissipation
– Secure erase, secure trim and secure bad
block erase commands
– Standby current: down to 100 µA (typ)
– Read current: down to 70 mA (typ)
– Write current: down to 100 mA (typ)
– Disable protection modes (lock/unlock by
password and device’s permanent write
protection)
■ Trim for data management optimization
■ Simple boot sequence method
– Password protection of data
– Built-in write protection
■ Enhanced power saving method by introducing
sleep functionality
Table 1.
Device summary
Root part number
Density
Package
Operating voltage
NAND16GAH0P
NAND32GAH0P
NAND64GAH0P
2 Gbytes
4 Gbytes
8 Gbytes
LFBGA169
VCC = 3.3 V, VCCQ = 1.8 V/3.3 V
September 2009
Rev 3
1/32
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.numonyx.com
1
Contents
NANDxxGAH0P
Contents
1
2
3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
eMMC Standard Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
System performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Device physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
3.2
Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
5
Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MultiMediaCard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Command (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input/outputs (DAT0-DAT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
V
V
V
core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CC
SS
input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CCQ
SSQ
5.2
5.3
5.4
5.5
5.6
5.7
Bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6
High speed MultiMediaCard operation . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
6.2
6.3
6.4
Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write protect management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Secure erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Secure trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/32
NANDxxGAH0P
Contents
6.5
6.6
6.7
6.8
6.9
Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Secure Bad Block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.10 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.11 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.12 State transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.13 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.14 Timing diagrams and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.15 Minimum performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7
Device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Operation conditions register (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Card specific data register (CSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Extended CSD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RCA (relative card address) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DSR (driver stage register) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
10
3/32
List of tables
NANDxxGAH0P
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Communication channel performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OCR register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Card specific data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended CSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, mechanical data . . . . . . . . . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4/32
NANDxxGAH0P
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LFBGA169 package connections (top view through package). . . . . . . . . . . . . . . . . . . . . . 10
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory array structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline . . . . . . . . . . . 28
5/32
Description
NANDxxGAH0P
1
Description
The NANDxxGAH0P is an embedded flash memory storage solution with MultiMediaCard™
interface (eMMC™). The eMMC™ was developed for universal low-cost data storage and
communication media. The NANDxxGAH0P is fully compatible with MMC bus and hosts.
The NANDxxGAH0P communications are made through an advanced 13-pin bus. The bus
can be either 1-bit, 4-bit, or 8-bit in width. The device operates in high-speed mode at clock
frequencies equal to or higher than 20 MHz, which is the MMC standard. The
communication protocol is defined as a part of this MMC standard and referred to as
MultiMediaCard mode.
The device is designed to cover a wide area of applications such as smart phones,
cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They
feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications,
the NANDxxGAH0P supports both 3.3 V supply voltage (V ), and 1.8 V/3.3 V input/output
CC
voltage (V
).
CCQ
The address argument for the NAND16GAH0P is the byte address, while the address
argument for the NAND32GAH0P and NAND64GAH0P is the sector address (512-byte
sectors). This means that the NAND32GAH0P and NAND64GAH0P are not backward
compatible with devices of density lower than 2 Gbytes. If the host does not indicate its
capability of handling sector type of addressing to the memory, the NAND32GAH0P and
NAND64GAH0P change their state to inactive.
The device has a built-in intelligent controller which manages interface protocols, data
storage and retrieval, wear leveling, bad block management, garbage collection, and
internal ECC.
The NANDxxGAH0P makes available to the host sudden power failure safe-update
operations for the data content, by supporting reliable write features.
The device supports boot operation and sleep/awake commands. In particular, during the
sleep state the host power regulator for V can be switched off, thus minimizing the power
CC
consumption of the NANDxxGAH0P.
The password protection feature can be disabled permanently by setting the permanent
password disable bit in the extended CSD (PERM_PSWD_DIS bit in the EXT_CSD byte
[171], see Section 7.4: Extended CSD register). It is recommended to disable the password
protection feature on the card, if it is not required. In this way the protection feature can not
be set unintentionally or maliciously.
In addition to the standard Erase command, the NANDxxGAH0P devices feature optional
Secure Erase command, trim operation, and secure trim operation.
The Secure Erase command allows the applications with tight security constraints, to
request that the device performs secure operations even though a negative impact on the
erase time performance is possible.
The trim operation is similar to the standard erase operation, but it applies to write blocks
instead of erase groups. The secure trim operation is similar to the secure erase operation,
but it performs a secure purge operation on write blocks instead of erase groups.
The system performance and characteristics are given in Table 2, Table 3, and Table 4.
6/32
NANDxxGAH0P
Description
1.1
eMMC Standard Specification
The NANDxxGAH0P device is fully compatible with the JEDEC Standard Specification No.
JESD84-A43.
This datasheet describes the key and specific features of the NANDxxGAH0P device. Any
additional information required to interface the device to a host system and all the practical
methods for card detection and access can be found in the proper sections of the JEDEC
Standard Specification.
7/32
Product specification
NANDxxGAH0P
2
Product specification
2.1
System performance
Table 2.
System performance
Typical value(1)
NAND16GAH0P NAND32GAH0P NAND64GAH0P
System performance
Unit
Multiple block read sequential
Multiple block write sequential
15
29
29
Mbyte/s
Mbyte/s
8.5
19.3
19.3
1. Values given for an 8-bit bus width, a clock frequency of 52 MHz, VCC = 3.3 V and VCCQ = 3.3 V.
Table 3.
Current consumption
Test conditions
Current consumption(1)
NAND32GAH0P
Operation
Unit
NAND16GAH0P
NAND64GAH0P
Typ
60
Max
70
Typ
65
Max
70
Typ
65
Max
70
Read
Write
V
CC= 3.3 V ± 5%
mA
µA
VCCQ = 1.8 V ± 5%
68
80
80
90
80
90
VCC = 3.3 V ± 5%
30
50
50
80
70
135
230
Standby
VCCQ = 1.8 V ± 5%
40
170
40
230
40
1. Values given for an 8-bit bus width and a clock frequency of 52 MHz.
Table 4.
Communication channel performance
MultiMediaCard communication channel performance
Three-wire serial data bus (clock, command, data)
Variable clock rate 0, 26, 52 MHz
Easy card identification
Error protected data transfer
Sequential and single/multiple block oriented data transfer
8/32
NANDxxGAH0P
Device physical description
3
Device physical description
The NANDxxGAH0P contains a single chip controller and flash memory module, see
Figure 1: Device block diagram. The microcontroller interfaces with a host system allowing
data to be written to and read from the flash memory module. The controller allows the host
to be independent from details of erasing and programming the flash memory.
Figure 2 shows the package connections. See Table 5: Signal names for the description of
the signals corresponding to the balls.
Figure 1.
Device block diagram
Data
I/O
Numonyx
single chip
microcontroller
MultiMediaCard
interface
Flash
module
Control
AI13614e
9/32
Device physical description
NANDxxGAH0P
3.1
Package connections
Figure 2.
LFBGA169 package connections (top view through package)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
V
NC
SS
CC
V
CC
NC
NC
NC
NC
NC
NC
NC
8
7
NC
NC
NC
NC
V
NC
NC
SS
V
NC
SS
NC
V
NC
V
NC
NC
6
5
4
3
NC
DAT7
V
NC
NC
CLK
CC
SSQ
CCQ
NC
DAT6
NC
V
CMD
V
SSQ
DAT2
DAT1
V
NC
NC
V
CC
SS
CCQ
NC
V
V
NC
DAT5
V
V
CCQ
NC
SSQ
SSQ
NC
CCQ
NC
DAT4
NC
NC
NC
DAT0
NC
NC
NC
NC
NC
NC
NC
V
CCQ
NC
NC
V
NC
NC
NC
V
SSQ
2
1
DAT3
NC
NC
M
NC
NC
NC
NC
NC
CCI
NC
H
NC
N
NC
Y
NC
NC
D
NC
J
NC
K
NC
L
NC
P
NC
R
NC
T
NC
U
NC
V
NC
W
NC
AA
A
B
C
E
F
G
AB
AC
AD
AE
AF
AG
AH
AI13626
1. The ball corresponding to VCCI must be decoupled with an external capacitance.
3.2
Form factor
The ball diameter, d, and the ball pitch, p, for the LFBGA169 package are:
■
■
d = 0.30 mm (solder ball diameter)
p = 0.5 mm (ball pitch)
Figure 3.
Form factor
NC
NC
V
NC
CCQ
d
p
AI13627
10/32
NANDxxGAH0P
Memory array partitioning
4
Memory array partitioning
The basic unit of data transfer to/from the device is one byte. All data transfer
operations which require a block size always define block lengths as integer
multiples of bytes. Some special functions need other partition granularity.
For block oriented commands, the following definitions are used:
■
Block: the unit which is related to the block oriented read and write commands.
Its size is the number of bytes which are transferred when one block command
is issued by the host. The size of a block is either programmable or fixed. The
information about allowed block sizes and the programmability is stored in the
CSD register.
■
■
Erase group: the unit which is related to special erase and write commands
defined for R/W cards. Its size is the smallest number of consecutive write
blocks which can be addressed for erase. The size of the erase group depends
on each device and is stored in the CSD.
Write protect group: the smallest unit that may be individually write protected.
Its size is defined in units of erase groups. The size of a WP-group depends on
each device and is stored in the CSD.
Figure 4 shows the NANDxxGAH0P memory array organization.
Figure 4.
Memory array structure
Write protect group 0
Erase group 0
Block 0
Erase group 1
Erase group n
Write protect group 1
Write protect group 2
Write protect group n
MultiMediaCard
AI13615e
1. n = number of last erase group or last write protect group.
11/32
MultiMediaCard interface
NANDxxGAH0P
5
MultiMediaCard interface
The signal/pin assignments are listed in Table 5. Refer to this table in conjunction with
Figure 2 and Figure 3: Form factor.
5.1
Signals description
5.1.1
Clock (CLK)
The Clock input, CLK, is used to synchronize the memory to the host during command and
data transfers. Each clock cycle gates one bit on the command and on all the data lines. The
Clock frequency, f , may vary between zero and the maximum clock frequency.
PP
5.1.2
5.1.3
Command (CMD)
The CMD signal is a bidirectional command channel used for device initialization and
command transfer. The CMD signal has two operating modes: open-drain and push-pull.
The open-drain mode is used for initialization, while the push-pull mode is used for fast
command transfer. Commands are sent by the MultiMediaCard bus master (or host) to the
device who responds by sending back responses.
Input/outputs (DAT0-DAT7)
DAT0 to DAT7 are bidirectional data channels. The signals operate in push-pull mode. The
NANDxxGAH0P includes internal pull ups for all data lines. These signals cannot be driven
simultaneously by the host and the NANDxxGAH0P device. Right after entering the 4-bit
mode, the card disconnects the internal pull ups of lines DAT1 and DAT2. Correspondingly
right after entering the 8-bit mode, the card disconnects the internal pull ups of lines DAT1,
DAT2 and DAT4-DAT7.
By default, after power-up or hardware reset, only DAT0 is used for data transfers. The host
can configure the device to use a wider data bus, DAT0, DAT0-DAT3 or DAT0-DAT7, for data
transfer.
5.1.4
5.1.5
V
core supply voltage
CC
V
provides the power supply to the internal core of the memory device. It is the main
CC
power supply for all operations (read, program and erase). The core voltage (V ) can be
within 2.7 V and 3.6 V.
CC
V
ground
SS
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
12/32
NANDxxGAH0P
MultiMediaCard interface
5.1.6
V
input/output supply voltage
CCQ
V
provides the power supply to the I/O pins and enables all outputs to be powered
CCQ
independently from V
.
CC
The input/output voltage (V
) can be either within 1.65/1.7 V and 1.95 V (low voltage
CCQ
range) or 2.7 V and 3.6 V (high voltage range).
5.1.7
V
supply voltage
SSQ
V
ground is the reference for the input/output circuitry driven by V
.
CCQ
SSQ
Table 5.
Name
Signal names
Type(1)
Description
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (PP)
I/O (OD or PP)
I (PP)
Data
Data
Data
Data
Data
Data
Data
Data
Command
Clock
VCCQ
VCC
Input/output power supply
Core power supply
VSSQ
VCCI
VSS
Input/output ground
I
Must be decoupled with an external capacitance
Ground
NC
NC
Not connected(2)
1. I: input; O: output, OD: open drain, PP: push-pull.
2. NC pins can be connected to ground or left floating.
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MultiMediaCard interface
NANDxxGAH0P
5.2
Bus topology
The NANDxxGAH0P device supports the MMC protocol. For more details, refer to section
6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC
Standard Specification contains a bus circuitry diagram for reference.
5.3
Power-up
The power-up is handled locally in each device and in the bus master. Figure 5: Power-up
shows the power-up sequence. Refer to section 12.3 of the JEDEC Standard Specification
No. JESD84-A43 for specific instructions regarding the power-up sequence.
After power-up, the maximum initial load the NANDxxGAH0P can present on the V line is
CC
C4, in parallel with a minimum of R4. During operation, device capacitance on the V line
CC
must not exceed 10 µF.
5.4
Power cycling
The bus master can execute any sequences of V and V
power-up/power down.
CCQ
CC
However, the master must not issue any commands until V and V
are stable within
CC
CCQ
each operating voltage range. For more information about power cycling see Section 12.3.3
of the JEDEC Standard Specification No. JESD84-A43 and Figure 6: Power cycling.
14/32
NANDxxGAH0P
MultiMediaCard interface
Figure 5.
Power-up
Supply
voltage
(3)
V
CCmax
Memory
field
working
voltage
range
(3)
V
CC
(3)
V
CCmin
(3)
V
CCQmax
Control logic
working
voltage range
(3)
V
CCQmin
Time
Power-up
Supply
(2)
First CMD1 to card ready
ramp-up
N
N
CC
CC
Initialization
sequence
CMD2
CMD1
CMD1
CMD1
(1)
CMD1 repeated
until busy flag cleared
Initialization
delay
The longest of: 1 ms,
74 clock cycles,
supply ramp-up time,
or the boot operation period.
AI14104b
1. The initialization sequence is a contiguous stream of logic 1’s. Its length is either 1 ms, 74 clocks or the supply ramp up
time, whichever is the longest. The device shall complete its initialization within 1 second from the first CMD1 with a valid V
range.
2. NCC is the number of clock cycles.
3. Refer to Section 7.1: Operation conditions register (OCR) for details on voltage ranges.
Figure 6.
Power cycling
Supply
voltage
V
CC
V
CCmin
V
CCQ
V
CCQmin
Command input prohibited
Command input prohibited
Sleep mode
Time
AI14122b
15/32
MultiMediaCard interface
NANDxxGAH0P
5.5
5.6
5.7
Bus operating conditions
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
Bus signal levels
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
Bus timing
Refer to section 12.7 of the JEDEC Standard Specification No. JESD84-A43.
16/32
NANDxxGAH0P
High speed MultiMediaCard operation
6
High speed MultiMediaCard operation
All communication between the host and the device is controlled by the host (master).
The following section provides an overview of the identification and data transfer modes,
commands, dependencies, various operation modes and restrictions for controlling the clock
signal. For detailed information, refer to section 7 of the JEDEC Standard Specification No.
JESD84-A43.
6.1
6.2
Boot mode
The host can read boot data from NANDxxGAH0P by keeping CMD line Low after power-on
or sending CMD0 with argument + 0xFFFFFFFA (optional for slave), before issuing CMD1.
The data can be read from either boot area or user area depending on the register setting.
Refer to section 7.2 of the JEDEC Standard Specification No. JESD84-A43.
Write protect management
To allow the host to protect data against erase or write operations, the NANDxxGAH0P
supports two levels of write protect commands:
■
The whole NANDxxGAH0P is write-protected by setting the permanent or temporary
write protect bits in the CSD register.
■
Specific segments of the NANDxxGAH0P are write-protected. ERASE_GROUP_DEF
in EXT_CSD defines the segment size.
When set to ‘0’, the segment size is defined in units of WP_GRP_SIZE erase groups as
specified in the CSD register.
When set to ‘1’, the segment size is defined in units of HC_WP_GRP_SIZE erase
groups as specified in the EXT_CSD.
The SET_WRITE_PROT command sets the write protection of the addressed write protect
group, and the CLR_WRITE_PROT command clears the write protection of the addressed
write protect group. The SEND_WRITE_PROT command is similar to a single block read
command.
The card sends a data block containing 32 write protection bits (representing 32 write
protect groups starting at the specified address) followed by 16 CRC bits. The address field
in the write protect commands is a group address in byte units, for NAND16GAH0P, and in
sector units for NAND32GAH0P and NAND64GAH0P. Both permanent and temporary write
protection applies not only to user data area but also to boot partitions.
6.3
Secure erase
In addition to the standard Erase command the NANDxxGAH0P devices feature also an
optional Secure Erase command. The Secure Erase command differs from the standard
Erase command since it requires the card to execute the erase operation on the memory
array when the command is issued and requires the card and host to wait until the operation
is complete before moving to the next card operation. Also, the secure erase command
requires the card to do a secure purge operation on the erase groups, and that any copies of
items in those erase groups must be identified for erase.
17/32
High speed MultiMediaCard operation
NANDxxGAH0P
The Secure Erase command is executed in the same way as the erase command outlined in
section 7.5.8 of JEDEC Standard Specification No. JESD84-A43, except that the Erase
command (CMD38) is executed with argument bit 31 set to ‘1’ and the other argument bits
set to ‘0’.
The host has to excute the Secure Erase command with caution to avoid unintentional data
loss. A card resetting (using CMD0, CMD15) or a power failure terminates any pending or
active Secure Erase command. This may leave the data involved in the operation in an
unknown state.
6.4
Secure trim
The Secure Trim command is very similar to the Secure Erase command. The Secure Trim
command performs a secure purge operation on write blocks instead of erase groups. To
minimize the impact on the card's performance and reliability, the secure trim operation is
completed by executing two distinct steps:
■
In the Secure Trim step 1 the host defines the range of write blocks to be marked for the
secure purge operation. This step does not perform the actual purge operation. The
blocks are marked by defining the start address of the range using the
ERASE_GROUP_START command (CMD35), followed by defining the last address of
the range using the ERASE_GROUP_END command (CMD36). In the case of Secure
Trim, both the ERASE_GROUP_START and ERASE_GROUP_END arguments
identify write block addresses. Once the range of blocks has been identified, the
ERASE (CMD 38) with argument bit 31and 0 set to ‘1’ and the remainder of the
argument bits set to ‘0’ is applied. This completes the step 1, which can be repeated
several times, with other commands being allowed in between, until all the write blocks
that need to be purged have been identified. It is recommended that the Secure Trim
Step 1 is done on as many blocks as possible to improve the efficiency of the secure
trim operation.
■
The Secure Trim step 2 issues the ERASE_GROUP_START (CMD35) and
ERASE_GROUP_END (CMD36) with addresses that are in range. Note that the
arguments used with these commands are ignored. Then the ERASE (CMD 38), with
bit 31 and 15 set to ‘1’ and the remainder of the argument bits set to ‘0’, is sent. This
step actually performs the secure purge on all the write blocks, as well as any copies of
those blocks, that were marked during Secure Trim Step 1 and completes the secure
trim operation.
Once a write block is marked for erase using Secure Trim Step 1, it is recommended that the
host consider this block as erased. However, if the host does write to a block after it has
been marked for erase, then the last copy of the block, which occurred as a result of the
modification, will not be marked for erase. All previous copies of the block will remain
marked for erase.
6.5
Trim
The trim operation is similar to the standard erase operation described in section 7.5.8 of
JEDEC Standard Specification No. JESD84-A43. The trim function applies the erase
operation to write blocks instead of erase groups. The trim function allows the host to
identify data that is no longer required so that the card can erase the data, if necessary,
during background erase events. The contents of a write block where the trim function has
18/32
NANDxxGAH0P
High speed MultiMediaCard operation
been applied is '0' or '1' depending on the memory technology. This value is defined in the
EXT_CSD.
The trim process consists of a three-steps sequence:
■
■
■
First the host defines the start address of the range using the ERASE_GROUP_START
command (CMD35)
Next it defines the last address of the range using the ERASE_GROUP_END
command (CMD36)
Finally it starts the erase process by issuing the ERASE command (CMD38) with
argument bit 0 set to ‘1’ and the remainder of the arguments set to ‘0’.
In the case of a trim operation both CMD35 and CMD36 identify the addresses of write
blocks rather than erase groups.
If an element of the Trim command (either CMD35, CMD36, CMD38) is received out of the
defined erase sequence, the card sets the ERASE_SEQ_ERROR bit in the status register
and resets the whole sequence.
If the host provides an out-of-range address as an argument to CMD35 or CMD36, the card
rejects the command, responds with the ADDRESS_OUT_OF_RANGE bit set and resets
the whole erase sequence.
If a non erase command (neither of CMD35, CMD36, CMD38 or CMD13) is received, the
card responds with the ERASE_RESET bit set, resets the erase sequence and executes the
last command. Commands not addressed to the selected card do not abort the erase
sequence.
If the trim range includes write protected blocks, they shall be left intact and only the non
protected blocks shall be erased. The WP_ERASE_SKIP status bit in the status register
shall be set.
As described above for block write, the card indicates that a Trim command is in progress by
holding DAT0 Low. The actual erase time may be quite long, and the host may issue CMD7
to deselect the card.
The host must excute the Trim command with caution to avoid unintentional data loss.
A card reset or a power failure terminates any pending or active Trim command. This may
leave the data involved in the operation in an unknown state.
6.6
6.7
Secure Bad Block management
The memory array can become defective with use. The NANDxxGAH0P will recover the
information from the defective portion of the memory array before it retires the block. If the
register bit SEC_BAD_BLK_MGMNT [134] of the EXT_CSD is set, the NANDxxGAH0P
performs a secure purge on the contents of the defective region before it is retired. This
feature requires only those bits that are not defective in the region to be purged.
Identification mode
When in card identification mode, the host resets the NANDxxGAH0P, validates the
operating voltage range and the access mode, identifies the device and assigns a relative
address (RCA) to it. For more information see section 7.3 of the JEDEC Standard
Specification No. JESD84-A43.
19/32
High speed MultiMediaCard operation
NANDxxGAH0P
6.8
Data transfer mode
The device enters data transfer mode once an RCA is assigned to it. When the device is in
standby mode, issuing the CMD7 command along with the RCA, selects the device and puts
it into the transfer state. The host enters data transfer mode after identifying the
NANDxxGAH0P on the bus. When the device is in standby state, communication over the
CMD and DAT lines is in push-pull mode.
The section 7.5 of the JEDEC Standard Specification No. JESD84-A43 contains more
detailed information about data read and write, erase, write protect management,
lock/unlock operations, the switch function command, high speed mode selection, and bus
testing procedure. Moreover section 7.5.7 contains a detailed description of the reliable
write features supported by the NANDxxGAH0P.
6.9
Clock control
Refer to section 7.6 of the JEDEC Standard Specification No. JESD84-A43.
6.10
6.11
6.12
6.13
6.14
6.15
Error conditions
Refer to section 7.7 of the JEDEC Standard Specification No. JESD84-A43.
Commands
Refer to section 7.9 of the JEDEC Standard Specification No. JESD84-A43.
State transition
Refer to section 7.10 and 7.12 of the JEDEC Standard Specification No. JESD84-A43.
Response
Refer to section 7.11 of the JEDEC Standard Specification No. JESD84-A43.
Timing diagrams and values
Refer to section 7.14 of the JEDEC Standard Specification No. JESD84-A43.
Minimum performance
Refer to section 7.8 of the JEDEC Standard Specification No. JESD84-A43.
20/32
NANDxxGAH0P
Device registers
7
Device registers
There are five different registers within the device interface:
■
■
■
■
■
■
Operation conditions register (OCR)
Card identification register (CID)
Card specific data register (CSD)
Relative card address register (RCA)
DSR (driver stage register)
Extended card specific data register (EXT_CSD).
These registers are used for the serial data communication and can be accessed only using
the corresponding commands (refer to section 7.9 of the JEDEC Standard Specification No.
JESD84-A43. The device does not implement the DSR register.
The NANDxxGAH0P has a status register to provide information about the device current
state and completion codes for the last host command.
7.1
Operation conditions register (OCR)
The 32-bit operation conditions register stores the V
, the input/output voltage of the
CCQ
flash memory component. The device is capable of communicating (identification procedure
and data transfer) with any MultiMediaCard host using any operating voltage within 1.7 V
and 1.95 V (low-voltage range) or 2.7 V and 3.6 V (high-voltage range) depending on the
voltage range supported by the host. For further details, refer to section 8.1 of the JEDEC
Standard Specification No. JESD84-A43.
If the host tries to change the OCR values during an initialization procedure the changes in
the OCR content will be ignored.
The level coding of the OCR register is as follows:
■
■
Restricted voltage windows = Low
Device busy = Low
Table 6.
OCR register definition
OCR bit
Description
MultiMediaCard
6 to 0
7
Reserved
Low VCCQ
000 0000b
1b
000 0000b
14 to 8
23 to 15
28 to 24
2.0 - 2.6
2.7 - 3.6 (High VCCQ range)
Reserved
1 1111 1111b
000 0000b
00b (byte mode for 2-Gbyte devices)
30 to 29
31
Access mode
01b (sector mode for 4- and 8-Gbyte
devices)
Power-up status bit (busy)(1)
1. This bit is set to Low if the device has not finished the power-up routine.
21/32
Device registers
NANDxxGAH0P
7.2
Card identification (CID) register
The CID register is 16-byte long and contains a unique card identification number used
during the card identification procedure. It is a 128-bit wide register with the content as
defined in Table 7. It is programmed during device manufacturing and can not be changed
by MultiMediaCard hosts. For details, refer to section 8.2 of the JEDEC Standard
Specification No. JESD84-A43.
Table 7.
Card identification (CID) register
Name
Field
Width
CID - slice
CID - value
Note
Manufacturer ID
Reserved
MID
8
6
2
8
[127:120]
[119:114]
[113:112]
[111:104]
0xFE
Card/BGA
CBX
OID
0x01
0x4E
BGA
OEM/application ID
MMC02, MMC04,
MMC08
Product name
PNM
48
[103:56]
Product revision
PRV
PSN
MDT
CRC
–
8
32
8
[55:48]
[47:16]
[15:8]
[7:1]
TBD
TBD
TBD
TBD
1
Product serial number
Manufacturing date
CRC7 checksum
7
Not used, always ‘1’
1
[0:0]
7.3
Card specific data register (CSD)
All the configuration information required to access the device data is stored in the CSD
register. The MSB bytes of the register contain the manufacturer data and the two least
significant bytes contains the host controlled data (the device copy, write protection and the
user ECC register).
The host can read the CSD register and alter the host controlled data bytes using the
SEND_CSD and PROGRAM_CSD commands.
In Table 8, the cell type column defines the CSD field as read only (R), one time
programmable (R/W) or erasable (R/W/E). The programmable part of the register (entries
marked by W or E) can be changed by command CMD27.
The copy bit in the CSD can be used to mark the device as an original or a copy. Once set it
cannot be cleared. The device can be purchased with the copy bit set (copy) or cleared,
indicating the device is a master.
The one time programmable (OTP) characteristic of the copy bit is implemented in the
MultiMediaCard controller firmware and not with a physical OTP cell.
For details, refer to section 8.3 of the JEDEC Standard Specification No. JESD84-A43.
22/32
NANDxxGAH0P
Device registers
CSD-value
Table 8.
Card specific data register
Width Cell
[bits] type
Name
Field
CSD-slice
CSD structure
CSD_STRUCTURE
SPEC_VERS
2
4
R
R
[127:126]
[125:122]
0x02
0x04
MultiMediaCard protocol
version
Reserved
2
8
R
R
[121:120]
[119:112]
TBD
Data read access-time-1
TAAC
NSAC
0x4F
Data read access-time-2 in
CLK cycles (NSAC*100)
8
R
[111:104]
0x01
Max. data transfer rate
Command classes
TRAN_SPEED
CCC
8
R
R
[103:96]
[95:84]
0x32
0xF5
12
10 for 2-Gbyte devices
9 for 4- and 8-Gbyte
devices
Max. read data block length
READ_BL_LEN
4
R
[83:80]
Partial blocks for read allowed READ_BL_PARTIAL
1
1
1
1
2
R
R
R
R
R
[79:79]
[78:78]
[77:77]
[76:76]
[75:74]
0x01
0x00
0x00
0x00
TBD
Write block misalignment
Read block misalignment
DSR implemented
Reserved
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
1976320 blocks for 2-
Gbyte devices
Device size
C_SIZE
12
R
[73:62]
Refer to the extended
CSD for 4- and 8-Gbyte
devices
Max. read current at VCC(min) VDD_R_CURR_MIN
Max. read current at VCC(max) VDD_R_CURR_MAX
Max. write current at VCC(min) VDD_W_CURR_MIN
Max. write current at VCC(max) VDD_W_CURR_MAX
3
3
3
3
3
5
5
5
1
2
3
R
R
R
R
R
R
R
R
R
R
R
[61:59]
[58:56]
[55:53]
[52:50]
[49:47]
[46:42]
[41:37]
[36:32]
[31:31]
[30:29]
[28:26]
0x07
0x07
0x07
0x07
0x07
0x1F
0x1F
0x0F
0x01
TBD
0x02
Device size multiplier
Erase group size
C_SIZE_MULT
ERASE_GRP_SIZE
ERASE_GRP_MULT
WP_GRP_SIZE
WP_GRP_ENABLE
DEFAULT_ECC
Erase group size multiplier
Write protect group size
Write protect group enable
Manufacturer default ECC
Write speed factor
R2W_FACTOR
10 for 2-Gbyte devices
9 for 4- and 8-Gbyte
devices
Max. write data block length
WRITE_BL_LEN
4
1
R
R
[25:22]
[21:21]
Partial blocks for write allowed WRITE_BL_PARTIAL
0x00
23/32
Device registers
NANDxxGAH0P
CSD-value
Table 8.
Card specific data register (continued)
Width Cell
[bits] type
Name
Field
CSD-slice
Reserved
[20:20]
[16:16]
[15:15]
[14:14]
TBD
0x00
0x00
0x00
Content protection application CONTENT_PROT_APP
1
1
1
R
File format group
Copy flag (OTP)
FILE_FORMAT_GROUP
COPY
R/W
R/W
PERM_WRITE_PROTE
CT
Permanent write protection
Temporary write protection
File format
1
1
2
2
R/W
[13:13]
[12:12]
[11:10]
[9:8]
0x00
0x00
R/W/
E
TMP_WRITE_PROTECT
Hard disk like file system
with partition table
FILE_FORMAT
ECC
R/W
R/W/
E
ECC code 2 R/W/E none 0
0x00
R/W/
E
CRC
CRC
7
1
[7:1]
[0:0]
TBD
TBD
Not used, always ‘1’
–
7.4
Extended CSD register
The extended CSD register defines the device properties and selected modes. It is 512-byte
long. The 320 most significant bytes are the properties segment that defines the device
capabilities and cannot be modified by the host. The 192 lower bytes are the modes
segment that defines the configuration the device is working in. For details, refer to section
8.4 of the JEDEC Standard Specification No. JESD84-A43.
These modes can be changed by the host by means of the Switch command.
(1)(2)
Table 9.
Extended CSD
Size
(bytes)
Name
Field
Cell type CSD-slice CSD-slice value
Properties segment
Reserved(3)
7
1
[511:505]
[504]
TBD
0x01
TBD
0x03
0x15
0x01
0x01
0x01
TBD
0x02
Supported command sets
Reserved(3)
S_CMD_SET
R
TBD
R
272
1
[503:233]
[232]
TRIM multiplier
TRIM_MULT
Secure feature support
Secure erase multiple
Secure trim multiple
Boot information
Reserved(3)
SEC_FEATURE_SUPPORT
SEC_ERASE_MULT
SEC_TRIM_MULT
BOOT_INFO
1
R
[231]
1
R
[230]
1
R
[229]
1
R
[228]
1
TBD
R
[227]
Boot partition size
BOOT_SIZE_MULTI
1
[226]
24/32
NANDxxGAH0P
Device registers
(1)(2)
Table 9.
Extended CSD
(continued)
Field
Size
(bytes)
Name
Cell type CSD-slice CSD-slice value
Access size
ACC_SIZE
1
1
R
R
[225]
[224]
0x00
0x00
High-capacity erase unit
size
HC_ERASE_GRP_SIZE
High-capacity erase timeout ERASE_TIMEOUT_MULT
Reliable write sector count REL_WR_SEC_C
1
1
R
R
[223]
[222]
0x03
0x01
High-capacity write protect
HC_WP_GRP_SIZE
group size
1
R
[221]
0x00
Sleep current (VCC
)
S_C_VCC
1
1
1
1
1
R
R
[220]
[219]
[218]
[217]
[216]
0x04
0x08
TBD
0x0B
TBD
Sleep current (VCCQ
Reserved(3)
)
S_C_VCCQ
TBD
R
Sleep/awake timeout
Reserved(3)
S_A_TIMEOUT
SEC_COUNT
TBD
0x0040F100 for
8-Gbyte devices
0x00A07800 for
4-Gbyte devices
Sector count
Reserved(3)
4
R
[215:212]
1
1
[211]
[210]
TBD
0x08
Minimum write performance
for 8 bit at 52 MHz
MIN_PERF_W_8_52
MIN_PERF_R_8_52
R
R
Minimum read performance
for 8 bit at 52 MHz
1
1
[209]
[208]
0x08
0x08
Minimum write performance
for 8 bit at 26 MHz, for 4 bit MIN_PERF_W_8_26_4_52
at 52 MHz
R
R
Minimum read performance
for 8 bit at 26 MHz, for 4 bit MIN_PERF_R_8_26_4_52
at 52 MHz
1
1
[207]
[206]
0x08
0x08
Minimum write performance
MIN_PERF_W_4_26
for 4 bit at 26 MHz
R
R
Minimum read performance
MIN_PERF_R_4_26
for 4 bit at 26 MHz
1
1
1
[205]
[204]
[203]
0x08
TBD
0x00
Reserved(3)
Power class for 26 MHz at
PWR_CL_26_360
3.6 V
R
R
R
R
Power class for 52 MHz at
PWR_CL_52_360
3.6 V
1
1
1
[202]
[201]
[200]
0x00
0x00
0x00
Power class for 26 MHz at
PWR_CL_26_195
1.95 V
Power class for 52 MHz at
PWR_CL_52_195
1.95 V
Reserved(3)
3
1
[199:197]
[196]
TBD
0x03
Card type
CARD_TYPE
R
25/32
Device registers
NANDxxGAH0P
(1)(2)
Table 9.
Extended CSD
(continued)
Field
Size
(bytes)
Name
Cell type CSD-slice CSD-slice value
Reserved(3)
1
1
1
1
[195]
[194]
[193]
[192]
TBD
0x02
TBD
0x03
CSD structure version
Reserved(3)
CSD_STRUCTURE
EXT_CSD_REV
CMD_SET
R
Extended CSD revision
Modes segment
Command set
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
RO
[191]
[190]
[189]
[188]
[187]
[186]
[185]
[184]
[183]
[182]
[181]
[180]
[179]
[178]
[177]
[176]
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
0x00
TBD
Reserved(3)
Command set revision
Reserved(3)
CMD_SET_REV
POWER_CLASS
Power class
R/W
R/W
WO
RO
Reserved(3)
High speed interface timing HS_TIMING
Reserved(3)
Bus width mode
Reserved(3)
BUS_WIDTH
Erased memory content
Reserved(3)
ERASED_MEM_CONT
BOOT_CONFIG
Boot configuration
Reserved(3)
R/W
R/W
Boot bus width 1
Reserved(3)
BOOT_BUS_WIDTH
High-density erase group
definition
ERASE_GROUP_DEF
USER_WP
1
3
R/W
TBD
[175]
0x00
TBD
Reserved(3)
[174:172]
R/W,
R/W/C_P
,
User Write Protect
Reserved(3)
1
[171]
0x00
R/W/E_P
37
1
TBD
R/W
TBD
[174:134]
[134]
TBD
0x00
TBD
Secure bad block
management
SEC_BAD_BLK_MGMNT
Reserved(3)
133
[132:0]
1. TBD stands for ‘to be defined’.
2. CSD-slices are added to manage secure erase and secure trim functionalities which are not available in JEDEC Standard
Specification No. JESD84-A43.
3. Reserved bits should read as ‘0’.
26/32
NANDxxGAH0P
Device registers
7.5
RCA (relative card address) register
The writable 16-bit relative card address (RCA) register carries the device address assigned
by the host during the device identification. This address is used for the addressed host-card
communication after the device identification procedure. The default value of the RCA
register is ‘0x0001’. The value ‘0x0000’ is reserved to set all cards into the standby state
with CMD7. For details refer to section 8.5 of the JEDEC Standard Specification No.
JESD84-A43.
7.6
DSR (driver stage register) register
The 16-bit driver stage register (DSR) can be optionally used to improve the bus
performance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of devices on the bus).
The CSD register contains the information concerning the DSR register usage.
The default value of the DSR register is ‘0x404’. For details refer to section 8.6 of the
JEDEC Standard Specification No. JESD84-A43.
7.7
Status register
The status register provides information about the device current state and completion
codes for the last host command. The device status can be explicitly read (polled) with the
SEND_STATUS command. The MultiMediaCard status register structure is defined in
section 7.12 of the JEDEC Standard Specification No. JESD84-A43.
27/32
Package mechanical
NANDxxGAH0P
8
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 7.
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline
D
D1
SD
b
e
SE
E
E4 E3 E2 E1
ddd
FE
FE1
FE2
FE3
FD
FD1
FD2
FD3
e
A
A2
A1
DB_ME
1. Drawing is not to scale.
28/32
NANDxxGAH0P
Package mechanical
inches
Table 10.
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, mechanical data
millimeters
Min
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.40
0.055
0.15
0.006
1.00
0.30
0.039
0.012
0.472
0.256
0.25
0.35
0.010
0.469
0.014
0.476
D
12.00
6.50
11.90
12.10
D1
ddd
E
0.08
0.003
0.634
16.00
6.50
10.50
12.50
13.50
0.50
2.75
3.25
4.25
5.25
4.75
2.75
1.75
1.25
0.25
0.25
15.90
16.10
0.630
0.256
0.413
0.492
0.531
0.020
0.108
0.128
0.167
0.207
0.187
0.108
0.069
0.049
0.010
0.010
0.626
E1
E2
E3
E4
e
–
–
–
–
FD
FD1
FD2
FD3
FE
FE1
FE2
FE3
SD
SE
–
–
–
–
–
–
–
–
29/32
Ordering information
NANDxxGAH0P
9
Ordering information
Table 11. Ordering information scheme
Example:
NAND64GAH
0
P
ZA
5
E
Device type
NAND flash memory
Density
16G = 2 Gbytes
32G = 4 Gbytes
64G = 8 Gbytes
Operating voltage
A = VCC = 3.3 V, VCCQ = 1.8 V or 3.3 V
Memory type
H = eMMC
Device options
0 = no option
Product version
P = version P
Package
ZA = LFBGA169 12 x 16 x 1.4 mm
Temperature range
5 = −25 to 85 °C
Packing
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape & reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available devices and for further information on any aspect of these products,
please contact your nearest Numonyx sales office.
30/32
NANDxxGAH0P
Revision history
10
Revision history
Table 12. Document revision history
Date
Revision
Changes
25-Mar-2009
1
Initial release.
Added 4-Gbyte density throughout the document.
11-Jun-2009
2
Modified Table 3: Current consumption and Table 9: Extended CSD.
Modified: Table 6: OCR register definition, CID-values in Table 7:
Card identification (CID) register, CSD-slice values in Table 8: Card
specific data register, and extended CSD-slice values in Table 9:
Extended CSD.
09-Sep-2009
3
31/32
NANDxxGAH0P
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
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