RD38F3362LLYBB0_技术文档

®

Numonyx™ StrataFlash Wireless Memory

(L18)

512-Mbit LX Family with LPSDRAM (x16)

Datasheet

Product Features

Device Architecture

Flash Performance

— Flash die density: 128- or 256-Mbit

— LPSDRAM die density: 128- or 256-Mbit

— Async SRAM die density: 8-Mbit

— 85 ns Asynchronous single-word read

— 25 ns Asynchronous four-word page read

— 14 ns Synchronous read (t_CHQV

)

— Top, Bottom or Dual flash parameter

configuration

Device Voltage

— 54 MHz CLK

— Buffered Enhanced Factory Programming: 5

µs/byte (typ.) per die

— Core: V_CC= 1.8 V (Typ)

— I/O: V_CCQ= 1.8 V (Typ)

Device Packaging

— Ball count: 103 Active balls

— Area: 9x11 mm

— Height: 1.2 mm to 1.4 mm

SDRAM Architecture and Performance

— Clock rate: 104 MHz

— Four internal banks

— Burst length: 1, 2, 4, 8 or full page

SRAM Performance

— 70 ns initial access at 1.8 V I/O

Quality and Reliability

— Buffered programming at 7 µs/byte (typ.)

per die

Flash Architecture

— Hardware Read-While-Write/Erase

— Asymmetrical blocking structure

— 8-Mbit or 16-Mbit partition size

— 16-KWord parameter blocks (Top or

Bottom); 64-KWord main blocks

— 2-Kbit One-Time Programmable (OTP)

Protection Register

— Zero-latency block locking

— Absolute write protection with block lock-

down using F-VPP and F-WP#

Flash Software

— Extended Temperature –25 °C to +85 °C

— Minimum 100K Flash Block Erase cycles

— 0.13 µm ETOX™ VIII Process

— Numonyx™ FDI, Numonyx™ PSM and

Numonyx™ VFM

— Common Flash Interface (CFI)

— Basic/Extended Command Set

317623-15

November 2007

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND

CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx

products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.

Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented

subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or

otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting

Numonyx's website at http://www.numonyx.com.

Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

2

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Contents

1.0 Introduction..............................................................................................................6

1.1

1.2

Nomenclature.....................................................................................................6

Conventions .......................................................................................................7

2.0 Functional Overview..................................................................................................8

3.0 Package Information.................................................................................................9

4.0 Ballout and Signal Descriptions ...............................................................................11

4.1

4.2

Device Electrical Ballout ..................................................................................... 11

Signal Descriptions............................................................................................ 12

5.0 Maximum Ratings and Operating Conditions............................................................ 15

5.1

5.2

Absolute Maximum Ratings.................................................................................15

Operating Conditions .........................................................................................15

6.0 Electrical Specifications........................................................................................... 16

6.1

6.2

Flash DC Characteristics..................................................................................... 16

SRAM and LPSDRAM DC Characteristics................................................................16

7.0 AC Characteristics ................................................................................................... 19

7.1

7.2

AC Test Conditions ............................................................................................ 19

Flash AC Characteristics..................................................................................... 19

7.2.1 Capacitance........................................................................................... 19

7.2.2 AC Read Specifications............................................................................ 19

7.2.3 Flash AC Write Specifications ................................................................... 19

7.2.4 Flash Program and Erase Characteristics.................................................... 19

SRAM and LPSDRAM AC Characteristics................................................................19

7.3.1 SRAM and LPSDRAM Capacitance ............................................................. 19

7.3.2 LPSDRAM AC Characteristics.................................................................... 20

7.3.3 SRAM AC Read Specifications................................................................... 21

7.3.4 SRAM AC Write Specifications ..................................................................22

7.3

8.0 Power and Reset Specifications...............................................................................25

8.1

8.2

Flash Power and Reset Specifications ................................................................... 25

LPSDRAM Power-up Sequence and Initialization..................................................... 25

9.0 Bus Operations Overview ........................................................................................26

9.1 Flash, LPSDRAM and SRAM Bus Operations...........................................................26

10.0 Flash OperationS ..................................................................................................... 32

11.0 LPSDRAM Register Definition................................................................................... 33

11.1 Mode Register................................................................................................... 33

11.2 LPSDRAM Extended Mode Register....................................................................... 34

12.0 LPSDRAM Commands and Operations...................................................................... 35

12.1 LPSDRAM No Operation / LPSDRAM Deselect.........................................................35

12.2 LPSDRAM Active................................................................................................35

12.3 LPSDRAM Read Command .................................................................................. 35

12.4 LPSDRAM Write Command.................................................................................. 36

12.5 LPSDRAM Power-Down.......................................................................................36

12.6 LPSDRAM Deep Power-Down...............................................................................36

12.7 LPSDRAM Clock Suspend.................................................................................... 37

12.8 LPSDRAM Precharge .......................................................................................... 37

12.9 LPSDRAM Auto Precharge................................................................................... 37

12.10 LPSDRAM Concurrent Auto Precharge................................................................... 37

November 2007

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Datasheet

3

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

12.11 LPSDRAM Burst Terminate ..................................................................................44

12.12 LPSDRAM Auto-Refresh ......................................................................................44

12.13 LPSDRAM Self-Refresh........................................................................................45

A

Ordering Information...............................................................................................45

Datasheet

4

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Revision History

Date

Revision

Description

July 19, 2003

-001

-002

-003

-004

Initial Release.

July 24, 2003

Editing changes.

September 5, 2003

November 17, 2003

Ordering information changes; edits.

Fixed Internet pdf presentation problem, and added tracking number.

Added the following:

Line items, new package information (High Performance DRAM Ballout), Flash + SRAM Bus

Operations, SRAM DC and AC specifications.

November 20, 2003

-005

Made the following edits: Various text edits, the subtitle.

January 7, 2004

April 16, 2004

-006

-007

Added line items and made minor edits.

Added product 256L18+128SD with device name LZ38F4060L0YBB0 to Table 25.

Modified UT-SCSP mechanical specs - (not applicable in rev -009).

Updated the line items in order table.

July 9, 2004

-008

-009

Various text edits and updates to the document to reflect current products available within

the LX family. Remove any irrelevant information from the datasheet.

October, 2004

January, 2005

May, 2005

-010

-011

-012

Updated Mechanical Specifications for x16D (103 balls) Package 9x11x1.2 mm.

Added line items to ordering table

May, 2006

Added product 256L18+256L18+256SD and device name PF38F4470LLYBB0.

Updated the RAM “Row to column delay” & “Row precharge time” from 28.5ns to 30.0ns.

Updated hold times from 1.0 ns to 1.5 ns.

Updated VCCQ, S-VCC, and D-VCC voltage MAX from +2.45 V to +2.3 V.

Updated the ordering information table with the ordering matrix we now use and it will have

the Samsung line item in it.

June 2007

013

Updated format and changed document number (from FD1006 to FD317623) to be consistent

with current document tracking implementation.

July 2007

014

15

Updated ordering information

Applied Numonyx branding.

November 2007

317623-15

Datasheet

5

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

1.0

Introduction

This document contains information pertaining to the products in the Numonyx™

StrataFlash® Wireless Memory (L18 SCSP), 512-Mbit LX family with LPSDRAM (x16).

The LX family offers a variety of stacked combinations that includes, flash only, flash +

SDRAM, and flash + SDRAM + SRAM. The intent of this document is to provide

information where this product differs from the Numonyx™ StrataFlash® Wireless

Memory (L18) discrete datasheet.

Refer to the latest revision of the Numonyx™ StrataFlash® Wireless Memory (L18)

Datasheet (order number 251902) for specific flash product details not included in this

document.

The Numonyx™ StrataFlash® Wireless Memory (L18 SCSP), 512-Mbit LX with

LPSDRAM family offers a variety of flash plus xRAM combinations. This L18 flash die

uses the latest generation of Numonyx™ StrataFlash® Wireless Memory featuring

flexible, multiple partitions, hardware read-while-erase / read-while-write operations,

with high performance asynchronous and synchronous burst reads. The LPSDRAM is a

low-power, high-performance volatile memory operating up to 104 MHz with

configurable burst lengths. The LX family integrates up to four flash dies and two xRAM

dies in a common x16D (103 balls) package footprint and signal ballout.With a common

package footprint signal ballout, higher memory density and flash/xRAM combination

migrations can be easily supported without any PCB changes.

1.1

Nomenclature

0x

Hexadecimal prefix

Binary prefix

0b

Byte

8 bits

CFI

Common Flash Interface

Command User Interface

Do Not Use

CUI

DU

ETOX

EPROM Tunnel Oxide

Numonyx™ Flash Data Integrator (software solution)

1 thousand

Numonyx™ FDI

K (noun)

Kb

1024 bits

KB

1024 bytes

Kword

M (noun)

Mb

1024 words

1 million

1,048,576 bits

MB

1,048,576 bytes

One-Time Programmable

(Protection) Lock Register

Protection Register

OTP

LR

PR

Datasheet

6

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

PRD

Protection Register Data

Numonyx™ PSM

Numonyx™ Persistent Storage Manager (software solution)

Read Configuration Register

Reserved for Future Use

Stacked Chip Scale Package

Status Register

RCR

RFU

SCSP

SR

SRD

Word

WSM

Status Register Data

16 bits

Write State Machine

1.2

Conventions

Group Membership Brackets: Square brackets are used to designate group membership

or to define a group of signals with a similar function, such as A[21:1] and SR[4,1].

VCC vs. V_CC: When referring to a signal or package-connection name, the notation

used is VCC. When referring to a timing or electrical level, the notation used is

subscripted such as V_CC

.

Device: This term is used interchangeably throughout this document to denote either a

particular die, or both die in the SCSP.

F[4:1]-CE#: This is a group reference to multiple chip-enable pins in a flash device.

Note that this group reference is different from an individual reference to a single chip-

enable pin. For example, a reference to a single chip enable pin in a flash device is F1-

CE# for die #1,

F2-CE# for die #2, and so on until F4-CE# for die #4. Any F-CE# not used in the LX

device should be treated as a Reserved for Future Use (RFU) signal ball.

F-VCC, D-CAS#, S-VCC: When referencing flash memory signals or timings, the

notation is prefixed with “F-” (e.g. F-VCC, F-V_CC). When the reference is to SDRAM

signals or timings, the notation is prefixed with “D-” (e.g., D-CAS#, D-RAS#). When

the reference is to SRAM signals or timings, the notation is prefixed with “S-” (e.g., S-

VCC, S-CS1#).

November 2007

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Datasheet

7

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

2.0

Functional Overview

The LX family encompasses multiple flash and xRAM die combinations in top/bottom or

dual parameter configurations.

Figure 1 shows the device capability and internal package connections for the LX

product family.

Figure 1: LX Family Block Diagram

LX Family

Flash Segment

F1-CE#

F2-CE#

F-WP1#

Flash Die #1

Flash Die #2

(128 or 256 Mbits)

F-RST#

F-VCC

F-VPP

F4-CE#

F-CLK

ADV#

F-WP2#

WAIT

OE#

Flash Die #3

(128 or 256 Mbits)

Flash Die #4

(128 or 256 Mbits)

F3-CE#

WE#

DQ[15:0]

VCCQ

VSS

xRAM Segment

A[MAX:MIN]

D1-CS#

D2-CS#

LPSDRAM Die#1

(64/128/256 Mbits)

D-DM1 / R-UB#

D-DM0 / R-LB#

D-BA[1:0]

SRAM Die #1

(8 Mbits)

D-CAS#

D-RAS#

S-CS1#

S-CS2

S-VCC

LPSDRAM Die #2

(128/256 Mbits)

D-CLK

D-CKE

D-VCC

Datasheet

8

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

3.0

Package Information

The following package dimensions are available for the 512-Mbit LX Family x16:

• Figure 2, “Mechanical Specifications for x16D (103 balls) Package (9x11x1.4 mm)”

on page 9

• Figure 3, “Mechanical Specifications for x16D (103 balls) Package (9x11x1.2 mm)”

on page 10

Figure 2: Mechanical Specifications for x16D (103 balls) Package (9x11x1.4 mm)

S1

Pin 1

Corner

1

2

3

4

5

6

7

8

9

S2

A

B

C

D

E

F

D

G

H

J

K

e

L

M

b

E

SC SP

Top View - BallSide Down

A2

A1

A

Y

Note: Drawing not to scale.

Dimensions

Package Height

Symbol

A

Min

Nom

Max Notes

1.4

Min

Nom

Max

0.0551

Ball Height

A1

A2

b

D

E

0.200

0.0079

Package Body Thickness

Ball (Lead) Width

Package Body Length

Package Body Width

Pitch

1.070

0.375

11.00

9.00

0.800

103

0.0421

0.0148

0.4331

0.3543

0.0315

103

0.325

10.90

8.90

0.425

11.10

9.10

0.0128

0.4291

0.3504

0.0167

0.4370

0.3583

e

Ball (Lead) Count

Seating Plane Coplanarity

Corner to Ball Distance Along E

Corner to Ball Distance Along D

N

Y

S1

S2

0.100

1.400

1.200

0.0039

0.0551

0.0472

1.200

1.000

1.300

1.100

0.0472

0.0394

0.0512

0.0433

November 2007

317623-15

Datasheet

9

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 3: Mechanical Specifications for x16D (103 balls) Package (9x11x1.2 mm)

9x11x1.2 HPx16D 103ball

S1

1

Corner

1

2

3

4

5

6

7

8

9

S2

A

B

C

D

E

F

D

G

H

J

K

L

e

M

b

E

SCS

Top Vi ew -PBal l S i de

Down

A2

A1

A

Y

Note: Drawing not to scale.

Dimensions

Package Height

Ball Height

Package Body Thickness

Ball (Lead) Width

Package Body Length

Package Body Width

Pitch

Symbol

Min

Nom

Max Notes

1.2

Min

Nom

Max

0.0472

A

A1

A2

b

D

E

0.200

0.0079

0.860

0.375

11.00

9.00

0.800

103

0.0339

0.0148

0.4331

0.3543

0.0315

103

0.325

10.90

8.90

0.425

11.10

9.10

0.0128

0.4291

0.3504

0.0167

0.4370

0.3583

e

N

Ball (Lead) Count

Seating Plane Coplanarity

Corner to Ball Distance Along E

Corner to Ball Distance Along D

Y

S1

S2

0.100

1.400

1.200

0.0039

0.0551

0.0472

1.200

1.000

1.300

1.100

0.0472

0.0394

0.0512

0.0433

Datasheet

10

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

4.0

Ballout and Signal Descriptions

4.1

Device Electrical Ballout

The LX family is available in the x16D (103 balls) package ballout (Figure 4). See

Section 3.0, “Package Information” on page 9 for the mechanical package dimensions

for each ballout. See Table 1, “Signal Descriptions” for electrical connections details on

the SCSP combination intended in this datasheet.

Figure 4: x16D (103 balls) Performance Electrical Ballout for LX Device Family

P

i n

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

A

B

C

D

E

F

D

U

3

A

5

4

A

7

6

A

8

A

2

0

9

A

R

V

2

4

U

S

A

2

5

3

S

A

V

2

6

7

S

U

1

0

D U

A

1

8

1

F

S

2

S

F

1

A

1

7

6

5

4

3

2

V

S

V

S

V

S

D

- V

C

V

S

A

1

S

- V

C

D

- V

C

F

- V

C

F

- A

D

V

#

F

- V

- C

C

#

D

- V

C

R

A

D

e

p

o

e

p

x

D

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p

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p

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F

4

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/

F

- W

P

1

2

#

W

E

#

D

2

- C

S

#

A

2

1

( I n

d

)

( R

F

)

A

2 8

D

e

p

U

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p

s

- W

R

D

1

2

- C

S

E

#

D

F

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A

S

#

S

- C

S

1

#

2

1

( R

F

D

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p

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p

s

G

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1

D

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K

U

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F

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A

9

A

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F

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p

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M

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D

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- D

M 0 /

R

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- C

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R

F

E #

( R

F

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s

S

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#

S

- L

B

#

F

- V

P

V

C

Q

V

C

Q

C

D

F

- C

L

K

F

- V

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V

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Q

- W

A

I T

K

L

K

L

D

Q

2

V

S

V

S

V

S

6

4

L

V

S

9

V

S

V

S

D

Q

1

3

1

D

Q

3

0

D

R

Q

5

D

Q

D

Q

7

D

Q

D

Q

1

D

Q

1

2

5

4

M

D

U

Q

F

U

D

Q

8

D

Q

1

0

R

F

U

D

Q

1

D

U

M

1

2

3

4

5

6

7

8

9

T

o

p

V

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w

-

B

a

l l

S

i d

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D

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w

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lls

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e

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l a t e

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a l ls

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November 2007

317623-15

Datasheet

11

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

4.2

Signal Descriptions

Table 1:

Signal Descriptions (Sheet 1 of 3)

Symbol

Type

Name and Function

Notes

ADDRESS: Global device signals. Share inputs for all memory die addresses during read

and write operations. LPSDRAM Address inputs also provide the op-code during a Mode

Register Set or Special Mode Register Set command.

•

256-Mbit die: AMAX = A24

128-Mbit die: AMAX = A23

64-Mbit die: AMAX = A22

32-Mbit die: AMAX = A21

8-Mbit die: AMAX = A19

A[MAX:1]

Input

A[13:1] are the row and A[9:1] are the column addresses for 256-Mbit LPSDRAM

A[12:1] are the row and A[9:1] are the column addresses for 128-Mbit LPSDRAM

A11 defines the Auto Precharge. During a LPSDRAM Precharge command, A11 is

sampled to determine if all banks are to be precharged (A11 = High).

Note:

A1 is the lowest-order x16 address.

DATA INPUT/OUTPUTS: Global device signals. Inputs data and commands during write

cycles, outputs data during read cycles. Data signals float when the device or its output are

deselected. Data are internally latched during writes on the device.

Input/

DQ[15:0]

ADV#

Output

ADDRESS VALID: Low-true input.

During synchronous flash read operations, addresses are latched on the rising edge of

ADV#, or on the next valid F-CLK edge, whichever occurs first.

Input

In asynchronous flash read operation, addresses are latched on the rising edge ADV#, or

are continuously flow-through when ADV# is kept asserted.

FLASH CHIP ENABLE: Low-true input.

F[4:1]-CE# low selects the associated flash memory die. F[4:1]-CE# high deselects the

associated flash die. When deasserted, the associated flash die is deselected, power is

reduced to standby levels, data and WAIT outputs are placed in high-Z state.

F[4:1]-CE# Input

1

•

F1-CE# is dedicated as flash die #1.

F[4:2]-CE# controls any subsequent individual flash die.

DEVICE CLOCK: Synchronizes the selected memory die to the system’s bus clock in

synchronous operations.

F-CLK,

Input

•

F-CLK is a flash signal. Synchronizes the flash die to the system’s flash bus frequency in

synchronous operations.

D-CLK is a LPSDRAM input signal. Synchronizes the LPSDRAM die to the system’s

memory bus clock. LPSDRAM is sampled on the positive edge of D-CLK.

D-CLK

OUTPUT ENABLE: Global device signal. Low-true input.

OE#

Input

OE# low enables the output drivers of the selected die. OE# high places the output drivers

of the selected die in high-Z.

FLASH RESET: Flash specific signal. Low-true input.

F-RST#

F-RST# low resets internal operations and inhibits write operations. F-RST# high enables

normal operation. Exit from reset places the flash device in asynchronous read array mode.

DEVICE WAIT: Flash device signal.

Indicates data is valid in synchronous array or non-array sync flash reads. Configuration

Register bit 10 (CR.10, WT) determines its polarity when asserted. With F-CE# and OE# at

V_IL, WAIT’s active output is V_OLor V_OH. WAIT is high-Z if F-CE# or OE# is V_IH

.

WAIT

WE#

Output

Input

•

In synchronous array or non-array flash read modes, WAIT indicates invalid data when

asserted and valid data when deasserted.

•

In asynchronous flash page read, and all flash write modes, WAIT is deasserted.

WRITE ENABLE: Global device signal. Low-true input.

WE# low selects the associated memory die for write operation. WE# high deselect the

associated memory die, data are placed in high-Z state.

With LPSDRAM operation, WE# is latched on the positive clock edge in conjunction with the

D-RAS# and D-CAS# signals. The WE# input is used to select the Bank Activate or

Precharge command and Read or Write command.

Datasheet

12

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 1:

Signal Descriptions (Sheet 2 of 3)

Symbol

Type

Name and Function

Notes

FLASH WRITE PROTECT: Flash specific signals. Low-true input.

F-WP# low enables the Lock-Down mechanism. Blocks in a lock-down state cannot be

unlocked with the Unlock command. F-WP# high overrides the Lock-Down function,

enabling locked-down blocks to be unlocked with the Unlock command.

F-WP[2:1]# Input

•

F-WP1# controls flash die #1; F-WP2# are common to all other remaining flash dies.

LPSDRAM CLOCK ENABLE: High-true input

•

If D-CKE goes low synchronously with clock, the internal clock is suspended from the

next clock cycle.

•

The state of the outputs and the burst address is halted.

When all banks are in the idle state, D-CKE is high, the LPDRAM enters into Power

Down and Self-Refresh modes.

D-CKE

Input

•

D-CKE is synchronous except after the device enters Power Down and Self-Refresh

modes, where D-CKE becomes asynchronous until exiting the same mode. The input

buffers, including D-CLK, are disabled during Power Down and Self-Refresh modes,

providing low standby power.

LPSDRAM BANK SELECT: D-BA0 and D-BA1 defines to which bank the Bank Activate,

Read, Write, or Bank Precharge command is being applied. The bank address D-BA0 and

D-BA1 is used latched in Mode Register set.

D-BA[1:0]

D-RAS#

Input

LPSDRAM ROW ADDRESS STROBE: Low-true input.

•

The D-RAS# signal defines the operation commands, with the D-CAS# and WE#

signals.

•

The D-RAS# is latched at the rising edges of D-CLK. When D-RAS# and D-CS# are

asserted and D-CAS# is deasserted, either the Bank Activate command or the

Precharge command is selected by the WE# signal.

•

WE# is deasserted, the Bank Activate command is selected and the bank designated by

D-BA[1:0] is turned on to the active state.

LPSDRAM COLUMN ADDRESS STROBE: Low-true input.

•

D-CAS# signal defines the operation commands in conjunction with the D-RAS# and

WE# signals and is latched at the rising edges of D-CLK.

D-CAS#

Input

•

D-RAS# is deasserted and D-CS# is asserted, the column access is started by asserting

D-CAS#. Read or Write command then is selected by asserting WE# low or high.

LPSDRAM CHIP SELECT: Low-true input.

D[2:1]-CS# low selects the associated LPSDRAM memory die. All commands are masked

when D[2:1]-CS# high. D[2:1]-CS# provides for external bank selection on systems with

multiple banks. It is considered part of the command code.

D[2:1]-CS#

D-DM[1:0]

Input

•

D1-CS# controls LPSDRAM die #1.

D2-CS# controls LPSDRAM die #2.

LPSDRAM INPUT Mask: Data Input Mask.

•

D-DM[1:0] are byte selects. Input data is masked when D-DM[1:0] are sampled HIGH

during a write cycle. D-DM1 masks DQ[15-8], and D-DM0 masks D[7-0].

2

3

•

The D-DM[1:0] latency for Read is 2 Clocks and for Write is 0 Clocks.

SRAM CHIP SELECTS: SRAM specific signal. Low-true input.

When both SRAM chip selects are asserted, SRAM internal control logic, input buffers,

decoders, and sense amplifiers are active. When either or both SRAM chip selects are

deasserted (S-CS1# = V_IHand/or S-CS2 = V_IH), the SRAM is deselected and its power is

reduced to standby levels.

S-CS1#

S-CS2

Input

S-CS1# and S-CS2 are available on stacked combinations with SRAM die, and are RFU on

stacked combinations without SRAM die.

SRAM UPPER/ LOWER BYTE ENABLES: Low - true inputs.

•

During SRAM read and write cycles, R-UB# low enables the SRAM high-order byte on

DQ[15:8], and R-LB# low enables the SRAM low-order byte on DQ[7:0].

R-UB#

R-LB#

Input

2, 3

R-UB# and R-LB# are available on stacked combinations with SRAM die, and are RFUs on

stacked combinations without SRAM die.

FLASH ERASE/ PROGRAM VOLTAGE LEVEL: Flash specific signal.

Valid F-VPP voltage on this ball allows block erase or program functions. Flash memory

array contents cannot be altered when F-V_PP≤ V_PPLK. Block erase and program at invalid F-

VPP voltage should not be attempted.

F-VPP

Power

November 2007

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Datasheet

13

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 1:

Signal Descriptions (Sheet 3 of 3)

Symbol

Type

Name and Function

Notes

FLASH CORE VOLTAGE LEVEL: Flash specific signals. Flash core source voltage.

F-VCC

VCCQ

D-VCC

Power

Flash operations are inhibited when F-V_CC≤ V_LKO. Operations at invalid F-VCC voltage

should not be attempted.

OUTPUT VOLTAGE LEVEL: Global device signals. Device output-driver source voltage.

This balls can be tied directly to the respective memory type VCC if operating within its V_CC

range.

Power

RAM POWER SUPPLY: Supplies power to the RAM dies.

Performance ballout:

•

D-VCC supplies power for LPSDRAM operation.

SRAM POWER SUPPLY: Supplies power to the SRAM die.

S-VCC

Power

3

S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked

combinations without SRAM die.

GROUND: Global ground reference for device memory core type voltages.

VSS

DU

•

Connect all VSS to system ground. Do not float any VSS connections.

DO NOT USE: This ball must be left floating. This ball should not be connected to any

power supplies, signals, or other balls.

-

RESERVED for FUTURE USE: Reserved by Numonyx for future device functionality and

enhancement.

RFU

Notes:

1.

2.

3.

F4-CE# is a shared signal with A28 for the 103-Active Ball High-Performance DRAM package.

D-DM[1:0] are shared signals with R-UB# and R-LB# respectively.

Only available in the 103-Active Ball High-Performance DRAM package.

Datasheet

14

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

5.0

Maximum Ratings and Operating Conditions

5.1

Absolute Maximum Ratings

Warning:

Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent

damage. These are stress ratings only.

NOTICE: This document contains information available at the time of its release. The specifications are subject to change without

notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.

Table 2:

Flash Absolute Maximum Ratings

Parameter

Min

Max

Unit

Notes

Case Temperature under Bias (T_C)

–25

–55

+85

°C

Storage Temperature

+125

Voltage On Any Signal (except F-V_CC,F-V_PP,D-V_CC, S-VCC and

–0.2

+2.0

V

1

V_CCQ

)

F-V_CCVoltage

–0.2

–

+2.50

+2.3

+10.0

50

V

1

V_CCQ, S-VCC and D-V_CCVoltage

F-V_PPVoltage

1

V

1,2,3

4

I

_SHOutput Short Circuit Current

mA

Notes:

1.

All Specified voltages are relative to V_SS. Minimum DC voltage is –0.2 V on input/output signals, F-VCC, D-VCC, VCCQ

and F-VPP signals. During transitions, this level may overshoot to –1.0 V for periods < 5 ns. Maximum DC voltage on F-

VCC is F-V_CC+ 0.5 V, which during transitions may overshoot to F-Vcc +2.0 V for periods < 20 ns. Maximum DC voltage

on input/output signals and VCCQ is V_CCQ+0.5 V, which during transitions may overshoot to V_CCQ+ 2.0V for periods <

20 ns.

2.

3.

Maximum DC voltage on F-VPP may overshoot to +10.0 V for periods < 20 ns.

Program/erase voltage is typically 1.7 V - 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for

1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.

Output shorted for no more than one second. No more than one output shorted at a time.

4.

5.2

Operating Conditions

Warning:

Operation beyond the “Operating Conditions” is not recommended and extended

exposure beyond the “Operating Conditions” may affect device reliability.

Table 3:

Device Operating Conditions

Flash + xRAM

Symbol

Parameter

Min

–25

1.7

Max

+85

2.0

T_C

Operating Temperature

Flash Supply Voltage

°C

V

F-V_CC

Flash and LPSDRAM I/O Voltage

LPSDRAM Supply Voltage

V_CCQ

D-V_CC, S-V_CC

1.7

1.9

V

V_PPL

V_PPH

F-V_PPVoltage Supply (Logic Level)

Factory word programming F-V_PP

0.9

8.5

2

V

9.5

Note: In typical operation, the F-VPP program voltage is V_PPL. F-VPP can be connected to 8.50 V - 9.50 V for 1000 cycles on

main blocks and 2500 cycles on parameter blocks.

November 2007

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Datasheet

15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

6.0

Electrical Specifications

6.1

Flash DC Characteristics

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for flash DC characteristics.

6.2

SRAM and LPSDRAM DC Characteristics

NOTICE: DC Characteristics of all die in a SCSP device need to be considered accordingly, depending

on the SCSP device operation.

Table 4:

Parameter

D-VCC

LPSDRAM DC Characteristics (Sheet 1 of 2)

Description

Test Conditions

Min

Typ

Max

Unit

Notes

Voltage Range

Density

1.7

—

–

—

1.9

60

V

128-Mbit

256-Mbit

128-Mbit

Operating Current at

min cycle time

Burst Length = 1

I_CC1

(One Bank

Active)

I_IO= 0mA

t_CK= min

mA

75

Precharge Standby

Current: Power

Down Mode (All

banks idle)

–

600

D-CKE = L,

D-CS# = H

t_CK= min

I_CC2P

I_CC2N

I_CC3P

I_CC3N

μA

256-Mbit

128-Mbit

256-Mbit

128-Mbit

256-Mbit

128-Mbit

256-Mbit

—

700

15

5

Precharge Standby

Current: Non-Power

Down Mode (All

banks idle)

D-CKE = H,

D-CS# = H

t_CK= min

mA

Active Standby

Current in Power

Down Mode (All

banks active)

D-CKE = L,

t_CK= min

5

Active Standby

Current: Non-Power

Down Mode (All

banks active)

20

25

D-CKE = H,

t_CK= min

mA

3

128-Mbit

256-Mbit

—

70

80

I_CC4

(4 Banks

active)

Operating Current

Burst Mode

I_IO= 0mA

t_CK= min

128-Mbit

256-Mbit

128-Mbit

256-Mbit

128-Mbit

256-Mbit

—

130

150

500

600

—

I_CC5

I_CC6

I_CC7

Auto-Refresh Current

Self-Refresh Current

t_RC> t_RCmin

mA

μA

2

4

Address & Data

toggling at min cycle

time

—

Address & Data

toggling at min cycle

time

—

15

Deep Power Down

Current

μA

—

V_CCQ

–

V_OH

V_OL

V_IH

Output High Voltage

Output Low Voltage

Input High Voltage

I_OH= -100 μΑ

—

–

V

0.15

I_OL= 100 μΑ,

–0.1

0.2

V_CCQmin

V_CCQ

0.4

–

V_CCQ

0.2

+

—

Datasheet

16

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 4:

LPSDRAM DC Characteristics (Sheet 2 of 2)

V_IL

Input Low Voltage

—

-0.2

–2

—

0.3

+2

V

Input Leakage

Current

–0.2V < V_IN<

V_CCQ+0.2 V

I_IL

μA

1

Notes:

1.

2.

3.

4.

Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.

Input signals are toggled at max frequency to simulate SCSP condition, where another device may be active.

No accesses in progress.

See Table 5, “LPSDRAM Self-Refresh Current”.

Table 5:

LPSDRAM Self-Refresh Current

# of Banks

Set

Temperatur

e

Parameter

Description

Test Condition

Unit

Bank 0 &

1

Refreshed

All Banks

Refreshed

Bank 0

Refreshed

85 °C max

70 °C max

45 °C max

15 °C max

85 °C max

70 °C max

45 °C max

15 °C max

500

440

390

350

600

525

450

375

400

350

290

240

450

375

300

250

300

280

260

240

315

295

270

250

Self-Refresh Current

(All Banks Refreshed)

D-CKE < 0.2 V

t_CK= Infinity

ICC6

(128-Mbit)

μA

Self-Refresh Current

(All Banks Refreshed)

D-CKE < 0.2 V

t_CK= Infinity

ICC6

(256-Mbit)

μA

Note: Other than I_CC6for all Banks at 85°C, the Self-Refresh currents are verified during device characterization and not

100% tested.

Table 6:

SRAM DC Characteristics (Sheet 1 of 2)

1.8 V SRAM

Parameter

Description

Test Conditions

Unit

MIN

MAX

1.9

—

S-V_CC

V_DR

Voltage Range

—

1.7

1.0

V

S-V_CCfor Data Retention

Operating Current at minimum cycle

time

I_CC

I_IO= 0 mA

—

35

6

mA

Operating Current at maximum

cycle time (1 μs)

I_CC2

S-CS1# ≥ S-V_CC-0.2 V

or S-CS2 ≤ V_SS+0.2 V

Address/Data toggling at minimum

cycle time

I_SB

Standby Current

—

20

μA

I_DR

Current in Data Retention mode

Output High Voltage

S-V_CC= 1.0 V

10

—

μA

S-V_CC

0.15

-

V_OH

I_OH= -100 μA

V

I

_OL= 100 μA,

V_CCMIN

V_OL

Output Low Voltage

-0.1

0.2

V

November 2007

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Datasheet

17

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 6:

SRAM DC Characteristics (Sheet 2 of 2)

Input High Voltage

S-V_CC

0.4

-

S-V_CC

+

V_IH

—

V

0.2

V_IL

Input Low Voltage

-0.2

-1

0.4

+1

V

*I_IL

Input Leakage Current

-0.2 < V_IN< S-V_CC+0.2 V

μA

-0.2 < V_IN< S-V_CC+0.2 V

S-V_CC= V_DR

Input Leakage Current in Data

Retention Mode

*I_LDR

-1

+1

μA

Note: * Input leakage currents include High-Z output leakage for bi-directional buffers with tri-state outputs.

Datasheet

18

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

7.0

AC Characteristics

7.1

AC Test Conditions

Figure 5: Transient Equivalent Testing Load Circuit

Z_O= 50 Ohms

I/O

Output

C_L=

30pf

50

Ohms

V_CCQ/2

Notes:

1.

2.

Test configuration component value for worst case speed conditions.

C_Lincludes jig capacitance

7.2

Flash AC Characteristics

Capacitance

7.2.1

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information.

7.2.2

7.2.3

7.2.4

AC Read Specifications

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information.

Flash AC Write Specifications

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information.

Flash Program and Erase Characteristics

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information.

7.3

SRAM and LPSDRAM AC Characteristics

SRAM and LPSDRAM Capacitance

7.3.1

November 2007

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Datasheet

19

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 7:

SRAM and LPSDRAM Capacitance

MAX

(SRAM)

MAX

(LPSDRAM)

Symbol

Parameter

Unit

Condition

C_IN

Input Capacitance

Output Capacitance

6

7

5

7

pF

V_IN= 0 V

C_OUT

V_OUT= 0 V

Note: Sampled, not 100% tested. T_C= 25 °C, f = 1 MHz.

7.3.2

LPSDRAM AC Characteristics

Table 8:

LPSDRAM AC Characteristics—Read-Only Operations

Symbol

Parameter

Clock Cycle Time

Test Condition

Min

Max

Unit

Notes

CL = 3

D-CLK = 104 MHz

t_RC

9.5

—

ns

1,2

t_CKH

t_CKL

t_T

Clock High Level Pulse Width

Clock Low Level Pulse Width

Transition Time

3

—

ns

1,2

0.5

1.5

2

1.0

—

t_CKEH

t_CKES

t_AH

D-CKE Hold Time

D-CKE Setup Time

—

Address Hold Time

1.5

2

—

t_AS

Address Setup Time

Data Input Hold Time

Data Input Setup Time

—

t_IH

1.5

2

—

t_IS

—

D-CS#, D-RAS#, D-CAS#, WE#, D-DM

Hold Time

t_CMH

t_CMS

t_AC

1.5

2

—

7

ns

1,2

D-CS#, D-RAS#, D-CAS#, WE#, D-DM

Setup Time

Clock to valid output delay (positive

edge of clock)

CL = 3

—

t_OH

t_LZ

Data Out Hold Time

2.0

1

—

7

ns

1,2

Clock to Output in Low-Z

Clock to Output in High-Z

t_HZ

—

Row Active time (Active to Precharge

command)

t_RAS

t_RC

60

90

30

100K

—

ns

1,2

Row Cycle time (Active to Active

command on same bank)

Row to column delay (Active to Read/

Write)

t_RCD

—

t_RP

t_REF

t_RFC

t_SREX

Row Precharge Time

30

—

64

—

ns

ms

ns

1,2

Refresh Period (4096 rows)

Auto-Refresh Period

110

120

Self-Refresh Exit Time (Self refresh to active)

ns

Notes:

1.

2.

The minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time.

LPSDRAM AC specs are guaranteed only when normal output driver strength is used. See Table 23, “LPSDRAM

Configurable Output Driver Strength” on page 34.

Datasheet

20

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 9:

LPSDRAM AC Characteristics—Write Operations

Symbol

Parameter

Test Condition

Min

Max

Unit

t_WR

Write Recovery Time

20

—

ns

t_RRD

t_DAL

t_CDL

t_BDL

t_CCD

t_DQW

t_DQZ

Active bank a to Active Bank b command

Last data input to Active Delay

—

t_WR+ t_RP

ms

t_CK

Last data input to New Read/Write Command

Last data input to Burst Terminate Command

Read/Write command to Read/Write command

D-DM write mask latency

1

0

2

D-DM data out mask latency

Load Mode Register Command to Active/Refresh

Command

t_MRD

—

2

t_CK

t_WR/ t_CK< 1

1 < t_WR/ t_CK< 2

CL = 3

—

1

2

t_WR

Write Recovery Time

t_CK

—

3

t_PHZ

Data out to High Z from Precharge command

Initialization Delay

CL = 2

—

2

t_CK

CL = 1

—

t_INI

200

μs

Notes:

1.

2.

The minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time.

LPSDRAM AC specs are guaranteed only when Normal Output Driver Strength is used. See Table 23.

7.3.3

SRAM AC Read Specifications

Table 10: SRAM Asynchronous Read Specifications (Sheet 1 of 2)

#

Symbol

Parameter

MIN

MAX

Unit

Notes

R1

R2

R3

R4

R5

R6

R7

R8

R9

t_RC

Read Cycle Time

70

—

5

—

70

35

70

—

ns

t_AA

Address to Output Delay

S-CS₁# to Output Delay

S-CS₂to Output Delay

t_CO1

t_CO2

t_OE

OE# to Output Delay

t_BA

R-UB#, R-LB# to Output Delay

S-CS₁# or S-CS₂to Output in Low-Z

OE# to Output in Low-Z

S-CS₁# or S-CS₂to Output in High-Z

OE# to Output in High-Z

t_LZ

1,2

1

t_OLZ

t_HZ

0

—

0

25

1,2,3

1,3

t_OHZ

0

Output Hold (from Address, S-CS₁#, S-CS₂, or OE#

change, whichever occurs first)

R10

t_OH

0

—

ns

November 2007

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Datasheet

21

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 10: SRAM Asynchronous Read Specifications (Sheet 2 of 2)

R11

R12

t_BLZ

t_BHZ

R-UB#, R-LB# to Output in Low-Z

R-UB#, R-LB# to Output in High-Z

0

—

ns

1

25

Notes:

1.

2.

Sampled, not 100% tested.

At any given temperature and voltage condition, t_HZ(MAX) is less than t_LZ(MAX) for a given device and from device-to-

device interconnection.

3.

Timings of t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

7.3.4

SRAM AC Write Specifications

Table 11: SRAM Asynchronous Write Specifications

70 ns

85 ns

#

Symbol

Parameter¹

Notes

MIN

MAX

MIN

MAX

W1

W2

W3

W4

W5

W6

W7

W8

W9

t_WC

t_AS

Write Cycle Time

70

0

—

85

0

—

Address Setup to WE# and R-UB#, R-LB# going low

WE# Pulse Width

4,6

t_WP

t_DW

t_AW

t_CW

t_DH

t_WR

t_BW

55

30

60

0

60

35

70

0

2,3,6

Data to Write Time Overlap

Address Setup to WE# going high

S-CS1# Setup to WE# going high

Data Hold from WE# High

6

Write Recovery

0

5,6

6

R-UB#, R-LB# setup to WE# going high

60

70

Notes:

1.

2.

See also Figure 6, “AC Waveform SRAM Write Operation” on page 23.

A write occurs during the overlap (t_WP) of low CS1# and low WE#. A write begins when S-CS1# goes low and WE# goes

low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double

byte operation. A write ends at the earliest transition when

S-CS1# goes high and WE# goes high. The t_WPis measured from the beginning of write to the end of write.

t_WPis measured from S-CS1# going low to end of write.

t_ASis measured from the address valid to the beginning of write.

t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as

S-CS1# or WE# going high.

The same-e timing parameters apply if the Write operation is performed by toggling S-CS2 instead of

S-CS1#. S-CS2 is asserted high while S-CS1# is asserted low

3.

4.

5.

6.

Datasheet

22

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 6: AC Waveform SRAM Write Operation

Device

Standby

Address Selection

V_IH

Address Stable

A[MAX:MIN]

V_IL

W1

V_IH

S-CS1#

W8

V_IL

V_IH

S-CS2

V_IL

W6

V_IH

OE#

W5

V_IL

W3

V_IH

WE#

V_IL

W7

W4

V_OH

H igh Z

High Z

Data In

W9

DQ[15:0]

V_OL

W2

V_IH

R-UB# / R-LB#

V_IH

Table 12: SRAM Data Retention Timing

Parameter

Description

MIN

MAX

Unit

t_SDR

t_RDR

Data Retention Set-up Time

Data Retention Recovery Time

0

–

ns

70 or 85

November 2007

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Datasheet

23

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 7: SRAM Data Retention Waveform (S-CS1# Controlled)

t_RDR

t_SDR

Data Retention Mode

S-V_CC

S-V_CCmin

S-V_IHmin

V_DR

S-CS1#

V_SS

Note: S-CS1# ≥ S-V_CC- 0.2 V, S-CS2 ≥ S-Vcc – 0.2V

Figure 8: SRAM Data Retention Waveform (S-CS2 Controlled)

t_SDRt_RDR

Data Retention Mode

S-V_CC

S-CS2

S-V_CCMIN

V_DR

V_ILMAX

V_SS

Note: S-CS2 ≤ 0.2 V

Datasheet

24

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

8.0

Power and Reset Specifications

8.1

Flash Power and Reset Specifications

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information.

8.2

LPSDRAM Power-up Sequence and Initialization

The LPSDRAM must be powered up and initialized in a predefined manner. Once power

is applied to D-VCC and VCCQ simultaneously, and the clock is stable, the LPSDRAM

requires a t_INIdelay prior to issuing any command other than the NOP command. The

NOP command should be applied at least once during the t_INIdelay. After the t_INIdelay,

a Precharge command should be applied to precharge all banks. This must be followed

by two back to back Auto-Refresh cycles. After the Auto-Refresh cycles are complete,

the Mode Registers must be programmed. The Mode Register will power-up in an

unknown state. The Mode Register and the Extended Mode Register should be loaded

prior to issuing any operational commands.

November 2007

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Datasheet

25

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

9.0

Bus Operations Overview

9.1

Flash, LPSDRAM and SRAM Bus Operations

Bus operations for this L18 SCSP LX family (x16) device involve the control of flash,

SRAM, and LPSDRAM inputs. The bus operations are shown in:

• Table 13, “Flash + LPSDRAM Bus Operations”

• Table 14, “LPSDRAM Functional Mode Description: Current State bank n, Command

to Bank n”

• Table 15, “LPSDRAM Functional Mode Description: Current State bank n, Command

to Bank m”

• Table 16, “Flash + SRAM Bus Operations”

Fully synchronous operations are performed by the LPSDRAM to latch the commands at

the positive edges of D-CLK.

See the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for complete descriptions of flash modes and commands, command bus-cycle

definitions and flowcharts that illustrate operational routines.

Table 13: Flash + LPSDRAM Bus Operations (Sheet 1 of 3)

Mode

Sync Array

Read

Flash

D_OUT

1,4

, 6

H

L

X

Active

H

1,4

,5,

6

Async

Read

De-

asserted

Flash

D_OUT

X

LPSDRAM outputs must be in High-Z

2,3

,5,

6

V_PPL/

V_PPH

Flash

D_IN

Write

H

L

H

L

High-Z

L

Output

Disable

Flash

H

L

H

X

H

X

High-Z

H

X

6

High-Z

Flash

High-Z

Standby

Reset

Any LPSDRAM mode allowed

Flash

High-Z

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26

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 13: Flash + LPSDRAM Bus Operations (Sheet 2 of 3)

Mode

RAM

D_OUT

Active

Read

H

X

L

H

L

X

V

Row Address

6,7

L

6,7

,8,

10

L/

H

Col

RAM

D_OUT

H

With Auto

Precharge

Addr

H

Write

L

L/

H

RAM

D_IN

6,9

,10

Flash outputs must be in High-Z

L

H

X

H

X

L

H

L

V

X

With Auto

Precharge

H

RAM

High-Z

Burst Stop

H

X

6

Precharge

One Bank

V

X

L

H

X

RAM

High-Z

6

All Banks

Auto-

Refresh

RAM

High-Z 13

6,

H

L

X

Flash must be in High-Z

Self-

Refresh

Entry

RAM

High-Z 13

6,

X

Self-

Refresh

Exit

Flash must be in High-Z

Any flash mode allowed

H

X

L

H

X

H

X

RAM

6

L

H

X

High-Z

H

November 2007

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Datasheet

27

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 13: Flash + LPSDRAM Bus Operations (Sheet 3 of 3)

Mode

6,

11,

12

Load Mode

Register

RAM

High-Z

L

H

X

L

X

L

Operand Code

X

Flash outputs must be in High-Z

Any flash mode allowed

Input/

Output

Enable

RAM

6,

X

High-Z 10

Input

Inhibit/

Output

High-Z

RAM

6,

X

H

X

High-Z 10

Clock

Suspend

Entry

Any flash mode allowed

X

V

H

L

X

V

X

V

RAM

High-Z 14

6,

H

L

H

L

X

Flash outputs must be in High-Z

Clock

Suspend

Exit

RAM

6

Flash outputs must be in High-Z

X

High-Z

Power

Down

Entry

Any flash mode allowed

Flash outputs must be in High-Z

Any flash mode allowed

X

H

X

H

L

X

H

X

H

X

H

X

H

RAM

High-Z 15

6,

H

L

H

L

Power

Down Exit

RAM

6

H

High-Z

Flash outputs must be in High-Z

Deep

Power

Down

Entry

RAM

6

L

H

L

H

X

High-Z

Flash outputs must be in High-Z

Deep

RAM

6

Power

X

H

L

H

X

H

L

X

H

X

H

X

High-Z

Down Exit

Device

Deselect

(NOP)

RAM

6

Any flash mode allowed

H

High-Z

No

Operation

(NOP)

RAM

6

Flash outputs must be in High-Z

High-Z

Notes:

1.

2.

3.

4.

5.

6.

7.

WAIT is only valid during synchronous flash reads. Refer to the discrete datasheet for detailed WAIT functionality.

OE# and WE# should never be asserted simultaneously.

X can be V_ILor V_IHfor inputs, V_PPL, V_PPHor V_PPLKfor F-V_PP.

Flash CFI query and Status Register accesses use DQ[7:0] only, all other reads use DQ[15:0].

Refer to the L18 datasheet for valid D_INduring flash writes.

All states and sequences not shown are illegal or reserved.

A[13:1] provide row address for 256-Mbit LPSDRAM. A[12:1] provide row address for 128-Mbit LPSDRAM. A[9:1]

provide column address for 128-Mbit or 256-Mbit LPSDRAM.

8.

Select bank and column address, and start Read. A11 High enables auto precharge.

Select bank and column address, and start Write. A11 High enables auto precharge.

Activate or deactivate the data during Writes with zero-clock delay and during Reads with two-clock delay. D-DM0

corresponds to DQ[7:0], D-DM1 corresponds to DQ[15:8].

9.

10.

11.

12.

A[11:1] define the operand code to the register.

Extended Mode Register is programmed by setting D-BA1 = H and D-BA0 = L. For Mode Register programming, set

D-BA1 = D-BA0 = L.

13.

14.

15.

All banks must be precharged before issuing an Auto-refresh command.

Clock suspend mode occurs when column access or burst is in progress.

Power-Down occurs when no accesses are in progress.

Datasheet

28

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 14: LPSDRAM Functional Mode Description: Current State bank n, Command to Bank

n

D-

RAS#

Current State D-CS#

D-CAS# WE#

Command

Action

Notes

H

X

H

L

X

H

L

NOP

Continue previous operation

Select and activate row

Auto refresh

Any

L

H

L

NOP

L

Active

L

Auto refresh

Load Mode Register

Precharge

Read

Idle

L

Mode Register set

L

H

L

NOP

H

L

H

L

Select Column & start read burst

Select Column & start write burst

Deactivate Row in bank (or banks)

Row Active

L

Write

H

L

Precharge

3

Truncate read & start new read

burst

L

H

L

H

L

Read

Write

5

Read (without

Auto

Truncate read & start new write

burst

precharge)

L

H

L

Precharge

Truncate read, start precharge

Burst terminate

H

Burst Terminate

Truncate write & start new read

burst

L

H

L

H

L

Read

Write

5

Write (without

Auto

Truncate write & start new write

burst

precharge)

L

H

L

Precharge

Truncate write, start precharge

Burst terminate

H

Burst Terminate

Notes:

1.

2.

3.

The table applies when both D-CKE_n-1and D-CKE_nare high.

All states and sequences not shown are illegal or reserved.

This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for

precharging.

4.

5.

A command other than No Operation (NOP), should not be issued to the same bank while a Read or Write Burst with

auto precharge is enabled.

The new Read or Write command could be auto precharge enabled or auto precharge disabled.

Table 15: LPSDRAM Functional Mode Description: Current State bank n, Command to Bank

m

Current

State

D-

RAS#

D-

CAS#

D-CS#

WE#

Command

Action

Notes

H

X

NOP

Any

Continue previous Operation

1,2

Any

L

X

L

H

X

L

H

X

H

L

H

X

H

L

Idle

Any command allowed to bank m 1,2

Active

Read

Activate Row

Start Read burst

Precharge

1,2

Row

H

L

Activating,

Active, or

Precharging

L

Write

H

L

Precharge

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Datasheet

29

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 15: LPSDRAM Functional Mode Description: Current State bank n, Command to Bank

m

L

H

L

H

L

Active

Read

Activate Row

Start Read burst

Start Write burst

Precharge

1,2

Read with

Auto

Precharge

disabled

H

L

Write

H

L

Precharge

Active

Read

L

H

L

Activate Row

Start Read burst

Start Write burst

Precharge

Write with

Auto

precharge

disabled

H

L

Write

H

L

Precharge

Active

Read

L

H

L

Activate Row

Start Read burst

Start Write burst

Precharge

Read with

Auto

Precharge

H

L

Write

H

L

Precharge

Active

Read

L

H

L

Activate Row

Start Read burst

Start Write burst

Precharge

Write with

Auto

precharge

H

L

Write

H

L

Precharge

Notes:

1.

2.

The table applies when both D-CKE_n-1and D-CKE_nare high.

All states and sequences not shown are illegal or reserved.

Table 16: Flash + SRAM Bus Operations (Sheet 1 of 2)

Synchronous Array

H

L

H

L

Active

L

X

L

X

H

X

Flash D_OUT

Flash D_IN

1,2,3,5

1,2,3,4

and Non-Array Read

Deasserte

d

Asynchronous Read

X

V

_PPLor

V_PPH

Write

H

High-Z

Output Disable

Standby

H

L

H

X

H

X

H

X

High-Z

X

Flash High-Z

1,2,3

Any SRAM

mode allowed

X

Reset

X

Datasheet

30

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 16: Flash + SRAM Bus Operations (Sheet 2 of 2)

Read

Write

X

H

L

H

L

High-Z

X

L

H

L

SRAM D_OUT

SRAM D_IN

1,2,3

H

1,2,3,5

,6

Output Disable

Standby

L

H

X

SRAM High-Z

1,2,3,5

,6

Any Flash mode allowed

H

Same as SRAM

Standby

Data Retention

1,6

Notes:

1.

2.

3.

4.

5.

6.

Flash + SRAM Bus Operations only applicable with 103-Active Ball High-Performance DRAM ballout.

OE# and WE# should never be asserted simultaneously.

X can be V_ILor V_IHfor flash or RAM inputs. V_PPLor V_PPHfor F-VPP.

Refer to the latest revision of theL18 datasheet for valid D_INduring Flash writes.

Flash CFI query and Status Register accesses use DQ[7:0] only, all other reads use DQ[15:0].

The SRAM can be placed into data retention mode by lowering S-VCC to the V_DRlimit when in standby mode.

November 2007

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Datasheet

31

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

10.0

Flash OperationS

Refer to the Numonyx™ StrataFlash^®Wireless Memory (L18) Datasheet (order number

251902) for detailed information on the following:

• Read Operations

• Program Operations

• Erase Operations

• Suspend and Resume Operations

• Block Locking and Unlocking Operations

• Protection Register Operations

• Configuration Operations

• Dual Operations Considerations

• Memory Map and Partitioning

• Flash Write State Machine

• Flash Common Flash Interface

• Flash Flowcharts

Datasheet

32

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

11.0

LPSDRAM Register Definition

11.1

Mode Register

The Mode Register is used to define specific modes of operation of the LPSDRAM. This

definition includes the selection of a burst length, burst type, a D-CAS# latency, and a

write burst mode. The Mode Register settings are illustrated in the Table below. The

Mode Register is programmed by the Load Mode Register command and will retain the

information until it is reprogrammed, the LPSDRAM loses power, or the LPSDRAM goes

in Deep Power-Down mode. The register should be loaded when all banks are idle, and

subsequent operation should only be initiated after t_MRD

.

Addresses A[12, 11, 9, 8] must be set to “0“ for all Mode Register programming. D-

BA[1:0] should be set to (0,0) to differentiate from Extended Mode Register

programming.

Table 17: LPSDRAM Setting for Burst Length

Burst Length

A3

A2

A1

A4 = 0

A4 = 1

1

0

1

0

1

0

1

0

1

2

4

8

4

8

Full Page

Reserved

Notes:

1.

2.

States not mentioned are undefined.

The sequential burst will wrap on reaching the last column of the burst length.

Table 18: LPSDRAM Setting for Burst Type

A4

Burst Type

0

1

Sequential

Interleaved

Table 19: LPSDRAM Setting for D-CAS# Latency

A7

A6

A5

CAS# Latency

0

1

0

1

2

3

Note: CAS# Latency not mentioned are undefined.

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Datasheet

33

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 20: LPSDRAM Setting for Write Burst Mode

A10

Write Burst Mode

0

1

Programmed Burst

Single Word Burst

11.2

LPSDRAM Extended Mode Register

The Extended Mode Register controls two power saving functions: Temperature-

Compensated Self-Refresh (TCSR), and Partial-Array Self-Refresh (PASR). Both these

features can only be used when the LPSDRAM is under Self-Refresh. In addition, the

Configurable Output Driver Strength can be programmed through the Extended Mode

Register.

The Extended Mode Register is programmed by the Load Mode Register command and

will retain the information until it is reprogrammed, the LPSDRAM loses power, or the

LPSDRAM goes in Deep Power-Down mode. The register should be loaded when all

banks are idle, and subsequent operation should only be initiated after t_MRD

.

To program the Extended Mode Register, bank addresses D-BA1 = 1, and D-BA0 = 0

should be used. Addresses A[12:6] should be set to '0'.

Table 21: LPSDRAM Setting for Partial-Array Self-Refresh (PASR)

A3

A2

A1

Self-Refresh Coverage

0

1

0

1

0

Four Banks

Two Banks (Bank 0 & Bank 1)

One Bank (Bank 0)

Table 22: LPSDRAM Setting for Temperature-Compensated Self-Refresh

A5

A4

Maximum Ambient Temperature

1

0

1

0

1

0

85 °C

70 °C

45 °C

15 °C

Table 23: LPSDRAM Configurable Output Driver Strength

A7

A6

Strength

Output Load (pF)

0

1

0

1

0

1

Normal

Half

30

TBD

NA

Reserved

NA

Note: LPSDRAM AC specs are guaranteed only when normal output driver strength is used.

Datasheet

34

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

12.0

LPSDRAM Commands and Operations

12.1

LPSDRAM No Operation / LPSDRAM Deselect

The NOP (No Operation) / LPSDRAM Deselect command is used on a LPSDRAM that is

selected

(D-CS# low). It is also used to deselect the LPSDRAM by preventing new commands

from being executed. Operations already in progress are not affected.

12.2

LPSDRAM Active

The Active command is used to activate a row in particular bank for a subsequent read

or write access. The value of the bank D-BA[1:0] and the row address needs to be

provided. The row remains active until a precharge command is issued to the bank. A

Precharge command must be issued before opening a different row in the same bank.

More than one bank can be active at any time. A read or write command could be

issued to that row, subject to the t_RCDspecification. t_RCD(min) should be divided by the

clock period and rounded up to the next whole number to determine the earliest clock

edge after the active command on which the read/write can be entered. A subsequent

Active command to another row in the same bank can only be issued after the previous

row has been closed. The minimum time interval between two successive active

commands on the same bank is defined by t_RC. The minimum time interval between

two successive active commands on the different banks is defined by t_RRD. This is

illustrated in Figure 11 on page 38.

12.3

LPSDRAM Read Command

Read command is used to initiate a burst read to an active row. The value of D-BA[1:0]

select the bank and address inputs select the starting column location. The value of

A11 determines whether or not auto precharge is used. Output data appears on the

data bus, subject to the logic level on the D-DM[1:0] inputs two clocks earlier. D-

DM[1:0] latency for read command is 2 clock cycles.

The burst length is set in the mode register. The starting column and bank address is

provided along with the auto precharge option. During read bursts, the starting valid

data-out corresponding to the starting column address will be available after CAS

latency cycles after the read command. Each subsequent data-out will be valid by the

next positive edge of the clock. This is shown in Figure 12, “LPSDRAM Example of D-

CAS# Latency, CL = 2” on page 38 with a CAS latency of 2. Data from a read burst may

be truncated by a subsequent read command. The first data from the new burst follows

either the last element of a completed burst or the last desired element of a longer

burst that is being truncated. The new read command can be issued as early as CL-1

cycles before the last desired element. This is shown in Figure 13, “Consecutive

LPSDRAM Read Bursts with CL = 2” on page 39.

Figure 14 on page 39 shows random LPSDRAM access reads. These can be issued to

the same or different banks.

A read burst can be terminated by a subsequent write command, and data from a fixed

length read burst can be followed by a write command. The write command may be

initiated on the clock edge immediately following the last data element from the read

burst, provided the I/O contention could be avoided. D-DM[1:0] can be used to control

I/O contention as shown in Figure 15, “LPSDRAM Read to LPSDRAM Write Command”

on page 39. D-DM[1:0] latency is 2 clocks for output buffers masking, so the D-

DM[1:0] signal must be set high at least 2 clocks prior to the write command. D-

DM[1:0] latency for write is zero clocks, so D-DM[1:0] must be set low before write

command to ensure data written is not masked.

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Datasheet

35

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

A read burst may be followed by or truncated with a Precharge command, which could

be issued CL-1 cycles before the last desired element. This is shown in Figure 16,

“LPSDRAM Read Command Followed by Precharge” on page 40. Following Precharge

command, another command to the same bank cannot be issued until t_RPis met.

Similarly Burst Terminate command can be used to stop a burst as shown in Figure 17,

“LPSDRAM Read Followed by Burst Terminate” on page 40.

12.4

LPSDRAM Write Command

The write command is used to initiate a burst write access to an active row. The value

of D-BA[1:0] select the bank and address inputs select the starting column location.

The value of A11 determines whether or not auto precharge is used. Input data

appearing on the data bus, is written to the memory array subject to the D-DM[1:0]

input logic level appearing coincident with the data.

D-DM[1:0] latency for write command is 0-clock cycle.

The burst length is set in the mode register. The starting column and bank address is

provided along with the auto precharge option. The first valid data-in is registered

coincident with the Write command. Subsequent data elements will be registered on

each successive positive clock edge. Figure 16, “LPSDRAM Read Command Followed by

Precharge” on page 40 shows 2 consecutive 4 word write bursts. A write burst may be

followed by or truncated with a Precharge command to the same bank. The Precharge

should be issued t_WRafter the clock edge after the last desired input data is entered. In

addition, when truncating a Write burst, the D-DM[1:0] signal must be used to mask

input data for the clock edge coincident with the precharge command. This is shown in

Figure 19 and Figure 20 on page 41, where t_WRcorresponds to either 1 or 2 clock

cycles, respectively. Following the Precharge command, a subsequent command cannot

be issued to the same bank until t_RPis met.

Write Burst can be truncated with a Burst Terminate command. While truncating, the

input data being applied coincident to the burst terminate will be ignored.

Data for any writes may be truncated by a subsequent Read command as shown in

Figure 21 on page 41. Once the Read command is registered, the data inputs will be

ignored.

12.5

12.6

LPSDRAM Power-Down

Power-down occurs if D-CKE is set low coincident with LPSDRAM Deselect or NOP

command and when no accesses are in progress. If power-down occurs when all banks

are idle, it is Precharge Power-Down. If power-down occurs when one or more banks

are active, it is referred to as Active power-down. The LPSDRAM cannot stay in this

mode for longer than the refresh period (64 ms) without losing data. The Power-Down

state is exited by setting D-CKE high while issuing a LPSDRAM Deselect or NOP

command. This is shown in Figure 22 on page 42.

LPSDRAM Deep Power-Down

The Deep Power-Down (DPD) mode enables very low standby currents. All internal

voltage generators inside the LPSDRAM are stopped and all memory data are lost in

this mode. To enter the DPD mode, all banks must be precharged, prior to the DPD

command. To exit this mode, the

D-CKE is taken high after the clock is stable.

Datasheet

36

November 2007

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Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

12.7

LPSDRAM Clock Suspend

This mode occurs when a column access or burst is in progress, and D-CKE is set low.

The internal clock gets suspended freezing the LPSDRAM logic. Any command or data

present on the input pins at the time of suspended internal clock is ignored. The output

data on the pins stays frozen. This mode is exited by setting D-CKE high, which results

in resumption of the operation. Figure 23 on page 42 shown clock suspend during a

write burst and Figure 24 on page 43 shows a clock suspend during a read burst.

12.8

12.9

LPSDRAM Precharge

The Precharge is used to deactivate an active row in a particular bank or active row in

all banks. The banks will be available for row access after a specified time (t_RP) after

the Precharge command is issued. If one bank is to precharged, the particular bank

address needs to be addressed. If all banks are to be precharged, A11 should be set

high along with the Precharge command.

LPSDRAM Auto Precharge

Auto Precharge is accomplished when A11 is high, to enable auto precharge in

conjunction with a specific read or write command. This precharges the row after the

read or write burst is complete. Auto precharge ensures that a precharge is initiated at

the earliest valid stage within a burst. Another command to the same bank must not be

issued until the precharge time (t_RP) is completed. Auto precharge does not apply in

full-page burst mode. Auto precharge is non- persistent.

12.10

LPSDRAM Concurrent Auto Precharge

If an access command with Auto Precharge enabled is being executed, it can be

interrupted by another access command.

• Figure 25 on page 43 shows a Read with Auto Precharge to Bank n, interrupted by

a Read (with or without Auto precharge) to bank m. The Read to bank m will

interrupt the Read to Bank n, CAS latency later. The precharge to bank n will begin

when the Read to bank m is registered.

• Figure 26 on page 43 shows a Read with Auto Precharge to Bank n, interrupted by

a Write (with or without Auto precharge) to bank m. The precharge to bank n will

begin when the Write to bank m is registered. D-DM[1:0] should be set high 2 clock

before the Write command to prevent bus contention.

• Figure 27 on page 44 shows a Write with Auto Precharge to Bank n, interrupted by

a Read (with or without Auto precharge) to bank m. The new command initiates

bank n Write recovery (t_WR) followed by precharge. The last valid data-in to bank n

is 1 clock prior to the Read to bank m.

• Figure 28 on page 44 shows a Write with Auto Precharge to Bank n, interrupted by

a Write (with or without Auto precharge) to bank m. The new command initiates

bank n Write recovery (t_WR) followed by precharge. The last valid data-in to bank n

is 1 clock prior to the Write to bank m.

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Datasheet

37

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 9: LPSDRAM Auto-Refresh Cycles with D-CKE High

T0

T1

T2

Tn

Tm

D- CLK

t_RP

t_RFC

Command

Precharge

NOP

Auto Refresh

Active

Figure 10: LPSDRAM Self-Refresh Entry and Exit Mode

T0

T1

T2

Tn

Tm

D-CLK

t_RP

Command

Precharge

NOP

Auto Refresh

NOP

Auto Refresh

t_SREX

D-CKE

t

RAS

>

Figure 11: LPSDRAM Active Command and LPSDRAM Read Access Command Issued to

2 Different Banks

T0

T1

T2

T3

T4

T5

T6

T7

D- CLK

Command

Active

NOP

Read-AP

NOP

Active

NOP

Read-AP

NOP

t_RCD,

Bank 0

Address

Data I/O

Bk0/ Row

Bk 0 / Col a

Bk1/Row

Bk 1 / Col b

t_RRD

Dout - a

Dout – a + 1

Dout – a +2

t

_{RA S,}Bank 0

Figure 12: LPSDRAM Example of D-CAS# Latency, CL = 2

T0

T1

T2

T3

CL=2

D-CLK

Command

Read

NOP

tAC

tLZ

tHZ

tCH

Data I/O

Dout

Datasheet

38

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 13: Consecutive LPSDRAM Read Bursts with CL = 2

T0

T1

T2

T3

T4

T5

T6

D- CLK

Command

Read

NOP

Read

NOP

Address

Data I/O

Bk n / Col a

Bk any / Col b

CL - 1

Dout-a+2

-

Dout - a

Dout-a+1

Dout – a + 3

Dout - b

Note: New command should be issued CL-1 clock cycles before the last desired data. New command can be used to truncate

previous Read Burst.

Figure 14: Random LPSDRAM Read Access with CL = 2

T0

T1

T2

T3

T4

T5

T6

D-CLK

Command

Read

Bk any/Col c

Dout - a

Read

Bk any/Col d

Dout - b

NOP

Bk any/ Col a

Bk any/ Col b

Address

Data I/O

Dout - c

Dout - d

Figure 15: LPSDRAM Read to LPSDRAM Write Command

T0

T1

T2

T3

T4

D -

CLK

D -

DM

Command

Address

Read

NOP

Dout

NOP

Write

Bk any / Col b

Din- b

Bk n / Col a

-

a

Dout - a + 1

Data I/O

Note: Data masking used to prevent I/O contention.

November 2007

317623-15

Datasheet

39

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 16: LPSDRAM Read Command Followed by Precharge

T0

T1

T2

T3

T4

T5

T6

T7

D-CLK

Command

Read

NOP

Precharge

Bk n/all

NOP

Active

Address

Data I/O

Bk n / Col a

Bk/Row

CL - 1

Dout- a+3

Dout - a

Dout – a + 1

Dout – a + 3

CL = 2

Note: Command issued CL-1 clocks before last desired data-out element.

Figure 17: LPSDRAM Read Followed by Burst Terminate

T0

T1

T2

T3

T4

T5

T6

D- CLK

Command

Address

Read

NOP

Brst Term

Bk n / Col a

CL - 1

Dout – a + 2

Dout - a+3

Data I/O

Dout - a

Dout – a + 1

CL =2

Figure 18: Random LPSDRAM Write to 4-Word Bursts

T0

T1

T2

T3

T4

T5

T6

CLK

D-CLK

Command

Address

Write

Bk n / Col a

Din - a

NOP

Write

NOP

Bk any/Col b

-

Data I /O

Din – a + 1

Din – a + 2

Din - a+3

Din - b

Din- b+ 1

Din- b+2

Note: The commands can be to any active bank.

Datasheet

40

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 19: LPSDRAM Write to Precharge Command Where Write Recovery Takes 1 Clock

Cycle

T0

T1

T2

T3

T4

T5

T6

D- CLK

D-DM

Command

Write

Bk n / Col a

Din - a

NOP

Precharge

Bk a / all

NOP

Active

NOP

t_RP

Address

Data I/O

Bk any / Col b

t_WR

Din-a+1

Figure 20: LPSDRAM Write to Precharge Command Where Write Recovery Takes 2 Clock

Cycles

T0

T1

T2

T3

T4

T5

T6

D-CLK

D-DM

Command

Write

Bk n / Col a

Din - a

NOP

Precharge

NOP

Active

t_RP

Address

Data I/O

Bk a / all

Bk any / Col b

t_WR

Din-a+1

Figure 21: LPSDRAM Write Command Followed by LPSDRAM Read Command

T0

T1

T2

T3

T4

T5

CLK

D-CLK

Command

Address

Write

NOP

Read

NOP

Bk n / Col a

Bk any / Col b

Data I /O

Din - a

Din - a +1

Dout - b

Dout - b+1

CL = 2

Note: The Read and Write command can be done to any bank. (CL = 2)

November 2007

317623-15

Datasheet

41

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 22: LPSDRAM Precharge Power-Down Mode

T0

T1

T2

Tn

Tn + 1

CDL-KCLK

D- CKE

Two CLK Cycles

NOP

Command

Precharge

All Banks

NOP

Active

Row

A11

A10

,

D-BA[1:0]

Single Bank

High-Z

Row

Data I/O

Note: All banks are idle with D-CKE low.

Figure 23: LPSDRAM Clock Suspend During LPSDRAM Write Burst

T0

T1

T2

T3

T4

T5

D-CLK

D

CKE

Internal CLK

Command

Address

NOP

Write

Bk n / Col a

Din - a

NOP

Bk any / Col b

Din – a + 1

Data I /O

Din -a + 2

Note: Input data is ignored when internal clock is suspended.

Datasheet

42

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 24: LPSDRAM Clock Suspend During LPSDRAM Read Burst (CL = 2)

T0

T1

T2

T3

T4

T5

T6

D-CLK

CKE

D-CKE

Internal CLK

Command

Read

NOP

Address

Data I/O

Bk n / Col a

Dout - a

Dout-a+1

Dout – a + 2

Dout – a + 3

Note: Output data gets frozen while internal clock is suspended.

Figure 25: LPSDRAM Read with Auto Precharge to Bank n Interrupted by Read to Bank m

T0

T1

T2

T3

T4

T5

T6

D-CLK

Command

Bank n

Bank m

Read -AP

NOP

t_RP, Bank n

Interrupt Burst , Precharge

Read Burst

Idle

Page Active

Bank m

Address

Data I/O

Read Burst

Bk m / Col b

Bk n / Col a

CL=2

Dout - a

Dout - a+1

Dout - b

Dout - b+1

Figure 26: LPSDRAM Read with Auto Precharge to Bank n Interrupted by Write to Bank m

T0

T1

T2

T3

T4

T5

T6

D- CLK

Bank n

Read-AP

Bank m

Write-AP

NO

P

Command

NOP

t

_RP, Bank n

Bank n

Bank m

Address

D-DM

Page Active

Read Burst

Interrupt Burst, Precharge

Page Active

Write Burst

Bk n /Cola

Bk m / Col b

CL=2

Data I/O

Dout - a

Din - b

Din- b+1

Din - b+2

November 2007

317623-15

Datasheet

43

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Figure 27: LPSDRAM Write with Auto Precharge to Bank n Interrupted by Read to Bank m

T0

T1

T 2

T 3

T4

T5

T6

D- CLK

Bank n

Bank m

Command

NOP

Write-AP

Read -AP

t_WR,

t_RP,Bank n

Bank n

Bank m

Active

Write Burst

Interrupt Burst , Write Recovery

Precharge

Page Active

Read Burst ( 4 Word)

Precharge

Bk n / Col a

Bk m / Col b

Address

Data I /O

Din -a

Din – a + 1

Dout - b

Dout – b + 1

Dout – b + 2

Figure 28: LPSDRAM Write with Auto Precharge to Bank n Interrupted by Write to Bank m

T0

T1

T2

T3

T4

T5

T6

DC-LCKLK

Bank n

Bank m

Command

NOP

Write-AP

t_WR,

t

_RP,Bank n

Bank n

Active

Write Burst (4 Word)

Page Active

Interrupt Burst , Write Recovery

Precharge

t

WR,

Bank m

Address

Data I/O

Write Burst (4 Word)

Write Recovery

Bk m / Col b

Din - b

Bk n / Col a

Din - a

Din- b+1

Din- b+2

Din- b+3

Din – a + 1

12.11

LPSDRAM Burst Terminate

This command is used to truncate bursts. The most recent command prior to the burst

terminate command will be truncated.

12.12

LPSDRAM Auto-Refresh

This command is used during normal operation of the LPSDRAM. This command is non-

persistent. All banks must be idle before issuing Auto-Refresh command. This

command can be issued after a minimum of t_RPafter the precharge command. The

address bits are "Don't care" during the Auto-Refresh command. As an example, the

256-Mbit LPSDRAM requires 4096 auto refresh cycles (4096 rows/bank) every 64 ms

(t_REF). Providing a distributed Auto-Refresh command every 15.625 μs will meet the

refresh requirement and ensure that each row is refreshed. Alternatively, 4096 refresh

command cycles can be issued in a burst at a minimum cycle rate (t_RFC), once every 64

ms. Figure 9 on page 38 shows auto refresh cycles.

Datasheet

44

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

12.13

LPSDRAM Self-Refresh

This state retains data in the LPSDRAM, even as the rest of the system is powered

down. The Self-Refresh command is initiated like the auto refresh command, except

the D-CKE is disabled (low). All banks must be idle before this command is issued.

Once the Self-Refresh command is registered, all inputs become "Don't Care" except D-

CKE, which must remain low. The procedure for exiting Self-Refresh mode requires a

series of commands. First clock must be stable before

D-CKE going high. NOP commands should be issued (minimum of 2 clocks) to meet the

refresh exit time (t_SREX) limitation. Figure 10 on page 38 shows self refresh entry and

exit mode.

Appendix A Ordering Information

To order samples, obtain datasheets or inquire about any stack combination, please

contact your local Numonyx representative.

Table 24: 38F Type Stacked Components

PF

38F

5070

M0

Y

0

B

0

Product Die/

Density

Configuration

Voltage/NOR

Flash CE#

Configuration

Parameter /

Mux

Configuration

Package

Designator

Product Line

Designator

NOR Flash Product

Family

Ballout

Identifier

Device

Details

Char 1 = Flash

die #1

V =

0 =

First character

applies to Flash

die #1

1.8 V Core

and I/O;

Separate Chip

Enable per die

Char 2 = Flash

die #2

No parameter

blocks; Non-

Mux I/O

B =

x16D

Ballout

interface

Char 3 =

0 =

PF =

Second character

applies to Flash

die #2

RAM die #1

Original

released

version of

this

SCSP, RoHS

(See

Table 28,

“Voltage /

NOR Flash

CE#

Table 30

Stacked NOR

Table 29,

“Parameter

/ Mux

,

Flash + RAM Char 4 =

RD =

“Ballout

Decoder

” on

(See Table 27,

“NOR Flash

Family

RAM die #2

SCSP, Leaded

product

Configurati

on

Configurati

on

(See

page 48

for details)

Decoder” on

page 47 for

details)

Decoder”

on page 47

for details)

Table 26,

“38F / 48F

Density

Decoder”

onpage 47

for details)

Decoder”

on page 46

for details)

November 2007

317623-15

Datasheet

45

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 25: 48F Type Stacked Components

PC

48F

4400

P0

V

B

0

Product Die/

Density

Configuration

Voltage/NOR

Flash CE#

Configuration

Parameter /

Mux

Configuration

Package

Designator

Product Line

Designator

NOR Flash Product

Family

Ballout

Identifier

Device

Details

PC =

Char 1 = Flash

die #1

Easy BGA,

RoHS

V =

B =

Bottom

parameter;

Non-Mux I/O

interface

First character

applies to Flash

dies #1 and #2

1.8 V Core

and 3 V I/O;

Virtual Chip

Enable

Char 2 = Flash

die #2

0 =

Discrete

Ballout

RC =

Easy BGA,

Leaded

0 =

Char 3 = Flash

die #3

Second character

applies to Flash

dies #3 and #4

Original

released

version of

this

(See

JS =

TSOP, RoHS

(See

Stacked

NOR Flash

only

Table 28,

“Voltage /

NOR Flash

CE#

Table 30

Table 29,

“Parameter

/ Mux

Char 4 = Flash

die #4

,

“Ballout

Decoder

” on

(See Table 27,

“NOR Flash

Family

product

TE =

TSOP, Leaded

Configurati

on

Configurati

on

(See

page 48

for details)

Table 26,

“38F / 48F

Density

Decoder” on

page 47 for

details)

Decoder”

on page 47

for details)

Decoder”

on page 47

for details)

PF =

SCSP, RoHS

Decoder”on

page 46 for

details)

RD =

SCSP, Leaded

Table 26: 38F / 48F Density Decoder

Code

Flash Density

RAM Density

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

No Die

4-Mbit

32-Mbit

64-Mbit

128-Mbit

256-Mbit

512-Mbit

1-Gbit

8-Mbit

16-Mbit

32-Mbit

64-Mbit

128-Mbit

256-Mbit

512-Mbit

1-Gbit

2-Gbit

4-Gbit

8-Gbit

16-Gbit

32-Gbit

64-Gbit

128-Gbit

256-Gbit

512-Gbit

2-Gbit

4-Gbit

8-Gbit

16-Gbit

32-Gbit

64-Gbit

Datasheet

46

November 2007

317623-15

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 27: NOR Flash Family Decoder

Code

Family

Marketing Name

C

C3

Numonyx Advanced+ Boot Block Flash Memory

Numonyx Embedded Flash Memory

Numonyx™ StrataFlash® Wireless Memory

Numonyx™ StrataFlash® Cellular Memory

Numonyx™ StrataFalsh® Embedded Memory

Numonyx™ Wireless Flash Memory

No Die

J3v.D

J

L

L18 / L30

M18

M

P

P30 / P33

W18 / W30

-

W

0(zero)

Table 28: Voltage / NOR Flash CE# Configuration Decoder

I/O Voltage

Code

Core Voltage (Volt)

CE# Configuration

Seperate Chip Enable per die

(Volt)

Z

3.0

1.8

3.0

1.8

3.0

1.8

3.0

1.8

3.0

1.8

3.0

1.8

3.0

Seperate Chip Enable per die

Virtual Chip Enable

Virtual Address

Y

X

V

U

T

R

Q

P

Virtual Address

Table 29: Parameter / Mux Configuration Decoder

Code, Mux

Identification

Number of Flash Die

Bus Width

Flash Die 1

Flash Die 2

Flash Die 3

Flash Die 4

0 = Non Mux

1 = AD Mux¹

2= AAD Mux

Any

NA

Notation used for stacks that contain no parameter blocks

3 =Full" AD

Mux²

1

2

3

4

2

4

Bottom

-

Top

-

B = Non Mux

C = AD Mux

F = "Full" Ad

Mux

X16

X32

Bottom

Top

Bottom

-

Top

-

Bottom

Top

November 2007

317623-15

Datasheet

47

Numonyx™ StrataFlash^®Wireless Memory (L18) with LPSDRAM

Table 29: Parameter / Mux Configuration Decoder

Code, Mux

Identification

Number of Flash Die

Bus Width

Flash Die 1

Flash Die 2

Flash Die 3

Flash Die 4

1

2

3

4

2

4

Top

-

Top

Bottom

Top

T = Non Mux

U = AD Mux

X16

Bottom

Top

W = "Full" Ad

Mux

Bottom

Top

Bottom

-

X32

Top

Bottom

1. Only Flash is Muxed and RAM is non-Muxed

2. Both Flash and RAM are AD-Muxed

Table 30: Ballout Decoder

Code

Ballout Definition

0 (Zero)

SDiscrete ballout (Easay BGA and TSOP)

B

x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus)

x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus)

QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus)

x32SH ballout, 106 ball (x32 NOR only Share Bus)

C

Q

U

V

x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus

x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus

W

Datasheet

48

November 2007

317623-15


型号：	RD38F3362LLYBB0
厂家：	NUMONYX B.V
描述：	Memory Circuit, Flash+SDRAM, PBGA103, 动态存储器内存集成电路
文件：	总48页 (文件大小：865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RD38F3362LLYBB0 [NUMONYX]

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