I91230BYI [NUVOTON]
ISD ARM® Cortex®-M0 SoC;
| 型号： | I91230BYI |
| 厂家： | 
NUVOTON |
| 描述： | ISD ARM® Cortex®-M0 SoC |
| 文件： | 总48页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD91200 Series Datasheet
ISD ARM® Cortex®-M0 SoC
ISD91200 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ChipCorder
microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Release Date: Sep. 19, 2019
- 1 -
Revision V1.3
ISD91200 Series Datasheet
Table of Contents-
TABLE OF CONTENTS- ......................................................................................................................... 2
1
2
GENERAL DESCRIPTION.......................................................................................................... 4
FEATURES ................................................................................................................................. 5
2.1
Selection Guide............................................................................................................. 10
2.1.1 ISD91200RI/CRI/PRI/GRI sereies (non ISD91200B)......................................................10
2.1.2 ISD91200YI/CYI sereies (non ISD91200B) ....................................................................12
2.1.3 91200B series (Bridge Sense)........................................................................................11
3
PART INFORMATION AND PIN CONFIGURATION ............................................................... 13
3.1
Pin Configuration .......................................................................................................... 13
3.1.1 ISD91200 LQFP 64 pin (Normal & C series) ..................................................................13
3.1.2 ISD91200 LQFP 64 pin (P series) ..................................................................................14
3.1.3 ISD91200 LQFP 64 pin (G series)..................................................................................15
3.1.4 ISD91200 LQFP 64 pin (B series) ..................................................................................16
3.1.5 ISD91200 QFN 32 pin (Y series)....................................................................................17
Pin Description.............................................................................................................. 18
3.2
3.2.1 ISD91200RI/CRI/PRI/GRI sereies (non ISD91200B)......................................................18
3.2.2 ISD91200B sereies difference........................................................................................23
3.2.3 ISD91200YI/ISD91200CYI (QFN32)...............................................................................24
4
5
BLOCK DIAGRAM .................................................................................................................... 27
APPLICATION DIAGRAM......................................................................................................... 28
5.1
5.2
5.3
ISD91200RI/CRI/PRI/GRI Series (non ISD91200B)..................................................... 28
ISD91200B Series ........................................................................................................ 29
ISD91200YI/CYI Series (non ISD91200B) ................................................................... 30
6
ELECTRICAL CHARACTERISTICS......................................................................................... 31
6.1
6.2
6.3
Absolute Maximum Ratings .......................................................................................... 31
DC Electrical Characteristics ........................................................................................ 32
AC Electrical Characteristics......................................................................................... 36
6.3.1 External 32kHz XTAL Oscillator .....................................................................................36
6.3.2 Internal 49.152MHz Oscillator ........................................................................................36
6.3.3 Internal 10 kHz Oscillator................................................................................................36
6.3.4 External 12MHz XTAL Oscillator ....................................................................................36
Analog Characteristics.................................................................................................. 37
6.4
6.4.1 Specification of ADC and Speaker Driver.......................................................................37
6.4.2 Specification of PGA.......................................................................................................37
6.4.3 Specification of ALC and MICBIAS.................................................................................38
6.4.4 Specification of LDO and Power Management...............................................................39
6.4.5 Specification of Brownout Detector.................................................................................39
6.4.6 Specification of Power-On Reset (VCCD) ......................................................................40
6.4.7 Specification of Comparator( for capsense)....................................................................41
6.4.8 OP Amplifier Electrical Characteristics ...........................................................................41
6.4.9 Specification of Comparator( for OP)..............................................................................42
Release Date: Sep. 19, 2019
- 2 -
Revision V1.3
ISD91200 Series Datasheet
6.4.10 SARADC Spec................................................................................................................43
PACKAGE DIMENSIONS ......................................................................................................... 44
7
7.1
7.2
64L LQFP (7x7x1.4mm footprint 2.0mm) ..................................................................... 44
QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm .................................... 45
8
9
ORDERING INFORMATION..................................................................................................... 46
REVISION HISTORY ................................................................................................................ 47
IMPORTANT NOTICE........................................................................................................................... 48
Release Date: Sep. 19, 2019
- 3 -
Revision V1.3
ISD91200 Series Datasheet
1 GENERAL DESCRIPTION
The ISD91200 series is a system-on-chip product optimized for low power, audio record and
playback with an embedded ARM® Cortex™-M0 32-bit microcontroller core.
The ISD91200 device embeds a Cortex™-M0 core running up to 50 MHz with 64K/128K byte of
non-volatile flash memory and 12K-byte of embedded SRAM. It also comes equipped with a
variety of peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC),
Peripheral Direct Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C,
I2S), PWM modulators, GPIO, LDO, SDADC, SARADC, DPWM, Low Voltage Detector and
Brown-out detector.
The ISD91200 comes equipped with a rich set of power saving modes including a Deep Power
Down (DPD) mode drawing less than 1µA. A micro-power 10KHz oscillator can periodically wake
up the device from deep power down to check for other events. Standby Power Down (SPD)
mode can maintain a real time clock function with less than 5 µA.
For audio functionality the ISD91200 includes a Sigma-Delta ADC with 91dB SNR performance
coupled with a Programmable Gain Amplifier (PGA with 0-6/12dB gain) and volume control (36dB
to -108dB) in digital domain to enable direct connection of a microphone. Audio output is provided
by a Differential Class D amplifier (DPWM) that can deliver 0.5W of power to an 8Ω speaker.
The ISD91200 provides eight analog enabled general purpose IO pins (GPIO). These pins can be
configured to connect to an analog comparator, can be configured as analog current sources or
can be routed to the SDADC for analog conversion. They can also be used as a relaxation
oscillator to perform capacitive touch sensing.
Release Date: Sep. 19, 2019
- 4 -
Revision V1.3
ISD91200 Series Datasheet
2 FEATURES
•
Core
–
–
–
–
–
ARM® Cortex™-M0 core running up to 50 MHz for normal speed.
One 24-bit System tick timer for operating system support.
Supports a variety of low power sleep and power down modes.
Single-cycle 32-bit hardware multiplier.
NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of
priority.
–
Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints.
•
Power Management
–
–
–
–
Wide operating voltage range from 1.8V to 5.5V.
Power management Unit (PMU) providing four levels of power control.
Deep Power Down (DPD) mode with sub micro-amp leakage (<2µA).
Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from
internal low power 10KHz oscillator.
–
Standby current in SPD mode with limited RAM (256byte SBRAM) retention and RTC
operation <5µA.
–
–
–
–
Standby current in STOP mode with full SRAM retention <10µA.
Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.
Sleep mode with minimal dynamic power consumption.
3V LDO for operation of external 3V devices such as serial flash.
•
Flash EPROM Memory
–
–
–
–
–
–
64K/128K bytes Flash EPROM for program code and data storage.
Mini-cache to maintain near zero-wait state memory access.
Support In-system program (ISP) and In-circuit program (ICP) application code update
512 byte page erase for flash.
Configurable boundary to delineate code and data flash.
Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface
•
•
SRAM Memory
12K bytes embedded SRAM.
Clock Control
–
–
High speed and low speed oscillators providing flexible selection for different applications.
No external components necessary.
–
Built-in trimmable oscillator with range of 16-50MHz. Factory trimmed within 1% to
settings of 49.152MHz and 32.768MHz. User trimmable with in-built frequency
measurement block (OSCFM) using reference clock of 32kHz crystal or external
reference source.
–
Ultra-low power (<1uA) 10kHz oscillator for watchdog and wakeup from power-down or
sleep operation.
–
–
External 32kHz crystal input for RTC function and low power system operation.
External 12 MHz crystal input for precise timing operation.
Release Date: Sep. 19, 2019
- 5 -
Revision V1.3
ISD91200 Series Datasheet
•
GPIO
–
Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
–
–
–
–
–
Schmitt trigger input selectable.
I/O pin can be configured as interrupt source with edge/level setting.
Supports High Driver and High Sink IO mode.
Capacitive Touch: 16
Maximal 32 GPIO
•
Audio Analog to Digital converter (no function in ISD91200B series)
–
–
–
–
–
–
–
Sigma Delta ADC with configurable decimation filter and 16 bit output.
90dB Signal-to-Noise (SNR) performance.
Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
Boost gain stage of 26dB, giving maximum total gain of 61dB.
Input selectable from dedicated MIC pins or analog enabled GPIO.
Programmable biquad filter to support multiple sample rates from 8-32kHz.
DMA support for minimal CPU intervention.
•
Differential Audio PWM Output (DPWM)
–
–
–
–
–
–
Direct connection of speaker
0.5W drive capability into 8Ω load.
Configurable up-sampling to support sample rates from 8-48kHz.
Programmable volume control from -128dB to +36dB in 0.5 dB step
Programmable biquad filter to support multiple sample rates from 8-48kHz
DMA support for minimal CPU intervention.
•
•
Timers
–
–
Two timers with 8-bit pre-scaler and 24-bit resolution.
Counter auto reload.
Watch Dog Timer
–
–
–
–
–
Default ON/OFF by configuration setting
Multiple clock sources
8 selectable time out period from micro seconds to seconds (depending on clock source)
WDT can wake up power down/sleep.
Interrupt or reset selectable on watchdog time-out.
•
RTC
–
–
–
–
–
Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Time tick and alarm interrupts.
Release Date: Sep. 19, 2019
Revision V1.3
- 6 -
ISD91200 Series Datasheet
–
–
Device wake up function.
Supports software compensation of crystal frequency by compensation register (FCR)
•
PWM/Capture
–
Four 16-bit PWM generators provide four single ended PWM outputs or two
complementary paired PWM outputs.
–
The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-
scaler and Dead-Zone generator for complementary paired PWM.
–
–
–
PWM interrupt synchronous to PWM period.
16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
Support Capture interrupt
•
•
UART
–
–
–
–
–
Up to two uart controller
UART ports with flow control (TX, RX, CTS and RTS)
8-byte FIFO.
Support IrDA (SIR) and LIN function
Programmable baud-rate generator up to 1/16 of system clock.
SPI
–
–
–
–
–
–
–
–
–
–
Up to two SPI controller
SPI Clock up to 24 MHz.
SPI data rate in Quad mode up to 98 Mbps
Support MICROWIRE/SPI master/slave mode (SSP)
Full duplex synchronous serial data transfer
Variable length of transfer data from 1 to 4 bytes
MSB or LSB first data transfer
2 slave/device select lines when used in master mode.
DMA support.( 64bit (16x4) data FIFO)
Quad/Dual SPI support.
•
I2C
–
–
–
–
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
–
–
Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
–
–
–
Programmable clock allowing versatile rate control.
Supports multiple address recognition (four slave address with mask option)
Supports wake-up by address recognition (for 1st slave address only)
•
I2S
Release Date: Sep. 19, 2019
- 7 -
Revision V1.3
ISD91200 Series Datasheet
–
–
–
–
–
–
–
–
Interface with external audio CODEC.
Operate as either master or slave.
Capable of handling 8, 16, 24 and 32 bit word sizes
Mono and stereo audio data supported
I2S and MSB justified data format supported
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Supports DMA requests, for transmit and receive
•
SARADC
–
–
–
–
–
–
–
–
12-bit SAR ADC with 700K SPS
Up to 12-ch single-end input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion start by software programming or external input
Supports PDMA mode
•
Bridge Sense ADC (only support in ISD91200B series)
–
–
–
–
On chip calibaration
8 steps Programmable Gain Amplifier (BSPGA)
Programmable data output rate
21 bit precision @ moving average 6.4 SPS
•
•
Low Voltage Reset
Threshold voltage levels: 1.8V
Brown-out detector
–
–
–
–
Supports 8-level brown-out setting.
Supports time-multiplex operation to minimize power consumption.
Supports Brownout Interrupt and Reset option
•
•
Built in Low Dropout Voltage Regulator (LDO)
–
–
–
–
Capable of delivering 30mA load current.
Configurable 8 output voltage selections from 1.5V – 3.3V.
LDO output powers IO ring for GPIOA<7:0> and can supply power to external SPI Flash.
Can be bypassed and voltage domain supplied directly from system power.
Additional Features
–
Over temperature alarm. Can generate interrupt if device exceeds safe operating
temperature.
–
Temperature proportional voltage source which can be routed to ADC for temperature
measurements.
–
–
Digital Microphone interface.
2 Low noise high impedance high working temperature OPAMPs suitable for smoke-
Release Date: Sep. 19, 2019
- 8 -
Revision V1.3
ISD91200 Series Datasheet
detect application.
•
•
•
Standby current in STOP mode with SRAM retention <=10µA at 25°C.
Operating Temperature: -40C~85C
Package:
–
All Green package (RoHS)
LQFP 64-pin
Release Date: Sep. 19, 2019
Revision V1.3
- 9 -
ISD91200 Series Datasheet
2.1 Selection Guide
2.1.1 ISD91200RI/CRI/PRI/GRI sereies (non ISD91200B)
\Part
No ISD91230PR ISD91260CR ISD91230R ISD91260R ISD91230GR ISD91260GR
Featur
I
I
I
I
I
I
e
Flash
SRAM
Data
Flash
LDROM
64K
12K
Configurable
128K
12K
Configurable
64K
12K
Configurabl
128K
12K
Configurabl
64K
12K
Configurable
128K
12K
Configurable
4K
e
e
4K
4K
4K
4K
4K
I/O
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
Timer
UART
SPI
I2C
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
2
1
1
4
I2S
PWM
12-Bit
ADC
V
2
V
2
V
2
V
2
V
2
V
2
ACMP
Bridge
Sense
ADC
Audio
ADC
V
V
V
VR
V
V
DMIC
DPWM
driver
PDMA
V
V
V
V
V
V
4
V
4
V
4
V
4
V
4
V
4
V
ISP/ICP
Package
LQFP64
LQFP64
LQFP64
LQFP64
LQFP64
LQFP64
Release Date: Sep. 19, 2019
Revision V1.3
- 10 -
ISD91200 Series Datasheet
2.1.2 91200B series (Bridge Sense)
\Part No
Feature
ISD91230BRI ISD91260BRI
Flash
SRAM
Data
64K
12K
Configurable
128K
12K
Configurable
Flash
LDROM
4K
4K
I/O
32
2x 32bit
+ 2x 16 bit
2
32
2x 32bit
+ 2x 16 bit
2
Timer
UART
SPI
I2C
2
1
1
4
2
1
1
4
I2S
PWM
12-Bit
ADC
V
2
V
2
ACMP
Bridge
Sense
ADC
V
V
Audio
ADC
VR
DMIC
DPWM
driver
PDMA
V
V
V
V
4
V
4
V
ISP/ICP
Package
LQFP64
LQFP64
Release Date: Sep. 19, 2019
Revision V1.3
- 11 -
ISD91200 Series Datasheet
2.1.3 ISD91200YI/CYI sereies (non ISD91200B)
\Part No
ISD91260CYI ISD91260YI ISD91230YI
Feature
Flash
SRAM
128K
12K
128K
12K
64K
12K
Configurable
Configurable Configurable
Data Flash
LDROM
I/O
4K
4K
4K
15
2x 32bit
+ 2x 16 bit
1
15
2x 32bit
+ 2x 16 bit
1
15
2x 32bit
+ 2x 16 bit
1
Timer
UART
SPI
I2C
1
1
1
2
V
2
1
1
1
2
V
2
1
1
1
2
V
2
I2S
PWM
12-Bit ADC
ACMP
Bridge
Sense ADC
Audio ADC
V
V
V
V
V
V
VR
DMIC
DPWM
driver
PDMA
V
4
V
4
V
4
V
ISP/ICP
QFN32
Package
QFN32
QFN32
Release Date: Sep. 19, 2019
Revision V1.3
- 12 -
ISD91200 Series Datasheet
3 PART INFORMATION AND PIN CONFIGURATION
3.1 Pin Configuration
3.1.1 ISD91200 LQFP 64 pin (Normal & C series)
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOB<6>
GPIOB<5>
GPIOB<4>
GPIOB<3>
GPIOB<2>
GPIOB<1>
GPIOB<0>
VCC
3
NC
VCCA
4
VCCLDO
VLDOx
5
6
GPIOA<0>
GPIOA<1>
GPIOA<2>
GPIOA<3>
GPIOA<4>
GPIOA<5>
GPIOA<6>
GPIOA<7>
VSS
7
8
I91200/I91200C
NC
9
10
11
12
13
14
15
16
VDDL/ VREG
GPIOA<11>
GPIOA<10>
RESETB
ICE_CLK
ICE_DAT
NC
NC
Release Date: Sep. 19, 2019
Revision V1.3
- 13 -
ISD91200 Series Datasheet
3.1.2 ISD91200 LQFP 64 pin (P series)
Basic feature & play-back only
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOB<6>
GPIOB<5>
GPIOB<4>
GPIOB<3>
GPIOB<2>
GPIOB<1>
GPIOB<0>
VCC
3
NC
VCCA
4
VCCLDO
VLDOx
5
6
GPIOA<0>
GPIOA<1>
GPIOA<2>
GPIOA<3>
GPIOA<4>
GPIOA<5>
GPIOA<6>
GPIOA<7>
VSS
7
8
I91200P
NC
9
10
11
12
13
14
15
16
VDDL/ VREG
GPIOA<11>
GPIOA<10>
RESETB
ICE_CLK
ICE_DAT
NC
NC
Release Date: Sep. 19, 2019
Revision V1.3
- 14 -
ISD91200 Series Datasheet
3.1.3 ISD91200 LQFP 64 pin (G series)
Basic feature, no MIC & SPK supported
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOB<6>
GPIOB<5>
GPIOB<4>
GPIOB<3>
GPIOB<2>
GPIOB<1>
GPIOB<0>
VCC
3
NC
VCCA
4
VCCLDO
VLDOx
5
6
GPIOA<0>
GPIOA<1>
GPIOA<2>
GPIOA<3>
GPIOA<4>
GPIOA<5>
GPIOA<6>
GPIOA<7>
VSS
7
8
I91200G
NC
9
10
11
12
13
14
15
16
VDDL/ VREG
GPIOA<11>
GPIOA<10>
RESETB
ICE_CLK
ICE_DAT
NC
NC
Release Date: Sep. 19, 2019
Revision V1.3
- 15 -
ISD91200 Series Datasheet
3.1.4 ISD91200 LQFP 64 pin (B series)
No SDADC but bridge sense ADC supported
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIOB<6>
GPIOB<5>
GPIOB<4>
GPIOB<3>
GPIOB<2>
GPIOB<1>
GPIOB<0>
VCC
3
NC
VCCA
4
VCCLDO
VLDOx
5
6
GPIOA<0>
GPIOA<1>
GPIOA<2>
GPIOA<3>
GPIOA<4>
GPIOA<5>
GPIOA<6>
GPIOA<7>
VSS
7
8
I91200B
NC
9
10
11
12
13
14
15
16
VDDL/ VREG
GPIOA<11>
GPIOA<10>
RESETB
ICE_CLK
ICE_DAT
NC
NC
Release Date: Sep. 19, 2019
Revision V1.3
- 16 -
ISD91200 Series Datasheet
3.1.5 ISD91200 QFN 32 pin (Y series)
32
31
30
29
28
27
26
25
24
23
22
21
PB1
VCCA/VLDOx
PA0
1
2
3
4
PB0
PA1
VCCD
VREG
PA10
RESETN
PA2
I92100Y
QFN32
PA3
20
19
5
6
PA4
18
17
7
8
ICE_CLK
ICE_DAT
PA7
33/EPAD: VSSD
14 15 16
VCCSPK
9
10
11
12
13
Release Date: Sep. 19, 2019
Revision V1.3
- 17 -
ISD91200 Series Datasheet
3.2 Pin Description
The ISD91200 is a low pin count device where many pins are configurable to alternative
functions. All General Purpose Input/Output (GPIO) pins can be configured to alternate functions
as described in the tables below.
3.2.1 ISD91200RI/CRI/PRI/GRI sereies (non ISD91200B)
Pin
Type
LQFP64 Pin Name
Alt CFG Description
1
2
3
4
5
NC
NC
NC
VCCA
VCCLDO
P
P
Analog power supply.
Power supply for LDO, should be connected to VCCD.
LDO regulator output. if used, a 1μF decoupling capacitor must
be placed. If not used then tie to VCCD.
6
VLDOx
P
PA.0
I/O
O
0
1
2
3
0
1
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
General purpose input/output pin; Port A, bit 0
2nd Master In, Slave Out for SPI0 interface
Slave Select Bar 1 for SPI0 interface
Frame Sync Clock for I2S interface
General purpose input/output pin; Port A, bit 1
1st Master Out, Slave In for SPI0 interface
Bit Clock for I2S interface
SPI0_MISO1
SPI0_SSB1
I2S0_FS
7
O
I/O
I/O
O
PA.1
8
9
SPI0_MOSI0
I2S0_BCLK
PA.2
I/O
I/O
I/O
I
General purpose input/output pin; Port A, bit 2
Serial Clock for SPI 0interface
SPI0_SCLK0
DMIC_DAT
I2S0_SDI
PA.3
DMIC data. Not support for G & P series.
Serial Data Input for I2S interface
I
I/O
O
General purpose input/output pin; Port A, bit 3
Slave Select Bar 0 for SPI0 interface
SARADC Trigger
SPI0_SSB0
SARADC_TRIG
I2S0_SDO
PA.4
10
11
12
13
I
O
Serial Data Output for I2S interface
General purpose input/output pin; Port A, bit 4
Master In, Slave Out channel 0 for SPI interface
Transmit channel of UART 0
I/O
O
SPI0_MISO0
UART0_TX
SPI1_MOSI
PA.5
O
O
Master Out, Slave In for SPI1 interface
General purpose input/output pin; Port A, bit 5
2nd Master Out, Slave In for SPI0 interface
Receive channel of UART 0
I/O
O
SPI0_MOSI1
UART0_RX
SP1_SCLK
PA.6
I
I/O
I/O
O
Serial Clock for SPI1 interface
General purpose input/output pin; Port A, bit 6
Transmit channel of UART 0
UART0_TX
I2C0_SDA
SPI1_SSB
I/O
O
Serial Data, I2C interface
Slave Select Bar for SPI1 interface
Release Date: Sep. 19, 2019
- 18 -
Revision V1.3
ISD91200 Series Datasheet
PA.7
I/O
0
1
2
3
General purpose input/output pin; Port A, bit 7
UART0_RX
I2C0_SCL
SPI1_MISO
I
I/O
I
Receive channel of UART 0
Serial Clock, I2C interface
Master In, Slave Out for SPI1 interface
Digital Ground.
14
15
16
17
18
VSSD
NC
P
NC
NC
Power Supply for PWM Speaker Driver. Need VCC connection
for G series.
Positive Speaker Driver Output. Not support for G series.
Ground for PWM Speaker Driver. Need VSS connection for G
19
20
21
VCCSPK
SPKP
P
O
P
VSSSPK
series.
Ground for PWM Speaker Driver. Need VSS connection for G
series.
Negative Speaker Driver Output. Not support for G series.
Power Supply for PWM Speaker Driver. Need VCC connection
for G series.
22
23
24
25
VSSSPK
SPKN
P
O
P
VCCSPK
NC
PA.8
I/O
I/O
O
0
1
2
3
0
1
2
3
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
General purpose input/output pin; Port A, bit 8
Serial Data, I2C interface
I2C0_SDA
UART1_TX
UART0_RTS
PA.9
26
27
28
29
30
31
Transmit channel of UART 1
O
UART 0 Request to Send Output.
I/O
I/O
I
General purpose input/output pin; Port A, bit 9
Serial Clock, I2C interface
I2C0_SCL
UART1_RX
UART0_CTS
I2C0_SDA
PA.12
Receive channel of UART 1
I
UART 0 Clear to Send Input.
I/O
I/O
O
Serial Data, I2C interface
General purpose input/output pin; Port A, bit 12
PWM0CH2 Output.
PWM0CH2
XI12M
I
12MHz Crystal Oscillator Input. Max Voltage 1.8V
General purpose input/output pin; Port A, bit 13
PWM0CH3 Output.
PA.13
I/O
O
PWM0CH3
XO12M
I2C0_SCL
PA.14
O
12MHz Crystal Oscillator Output
I/O
I/O
O
Serial Clock, I2C interface
General purpose input/output pin; Port A, bit 14
Transmit channel of UART 1
UART1_TX
DMIC_CLK
XI32K
IO
I
DMIC clock. Not support for G & P series.
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
General purpose input/output pin; Port A, bit 15
Receive channel of UART 1
PA.15
I/O
I
UART1_RX
MCLK
O
Master clock output for synchronizing external device
32.768kHz Crystal Oscillator Output
XO32K
O
Release Date: Sep. 19, 2019
- 19 -
Revision V1.3
ISD91200 Series Datasheet
32
33
34
35
NC
NC
ICE_DAT
ICE_CLK
I/O
O
Serial Wire Debug port clock pin. Has internal weak pull-up.
Serial Wire Debug port data pin. Has internal weak pull-up.
External reset input. Pull this pin low to reset device to initial
state. Has internal weak pull-up.
36
RESETN
I
PA.10
I/O
O
I
0
1
2
3
0
1
2
3
General purpose input/output pin; Port A, bit 10
PWM0CH0 Output.
PWM0CH0
TM0
37
External input to Timer 0
DPWM_P
PA.11
O
I/O
O
I
Audio PWM positive. Not support for G series.
General purpose input/output pin; Port A, bit 11
PWM0CH1 Output.
PWM0CH1
TM1
38
External input to Timer 1
DPWM_N
O
Audio PWM negative. Not support for G series.
Logic regulator output decoupling pin. A 1μF capacitor
returning to VSSD must be placed on this pin.
39
40
41
VREG
NC
P
Main Digital Supply for Chip. Supplies all IO except analog,
Speaker Driver
VCCD
P
General purpose input/output pin, analog capable; Port B, bit 0.
Triggers external interrupt 0 (EINT0/IRQ2)
Master Out, Slave In for SPI1 interface
Touch scan channel 0
PB.0
I/O
0
1
SPI1_MOSI
CS0
O
AI
AI
42
43
A0P
Operational Amplifier 0 positive input
General purpose input/output pin, analog capable; Port B, bit 1.
Triggers external interrupt 1 (EINT1/IRQ3)
Serial Clock for SPI1 interface
PB.1
I/O
0
1
SP1_SCLK
CS1
I/O
AI
Touch scan channel 1
A0N
AI
Operational Amplifier 0 negative input
General purpose input/output pin, analog capable; Port B, bit 2
Slave Select Bar for SPI1 interface
Touch scan channel 1
PB.2
I/O
O
0
1
SPI1_SSB
CS2
44
AI
A0E
AO
AI
Operational Amplifier 0 output
SAR11
PB.3
SARADC channel 11
I/O
I
0
1
General purpose input/output pin, analog capable; Port B, bit 3
Master In, Slave Out for SPI1 interface
Touch scan channel 3
SPI1_MISO
CS3
45
46
AI
A1P
AI
Operational Amplifier 1 positive input
General purpose input/output pin, analog capable; Port B, bit 4
Frame Sync Clock for I2S interface
Touch scan channel 4
PB.4
I/O
I/O
AI
0
1
I2S0_FS
CS4
A1N
AO
Operational Amplifier 1 negative input
Release Date: Sep. 19, 2019
- 20 -
Revision V1.3
ISD91200 Series Datasheet
PB.5
I/O
I/O
AI
0
1
General purpose input/output pin, analog capable; Port B, bit 5
Bit Clock for I2S interface
I2S0_BCLK
CS5
47
48
49
Touch scan channel 5
A1E
AO
AI
Operational Amplifier 1 output
SARADC channel 10
SAR10
PB.6
I/O
I
0
1
General purpose input/output pin, analog capable; Port B, bit 6
Serial Data Input for I2S interface
Touch scan channel 6
I2S0_SDI
CS6
AI
CNP
AI
Comparator 1 positive input and comparator 2 negative input
SARADC channel 8
SAR8
AI
PB.7
I/O
O
0
1
General purpose input/output pin, analog capable; Port B, bit 7
Serial Data Output for I2S interface
Touch scan channel 7
I2S0_SDO
CS7
AI
C1N
AI
Comparator 1 negative input
SAR9
AI
SARADC channel 9
PB.8
I/O
I/O
I/O
O
0
1
2
3
General purpose input/output pin, analog capable; Port B, bit 8.
Serial Data, I2C interface
I2C0_SDA
I2S0_FS
UART1_RTS
CS8
Frame Sync Clock for I2S interface
UART 1 Request to Send Output.
Touch scan channel 8
50
51
AI
C2P
AI
Comparator 2 positive input
SAR0
AI
SARADC channel 0
PB.9
I/O
I/O
I/O
I
0
1
2
3
General purpose input/output pin, analog capable; Port B, bit 9.
Serial Clock, I2C interface
I2C0_SCL
I2S0_BCLK
UART1_CTS
CS9
Bit Clock for I2S interface
UART 1 Clear to Send Input.
AI
Touch scan channel 9
SAR1
AI
SARADC channel 1
General purpose input/output pin, analog capable; Port B, bit
10
PB.10
I/O
0
CMP1
O
I
1
2
3
Compare 1 Output
I2S0_SDI
UART1_TX
CS10
Serial Data Input for I2S interface
Transmit channel of UART 1
Touch scan channel 10
SARADC channel 2
52
53
O
AI
AI
SAR2
General purpose input/output pin, analog capable; Port B, bit
11
Compare 2 Output
PB.11
I/O
0
CMP2
O
O
I
1
2
3
I2S0_SDO
UART1_RX
CS11
Serial Data Output for I2S interface
Receive channel of UART 1
Touch scan channel 11
AI
Release Date: Sep. 19, 2019
- 21 -
Revision V1.3
ISD91200 Series Datasheet
SAR3
AI
SARADC channel 3
General purpose input/output pin, analog capable; Port B, bit
12
PB.12
I/O
0
SPI0_MISO0
SPI1_MOSI
DMIC_DAT
CS12
I/O
I/O
I
1
2
3
1st Master In, Slave Out for SPI0 interface
Master Out, Slave In for SPI1 interface
DMIC data. Not support for G & P series.
Touch scan channel 12
54
55
56
57
AI
AI
SAR4
SARADC channel 4
General purpose input/output pin, analog capable; Port B, bit
13
1st Master Out, Slave In for SPI0 interface
Serial Clock for SPI1 interface
SARADC Trigger
PB.13
I/O
0
SPI0_MOSI0
SPI1_SCLK
SARADC_TRIG
CS13
I/O
I/O
I
1
2
3
AI
AI
Touch scan channel 13
SAR5
SARADC channel 5
General purpose input/output pin, analog capable; Port B, bit
14
1st Serial Clock for SPI0 interface
Slave Select Bar 1 for SPI1 interface
DMIC clock. Not support for G & P series.
Touch scan channel 14
PB.14
I/O
0
SPI0_SCLK0
SPI1_SSB
DMIC_CLK
CS14
I/O
O
1
2
3
O
AI
AI
SAR6
SARADC channel 6
General purpose input/output pin, analog capable; Port B, bit
15
Slave Select Bar 0 for SPI0 interface
Master In, Slave Out for SPI1 interface
Master clock output for synchronizing external device
Touch scan channel 15
PB.15
I/O
0
SPI0_SSB0
SPI1_MISO
MCLK
O
I/O
O
1
2
3
CS15
AI
SAR7
AI
SARADC channel 7
58
59
VSSA
AP
Ground for analog circuitry.
VMID
O
Mid rail reference. Connect 4.7µF to VSSA.
60
61
62
MICP
VSS_SARADC
MICN
AI
AP
AI
SDADC positive input. Not support for G & P series.
SARADC ground
SDADC negative input. Not support for G & P series.
63
64
NC
MICBIAS
O
Microphone bias output. Still need for SARADC in G & P series.
Note:
•
Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power
Release Date: Sep. 19, 2019
Revision V1.3
- 22 -
ISD91200 Series Datasheet
3.2.2 ISD91200B sereies difference
60
61
62
VSS_SARADC
BSP
AP
AI
SARADC & BSADC ground
Bridge sense positive input
BS band-gap output.
Bridge sense negative input
BS LDO output
VBG
AP
AI
AO
63
64
BSN
MICBIAS
Note:
•
Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power
Release Date: Sep. 19, 2019
Revision V1.3
- 23 -
ISD91200 Series Datasheet
3.2.3 ISD91200YI/ISD91200CYI (QFN32)
Pin
Type
P
P
LQFP64 Pin Name
Alt CFG Description
Analog power supply.
VCCA
1
VLDOx
LDO power plane, internal bonded to VCCA. LDO is no used.
General purpose input/output pin; Port A, bit 0
2nd Master In, Slave Out for SPI0 interface
Slave Select Bar 1 for SPI0 interface
Frame Sync Clock for I2S interface
PA.0
I/O
0
1
2
3
0
1
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
SPI0_MISO1
O
O
2
SPI0_SSB1
I2S0_FS
PA.1
I/O
I/O
O
General purpose input/output pin; Port A, bit 1
1st Master Out, Slave In for SPI0 interface
Bit Clock for I2S interface
3
4
SPI0_MOSI0
I2S0_BCLK
PA.2
I/O
I/O
I/O
I
General purpose input/output pin; Port A, bit 2
Serial Clock for SPI 0interface
SPI0_SCLK0
DMIC_DAT
I2S0_SDI
PA.3
DMIC data. Not support for G & P series.
Serial Data Input for I2S interface
I
I/O
O
General purpose input/output pin; Port A, bit 3
Slave Select Bar 0 for SPI0 interface
SARADC Trigger
SPI0_SSB0
SARADC_TRIG
I2S0_SDO
PA.4
5
6
7
I
O
Serial Data Output for I2S interface
General purpose input/output pin; Port A, bit 4
Master In, Slave Out channel 0 for SPI interface
Transmit channel of UART 0
I/O
O
SPI0_MISO0
UART0_TX
SPI1_MOSI
PA.7
O
O
Master Out, Slave In for SPI1 interface
General purpose input/output pin; Port A, bit 7
Receive channel of UART 0
I/O
I
UART0_RX
I2C0_SCL
SPI1_MISO
I/O
I
Serial Clock, I2C interface
Master In, Slave Out for SPI1 interface
Power Supply for PWM Speaker Driver. Need VCC connection
for G series.
Positive Speaker Driver Output. Not support for G series.
Ground for PWM Speaker Driver. Need VSS connection for G
series.
Negative Speaker Driver Output. Not support for G series.
Power Supply for PWM Speaker Driver. Need VCC connection
for G series.
8
9
VCCSPK
SPKP
P
O
P
10 VSSSPK
11 SPKN
12 VCCSPK
I2C0_SCL
O
P
I/O
I/O
O
3
0
1
2
0
1
Serial Clock, I2C interface
PA.12
13
General purpose input/output pin; Port A, bit 12
PWM0CH2 Output.
PWM0CH2
XI12M
I
12MHz Crystal Oscillator Input. Max Voltage 1.8V
General purpose input/output pin; Port A, bit 13
PWM0CH3 Output.
PA.13
14
I/O
O
PWM0CH3
Release Date: Sep. 19, 2019
- 24 -
Revision V1.3
ISD91200 Series Datasheet
XO12M
I2C0_SCL
PA.14
O
I/O
I/O
O
2
3
0
1
2
3
0
1
2
3
12MHz Crystal Oscillator Output
Serial Clock, I2C interface
General purpose input/output pin; Port A, bit 14
Transmit channel of UART 1
UART1_TX
DMIC_CLK
XI32K
15
16
IO
I
DMIC clock. Not support for G & P series.
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
General purpose input/output pin; Port A, bit 15
Receive channel of UART 1
PA.15
I/O
I
UART1_RX
MCLK
O
Master clock output for synchronizing external device
32.768kHz Crystal Oscillator Output
XO32K
O
17 ICE_DAT
18 ICE_CLK
I/O
O
Serial Wire Debug port clock pin. Has internal weak pull-up.
Serial Wire Debug port data pin. Has internal weak pull-up.
External reset input. Pull this pin low to reset device to initial
state. Has internal weak pull-up.
19 RESETN
I
PA.10
I/O
O
I
0
1
2
3
General purpose input/output pin; Port A, bit 10
PWM0CH0 Output.
PWM0CH0
20
TM0
External input to Timer 0
DPWM_P
O
Audio PWM positive. Not support for G series.
Logic regulator output decoupling pin. A 1μF capacitor
returning to VSSD must be placed on this pin.
Main Digital Supply for Chip. Supplies all IO except analog,
Speaker Driver
General purpose input/output pin, analog capable; Port B, bit 0.
Triggers external interrupt 0 (EINT0/IRQ2)
21 VREG
P
P
22 VCCD
PB.0
I/O
0
1
SPI1_MOSI
CS0
O
AI
AI
Master Out, Slave In for SPI1 interface
Touch scan channel 0
23
A0P
Operational Amplifier 0 positive input
General purpose input/output pin, analog capable; Port B, bit 1.
Triggers external interrupt 1 (EINT1/IRQ3)
Serial Clock for SPI1 interface
PB.1
I/O
0
1
SP1_SCLK
CS1
I/O
AI
24
Touch scan channel 1
A0N
AI
Operational Amplifier 0 negative input
General purpose input/output pin, analog capable; Port B, bit 2
Slave Select Bar for SPI1 interface
Touch scan channel 1
PB.2
I/O
O
0
1
SPI1_SSB
CS2
25
AI
A0E
AO
AI
Operational Amplifier 0 output
SAR11
PB.3
SARADC channel 11
I/O
I
0
1
General purpose input/output pin, analog capable; Port B, bit 3
Master In, Slave Out for SPI1 interface
Touch scan channel 3
SPI1_MISO
CS3
26
27
AI
A1P
AI
Operational Amplifier 1 positive input
Ground for analog circuitry.
VSSA
AP
Release Date: Sep. 19, 2019
- 25 -
Revision V1.3
ISD91200 Series Datasheet
28
VMID
O
Mid rail reference. Connect 4.7µF to VSSA.
29
30
31
32
MICP
VSS_SARADC
MICN
AI
AP
AI
O
SDADC positive input. Not support for G & P series.
SARADC ground
SDADC negative input. Not support for G & P series.
Microphone bias output
MICBIAS
EPAD VSSD
P
Digital power ground
Note:
•
•
Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power
EPAD is VSSD, different power plane as VSSA
Release Date: Sep. 19, 2019
Revision V1.3
- 26 -
ISD91200 Series Datasheet
4 BLOCK DIAGRAM
Debug interface
HIRC Internal Osc.
CLK CTRL
LXT RTC Osc
LIRC low power Osc
HXT Crystal Osc
Embedded Flash
128KB
RAM
12KB
Cortex M0
AHB Lite
Peripherals with PDMA
LDO 3.0V
LDO 1.5V
GPIO
PDMA
AHB to APB bridge
I2C
Flash Mem Controller
SPI0/1
PWM Speaker Driver
System Control/PMU
SDADC
POR
BOD
Timers/PWM
UART0/1
I2S
SARADC
RTC
WDT
Figure 4-1 ISD91200 Block Diagram
Release Date: Sep. 19, 2019
Revision V1.3
- 27 -
ISD91200 Series Datasheet
5 APPLICATION DIAGRAM
5.1 ISD91200RI/CRI/PRI/GRI Series (non ISD91200B)
VCCD
5
41
15
VCCLDO
VCCD
VSSD
0.1uF
47
uF
0.1
uF
11
10
6
9
8
PA.4/SPI0_MISO0
PA.3/SPI0_SSB0
VLDOx
PA.2/SPI0_SCLK0
PA.1/SPI0_MOSI0
VCCD
1uF
19
24
CSB
DO
VCC
VCCSPKL
VCCSPKR
HOLDB
47
uF
0.1
uF
WPB
GND
CLK
DIO
21
22
VSSSPK
VSSSPK
W25Q
20
23
SPK+
SPK-
ISD91200
LQFP64
30
31
XI32K
32.768K
20pF
4.7uF
0.1uF
XO32K
20pF
2.2 KΩ
64
60
MICBIAS
MIC+
39
VREG
MIC
1uF
62
MIC-
0.1uF
2.2 K
Ω
VCCA
4
VCCA
VSSA
59
47
uF
0.1
uF
VMID
58
4.7uF
: Digital ground;
: Analog ground;
Note:
1. For SPI flash quad mode access, disconnect HOLDB & WPB from VDDB, then connect
HOLDB to PA.0 and WPB to PA.5.
2. No MIC function in ISD91200P series
3. No MIC & SPK function in ISD91200G series
Release Date: Sep. 19, 2019
- 28 -
Revision V1.3
ISD91200 Series Datasheet
5.2 ISD91200B Series
VCCD
5
41
VCCLDO
VCCD
0.1uF
47
uF
0.1
uF
15
11
10
6
9
8
VSSD
PA.4/SPI0_MISO0
PA.3/SPI0_SSB0
VLDOx
PA.2/SPI0_SCLK0
PA.1/SPI0_MOSI0
VCCD
1uF
19
24
CSB
DO
VCC
VCCSPKL
VCCSPKR
HOLDB
47
uF
0.1
uF
WPB
GND
CLK
DIO
21
22
VSSSPK
VSSSPK
W25Q
20
23
SPK+
SPK-
ISD91200B
LQFP64
30
31
XI32K
32.768K
20pF
4.7uF
XO32K
20pF
64
61
MICBIAS
BSP
39
VREG
1uF
63
BSN
VCCA
62
59
4
Sensor
VBG
VCCA
VSSA
47
uF
0.1
uF
4.7uF
VMID
58
VSS_SARADC
60
4.7uF
: Digital ground;
: Analog ground;
Release Date: Sep. 19, 2019
Revision V1.3
- 29 -
ISD91200 Series Datasheet
5.3 ISD91200YI/CYI Series (non ISD91200B)
VCCD
VCCA
22
33
VCCD
VSSD
1
VCCA/VLDOx
VSSA
47
uF
0.1
uF
47
uF
0.1
uF
27
VCCD
12
8
6
5
PA.4/SPI0_MISO0
PA.3/SPI0_SSB0
VCCSPK
VCCSPK
47
uF
0.1
uF
4
3
10
1uF
PA.2/SPI0_SCLK0
PA.1/SPI0_MOSI0
VSSSPK
CSB
DO
VCC
HOLDB
WPB
GND
CLK
DIO
9
SPK+
SPK-
W25Q
11
ISD91200
QFN32
15
16
XI32K
32.768K
20pF
4.7uF
0.1uF
XO32K
20pF
1uF
2.2 KΩ
32
29
MICBIAS
MIC+
21
VREG
MIC
31
MIC-
0.1uF
2.2 K
Ω
28
VMID
4.7uF
: Digital ground;
: Analog ground;
Release Date: Sep. 19, 2019
Revision V1.3
- 30 -
ISD91200 Series Datasheet
6 ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
Input Voltage
PARAMETER
MIN
-0.3
MAX
+6.0
UNIT
V
VDD−VSS
VIN
VSS-0.3
VDD+0.3
V
Oscillator Frequency
1/tCLCL
TA
0
40
MHz
Operating Temperature
-40
+85
°C
Storage Temperature
TST
-55
-
+150
120
120
35
°C
Maximum Current into VDD
Maximum Current out of VSS
mA
mA
mA
Maximum Current sunk by a
I/O pin
Maximum Current sourced by
a I/O pin
35
mA
mA
mA
Maximum Current sunk by
total I/O pins
100
100
Maximum Current sourced by
total I/O pins
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
.
Release Date: Sep. 19, 2019
Revision V1.3
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ISD91200 Series Datasheet
6.2 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25°C, FOSC = 49.152 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operation voltage
VDD
1.8
5.5
V
VDD =1.8V ~ 5.5V up to 50 MHz
VSS
Power Ground
-0.3
-10%
1.8
V
V
V
V
AVSS
LDO Output Voltage
Analog Operating Voltage
Analog Reference Voltage
VLDO
AVDD
Vref
1.5
+10%
VDD
VDD > 1.8V
Note: SDADC & SARADC performance
start degraded when AVDD <2.4V
0
AVDD
V
DD= 5.5V@50Mhz,
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
50
33
45
27
22
15
20
12
mA
mA
mA
mA
mA
mA
mA
mA
enable all IP, XTAL=12MHz
V
DD=5.5V@50Mhz,
Operating Current
Normal Run Mode
@ 50Mhz
disable all IP, XTAL=12MHz
V
DD = 3V@50Mhz,
enable all IP, XTAL=12MHz
V
DD = 3V@50Mhz,
disable all IP , XTAL=12MHz
V
DD = 5.5V@12Mhz,
enable all IP a, XTAL=12MHz
V
DD = 5.5V@12Mhz,
Operating Current
Normal Run Mode
@ 12Mhz
disable all IP XTAL=12MHz
V
DD = 3V@12Mhz,
enable all IP, XTAL=12MHz
V
DD = 3V@12Mhz,
disable all IP, XTAL=12MHz
Release Date: Sep. 19, 2019
Revision V1.3
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ISD91200 Series Datasheet
V
DD = 5V@4Mhz,
IDD9
IDD10
IDD11
IDD12
IIDLE1
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
IIDLE11
IIDLE12
5.8
4.2
5.1
3.6
35
15
34
13
14
5
MA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Enable All IP, XTAL=4MHz
V
DD = 5V@4Mhz,
Operating Current
Normal Run Mode
@ 4Mhz
disable all IP, XTAL=4MHz
V
DD = 3V@4Mhz,
enable all IP, XTAL=4MHz
V
DD = 3V@4Mhz,
disable all IP, XTAL=4MHz
V
DD= 5.5V@50Mhz,
enable all IP, XTAL=12MHz
V
DD=5.5V@50Mhz,
Operating Current
Idle Mode
disable all IP, XTAL=12MHz
V
DD = 3V@50Mhz,
@ 50Mhz
enable all IP, XTAL=12MHz
V
DD = 3V@50Mhz,
disable all IP a XTAL=12MHz
V
DD = 5.5V@12Mhz,
enable all IP XTAL=12MHz
V
DD = 5.5V@12Mhz,
Operating Current
Idle Mode
disable all IP XTAL=12MHz
V
DD = 3V@12Mhz,
@ 12Mhz
12
4
enable all IP, XTAL=12MHz
V
DD = 3V@12Mhz,
disable all IP, XTAL=12MHz
V
DD = 5V@4Mhz,
3.4
1.8
2.8
1.2
enable all IP XTAL=4MHz
V
DD = 5V@4Mhz,
Operating Current
Idle Mode
disable all IP XTAL=4MHz
V
DD = 3V@4Mhz,
@ 4Mhz
enable all IP, XTAL=4MHz
V
DD = 3V@4Mhz,
disable all IP, XTAL=4MHz
Release Date: Sep. 19, 2019
Revision V1.3
- 33 -
ISD91200 Series Datasheet
Supply Current at STOP Mode
(special characteristic)
ISTOP
ISPD
10
5
XTAL32K ON; RTC OFF; NO LOAD
µA
µA
Supply Current at Standby Power
Down Mode
XTAL32K ON; RTC ON; NO LOAD
XTAL32K ON; RTC OFF; NO LOAD
Supply Current at Deep Sleep
Supply Current Sleep Mode
IDSLP
ISLP
200
6
µA
mA
Supply Current at Deep Power
Down Mode
IDPD
IIN1
2
-
Wakeup with Wakeup Pin
µA
µA
Input Current PA, PB, (Quasi-
bidirectional mode)
-75
+15
VDD = 5.5V, VIN = 0V or VIN=VDD
Input Current at /RESET [1]
IIN2
ILK
-75
-2
-45
-
-30
+2
VDD = 3.3V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
µA
µA
Input Leakage Current PA, PB,
Logic 1 to 0 Transition Current
PA~PB (Quasi-bidirectional mode)
[3]
ITL
-650
-
-200
VDD = 5.5V, VIN<2.0V
µA
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
VDD = 5.5V
VDD =3.0V
VDD = 4.5V
VDD = 3.0V
VDD = 5.5V
VDD = 3.0V
Input Low Voltage PA, PB (TTL
input)
VIL1
VIH1
VIL3
VIH3
V
VDD +0.2
VDD +0.2
0.8
Input High Voltage PA, PB (TTL
input)
V
Input Low Voltage XT1[*2]
V
V
0
0.4
3.5
2.4
0
VDD +0.2
VDD +0.2
0.4
Input High Voltage XT1[*2]
Input Low Voltage X32I[*2]
Input High Voltage X32I[*2]
VIL4
VIH4
V
V
1.7
2.5
Negative going threshold
(Schmitt input), /REST
VILS
-0.5
-
0.3VDD
V
Positive going threshold
(Schmitt input), /REST
VIHS
0.7VDD
-
VDD+0.5
V
V
Hysteresis voltage of
PA~PB(Schmitt input)
VHY
0.2VDD
Release Date: Sep. 19, 2019
Revision V1.3
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ISD91200 Series Datasheet
ISR11
ISR12
ISR12
ISR21
ISR22
-300
-50
-40
-20
-4
-370
-70
-60
-24
-6
-450
-90
-80
-28
-8
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
µA
µA
µA
Source Current PA, PB, Quasi-
Bidirectional Mode)
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
Source Current PA, PB (Push-pull
Mode)
ISR22
ISK1
ISK1
ISK1
-3
10
7
-5
16
10
9
-7
20
13
12
mA VDD = 2.5V, VS = 2.0V
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
mA VDD = 2.5V, VS = 0.45V
Sink Current PA, PB (Quasi-
bidirectional and Push-pull Mode)
6
Brownout voltage with
BOV_VL [1:0] =00b
VBO2.2
VBO2.7
VBO3.8
2.1
2.6
3.7
2.2
2.7
3.8
2.3
2.8
3.9
V
V
V
Brownout voltage with
BOV_VL [1:0] =01b
Brownout voltage with
BOV_VL [1:0] =10b
Brownout voltage with
BOV_VL [1:0] =11b
VBO4.5
VBH
4.4
30
4.5
-
4.6
V
Hysteresis range of BOD voltage
150
mV VDD = 2.5V~5.5V
Notes:
1. /REST pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, 5he transition current
reaches its maximum value when Vin approximates to 2V.
Release Date: Sep. 19, 2019
- 35 -
Revision V1.3
ISD91200 Series Datasheet
6.3 AC Electrical Characteristics
6.3.1 External 32kHz XTAL Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Input clock frequency
External crystal
-
32.768
-
kHz
Temperature
VDD
-
-
-40
2.4
-
-
85
℃
5.5
V
6.3.2 Internal 49.152MHz Oscillator
PARAMETER
Supply voltage
CONDITION
MIN.
TYP.
MAX.
UNIT
-
1.8
-
-
5.5
V
MHz
%
Center Frequency
-
49.152
Calibrated Internal Oscillator
Frequency
-0.5
-2.0
-
-
0.5
1.0
+25°C; VDD =3V
-40°C~+85°C;
%
VDD=2.4V~5.5V
6.3.3 Internal 10 kHz Oscillator
PARAMETER
Supply voltage
CONDITION
MIN.
TYP.
MAX.
UNIT
-
1.8
-
-
10
-
5.5
-
V
kHz
%
Center Frequency
-
Calibrated Internal Oscillator
Frequency
-10
-20
10
20
+25°C; VDD =3V
-40°C~+85°C;
-
%
VDD=2.4V~5.5V
.
6.3.4 External 12MHz XTAL Oscillator
PARAMETER
Input clock frequency
Temperature
CONDITION
MIN.
-
TYP.
MAX.
-
UNIT
MHz
℃
External crystal
12
-
-
-
-40
1.8
85
VDD
-
5.5
V
Release Date: Sep. 19, 2019
Revision V1.3
- 36 -
ISD91200 Series Datasheet
6.4 Analog Characteristics
6.4.1 Specification of ADC and Speaker Driver
Conditions: VCCD = 3.3V, VCCA = 3.3V, TA = +25°C, 1kHz signal, fs = 48kHz, 16-bit audio data, unless
otherwise stated.
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Analog to Digital Converter (SDADC)
Full scale input signal 1
VINFS
SNR
PGAGAIN = 0dB
0.85
Vrms
-1.41
dBV
Signal-to-noise ratio
Gain = 0dB, A-weighted
tbd
95
dB
Total harmonic distortion 2
THD+N Input = -3dB FS input
-85
tbd
dB
PWM Speaker Output (8Ω bridge-tied-load)
Full scale output 4
VCCSPK / 3.3
53
Vrms
dB
Total harmonic distortion 2
THD+N Po= 200mW, VDDSPK=3.3V
Po=
320mW,
500mW,
1000mW,
dB
VDDSPK = 3.3V
Po=
-56
dB
dB
dB
VDDSPK = 5V
Po=
VDDSPK = 5V
Signal-to-noise ratio
SNR
VDDSPK = 3.3V
VDDSPK=5V
80
80
dB
Power
(50Hz - 22kHz)
supply
rejection
ratio
PSRR
VDDSPK = 3.3V
VDDSPK = 5V
70
72
dB
dB
6.4.2 Specification of PGA
Conditions: VCCD = 3.3V, VCCA = 3.3V, Vldo=1.5V TA = +25°C, 1kHz signal, fs = 48kHz, 16-bit audio data,
unless otherwise stated.
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Microphone Inputs (MICP, MICN) and Programmable Gain Amplifier (PGA)
Full scale input signal 1
Programmable gain
PGAGAIN = 0dB
0.85
Vrms
-1.41
dBV
Low impedance mode
High impedance mode
0
6
6
dB
dB
12
Release Date: Sep. 19, 2019
Revision V1.3
- 37 -
ISD91200 Series Datasheet
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
dB
Programmable gain step size
Mute Attenuation
Guaranteed Monotonic
6
120
dB
Input resistance, each input pin
Low impedance mode
High impedance mode
12
kΩ
kΩ
500
Input capacitance
10
pF
PGA equivalent input noise
0 to 20kHz, 0dB gain, low
impedance mode
8.5
µVrms
6.4.3 Specification of ALC and MICBIAS
Conditions: VCCD = 3.3V, VCCA = 3.3V, TA = +25°C, 1kHz signal, fs = 10kHz, 16-bit audio data, unless
otherwise stated.
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Automatic Level Control (ALC) & Limiter:
Target record level
-22.5
-12
-1.5
35.25
dBFS
Programmable gain
dB
ms
Gain hold time 3
tHOLD
Doubles every gain step, with
16 steps total
0 / 2.67 / 5.33 / … / 43691
Gain ramp-up (decay) 3
tDCY
ALC Mode
ALC = 0
4 / 8 / 16 / … / 4096
ms
ms
ms
ms
dB
Limiter Mode
ALC = 1
1 / 2 / 4 / … / 1024
1 / 2 / 4 / … / 1024
0.25 / 0.5 / 1 / … / 128
120
Gain ramp-down (attack) 3
tATK
ALC Mode
ALC = 0
Limiter Mode
ALC = 1
Mute Attenuation
Microphone Bias
Mic Bias voltage
VMICBIAS
Gain settings
1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7,
1.8,
Vldo
V
1.5, 1.8, 1.95, 2.1, 2.25, 2.4,
2.55, 2.7
Output voltage
Maximum output current
Output noise voltage
IMICBIAS
Vn
3
mA
1kHz to 20kHz
46
nV/√Hz
Notes
1. Full Scale is relative to the magnitude of Vldo
.
2. Distortion is measured in the standard way as the combined quantity of distortion products plus noise.
The signal level for distortion measurements is at 3dB below full scale, unless otherwise noted.
Release Date: Sep. 19, 2019
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Revision V1.3
ISD91200 Series Datasheet
3. Time values scale proportionally with HCLK. Complete descriptions and definitions for these values
are contained in the detailed descriptions of the ALC functionality.
6.4.4 Specification of LDO and Power Management
PARAMETER
MIN
TYP
MAX
UNIT
NOTE
Input Voltage
1.8
5
5.5
V
V
VDD input voltage
VDD > 1.8V
Output Voltage
(bypass=0)
-10%
1.5
+10%
Temperature
-40
-
25
85
-
°C
Quiescent Current
(PD=0, bypass=0)
100
uA
Quiescent Current
(PD=1, bypass=0)
-
5
-
uA
Iload (PD=0)
Iload (PD=1)
Cbp
-
-
-
-
-
-
100
mA
uA
F
100
1u
-
-
Resr=1ohm
Cload
250p
F
Note:
1.
It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected
between VCCD and the VSSD pin of the device.
2. To ensure regulator stability, a 1.0uF capacitor must be connected between LDO pin and the VSSD
pin of the device. Also a 100nF bypass capacitor between LDO and VSSD will help suppress
output noise.
6.4.5 Specification of Brownout Detector
PARAMETER
CONDITION
-
MIN.
TYP.
MAX.
UNIT
V
Operation voltage
1.8
-
5.5
Quiescent current
Temperature
AVDD=5.5V
-
-
125
85
μA
℃
V
-40
25
-
4.6
4.2
3.9
3.7
3.6
BOV_VL[3:0]=1111
BOV_VL [3:0]=1110
BOV_VL [3:0]=1101
BOV_VL [3:0]=1100
BOV_VL [3:0]=1011
V
V
Brown-out voltage
V
V
Release Date: Sep. 19, 2019
Revision V1.3
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ISD91200 Series Datasheet
3.4
3.1
3.0
2.8
2.6
2.4
2.2
2.1
2.0
1.9
1.8
BOV_VL [3:0]=1010
BOV_VL [3:0]=1001
BOV_VL [3:0]=1000
BOV_VL [3:0]=0111
BOV_VL [3:0]=0110
BOV_VL [3:0]=0101
BOV_VL [3:0]=0100
BOV_VL [3:0]=0011
BOV_VL [2:0]=0010
BOV_VL [3:0]=0001
BOV_VL [2:0]=0000
-
V
V
V
V
V
V
V
V
V
V
V
Hysteresis
40
130
mV
6.4.6 Specification of Power-On Reset (VCCD)
PARAMETER
Temperature
CONDITION
-
MIN.
TYP.
25
MAX.
UNIT
℃
-40
85
Reset Release voltage
Quiescent current
VCC ramping up
Vin>reset voltage
1.5
60
V
-
-
nA
Release Date: Sep. 19, 2019
Revision V1.3
- 40 -
ISD91200 Series Datasheet
6.4.7 Specification of Comparator( for capsense)
PARAMETER
Temperature
MIN.
TYP.
25 ℃
3
MAX.
85℃
5.5
Condition
-40℃
-
VCCA
1.8
-
VCCA current
-
20uA
5mV
-
40uA
15mV
VDD-1.2
-
20uA@VDD=3V
Input offset voltage
Input common mode range
DC gain
-
0.1
-
-
-
70dB
200ns
-
Propagation delay
-
-
@VCM=1.2V & VDIFF=0.1V
20mV@VCM=1V
50mV@VCM=0.1V
Comparison voltage
10mV
20mV
-
50mV@VCM=VDD-1.2
@10mV for non-hysteresis
One bit control
Hysteresis
-
-
±10mV
-
-
W/O & W. hysteresis
@VCM=0.4V ~ VDD-1.2V
@CINP=1.3V
CINN=1.2V
Wake up time
2us
6.4.8 OP Amplifier Electrical Characteristics
Conditions: VCCD = 5.0V, VCCA = 5.0V, TA = +25°C,
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
D.C. Characteristic
Operating voltage
Quiescent current
Vdd
Idd
-
-
1.8
-
5.5
V
5V
No load, A0OEN/A1OEN fixed
to 0
-
200
350
uA
Input offset voltage
Input offset current
Vopos
Iopos
5V
-
-
-2
-
-
+2
-
mV
nA
VDD=5V, VCM=1/2VDD, Ta=-
40~85C
10
Release Date: Sep. 19, 2019
Revision V1.3
- 41 -
ISD91200 Series Datasheet
Parameter
Symbol
Comments/Conditions
Min
Vss
Typ
Max
Vdd-
Units
Common Mode Voltage Range
Vcm
-
-
-
V
1.4
Power Supply Rejection Ratio
Common Mode Rejection Ratio
PSRR
CMRR
-
-
-
58
58
80
-
dB
dB
VDD=5V, VCM=0~VDD-1.4V
80
-
A.C. Characteristic
Open Loop Gain
Slew Rate+, Rate
Gain Band Width
Aol
SR
-
-
-
-
60
-
80
-
-
-
dB
No load
0.1
V/us
MHz
GBW
RL=1MΩ, CL=100pF
1
Notes
6.4.9 Specification of Comparator( for OP)
PARAMETER
Temperature
VCCA
MIN.
-40℃
1.8
TYP.
25 ℃
3
MAX.
85℃
5.5
Condition
-
-
VCCA current
-
20uA
40uA
20uA@VDD=3V
-
Comparator 1 Input offset
voltage
10mV
4mV
Comparator 2 Input offset
voltage
-
Input common mode range
DC gain
0.1
-
VDD-1.2
-
-
-
-
80dB
200ns
-
-
Propagation delay
@VCM=1.2V & VDIFF=0.1V
20mV@VCM=1V
50mV@VCM=0.1V
Comparison voltage
10mV
20mV
-
50mV@VCM=VDD-1.2
@10mV for non-hysteresis
One bit control
Hysteresis
-
-
±10mV
-
-
W/O & W. hysteresis
@VCM=0.4V ~ VDD-1.2V
@CINP=1.3V
CINN=1.2V
Wake up time
2us
Release Date: Sep. 19, 2019
Revision V1.3
- 42 -
ISD91200 Series Datasheet
6.4.10 SARADC Spec
Conditions: VCCD = 5.0V, VCCA = 5.0V, TA = +25°C,
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Bit
Resolution
3V
3V
3V
3V
3V
3V
12
Differential nonlinearity error
Integral nonlinearity error
Offset error
DNL
INL
EO
EG
-
-
-1 ~ 2
-1 ~ 4
LSB
LSB
LSB
-
-
-
-
-
2
1
1
-
4
10
Gain error (Transfer gain)
Monotonic
1.005
-
-
SARADC clock frequency (AVDD =
5V/3V)
Fadc
3V
-
-
10
Mhz
Sample rate
Fs
Vdda
Idd
3V
3V
3V
3V
3V
-
1.8
-
-
-
700
5.5
KSPS
V
Supply voltage
Supply current (Avg.)
0.5
0.5
-
mA
mA
V
Idda
Vref
Iref
-
Reference voltage
Reference current (Avg.)
Input voltage
3
Vdda
Vref
-
0.5
-
mA
V
Vin
0
Release Date: Sep. 19, 2019
Revision V1.3
- 43 -
ISD91200 Series Datasheet
7 PACKAGE DIMENSIONS
7.1 64L LQFP (7x7x1.4mm footprint 2.0mm)
Release Date: Sep. 19, 2019
Revision V1.3
- 44 -
ISD91200 Series Datasheet
7.2 QFN 32L 4X4 mm2, Thickness: 0.8mm (Max), Pitch: 0.40mm
Release Date: Sep. 19, 2019
Revision V1.3
- 45 -
ISD91200 Series Datasheet
8 ORDERING INFORMATION
I9 1x x x x x x
Temperature
ISD Audio Product Family
I: -40°C ~ +85°C
Product Series
1: Cortex-M0
Package
R: LQFP-64
Y: QFN-32
Family ID
2: Family Series ID
Feature
Blank: Standard
Flash ROM
C: Voice Recognition
P: SARADC, playback-only
G: Basic feature set
B: Bridge Sense
3: 64KB
6: 128KB
SRAM
0: 12KB
Release Date: Sep. 19, 2019
Revision V1.3
- 46 -
ISD91200 Series Datasheet
9 REVISION HISTORY
VERSION
DATE
DESCRIPTION
NOTE
V0.12
Aug 24, 2017
–
–
–
–
–
–
–
–
–
–
–
Preliminary Release.
V0.13
Oct 25, 2017
Some DC current change. Add SARADC characteristic
Add analog pin function in pin description section
Add part for ordering information
V0.14
Dec 19,2017
Add pin diagram for P & G series
Modify ADC maximum SPS to 700K
Add Selection Guide
V0.15
V0.16
V0.17
Feb. 13, 2018
Mar. 14, 2018
Apr. 13, 2018
Modify ADC maximum SPS to 700K in future
Add note for ADC performance degrade when power <2.4V
Modify SARADC up to 12 channels in Features
Add ISD91200B series
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Add 21 bit precision in Bridge Sense feature
Add ISD91200B in Order Information
Add QFN32 related
V0.18
July. 3, 2018
V1.0
V1.1
V1.2
Sep. 4, 2018
Oct. 29, 2018
Mar. 19, 2019
Modify QFN32 IO quantity to 15 in selection guide
Revise PA12 share pin function from I2C SCL to I2C SDA
Changed cover title
V1.3
Sep. 16, 2019
Changed content of I91200 to ISD91200
Release Date: Sep. 19, 2019
Revision V1.3
- 47 -
ISD91200 Series Datasheet
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as
components in systems or equipment intended for surgical implantation, atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic
signal instruments, combustion control instruments, or for other applications intended to
support or sustain life. Furthermore, Nuvoton products are not intended for applications
wherein failure of Nuvoton products could result or lead to a situation where personal
injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at
their own risk and agree to fully indemnify Nuvoton for any damages resulting from such
improper use or sales.
Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this datasheet belong to their
respective owners.
Release Date: Sep. 19, 2019
- 48 -
Revision V1.3
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