I94123PDI [NUVOTON]
ISD ARM® Cortex®-M4F SoC;
| 型号： | I94123PDI |
| 厂家： | 
NUVOTON |
| 描述： | ISD ARM® Cortex®-M4F SoC |
| 文件： | 总109页 (文件大小：3404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD94100 Series Datasheet
ISD ARM® Cortex®-M4F SoC
ISD94100 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of microcontroller based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sep 09, 2019
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Rev1.13
ISD94100 Series Datasheet
TABLE OF CONTENTS
1
2
GENERAL DESCRIPTION ..............................................................8
FEATURES ................................................................................9
ISD94100 Series Features .................................................................. 9
ABBREVIATIONS....................................................................... 15
Abbreviations ................................................................................ 15
PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 17
Parts Information............................................................................ 17
Ordering Information ....................................................................... 18
Pin Configuration............................................................................ 20
2.1
3.1
3
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
QFN48 (6x6 mm) Pin Diagram ...................................................................20
LQFP64 (7x7 mm) Pin Diagram ..................................................................21
LQFP64 (10x10 mm) Pin Diagram...............................................................22
Pin Description .............................................................................. 23
GPIO Alternate Function Summary...................................................... 32
4.4
4.5
5
6
BLOCK DIAGRAM ...................................................................... 34
ISD94100 Series Block Diagram ......................................................... 34
FUNCTIONAL DESCRIPTION........................................................ 35
ARM® Cortex®-M4 Core.................................................................... 35
System Manager............................................................................ 38
5.1
6.1
6.2
6.2.1
6.2.2
Overview .............................................................................................38
System Reset........................................................................................38
System Power Distribution ........................................................................38
System Memory Map...............................................................................39
SRAM Memory Organization .....................................................................40
System Timer (SysTick) ...........................................................................43
Nested Vectored Interrupt Controller (NVIC) ...................................................44
Clock Controller ............................................................................. 48
Overview .............................................................................................48
Clock Generator.....................................................................................50
System Clock and SysTick Clock ................................................................51
Peripheral Clock ....................................................................................52
Power-down Mode Clock ..........................................................................53
Clock Output.........................................................................................53
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
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6.4
Flash Memory Controller (FMC).......................................................... 54
Overview .............................................................................................54
Features..............................................................................................54
General Purpose I/O (GPIO).............................................................. 55
Overview .............................................................................................55
Features..............................................................................................55
PDMA Controller (PDMA) ................................................................. 56
Overview .............................................................................................56
Features..............................................................................................56
Timer Controller (TMR) .................................................................... 57
Overview .............................................................................................57
Features..............................................................................................57
PWM Generator and Capture Timer (PWM) ........................................... 59
Overview .............................................................................................59
Features..............................................................................................59
Watchdog Timer (WDT).................................................................... 61
Overview .............................................................................................61
Features..............................................................................................61
Window Watchdog Timer (WWDT) ...................................................... 62
Overview ..........................................................................................62
Features ...........................................................................................62
Real Time Clock (RTC) .................................................................... 63
Overview ..........................................................................................63
Features ...........................................................................................63
UART Interface Controller (UART)....................................................... 64
Overview ..........................................................................................64
Features ...........................................................................................64
I2C Serial Interface Controller (I2C) ...................................................... 66
Overview ..........................................................................................66
Features ...........................................................................................66
Serial Peripheral Interface (SPI).......................................................... 67
Overview ..........................................................................................67
Features ...........................................................................................67
CRC Controller (CRC) ..................................................................... 69
Overview ..........................................................................................69
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.12
6.12.1
6.12.2
6.13
6.13.1
6.13.2
6.14
6.14.1
6.14.2
6.15
6.15.1
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6.15.2
Features ...........................................................................................69
Enhanced 12-bit Analog-to-Digital Converter (EADC) ................................ 70
Overview ..........................................................................................70
Features ...........................................................................................70
I2S Controller (I2S) .......................................................................... 71
Overview ..........................................................................................71
Features ...........................................................................................71
USB 1.1 Device Controller (USBD) ...................................................... 72
Overview ..........................................................................................72
Features ...........................................................................................72
Digital Microphone Inputs (DMIC)........................................................ 73
Overview ..........................................................................................73
Features ...........................................................................................73
Voice Active Detection (VAD)............................................................. 74
Overview ..........................................................................................74
Features ...........................................................................................74
Audio DPWM Modulator (DPWM)........................................................ 75
Overview ..........................................................................................75
Features ...........................................................................................75
6.16
6.16.1
6.16.2
6.17
6.17.1
6.17.2
6.18
6.18.1
6.18.2
6.19
6.19.1
6.19.2
6.20
6.20.1
6.20.2
6.21
6.21.1
6.21.2
7
ELECTRICAL CHARACTERISTICS ................................................. 76
Absolute Maximum Ratings ............................................................... 76
7.1
7.1.1
7.1.2
Voltage Characteristics ............................................................................76
Current Characteristics ............................................................................76
Thermal Characteristics ...........................................................................76
Electrostatic Discharge (ESD) Ratings ..........................................................77
General Operating Conditions ............................................................ 78
DC Electrical Characteristics.............................................................. 79
AC Electrical Characteristics.............................................................. 88
External High Speed Crystal (HXT) Characteristics...........................................88
Internal High Speed RC Oscillator (HIRC) Characteristics...................................89
External Low Speed Crystal (LXT) Characteristics............................................89
Internal Low Speed RC Oscillator (LIRC) Characteristics....................................90
Analog Characteristics ..................................................................... 91
12-bit SARADC......................................................................................91
LDO ...................................................................................................93
7.1.3
7.1.4
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.5.2
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7.5.3
7.5.4
Low Voltage Reset and Brown-out Detector ...................................................93
Power-on Reset.....................................................................................93
USB Characteristics ........................................................................ 95
USB Full-Speed Characteristics..................................................................95
USB Full-Speed PHY Characteristics ...........................................................95
USB VBUS Characteristics........................................................................95
VAD Characteristics ........................................................................ 96
Flash DC Electrical Characteristic ....................................................... 97
I2C Dynamic Characteristics .............................................................. 98
SPI Dynamic Characteristics.............................................................. 99
I2S Dynamic Characteristics..............................................................102
7.6
7.6.1
7.6.2
7.6.3
7.7
7.8
7.9
7.10
7.11
8
9
APPLICATION CIRCUIT..............................................................104
PACKAGE DIMENSIONS ............................................................105
QFN 48L (6x6x0.8 mm3 Pitch 0.4 mm) .................................................105
LQFP 64L (7x7x1.4 mm3 footprint 2.0 mm)............................................106
LQFP 64L (10x10x1.4 mm3 footprint 2.0 mm).........................................107
9.1
9.2
9.3
10 REVISION HISTORY..................................................................108
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List of Figure
Figure 4.2-1 Ordering Information Scheme ................................................................................... 18
Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram .................................................................................. 20
Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram ................................................................................ 21
Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram ............................................................................ 22
Figure 5.1-1 ISD94100 Series Block Diagram............................................................................... 34
Figure 6.1-1 Cortex®-M4 Block Diagram........................................................................................ 35
Figure 6.2-1 ISD94100 Series Power Distribution Diagram .......................................................... 39
Figure 6.2-2 SRAM Block Diagram................................................................................................ 41
Figure 6.2-3 SRAM Memory Organization..................................................................................... 41
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 49
Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 50
Figure 6.3-3 System Clock Block Diagram .................................................................................... 51
Figure 6.3-4 HXT Stop Protect Procedure ..................................................................................... 52
Figure 6.3-5 SysTick Clock Control Block Diagram....................................................................... 52
Figure 6.3-6 Clock Output Block Diagram ..................................................................................... 53
Figure 7.4-1 External High Speed Crystal Timing Diagram........................................................... 88
Figure 7.4-2 HXT Typical Crystal Application Circuit..................................................................... 89
Figure 7.4-3 LXT Typical Crystal Application Circuit...................................................................... 90
Figure 7.5-1 Power-on Reset Condition......................................................................................... 94
Figure 7.8-1 I2C Timing Diagram ................................................................................................... 98
Figure 7.9-1 SPI Master Mode Timing Diagram ............................................................................ 99
Figure 7.9-2 SPI Slave Mode Timing Diagram ............................................................................ 101
Figure 7.10-1 I2S Master Mode Timing Diagram.......................................................................... 103
Figure 7.10-2 I2S Slave Mode Timing Diagram............................................................................ 103
Figure 8-1 Application Circuit....................................................................................................... 104
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List of Tables
Table 3.1-1 List of Abbreviations.................................................................................................... 16
Table 4.1-1 Devices Features and Peripheral Counts................................................................... 17
Table 4.2-1 Devices Features Summary ....................................................................................... 19
Table 4.4-1 Pin Description............................................................................................................ 31
Table 4.5-1 GPIO Alternate Function Summary ............................................................................ 33
Table 6.2.4-1 Address Space Assignments for On-Chip Controllers............................................. 40
Table 6.2.7-1 Exception Model ...................................................................................................... 45
Table 6.2.7-2 Interrupt Number Table............................................................................................ 46
Table 6.12.2-1 UART Feature........................................................................................................ 65
Table 6.14.2-1 SPI feature difference (SPI0~SPI2)....................................................................... 68
Table 7.1.1-1 Voltage characteristics............................................................................................. 76
Table 7.1.2-1 Current characteristics............................................................................................. 76
Table 7.1.3-1 Thermal characteristics............................................................................................ 76
Table 7.1.4-1 Electrostatic Discharge (ESD) Ratings.................................................................... 77
Table 7.2-1 General Operating Conditions .................................................................................... 78
Table 7.3-1 DC Electrical Characteristics ...................................................................................... 87
Table 7.4.1-1 External High Speed Clock Input Characteristics.................................................... 88
Table 7.4.1-2 External High Speed Crystal (HXT) Characteristics................................................ 89
Table 7.4.2-1 Internal High Speed RC Oscillator (HIRC) Characteristics...................................... 89
Table 7.4.3-1 External Low Speed Crystal (LXT) Characteristics ................................................. 90
Table 7.4.4-1 Internal Low Speed RC Oscillator (LIRC) Characteristics....................................... 90
Table 7.5.1-1 12-bit SARADC Characteristics............................................................................... 91
Table 7.5.2-1 LDO Characteristics................................................................................................. 93
Table 7.5.3-1 Low Voltage Reset and Brown-out Detector Characteristics................................... 93
Table 7.5.4-1 Power-on Reset Characteristics .............................................................................. 94
Table 7.6.1-1 USB Full-Speed Characteristics .............................................................................. 95
Table 7.6.2-1 USB Full-Speed PHY Characteristics...................................................................... 95
Table 7.6.3-1 USB VBUS Characteristics...................................................................................... 95
Table 7.7-1 VAD Characteristics.................................................................................................... 96
Table 7.8-1 Flash DC Electrical Characteristics ............................................................................ 97
Table 7.8-1 I2C Dynamic Characteristics ....................................................................................... 98
Table 7.6.3-1 Dynamic Characteristics of Data Input and Output Pin in Master Mode ................. 99
Table 7.6.3-2 Dynamic Characteristics of Data Input and Output Pin in Slave Mode ................. 100
Table 7.10-1 I2S Dynamic Characteristics ................................................................................... 102
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1
GENERAL DESCRIPTION
The ISD94100 series 32-bit microcontrollers are an embedded ARM® Cortex®-M4F core with DSP
extensions and a Floating Point Unit which run up to 200 MHz. It provides up to 512 KB of flash
memory and up to 192 KB of SRAM. It is ideal for consumer product applications which need
communication interfaces and high computing power.
The ISD94100 is also equipped with a variety of peripheral devices, such as Multi-Function Timers,
Watchdog Timers, RTC, PDMA, UART, SPI, I2C, PWM, GPIO, 12-bit ADC, USB1.1 Device, Low
voltage reset and Brown-out Detector. In addition, it supports plenty of audio peripherals such as
I2S, DMIC and audio DPWM modulator.
The ISD94100 series is suitable for a wide range of applications such as:
Audio Processing Platform
Consumer Products
Industrial Automation
Home Automation
Security Alarm System
System Supervisors
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2
FEATURES
2.1 ISD94100 Series Features
Core
ARM® Cortex®-M4F core running up to 200 MHz
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Supports DSP extension with hardware divider
Supports IEEE 754 compliant Floating-point Unit (FPU)
Supports Memory Protection Unit (MPU)
One 24-bit system timer
Supports Low Power Sleepmode by WFI and WFE instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
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Supports programmable mask-able interrupts
Supports Embedded Trace Macrocell
Built-in LDO for wide operating voltage range
Flash Memory
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Up to 512 KB on-chip Application ROM (APROM)
Configurable program code/data allocation
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4 KB on-chip Flash for user-defined loader (LDROM)
Supports 2-wire ICP update through SWD/ICE interface
Supports In-system program (ISP), In application program (IAP) update
Supports 4 KB page erase for all embedded flash
Supports 4 KB two-way cache to reduce power consumption and improve
performance.
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Enhanced performance up to 3.4 Core Mark/MHz when running code in Flash with
cache
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Supports 2-wire ICP flash updating through SWD interface
Supports 32-bit/64-bit and multi-word flash programming function.
Supports fast flash programming verification by CRC function.
SRAM
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Up to 192 KB embedded SRAM
32 KB SRAM in bank 0 that supports hardware parity check and retention mode
Supports byte-, half-word- and word-access
Supports exception (NMI) generated once a parity check error occurs
Supports PDMA mode
Clock Control
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Built-in 48.0 MHz or 49.152 MHz selectable internal high speed RC oscillator (HIRC) for
system operation.
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation.
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4~24.576 MHz external high speed crystal oscillator (HXT) for precise timing operation.
32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power
system operation.
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Supports one PLL up to 500 MHz for high performance system operation, sourced from
HIRC or HXT.
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Supports clock failure detection for high/low speed external crystal oscillator.
Supports exception (NMI) generation once a clock failure detected.
Supports clock output.
GPIO
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Supports four I/O modes:
Quasi bi-direction
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Push-Pull output
Open-Drain output
Input only with high impendence
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TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high slew driver and high sink current I/O (up to 20mA at 3.3V)
Supports software selectable slew rate control
Supports 5V tolerance function on subset of GPIO except analog I/O
PDMA (Peripheral DMA)
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Supports 16 independent configurable channels for automatic data transfer between
memories and peripherals
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Supports stride function.
Channel 0, 1 supports time-out function for each channel.
Supports Basic and Scatter-Gather Transfer modes
Each channel supports circular buffer management using Scatter-Gather Transfer mode
Supports two types of priorities modes: Fixed-priority and Round-robin modes
Supports byte-, half-word- and word-access
Supports single and burst transfer type
Supports source and destination address can be increment or fixed.
DMA transfer count up to 65536.
Multi-Function Timer (MFT, Timer + PWM)
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TIMER mode
Supports 4 sets of 32-bit timers with 24-bit up-timer and 8-bit prescale counter,
24-bit up counter value is readable.
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports external capture pin event for interval measurement.
Supports external capture pin event to reset 24-bit up counter.
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to
trigger PWM, EADC and DMA.
Supports Inter-Timer trigger mode
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PWM mode
Supports four 16-bit PWM counters with 10-bit dead time generator
Supports 12-bit pre-scale for PWM.
Supports independent mode for PWM output channel
Supports 8 channel PWM outputs in complementary mode
Supports mask function and tri-state enable for each PWM pin
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Supports trigger EADC on the following events:
PWM counter match zero, period value or compared value
PWM
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Supports up to 6 independent PWM outputs with 16-bit resolution
Supports maximum clock frequency up to 200MHz
Supports 12-bit clock prescale
Supports dead time with maximum divided 12-bit prescale
Supports one-shot or auto-reload counter operation mode
Supports up, down or up-down PWM counter type
Supports synchronous function for phase control
Supports counter synchronous start function
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ISD94100 Series Datasheet
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Supports complementary mode for 3 complementary paired PWM output channel
Supports brake function with auto recovery after brake condition removed
Supports mask function and tri-state output for each PWM channel
Supports trigger EADC to start conversion
Supports up to 6 independent input capture channels with 16-bit resolution counter
Watchdog Timer
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18-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
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Configurable to force WDT enable after chip power-on or reset.
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC
or LXT
Window Watchdog Timer
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Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
WWDT counter suspends in Idle/Power-down mode
RTC
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Supports software compensation by setting frequency compensate register
(FCR),compensated clock accuracy reaches ±5ppm within 5 seconds
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports Day of the Week counter
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
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Supports 1 Hz, clock output
Supports wake-up from idle mode, Power-down mode and Standby Power-down mode
Supports 32 kHz Oscillator gain control
Supports RTC Time Tick and Alarm Match interrupt
Support Time stamp
UART
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Supports low power UART (LPUART): baud rate clock from LXT(32.768 kHz) with
9600bps in Power-down mode even system clock is stopped
Support baud rate up to 12.5 MHz
Supports 16-byte FIFOs with programmable level trigger
Supports auto flow control ( CTS and RTS)
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Programmable receiver FIFO trigger level
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Supports wake-up function
Supports 8-bit receiver FIFO time-out detection function
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit FIFO overflow
detection function
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Supports nCTS, incoming data, RX FIFO reached threshold and RS-485 Address
Match (AAD mode) wake-up function in idle mode.
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
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Supports PDMA mode
I2C
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Supports up to two sets of I2C devices
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports 10 bits mode
Support High speed mode 3.4Mbps
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)
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Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
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Programmable clocks allow versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports SMBus and PMBus
Supports multi-address Power-down wake-up function
I2S
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Supports one I2S interface
Interface with external audio CODEC
Supports Master and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Mono and stereo audio data
I2S protocols: Philips standard, MSB-justified, and LSB-justified data format
PCM protocols: PCM standard, MSB-justified, and LSB-justified data format
PCM protocol supports TDM multi-channel transmission in one audio sample, the
number of data channels can be set as 2, 4, 6, or 8
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Two 16-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
SPI0
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SPI Quad controller – SPI0
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Supports one/two data channel half-duplex transfer
Support receive-only mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wired, no slave select signal, bi-direction interface
Master up to 25 MHz, and Slave up to 25 MHz (when chip operating at VDD = 2.7~3.6V)
Supports PDMA mode
SPI / I2S
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Supports two sets of SPI/ I2S controllers – SPI1/ SPI2
Supports Master or Slave mode operation
Supports two PDMA requests, one for transmitting and the other for receiving
SPI supports configurable bit length of a transfer word from 8 to 32-bit
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SPI Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depended on SPI setting of data width
SPI supports MSB first or LSB first transfer sequence
SPI supports the byte reorder function
SPI supports Byte or Word Suspend mode
SPI supports one data channel half-duplex transfer
SPI supports receive-only mode
I2S interface with external audio CODEC
I2S supports Master and Slave mode
I2S supports 8-, 16-, 24- and 32-bit audio data sizes
I2S supports mono and stereo audio data
I2S supports PCM mode A, PCM mode B, I2S and MSB justified data format
I2S Interface with external audio CODEC
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I2S provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
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Generates interrupt requests when buffer levels cross a programmable boundary
EADC
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Analog input voltage range: 0~ AVDD
Supports single 12-bit SAR EADC conversion
12-bit resolution and 10-bit accuracy is guaranteed
Up to 13 external single-ended analog input channels
Up to 2 MSPS conversion rate
Supports three power saving modes:
Deep Power-down mode
Power-down mode.
Standby mode.
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Supports single EADC interrupt
Supports calibration and load calibration words capability.
An A/D conversion can be triggered by Software enable, External pin, Timer 0~3
overflow pulse trigger and PWM trigger.
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12-bit, 10-bit, 8-bit, 6-bit configurable resolution.
Maximum EADC clock frequency is 60 MHz.
Configurable EADC internal sampling time.
Up to 13 sample modules
Each of sample module 0~12 which is configurable for EADC converter channel
EADC_CH0~12 and trigger source.
Double buffer for sample module 0~3
Configurable sampling time for each sample module.
Conversion results are held in 13 data registers with valid and overrun
indicators.
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Supports PDMA transfer
USB 1.1 Device Controller
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Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
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Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 1k bytes buffer size
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Provides remote wake-up capabilityProgrammable initial value
Digital Microphone Inputs
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–
Provides one 32-level FIFO data buffers for receiving.
Generates interrupt requests when buffer levels cross a programmable boundary.
Supports PDMA transfer.
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ISD94100 Series Datasheet
–
–
Supports up to four channel digital microphones.
Both digital PDM microphone inputs can be used simultaneously.
Voice Active Detection
–
Configuration detect levels.
–
–
–
Supports idle mode wake-up function.
Supports auto switch DMIC path when CPU wake-up by VAD.
Generates interrupt requests when voice detected.
Audio DPWM Modulator
–
Differential Audio PWM Output (DPWM)
–
–
–
–
–
–
Supports left channel, right channels and sub-woofer channel.
Supports sample rate from 16~96 kHz
Programmable biquad filter with 10 band.
PDMA data channel for streaming of PCM audio data.
Supports the single precision floating point for input data and BIQ coefficient.
Provides one 32-level FIFO data buffers for transmitting.
Cyclic Redundancy Calculation Unit
–
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
Programmable initial value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum.
Supports 8-/16-/32-bit of data width
–
–
–
–
–
–
–
–
–
Programmable seed value
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using DMA to write data to perform CRC operation
Brown-out Detector
–
–
With 8 levels: 3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 1.5V
Operating Temperature: -40℃~85℃
Packages
–
All Green package (RoHS)
QFN 48-pin (6x6 mm)
LQFP 64-pin (7x7 mm)
LQFP 64-pin (10x10 mm)
–
–
–
Sep 09, 2019
Page 14 of 109
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ISD94100 Series Datasheet
3
ABBREVIATIONS
3.1 Abbreviations
Description
Acronym
ACMP
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
ADC
AES
APB
AHB
BOD
CAN
DAP
DES
DMIC
DPWM
EBI
Controller Area Network
Debug Access Port
Data Encryption Standard
Digital Microphone Inputs
Audio DPWM Modulator
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
High Speed RC Oscillator
External High Speed Crystal Oscillator
In Application Programming
IAP
ICP
In Circuit Programming
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
LIRC
MPU
NVIC
PCLK
PDMA
PLL
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
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ISD94100 Series Datasheet
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TMR
UART
UCID
USB
VAD
WDT
WWDT
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Voice Active Detection
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
Sep 09, 2019
Page 16 of 109
Rev1.13
ISD94100 Series Datasheet
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 Parts Information
ISD941
PART NUMBER
24
24
24
24
24
24
24
13
24
23
13
ARI
BRI
ADI
CDI
DDI
PDI
EDI
ADI
BYI
BYI
BYI
Max. CPU frequency
200 *1
200
(MHz)
Flash (KB)
SRAM (KB)
512
192
256
128
512
256
192
128
ISP Loader ROM (KB)
4
I/O
58
57
41
32-bit Timer
4
√
1
1
2
1
2
RTC
UART
SPI
SPI/I2S
I2S
I2C
PWM
6
5
USB 1.1 FS Device
12-bit ADC
Audio DPWM
VAD
-
√
13
12
-
2.1
√
--
-
2.1
√
-
4 *1
-
4
-
DMIC
Acoustic Echo
Cancellation
-
√
-
Beamforming
-
-
√
-
Noise
Reduction
Voice
√
-
-
-
√
-
√
Recognition
LQFP 64
(10x10 mm)
LQFP 64
(7x7 mm)
QFN 48
(6x6 mm)
Package
Table 4.1-1 Devices Features and Peripheral Counts
Note *1: maximum CPU 100MHz when DMIC is used.
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ISD94100 Series Datasheet
I9 4 X X X X X X
4.2 Ordering Information
ISD Audio
Product Family
Product Series
4: Cortex-M4F
Family ID
1: Family Series ID
Flash ROM
1: 256KB
2: 512KB
SRAM Size
3: 128KB
4: 192KB
Feature
A: Standard
B: Basic, no Audio
C: Standard + Voice Recognition
D: Standard + Beamforming + Noise Reduction
P: Standard + Beamforming + Noise Reduction + Voice Recognition
Package Type
Y: QFN48 (6x6 mm)
D: LQFP64 (7x7 mm)
R: LQFP64 (10x10 mm)
Temperature
I: -40℃ ~ +85℃
Figure 4.2-1 Ordering Information Scheme
Sep 09, 2019
Page 18 of 109
Rev1.13
ISD94100 Series Datasheet
PART NUMBER
ISD94124BYI
ISD94123BYI
ISD94113BYI
ISD94124ADI
ISD94124CDI
ISD94124DDI
ISD94124PDI
ISD94124EDI
ISD94113ADI
ISD94124ARI
RAM
FLASH
FEATURE
PACKAGE
192 KB
128 KB
128 KB
192 KB
192 KB
192 KB
192 KB
192 KB
128 KB
192 KB
192 KB
512 KB
512 KB
256 KB
512 KB
512 KB
512 KB
512 KB
512 KB
256 KB
512 KB
512 KB
Basic feature
Basic feature
Basic feature
QFN48 (6x6 mm)
QFN48 (6x6 mm)
QFN48 (6x6 mm)
Standard feature
LQFP64 (7x7 mm)
LQFP64 (7x7 mm)
LQFP64 (7x7 mm)
LQFP64 (7x7 mm)
LQFP64 (7x7 mm)
LQFP64 (7x7 mm)
LQFP64 (10x10 mm)
LQFP64 (10x10 mm)
Standard feature + VR
Standard feature + BF + NR
Standard feature + BF + NR + VR
Standard feature + AEC + NR + VR
Standard feature
Standard feature
ISD94124BRI
Basic feature
Note:
1. VR = Voice Recognition / BF = Beamforming / NR = Noise Reduction / AEC = Acoustic Echo Cancellation
Table 4.2-1 Devices Features Summary
Sep 09, 2019
Page 19 of 109
Rev1.13
ISD94100 Series Datasheet
4.3 Pin Configuration
4.3.1
QFN48 (6x6 mm) Pin Diagram
PA.4
PA.5
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PD.1
Top transparent view
PD.0
PA.6
PB.13
PB.14
PB.15
USB_VDD33
PC.4
PA.7
PA.8
PA.9
QFN48
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
PC.3
PC.2
PC.1
PC.0
VSS
AVDD
Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram
Sep 09, 2019
Page 20 of 109
Rev1.13
ISD94100 Series Datasheet
4.3.2
LQFP64 (7x7 mm) Pin Diagram
PA.0
PA.1
PA.2
PA.3
49
50
51
52
32
31
30
29
USB_VDD33
PC.14
PC.13
PC.12
PA.4
PA.5
53
54
55
56
57
58
59
60
61
62
63
64
28
27
26
25
24
23
22
21
20
19
18
17
PC.11
PC.10
PC.9
PC.8
PC.7
PC.6
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
PA.6
PA.7
LQFP64
(7x7 mm)
PA.8
PA.9
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram
Sep 09, 2019
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ISD94100 Series Datasheet
4.3.3
LQFP64 (10x10 mm) Pin Diagram
PA.0
PA.1
PA.2
PA.3
49
50
51
52
32
31
30
29
PC.15
PC.14
PC.13
PC.12
PA.4
PA.5
53
54
55
56
57
58
59
60
61
62
63
64
28
27
26
25
24
23
22
21
20
19
18
17
PC.11
PC.10
PC.9
PC.8
PC.7
PC.6
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
PA.6
PA.7
LQFP64
(10x10 mm)
PA.8
PA.9
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram
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Rev1.13
ISD94100 Series Datasheet
4.4 Pin Description
MFP = Multi-function pin.
Note: Pin Type I=Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin;
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PB.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin.
PWM0_SYNC_IN
I2C0_SCL
PWM0_CH0
PB.1
MFP1 PWM0 counter synchronous trigger input pin.
MFP2 I2C0 clock pin.
1
2
3
1
2
3
1
2
3
MFP3 PWM0 channel0 output/capture input.
MFP0 General purpose digital I/O pin.
PWM0_SYNC_OUT
I2C0_SDA
PWM0_CH1
PB.2
MFP1 PWM0 counter synchronous trigger output pin.
MFP2 I2C0 data input/output pin.
MFP3 PWM0 channel1 output/capture input.
MFP0 General purpose digital I/O pin.
PWM0_CH0
TM2
MFP1 PWM0 channel0 output/capture input.
MFP2 Timer2 event counter input / toggle output.
MFP3 PWM0 channel2 output/capture input.
MFP0 General purpose digital I/O pin.
PWM0_CH2
PB.3
PWM0_CH1
TM2_EXT
DMIC_DAT1
UART0_RXD
PWM0_CH3
PB.4
MFP1 PWM0 channel1 output/capture input.
MFP2 Timer2 external capture input.
4
4
4
MFP3 Digital microphone channel 1 data input pin.
MFP4 UART0 Data receiver input pin.
I
I/O
I/O
I
MFP5 PWM0 channel3 output/capture input.
MFP0 General purpose digital I/O pin.
UART0_nCTS
PWM0_CH0
DMIC_CLK1
UART0_TXD
PWM0_CH4
RESETN
MFP1 Clear to Send input pin for UART0.
MFP2 PWM0 channel0 output/capture input.
MFP3 Digital microphone channel 1 clock output pin.
MFP4 UART0 data transmitter output pin.
MFP5 PWM0 channel4 output/capture input.
I/O
O
5
6
5
6
5
6
O
I/O
I
MFP0 External reset input: active LOW, with an internal pull-
up. Set this pin low reset to initial state.
Sep 09, 2019
Page 23 of 109
Rev1.13
ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PB.5
I/O
I
MFP0 General purpose digital I/O pin.
XT1_OUT
MFP1 External 4~24.576 MHz (high speed) crystal output
pin.
PWM0_CH1
I2C0_SDA
I2C1_SDA
DMIC_DAT0
PB.6
I/O
I/O
I/O
I
MFP2 PWM0 channel1 output/capture input.
MFP3 I2C0 data input/output pin.
7
7
7
MFP4 I2C1 data input/output pin.
MFP5 Digital microphone channel 0 data input pin.
MFP0 General purpose digital I/O pin.
MFP1 External 4~24.576 MHz (high speed) crystal input pin.
MFP2 PWM0 channel2 output/capture input.
MFP4 I2C0 serial clock pin.
I/O
I
XT1_IN
PWM0_CH2
I2C0_SCL
I2C1_SCL
DMIC_CLK0
PB.7
I/O
I/O
I/O
O
8
8
8
MFP5 I2C1 serial clock pin.
MFP6 Digital microphone channel 0 clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 Request to Send output pin for UART0.
MFP2 PWM0 channel3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP1 UART0 Data transmitter output pin.
MFP2 PWM0 channel4 output/capture input.
MFP0 General purpose digital I/O pin.
MFP1 UART0 Data receiver input pin.
MFP2 PWM0 channel5 output/capture input.
I/O
O
UART0_nRTS
PWM0_CH3
PB.8
9
9
I/O
I/O
O
UART0_TXD
PWM0_CH4
PB.9
10
10
I/O
I/O
I
UART0_RXD
PWM0_CH5
LDO_CAP
11
12
11
12
I/O
P
MFP0 LDO output pin.
9
Note: This pin needs to be connected with a 1uF
capacitor.
VSS
P
P
P
MFP0 Ground pin for digital circuit.
MFP0 Ground pin for analog circuit.
10
11
13
14
13
14
AVSS
VDD
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
12
13
15
16
15
16
AVDD
P
MFP0 Power supply for internal analog circuit.
MFP0 General purpose digital I/O pin.
MPF1 I2C1 clock pin.
PC.0
I/O
I/O
O
I2C1_SCL
X32_OUT
SPI1_MOSI
14
17
17
MFP2 External 32.768 kHz (low-speed) crystal output pin.
I/O
MFP3 SPI1 MOSI (Master Out, Slave In) pin; or I2S1 data
output pin.
Sep 09, 2019
Page 24 of 109
Rev1.13
ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PC.1
I/O
I/O
I
MFP0 General purpose digital I/O pin.
I2C1_SDA
X32_IN
MFP1 I2C1 data input/output pin.
15
16
17
18
18
19
20
21
18
19
20
21
MFP2 External 32.768 kHz (low-speed) crystal input pin.
SPI1_MISO
I/O
MFP3 SPI1 MISO (Master In, Slave Out) pin; or I2S1 data
input pin.
PC.2
I/O
O
MFP0 General purpose digital I/O pin.
I2C1_SMBSUS
TM3
MFP1 I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
MFP2 Timer3 event counter input / toggle output.
MFP3 SPI1 Serial Clock pin; or I2S1 bit clock pin.
MFP0 General purpose digital I/O pin.
I/O
I/O
I/O
O
SPI1_CLK
PC.3
I2C1_SMBAL
TM3_EXT
SPI1_SS
MFP1 I2C1 SMBus SMBALERT# pin
I/O
I/O
MFP2 Timer3 external capture input.
MFP3 SPI1 slave select pin; or I2S1 left right channel clock
pin.
PC.4
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel2 output/capture input.
MFP2 Clock Output pin.
PWM0_CH2
CLKO
SPI1_I2SMCLK
PC.5
O
MFP3 SPI1 I2S master clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 External interrupt1 input pin.
MFP2 SPI2 MOSI (Master Out, Slave In) pin.
MFP0 General purpose digital I/O pin.
MFP1 External interrupt2 input pin.
MFP2 SPI2 MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP1 1st SPI0 Slave Select pin
I/O
I
INT1
22
23
24
25
26
22
23
24
25
26
SPI2_MOSI
PC.6
I/O
I/O
I
INT2
SPI2_MISO
PC.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI0_SS0
SPI2_CLK
PC.8
MFP2 SPI2 serial clock pin.
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 MOSI (Master Out, Slave In) pin.
MFP2 SPI2 Slave Select pin.
SPI0_MOSI1
SPI2_SS
PC.9
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 MISO (Master In, Slave Out) pin.
MFP2 SPI2 I2S master clock output pin
SPI0_MISO1
SPI2_I2SMCLK
Sep 09, 2019
Page 25 of 109
Rev1.13
ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PC.10
I/O
I/O
MFP0 General purpose digital I/O pin.
SPI0_MOSI0
MFP1 1st SPI0 MOSI (Master Out, Slave In) pin.
27
27
PWM0_BRAKE0
DPWM_RN
PC.11
I
MFP2 Brake input pin 0 of PWM0.
O
MFP3 Audio DPWM right channel negative output pin.
MFP0 General purpose digital I/O pin.
I/O
SPI0_MISO0
I/O
MFP1 1st SPI0 MISO (Master In, Slave Out) pin.
28
29
30
28
29
30
PWM0_BRAKE1
DPWM_RP
PC.12
I
MFP2 Brake input pin 1 of PWM0.
O
MFP3 Audio DPWM right channel positive output pin.
MFP0 General purpose digital I/O pin.
I/O
SPI0_CLK
DPWM_LN
PC.13
I/O
O
MFP1 SPI0 serial clock pin.
MFP3 Audio DPWM left channel negative output pin.
MFP0 General purpose digital I/O pin.
I/O
PWM0_CH3
I/O
MFP1 PWM0 channel3 output/capture input.
I2C0_SCL
DPWM_LP
PC.14
I/O
O
MFP2 I2C0 clock pin.
MFP3 Audio DPWM left channel positive output pin.
MFP0 General purpose digital I/O pin.
I/O
PWM0_CH4
I2C0_SDA
DPWM_SN
I/O
I/O
O
MFP1 PWM0 channel4 output/capture input.
MFP2 I2C0 data input/output pin.
31
31
32
MFP3 Audio DPWM sub-woofer channel negative output
pin.
PC.15
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 Slave Select pin
SPI0_SS1
DPWM_SP
USB_VDD33
PB.15
O
MFP3 Audio DPWM sub-woofer channel positive output pin.
MFP0 Power supply for USB, DC 3.3V.
MFP0 General purpose digital I/O pin.
MFP1 Power supply from USB or HUB.
MFP2 I2S0 master clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 USB differential signal D-.
19
20
32
33
P
I/O
P
USB_VBUS
I2S0_MCLK
PB.14
O
I/O
A
21
34
35
USB_D-
I2S0_DO
PB.13
O
MFP2 I2S0 data output pin.
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 USB differential signal D+.
22
USB_D+
I2S0_DI
I
MFP2 I2S0 data input pin.
Sep 09, 2019
Page 26 of 109
Rev1.13
ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PD.0
INT3
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 External interrupt3 input pin.
I2C1_SCL
I2C0_SCL
I2S0_BCLK
DPWM_LN
PD.1
I/O
I/O
I/O
O
MFP2 I2C1 clock pin.
23
24
25
26
27
36
37
38
39
40
33
34
35
36
37
MFP3 I2C0 clock pin.
MFP4 I2S0 bit clock pin.
MFP5 Audio DPWM left channel negative output pin.
MFP0 General purpose digital I/O pin.
MFP1 External interrupt4 input pin.
I/O
I
INT4
I2C1_SDA
I2C0_SDA
I2S0_LRCK
DPWM_LP
PD.2
I/O
I/O
I/O
O
MFP2 I2C1 data p input/output in.
MFP3 I2C0 data input/output pin.
MFP4 I2S0 left right channel clock pin.
MFP5 Audio DPWM left channel positive output pin.
MFP0 General purpose digital I/O pin.
MFP1 TPIU for ETM Tx trace clock output pin.
MFP2 SPI1 MOSI (Master Out, Slave In) pin.
MFP3 I2S0 master clock output pin.
MFP4 I2C1 clock pin.
I/O
O
TRACE_CLK
SPI1_MOSI
I2S0_MCLK
I2C1_SCL
TM0
I/O
O
I/O
I/O
I/O
O
MFP5 Timer0 event counter input / toggle output.
MFP0 General purpose digital I/O pin.
MFP1 TPIU for ETM Tx trace data output bit0.
MFP2 SPI1 MISO (Master In, Slave Out) pin.
MFP3 I2S0 left right channel clock pin.
MFP4 Digital microphone channel 1 clock output pin.
MFP5 Timer2 event counter input / toggle output.
MFP0 General purpose digital I/O pin.
MFP1 TPIU for ETM Tx trace data output bit1.
MFP2 SPI1 serial clock pin.
PD.3
TRACE_DATA0
SPI1_MISO
I2S0_LRCK
DMIC_CLK1
TM2
I/O
I/O
O
I/O
I/O
O
PD.4
TRACE_DATA1
SPI1_CLK
I2S0_DI
I/O
I
MFP3 I2S0 data input pin.
DMIC_DAT1
TM1
I
MFP4 Digital microphone channel 1 data input pin.
MFP5 Timer1 event counter input / toggle output.
I/O
Sep 09, 2019
Page 27 of 109
Rev1.13
ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PD.5
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 TPIU for ETM Tx trace data output bit2.
MFP2 SPI1 Slave Select pin.
TRACE_DATA2
SPI1_SS
I/O
O
28
41
38
I2S0_DO
MFP3 I2S0 data output pin.
DMIC_CLK0
DPWM_RN
PD.6
O
MFP4 Digital microphone channel 0 clock output pin.
MFP5 Audio DPWM right channel negative output pin.
MFP0 General purpose digital I/O pin.
MFP1 TPIU for ETM Tx trace data output bit3.
MFP2 SPI1 I2S master clock output pin
MFP3 I2S0 Bit Clock pin.
O
I/O
O
TRACE_DATA3
SPI1_I2SMCLK
I2S0_BCLK
DMIC_DAT0
DPWM_RP
PD.7
O
42
43
39
40
I/O
I
MFP4 Digital microphone channel 0 data input pin.
MFP5 Audio DPWM right channel positive output pin.
MFP0 General purpose digital I/O pin.
O
I/O
PWM0_CH5
INT1
I/O
I
MFP1 PWM0 channel5 output/capture input.
MFP2 External interrupt1 input pin.
PD.8
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 Serial wired debugger clock pin
MFP2 Timer0 event counter input / toggle output.
MFP3 I2C1 clock pin.
ICE_CLK
TM0
I/O
I/O
I/O
O
29
44
41
I2C1_SCL
I2C0_SCL
DPWM_SN
MFP4 I2C0 clock pin.
MFP5 Audio DPWM sub-woofer channel negative output
pin.
PD.9
I/O
I/O
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 Serial wired debugger data pin
MFP2 Timer0 external capture input.
MFP3 I2C1 data input/output pin.
ICE_DAT
TM0_EXT
I2C1_SDA
I2C0_SDA
DPWM_SP
PD.10
30
45
42
MFP4 I2C0 data input/output pin.
MFP5 Audio DPWM sub-woofer channel positive output pin.
MFP0 General purpose digital I/O pin.
MFP1 External interrupt5 input pin.
MFP2 EADC0 external trigger input.
MFP0 General purpose digital I/O pin.
MFP1 UART0 Data transmitter output pin.
MFP2 External interrupt2 input pin.
I/O
I
INT5
43
44
EADC0_ST
PD.11
I
I/O
O
UART0_TXD
INT2
I
Sep 09, 2019
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ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PD.12
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 UART0 Data receiver input pin.
MFP2 External interrupt3 input pin.
UART0_RXD
INT3
I
45
46
PWM0_CH3
INT0
I/O
I
MFP3 PWM0 channel3 output/capture input.
MFP4 External interrupt0 input pin.
PD.13
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 Slave Select pin
SPI0_SS1
EADC0_CH10
PD.14
46
47
A
MFP2 EADC0 channel10 analog input.
MFP0 General purpose digital I/O pin.
MFP1 Clear to Send input pin for UART0.
MFP2 EADC0 channel11 analog input.
MFP3 I2C0 clock pin.
I/O
I
UART0_nCTS
EADC0_CH11
I2C0_SCL
UART0_TXD
I2C1_SCL
PD.15
A
31
47
I/O
O
MFP4 UART0 data transmitter output pin.
MFP5 I2C1 clock pin.
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 Request to Send output pin for UART0.
MFP2 EADC0 channel12 analog input.
MFP3 I2C0 data input/output pin.
UART0_nRTS
EADC0_CH12
I2C0_SDA
UART0_RXD
I2C1_SDA
PA.0
A
32
48
48
I/O
I
MFP4 UART0 data receiver input pin.
MFP5 I2C1 data input/output pin.
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 Slave Select pin
SPI0_SS1
EADC0_CH0
DMIC_DAT0
PA.1
33
34
35
49
50
51
49
50
51
A
MFP2 EADC0 channel0 analog input.
MFP3 Digital microphone channel 0 data input pin.
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 MOSI (Master Out, Slave In) pin.
MFP2 EADC0 channel1 analog input.
MFP3 Digital microphone channel 0 clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 2nd SPI0 MISO (Master In, Slave Out) pin.
MFP2 EADC0 channel2 analog input.
MFP3 Digital microphone channel 1 data input pin.
I
I/O
I/O
A
SPI0_MOSI1
EADC0_CH1
DMIC_CLK0
PA2
O
I/O
I/O
A
SPI0_MISO1
EADC0_CH2
DMIC_DAT1
I
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ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PA.3
I/O
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 1st SPI0 MOSI (Master Out, Slave In) pin.
MFP2 EADC0 channel3 analog input.
MFP3 Digital microphone channel 1 clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 1st SPI0 MISO (Master In, Slave Out) pin.
MFP2 EADC0 channel4 analog input.
MFP3 Audio DPWM left channel negative output pin.
MFP0 General purpose digital I/O pin.
MFP1 SPI0 serial clock pin.
SPI0_MOSI0
EADC0_CH3
DMIC_CLK1
PA.4
36
37
52
53
52
53
O
I/O
I/O
A
SPI0_MISO0
EADC0_CH4
DPWM_LN
PA.5
O
I/O
I/O
A
SPI0_CLK
EADC0_CH5
DPWM_LP
PA.6
38
39
54
55
54
55
MFP2 EADC0 channel5 analog input.
MFP3 Audio DPWM left channel positive output pin.
MFP0 General purpose digital I/O pin.
MFP1 1st SPI0 Slave Select pin
O
I/O
I/O
A
SPI0_SS0
EADC0_CH6
PA.7
MFP2 EADC0 channel6 analog input.
MFP0 General purpose digital I/O pin.
MFP1 UART0 data transmitter output pin.
MFP2 EADC0 channel7 analog input.
I/O
O
UART0_TXD
EADC0_CH7
SPI2_MISO
40
41
42
56
57
58
56
57
58
A
I/O
MFP4 SPI2 MISO (Master In, Slave Out) pin; or I2S2 data
input pin.
PA.8
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 UART0 data receiver input pin..
MFP2 EADC0 channel8 analog input.
UART0_RXD
EADC0_CH8
SPI2_MOSI
A
I/O
MFP4 SPI2 MOSI (Master Out, Slave In) pin; or I2S2 data
output pin.
PA.9
I/O
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 I2C0 Serial Clock pin
I2C0_SCL
EADC0_CH9
SPI2_SS
MFP2 EADC0 channel9 analog input.
I/O
MFP4 SPI2 slave select pin; or I2S2 left right channel clock
pin.
PA.10
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C0 data input/output pin.
I2C0_SDA
EADC0_ST
DPWM_RN
SPI2_CLK
MFP2 EADC0 external trigger input.
43
59
59
O
MFP3 Audio DPWM right channel negative output pin.
MFP4 SPI2 clock pin; or I2S2 bit clock pin.
I/O
Sep 09, 2019
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ISD94100 Series Datasheet
Pins
Pin Name
Type MFP Description
QFN48
(6x6)
LQFP64
(7x7)
LQFP64
(10x10)
PA.11
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
MFP2 Timer0 event counter input / toggle output.
MFP3 Audio DPWM right channel positive output pin.
MFP0 General purpose digital I/O pin.
MFP1 I2C0 SMBus SMBALERT# pin
MFP2 Timer0 external capture input.
I2C0_SMBSUS
TM0
44
45
60
61
60
61
I/O
O
DPWM_RP
PA.12
I/O
O
I2C0_SMBAL
TM0_EXT
SPI2_I2SMCLK
PA.13
I/O
O
MFP4 SPI2 I2S master clock output pin.
MFP0 General purpose digital I/O pin.
MFP1 Clock Output pin.
I/O
O
CLKO
INT0
I
MFP2 External interrupt0 input pin.
46
62
62
DPWM_SN
O
MFP3 Audio DPWM sub-woofer channel negative output
pin.
I2C1_SCL
PA.14
I/O
I/O
MFP4 I2C1 clock pin.
MFP0 General purpose digital I/O pin.
SPI0_SS0
I/O
MFP1 1st SPI0 Slave Select pin
47
48
63
64
63
64
TM1
I/O
O
MFP2 Timer1 event counter input / toggle output.
MFP3 Audio DPWM sub-woofer channel positive output pin.
MFP4 I2C1 data input/output pin.
DPWM_SP
I2C1_SDA
I/O
PA.15
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 External interrupt0 input pin.
MFP2 Timer1 external capture input.
INT0
TM1_EXT
I/O
Note:
1. Part number ISD941XXBYI and ISD941XXBRI do not provide DPWM and DMIC functionality.
Table 4.4-1 Pin Description
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ISD94100 Series Datasheet
4.5 GPIO Alternate Function Summary
MFP* = Multi-function pin. (Reference section )
Pin function is defined in SYS_GPx_MFPx registers. For example PA0~7 pin functions are defined in SYS_GPA_MFPL register,
and PA8~15 pin functions are defined in SYS_GPA_MFPH register.
MFP0
MFP1
SPI0_SS1
MFP2
EADC0_CH0
EADC0_CH1
EADC0_CH2
EADC0_CH3
EADC0_CH4
EADC0_CH5
EADC0_CH6
EADC0_CH7
EADC0_CH8
EADC0_CH9
EADC0_ST
TM0
MFP3
DMIC_DAT0
DMIC_CLK0
DMIC_DAT1
DMIC_CLK1
DPWM_LN
DPWM_LP
MFP4
MFP5
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PA.8
PA.9
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
PB.0
PB.1
PB.2
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
PB.13
PB.14
PB.15
PC.0
PC.1
SPI0_MOSI1
SPI0_MISO1
SPI0_MOSI0
SPI0_MISO0
SPI0_CLK
SPI0_SS0
UART0_TXD
UART0_RXD
I2C0_SCL
SPI2_MISO
SPI2_MOSI
SPI2_SS
I2C0_SDA
I2C0_SMBSUS
I2C0_SMBAL
CLKO
DPWM_RN
DPWM_RP
SPI2_CLK
TM0_EXT
SPI2_I2SMCLK
I2C1_SCL
INT0
DPWM_SN
DPWM_SP
SPI0_SS0
INT0
TM1
I2C1_SDA
TM1_EXT
PWM0_SYNC_IN I2C0_SCL
PWM0_SYNC_OUT I2C0_SDA
PWM0_CH0
PWM0_CH1
PWM0_CH2
DMIC_DAT1
DMIC_CLK1
I2C0_SDA
PWM0_CH0
PWM0_CH1
UART0_nCTS
XT1_OUT
TM2
TM2_EXT
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
I2S0_DI
UART0_RXD
UART0_TXD
I2C1_SDA
PWM0_CH3
PWM0_CH4
DMIC_DAT0
DMIC_CLK0
XT1_IN
I2C0_SCL
I2C1_SCL
UART0_nRTS
UART0_TXD
UART0_RXD
USB_D+
USB_D-
I2S0_DO
USB_VBUS
I2C1_SCL
I2C1_SDA
I2S0_MCLK
X32_OUT
X32_IN
SPI1_MOSI
SPI1_MISO
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ISD94100 Series Datasheet
MFP0
MFP1
I2C1_SMBSUS
I2C1_SMBAL
PWM0_CH2
INT1
MFP2
MFP3
SPI1_CLK
MFP4
MFP5
PC.2
PC.3
PC.4
PC.5
PC.6
PC.7
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PD.0
PD.1
PD.2
PD.3
PD.4
PD.5
PD.6
PD.7
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PD.14
TM3
TM3_EXT
SPI1_SS
CLKO
SPI1_I2SMCLK
SPI2_MOSI
SPI2_MISO
SPI2_CLK
INT2
SPI0_SS0
SPI0_MOSI1
SPI0_MISO1
SPI0_MOSI0
SPI0_MISO0
SPI0_CLK
SPI2_SS
SPI2_I2SMCLK
PWM0_BRAKE0
PWM0_BRAKE1
DPWM_RN
DPWM_RP
DPWM_LN
DPWM_LP
DPWM_SN
DPWM_SP
I2C0_SCL
I2C0_SDA
I2S0_MCLK
I2S0_LRCK
I2S0_DI
PWM0_CH3
PWM0_CH4
SPI0_SS1
I2C0_SCL
I2C0_SDA
INT3
I2C1_SCL
I2C1_SDA
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI1_SS
I2S0_BCLK
I2S0_LRCK
I2C1_SCL
DPWM_LN
INT4
DPWM_LP
TM0
TRACE_CLK
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
TRACE_DATA3
PWM0_CH5
ICE_CLK
DMIC_CLK1
DMIC_DAT1
DMIC_CLK0
DMIC_DAT0
TM2
TM1
I2S0_DO
DPWM_RN
DPWM_RP
SPI1_I2SMCLK
INT1
I2S0_BCLK
TM0
I2C1_SCL
I2C1_SDA
I2C0_SCL
I2C0_SDA
DPWM_SN
DPWM_SP
ICE_DAT
TM0_EXT
EADC0_ST
INT2
INT5
UART0_TXD
UART0_RXD
SPI0_SS1
INT3
PWM0_CH3
INT0
EADC0_CH10
EADC0_CH11
EADC0_CH12
UART0_nCTS
UART0_nRTS
I2C0_SCL
I2C0_SDA
UART0_TXD
UART0_RXD
I2C1_SCL
I2C1_SDA
PD.15
Note:
1. Part number ISD941XXBYI does not provide DPWM and DMIC functionality.
Table 4.5-1 GPIO Alternate Function Summary
Sep 09, 2019
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ISD94100 Series Datasheet
5
BLOCK DIAGRAM
5.1 ISD94100 Series Block Diagram
Power control
Timer / PWM
Analog Interface
Memory
APROM
512KB
POR / LVR / BOD
Timer x4
WDT x1/WWDT x1
PWM x6
12-bit ADC 13-ch
ARM
CortexTM-M4
(DSP/FPU/ETM)
200MHz
SRAM 192KB
LDROM 4KB
CPU core LDO
1.2V
Data Flash share
with APROM
RTC
Bridge
AHB Bus
APB Bus
Connectivity
Security
GPIO
Clock control
HS Osc.
48.0/49.152MHz
CRC
External interrupt
UART0 x1
USB 1.1 Device
I2S
LS Osc. 10KHz
PDMA
16-ch
General Purpose
IO
I2C x2
PLL 100~500MHz
HS Ext. Crystal
4~24.576MHz
(SPI/I2S) x2
SPI (Quad) x1
DMIC
LS Ext. Crystal
32.768KHz
DPWM
Figure 5.1-1 ISD94100 Series Block Diagram
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ISD94100 Series Datasheet
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex®-M4 Core
The Cortex®-M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The processor
with optional hardware debug functionality can execute Thumb code and is compatible with other
Cortex®-M profile processors. The profile supports two modes -Thread mode and Handler mode.
Handler mode is entered as a result of an exception. An exception return can only be issued in
Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception
return. The Cortex®-M4F is a processor with the same capability as the Cortex®-M4 processor and
includes floating point arithmetic functionality. The ISD94100 series contains an embedded
Cortex®-M4F processor. Throughout this document, the name Cortex®-M4 refers to both Cortex®-
M4 and Cortex®-M4F processors. The following figure shows the functional controller of the
processor.
Figure 6.1-1 Cortex®-M4 Block Diagram
Cortex®-M4 processor features:
A low gate count processor core, with low latency interrupt processing that has:
A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual
Banked Stack Pointer (SP)
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ISD94100 Series Datasheet
Hardware integer divide instructions, SDIV and UDIV
Handler and Thread modes
Thumb and Debug states
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit
Support for ARMv6 big-endian byte-invariant or little-endian accesses
Support for ARMv6 unaligned accesses
Floating Point Unit (FPU) in the Cortex®-M4F processor providing:
32-bit instructions for single-precision (C float) data-processing operations
Combined Multiply and Accumulate instructions for increased precision (Fused
MAC)
Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers
Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing. Features include:
External interrupts. Configurable from 1 to 240 (the ISD94100 series configured
with 97 interrupts)
Bits of priority, configurable from 3 to 8
Dynamic reprioritization of interrupts
Priority grouping which enables selection of preempting interrupt levels and non-
preempting interrupt levels
Support for tail-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration between
interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
Eight memory regions
Sub Region Disable (SRD), enabling efficient use of memory regions
The ability to enable a background region that implements the default memory
map attributes
Low-cost debug solution that features:
Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is asserted.
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ISD94100 Series Datasheet
Serial Wire Debug Port(SW-DP) debug access
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
code patches
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,
and System bus interfaces
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
Bit-band support that includes atomic bit-band write and read operations.
Memory access alignment
Write buffer for buffering of write data
Exclusive access transfers for multiprocessor systems
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ISD94100 Series Datasheet
6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Organization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
A system reset can be triggered by one of the nine sources listed below. The reset source can be
identified by checking the reset flag bits in the System Reset Status Register (SYS_RSTSTS).
Hardware Reset Sources
-
-
-
-
-
-
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
CPU Lockup Reset
Software Reset Sources
-
-
CHIP Reset: writing 1 to CHIPRST (SYS_IPRST0[0]) will reset whole chip.
MCU Reset: writing 1 to SYSRESETREQ (AIRCR[2]) will reboot the device,
according to the boot selection defined in configuration byte CONFIG0.
CPU Reset: writing 1 to CPURST (SYS_IPRST0[1]) will reset Cortex®-M4 core
Only.
-
6.2.3
System Power Distribution
ISD94100 series device power distribution is divided into:
Analog power from AVDD and AVSS : provides the power for analog components
operation.
Digital power from VDD and VSS : supplies the power to the internal regulator which
provides a regulated 1.2 V power for digital operation.
USB transceiver power from USB_VDD33 offers the power for operating the USB
transceiver.
Analog power (AVDD) should be at the same voltage level as digital power (VDD).
Both power supplies should have decoupling capacitors placed as close as possible to pins
preferably with no via.
The outputs of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to LDO_CAP pin and returned directly to VSS. The Figure 6.2-1 shows the power
distribution of the ISD94100 series.
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ISD94100 Series Datasheet
USB 1.1
PHY
Digital
Logic
SRAM
Flash
IO Cell
PB.13~PB.15
1.2V
LDO_CAP
1uF
AVDD
AVSS
PLL
POR12
12-bit ADC
4~24.576
MHz crystal
oscillator
PB.5
PB.6
Power On
Control
VDD to 1.2V
LDO
GPIOs except
PB.13~PB.15
POR33
IO Cell
32.768 kHz
crystal
oscillator
Low Voltage Reset
Brown-out Detector
48.0/49.152
MHz HIRC
Oscillator
10 KHz
LIRC
Oscillator
PC.0
PC.1
ISD94100 Series Power Distribution
Figure 6.2-1 ISD94100 Series Power Distribution Diagram
6.2.4
System Memory Map
The ISD94100 series provides 4G-byte addressing space. The memory addresses assigned to
each on-chip controllers are shown in Table 6.2.4-1. The detailed register definition, memory space,
and programming will be described in the following sections for each on-chip peripheral. The
ISD94100 series only supports little-endian data format.
Token
Controllers
Address Space
Flash and SRAM Memory Space
0x0000_0000 – 0x0007_FFFF
0x2000_0000 – 0x2000_7FFF
0x2000_8000 – 0x2002_FFFF
FLASH_BA
SRAM0_BA
SRAM1_BA
FLASH Memory Space (512 Kbytes)
SRAM Memory Space (32 Kbytes)
SRAM Memory Space (160 Kbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
SYS_BA
CLK_BA
NMI_BA
GPIO_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO Control Registers
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ISD94100 Series Datasheet
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4003_1000 – 0x4003_1FFF
PDMA_BA
FMC_BA
CRC_BA
Peripheral DMA Control Registers
Flash Memory Control Registers
CRC Generator Registers
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_8000 – 0x4004_8FFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4006_2000 – 0x4006_2FFF
0x4006_3000 – 0x4006_30FF
0x4006_3100 – 0x4006_3FFF
0x4006_4000 – 0x4006_4FFF
0x4007_0000 – 0x4007_0FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x400C_0000 – 0x400C_0FFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Enhanced Analog-Digital-Converter (EADC) Control Registers
I2S0 Interface Control Registers
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
PWM0 Control Registers
EADC_BA
I2S0_BA
TMR01_BA
TMR23_BA
PWM0_BA
SPI0_BA
SPI1_BA
SPI2_BA
DMIC_BA
VAD_BA
SPI0 Control Registers
SPI1 Control Registers
SPI2 Control Registers
DMIC Control Registers
VAD Control Registers
DPWM_BA
UART0_BA
I2C0_BA
DPWM Control Registers
UART0 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
USBD_BA
USB Device Control Register
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2.4-1 Address Space Assignments for On-Chip Controllers
6.2.5
SRAM Memory Organization
The ISD94100 series supports up to 192 KB of embedded SRAM and the SRAM organization is
separated to two banks: SRAM bank0 and SRAM bank1. The SRAM bank0 supports parity error
check to make sure chip operating more stable.
Supports up to 192 KB of SRAM
Supports byte / half word / word write
Supports parity error check function for SRAM bank0
Supports oversize response error
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AHB interface
controller
SRAM decoder
SRAM bank0
SRAM bank1
AHB interface
controller
SRAM decoder
Figure 6.2-2 SRAM Block Diagram
0x3FFF_FFFF
Reserved
0x2003_0000
0x2002_FFFF
160 KB
SRAM
0x2000_8000
0x2000_7FFF
32 KB
SRAM
0x2000_0000
Figure 6.2-3 SRAM Memory Organization
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SRAM address from 0x2000_0000 to 0x2000_7FFF has byte parity error check function. When
CPU is accessing SRAM address from 0x2000_0000 to 0x2000_7FFF the parity error checking
mechanism is operating dynamically. If parity error occurrs, the PERRIF (SYS_SRAM_STATUS[0])
will be asserted to 1 and the SYS_SRAM_ERRADDR register will record the address with parity
error. Chip will enter interrupt when SRAM parity error occurs if PERRIEN (SYS_SRAM_INTCTL[0])
is set to 1. When SRAM parity error occurs, chip will stop detecting SRAM parity errors until user
writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.
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6.2.6
System Timer (SysTick)
The Cortex®-M4 integrates a system timer, SysTick, which provides a simple, 24-bit clear-on-write,
decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used
as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the
counter decrements to zero, the COUNTFLAG status bit is set. A read or write on Current Value
Register clears the COUNTFLAG bit to 0.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_LOAD value
rather than an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex™-M4 Technical Reference Manual”
and “ARM® v6-M Architecture Reference Manual”.
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6.2.7
Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the
NVIC from privileged mode, but you can cause interrupts to enter a pending state in user mode if
you enable the Configuration and Control Register. Any other user mode access causes a bus fault.
You can access all NVIC registers using byte, halfword, and word accesses unless otherwise stated.
NVIC registers are located within the SCS (System Control Space). All NVIC registers and system
debug registers are little-endian regardless of the endianness state of the processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-16 for each interrupt; a higher level corresponds to
a lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
6.2.7.1 Exception Model and System Interrupt Map
The Table 6.2.7-1 lists the exception model supported by ISD94100 Series. Software can set 16
levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0x00” and the lowest priority is denoted as “0xF0” (The 4-LSB
always 0). The default priority of all the user-configurable interrupts is “0x00”. Note that priority “0”
is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and
“Hard Fault”.
When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is
fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table
start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
The vector table contains the initialization value for the stack pointer on reset, and the entry point
addresses for all exception handlers. The vector number on previous page defines the order of
entries in the vector table associated with exception handler entry as illustrated in previous section.
Vector Number
Vector Address
Priority
Exception Type
Reset
0x00000004
1
-3
NMI
2
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
-2
Hard Fault
Memory Manager Fault
Bus Fault
3
-1
4
Configurable
Configurable
Configurable
Reserved
Configurable
Configurable
5
Usage Fault
Reserved
6
7 ~ 10
11
SVCall
0x0000002C
0x00000030
Debug Monitor
12
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Reserved
PendSV
SysTick
13
14
15
Reserved
0x00000038
0x0000003C
Configurable
Configurable
0x00000000 +
Interrupt (IRQ0 ~ IRQ)
16 ~ 111
Configurable
(Vector Number)*4
Table 6.2.7-1 Exception Model
Interrupt Number
(Bit In Interrupt
Vector
Number
Interrupt Name
Interrupt Description
Registers)
0 ~ 15
-
-
System exceptions
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 ~ 37
38
39
40
41
0
BODOUT
IRC_INT
PWRWU_INT
SRAM_PERR
CLKFAIL
Reserved
RTC_INT
Reserved
WDT_INT
WWDT_INT
EINT0
Brown-Out low voltage detected interrupt
IRC TRIM interrupt
1
2
Clock controller interrupt for chip wake-up from power-down state
SRAM parity check error interrupt
Clock fail detected interrupt
Reserved
3
4
5
6
Real time clock interrupt
Reserved
7
8
Watchdog Timer interrupt
Window Watchdog Timer interrupt
External interrupt
9
10
11
12
13
14
15
16
17
18
19
20 ~ 21
22
23
24
25
EINT1
External interrupt
EINT2
External interrupt
EINT3
External interrupt
EINT4
External interrupt
EINT5
External interrupt
GPA_INT
GPB_INT
GPC_INT
GPD_INT
Reserved
SPI0_INT
SPI1_INT
BRAKE0_INT
PWM0_P0_INT
External interrupt from PA[15:0] pin
External interrupt from PB[14:12/9:0] pin
External interrupt from PC[15:0] pin
External interrupt from PD[15:0] pin
Reserved
SPI0 interrupt
SPI1 interrupt
PWM0 brake interrupt
PWM0 pair 0 interrupt
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42
26
PWM0_P1_INT
PWM0_P2_INT
Reserved
PWM0 pair 1 interrupt
43
27
PWM0 pair 2 interrupt
Reserved
44 ~ 47
48
28 ~ 31
32
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
Reserved
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
Reserved
49
33
50
34
51
35
52
36
53
37
54
38
I2C0_INT
I2C0 interrupt
I2C1 interrupt
PDMA interrupt
Reserved
55
39
I2C1_INT
56
40
PDMA_INT
Reserved
57
41
58
42
EADC0_INT
EADC1_INT
Reserved
EADC interrupt source 0
EADC interrupt source 1
Reserved
59
43
60
44
61
45
Reserved
Reserved
62
46
EADC2_INT
EADC3_INT
Reserved
EADC interrupt source 2
EADC interrupt source 3
Reserved
63
47
64 ~ 66
67
48~ 50
51
SPI2_INT
SPI2 interrupt
DMIC interrupt
USB device interrupt
Reserved
68
52
DMIC_INT
USBD_INT
Reserved
69
53
70 ~ 71
72
54 ~ 55
56
VAD_INT
VAD interrupt
73 ~ 77
78
57 ~ 61
62
Reserved
Reserved
DPWM_INT
Reserved
DPWM interrupt
Reserved
79 ~ 83
84
63 ~ 67
68
I2S0_INT
I2S0 interrupt
85 ~ 111
69 ~ 95
Reserved
Reserved
Table 6.2.7-2 Interrupt Number Table
6.2.7.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable
or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When
an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however,
the interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state
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until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down
mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex®-M4 core
executes the WFI instruction. After that, chip enters Power-down mode and wait for wake-up
interrupt source triggered to leave Power-down mode. In Power-down mode, the clock controller
turns off the 4~24.576 MHz external high speed crystal (HXT) and internal high speed RC oscillator
(HIRC) to reduce the overall system power consumption. The Figure 6.3-1 shows the clock
generator and the overview of the clock source control.
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HIRC
48 / 49.152
MHz
HXT
4~24.576
MHz
LXT
32.768
kHz
LIRC
10
kHz
CPU
CRC
PWM0
I2C0
EADC
I2C1
FMC
SPI0
RTC
PCLK0
PCLK1
HIRC
HXT
PDMA
SRAM
/1,/2,/4,/8,/16
SPI2
SPI1
1
0
PLLFOUT
PLL FOUT
TMR0
TMR1
I2S
TMR2
TMR3
DMIC
CLK_PLLCTL[19]
HIRC
DPWM
111
011
010
001
000
LIRC
PLLFOUT
HCLK
1/(HCLKDIV+1)
/1,/2,/4,/8,/16
PCLK1
LXT
HXT
1/(EADCDIV+1)
1
EADC
CLK_CLKSEL0[2:0]
LIRC
11
10
01
PCLK0
HCLK
PWM 0
1/2048
LXT
WDT
PLLFOUT
0
CLK_CLKSEL2[0]
CLK_CLKSEL1[1:0]
LIRC
HIRC
11
11
10
LXT
WWDT
10
HCLK
1/2048
1/(UART0DIV+1)
UART0
PLLFOUT
HXT
01
00
CLK_CLKSEL1[31:30]
HIRC
1/2
111
011
010
001
000
CPUCLK
CLK_CLKSEL1[25:24]
HCLK
1/2
1
0
SysTick
HXT
1/2
DIV1EN
(CLK_CLKOCTL[5])
CLK1HZEN
HIRC
LXT
11
10
(CLK_CLKOCTL[6])
SYST_CTRL[2]
HCLK
LXT
HXT
/2(CLK_CLKOCTL[3:0]+1)
0
1
01
00
0
1
CLKO
CLK_CLKSEL0[5:3]
HXT
LIRC
LXT
1
0
CLK_CLKSEL1[29:28]
LIRC
RTC
/10000
/32768
1
1 Hz clock from RTC
CLK_CLKSEL3[8]
LXT
0
RTCSEL(CLK_CLKSEL3[8])
HIRC
HIRC
11
10
01
00
11
10
01
00
PCLK0
PLLFOUT
HXT
PCLK1
PLLFOUT
HXT
SPI0
SPI2
1/(SPI0_CLKDIV[8:0]+1)
1/(SPI2_CLKDIV[8:0]+1)
1/(SPI1_CLKDIV[8:0]+1)
SPI1
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
CLK_CLKSEL2[5:4]
HIRC
LIRC
HIRC
LIRC
111
101
011
010
001
000
111
101
011
010
001
000
TM0/TM1
TM2/TM3
PCLK1
TMR0
TMR1
TMR2
TMR3
PCLK0
LXT
LXT
HXT
HXT
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
HIRC
HIRC
11
10
01
00
11
10
01
00
PCLK1
PLLFOUT
HXT
PCLK0
PLLFOUT
HXT
DMIC
DPWM
CLK_CLKSEL2[11:10]
CLK_CLKSEL2[13:12]
PLLFOUT
HIRC
HIRC
1
48MHz
11
10
/(USBDIV + 1)
/4
USB1.1 PHY
PCLK0
PLLFOUT
HXT
0
I2S
CLK_CLKSEL4[24]
01
00
USB1.1 Device
Controller
CLK_CLKSEL3[17:16]
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2
Clock Generator
Five clock sources can be used to drive all the internal clocks:
32.768 kHz external low speed crystal oscillator (LXT)
4~24.576 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~24.576 MHz external high speed crystal (HXT) or internal high speed
oscillator (HIRC)
Selectable 48.0 MHz or 49.152 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External
LXT
32.768 kHz
Crystal
(LXT)
X32_OUT
XT1_IN
HXTEN (CLK_PWRCTL[0])
HXT
External
4~24.576 MHz
Crystal
PLLSRC (CLK_PLLCTL[19])
(HXT)
XT1_OUT
0
1
PLL FOUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal
48.0/49.152 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal
10 kHz
Oscillator
(LIRC)
Figure 6.3-2 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
Five clock sources can be used to drive the system clock (HCLK), as shown in Figure 6.3-3. Clock
source can be chosen by configuring HCLKSEL bits(CLK_CLKSEL0[2:0]).
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Figure 6.3-3 System Clock Block Diagram
There are two clock failure detectors monitoring HXT and LXT; each has its own enabling and
interrupt control.
If HXT failure detector is enabled, the HIRC clock will be also enabled automatically. The clock
controller will automatically switch the system clock (HCLK) source from HXT to HIRC if the
following conditions are met:
HCLK clock source was from HXT, or from PLLOUT and PLL source clock was from HXT,
HXT clock failure has been detected.
An HXT clock failure condition will set HXTFIF bit (CLK_CLKDSTS[0]) 1, and raise an HXT failure
interrupt if HXTFIEN (CLK_CLKDCTL[5]) is enabled.
To recover from HXT failure, user can first disable HXT, then enable HXT, and then check if the
HXT clock stable bit HXTSTB (CLK_STATUS[0]) is 1. HXTSTB bit being 1 means HXT is recovered
and enabled so that system clock source can be switched to HXT again.
The hardware procedure of HXT failure detection and system clock source auto switch to HIRC is
shown in the Figure 6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
The SysTick clock source can be from CPU clock or external reference clock, determined by
CLKSRC bit (SYST_CTRL[2]).
If CLKSRC = 1, CPU core clock is used for SysTick,
If CLKSRC = 0, SysTick clock source is from one of the 5 external reference clock, which
is chosen by STCLKSEL bits (CLK_CLKSEL0[5:3]), shown in Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4
Peripheral Clock
Each peripheral module can have its own clock source selection and configuration, please refer to
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CLK_CLKSEL1 and CLK_CLKSEL2 register description for more detailed information.
6.3.5 Power-down Mode Clock
Different power down modes have different impact on the system clocks. Under a certain power
down mode, some clock sources (including system clocks and peripheral clocks) are disabled
while some other clock sources are still available. However regardless the power down mode the
following clocks are always available:
Clock Generator
10 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripheral Clock which uses LXT or LIRC as clock source
6.3.6
Clock Output
The ISD94100 series device is equipped with a power-of-2 frequency divider which is composed of
16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to
one multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2
divided clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing
0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches
low state and stays in low state.
CLKOEN
Enable
(CLK_CLKOCTL[4])
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
CLK1HZEN
(CLK_CLKOCTL[6])
0000
0001
:
HIRC
16 to 1
MUX
11
10
01
00
0
1
:
0
1
1110
CLKO
HCLK
LXT
1111
HXT
RTCSEL(CLK_CLKSEL3[8])
CLKOSEL (CLK_CLKSEL1[29:28])
LIRC
LXT
/10000
/32768
0
1
1 Hz clock from RTC
Figure 6.3-6 Clock Output Block Diagram
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ISD94100 Series Datasheet
6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The ISD94100 Series provides up to 512 KB of on-chip embedded flash for application program
memory (APROM) and data flash. In-System-Programming (ISP) and In-Application-Programming
(IAP) enables user to update chip embedded flash when chip is soldered on PCB. After chip
powers-on, Cortex®-M4 CPU fetches code from APROM or LDROM depending on the boot select
(CBS) configuration in CONFIG0. The ISD94100 Series also provides Data Flash for user to store
some application dependent data to be retained when chip is powered off.
The ISD94100 Series supports configurable data flash size. The data flash size is decided by data
flash enable (DFEN) in CONFIG0 and data flash base address (DFBA) in CONFIG1. When DFEN
is set to 1, the data flash size is zero. When DFEN is set to 0, the APROM and data flash share
512 KB continuous address and the start address of data flash is defined by (DFBA) in CONFIG1.
6.4.2
Features
Supports up to 512 KB of application ROM (APROM).
Supports 4 KB loader ROM (LDROM).
Supports Data Flash with configurable memory size.
Supports 12 bytes User Configuration block to control system initiation.
Supports 4 KB page erase for all embedded flash.
Supports 32-bit/64-bit and multi-word flash programming function.
Supports fast flash programming verification function.
Supports CRC32 checksum calculation function.
Supports flash all one verification function
Supports cache memory to improve flash access performance and reduce power
consumption.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
Supports cache memory to improve flash access performance and reduce power
consumption.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The ISD94100 series device has up to 58 General Purpose I/O (GPIO) pins, grouped in 4 ports PA,
PB, PC and PD. Port PA, PC and PD each has 16 pins, and there are 13 pins in Port PB.
All the GPIO pins are multi-functional pins, in that they can be I/O pins or they can work as alternate
function pins. Each pin can be individually configured. Pin function are defined in MFP registers, for
example PA0~7 pin functions are defined in SYS_GPA_MFPL register.
When working as an I/O pin, each pin can be configured by software in several modes:
Input
Push-pull Output
Open-Drain Output
Quasi-bidirectional
After a power-on or reset event, all GPIO pins’ default working mode are determined by CIOINI bit
(CONFIG0[10]) except PA.8. PA.8 pin default I/O mode is determined by GPA8_LOW bit
(CONFIG0[11]). Every I/O pin has a weak pull-up resistor with value ~50 k when I/O pin configured
as quasi-bidirectional output low.
6.5.2
Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input capability
I/O pin can be configured as interrupt source with edge/level trigger option
Supports High Drive and High Slew Rate I/O mode
CIOINI bit (CONFIG0[10]) configures all GPIO pins’ default I/O mode except PA.8 after
power-on or reset:
CIOINI = 0: Quasi-bidirectional mode,
CIOINI = 1: input mode.
GPA8_LOW (CONFIG[11]) configures PA.8 pin’s default I/O mode after power-on or reset:
GPA8_LOW = 0: Push-Pull mode and output low,
GPA8_LOW = 1: PA.8 follows CIOINI setting.
I/O pin internal pull-up only available in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
PB0 ~ PB4, PB7 ~ PB9, PB13 ~ PB15, PC2 ~ PC15 and PD0 ~ PD15 support 5V-tolerance
functions
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other
applications. The PDMA controller has a total of 16 channels and each channel can perform transfer
between memory and peripherals or between memory and memory.
6.6.2
Features
Supports 16 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word
or no increment
Supports software and SPI, UART, ADC and PWM request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of
the descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
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6.7 Timer Controller (TMR)
6.7.1 Overview
The Timer controller contains four 32-bit multi-functional timers, Timer0, 1, 2 and 3. These timers
can be used to count, or time external events that drive the Timer input pins.
Or the four timers can be configured as four PWM generators; each can support two PWM output
channels in independent or complementary mode. The output state of PWM output pin can be
control by pin mask, polarity, and dead-time generator.
6.7.2
Features
6.7.2.1 Timer Function Features
Four sets of 32-bit timers, each timer equips one 24-bit up counter and one 8-bit prescaler
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM,
EADC and PDMA function
Supports Inter-Timer trigger mode
6.7.2.2 PWM Function Features
Supports maximum clock frequency up to maximum PCLK
Supports independent mode for PWM generator with two output channels
Supports complementary mode for PWM generator with paired PWM output channel
12-bit dead-time insertion with 12-bit prescaler
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit PWM counter
Up, down and up-down count operation type
One-shot or auto-reload counter operation mode
Supports mask function and tri-state enable for each PWM output pin
Supports interrupt on the following events:
PWM zero point, period point, up-count compared or down-count compared point
events
Supports trigger ADC on the following events:
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PWM zero point, period, zero or period point, up-count compared or down-count
compared point events
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6.8 PWM Generator and Capture Timer (PWM)
6.8.1 Overview
The ISD94100 series provides one PWM generators － PWM0. It supports 6 channels of PWM
output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM
counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.
PWM using comparator compared with counter to generate events. These events use to generate
PWM pulse, interrupt and trigger signal for EADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. There are two output functions based on
standard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled under
complementary mode. Complementary mode has two comparators to generate various PWM pulse
with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for
EADC. For PWM output control unit, it supports polarity output, independent pin mask and brake
functions.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition
is happened. Capture function also support PDMA to transfer captured data to memory.
6.8.2
Features
6.8.2.1 PWM function features
Clock source supports maximum clock frequency up to 200 MHz
Supports up to 6 output channels.
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Synchronous function for phase control
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin, system safety events (clock failed, SRAM parity error,
Brown-out detection and CPU lockup).
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
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Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger EADC on the following events:
PWM counter match zero, period value or compared value
PWM counter match free trigger comparator compared value (only for EADC)
6.8.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.9 Watchdog Timer (WDT)
6.9.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.9.2
Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset
delay period
Supports to force WDT enabled after chip power-on or reset by setting CWDTEN[2:0] in
CONFIG0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz or
LXT.
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6.10 Window Watchdog Timer (WWDT)
6.10.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.10.2 Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value (CMPDAT,
WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.11 Real Time Clock (RTC)
6.11.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
message are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
6.11.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) setting in
RTC_TALM and RTC_CALM
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in
RTC_TAMSK and RTC_CAMSK
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counter in RTC_WEEKDAY register
Frequency of RTC clock source compensate by RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
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6.12 UART Interface Controller (UART)
6.12.1 Overview
The ISD94100 series is equipped with one Universal Asynchronous Receiver/Transmitters (UART)
port, which offers a mean of full-duplex asynchronous communication with external device.
The ISD94100 series UART controller also supports RS-485 standard.
6.12.2 Features
One UART port: UART0.
Programmable baud-rate generator
Separate receive (RX) and transmit (TX) FIFOs with 16 bytes each to reduce CPU interrupt
service loading
RX FIFO trigger level of 1/16, 4/16, 8/16 and 14/16.
Supports hardware auto-flow control
Supports wake-up function which can be triggered by nCTS, incoming data, RX FIFO reached
threshold or RS-485 Address Match (AAD mode).
Supports 8-bit RX FIFO time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface characteristics
5, 6, 7, or 8 data bits
even, odd, stick or no-parity generation/detection
1, 1.5, or 2 stop bit generation
Support PDMA transfer function
Supports RS-485 function mode
RS-485 9-bit mode
hardware or software managing nRTS pin to control RS-485 transmission direction
UART Feature
UART0
FIFO
16 Bytes
Auto Flow Control (CTS/RTS)
RS-485 Function Mode
nCTS Wake-up
√
√
√
√
Incoming Data Wake-up
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RX FIFO reached threshold
Wake-up
√
√
RS-485 Address Match (AAD
mode) Wake-up
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
1, 1.5, 2 bit
5, 6, 7, 8 bits
√
Even / Odd Parity
Stick Bit
√
√= Supported
Table 6.12.2-1 UART Feature
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6.13 I2C Serial Interface Controller (I2C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The ISD94100 series device provides two sets of I2C controller which
can function as either master or slave, provide multi-master capability, support up to 1Mbs transfer
rate.
The ISD94100 I2C module can also be used for a variety of purposes, including CRC verification,
SMBus (System Management Bus) and PMBus (Power Management Bus).
6.13.2 Features
The ISD94100 series I2C module supports the following features:
Two I2C ports
Master, Salve and Multi-master mode operation
Support High speed mode 3.4Mbps
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-
out counter overflows
Programmable clocks allow for versatile rate control
7-bit and 10-bit addressing mode
Multiple address recognition ( four slave address with mask option)
Power-down wake-up function
PDMA capability with one buffer
Programmable setup/hold time
Bus Management (SM/PM compatible) function
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6.14 Serial Peripheral Interface (SPI)
6.14.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication interface. SPI
devices communicate in full duplex mode using a master-slave architecture. The single master and
the slave(s) communicate bi-directionally through a 4-wire interface.
The ISD94100 series contains up to three sets of SPI controllers which perform serial-to-parallel
conversion when receiving data from a peripheral device, and parallel-to-serial conversion when
transmitting data to a peripheral device. Each SPI controller can be configured as a master or a
slave device.
SPI0 controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode. SPI1 and SPI2 controllers support I2S mode to connect
external audio CODEC. Each SPI controller supports the PDMA function to access the data buffer.
6.14.2 Features
SPI Mode
Up to three sets of SPI controllers
Supports Master or Slave mode operation
Master mode up to 25 MHz and Slave mode up to 25 MHz (when chip works at VDD =
2.7~3.6V)
Supports 2-bit Transfer mode (SPI0 Only)
Supports Dual and Quad I/O Transfer mode (SPI0 Only)
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface (SPI0 Only)
Supports one data channel half-duplex transfer
Support receive-only mode
I2S Mode (for SPI1~SPI2)
Supports Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Each provides two 4-level FIFO data buffers, one for transmitting and the other for receiving
Supports monaural and stereo audio data
Supports PCM mode A, PCM mode B, I2S and MSB justified data format
Supports two PDMA requests, one for transmitting and the other for receiving
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SPI0
V
SPI1 / SPI2
Dual/Quad I/O Mode
X
X
Two-Bit Transfer Mode
V
SPI mode 8~16 bits data length: 8-level
Otherwise: 4-level
FIFO Depth
8-level
Slave Time-out Function
Slave 3-Wired Mode
I2S Mode
V
V
X
X
X
V
Table 6.14.2-1 SPI feature difference (SPI0~SPI2)
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6.15 CRC Controller (CRC)
6.15.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable
polynomial settings.
6.15.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.16 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.16.1 Overview
The ISD94100 series contains one 12-bit successive approximation analog-to-digital converter
(SAR ADC converter) with 13 external input channels. The ADC converter can be started by
software trigger, PWM0 triggers, timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC
(End of conversion) pulse trigger and external pin (EADC0_ST) input signal.
6.16.2 Features
Analog input voltage range: 0~AVDD.
Reference voltage from AVDD.
12-bit resolution and 9-bit accuracy is guaranteed.
Up to 13 single-end analog external input channels.
Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses.
Maximum ADC clock frequency is 60 MHz.
Up to 2 MSPS conversion rate.
Configurable ADC internal sampling time.
12-bit, 10-bit, 8-bit, 6-bit configurable resolution.
Supports calibration capability when EADC enabled.
Supports three power saving modes:
Deep Power-down mode
Power-down mode.
Standby mode.
Up to 13 sample modules
Each of sample modules which is configurable for ADC converter channel
EADC_CH0~12 and trigger source.
Double buffer for sample control logic module 0~3
Configurable sampling time for each sample module.
Conversion results are held in 13 data registers with valid and overrun indicators.
An ADC conversion can be started by:
Write 1 to SWTRGn (EADC_SWTRG[n] , n = 0~12)
External pin EADC0_ST
Timer0~3 overflow pulse triggers
ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
PWM triggers
Supports PDMA transfer
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6.17
I2S Controller (I2S)
6.17.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 16-level
depth FIFO for reading path and writing path respectively and is capable of handling 8/16/24/32 bits
audio data sizes. PDMA controller handles the data movement between FIFO and memory.
6.17.2 Features
Support Master mode and Slave mode
Capable of handling 8, 16, 24 and 32 bits data sizes in each audio channel
Supports monaural and stereo audio data
Supports I2S protocols: Philips standard, MSB-justified, and LSB-justified data format
Supports PCM protocols: PCM standard, MSB-justified, and LSB-justified data format
PCM protocol supports TDM multi-channel transmission in one audio sample, and the
number of data channel can be set as 2, 4, 6, or 8
Provides two 16-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two PDMA requests, one for transmitting and the other for receiving
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6.18 USB 1.1 Device Controller (USBD)
6.18.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous
transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 1KBytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGx).
There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS0 and
USBD_EPSTS1) to acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable
the SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
6.18.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 1KBytes buffer size
Provides remote wake-up capability
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6.19 Digital Microphone Inputs (DMIC)
6.19.1 Overview
Using the dual channel digital PDM (Pulse Density Modulation) microphone interface (DMIC_CLK0,
DMIC_DAT0, DMIC_CLK1 and DMIC_DAT1 pins) that are handled four digital PDM microphone
inputs. Both DMIC_DAT0 and DMIC_DAT1 inputs are able to handle two digital microphones by
selecting them alternately for each half of the clock cycle.
6.19.2 Features
The digital microphone interface use two wires (DMIC_DATn and DMIC_CLKn) to receive
information from digital microphones. The main features of DMIC includes:
Provides one 32-level FIFO data buffers for receiving.
Generates interrupt requests when buffer levels cross a programmable boundary.
Supports PDMA transfer.
Supports up to four channel digital microphones.
Both digital PDM microphone inputs can be used simultaneously.
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6.20 Voice Active Detection (VAD)
6.20.1 Overview
The Voice Active Detection (VAD) analyses the PCM data from DMIC channel 0, and it consists of
a SINC filter, a biquad filter and a VAD module. The idea of the VAD is to calculate the short term
power and long term power of the input signal, and then compare the short term power with the
short term power threshold. Moreover, the deviation of the short term power and long term power
can be calculated and compared with the threshold deviation. Based on these two results, which
can determine if the input signal is voice or not.
VAD can be active during idle mode and therefore provide lowest power operation, compared with
a software based implementation.
6.20.2 Features
Configuration detect levels.
Supports idle mode wake-up function.
Supports auto switch DMIC path when CPU wake-up by VAD.
Generates interrupt requests when voice detected.
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6.21 Audio DPWM Modulator (DPWM)
6.21.1 Overview
The DPWM modulator is sigma-delta modulator which is for class D amplifer. ISD94100 series has
3 DPWM modulator and each one can provide 2 differential bits.
6.21.2 Features
Differential Audio PWM Output (DPWM)
Support left channel,right channel and sub-woofer channel.
Support sample rates from 16~96kHz.
Programeable biquad filter with 10 band
PDMA data channel for streaming of PCM audio data.
Support the single precision floating point for input data and BIQ coefficient
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
7.1.1 Voltage Characteristics
Symbol
VDD VSS
Parameter
Min
Max
+3.6
VDD + 0.3
50
Unit
V
DC Power Supply
-0.3
VIN
Input Voltage
VSS - 0.3
V
|VDD - AVDD
|
Allowed voltage difference for VDD and AVDD
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance GPIO
Input voltage on any other pin[2]
-
-
-
-
mV
mV
V
|VSS – AVSS
|
50
5.5
VIN
VDD
V
Note:
1. Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life
and reliability of the device.
2. Non 5V-tolerance PIN: PA0 ~ PA15, PB5, PB6, PC0 and PC1.
Table 7.1.1-1 Voltage characteristics
7.1.2
Current Characteristics
Symbol
Parameter
Min
Max
200
100
20
Unit
–
IDD
Maximum Current into VDD
-
-
-
-
-
-
ISS
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
mA
20
IIO
100
100
Table 7.1.2-1 Current characteristics
Thermal Characteristics
7.1.3
Symbol
TA
Parameter
Operating Temperature
Storage Temperature
Min
Max
+85
Unit
-40
-55
℃
TST
+150
Table 7.1.3-1 Thermal characteristics
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7.1.4
Electrostatic Discharge (ESD) Ratings
Symbol
VESD
Note:
Ratings
ESD for Human Body Model (HBM)
Max
Unit
4
kV
1. This is guaranteed by characterization results, not tested in production
Table 7.1.4-1 Electrostatic Discharge (ESD) Ratings
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7.2 General Operating Conditions
(VDD - VSS = 1.8 ~ 3.3 V, TA = 25C)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Internal
Frequency
AHB
Clock
fHCLK
-
-
200
MHz
Typical Operation
Voltage
VDD
1.8[1]
-
3.3[1]
V
V
Analong Operation
Voltage
AVDD
VDD
USB_VDD33 USB Operation Voltage
3.0
-
1.2
1
3.6
V
V
VLDO
CLDO
LDO Output Voltage
Normal mode
LDO Output Capacitance
on LDO_CAP Pin
-
-
uF
Note:
1. The limitation of VDD operation voltage is 1.62V ~ 3.6V.
Table 7.2-1 General Operating Conditions
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7.3 DC Electrical Characteristics
(VDD - VSS = 1.8 ~ 3.3 V, TA = 25C)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
3.3 V
HXT_GM
HIRC
Disabled
Enabled
Disabled
Enabled
IDD5
-
10
16
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3 V
Disabled
Enabled
Disabled
Disabled
IDD6
IDD7
IDD8
-
-
-
8
10
8
12
16
12
mA
mA
mA
PLL
Operating Current
Normal Run Mode
HCLK = 49.152 MHz
while(1){}
All digital
modules
VDD
HXT_GM
HIRC
1.8 V
executed from flash
Disabled
Enabled
Disabled
Enabled
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8 V
Disabled
Enabled
Disabled
Disabled
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}
12 MHz
Disabled
Disabled
Enabled
IDD5
-
5
-
mA
PLL
executed from flash
All digital
modules
Sep 09, 2019
Page 79 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
3.3V
HXT_GM
HIRC
12 MHz
Disabled
Disabled
Disabled
IDD6
-
3.2
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
12 MHz
Disabled
Disabled
Enabled
IDD7
-
4.8
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
12 MHz
Disabled
Disabled
Disabled
IDD8
-
3
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
12 MHz
Disabled
160 MHz
Enabled
IDD9
-
31
-
mA
PLL
Operating Current
Normal Run Mode
HCLK = 160 MHz
while(1){}
All digital
modules
VDD
HXT_GM
HIRC
3.3V
executed from flash
12 MHz
Disabled
160 MHz
Disabled
IDD10
-
21
-
mA
PLL
All digital
modules
Sep 09, 2019
Page 80 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
1.8V
HXT_GM
HIRC
12 MHz
Disabled
160 MHz
Enabled
IDD11
-
30.5
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
12 MHz
Disabled
160M
IDD12
-
-
-
-
-
20.7
-
-
-
-
-
mA
mA
mA
mA
mA
PLL
All digital
modules
Disabled
VDD
HXT_GM
HIRC
3.3 V
12 MHz
Disabled
200 MHz
Enabled
IDD9
39
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3 V
12 MHz
Disabled
200 MHz
Disabled
IDD10
IDD11
IDD12
26.6
38.5
26.3
PLL
Operating Current
Normal Run Mode
HCLK = 200 MHz
while(1){}
All digital
modules
VDD
HXT_GM
HIRC
1.8 V
executed from flash
12 MHz
Disabled
200 MHz
Enabled
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8 V
12 MHz
Disabled
200 MHz
Disabled
PLL
All digital
modules
Sep 09, 2019
Page 81 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
3.3V
HXT_GM
HIRC
4 MHz
Disabled
Disabled
Enabled
IDD13
-
3.5
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
4 MHz
Disabled
Disabled
Disabled
IDD14
IDD15
IDD16
IIDLE1
-
-
-
-
2.4
3.2
2
-
mA
mA
mA
mA
PLL
Operating Current
Normal Run Mode
HCLK =4 MHz
All digital
modules
VDD
HXT_GM
HIRC
1.8V
while(1){}
executed from flash
4 MHz
Disabled
Disabled
Enabled
-
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
4 MHz
Disabled
Disabled
Disabled
-
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
Disabled
Enabled
Disabled
Enabled
Operating Current
Idle Mode
6.1
10
HCLK = 49.152 MHz
PLL
All digital
modules
Sep 09, 2019
Page 82 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
3.3V
HXT_GM
HIRC
Disabled
Enabled
Disabled
Disabled
IIDLE2
-
2.8
6
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
Disabled
Enabled
Disabled
Enabled
IIDLE3
IIDLE4
IIDLE5
IIDLE6
-
-
-
-
6.1
2.8
3.5
2.3
10
6
-
mA
mA
mA
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
Disabled
Enabled
Disabled
Disabled
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
12 MHz
Enabled
Disabled
Enabled
PLL
All digital
modules
Operating Current
Idle Mode
VDD
HXT_GM
HIRC
3.3V
HCLK =12 MHz
12 MHz
Enabled
Disabled
Disabled
-
PLL
All digital
modules
Sep 09, 2019
Page 83 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
1.8V
HXT_GM
HIRC
12 MHz
Enabled
Disabled
Enabled
IIDLE7
-
3.4
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
12 MHz
Enabled
Disabled
Disabled
IIDLE8
-
2.1
19.6
8.5
-
mA
mA
mA
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
12 MHz
Disabled
160 MHz
Enabled
IIDLE9
-
-
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
12 MHz
Disabled
160 MHz
Disabled
Operating Current
Idle Mode
IIDLE10
HCLK =160 MHz
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
12 MHz
Disabled
160 MHz
Enabled
IIDLE11
-
19.4
-
PLL
All digital
modules
Sep 09, 2019
Page 84 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
1.8V
HXT_GM
HIRC
12 MHz
Disabled
160 MHz
Disabled
IIDLE12
-
8.3
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3 V
12 MHz
Disabled
200 MHz
Enabled
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
-
24.9
10.6
24.5
10.3
2.6
-
mA
mA
mA
mA
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3 V
12 MHz
Disabled
200 MHz
Disabled
PLL
All digital
modules
Operating Current
Idle Mode
VDD
HXT_GM
HIRC
1.8 V
HCLK =200 MHz
12 MHz
Disabled
200 MHz
Enabled
-
-
-
-
-
-
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8 V
12 MHz
Disabled
200 MHz
Disabled
PLL
All digital
modules
VDD
HXT_GM
HIRC
3.3V
4 MHz
Operating Current
Idle Mode
Disabled
Disabled
Enabled
HCLK =4 MHz
PLL
All digital
modules
Sep 09, 2019
Page 85 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
3.3V
HXT_GM
HIRC
4 MHz
Disabled
Disabled
Disabled
IIDLE14
-
2
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
4 MHz
Disabled
Disabled
Enabled
IIDLE15
-
2.3
-
mA
PLL
All digital
modules
VDD
HXT_GM
HIRC
1.8V
4 MHz
Disabled
Disabled
Disabled
IIDLE16
-
1.7
-
mA
PLL
All digital
modules
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
IPWD1
IPWD2
IPWD1
IPWD2
IPWD1
IPWD2
IPWD1
IPWD2
-
-
-
-
-
-
-
-
700
700
350
350
25
3500
A
A
A
A
A
A
A
A
Power-down Mode
(PD)
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
-
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
1500
Low Leakage Power-
down Mode
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
(LLPD)
-
70
-
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
Standby Current
Power-down Mode
(SPD0 SRAM retention)
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
25
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
15
46
-
Standby Current
Power-down Mode
(SPD1)
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
15
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
IPWD1
-
-
2
2
6
-
A
A
Deep
USB_VDD33 pin floating.
Power-down Mode
(DPD)
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
IPWD2
USB_VDD33 pin floating.
Sep 09, 2019
Page 86 of 109
Rev1.13
ISD94100 Series Datasheet
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 3.3 V, All oscillators and analog
blocks turned off. LIRC on
IPWD3
-
3.5
7.5
A
VDD = 1.8 V, All oscillators and analog
blocks turned off. LIRC on
IPWD4
-
3.5
-
-
A
A
VDD = 3.6 V, 0 < VIN< VDD
ILK
Input Leakage Current
-1
+1
Open-drain or input only mode
-0.3
-0.3
2.0
-
-
-
-
0.8
VDD = 3.3 V
VDD = 1.8 V
VDD = 3.3 V
VDD = 1.8 V
Input Low Voltage (TTL
input)
VIL1
V
0.6
VDD + 0.3
VDD + 0.3
Input High Voltage (TTL
input)
VIH1
V
V
1.5
Negative going threshold
(Schmitt input), nRESET
VILS
-0.3
-
0.3 VDD
Positive going threshold
(Schmitt input), nRESET
VIHS
0.7 VDD
-
VDD + 0.3
V
Internal nRESET pin pull
up resistor
RRST
-
50
-
kΩ
VILS
VIHS
Schmitt input high voltage
Schmitt input low voltage
0.6* VDD 0.75* VDD
0.4* VDD
V
V
0.3* VDD
Hysteresis Schmitt buffer hysteresis
ISR11
-
-
0.2 VDD
-9.3
-7.5
-5.6
-20
-
-
-
-
-
-
-
-
-
-
V
VDD = 3.3 V, VS = 2.8 V
VDD = 2.7 V, VS = 2.3 V
VDD = 1.8 V, VS = 1.5 V
VDD = 3.3 V, VS = 2.8 V
VDD = 2.7 V, VS = 2.3 V
VDD = 1.8 V, VS = 1.5 V
VDD = 3.3 V, VS = 0.5 V
VDD = 2.7 V, VS = 0.4 V
VDD = 1.8 V, VS = 0.3 V
A
A
A
mA
Source Current (Quasi-
bidirectional Mode)
ISR12
-
ISR13
ISR21
-
-
Source Current (Push-
pull Mode)
ISR22
-14
-11
14
11
-
-15
mA
mA
mA
mA
mA
ISR23
-7.9
20
ISK11
Sink Current (Quasi-
ISK12
ISK13
bidirectional, Open-Drain
and Push-pull Mode)
15
8.2
Notes:
1. nRESET pin is a Schmitt trigger input.
Table 7.3-1 DC Electrical Characteristics
Sep 09, 2019
Page 87 of 109
Rev1.13
ISD94100 Series Datasheet
7.4 AC Electrical Characteristics
7.4.1 External High Speed Crystal (HXT) Characteristics
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note:
1. Duty cycle is 50%.
2. Guaranteed by design, not tested in production
Figure 7.4-1 External High Speed Crystal Timing Diagram
Symbol
tCHCX
Parameter
Clock High Time
Min
10
10
2
Typ
Max
-
Unit
ns
Test Condition
-
-
-
-
-
-
-
-
tCLCX
tCLCH
tCHCL
Clock Low Time
Clock Rise Time
Clock Fall Time
-
ns
15
15
ns
2
ns
Table 7.4.1-1 External High Speed Clock Input Characteristics
Symbol
THXT
fHXT
Parameter
Operation Temperature
Oscillator Frequency
Min
-40
4
Typ
25
Max
85
Unit
℃
Test Conditions
-
12
24.576
MHz
VDD = 3.3V, fHXTAL = 4 MHz
-
-
-
-
-
-
0.37
0.5
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
TA = 25 ℃, GM TYPE
VDD = 3.3V, fHXTAL = 12 MHz
TA = 25 ℃, GM TYPE
VDD = 3.3V, fHXTAL = 16 MHz
0.66
0.84
0.57
1.4
TA = 25 ℃, GM TYPE
VDD = 3.3V, fHXTAL =24 MHz
TA = 25 ℃, GM TYPE
IHXT
Operating Current
VDD = 3.3V, fHXTAL = 4 MHz
TA = 25 ℃, INV TYPE
VDD = 3.3V, fHXTAL = 12 MHz
TA = 25 ℃, INV TYPE
VDD = 3.3V, fHXTAL = 16 MHz
-
-
2.1
2.8
-
-
mA
mA
TA = 25 ℃, INV TYPE
VDD = 3.3V, fHXTAL = 24 MHz
Sep 09, 2019
Page 88 of 109
Rev1.13
ISD94100 Series Datasheet
TA = 25 ℃, INV TYPE
Note:
1. This table is guaranteed by characteristics result, not tested in production.
Table 7.4.1-2 External High Speed Crystal (HXT) Characteristics
7.4.1.1 HXT Typical Crystal Application Circuit
C1
C2
CRYSTAL
4 MHz ~ 24.576 MHz
Optional (depending on the crystal specification)
XT1_IN
XT1_OUT
4~24.576
MHz
Crystal
C1
C2
Vss
Vss
Figure 7.4-2 HXT Typical Crystal Application Circuit
7.4.2
Internal High Speed RC Oscillator (HIRC) Characteristics
Parameter
Min
Typ
Max
Unit
Test Conditions
Symbol
THRC
℃
Operation Temperature
Center Frequency
-40
-
25
85
-
-
49.152
MHz
TA = 25 ℃
±0.25
-
-
%
fHRC
Calibrated Internal
VDD = 3.3 V
Oscillator Frequency
TA = -40℃~ 85 ℃
TA = 25 ℃,VDD = 3.3 V
-2
-
-
+2
-
%
IHRC
Operating Current
200
μA
Table 7.4.2-1 Internal High Speed RC Oscillator (HIRC) Characteristics
7.4.3
External Low Speed Crystal (LXT) Characteristics
Symbol
Parameter
Operation Temperature
Oscillator Frequency
Operating Current
Min
Typ
25
Max
Unit
℃
Test Conditions
TLXT
fLXT
ILXT
-40
85
-
-
-
32.768
0.8
kHz
μA
TA = 25 ℃,VDD = 3.3 V
-
Sep 09, 2019
Page 89 of 109
Rev1.13
ISD94100 Series Datasheet
TS
Stable Time
300
500
ms
Table 7.4.3-1 External Low Speed Crystal (LXT) Characteristics
7.4.3.1 LXT Typical Crystal Application Circuit
CRYSTAL
C1
C2
32.768 kHz
Optional (depending on the crystal specification)
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Figure 7.4-3 LXT Typical Crystal Application Circuit
7.4.4
Internal Low Speed RC Oscillator (LIRC) Characteristics
Symbol
Parameter
Operation Temperature
Center Frequency
Min
-40
5
Typ
25
Max
85
15
-
Unit
℃
Test Conditions
TLRC
fLRC
ILRC
-
10
KHz
nA
-
TA = 25 ℃, VDD = 3.3 V
Operating Current
-
500
Table 7.4.4-1 Internal Low Speed RC Oscillator (LIRC) Characteristics
Sep 09, 2019
Page 90 of 109
Rev1.13
ISD94100 Series Datasheet
7.5 Analog Characteristics
7.5.1
12-bit SARADC
Symbol
Parameter
Min
Typ
Max
Unit
Bit
Test Condition
-
Resolution
12
-
DNL
INL
EO
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
-
-
-
-
-
-
±2
±4
-
LSB
LSB
LSB
LSB
LSB
-
2MSPS
-
2MSPS
2
2MSPS
EG
Gain Error (Transfer Gain)
Absolute Error
-3
-
2MSPS
EA
6
-
2MSPS
-
Monotonic
Guaranteed
-
FADC
FS
ADC Clock Frequency
0.14
-
-
60
MHz
kSPS
1/FADC
1/FADC
V
AVDD = 1.8~3.6 V
Sample Rate (FADC/TCONV
)
-
2~9
16~23
-
2000
AVDD = 1.8~3.6 V
TACQ
TCONV
VIN
CIN
Acquisition Time (Sample Stage)
Total Conversion Time
Analog Input Voltage
-
-
-
-
0
-
AVDD
-
Input Capacitance
6
pF
Note:
1. This table is guaranteed by characteristics result, not tested in production.
2. The condition is that the error in a conversion started after ADC enable is less than ±0.5 LSB. The
reference and input signal are already settled.
Table 7.5.1-1 12-bit SARADC Characteristics
Sep 09, 2019
Page 91 of 109
Rev1.13
ISD94100 Series Datasheet
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve
and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from
the actual transfer curve.
Sep 09, 2019
Page 92 of 109
Rev1.13
ISD94100 Series Datasheet
7.5.2
LDO
Symbol
Parameter
Temperature
Min
-40
Typ
25
Max
85
Unit
℃
V
Test Condition
-
TA
VLDO1
VLDO2
VLDO3
Notes:
Output Voltage
Output Voltage
Output Voltage
1.176
1.2
0.9
1.26
1.224
Normal mode
Low power mode
Over voltage mode
V
V
1. It is critical that a 0.1 µF capacitor is connected between VDD and the closest VSS pin of the device.
2. To ensure power stability, a 1uF capacitor must be connected between LDO pin and the closest VSS pin of the
device.
Table 7.5.2-1 LDO Characteristics
7.5.3
Low Voltage Reset and Brown-out Detector
Symbol
Parameter
Temperature
Min
-40
Typ
25
Max
Unit
℃
μA
V
Test Condition
-
TA
85
IBOD
Operating Current
-
60
VDD = 3.6V
1.50
1.70
1.90
2.10
2.30
2.50
2.70
2.90
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
1.70
1.90
2.10
2.30
2.50
2.70
2.90
3.10
BODVL [2:0]=000
BODVL [2:0]=001
BODVL [2:0]=010
BODVL [2:0]=011
BODVL [2:0]=100
BODVL [2:0]=101
BODVL [2:0]=110
BODVL [2:0]=111
V
V
V
Brown-out Detect Level
(Falling edge)
VBOD_F
V
V
V
V
Brown-out Detect Level
(Rising edge)
VBOD_F
VHYS_BOD
+
VBOD_R
VHYS_BOD
VLVR
-
-
Hysteresis
-
80
-
mV
V
-
-
Low Voltage Reset Voltage
1.45
1.5
1.55
Table 7.5.3-1 Low Voltage Reset and Brown-out Detector Characteristics
7.5.4
Power-on Reset
Symbol
Parameter
Min
Typ
25
Max
Unit
℃
Test Condition
TA
Temperature
-40
85
-
-
-
VPOR
VPORHYS
Power-on Reset Voltage
Power-on Reset Hysteresis
1.45
110
V
-
-
mV
Sep 09, 2019
Page 93 of 109
Rev1.13
ISD94100 Series Datasheet
VDD Raising Rate to Ensure
Power-on Reset
RRVDD
FRVDD
0.01
0.5
-
-
-
-
ms/V
ms/V
-
-
VDD Falling Rate to Ensure
Power-on Reset
Table 7.5.4-1 Power-on Reset Characteristics
FRVDD
RRVDD
VPOR
VPOR - VPORHYS
VPORHYS
VDD
Power-on
Reset
Reset
Release
Reset
Figure 7.5-1 Power-on Reset Condition
Sep 09, 2019
Page 94 of 109
Rev1.13
ISD94100 Series Datasheet
7.6 USB Characteristics
7.6.1 USB Full-Speed Characteristics
Symbol
Parameter
Input High (driven)
Min
2.0
-
Typ
Max
Unit
V
Test Condition
VIH
VIL
VDI
-
-
-
-
0.8
-
-
Input Low
V
-
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
0.8
-
2.5
V
Includes VDI range
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
0.8
-
-
200
-
2.0
-
V
mV
V
-
VSE
-
VOL
VOH
VCRS
RPU
ZDRV
CIN
Output Low (driven)
0
0.3
3.6
2.0
-
Output High (driven)
2.8
1.3
-
V
-
Output Signal Cross Voltage
Pull-up Resistor
-
V
-
-
1.2
10
-
kΩ
Ω
Driver Output Resistance
Transceiver Capacitance
-
-
-
Steady state drive*
Pin to GND
20
pF
*Driver output resistance doesn’t include series resistor resistance.
Table 7.6.1-1 USB Full-Speed Characteristics
7.6.2
USB Full-Speed PHY Characteristics
Symbol
Parameter
Min
4
Typ
Max
20
Unit
ns
Test Condition
CL=50p
TFR
Rise Time
Fall Time
-
-
-
TFF
4
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
111.11
%
TFRFF=TFR/TFF
Table 7.6.2-1 USB Full-Speed PHY Characteristics
7.6.3
USB VBUS Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
VBUS
VBUS Pin Input Voltage
5.0
V
-
Table 7.6.3-1 USB VBUS Characteristics
Sep 09, 2019
Page 95 of 109
Rev1.13
ISD94100 Series Datasheet
7.7 VAD Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VDDA = VDD = 3.3 V
HCLK = 3.072MHz (HIRC/16)
DMIC_MCLK = 1.536 MHz (HIRC/32)
DMIC_CLK = 384 kHz (DMIC_MCLK/4)
Sample Rate = 8 kHz (Down sample 48)
No load
Operation Current
Idle mode with VAD
IVADIDLE
-
1.25
-
mA
Table 7.7-1 VAD Characteristics
Note: This table is guaranteed by characteristics result, not tested in production.
Sep 09, 2019
Page 96 of 109
Rev1.13
ISD94100 Series Datasheet
7.8 Flash DC Electrical Characteristic
Symbol
Parameter
Supply Voltage
Min
1.08
10000
10
Typ
Max
1.32
-
Unit
V
Test Condition
[1]
VFLA
-
-
-
-
-
-
-
-
-
NENDUR
TRET
TERASE
TMER
TPROG
IDD1
Endurance
cycles[2]
year
ms
Data Retention
Page Erase Time
Mass Erase Time
Program Time
Read Current
-
92
160
350
50
4.12
5
TA = 25 ℃
300
42
ms
us
-
mA
IDD2
Program Current
Erase Current
-
mA
IDD3
-
5
uA
Notes:
1. VFLA is source from chip LDO output voltage.
2. Number of program/erase cycles.
3. This table is guaranteed by design, not test in production.
Table 7.8-1 Flash DC Electrical Characteristics
Sep 09, 2019
Page 97 of 109
Rev1.13
ISD94100 Series Datasheet
7.9 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
Max.
-
Min.
Max.
-
tLOW
SCL low period
1.2
0.6
1.2
uS
uS
uS
tHIGH
SCL high period
4
-
-
-
-
tSU; STA
Repeated START condition setup
time
4.7
tHD; STA
tSU; STO
tBUF
START condition hold time
STOP condition setup time
Bus free time
4
-
-
0.6
-
-
uS
uS
uS
nS
uS
nS
nS
pF
4
4.7[3]
250
0[4]
-
0.6
-
1.2[3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
-
-
-
Cb
Capacitive load for each bus line
-
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
Table 7.9-1 I2C Dynamic Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 7.9-1 I2C Timing Diagram
Sep 09, 2019
Page 98 of 109
Rev1.13
ISD94100 Series Datasheet
7.10 SPI Dynamic Characteristics
PARAMETER
MIN.
TYP.
MAX.
UNIT
SYMBOL
SPI MASTER MODE (VDD = 1.8 V~3.6V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20 MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tH(MI)
tV
1
-
tH(MO)
0
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20 MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
2
4
ns
ns
ns
ns
tH(MI)
tV
-
-
1
-
tH(MO)
0
Table 7.6.3-1 Dynamic Characteristics of Data Input and Output Pin in Master Mode
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
tr(SCK)
tf(SCK)
SPI data output
(SPI_MOSI)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MISO)
Data Valid
Data Valid
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MOSI)
Data Valid
tDH
Data Valid
Data Valid
tDS
SPI data input
(SPI_MISO)
Data Valid
Figure 7.10-1 SPI Master Mode Timing Diagram
Sep 09, 2019
Page 99 of 109
Rev1.13
ISD94100 Series Datasheet
PARAMETER
MIN.
TYP.
MAX.
UNIT
SYMBOL
SPI SLAVE MODE (VDD = 1.8 V~3.6V, 30 PF LOADING CAPACITOR)
Peripheral
clock
tSS
Slave select setup time
Slave select hold time
3
2
-
-
-
-
Peripheral
clock
tSH
tDS
Data input setup time
Data input hold time
Data output access time
Data output valid time
Data output hold time
2
5.5
-
-
-
-
ns
ns
ns
ns
ns
tH(SI)
ta(SO)
tV
-
-
18.5-
-
18
24.5
-
-
tH(SO)
6
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
Peripheral
clock
tSS
Slave select setup time
Slave select hold time
3
2
-
-
-
-
Peripheral
clock
tSH
tDS
Data input setup time
Data input hold time
Data output access time
Data output valid time
Data output hold time
2
6
-
-
-
-
-
ns
ns
ns
ns
ns
tH(SI)
ta(SO)
tV
-
24
30
-
-
23
-
tH(SO)
7
Table 7.6.3-2 Dynamic Characteristics of Data Input and Output Pin in Slave Mode
Sep 09, 2019
Page 100 of 109
Rev1.13
ISD94100 Series Datasheet
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDS
tDH
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
ta(so)
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 7.10-2 SPI Slave Mode Timing Diagram
Sep 09, 2019
Page 101 of 109
Rev1.13
ISD94100 Series Datasheet
7.11 I2S Dynamic Characteristics
Parameter
Min
Max
Unit
Test Conditions
Symbol
tw(CKH)
I2S clock high time
I2S clock low time
WS valid time
40
40
4
-
-
-
-
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
1
WS setup time
WS hold time
24
0
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
10
7
7
4
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
10
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
4
-
0
Table 7.11-1 I2S Dynamic Characteristics
Sep 09, 2019
Page 102 of 109
Rev1.13
ISD94100 Series Datasheet
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.11-1 I2S Master Mode Timing Diagram
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.11-2 I2S Slave Mode Timing Diagram
Sep 09, 2019
Page 103 of 109
Rev1.13
ISD94100 Series Datasheet
8
APPLICATION CIRCUIT
VCC
USB_VBUS
USB_D-
AVDD
USB_D+
USB Slot
uF
0.1uF
1
AVSS
Power
SPI_SS
SPI_CLK
CS
CLK
VDD
SPI Device
SPI_MISO
SPI_MOSI
MISO
MOSI
uF
0.1uF
1
VCC
VSS
4.7K
4.7K
VDD
ICE_CLK
ICE_DAT
CLK
DIO
SWD
Interface
I2C_SCL
I2C_SDA
I2C Device
VSS
VCC
PC COM Port
RS 232 Transceiver
ROUT RIN
RXD
TXD
10K
UART
TIN
TOUT
Reset
Circuit
nRESET
10uF/10V
20p
Audio Codec
FS
BCLK
DO
ISD94100
Series
I2S_LRCK
I2S_BCLK
I2S_DI
I2S Device
DI
I2S_DO
I2S_MCLK
MCLKI
XT1_IN
4~24.576
MHz
crystal
VCC
20p
20p
L/R
L/R
XT1_OUT
X32_IN
Crystal
DMIC_CLK0
DMIC_DAT0
Digital
Microphone
DMIC_CLK1
DMIC_DAT1
VCC
32.768kHz
crystal
20p
X32_OUT
L/R
L/R
Voltage
Measurement
Audio Power Stage
EADC0_CH[12:0]
SAR ADC
PWM
DPWM_LP
DPWM_LN
LP
LN
RP
RN
DPWM_RP
DPWM_RN
PWM0_CH[5:0]
LDO_CAP
Audio
Amplifier
Audio Power Stage
LDO
DPWM_SP
DPWM_SN
IP
IN
1uF
Figure 8-1 Application Circuit
Sep 09, 2019
Page 104 of 109
Rev1.13
ISD94100 Series Datasheet
9
PACKAGE DIMENSIONS
9.1 QFN 48L (6x6x0.8 mm3 Pitch 0.4 mm)
Sep 09, 2019
Page 105 of 109
Rev1.13
ISD94100 Series Datasheet
9.2 LQFP 64L (7x7x1.4 mm3 footprint 2.0 mm)
Sep 09, 2019
Page 106 of 109
Rev1.13
ISD94100 Series Datasheet
9.3 LQFP 64L (10x10x1.4 mm3 footprint 2.0 mm)
Sep 09, 2019
Page 107 of 109
Rev1.13
ISD94100 Series Datasheet
10 REVISION HISTORY
Date
Revision
1.0
Description
2017.10.27
2017.11.01
1. Preliminary version release
1. Figure 4.1-1 updated
1.01
1. Typo correction
2. Added application circuit
2017.11.28
2018.03.21
1.02
1.03
3. Electrical characteristics updated.
4. Figure 6.3-1 updated.
1. Maximum ADC clock frequency updated.
2. Figure 6.3-1, Figure 6.3-3, Figure 7.4-1, Section 7.4.4, Section 6.5.1,
Section 6.5.2 updated
3. Minimum VDD and AVDD operation voltage updated
4. Section 8 updated
1. Section 4.2.1 updated
2018.03.26
2018.05.17
1.04
1.05
2. Table 7.2-1, Table 7.5.2-1 updated
3. Section 7.2, Section 7.4, Section 7.5 updated
1. Added part number, QFN48 package dimension and QFN48 pin diagram
2. Electrical characteristics updated
3. Parts information list and pin configuration updated
2018.06.11
2018.08.14
1.06
1.07
1. Figure 6.3-1 updated.
1. Figure 4.2-1, Table 4.1-1 and Table 4.2-1 updated.
1. Added part number ISD94113ADI, Table 4.1-1 and Table 4.2-1 is
updated.
2018.12.17
2019.01.07
2019.01.29
1.08
1.09
1.10
1. Added part number ISD94124ARI and ISD94124BRI
2. Added LQFP64 10x10 package dimensions
1. Change ISD94124ARI maximum clock to 200MHz in section 4.1 Parts
Information, but add note for maximum 100MHz of DMIC application.
2019.07.01
2019.07.15
1.11
1.12
1. Added VAD Characteristics
1. Application circuit is updated
1. Changed cover title.
2019.09.09
1.13
2. Changed header title.
3. Changed ordering information - Feature.
Sep 09, 2019
Page 108 of 109
Rev1.13
ISD94100 Series Datasheet
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages
and liabilities thus incurred by Nuvoton.
Sep 09, 2019
Page 109 of 109
Rev1.13
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