ISD4004-12MX [NUVOTON]
SINGLE-CHIP, MULTIPLE-MESSAGES VOICE RECORD/PLAYBACK DEVICES 8-, 10-, 12-, AND 16-MINUTE DURATION;
| 型号： | ISD4004-12MX |
| 厂家： | 
NUVOTON |
| 描述： | SINGLE-CHIP, MULTIPLE-MESSAGES VOICE RECORD/PLAYBACK DEVICES 8-, 10-, 12-, AND 16-MINUTE DURATION CD 手持设备 商用集成电路 |
| 文件： | 总36页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD4004 SERIES
ISD4004 SERIES
SINGLE-CHIP, MULTIPLE-MESSAGES
VOICE RECORD/PLAYBACK DEVICES
8-, 10-, 12-, AND 16-MINUTE DURATION
Publication Release Date: March 2017
Revision 1.32
- 1 -
ISD4004 SERIES
1. GENERAL DESCRIPTION ............................................................................................................... 3
2. FEATURES....................................................................................................................................... 4
3. BLOCK DIAGRAM ............................................................................................................................ 5
4. PIN CONFIGURATION..................................................................................................................... 6
5. PIN DESCRIPTION........................................................................................................................... 7
6. FUNCTIONAL DESCRIPTION ....................................................................................................... 12
6.1. Detailed Description ................................................................................................................ 12
6.2. Serial Peripheral Interface (SPI) Description .......................................................................... 13
6.2.1
6.2.2
6.2.3
OPCODES....................................................................................................................... 14
SPI Diagrams................................................................................................................... 15
SPI Control and Output Registers.................................................................................... 16
7. TIMING DIAGRAMS ....................................................................................................................... 18
8. ABSOLUTE MAXIMUM RATINGS.................................................................................................. 20
8.1. Operating Conditions............................................................................................................... 21
9. ELECTRICAL CHARACTERISTICS............................................................................................... 22
9.1. Parameters For Packaged Parts............................................................................................. 22
9.2. Parameters For Die................................................................................................................. 25
9.3. SPI AC Parameters................................................................................................................. 26
10. TYPICAL APPLICATION CIRCUIT................................................................................................. 27
11. PACKAGING AND DIE INFORMATION......................................................................................... 30
11.1.
11.2.
11.3.
28-Lead 300-Mil Plastic Small Outline IC (SOIC)................................................................ 30
28-Lead 600-Mil Plastic Dual Inline Package (PDIP) .......................................................... 31
Die Information .................................................................................................................... 32
12. ORDERING INFORMATION .......................................................................................................... 34
13. VERSION HISTORY....................................................................................................................... 35
Publication Release Date: March 2017
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Revision 1.32
ISD4004 SERIES
1. GENERAL DESCRIPTION
The ISD4004 ChipCorder® series provides high-quality, 3-volt, single-chip record/playback solutions for
8- to 16-minute messaging applications ideally for cellular phones and other portable products. The
CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute®
feature, audio amplifier, and high density multilevel Flash memory array. The ISD4004 series is
designed to be used in a microprocessor- or microcontroller-based system. Address and control are
accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin
count.
Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage.
This unique single-chip solution utilizes Nuvoton’s patented multilevel storage technology. Voice and
audio signals are directly stored onto memory array in their natural form, providing high-quality voice
reproduction.
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Revision 1.32
ISD4004 SERIES
2. FEATURES
Single-chip voice record/playback solution
Single 3 volt supply
Low-power consumption
Operating current:
-
-
ICC_Play = 15 mA (typical)
ICC_Rec = 25 mA (typical)
Standby current:
ICC_Standby = 1 µA (typical)
-
Duration: 8, 10, 12, and 16 minutes
High-quality, natural voice/audio reproduction
AutoMute feature provides background noise attenuation
No algorithm development required
Microcontroller SPI or Microwire™ Serial Interface
Fully addressable to handle multiple messages
Non-volatile message storage
100K record cycles (typical)
100-year message retention (typical)
On-chip oscillator
Power-down feature to reduce power consumption
Available in die, PDIP, and SOIC
Packaged type: Lead-Free
Temperature:
-
-
-
Commercial (die): 0°C to +50°C
Commercial (packaged units): 0°C to +70°C
Industrial (packaged units): -40°C to +85°C
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ISD4004 SERIES
3. BLOCK DIAGRAM
Internal Clock
Timing
XCLK
Sampling Clock
ANA IN-
ANA IN+
5-Pole Active
Antialiasing Filter
Analog Transceivers
Amp
3,840K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
AutoMuteTM
Feature
Amp
AUDOUT
Power Conditioning
Device Control
VCCA VSSA VSSA VSSA VSSD VCCD
SCLK SS MOSI MISO INT RAC
AM CAP
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Revision 1.32
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ISD4004 SERIES
4. PIN CONFIGURATION
1
2
3
4
28
27
26
25
SS
MOSI
MISO
VSSD
SCLK
VCCD
XCLK
INT
5
6
7
24
23
22
NC
NC
NC
RAC
VSSA
NC
ISD4004
8
9
21
20
19
NC
NC
NC
NC
NC
NC
10
11
12
18
17
VSSA
VSSA
VCCA
ANA IN+
13
14
16
15
AUD OUT
AM CAP
ANA IN-
NC
SOIC / PDIP
VSSA
NC
NC
VCCA
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RAC
NC
NC
INT
XCLK
VCCD
2
3
ANA IN+
ANA IN-
NC
AM CAP
NC
AUD OUT
NC
VSSA
4
5
6
7
ISD4004
SCLK
SS
MOSI
MISO
VSSD
8
9
10
11
12
13
14
VSSA
NC
NC
NC
NC
TSOP
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ISD4004 SERIES
5. PIN DESCRIPTION
PIN NAME
FUNCTION
SOIC /
PDIP
1
Slave Select: This input, when LOW, will select the
ISD4004 device.
SS
MOSI
2
3
Master Out Slave IN: This is the serial input to the
ISD4004 device when it is configured as slave. The master
microcontroller places data on the MOSI line one half-cycle
before the rising edge of SCLK for clocking into the device.
MISO
Master In Slave Out: This is the serial output of the
ISD4004 device. This output goes into a high-impedance
state if the device is not selected.
VSSA / VSSD
11, 12,
23 / 4
Ground: The ISD4004 series utilizes separate analog and
digital ground busses. The analog ground (VSSA) pins
should be tied together as close as possible and connected
through a low-impedance path to power supply ground. The
digital ground (VSSD) pin should be connected through a
separate low-impedance path to power supply ground.
These ground paths should be large enough to ensure that
the impedance between the VSSA pins and the VSSD pin is
less than 3 Ω. The backside of the die is connected to VSS
through the substrate. For chip-on-board design, the die
attach area must be connected to VSS or left floating.
NC
5-10, 15, Not connected
19-22
AUD OUT [1]
13
Audio Output: This pin provides an audio output of the
stored data and is recommended be AC coupled. It is
capable of driving a 5 KΩ impedance REXT
.
[1] The AUD OUT pin is always at 1.2 volts when the device is powered up. When in playback, the output buffer
connected to this pin can drive a load as small as 5 KΩ. When in record, a built-in resistor connects AUD OUT to
the internal 1.2-volt analog ground supply. This resistor is approximately 850 KΩ, but will vary somewhat
according to the sample rate of the device. This relatively high impedance allows this pin to be connected to an
audio bus without loading it down.
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PIN NAME
FUNCTION
SOIC /
PDIP
AM CAP
14
AutoMute™ Feature: The AutoMute feature only applies
for playback operation and helps to minimize noise (with 6
dB of attenuation) when there is no signal (i.e. during
periods of silence). A 1 µF capacitor to ground is
recommended to connect to the AM CAP pin.
This capacitor becomes a part of an internal peak detector
which senses the signal amplitude. This peak level is
compared to an internally set threshold to determine the
AutoMute trip point. For large signals, the AutoMute
attenuation is set to 0 dB automatically but 6 dB of
attenuation occurs for silence. The 1 µF capacitor also
affects the rate at which the AutoMute feature changes with
the signal amplitude (or the attack time).
The AutoMute feature can be disabled by connecting the
AM CAP pin directly to VCCA..
ANA IN-
16
Inverting Analog Input: This pin transfers the signal into
the device during recording via differential-input mode.
In this differential-input mode, a 16 mVp-p maximum input
signal should be capacitively coupled to ANA IN- for optimal
signal quality, as shown in Figure 1: ANA IN Modes. This
capacitor value should be equal to that used on ANA IN+
pin. The input impedance at ANA IN- is normally 56 KΩ.
In the single-ended mode, ANA IN- should be capacitively
coupled to VSSA through a capacitor equal to that used on
the ANA IN+ pin.
ANA IN+
17
Non-Inverting Analog Input: This pin is the non-inverting
analog input that transfers the signal to the device for
recording. The analog input amplifier can be driven single
ended or differentially.
In the single-ended input mode, a 32 mVp-p (peak-to-peak)
maximum signal should be capacitively connected to this
pin for optimal signal quality. The external capacitor
associated with ANA IN+ together with the 3 KΩ input
impedance are selected to give cutoff at the low frequency
end of the voice passband.
In the differential-input mode, the maximum input signal at
ANA IN+ should be 16 mVp-p capacitively coupled for
optimal signal quality. The circuit connections for the two
modes are shown in Figure 1.
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ISD4004 SERIES
PIN NAME
FUNCTION
SOIC /
PDIP
VCCA / VCCD
18 / 27
Supply Voltage: To minimize noises, the analog and digital
circuits in the ISD4004 devices use separate power busses.
These +3V busses are brought out to separate pins and
should be tied together as close to the supply as possible.
In addition, these supplies should be decoupled as close to
the package as possible.
RAC
24
Row Address Clock: This is an open drain output that
provides the signal of a ROW with a 200 ms period for 8
KHz sampling frequency. (This represents a single row of
memory.) This signal stays HIGH for 175 ms and stays
LOW for 25 ms when it reaches the end of a row.
The RAC pin stays HIGH for 109.37 µsec and stays LOW
for 15.63 µsec in Message Cueing mode (see Message
Cueing section for detailed description). Refer to the AC
Parameters table for RAC timing information at other
sample rates.
When a record command is first initiated, the RAC pin
remains HIGH for an extra TRACL period. This is due to the
need of loading the internal sample and hold circuits in the
device. This pin can be used for message management
techniques.
A pull-up resistor is required to connect this pin to other
device.
25
Interrupt: This is an open drain output pin. This pin goes
LOW and stays LOW when an Overflow (OVF) or End of
Message (EOM) marker is detected. Each operation that
ends with an EOM or OVF will generate an interrupt. The
interrupt will be cleared the next time an SPI cycle is
initiated. The interrupt status can also be read by an RINT
instruction.
INT
A pull-up resistor is required to connect this pin to other
device.
Overflow Flag (OVF) – The Overflow flag indicates that the
end of memory has been reached during a record or
playback operation.
End of Message (EOM) – The End of Message flag is set
only during playback operation when an EOM is found.
There are eight EOM flag position options per row.
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Revision 1.32
ISD4004 SERIES
PIN NAME
FUNCTION
SOIC /
PDIP
XCLK
26
External Clock Input: The ISD4004 series is configured at
the factory with an internal sampling clock frequency
centered to 1 percent of specification. The frequency is
then maintained to a variation of 2.25 percent over the
entire commercial temperature and operating voltage
ranges. The internal clock has a –6/+4 percent tolerance
over the industrial temperature and voltage ranges. A
regulated power supply is recommended for industrial
temperature range parts. If greater precision is required, the
device can be clocked through the XCLK pin as follows:
Part Number
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
Sample Rate
8.0 kHz
Required Clock
1024 kHz
6.4 kHz
819.2 kHz
682.7 kHz
512 kHz
5.3 kHz
4.0 kHz
These recommended clock rates should not be varied
because the anti-aliasing and smoothing filters are fixed.
Otherwise, aliasing problems can occur if the sample rate
differs from the one recommended. The duty cycle on the
input clock is not critical, as the clock is immediately divided
by two. If the XCLK is not used, this input must be
connected to ground.
SCLK
28
Serial Clock: This is the input clock to the ISD4004 device.
It is generated by the master device (typically
microcontoller) and is used to synchronize the data transfer
in and out of the device through the MOSI and MISO lines,
respectively. Data is latched into the ISD4004 on the rising
edge of SCLK and shifted out of the device on the falling
edge of SCLK.
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Revision 1.32
ISD4004 SERIES
Internal to the device
53K
0.1
0.1
F
F
ANA IN+
ANA IN-
3K
Signal
32m Vp-p
-
To Filter
+
3K
53K
1.2V
Single-Ended Input Mode
Internal to the device
53K
0.1
0.1
F
F
ANA IN+
ANA IN-
3K
Input Signal
Input Signal
16m Vp-p
16m Vp-p
-
To Filter
+
180
3K
53K
1.2V
Differential Input Mode
FIGURE 1: ISD4004 SERIES ANA IN MODES
TRAC
(200 ms)
RAC
25 ms
TRACL
FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION
(example of 8KHz sampling rate)
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Revision 1.32
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ISD4004 SERIES
6. FUNCTIONAL DESCRIPTION
6.1. DETAILED DESCRIPTION
Audio Quality
The Nuvoton’s ISD4004 ChipCorder® series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the sampling frequency
will produce better sound quality, but affects duration. Please refer to Table 1: Product Summary for
details.
Analog speech samples are stored directly into on-chip non-volatile memory without the digitization and
compression associated with other solutions. Direct analog storage provides higher quality
reproduction of voice, music, tones, and sound effects than other solid-state solutions.
Duration
The ISD4004 Series is a single-chip solution with 8-, 10-, 12-, and 16-minute duration.
TABLE 1: PRODUCT SUMMARY OF ISD4004 SERIES
Part Number
Duration
(Minutes)
Sample Rate
(kHz)
Typical Filter Pass
Band (kHz) *
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
8
8.0
6.4
5.3
4.0
3.4
2.7
2.3
1.7
10
12
16
* This is the –3dB point. This parameter is not checked during production testing and may vary due to process
variations and other factors. Therefore, the customer should not rely upon this value for testing purposes.
Flash Storage
The ISD4004 series utilizes on-chip Flash memory, providing zero-power message storage. The
message is retained for up to 100 years typically without power. In addition, the device can be re-
recorded typically over 100,000 times.
Memory Architecture
The ISD4004 series contains a total of 3,840K Flash memory cells, which is organized as 2,400 rows
of 1,600 cells each. The address bits (A0-A15) are used to access various rows for multiple messages
of different durations.
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ISD4004 SERIES
Microcontroller Interface
A four-wire (SCLK, MOSI, MISO & SS ) SPI interface is provided for controlling and addressing
functions. The ISD4004 is configured to operate as a peripheral slave device, with a microcontroller-
based SPI bus interface. Read and write operations are controlled through this SPI interface. An
interrupt signal (
) and internal read only Status Register are provided for handshake purposes.
INT
Programming
The ISD4004 series is also ideal for playback-only applications, where single- or multiple-messages
playback is controlled through the SPI port. Once the desired message configuration is created,
duplicates can easily be generated via a programmer.
6.2. SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION
The ISD4004 series operates via SPI serial interface with the following protocol.
First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on
the falling edge of the SCLK. However, for the ISD4004, the protocols are as follows:
1. All serial data transfers begin with the falling edge of SS pin.
2. SS is held LOW during all serial communications and held HIGH between instructions.
3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of
the SCLK signal, with LSB first.
4. Playback and record operations are initiated when the device is enabled by asserting the SS
pin LOW, shifting in an opcode and an address data to the ISD4004 device (refer to the
Opcode Summary in the following page).
5. The opcodes contain <16 address bits> and <8 control bits>.
6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt will
be cleared the next time a SPI cycle is initiated.
7. As Interrupt data is shifted out of the MISO pin, while address and control data are
simultaneously shifted into the MOSI pin. Care should be taken such that the data shifted in is
compatible with current system operation. Because it is possible to read an interrupt data and
start a new operation within the same SPI cycle.
8. An operation begins with the RUN bit set and ends with the RUN bit reset.
9. All operations begin after the rising edge of SS
.
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ISD4004 SERIES
6.2.1 OPCODES
The available Opcodes are summarized as follows:
TABLE 2: OPCODE SUMMARY
Instructions
OpCodes
Descriptions
Address (16 bits)
Control bits (8 bits)
XXX C0 C1 C2 C3 C4
<A0 – A15>
POWERUP
<XXX……XXX>
XXX 0
0
1
0
0
Power-Up: Device will be ready for an operation after
TPUD
.
SETPLAY
PLAY
<A0 – A15>
XXX 0
XXX 0
0
1
1
1
1
1
1
1
Initiates playback from address <A0-A15>.
<XXX……XXX>
Playback from the current address (until EOM or
OVF).
SETREC
REC
<A0 – A15>
XXX 0
XXX 0
0
1
1
1
0
0
1
1
Initiates a record operation from address <A0-A15>.
<XXX……XXX>
Records from current address until OVF is reached or
Stop command is sent.
SETMC
MC [1]
<A0 – A15>
XXX 1
XXX 1
0
1
1
1
1
1
1
1
Initiates Message Cueing (MC) from address <A0-
A15>.
<XXX……XXX>
Performs a Message Cueing from current location.
Proceeds to the end of message (EOM) or enters OVF
condition if no more messages are present.
STOP
<XXX……XXX>
<XXX……XXX>
XXX 0
XXX X
1
1
1
0
X
X
0
0
Stops the current operation.
STOPPWRDN
Stops the current operation and enters into standby
(power-down) mode.
RINT [2]
<XXX……XXX>
XXX 0
1
1
X
0
Read Interrupt status bits: Overflow and EOM.
Notes:
C0 = Message cueing
C1 = Ignore address bit
C2 = Master power control
C3 = Record or playback operation
C4 = Enable or disable an operation
[1] Message Cueing can be selected only at the beginning of a playback operation.
[2]
As the Interrupt data is shifted out of the ISD4004, control and address data are being shifted in. Care should
be taken such that the data shifted in is compatible with current system operation. It is possible to read
interrupt data and start a new operation at the same time. See Figures 5 - 8 for references.
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6.2.2 SPI Diagrams
LSB
A0
A15
C
0
C
4
X
X X
Input Shift Register
MOSI
(Loaded to Row Counter
only if IAB = 0)
A0-A15
Select Logic
Row Counter
P0-P15
LSB
OVF EOM P0 ...
MISO
Output Shift Register
P15
FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM
The following diagram describes the SPI port and the control bits associated with it.
LSB
MSB
C0 C1 C2 C3 C4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
x
x
x
MOSI
Message Cueing (MC)
Ignore Address Bit (IAB)
Power Up (PU)
Play/Record (P/R)
RUN
LSB
MSB
MISO
OVF EOM P0 P1 P2 P3 P4 P5
P14 P15
0
0
0
0
P6 P7 P8 P9 P10 P11 P12 P13
0
0
Notes: 1. For MOSI, LSB is the 1st bit shifted into the ISD4004.
2. For MISO, LSB is the 1st bit shifted out from the ISD4004.
FIGURE 4: SPI PORT
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ISD4004 SERIES
6.2.3 SPI Control and Output Registers
The SPI control register provides control of individual function such as play, record, message cueing,
power-up, power-down, start, stop and ignore address pointer operations.
TABLE 3: SPI CONTROL REGISTERS
Control Bit
Control Register
Bit
Device Function
Message Cueing function
C0
MC
=
1
0
Enable Message Cueing
Disable Message Cueing
Ignore Address bit
=
C1
C2
IAB [1]
=
=
1
0
Ignore input address register (A0-A15)
Use the input address register (A0-A15)
Power Up
PU
=
=
1
0
Power-Up
Power-Down
P/
R
C3
C4
Playback or Record
=
=
1
0
Play
Record
RUN
Enable or Disable an operation
=
=
1
0
Start
Stop
Address Bits A0-A15
Input address register
TABLE 4: SPI OUTPUT REGISTERS
Output Bits Description
OVF
Overflow
EOM
End-of-Message
P0-P15
Output of the row pointer register
[1]
When IAB (Ignore Address Bit) is set to 0, a playback or record operation starts from address (A0-A15). For
consecutive playback or record, IAB should be changed to a 1 before the end of that row (see RAC timing).
Otherwise the ISD4004 will repeat the operation from the same row address. For memory management, the Row
Address Clock (RAC) signal and IAB can be used to move around the memory segments.
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ISD4004 SERIES
Message Cueing
Message cueing (MC) allows the user to skip through messages, without knowing the actual physical
location of the messages. It will stop when an EOM marker is reached. Then, the internal address
counter will point to the next message. Also, it will enter into OVF condition when it reaches the end of
memory. In this mode, the messages are skipped 1,600 times faster than the normal playback mode.
Power-Up Sequence
The ISD4004 will be ready for an operation after power-up command is sent and followed by the TPUD
timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other TPUD values with respect
to different sampling rates.
The following sequences are recommended for optimized Record and Playback operations.
Record Mode
1. Send POWERUP command.
2. Wait TPUD (power-up delay).
3. Send POWERUP command.
4. Wait 2 x TPUD (power-up delay).
5. a). Send SETREC command with address xx, or
b). Send REC command (recording from current location).
6. Send STOP command to stop recording.
7. Wait TSTOP/PAUSE.
For 3 & 4), please refer to Apps Brief 39A: recorded pop elimination in the ISD4000 series.
For 5.a), the device will start recording at address xx and will generate an interrupt when an overflow
(end of memory array) is reached, if no STOP command is sent before that. Then, it will automatic stop
recording operation.
Playback Mode
1. Send POWERUP command
2. Wait TPUD (power-up delay)
3. a). Send SETPLAY command with address xx, or
b). Send PLAY command (playback from current location).
4. a). Send STOP command to halt the playback operation, or
b). Wait for playback operation to stop automatically, when an EOM or OVF is reached.
5. Wait TSTOP/PAUSE.
For 3.a), the device will start playback at address xx and it will generate an interrupt when an EOM or
OVF is reached. It will then stop playback operation.
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ISD4004 SERIES
7. TIMING DIAGRAMS
TSSH
SS
TSSmin
TSCKhi
TSSS
SCLK
MOSI
TDIH
TSCKlow
TDIS
TPD
TPD
TDF
(TRISTATE)
LSB
MISO
FIGURE 5: TIMING DIAGRAM
SS
SCLK
LSB
A8
A9
A10
C0
C1
C2
C3
C4
MOSI
LSB
OVF
EOM
P0
P1
P2
P3
P4
P5
MISO
FIGURE 6: 8-BIT COMMAND FORMAT
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ISD4004 SERIES
SS
BYTE 1
BYTE 2
BYTE 3
SCLK
MOSI
LSB
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
X
C1 C2 C3 C4
X
X
C0
LSB
X
X
X
X
OVFEOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
X
X
MISO
FIGURE 7: 16-BIT COMMAND FORMAT
SS
SCLK
Stop
Play/Record
MOSI
Data
Data
MISO
TSTOP/PAUSE
(Rec)
ANA IN
TSTOP/PAUSE
(Play)
ANA OUT
FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE
Publication Release Date: March 2017
Revision 1.32
- 19 -
ISD4004 SERIES
8. ABSOLUTE MAXIMUM RATINGS
TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
CONDITIONS
Junction temperature
VALUES
150°C
Storage temperature range
-65°C to +150°C
Voltage applied to any pin
(VSS –0.3V) to (VCC +0.3V)
(VSS –1.0V) to (VCC +1.0V)
(VSS –1.0V) to 5.5V
Voltage applied to any pin (Input current limited to 20mA)
Voltage applied to MOSI, SCLK, and SS pins
(Input current limited to 20mA)
Lead temperature (soldering – 10 seconds)
VCC – VSS
300°C
-0.3V to +7.0V
TABLE 6: ABSOLUTE MAXIMUM RATINGS (DIE)
CONDITIONS
VALUES
150°C
Junction temperature
Storage temperature range
Voltage applied to any pad
-65°C to +150°C
(VSS –0.3V) to (VCC +0.3V)
(VSS –1.0V) to (VCC +1.0V)
(VSS –1.0V) to 5.5V
Voltage applied to any pad (Input current limited to 20 mA)
Voltage applied to MOSI, SCLK, and SS pins
(Input current limited to 20mA)
VCC – VSS
-0.3V to +7.0V
Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability and performance. Functional operation is not implied at these
conditions.
Publication Release Date: March 2017
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Revision 1.32
ISD4004 SERIES
8.1. OPERATING CONDITIONS
TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)
CONDITIONS
VALUES
0°C to +70°C
-40°C to +85°C
+2.7V to +3.3V
0V
Commercial operating temperature range (Case temperature)
Industrial operating temperature (Case temperature)
Supply voltage (VCC) [1]
Ground voltage (VSS) [2]
TABLE 8: OPERATING CONDITIONS (DIE)
CONDITIONS
Commercial operating temperature range
Supply voltage (VCC) [1]
VALUES
0°C to +50°C
+2.7V to +3.3V
0V
Ground voltage (VSS) [2]
[1]
V
V
= VCCA = VCCD
= VSSA = VSSD
CC
[2]
SS
Publication Release Date: March 2017
Revision 1.32
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ISD4004 SERIES
9. ELECTRICAL CHARACTERISTICS
9.1. PARAMETERS FOR PACKAGED PARTS
TABLE 9: DC PARAMETERS
PARAMETERS
Input Low Voltage
SYMBOLS
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
VIL
VCC x 0.2
V
V
V
V
Input High Voltage
Output Low Voltage
VIH
VCC x 0.8
VOL
VOL1
0.4
0.4
IOL = 10 µA
IOL = 1 mA
RAC,
INT
Voltage
Output Low
Output High Voltage
Operating Current
- Playback
VOH
ICC
VCC - 0.4
V
IOH = -10 µA
15
25
1
30
40
10
1
10
mA
mA
µA
µA
µA
KΩ
KΩ
KΩ
dB
REXT = ∞ [3]
REXT = ∞ [3]
- Record
[3] [4]
Standby Current
ISB
Input Leakage Current
MISO Tri-State Current
Output Load Impedance
ANA IN+ Input Resistance
ANA IN- Input Resistance
IIL
IHZ
1
REXT
RANA IN+
RANA IN-
AARP
5
2.2
40
3.0
56
23
3.8
71
32 mVpp 1 KHz
sinewave input [5]
ANA IN+ or ANA IN- to AUD
OUT Gain
Notes:
[1]
Typical values @ TA = 25°C and VCC = 3.0V.
[2]
[3]
All Min/Max limits are guaranteed by Nuvoton via electronical testing or characterization. Not all
specifications are 100 percent tested.
VCCA and VCCD connected together.
[4]
[5]
SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
Measured with AutoMute feature disabled.
Publication Release Date: March 2017
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Revision 1.32
ISD4004 SERIES
TABLE 10: AC PARAMETERS (Packaged Parts)
CHARACTERISTIC
Sampling Frequency
SYMBOLS
FS
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
[5]
[5]
[5]
[5]
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
8.0
6.4
5.3
4.0
KHz
KHz
KHz
KHz
Filter Pass Band
FCF
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
3.4
2.7
2.3
1.7
KHz
KHz
KHz
KHz
3 dB Roll-Off Point[3][7]
3 dB Roll-Off Point[3][7]
3 dB Roll-Off Point[3][7]
3 dB Roll-Off Point[3][7]
Record Duration
TREC
TPLAY
TPUD
[6]
[6]
[6]
[6]
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
8
min
min
min
min
10
12
16
Playback Duration
[6]
[6]
[6]
[6]
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
8
min
min
min
min
10
12
16
Power-Up Delay
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
25
31.25
37.5
50
msec
msec
msec
msec
Stop or Pause in Record or Play TSTOP or TPAUSE
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
50
62.5
75
msec
msec
msec
msec
100
RAC Clock Period
ISD4004-08M
TRAC
[10]
[10]
[10]
[10]
200
250
300
400
msec
msec
msec
msec
ISD4004-10M
ISD4004-12M
ISD4004-16M
RAC Clock Low Time
ISD4004-08M
TRACL
25
31.25
37.5
50
msec
msec
msec
msec
ISD4004-10M
ISD4004-12M
ISD4004-16M
RAC Clock Period in Message
Cueing Mode
TRACM
ISD4004-08M
ISD4004-10M
ISD4004-12M
ISD4004-16M
125
156.3
187.5
250
µsec
µsec
µsec
µsec
RAC Clock Low Time in
Message Cueing Mode
ISD4004-08M
TRACML
15.63
19.53
23.44
31.25
µsec
µsec
µsec
µsec
ISD4004-10M
ISD4004-12M
ISD4004-16M
Total Harmonic Distortion
ANA IN Input Voltage
THD
VIN
1
2
%
32 mVpp 1 KHz
sinewave input [11]
32
mV
Peak-to-Peak [4] [8] [9]
Publication Release Date: March 2017
Revision 1.32
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ISD4004 SERIES
Notes:
[1]
Typical values @ TA = 25°C, VCC = 3.0V and timing measurement at 50% of Vcc level.
[2]
All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all
specifications are 100 percent tested.
[3]
[4]
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
Single-ended input mode. In the differential input mode, VIN maximum for ANA IN+ and ANA IN- is 16
mVp-p.
[5]
[6]
[7]
Sampling Frequency can vary as much as 2.25 percent over the commercial temperature and voltage
ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an
external clock can be utilized (see Pin Descriptions)
Playback and Record Duration can vary as much as 2.25 percent over the commercial temperature
and voltage ranges, and –6/+4 percent over the industrial temperature and voltage ranges. For greater
stability, an external clock can be utilized (see Pin Descriptions)
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to
output, expect a 6 dB drop by nature of passing through both filters.
[8]
The typical output voltage will be approximately 450 mVp-p with VIN at 32 mVp-p.
For optimal signal quality, this maximum limit is recommended.
When a record command is sent, TRAC = TRAC + TRACL on the first row address.
Measured with AutoMute feature disabled.
[9]
[10]
[11]
Publication Release Date: March 2017
- 24 -
Revision 1.32
ISD4004 SERIES
9.2. PARAMETERS FOR DIE
TABLE 11: DC PARAMETERS
PARAMETERS [6]
Input Low Voltage
SYMBOLS
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
VIL
VCC x 0.2
V
V
V
V
Input High Voltage
Output Low Voltage
VIH
VCC x 0.8
VOL
VOL1
0.4
0.4
IOL = 10 µA
IOL = 1 mA
IOH = -10 µA
REXT = ∞ [3]
RAC,
INT
Voltage
Output Low
Output High Voltage
Operating Current
-Playback
VOH
ICC
VCC - 0.4
V
15
25
1
30
40
10
2
mA
mA
µA
%
-Record
REXT = ∞ [3]
[3] [4]
Standby Current
Total Harmonic Distortion
ISB
THD
1
32 mVpp 1 KHz
sinewave input [5]
32 mVpp 1 KHz
sinewave input [5]
ANA IN+ or ANA IN- to AUD
OUT Gain
AARP
23
dB
Notes:
[1]
Typical values @ TA = 25°C and VCC = 3.0V. Sampling Frequency can vary as much as 2.25 percent
over the commercial temperature and voltage ranges.
[2]
All Min/Max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all
specifications are 100 percent tested.
[3]
[4]
VCCA and VCCD connected together.
SS = VCCA = VCCD, XCLK = MOSI = VSSA = VSSA and all other pins floating.
Measured with AutoMute feature disabled.
[5]
[6]
The test coverage for die is limited to room temperature testing. The test conditions may differ from that
of packaged parts.
Publication Release Date: March 2017
- 25 -
Revision 1.32
ISD4004 SERIES
9.3. SPI AC PARAMETERS
PARAMETER
TABLE 12: AC PARAMETERS[1]
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
TSSS
500
nsec
SS Setup Time
TSSH
500
nsec
SS Hold Time
Data in Setup Time
Data in Hold Time
Output Delay
TDIS
TDIH
TPD
200
200
nsec
nsec
nsec
nsec
µsec
500
500
Output Delay to HighZ [2]
TDF
TSSmin
1
SS HIGH
SCLK High Time
SCLK Low Time
CLK Frequency
TSCKhi
TSCKlow
F0
400
400
nsec
nsec
KHz
1,000
Notes:
[1]
Typical values @ TA = 25C, VCC = 3.0V and timing measurement at 50% of Vcc level.
[2]
Tri-state test condition.
VCC
6.32K
MISO
10.91K
50pF (Includes scope and fixture capacitance)
Publication Release Date: March 2017
Revision 1.32
- 26 -
ISD4004 SERIES
10.TYPICAL APPLICATION CIRCUIT
These application examples are for illustration purposes only. Nuvoton makes no representation or
warranty that such application will be suitable for production.
Make sure all bypass capacitors are as close as possible to the package.
C9
C8
15-30 pF
15-25 pF
VCC
U2
U1
39
38
29
30
31
32
33
34
3
2
27
4
OCS1
OCS2
PD0/RDI
MISO
MOSI
SCLK
SS
VCCD
R7
C2 0.1
F
F
10 K
PD1/TD0
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
VSSD
28
1
C1
22
1
2
RESET
IRQ
F
18
23
12
VCCA
VSSA
VSSA
VSSA
C3 0.1
C4
37
35
28
27
26
25
24
23
22
21
TCAP
PC0
PC1
PC2
PC3
PC4
PC5
C11
11
13
1
F
0.1
F
J1
16
3
2
4
5
1
ANA IN- AUD OUT
ISD4004
LINE OUT
C10
TCMP
R2
1M
F 17
0.1
ANA IN+
VCC
R1
10K
68HC705C8PPC6
24
25
PC7
RAC
14
AM CAP
R4
R3 100
100K POT
12
13
14
15
16
17
18
19
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
INT
1
R6
3
C5
47 K
1
F
2
U3
11
10
9
26
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PD7
XCLK
13
11
-IN
GAIN-OUT
V01
J4
3
2
4
5
1
10
14
+IN
EXT
8
SPEAKER
15
12
V02
VDD
PDIP / SOIC
VCC
5
BYPASS
7
6
6
7
HP-IN1
HP-IN2
C6
C7
1
F
1
4
GND
GND
GND
GND
GND
.1
F
5
4
3
2
HPSENSE
R5
8
47 K
SHUTDOWN
9
16
LM4860M
FIGURE 9: APPLICATION EXAMPLE USING SPI
Publication Release Date: March 2017
Revision 1.32
- 27 -
ISD4004 SERIES
VCC
U2
U1
3
22
27
4
MISO
VCCD
D3
23
GND
C2 0.1
F
2
28
1
21
20
19
MOSI
SCLK
SS
D2
D1
D0
VSSD
C1
22
F
28
27
26
G3
G2
G1
18
23
12
11
VCCA
VSSA
24
RESET
C3 0.1
F
VSSA
VSSA
INT 25
3
C4
SI
SK
G7
SO
C9
1
F
0.1
F
J1
16
13
2
4
1
3
2
4
5
1
ANA IN-
AUD OUT
VCC
COP 820C
LINE OUT
ISD4004
6
VCC
R2
1M
C8
0.1
F 17
24
18
17
16
L7
L6
L5
L4
ANA IN+
RAC
R1
10K
R7
R4
R3 100
3.3 K
14
100K POT
AM CAP
1
3
5
7
8
15
CLI
10
C5
2
U3
14
13
L3
L2
L1
L0
25
26
1
F
INT
13
11
-IN
GAIN-OUT
V01
11
J4
3
2
4
5
1
10
14
+IN
C10
82 pF
EXT
SPEAKER
9
12
11
12
13
VCC
XCLK
VCC
15
12
V02
VDD
5
10
BYPASS
6
7
HP-IN1
HP-IN2
C6
R6
4.7 K
C7
1
F
R5
4.7 K
1
4
GND
GND
GND
GND
GND
F
.1
3
2
HPSENSE
PDIP / SOIC
8
9
16
SHUTDOWN
LM4860M
FIGURE 10: APPLICATION EXAMPLE USING MICROWIRE
Publication Release Date: March 2017
Revision 1.32
- 28 -
ISD4004 SERIES
VCC
U2
U1
3
2
27
4
MISO
VCCD
15
16
RC4
RC5
RC3
RC4
8
VSS
C2 0.1
F
MOSI
SCLK
SS
VSSD
28
1
C1
22
19
VSS
F
14
7
18
23
12
11
VCCA
VSSA
1
MCLR
C3 0.1
F
21
RB0
VSSA
VSSA
C9
C4
0.1
F
1
F
J1
16
13
3
2
4
5
1
ANA IN-
AUD OUT
VCC
PIC16C62A
LINE OUT
ISD4004
C8
R2
1M
0.1
F
20
VDD
17
ANA IN+
RAC
R1
10K
R7
R4
24
R3 100
3.3 K
14
100K POT
AM CAP
1
3
C5
2
U3
11
RC0
25
26
1
F
INT
13
11
-IN
GAIN-OUT
V01
J4
3
2
4
5
1
10
14
+IN
9
OSC1
EXT
VCC
SPEAKER
XCLK
VCC
15
12
V02
VDD
5
BYPASS
C10
6
7
HP-IN1
HP-IN2
C6
R6
4.7 K
C7
1
F
R5
4.7 K
1
4
GND
GND
GND
GND
GND
F
.1
3
2
HPSENSE
PDIP / SOIC
8
9
16
SHUTDOWN
LM4860M
FIGURE 11: APPLICATION EXAMPLE USING SPI PORT ON MICROCONTROLLER
Publication Release Date: March 2017
Revision 1.32
- 29 -
ISD4004 SERIES
11.PACKAGING AND DIE INFORMATION
11.1.
28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)
28
26 25
23 22 21 20 19 18 17
15
16
27
24
1
2
3
4
5
6 7
9 10 11 12 13 14
8
A
G
C
B
D
F
E
H
INCHES
Nom
MILLIMETERS
Min
Max
0.711
0.104
0.299
0.0115
0.019
Min
Nom
17.93
2.56
7.52
0.22
0.41
1.27
10.31
0.81
Max
18.06
2.64
7.59
0.29
0.48
A
B
C
D
E
F
0.701
0.097
0.292
0.005
0.014
0.706
0.101
0.296
0.009
0.016
0.050
0.406
0.032
17.81
2.46
7.42
0.127
0.35
G
H
0.400
0.024
0.410
0.040
10.16
0.61
10.41
1.02
Note: Lead coplanarity to be within 0.004 inches.
Publication Release Date: March 2017
Revision 1.32
- 30 -
ISD4004 SERIES
11.2.
28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES
Nom
MILLIMETERS
Nom
Min
Max
Min
Max
A
1.445
1.450
0.150
0.070
1.455
36.70
36.83
3.81
1.78
36.96
B1
B2
C1
C2
D
0.065
0.600
0.530
0.075
0.625
0.550
0.19
1.65
15.24
13.46
1.91
15.88
13.97
4.83
0.540
13.72
D1
E
0.015
0.125
0.015
0.055
0.38
3.18
0.38
1.40
0.135
0.022
0.065
3.43
0.56
1.62
F
0.018
0.060
0.100
0.010
0.075
0.46
1.52
2.54
0.25
1.91
G
H
J
0.008
0.070
0°
0.012
0.080
15°
0.20
1.78
0°
0.30
2.03
15°
S
q
Publication Release Date: March 2017
Revision 1.32
- 31 -
ISD4004 SERIES
11.3.
DIE INFORMATION
ISD4004 Series
o
Die Dimensions (with scribe line) [1]
VCCD
MOSI
MISO
SCLK
VSSD
INT
RAC
VCCD
XCLK
SS
X: 166.6 1 mils
VSSD
VSSA
Y: 385.0 1 mils
o
o
Die Thickness [2]
11.5 0.5 mils
Pad Opening
Single pad: 90 x 90 microns
Double pad: 180 x 90 microns
ISD4004
[3]
[3]
VSSA
[3]
VCCA
AUD OUT
AM CAP
ANA IN-
ANA IN+
[3]
VSSA
VCCA
VSSA
Notes:
[1]
The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or
damage may occur.
[2]
[3]
Die thickness is subject to change, please contact Nuvoton as this thickness may change in the future.
Double bond is recommended if treated as one pad.
Publication Release Date: March 2017
- 32 -
Revision 1.32
ISD4004 SERIES
ISD4004 SERIES PAD COORDINATIONS
(with respect to die center)
Pad
Pad Description
Analog Ground
X Axis (µm)
1885.2
Y Axis (µm)
4623.7
VSSA
RAC
Row Address Clock
Interrupt
1483.8
4623.7
794.8
4623.7
INT
XCLK
VCCD
External Clock Input
Digital Power Supply
Digital Power Supply
Slave Clock
564.8
387.9
169.5
-14.7
4623.7
4623.7
4623.7
4623.7
4623.7
VCCD
SCLK
Slave Select
-198.1
SS
MOSI
MISO
VSSD
VSSD
Master Out Slave In
Master In Slave Out
Digital Ground
-1063.7
-1325.6
-1665.3
-1836.9
-1943.1
-1853.1
-1599.9
281.9
4623.7
4623.7
4623.7
4623.7
-4622.4
-4622.4
-4622.4
-4622.4
-4622.4
-4622.4
-4622.4
-4622.4
-4622.4
Digital Ground
[1]
VSSA
VSSA
VSSA
Analog Ground
[1]
Analog Ground
Analog Ground
AUD OUT
AM CAP
ANA IN-
ANA IN+
Audio Output
AutoMute
577.3
Inverting Analog Input
Noninverting Analog Input
Analog Power Supply
Analog Power Supply
1449.3
1603.5
1853.7
1943.7
[1]
VCCA
[1]
VCCA
Note:
[1]
Double bond recommended if treated as one pad.
Publication Release Date: March 2017
Revision 1.32
- 33 -
ISD4004 SERIES
12.ORDERING INFORMATION
ISD4004-
Product Family :
Special Temperature Field :
ISD4000 Family
Blank = Commercial Package (0°C to + 70°C)
or Commercial Die (0°C to + 50°C)
Product Series :
I
=
Industrial (-40°C to + 85°C)
04
=
Fourth Series (8-16 min)
Duration :
Lead-Free Type:
= Lead-Free
Y
08M
10M
12M
16M
=
=
=
=
8 minutes
10 minutes
12 minutes
16 minutes
Packaged Units / Die :
X
P
S
=
=
=
Die
28-Lead 600-mil Plastic Dual Inline Package (PDIP)
28-Lead 300-mil Plastic Small Outline Package (SOIC)
When ordering the devices, please refer to the following valid ordering numbers and contact the local
Nuvoton Sales Representatives for availability.
Type Durati
on
8 Minutes
Part #
10 Minutes
Part #
12 Minutes
Part # Order #
16 Minutes
Part #
Packa
ge
Order #
Order #
Order #
ISD4004-08MX
ISD4004-08MPY
ISD4004-08MSY
I4408X
ISD4004-10MX
I4410X
ISD4004-12MX I4412X
ISD4004-16MX
I4416X
Die
I4408PY ISD4004-10MPY I4410PY ISD4004-12MP I4412PY
I4408SY ISD4004-10MSY I4410SY ISD4004-12MS I4412SY
ISD4004-16MPY I4416PY
ISD4004-16MSY I4416SY
PDIP
SOIC
ISD4004-08MSYI I4408SY ISD4004-10MSYI I4410SYI ISD4004-
12MSI
I4412SYI ISD4004-
16MSYI
I4416SY
I
I
For the latest product information, access Nuvoton worldwide website at http://www.Nuvoton-usa.com
Publication Release Date: March 2017
- 34 -
Revision 1.32
ISD4004 SERIES
13.VERSION HISTORY
VERSION
DATE
DESCRIPTION
0
June 2000
Feb. 2004
Initial version
1.0
Reformat the document.
Add note for typical filter pass band.
Add memory architecture description.
Revise RAC timing parameter for MC.
Revise AutoMute: playback only.
Revise SPI, opcodes sections, record & playback steps.
Rename TRACLO to TRACL
.
Revise AARP parameter.
Revise DC & AC parameters tables for die.
Revise die: (x,y) coordinates.
1.1
Apr. 2005
Add lead-free parts.
Revise the Ordering information.
Revise disclaim section.
1.2
1.3
Oct. 2005
Jul. 2007
Revise Packaging information.
Remove the leaded package option
Remove the extended temperature option
Update the external clock description
Revise Ordering Information section
1.31
1.32
Oct 31, 2008 Change to Nuvoton logo
Revise MISO description
March, 2017 Removed TSOP Package not recommended for new design
Publication Release Date: March 2017
Revision 1.32
- 35 -
ISD4004 SERIES
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for loss
of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the
Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton. This product incorporates
SuperFlash®.
Information contained in this ISD® ChipCorder® datasheet supersedes all data for the ISD ChipCorder products published
by ISD® prior to August, 1998.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder® product
specifications. In the event any inconsistencies exist between the information in this and other product documentation,
or in the event that other product documentation contains information in addition to the information in this, the information
contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change
without notice.
Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Nuvoton Technology Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks
are properties of their respective owners.
Headquarters
Nuvoton Technology Corporation America
Nuvoton Technology (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.Nuvoton-usa.com/
http://www.Nuvoton.com.tw/
Taipei Office
Nuvoton Technology Corporation Japan
Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
FAX: 81-45-4781800
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Publication Release Date: March 2017
Revision 1.32
- 36 -
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