ISD8104SYI [NUVOTON]

2W Class AB Audio Amplifier with Chip Enable;


型号：	ISD8104SYI
厂家：	NUVOTON
描述：	2W Class AB Audio Amplifier with Chip Enable
文件：	总19页 (文件大小：719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISD8102/ISD8104

ISD8102 / ISD8104

2W Class AB Audio Amplifier

with Chip Enable

i) ISD8102 - Earphone Sense IN (SE / Diff)

ii) ISD8104 - Differential Input pair

Preliminary Data Sheet Rev 1.2

- 1 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

1 GENERAL DESCRIPTION

The ISD8102/ ISD8104 are a general purpose analog audio amplifier, capable of driving a 4Ω load with

up to 2Wrms output power. This device includes output current limiting, chip enable, low standby

current and excellent pop-and-click suppression.

Also included is the ability to configure the input as either single-ended or differential. Internal resistors

set the device to have default 20dB gain (ISD8102/ISD8104), and with external resistors any gain less

than this can be achieved. The device is unity gain stable, including use with external feedback

resistors and external capacitors as may be optionally used for implementing simple filtering functions.

ISD8102:

The ISD8102 output can be configured to drive either single ended or bridge tied loads (BTL). The

Mode pin controls which configuration is active. This function is useful when using the IDS8102 to

alternate between driving a speaker or a mono earpiece which is connected through a shorting phone

jack. The Mode pin is connected to the normally closed pin of the shorting phone jack (see figure 3.1).

When nothing is plugged into the jack, the external resistor holds the Mode pin low, enabling BTL

mode. When a plug is inserted, the switch is opened and the mode pin goes to 1/2 VDD, as controlled

by the resistor divider, putting the amplifier into single ended mode. Note that in this example, the

speaker remains connected in both cases.

ISD8104:

The ISD8104 has differential inputs and can be configured to accept either single ended or differential

signals.

Preliminary Data Sheet Rev 1.2

- 2 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

2 FEATURES

•

Wide power supply range and excellent

standby current

o 2.0Vdc - 6.8Vdc operation

o <1uA standby current

•

High output power (capless BTL

configuration)

o Up to 2W output into 4Ω load (<10%

distortion) with 6.8Vdc supply voltage

o < 0.1% distortion at 600mW into 8-ohms

with 5Vdc supply voltage

•

Excellent pop-and-click performance

o Low to inaudible pop/click using Chip

Enable

Single-Ended or Differential signal inputs

o > 75dB common mode rejection in

differential mode

o > 70dB power supply noise rejection

Applications:

•

Very fast start-up time

o Less than 1msec when using Chip

Enable

Current limiting for over-current conditions

Package options: Pb-free SOP-8, SOP-8

(Ex-Pad)

Less BOM cost / Easy PCB layout

Temperature Range: -40°C to +85°C

•

Toys

Feature Phones

Portable Game Consoles

GPS

Portable Speakers

Boom Box

•

White Goods

Preliminary Data Sheet Rev 1.2

- 3 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

3 BLOCK DIAGRAM

3.1

ISD8102 WITH EARPIECE SENSE INPUT(PIN 3 = SE / BTL MODE)

ISD8102

0.47uF

VIN

330uF

VOUTP

1kΩ

20dB Gain

Current / Thermal

Protection

VOUTN

VDD

100kΩ

VREF

1uF

Shutdown

MODE

1uF

100kΩ

DC / Logic / Depop

Control

GND

0.1uF

Figure 3-1 ISD8102 Earpiece Configuration Block Diagram

Preliminary Data Sheet Rev 1.2

- 4 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

3.2

ISD8104 WITH DIFFERENTIAL INPUTS

Figure 3-2 ISD8104 Differential Input Pair Block Diagram

Preliminary Data Sheet Rev 1.2

- 5 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

4 PINOUT CONFIGURATION: SOP- 8

S-suffix

optional

thermal Ex-

Pad

Figure 4-1 ISD8102 8-Lead SOP Pin Configuration

S-suffix

optional

thermal Ex-

Pad

Figure 4-2 ISD8104 8-Lead SOP Pin Configuration

Preliminary Data Sheet Rev 1.2

- 6 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

5 PIN DESCRIPTION

Pin Name

I/O

Function

Number

Shutdown

VREF

MODE

VIN

Shutdown (Low = Chip Power Up / High = Chip Power Down)

Internal Reference Voltage (1/2 Vdd)

Single-Ended / Differential Output Logic Control

Inverting Signal Input

VOUTP

VDD

Non-Inverting Speaker Output

Supply Voltage

GND

Ground

VOUTN

Ex-Pad

Inverting Speaker Output

Thermal Tab (must be connected to Vss, SOP-8 package, only)

Table 5-1 ISD8102 8-Lead SOP Pin Description

Pin Name

I/O

Function

Number

Chip Enable

VREF

VIP

Internal Reference Voltage (1/2 Vdd)

Non-Inverting Signal Input

Inverting Signal Input

VIN

VOUTP

VDD

Non-Inverting Speaker Output

Supply Voltage

GND

VOUTN

Ex-Pad

Ground

Inverting Speaker Output

Thermal Tab (must be connected to Vss, SOP-8 package, only)

Table 5-2 ISD8104 8-Lead SOP Pin Description

Preliminary Data Sheet Rev 1.2

- 7 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

6 ELECTRICAL CHARACTERISTICS

6.1

OPERATING CONDITIONS

OPERATING CONDITIONS (DIE)

CONDITIONS

VALUES

Operating temperature range ¹

-40°C to +85°C

+2.0V to +6.8V

Supply voltage (V_DD)

Ground voltage (V_SS)

Input voltage (V_DD)

Vss to V_DD

Voltage applied to any pins

(V_SS– 0.3V) to (V_DD+ 0.3V)

OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)

CONDITIONS

VALUES

Operating temperature range (Case temperature) ¹

-40°C to +85°C

+2.0V to +6.8V

Supply voltage (V_DD)

Ground voltage (V_SS)

Input voltage (V_DD)

Vss to V_DD

Voltage applied to any pins

(V_SS– 0.3V) to (V_DD+ 0.3V)

Notes:

^[1]Conditions V_DD=5V, T_A=25°C unless otherwise stated. Die temperature must at all

times be kept less than 125°C by appropriate thermal design of the system.

6.2

DC PARAMETERS

PARAMETER

SYMBOL MIN

TYP ^[1]MAX

6.8

UNITS CONDITIONS

Supply Voltage

V_DD

I_DD

I_SB

2.0

Operating Current

Standby Current

2.6

0.1

µA

Ω

V_DD= 5V, no load

V_DD= 5V

CE input resistance

CE input current

20k

120

0.9

Internal pull-down @ 0dB

CE=2.3V, V_DD= 5V

All supply voltages

µA

CE threshold enabled

CE threshold standby

VREF Reference Voltage

V_ENL

V_ENH

1.5

V_DD/2

Notes:

times be kept less than 125°C by appropriate thermal design of the system.

^[1]Conditions V_DD=5V, T_A=25°C unless otherwise stated. Die temperature must at all

Preliminary Data Sheet Rev 1.2

- 8 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

6.3

AC PARAMETERS

6.3.1 Analog Characteristics; Cref = 1uF / Cvdd = 1uF

PARAMETER

SYMBOL MIN

TYP

0.3 - 6.5

0.3 – 3.4

0.3 - 1.7

TBD

MAX UNITS CONDITIONS

Vdd = 6.8Vdc

Input Voltage Range

Vdd = 3.7Vdc

Vdd = 2.0Vdc

Gain = 20dB

Vdd = 5Vdc

Inverting Input Impedance

Non-Inverting Input Impedance

Power Supply Rejection Ratio

Common Mode Rejection Ratio

Voltage Gain

PSRR

CMRR

Signal at INP = INV

Rinput = 0 Ω

Single-ended

Differential

Enable Time from Standby

Pop-and-Click from Standby ¹

Thermal Resistance

0.5

msec

0.5

Single Ended

Differential

°C/W

SOP-8 (with Ex-Pad)

SOP-8

Thermal Resistance

150

[1]

Notes:

Impulse voltage that is potentially audible. After impulse, there is a slow ramp from standby

Vref to operating Vref, which is typically inaudible with Cref = 1uF

Preliminary Data Sheet Rev 1.2

- 9 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

6.3.2 Speaker Outputs

PARAMETER

SYMBOL MIN

SNR

TYP^[1]

MAX UNITS CONDITIONS

Signal-to-Noise Ratio

Load Impedance

100

ꢀ

0dB gain, 5Vdc

R_L(SPK)

Output Offset Voltage

CONDITIONS

(THD+N)

PARAMETER

SYMBOL MIN

TYP^[1]

MAX UNITS

Output Power (BTL mode)

Load 4ꢀ

P_BTL

600

1600

2000

<0.1% distortion

<1% distortion

<10% distortion

Vdd=5Vdc / 0dB gain

PARAMETER

SYMBOL MIN

TYP^[1]

MAX

Units

Conditions (THD+N)

Output Power (BTL mode)

Load 8ꢀ

P_BTL

600

1200

1400

<0.1% distortion

<1% distortion

<10% distortion

Vdd=5Vdc / 0dB gain

Notes:

times be kept less than 125°C by thermal design of the system.

^[1]Conditions V_DD=5V, T_A=25°C unless otherwise stated. Die temperature must at all

Preliminary Data Sheet Rev 1.2

- 10 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

6.3.3 Chip Enable Threshold Voltage

Chip Enable Threshold vs. Supply Voltage

1.6

1.4

1.2

0.8

0.6

0.4

0.2

Vdc Supply Voltage (V)

6.3.4 Output Noise Spectrum

Noise spectrum at Vdd = 5.0Vdc, Gain = 0dB, BW<22kHz

Preliminary Data Sheet Rev 1.2

- 11 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

Noise Spectrum at Vdd = 5.0Vdc, Gain = 20dB, BW<22kHz

Preliminary Data Sheet Rev 1.2

- 12 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

7 APPLICATION

7.1

GAIN SETTING – ISD8102

ISD8102

Rext

20kꢀ

0.47uF

2kꢀ

VIN

330uF

VOUTP

1kꢀ

20dB Gain

Current / Thermal

Protection

VOUTN

VDD

100kꢀ

VREF

1uF

Shutdown

MODE

1uF

100kꢀ

DC / Logic / Depop

Control

GND

0.1uF

Differential Output Gain (VOUTP – VOUTN) =

By default: Rext = 0ꢀ,

ISD8102 Differential Output Gain = 20

ISD8102 Differential Output Gain (in dB) = 20 x log (20) = 26dB

Example: Rext = 18kꢀ

ISD8102 Differential Output Gain = 2

ISD8102 Differential Output Gain (in dB) = 20 x log (2) = 6dB

Preliminary Data Sheet Rev 1.2

- 13 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

7.2

GAIN SETTING – ISD8104

Differential Output Gain (VOUTP – VOUTN) =

By default: Rext = 0ꢀ,

ISD8104 Differential Output Gain = 20

ISD8104 Differential Output Gain (in dB) = 20 x log (20) = 26dB

Example: Rext = 18kꢀ

ISD8104 Differential Output Gain = 2

ISD8104 Differential Output Gain (in dB) = 20 x log (2) = 6dB

Preliminary Data Sheet Rev 1.2

- 14 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

8 PACKAGE SPECIFICATION

8.1

SOP- 8

H_E

DETAIL A

H_E

Preliminary Data Sheet Rev 1.2

- 15 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

8.2

SOP- 8 (THERMAL EX-PAD)

Preliminary Data Sheet Rev 1.2

- 16 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

9 ORDER INFORMATION

ISD8102 X Y I

Temperature

I: Industrial -40°C to 85°C

Blank: Commercial (die) 0°C to 50°C

Lead-Free

Y: Lead-Free

Package Type

X: Die

R: SOP-8

S: SOP-8 (with thermal Ex-Pad)

Model

2: ISD8102 (Pin3 = Mode)

4: ISD8104 (Pin3 = VIP)

Preliminary Data Sheet Rev 1.2

- 17 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

10 REVISION HISTORY

Version

0.0

Date

Description

Aug, 2010

Jun, 2011

Oct, 2011

Initial draft

1.0

Updated the specifications

1.1

Added the ISD8104 Gain Setting Calculation

Updated the specifications

1.2

Preliminary Data Sheet Rev 1.2

- 18 -

Publication Release Date Oct 30, 2011

ISD8102/ISD8104

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any

malfunction or failure of which may cause loss of human life, bodily injury or severe property

damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic

energy control instruments, airplane or spaceship instruments, the control or operation of

dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all

types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay

claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the

damages and liabilities thus incurred by Nuvoton.

Preliminary Data Sheet Rev 1.2

- 19 -

Publication Release Date Oct 30, 2011

ISD8104SYI [NUVOTON]

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