ISD9160CYI [NUVOTON]
ISD9160 Technical Reference Manual;
| 型号： | ISD9160CYI |
| 厂家： | 
NUVOTON |
| 描述： | ISD9160 Technical Reference Manual |
| 文件： | 总415页 (文件大小：6047K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD9160 Technical Reference Manual
ISD Cortex™-M0 ChipCorder
ISD9160 Technical Reference
Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ISD ChipCorder microcontroller
based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
Publication Release Date: Mar 30, 2016
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Revision V1.41
ISD9160 Technical Reference Manual
Table of Contents-
TABLE OF CONTENTS-.................................................................................................................. 2
1
2
3
GENERAL DESCRIPTION ..................................................................................................... 6
FEATURES ............................................................................................................................. 7
PART INFORMATION AND PIN CONFIGURATION ........................................................... 10
3.1
Pin Configuration........................................................................................................ 10
3.1.1 ISD9160 LQFP 48 pin ....................................................................................................10
3.1.2 Pin Description ...............................................................................................................10
4
5
BLOCK DIAGRAM ................................................................................................................ 15
FUNCTIONAL DESCRIPTION.............................................................................................. 16
5.1
5.2
ARM® Cortex™-M0 core ............................................................................................ 16
System Manager ........................................................................................................ 17
5.2.1 Overview ........................................................................................................................17
5.2.2 System Reset.................................................................................................................17
5.2.3 System Power Distribution .............................................................................................18
5.2.4 System Memory Map......................................................................................................19
5.2.5 System Manager Control Registers................................................................................21
5.2.6 System Timer (SysTick) .................................................................................................39
5.2.7 Nested Vectored Interrupt Controller (NVIC)..................................................................43
5.2.8 System Control Registers...............................................................................................83
Clock Controller and Power Management Unit (PMU) .............................................. 90
5.3
5.4
5.3.1 Clock Generator .............................................................................................................90
5.3.2 System Clock & SysTick Clock.......................................................................................91
5.3.3 Peripheral Clocks ...........................................................................................................92
5.3.4 Power Management .......................................................................................................92
5.3.5 Clock Control Register Map............................................................................................93
5.3.6 Clock Control Register Description.................................................................................95
General Purpose I/O ................................................................................................ 111
5.4.1 Overview and Features ................................................................................................111
5.4.2 GPIO I/O Modes...........................................................................................................111
5.4.3 GPIO Control Register Map..........................................................................................113
5.4.4 GPIO Control Register Description...............................................................................114
Brownout Detection and Temperature Alarm........................................................... 124
5.5
5.6
5.5.1 Brownout and Temperature Alarm Register Map .........................................................124
I2C Serial Interface Controller (Master/Slave) ......................................................... 129
5.6.1 Introduction...................................................................................................................129
5.6.2 I2C Protocol Registers..................................................................................................134
5.6.3 Register Mapping .........................................................................................................137
5.6.4 Register Description .....................................................................................................138
5.6.5 Modes of Operation......................................................................................................145
5.6.6 Data Transfer Flow in Five Operating Modes...............................................................146
PWM Generator and Capture Timer ........................................................................ 152
5.7
5.7.1 Introduction...................................................................................................................152
5.7.2 Features .......................................................................................................................153
5.7.3 PWM Generator Architecture .......................................................................................154
5.7.4 PWM-Timer Operation..................................................................................................154
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5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation .....................................156
5.7.6 Modulate Duty Cycle ....................................................................................................156
5.7.7 Dead-Zone Generator ..................................................................................................157
5.7.8 Capture Timer Operation..............................................................................................158
5.7.9 PWM-Timer Interrupt Architecture................................................................................159
5.7.10 PWM-Timer Initialization Procedure ...........................................................................159
5.7.11 PWM-Timer Stop Procedure ......................................................................................159
5.7.12 Capture Start Procedure.............................................................................................160
5.7.13 Register Map ..............................................................................................................161
5.7.14 Register Description ...................................................................................................162
Real Time Clock (RTC) ............................................................................................ 177
5.8
5.9
5.8.1 Overview ......................................................................................................................177
5.8.2 RTC Features...............................................................................................................177
5.8.3 RTC Block Diagram......................................................................................................178
5.8.4 RTC Function Description ............................................................................................179
5.8.5 Register Map................................................................................................................181
5.8.6 Register Description .....................................................................................................182
Serial Peripheral Interface (SPI) Controller.............................................................. 195
5.9.1 Overview ......................................................................................................................195
5.9.2 Features .......................................................................................................................195
5.9.3 SPI Block Diagram .......................................................................................................195
5.9.4 SPI Function Descriptions ............................................................................................196
5.9.5 SPI Timing Diagram .....................................................................................................204
5.9.6 SPI Configuration Examples.........................................................................................207
5.9.7 SPI Serial Interface Control Register Map....................................................................209
5.9.8 SPI Control Register Description..................................................................................210
5.10 Timer Controller........................................................................................................ 219
5.10.1 General Timer Controller............................................................................................219
5.10.2 Features .....................................................................................................................219
5.10.3 Timer Controller Block Diagram..................................................................................220
5.10.4 Timer Controller Register Map ...................................................................................221
5.11 Watchdog Timer....................................................................................................... 227
5.11.1 Watchdog Timer Control Registers Map.....................................................................229
5.12 UART Interface Controller........................................................................................ 232
5.12.1 Overview ....................................................................................................................232
5.12.2 Features of UART controller.......................................................................................234
5.12.3 Block Diagram............................................................................................................235
5.12.4 IrDA Mode ..................................................................................................................237
5.12.5 LIN (Local Interconnection Network) mode ................................................................239
5.12.6 UART Interface Control Register Map........................................................................240
5.12.7 UART Interface Control Register Description.............................................................241
5.13 I2S Audio PCM Controller ........................................................................................ 262
5.13.1 Overview ....................................................................................................................262
5.13.2 Features .....................................................................................................................262
5.13.3 I2S Block Diagram......................................................................................................263
5.13.4 I2S Operation .............................................................................................................264
5.13.5 FIFO operation ...........................................................................................................265
5.13.6 I2S Control Register Map ...........................................................................................266
5.13.7 I2S Control Register Description ................................................................................267
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5.14 Cyclic Redundancy Check (CRC) Controller ........................................................... 278
5.14.1 Overview and Features ..............................................................................................278
5.14.2 Operation....................................................................................................................278
5.14.3 Example .....................................................................................................................278
5.14.4 CRC Controller Register Map.....................................................................................279
CRC Control Register Description.............................................................................................280
5.15 PDMA Controller ...................................................................................................... 283
5.15.1 Overview ....................................................................................................................283
5.15.2 Features .....................................................................................................................283
5.15.3 Block Diagram............................................................................................................283
5.15.4 Function Description...................................................................................................284
5.15.5 PDMA Controller Register Map ..................................................................................285
5.15.6 PDMA Control Register Description ...........................................................................287
FLASH MEMORY CONTROLLER (FMC) .......................................................................... 305
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Overview .................................................................................................................. 305
Features ................................................................................................................... 305
Flash Memory Controller Block Diagram ................................................................. 306
Flash Memory Organization ..................................................................................... 307
Boot Selection .......................................................................................................... 308
Data Flash (DATAF)................................................................................................. 308
User Configuration (CONFIG).................................................................................. 309
In-System Programming (ISP) ................................................................................. 311
6.8.1 ISP Procedure..............................................................................................................311
Flash Control Register Map ..................................................................................... 314
6.9
6.10 Flash Control Register Description .......................................................................... 315
ANALOG SIGNAL PATH BLOCKS..................................................................................... 322
7
7.1
7.2
7.3
Audio Analog-to-Digital Converter (ADC)................................................................. 322
7.1.1 Functional Description..................................................................................................322
7.1.2 Features .......................................................................................................................322
7.1.3 Block Diagram..............................................................................................................322
7.1.4 Operation......................................................................................................................323
7.1.5 ADC Register Map........................................................................................................325
7.1.6 ADC Register Description.............................................................................................326
Audio Class D Speaker Driver (DPWM)................................................................... 334
7.2.1 Functional Description..................................................................................................334
7.2.2 Features .......................................................................................................................334
7.2.3 Block Diagram..............................................................................................................334
7.2.4 Operation......................................................................................................................334
7.2.5 DPWM Register Map....................................................................................................336
7.2.6 DPWM Register Description.........................................................................................337
Analog Comparator .................................................................................................. 342
7.3.1 Functional Description..................................................................................................342
7.3.2 Features .......................................................................................................................342
7.3.3 Block Diagram..............................................................................................................342
7.3.4 Operational Procedure .................................................................................................343
Setup Procedure .......................................................................................................................343
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7.3.5 Register Map................................................................................................................344
7.3.6 Register Description .....................................................................................................345
Analog Functional Blocks......................................................................................... 349
7.4
7.4.1 Overview ......................................................................................................................349
7.4.2 Features .......................................................................................................................349
7.4.3 Register Map................................................................................................................349
7.4.4 VMID Reference Voltage Generation ...........................................................................351
7.4.5 GPIO Current Source Generation ................................................................................353
7.4.6 LDO Power Domain Control.........................................................................................355
7.4.7 Microphone Bias Generator..........................................................................................358
7.4.8 Analog Multiplexer........................................................................................................362
7.4.9 Programmable Gain Amplifier ......................................................................................365
7.4.10 Capacitive Touch Sensing Relaxation Oscillator/Counter ..........................................370
7.4.11 Oscillator Frequency Measurement and Control ........................................................374
Automatic Level Control (ALC)................................................................................. 379
7.5
7.6
7.5.1 Overview and Features ................................................................................................379
7.5.2 ALC Control Register Map............................................................................................384
7.5.3 ALC Control Register Description.................................................................................385
Biquad Filter (BIQ).................................................................................................... 391
7.6.1 Overview and Features ................................................................................................391
7.6.2 BIQ Control Register Map ............................................................................................392
8
9
APPLICATION DIAGRAM................................................................................................... 396
ELECTRICAL CHARACTERISTICS................................................................................... 397
9.1
9.2
9.3
Absolute Maximum Ratings ..................................................................................... 397
DC Electrical Characteristics.................................................................................... 398
AC Electrical Characteristics.................................................................................... 402
9.3.1 External 32kHz XTAL Oscillator ...................................................................................402
9.3.2 Internal 49.152MHz Oscillator ......................................................................................402
9.3.3 Internal 16 kHz Oscillator .............................................................................................402
Analog Characteristics ............................................................................................. 403
9.4
9.4.1 Specification of ADC and Speaker Driver.....................................................................403
9.4.2 Specification of PGA and BOOST ................................................................................404
9.4.3 Specification of ALC an MICBIAS ................................................................................405
9.4.4 Specification of LDO & Power management ................................................................406
9.4.5 Specification of Brownout Detector ..............................................................................407
9.4.6 Specification of Power-On Reset (VCCD) ....................................................................407
9.4.7 Specification of Temperature Sensor ...........................................................................408
9.4.8 Specification of Comparator .........................................................................................408
Reset Characteristics ............................................................................................... 408
9.5
10 PACKAGE DIMENSIONS................................................................................................... 411
10.1.1 48L LQFP (7x7x1.4mm footprint 2.0mm) ...................................................................411
11 ORDERING INFORMATION............................................................................................... 412
12 REVISION HISTORY.......................................................................................................... 414
IMPORTANT NOTICE ................................................................................................................. 415
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1
GENERAL DESCRIPTION
The ISD9160 is a system-on-chip product optimized for low power, audio record and playback with an
embedded ARM® Cortex™-M0 32-bit microcontroller core.
The ISD9160 embeds a Cortex™-M0 core running up to 50 MHz with 145K-byte of non-volatile flash
memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of peripheral
devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct Memory
Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C, I2S), PWM modulators, GPIO,
Analog Comparator, Low Voltage Detector and Brown-out detector.
The ISD9160 comes equipped with a rich set of power saving modes including a Deep Power Down
(DPD) mode drawing less than 1A. A micro-power 16KHz oscillator can periodically wake up the
device from deep power down to check for other events. A Standby Power Down (SPD) mode can
maintain a real time clock function at less than 10A.
For audio functionality the ISD9160 includes a Sigma-Delta ADC with 92dB SNR performance coupled
with a Programmable Gain Amplifier (PGA) capable of a maximum gain of 61dB to enable direct
connection of a microphone. Audio output is provided by a Differential Class D amplifier (DPWM) that
can deliver 1W of power to an 8Ω speaker.
The ISD9160 provides eight analog enabled general purpose IO pins (GPIO). These pins can be
configured to connect to an analog comparator, can be configured as analog current sources or can
be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to
perform capacitive touch sensing.
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2
FEATURES
Core
– ARM® Cortex™-M0 core runs up to 50MHz.
– One 24-bit System tick timer for operating system support.
– Supports a variety of low power sleep and power down modes.
– Single-cycle 32-bit hardware multiplier.
– NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority.
– Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints.
Power Management
– Wide operating voltage range from 2.4V to 5.5V.
– Power management Unit (PMU) providing four levels of power control.
– Deep Power Down (DPD) mode with sub micro-amp leakage (<1µA).
– Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal
low power 16KHz oscillator.
– Standby mode with limited RAM retention and RTC operation (<10µA).
– Wakeup from Standby can be from any GPIO interrupt, RTC or BOD.
– Sleep mode with minimal dynamic power consumption.
– 3V LDO for operation of external 3V devices such as serial flash.
Flash EPROM Memory
– 145K bytes Flash EPROM for program code and data storage.
– 4KB of flash can be configured as boot sector for ISP loader.
– Support In-system program (ISP) and In-circuit program (ICP) application code update
– 1K byte page erase for flash
– Configurable boundary to delineate code and data flash.
– Support 2 wire In-circuit Programming (ICP) update from SWD ICE interface
SRAM Memory
– 12K bytes embedded SRAM.
Clock Control
– One high speed and two low speed oscillators providing flexible selection for different
applications. No external components necessary.
– Built-in trimmable oscillator with range of 16-50MHz. Factory trimmed within 1% to settings of
49.152MHz and 32.768MHz. User trimmable with in-built frequency measurement block
(OSCFM) using reference clock of 32kHz crystal or external reference source.
– Ultra-low power (<1uA) 16KHz oscillator for watchdog and wakeup from power-down or sleep
operation.
– External 32kHz crystal input for RTC function and low power system operation.
GPIO
– Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable.
– I/O pin can be configured as interrupt source with edge/level setting.
– Switchable pull-up.
Audio Analog to Digital converter
– Sigma Delta ADC with configurable decimation filter and 16 bit output.
– 92dB Signal-to-Noise (SNR) performance.
– Programmable gain amplifier with 32 steps from -12 to 35.25dB in 0.75dB steps.
– Boost gain stage of 26dB, giving maximum total gain of 61dB.
– Input selectable from dedicated MIC pins or analog enabled GPIO.
– Programmable biquad filter to support multiple sample rates from 8-32kHz.
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– DMA support for minimal CPU intervention.
Differential Audio PWM Output (DPWM)
– Direct connection of speaker
– 1W drive capability into 8Ω load.
– High efficiency 88%
– Configurable up-sampling to support sample rates from 8-32kHz.
– DMA support for minimal CPU intervention.
Timers
– Two timers with 8-bit pre-scaler and 24-bit resolution.
– Counter auto reload.
Watch Dog Timer
– Default ON/OFF by configuration setting
– Multiple clock sources
– 8 selectable time out period from micro seconds to seconds (depending on clock source)
– WDT can wake up power down/sleep.
– Interrupt or reset selectable on watchdog time-out.
RTC
– Real Time Clock counter (second, minute, hour) and calendar counter (day, month, year)
– Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Time tick and alarm interrupts.
– Device wake up function.
– Supports software compensation of crystal frequency by compensation register (FCR)
PWM/Capture
– Built-in up to two 16-bit PWM generators provide two PWM outputs or one complementary
paired PWM outputs.
– The PWM generator equipped with a clock source selector, a clock divider, an 8-bit pre-scaler
and Dead-Zone generator for complementary paired PWM.
– PWM interrupt synchronous to PWM period.
– 16-bit digital Capture timers (shared with PWM timers) provide rising/falling capture inputs.
– Support Capture interrupt
UART
– UART ports with flow control (TX, RX, CTS and RTS)
– 8-byte FIFO.
– Support IrDA (SIR) and LIN function
– Programmable baud-rate generator up to 1/16 of system clock.
SPI
– Master up to 20 Mbps / Slave up to 10 Mbps.
– Support MICROWIRE/SPI master/slave mode (SSP)
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 1 to 32 bits
– MSB or LSB first data transfer
– 2 slave/device select lines when used in master mode.
– Hardware CRC calculation module available for CRC calculation of data stream.
– DMA support for burst transfers.
I2C
– Master/Slave up to 1Mbit/s
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master).
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
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– Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer.
– Programmable clock allowing versatile rate control.
– I2C-bus controller supports multiple address recognition.
I2S
– Interface with external audio CODEC.
– Operate as either master or slave.
– Capable of handling 8, 16, 24 and 32 bit word sizes
– Mono and stereo audio data supported
– I2S and MSB justified data format supported
– Two 8 word FIFO data buffers are provided, one for transmit and one for receive
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports DMA requests, for transmit and receive
Brown-out detector
– With 8 levels: 2.1V, 2.2V, 2.4V, 2.5V, 2.625V, 2.8V, 3.0V, and 4.6V
– Supports time-multiplex operation to minimize power consumption.
– Supports Brownout Interrupt and Reset option
Built in Low Dropout Voltage Regulator (LDO)
– Capable of delivering 30mA load current.
– Configurable for output voltage of 1.8V, 2.4V, 3.0V and 3.3V
– Eight GPIO (GPIOA<7:0>) operate from LDO voltage domain allowing direct interface to, for
example, 3V SPI Flash.
– Can be bypassed and voltage domain supplied directly from system power.
Additional Features
– Over temperature alarm. Can generate interrupt if device exceeds safe operating temperature.
– Temperature proportional voltage source which can be routed to ADC for temperature
measurements.
– Digital Microphone interface.
Operating Temperature: -40C~85C
Package:
– All Green package (RoHS)
LQFP 48-pin
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3
PART INFORMATION AND PIN CONFIGURATION
3.1 Pin Configuration
3.1.1 ISD9160 LQFP 48 pin
WAKEUP
I2S_SDO/CMP7/PB.7
1
36
35
34
33
32
31
30
29
28
27
26
25
PA.14/TM0/SDCLK/SDCLKn
VCCLDO
2
I2S_SDI/CMP6/SPI_MOSI1/PB.6
PWM1B/CMP5/SPI_MISO1/PB.5
PWM0B/CMP4SPI_MOSI0/PB.4
I2C_SDA/CMP3/SPI_MISO0/PB.3
I2C_SCL/CMP2/SPI_SCLK/PB.2
MCLK/CMP1/SPI_SSB1/PB.1
SPI_SSB1/CMP0/SPI_SSB0/PB.0
VCCD
3
PA.0/SPI_MOSI0/MCLK
PA.1/SPI_SCLK/I2C_SCL
VDD33
4
5
6
PA.2/SPI_SSB0
PA.3/SPI_MISO0/I2C_SDA
PA.4/I2S_FS
LQFP 48-pin
7
8
9
PA.5/I2S_BCLK
PA.6/I2S_SDI
10
11
12
VREG
PA.7/I2S_SDO
NC
VSSD
3.1.2 Pin Description
The ISD9160 is a low pin count device where many pins are configurable to alternative functions. All
General Purpose Input/Output (GPIO) pins can be configured to alternate functions as described in
the table below and also in Error! Reference source not found. and Error! Reference source not
found..
Pin No.
Alt
CFG
Pin Name
Pin Type
Description
LQFP
48
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Pin No.
Alt
CFG
Pin Name
Pin Type
Description
LQFP
48
I
1
WAKEUP
PB.7
Pull low to wake part from deep power down
A/I/O
O
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
General purpose input/output pin, analog capable; Port B, bit 7
Serial Data Output for I2S interface
2
I2S_SDO
CMP7
AIO
A/I/O
I
Configure as relaxation oscillator for capacitive touch sensing
General purpose input/output pin, analog capable; Port B, bit 6
Serial Data Input for I2S interface
PB.6
I2S_SDI
CMP6
3
4
5
6
7
AIO
O
Configure as relaxation oscillator for capacitive touch sensing
Master Out, Slave In channel 1 for SPI interface
General purpose input/output pin, analog capable; Port B, bit 5
PWM channel 1 complementary output pin
SPI_MOSI1
PB.5
A/I/O
O
PWM1B
CMP5
AIO
I
Configure as relaxation oscillator for capacitive touch sensing
Master In, Slave Out channel 1 for SPI interface
General purpose input/output pin, analog capable; Port B, bit 4
PWM channel 0 complementary output pin
SPI_MISO1
PB.4
A/I/O
O
PWM0B
CMP4
AIO
O
Configure as relaxation oscillator for capacitive touch sensing
Master Out, Slave In channel 0 for SPI interface
General purpose input/output pin, analog capable; Port B, bit 3
Serial Data, I2C interface
SPI_MOSI0
PB.3
A/I/O
I/O
AIO
I
I2C_SDA
CMP3
Configure as relaxation oscillator for capacitive touch sensing
Master In, Slave Out channel 0 for SPI interface
General purpose input/output pin, analog capable; Port B, bit 2
Serial Clock, I2C interface
SPI_MISO0
PB.2
A/I/O
I/O
AIO
I/O
I2C_SCL
CMP2
Configure as relaxation oscillator for capacitive touch sensing
Serial Clock for SPI interface
SPI_SCLK
General purpose input/output pin, analog capable; Port B, bit
1. Triggers external interrupt 1 (EINT1/IRQ3)
A/I/O
PB.1
0
O
AIO
O
MCLK
1
2
3
Master clock output for synchronizing external device
Configure as relaxation oscillator for capacitive touch sensing
Slave Select Bar 1 for SPI interface
8
9
CMP1
SPI_SSB1
General purpose input/output pin, analog capable; Port B, bit
0. Triggers external interrupt 0 (EINT0/IRQ2)
A/I/O
O
PB.0
0
3
SPI_SSB1
Slave Select Bar 1 for SPI interface
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Pin No.
Alt
CFG
Pin Name
Pin Type
Description
LQFP
48
AIO
I/O
CMP0
2
3
Configure as relaxation oscillator for capacitive touch sensing
Slave Select Bar 0 for SPI interface
SPI_SSB0
Main Digital Supply for Chip. Supplies all IO except analog,
Speaker Driver and PA<7:0>
P
P
10
11
VCCD
VREG
Logic regulator output decoupling pin. A 1µF capacitor
returning to VSSD must be placed on this pin.
12
13
NC
Should remain unconnected.
NC
Should remain unconnected.
I/O
I
PA.15
0
1
2
0
1
2
0
1
2
General purpose input/output pin; Port A, bit 15
External input to Timer 1
14
15
16
TM1
I
SDIN
Sigma Delta bit stream input for digital MIC mode
General purpose input/output pin; Port A, bit 9
Receive channel of UART
I/O
I
PA.9
UART_RX
I2S_BCLK
PA.8
I/O
I/O
O
I/O
P
Bit Clock for I2S interface
General purpose input/output pin; Port A, bit 8
Transmit channel of UART
UART_TX
I2S_FS
VCCSPK
SPK+
Frame Sync Clock for I2S interface
Power Supply for PWM Speaker Driver
Positive Speaker Driver Output
17
18
19
20
21
O
P
VSSSPK
SPK-
Ground for PWM Speaker Driver
Negative Speaker Driver Output
Power Supply for PWM Speaker Driver
O
P
VCCSPK
External reset input. Pull this pin low to reset device to initial
state. Has internal weak pull-up.
I
22
RESETN
I/O
I
23
24
25
ICE_DAT
ICE_CLK
VSSD
Serial Wire Debug port data pin. Has internal weak pull-up.
Serial Wire Debug port clock pin. Has internal weak pull-up.
Digital Ground.
P
I/O
O
PA.7
0
1
0
1
0
1
General purpose input/output pin; Port A, bit 7
Serial Data Out for I2S interface
26
27
28
I2S_SDO
PA.6
I/O
I
General purpose input/output pin; Port A, bit 6
Serial Data In for I2S interface
I2S_SDI
PA.5
I/O
I/O
General purpose input/output pin; Port A, bit 5
Bit Clock for I2S interface
I2S_BCLK
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Pin No.
Alt
CFG
Pin Name
Pin Type
Description
LQFP
48
I/O
I/O
I/O
I
PA.4
0
1
0
1
2
0
1
General purpose input/output pin; Port A, bit 4
Frame Sync Clock for I2S interface
29
30
I2S_FS
PA.3
General purpose input/output pin; Port A, bit 3
Master In, Slave Out channel 0 for SPI interface
Serial Data, I2C interface
SPI_MISO0
I2C_SDA
PA.2
I/O
I/O
I/O
General purpose input/output pin; Port A, bit 2
Slave Select Bar 0 for SPI interface
31
32
SPI_SSB0
LDO Regulator Output. If used, a 1µF capacitor must be
placed to ground. If not used then tie to VCCD.
P
VDD33
I/O
I/O
I/O
I/O
O
PA.1
0
1
2
0
1
2
General purpose input/output pin; Port A, bit 1
Serial Clock for SPI interface
33
SPI_SCLK
I2C_SCL
PA.0
Serial Clock, I2C interface
General purpose input/output pin; Port A, bit 2
Master Out, Slave In channel 0 for SPI interface
Master clock output.
34
35
SPI_MOSI0
MCLK
O
P
VCCLDO
PA.14
Power Supply for LDO, should be connected to VCCD
General purpose input/output pin; Port A, bit 14
External input to Timer 0
I/O
I
0
1
1
2
0
1
2
3
0
1
2
3
TM0
36
37
38
O
SDCLK
SDCLKn
PA.13
Clock output for digital microphone mode.
Inverse Clock output for digital microphone mode.
General purpose input/output pin; Port A, bit 13
PWM1 Output.
O
I/O
O
PWM1
SPKM
O
Equivalent to SPK-.
I/O
I/O
O
I2S_BCLK
PA.12
Bit Clock for I2S interface
General purpose input/output pin; Port A, bit 12
PWM0 Output.
PWM0
SPKP
O
Equivalent to SPK+
I/O
O
I2S_FS
XO32K
XI32K
Frame Sync Clock for I2S interface
32.768kHz Crystal Oscillator Output
32.768kHz Crystal Oscillator Input. Max Voltage 1.8V
Ground for analog circuitry.
39
40
41
42
I
AP
O
VSSA
VMID
Mid rail reference. Connect 4.7µF to VSSA.
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Pin No.
Alt
CFG
Pin Name
Pin Type
Description
LQFP
48
AI
AI
AO
AP
I/O
I/O
O
43
44
45
46
MIC+
Positive microphone input.
MIC-
Negative microphone input.
Microphone bias output.
MICBIAS
VCCA
Analog power supply.
PA.11
0
1
2
3
0
1
2
3
General purpose input/output pin; Port A, bit 11
Serial Clock, I2C interface
I2C_SCL
I2S_SDO
UART_CTSn
PA.10
47
48
Serial Data Out I2S interface
UART Clear to Send Input.
I
I/O
I/O
I
General purpose input/output pin; Port A, bit 10
Serial Data, I2C interface
I2C_SDA
I2S_SDI
UART_RTSn
Serial Data In I2S interface
O
UART Request to Send Output.
Note:
1.
Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; P=Power Pin; AP=Analog Power
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4
BLOCK DIAGRAM
50MHz Internal Osc.
CLK CTRL
Debug interface
32kHz RTC Osc
10kHz low power
Osc
Embedded
RAM
12KB
Cortex M0
Flash
145KB
AHB Lite
Peripherals with PDMA
LDO 3.0V
LDO 1.8V
GPIO
PDMA
AHB to APB bridge
I2C
SPI
Flash Mem Controller
PWM Speaker Driver
System Control/PMU
Audio ADC
POR
BOD
Timers/PWM
UART
WDT
I2S
Figure 4-1 ISD9160 Block Diagram
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5
FUNCTIONAL DESCRIPTION
5.1 ARM® Cortex™-M0 core
The Cortex™-M0 processor is a multistage, 32-bit RISC processor. It has an AMBA AHB-Lite interface
and includes an NVIC component. It also has hardware debug functionality. The processor can
execute Thumb code and is compatible with other Cortex-M profile processor.
Figure 5-1 shows the functional blocks of processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
unit
Cortex-M0
Processor
core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire
debug port
AHB-Lite interface
Figure 5-1 Functional Block Diagram
The implemented device provides:
A low gate count processor that features:
– The ARMv6-M Thumb® instruction set.
– Thumb-2 technology.
– ARMv6-M compliant 24-bit SysTick timer.
– A 32-bit hardware multiplier.
– The system interface supports little-endian data accesses.
– The ability to have deterministic, fixed-latency, interrupt handling.
– Load/store-multiples that can be abandoned and restarted to facilitate rapid interrupt handling.
– C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers.
– Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event (WFE)
instructions, or the return from interrupt sleep-on-exit feature.
NVIC that features:
– 32 external interrupt inputs, each with four levels of priority.
– Dedicated non-Maskable Interrupt (NMI) input.
– Support for both level-sensitive and pulse-sensitive interrupt lines
– Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.
Debug support
– Four hardware breakpoints.
– Two watchpoints.
– Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
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– Single step and vector catch capabilities.
Bus interfaces:
– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system
peripherals and memory.
– Single 32-bit slave port that supports the DAP (Debug Access Port).
5.2 System Manager
5.2.1 Overview
The following functions are included in system manager section
System Memory Map
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System management registers for product ID
System management registers for chip and module functional reset and multi-function pin control
Brown-Out and chip miscellaneous Control Register
Combined peripheral interrupt source identify
5.2.2 System Reset
The system reset includes one of the list below event occurs. For these reset event flags can be read
by SYS_RSTSTS register.
The Power-On Reset
The low level on the RESETN pin
Watchdog Time Out Reset
Low Voltage Reset
Cortex-M0 MCU Reset
PMU Reset – for details of wakeup events, also examine CLK_PWRCTL register.
SWD Debug interface.
A power-on reset (POR) will occur if the main external supply rail ramps from 0V or the voltage of the
main supply drops below reset threshold. A low voltage reset monitors the regulated core logic (1.8V)
supply and will assert if the voltage on this rail drops below reliable logic threshold.
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5.2.3 System Power Distribution
The ISD9160 implements several power domains:
Analog power from VCCA and VSSA provides the power for analog module operation.
Digital power from VCCD and VSSD supplies the power to the IO ring and the internal regulator
which provides 1.8V power for digital operation.
VCCLDO supplies the LDO regulator whose output is available on pin VDD33. This supply
powers the IO ring for GPIOA<7:0>.
An internal Standby reference (SB REG) generates a 1.8V rail to part of the logic including the IO
ring, Standby RAM and RTC during standby mode for low power operation.
The outputs of internal voltage regulators; VREG and VDD33, require external decoupling capacitors
which should be located close to the corresponding pin. The following diagram shows the power
distribution of this device.
Speaker
SD ADC
Driver
VCCA
IO Cell
GPIOA<7:0>
VSSA
PGA
ISD9160
Power
Analog Comparator
Distribution
VDD33
1uF
3.3V
Brown
Current
5V to 3.3V
LDO
VCCLDO
Out
Source
Detector
RTC
32K
OSC
SB
RAM
Digital
Logic
50MHz
Osc.
XO32K
XI32K
RAM
FLASH
VREG
4.7uF
1.8V Standby Supply
10KHz
1.8V Main Supply
IO cell
POR18
POR50
SB
REG
1.8V
LDO
GPIOA<15:8>
GPIOB<7:0>
Osc.
Active in Standby Power Down Mode
Active in Deep and Standby Power Down Mode
Figure 5-2 ISD9160 Power Distribution Diagram
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5.2.4 System Memory Map
The ISD9160 provides 4G-byte address space. The memory locations assigned to each on-chip
module is shown in Table 5-1. The detailed register definition, memory space, and programming
detailed will be described in the following sections for each on-chip module. The ISD9160 supports
little-endian data format.
Table 5-1 Address Space Assignments for On-Chip Modules
Address Space
Token
Modules
Reference
Flash & SRAM Memory Space
0x0000_0000 – 0x0002_33FF
0x0000_0000 – 0x0002_43FF
0x2000_0000 – 0x2000_2FFF
FLASH_BA
FLASH_BA
SRAM_BA
FLASH Memory Space (141KB)
FLASH Memory Space (145KB)
SRAM Memory Space (12KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
0x5000_C000 – 0x5000_FFFF
SYS_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
5.2.5
5.3.5
0
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
FMC_BA
5.4.3
5.15
6.3
SRAM_APB DMA Control Registers
Flash Memory Control Registers
APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4007_0000 – 0x4007_3FFF
0x4008_0000 – 0x4008_3FFF
0x4008_4000 – 0x4008_7FFF
WDT_BA
Watch-Dog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0 Serial Interface Control Registers
PWM0/1 Control Registers
5.11
5.8
RTC_BA
TIMER0_BA
I2C0_BA
5.10
5.6
SPI0_BA
5.9
PWM_BA
UART0_BA
DPWM_BA
ANA_ BA
5.7
UART0 Control Registers
5.12
7.2
Differential Audio PWM Speaker Driver
Analog Block Control Registers
Brown Out Detector Control Registers
0
BODTALM_BA
5.5.1
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0x4009_0000 – 0x4009_7FFF
0x400A_0000 - 0x400A_FFFF
0x400B_0000 - 0x400B_FFFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_FFFF
0x400F_0000 – 0x400F_7FFF
CRC_BA
I2S_BA
CRC Block Control Registers
5.14
5.13
7.6
0
I2S Interface Control registers
BIQ_BA
Biquad Filter Control Registers
ACMP_BA
ADC0_BA
SBRAM_BA
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Registers
Standby RAM Block Address space
7.1
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF SYSTICK_BA System Timer Control Registers
5.2.6
5.2.7
5.2.8
0xE000_E100 – 0xE000_ECFF SCS_BA
External
Interrupt
Controller
Control
Registers
0xE000_ED00 – 0xE000_ED8F SYSINFO_BA
System Control Registers
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5.2.5 System Manager Control Registers
Register
Offset
R/W
Description
Reset Value
SYS Base Address:
SYS_BA = 0x5000_0000
SYS_RSTSTS
SYS_IPRST0
SYS_BA+0x04
SYS_BA+0x08
SYS_BA+0x0C
SYS_BA+0x30
SYS_BA+0x34
SYS_BA+0x38
SYS_BA+0x3C
SYS_BA+0x54
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
System Reset Source Register
IP Reset Control Resister1
0x0000_00XX
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0006
0x0000_0000
SYS_IPRST1
IP Reset Control Resister2
SYS_PASMTEN
SYS_PBSMTEN
SYS_GPA_MFP
SYS_GPB_MFP
SYS_WKCTL
GPIOA input type control register
GPIOB input type control register
GPIOA multiple function control register
GPIOB multiple function control register
WAKEUP pin control register
SYS_REGLCTL
SYS_IRCTCTL
SYS_BA+0x100 R/W
SYS_BA+0x110 R/W
Register Lock Key Address register
Oscillator Frequency Adjustment control register 0xXXXX_XXXX
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System Reset Source Register (SYS_RSTSTS)
This register provides specific information for software to identify this chip’s reset source from last
operation.
Register
Offset
R/W
Description
Reset Value
SYS_RSTSTS
SYS_BA+0x04
R/W System Reset Source Register
0x0000_00XX
31
23
15
30
22
14
29
21
13
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
6
5
3
2
1
0
CPURF
PMURSTF
SYSRF
Reserved
Reserved
WDTRF
Reserved
CORERSTF
Table 5-2 System Reset Source Register (SYS_RSTSTS, address 0x5000_0004) Bit Description.
Bits
Description
[31:8]
Reserved
Reserved
Reset Source From CPU
The CPURF flag is set by hardware if software writes SYS_IPRST0.CPURST with a
“1” to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).
[7]
CPURF
0= No reset from CPU
1= The Cortex-M0 CPU kernel and FMC has been reset by software setting CPURST
to 1.
This bit is cleared by writing 1 to itself.
Reset Source From PMU
The PMURSTF flag is set if the PMU.
0= No reset from PMU
[6]
PMURSTF
1= PMU reset the system from a power down/standby event.
This bit is cleared by writing 1 to itself.
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Reset Source From MCU
The SYSRF flag is set if the previous reset source originates from the Cortex_M0
kernel.
0= No reset from MCU
[5]
SYSRF
1= The Cortex_M0 MCU issued a reset signal to reset the system by software writing
1 to bit SYSCTL_AIRCTL.SYSRESTREQ, Application Interrupt and Reset Control
Register) in system control registers of Cortex_M0 kernel.
This bit is cleared by writing 1 to itself.
Reserved
[4:3]
[2]
Reserved
WDTRF
Reset Source From WDT
The WDTRF flag is set if pervious reset source originates from the Watch-Dog
module.
0= No reset from Watch-Dog
1= The Watch-Dog module issued the reset signal to reset the system.
This bit is cleared by writing 1 to itself.
[1]
Reserved
CORERSTF
Reserved
Reset Source From CORE
The CORERSTF flag is set if the core has been reset. Possible sources of reset are a
Power-On Reset (POR), RESETn Pin Reset or PMU reset.
[0]
0= No reset from CORE
1= Core was reset by hardware block.
This bit is cleared by writing 1 to itself.
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IP Reset Control Register1 (SYS_IPRST0)
Register
Offset
R/W
Description
Reset Value
SYS_IPRST0
SYS_BA+0x08
R/W
IP Reset Control Resister1
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
2
1
0
Reserved
PDMARST
CPURST
CHIPRST
Table 5-3 IP Reset Control Register 1 (SYS_IPRST0 address 0x5000_0008) Bit Description.
Bits
Description
Reserved
Reserved
[31:3]
PDMA Controller Reset
Set “1” will generate a reset signal to the PDMA Block. User needs to set this bit to “0”
to release from the reset state
[2]
PDMARST
0= Normal operation
1= PDMA IP reset
CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit
will automatically return to “0” after the 2 clock cycles
[1]
CPURST
This bit is a protected bit, to program first issue the unlock sequence (see Protected
Register Lock Key Register (SYS_REGLCTL))
0= Normal
1= Reset CPU
CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to “0” after the 2
clock cycles.
CHIPRST has same behavior as POR reset, all the chip modules are reset and the
chip configuration settings from flash are reloaded.
[0]
CHIPRST
This bit is a protected bit, to program first issue the unlock sequence (see Protected
Register Lock Key Register (SYS_REGLCTL))
0= Normal
1= Reset CHIP
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IP Reset Control Register2 (SYS_IPRST1)
Setting these bits “1” will generate an asynchronous reset signal to the corresponding peripheral
block. The user needs to set bit to “0” to release block from the reset state.
Register
Offset
R/W
Description
Reset Value
SYS_IPRST1
SYS_BA+0x0C
R/W IP Reset Control Resister2
0x0000_0000
31
Reserved
23
30
ANARST
22
29
I2S0RST
21
28
EADCRST
20
27
Reserved
19
26
Reserved
18
25
Reserved
17
24
Reserved
16
Reserved
15
ACMPRST
14
Reserved
13
PWM0RST
12
CRCRST
11
BIQRST
10
Reserved
9
UART0RST
8
Reserved
7
Reserved
6
DPWMRST
5
SPI0RST
4
Reserved
3
Reserved
2
Reserved
1
I2C0RST
0
TMR1RST
TMR0RST
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 5-4 IP Reset Control Register 2 (SYS_IPRST1 address 0x5000_000C) Bit Description.
Bits
[30]
Description
Analog Block Control Reset
ANARST
0 = Normal Operation
1 = Reset
I2S Controller Reset
[29]
[28]
[22]
[20]
[19]
I2S0RST
0 = Normal Operation
1 = Reset
ADC Controller Reset
0 = Normal Operation
1 = Reset
EADCRST
ACMPRST
PWM0RST
CRCRST
Analog Comparator Reset
0 = Normal Operation
1 = Reset
PWM10 controller Reset
0 = Normal Operation
1 = Reset
CRC Generation Block Reset
0 = Normal Operation
1 = Reset
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Biquad Filter Block Reset
0 = Normal Operation
1 = Reset
[18]
[16]
[13]
[12]
[8]
BIQRST
UART0 Controller Reset
0 = Normal Operation
1 = Reset
UART0RST
DPWMRST
SPI0RST
I2C0RST
DPWM Speaker Driver Reset
0 = Normal Operation
1 = Reset
SPI0 Controller Reset
0 = Normal Operation
1 = Reset
I2C0 Controller Reset
0 = Normal Operation
1 = Reset
Timer1 Controller Reset
0 = Normal Operation
1 = Reset
[7]
TMR1RST
TMR0RST
Timer0 Controller Reset
0 = Normal Operation
1 = Reset
[6]
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GPIOA Input Type Control Register (SYS_PASMTEN)
Register
Offset
R/W
Description
Reset Value
SYS_PASMTEN
SYS_BA+0x30
R/W
GPIOA input type control register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SMTEN [15:8]
SMTEN [7:0]
Reserved
1
0
Reserved
Table 5-5 GPIOA Input Type Control Register (SYS_PASMTEN address 0x5000_0030) Bit
Description.
Bits
Description
Schmitt Trigger
[n]
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
0 = GPIOA[15:0] I/O input Schmitt Trigger disabled
SMTEN
n=16,17..31
1 = GPIOA[15:0] I/O input Schmitt Trigger enabled
[15:0]
Reserved
Reserved
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GPIOB Input Type Control Register (SYS_PBSMTEN)
Register
Offset
R/W
Description
Reset Value
SYS_PBSMTEN
SYS_BA+0x34
R/W
GPIOB input type control register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
SMTEN [7:0]
Reserved
1
0
Reserved
Table 5-6 GPIOB Input Type Control Register (SYS_PBSMTEN address 0x5000_0034) Bit
Description.
Bits
Description
Schmitt Trigger
[n]
This register controls whether the GPIO input buffer Schmitt trigger is enabled.
0= GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled
SMTEN
n=16,17..23
1= GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled
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GPIO Alternative Function Control Register (SYS_GPA_MFP)
Each GPIO pin can take on multiple alternate functions depending on the setting of this register. Each
pin has two bits of alternate function control. Set to 00 the pin is a standard GPIO pin whose attributes
are defined by the GPIO control registers (See Section 0). Set to other values the pin is assigned to a
peripheral as outlined in table below.
Register
Offset
R/W
Description
Reset Value
SYS_GPA_MFP
SYS_BA+0x38
R/W
0x0000_0000
GPIOA multiple function control register
31
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
PA15MFP
PA14MFP
PA10MFP
PA6MFP
PA2MFP
PA13MFP
PA9MFP
PA5MFP
PA1MFP
PA12MFP
16
23
15
7
PA11MFP
PA7MFP
PA3MFP
PA8MFP
8
PA4MFP
0
4
1
PA0MFP
Table 5-7 GPIOA Alternate Function Register (SYS_GPA_MFP address 0x5000_0038)
Bits
Description
Alternate Function Setting For PA15MFP
00 = GPIO
[31:30]
[29:28]
PA15MFP
01 = TM1
10 = SDIN
Alternate Function Setting For PA14MFP
00 = GPIO
PA14MFP
PA13MFP
01 = TM0
10 = SDCLK
11 = SDCLKn
Alternate Function Setting For PA13MFP
00 = GPIO
[27:26]
01 = PWM1
10 = SPKM
11 = I2S_BCLK
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Alternate Function Setting For PA12MFP
00 = GPIO
01 = PWM0
10 = SPKP
11 = I2S_FS
[25:24]
[23:22]
[21:20]
PA12MFP
PA11MFP
PA10MFP
Alternate Function Setting For PA11MFP
00 = GPIO
01 = I2C_SCL
10 = I2S_SDO
11 = UART_CTSn
Alternate Function Setting For PA10MFP
00 = GPIO
01 = I2C_SDA
10 = I2S_SDI
11 = UART_RTSn
Alternate Function Setting For PA0MFP
00 = GPIO
[19:18]
[17:16]
PA9MFP
PA8MFP
01 = UART_RX
10 = I2S_BCLK
Alternate Function Setting For PA8MFP
00 = GPIO
01 = UART_TX
10 = I2S_FS
Alternate Function Setting For PA7MFP
00 = GPIO
[15:14]
[13:12]
[11:10]
[9:8]
PA7MFP
PA6MFP
PA5MFP
PA4MFP
01 = I2S_SDO
Alternate Function Setting For PA6MFP
00 = GPIO
01 = I2S_SDI
Alternate Function Setting For PA5MFP
00 = GPIO
01 = I2S_BCLK
Alternate Function Setting For PA4MFP
00 = GPIO
01 = I2S_FS
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Alternate Function Setting For PA3MFP
00 = GPIO
[7:6]
[5:4]
[3:2]
PA3MFP
PA2MFP
PA1MFP
01 = SPI_MISO0
10 = I2C_SDA
Alternate Function Setting For PA2MFP
00 = GPIO
01 = SPI_SSB0
Alternate Function Setting For PA1MFP
00 = GPIO
01 = SPI_SCLK
10 = I2C_SCL
Alternate Function Setting For PA0MFP
00 = GPIO
[1:0]
PA0MFP
01 = SPI_MOSI0
10 = MCLK
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GPIO Alternative Function Control Register (SYS_GPB_MFP)
Each GPIO pin can take on multiple alternate functions depending on the setting of this register. Each
pin has two bits of alternate function control. Set to 00 the pin is a standard GPIO pin whose attributes
are defined by the GPIO control registers (See Section 0). Set to other values the pin is assigned to a
peripheral as outlined in table below.
Register
Offset
R/W
Description
Reset Value
SYS_GPB_MFP
SYS_BA+0x3C
R/W
0x0000_0000
GPIOB multiple function control register
31
23
15
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
8
PB4MFP
0
PB7MFP
PB6MFP
PB2MFP
PB5MFP
PB1MFP
7
4
1
PB3MFP
PB0MFP
Table 5-8 GPIOB Alternate Function Register (SYS_GPB_MFP address 0x5000_003C)
Bits
Description
[31:16]
Reserved
PB7MFP
Reserved
Alternate Function Setting For PB7MFP
00 = GPIO
[15:14]
01 = I2S_SDO
10 = CMP7
Alternate Function Setting For PB6MFP
00 = GPIO
[13:12]
[11:10]
PB6MFP
PB5MFP
01 = I2S_SDI
10 = CMP6
11 = SPI_MOSI1
Alternate Function Setting For PB5MFP
00 = GPIO
01 = PWM1B
10 = CMP5
11 = SPI_MISO1
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Alternate Function Setting For PB4MFP
00 = GPIO
[9:8]
[7:6]
[5:4]
[3:2]
[1:0]
PB4MFP
PB3MFP
PB2MFP
PB1MFP
PB0MFP
01 = PWM0B
10 = CMP4
11 = SPI_MOSI0
Alternate Function Setting For PB3MFP
00 = GPIO
01 = I2C_SDA
10 = CMP3
11 = SPI_MISO0
Alternate Function Setting For PB2MFP
00 = GPIO
01 = I2C_SCL
10 = CMP2
11 = SPI_SCLK
Alternate Function Setting For PB1MFP
00 = GPIO
01 = MCLK
10 = CMP1
11 = SPI_SSB1
Alternate Function Setting For PB0MFP
00 = GPIO
01 = SPI_SSB1
10 = CMP0
11 = SPI_SSB0
GPAn=01
GPAn =10
Function
MCLK
GPAn =11
Function
GPIO
Power Domain
Function
Type
Type
Type
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
SPI_MOSI0
O
O
SPI_SCLK
SPI_SSB0
SPI_MISO0
I2S_FS
IO
IO
I
I2C_SCL
IO
IO
I2C_SDA
IO
IO
I
I2S_BCLK
I2S_SDI
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GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
GPIOA12
GPIOA13
GPIOA14
GPIOA15
VDD33
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
I2S_SDO
UART_TX
UART_RX
I2C_SDA
I2C_SCL
PWM0
O
O
I
I2S_FS
I2S_BCLK
I2S_SDI
I2S_SDO
SPKP
IO
IO
I
IO
IO
O
O
I
UART_RTSn
UART_CTSn
I2S_FS
O
I
O
O
O
O
I
IO
IO
O
PWM1
SPKM
I2S_BCLK
SDCLKn
TM0
SDCLK
SDIN
TM1
I
GPBn=01
GPBn =10
Function
CMP0
GPBn =11
Function
SPI_SSB0
GPIO
Power Domain
Function
Type
Type
Type
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
SPI_SSB1
O
AIO
IO
MCLK
O
IO
IO
O
O
I
CMP1
CMP2
CMP3
CMP4
CMP5
CMP6
CMP7
AIO
AIO
AIO
AIO
AIO
AIO
AIO
SPI_SSB1
SPI_SCLK
SPI_MISO0
SPI_MOSI0
SPI_MISO1
SPI_MOSI1
O
IO
I
I2C_SCL
I2C_SDA
PWM0B
PWM1B
I2S_SDI
I2S_SDO
O
I
O
O
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Wakeup Pin Control Register (SYS_WKCTL)
The WAKEUP pin of the ISD9160 is a special purpose pin that can be used to wake the device from a
deep power down condition when all other pins of the device are inactive. When the device is active,
this register can be used to set the state of the WAKEUP pin. The default state of the pin is as a tri-
state input.
Register
Offset
R/W
Description
Reset Value
SYS_WKCTL
SYS_BA+0x54 R/W WAKEUP pin control register
0x0000_0006
7
6
5
4
3
2
1
0
Reserved
WKDIN
WKPUEN
WKOENB
WKDOUT
Table 5-9 Wakeup Pin Control Register (SYS_WKCTL, address 0x5000_0054) Bit Description.
Bits
[3]
Description
Wakeup Output State
WKDOUT
WKOENB
0 = drive Low if the corresponding output mode bit is set (default)
1 = drive High if the corresponding output mode bit is set
Wakeup Pin Output Enable Bar
0 = drive WKDOUT to pin
1 = tristate (default)
[2]
Wakeup Pin Pull-up Control
This signal is latched in deep power down and preserved.
0 = pull-up enable
[1]
[0]
WKPUEN
WKDIN
1 = tristate (default)
State Of Wakeup Pin
Read only.
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Protected Register Lock Key Register (SYS_REGLCTL)
Certain critical system control registers are protected against inadvertent write operations which may
disturb chip operation. These system control registers are locked after power on reset until the user
specifically issues an unlock sequence to open the lock. The unlock sequence is to write to
SYS_REGLCTL the data 0x59, 0x16, 0x88. Any different sequence, data or a write to any other
address will abort the unlock sequence.
MDK provides the defined function UNLOCKREG(x); which will execute this sequence.
The status of the lock can be determined by reading SYS_REGLCTL bit0: “1” is unlocked, “0” is
locked. Once unlocked, user can update protected register values. To lock registers again, write any
data to SYS_REGLCTL.
This register is write accessible for writing key values and read accessible to determine REGLCTL
status.
Register
Offset
R/W
Description
Reset Value
SYS_REGLCTL SYS_BA+0x100 R/W
Register Lock Key Address register
0x0000_0000
7
6
5
4
3
2
1
0
REGLCTL
Table 5-10 Protected Register Lock Key Register (SYS_REGLCTL address 0x5000_0100) Bit
Description.
Bits
Description
[31:1]
Reserved
Reserved
Protected Register Unlock Register
[0]
REGLCTL
0 = Protected registers are locked. Any write to the target register is ignored.
1 = Protected registers are unlocked
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Oscillator Trim Control Register (SYS_IRCTCTL)
The master oscillator of the ISD9160 has an adjustable frequency and is controlled by the
SYS_IRCTCTL register. This register contains two oscillator frequency trim values, which one is active
depends upon the setting of register CLK_CLKSEL0.HIRCFSEL bit. If this bit is 0, SYS_IRCTCTL[0] is
active, if 1 then SYS_IRCTCTL[1] is active. Upon power on reset this register is loaded from flash
memory with factory stored values to give oscillator frequencies of 49.152MHz for SYS_IRCTCTL[0]
and 32.768MHz for SYS_IRCTCTL[1]. If users wish to change either of the default frequencies it is
possible to do so by setting this register. An additional SUPERFINE trim register is also available to
interpolate frequencies between the available SYS_IRCTCTL settings (see Table 7-37)
This register is a protected register, to write to register first issue the unlock sequence (see Protected
Register Lock Key Register (SYS_REGLCTL))
Register
Offset
R/W Description
Reset Value
SYS_IRCTCTL SYS_BA+0x110 R/W Oscillator Frequency Adjustment control register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
RGE1SEL
16
Reserved
20
FREQ1SEL
12
8
RGE0SEL
0
Reserved
4
1
FREQ0SEL
Table 5-11 Oscillator Frequency Adjustment Control Register (SYS_IRCTCTL, address
0x5000_0110).
Bits
Description
Range Bit For Oscillator
[24]
RGE1SEL
FREQ1SEL
RGE0SEL
FREQ0SEL
0 = high range
1 = low range
8 Bit Trim For Oscillator
[23:16]
[8]
FREQ1SEL [7:5] are 8 coarse trim ranges which overlap in frequency. FREQ1SEL
[4:0] are 32 fine trim steps of approximately 0.5% resolution.
Range Bit For Oscillator
0 = high range
1 = low range
8 Bit Trim For Oscillator
[7:0]
FREQ0SEL [7:5] are 8 coarse trim ranges which overlap in frequency. FREQ0SEL
[4:0] are 32 fine trim steps of approximately 0.5% resolution.
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5.2.6 System Timer (SysTick)
The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
An RTOS tick timer which fires at a programmable rate (for example 100Hz) and invokes a
SysTick routine.
A high speed alarm timer using Core clock.
A variable rate alarm or signal timer – the duration range dependent on the reference clock used
and the dynamic range of the counter.
A simple counter. Software can use this to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
When enabled, the timer will count down from the value in the SysTick Current Value Register
(SYST_CVR) to zero, reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR)
on the next clock edge, then decrement on subsequent clocks. When the counter transitions to zero,
the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than
an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
In DEEPSLEEP and power down modes, the SysTick timer is disabled so cannot be used to wake up
the device.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”.
5.2.6.1 System Timer Control Register Map
R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear
Register
Offset
R/W
Description
Reset Value
SYSTICK Base Address:
SYSTICK_BA = 0xE000_E000
SYST_CSR
SYST_RVR
SYST_CVR
SYSTICK_BA+0x10 R/W
SYSTICK_BA+0x14 R/W
SYSTICK_BA+0x18 R/W
SysTick Control and Status Register
SysTick Reload value Register
SysTick Current value Register
0x0000_0004
0xXXXX_XXXX
0xXXXX_XXXX
5.2.6.2 System Timer Control Register Description
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SysTick Control and Status （SYST_CSR）
Register
Offset
R/W
Description
Reset Value
SYST_CSR
SYSTICK_BA+0x10 R/W
SysTick Control and Status Register
0x0000_0004
Table 5-12 SysTick Control and Status Register (SYST_CSR, address 0xE000_E010)
31
23
15
7
30
22
14
6
29
21
13
28
27
19
11
3
26
18
10
25
17
9
24
Reserved
20
16
Reserved
12
COUNTFLAG
8
Reserved
5
4
2
1
0
Reserved
CLKSRC
TICKINT
ENABLE
Bits
Description
[31:17]
Reserved
Reserved
Count Flag
Returns 1 if timer counted to 0 since last time this register was read.
0= Cleared on read or by a write to the Current Value register.
1= Set by a count transition from 1 to 0.
[16]
COUNTFLAG
[15:3]
[2]
Reserved
Reserved
Clock Source
0= Core clock unused.
CLKSRC
1= Core clock used for SysTick, this bit will read as 1 and ignore writes.
Enables SysTick Exception Request
0 = Counting down to 0 does not cause the SysTick exception to be pended.
Software can use COUNTFLAG to determine if a count to zero has occurred.
1 = Counting down to 0 will cause SysTick exception to be pended. Clearing the
SysTick Current Value register by a register write in software will not cause
SysTick to be pended.
[1]
[0]
TICKINT
ENABLE
ENABLE
0 = The counter is disabled
1 = The counter will operate in a multi-shot manner.
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SysTick Reload Value Register （SYST_RVR）
Register
Offset
R/W
Description
Reset Value
SYST_RVR
SYSTICK_BA+0x14 R/W
SysTick Reload value Register
0xXXXX_XXXX
Table 5-13 SysTick Reload Value Register (SYST_RVR, address 0xE000_E014)
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
Reserved
20
19
RELOAD[23:16]
12 11
RELOAD[15:8]
4
3
1
0
RELOAD[7:0]
Bits
Description
[31:24]
Reserved
Reserved
SysTick Reload
Value to load into the Current Value register when the counter reaches 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a
RELOAD value of N-1. For example, if the SysTick interrupt is required every 200
clock pulses, set RELOAD to 199.
[23:0]
RELOAD
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SysTick Current Value Register （SYST_CVR）
Register
Offset
R/W
Description
Reset Value
SYST_CVR
SYSTICK_BA+0x18 R/W
SysTick Current value Register
0xXXXX_XXXX
Table 5-14 SysTick Current Value Register (SYST_CVR, address 0xE000_E018)
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
Reserved
20
19
CURRENT [23:16]
12 11
CURRENT [15:8]
4
3
1
0
CURRENT[7:0]
Bits
Description
[31:24]
Reserved
Reserved
Current Counter Value
This is the value of the counter at the time it is sampled. The counter does not provide
read-modify-write protection. The register is write-clear. A software write of any value
will clear the register to 0 and also clear the COUNTFLAG bit.
[23:0]
CURRENT
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5.2.7 Nested Vectored Interrupt Controller (NVIC)
Cortex-M0 includes an interrupt controller the “Nested Vectored Interrupt Controller (NVIC)”. It is
closely coupled to the processor kernel and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority changing
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When
an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When any interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and branch
to the starting address of the corresponding ISR by software. While the starting address is fetched,
NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12”
to the stack. At the end of the ISR, the NVIC will restore the above mentioned registers from the stack
and resume normal execution. This provides a high speed and deterministic time to process any
interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of state saving and restoration and therefore reduces delay time in switching to a pending
ISR at the end of the current ISR. The NVIC also supports “Late Arrival” which improves the efficiency
of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to
execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the
higher one without delay penalty. This aids real-time, high priority, interrupt capability.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and ““ARM® v6-M Architecture Reference Manual”.
5.2.7.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by ISD9160. Software can set four levels of
priority on certain exceptions as well as on all interrupts. The highest user-configurable priority is
denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable
interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system
exceptions “Reset”, “NMI” and “Hard Fault”.
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Table 5-15 Exception Model
Exception Name
Vector Number
Priority
Reset
NMI
1
2
-3
-2
Hard Fault
Reserved
3
-1
4 ~ 10
11
N/A
SVCall
Configurable
N/A
Reserved
12 ~ 13
14
PendSV
SysTick
Configurable
Configurable
Configurable
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 5-16 System Interrupt Map
Interrupt Number
Vector
Number
Interrupt
Name
Source IP
Interrupt description
(Bit in Interrupt
Registers)
-
0 ~ 15
16
-
-
Brown-Out
WDT
System exceptions
BOD_IRQn
WDT_IRQn
EINT0_IRQn
EINT1_IRQn
GPAB_IRQn
ALC_IRQn
PWM_IRQn
Reserved
0
1
2
3
4
5
6
7
8
Brownout low voltage detector interrupt
Watch Dog Timer interrupt
17
18
GPIO
External signal interrupt from PB.0 pin
External signal interrupt from PB.1 pin
External signal interrupt from PA[15:0] / PB[7:2]
Automatic Level Control Interrupt
PWM0, PWM1 interrupt
19
GPIO
20
GPIO
21
ALC
22
PWM01
23
TMR0_IRQn
24
TMR0
Timer 0 interrupt
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TMR1_IRQn
Reserved
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
TMR1
Timer 1 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Reserved
UART0_IRQn
Reserved
UART0
SPI0
UART0 interrupt
SPI0 interrupt
SPI0_IRQn
Reserved
Reserved
Reserved
I2C0_IRQn
Reserved
I2C0
I2C0 interrupt
Reserved
TALARM
Temperature Alarm Interrupt
TALARM_IRQn
Reserved
Reserved
Reserved
ACMP_IRQn
PDMA_IRQn
I2S_IRQn
ACMP
PDMA
I2S
Analog Comparator-0 or Comaprator-1 interrupt
PDMA interrupt
I2S interrupt
Capacitive Touch Sensing Relaxation Oscillator
Interrupt
CAPS_IRQn
44
28
ANA
ADC_INT
Reserved
RTC_INT
45
46
47
29
30
31
SDADC
Audio ADC interrupt
RTC
Real time clock interrupt
5.2.7.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from the vector table in memory. For ARMv6-M, the vector table base
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address is fixed in flash at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table.
Vector Table
Description
Word Offset
0
SP_main - The Main stack pointer
Vector Number
Exception Entry Pointer using that Vector Number
Table 5-17 Vector Table Format
5.2.7.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until
cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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5.2.7.4 NVIC Control Registers
R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear
Register
Offset
R/W
Description
Reset Value
SCS Base Address:
SCS_BA = 0xE000_E000
NVIC_ISER
NVIC_ICER
NVIC_ISPR
NVIC_ICPR
NVIC_IPR0
NVIC_IPR1
NVIC_IPR2
NVIC_IPR3
NVIC_IPR4
NVIC_IPR5
NVIC_IPR6
NVIC_IPR7
SCS_BA+0x100
SCS_BA+0x180
SCS_BA+0x200
SCS_BA+0x280
SCS_BA+0x400
SCS_BA+0x404
SCS_BA+0x408
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ0 ~ IRQ31 Set-Enable Control Register
IRQ0 ~ IRQ31 Clear-Enable Control Register
IRQ0 ~ IRQ31 Set-Pending Control Register
IRQ0 ~ IRQ31 Clear-Pending Control Register
IRQ0 ~ IRQ3 Priority Control Register
IRQ4 ~ IRQ7 Priority Control Register
IRQ8 ~ IRQ11 Priority Control Register
IRQ12 ~ IRQ15 Priority Control Register
IRQ16 ~ IRQ19 Priority Control Register
IRQ20 ~ IRQ23 Priority Control Register
IRQ24 ~ IRQ27 Priority Control Register
IRQ28 ~ IRQ31 Priority Control Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
SCS_BA+0x40C R/W
SCS_BA+0x410
SCS_BA+0x414
SCS_BA+0x418
R/W
R/W
R/W
SCS_BA+0x41C R/W
Release Date: Mar 30, 2016
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IRQ0 ~ IRQ31 Set-Enable Control Register （NVIC_ISER）
Register
Offset
R/W
Description
Reset Value
NVIC_ISER
SCS_BA+0x100 R/W
IRQ0 ~ IRQ31 Set-Enable Control Register
0x0000_0000
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is
not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never
activates the interrupt, regardless of its priority.
Table 5-18 Interrupt Set-Enable Control Register (ISER, address 0xE000_E100) Bit Description
Bits
Description
Set-Enable Control
Enable one or more interrupts within a group of 32. Each bit represents an interrupt
number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will enable the associated interrupt.
Writing 0 has no effect.
[31:0]
SETENA
The register reads back the current enable state.
Release Date: Mar 30, 2016
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IRQ0 ~ IRQ31 Clear-Enable Control Register (NVIC_ICER）
Register
Offset
R/W
Description
Reset Value
NVIC_ICER
SCS_BA+0x180 R/W
IRQ0 ~ IRQ31 Clear-Enable Control Register
0x0000_0000
Table 5-19 Interrupt Clear-Enable Control Register (ICER, address 0xE000_E180) Bit Description
Bits
Description
Clear-Enable Control
Disable one or more interrupts within a group of 32. Each bit represents an interrupt
number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).
Writing 1 will disable the associated interrupt.
Writing 0 has no effect.
[31:0]
CLRENA
The register reads back with the current enable state.
Release Date: Mar 30, 2016
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IRQ0 ~ IRQ31 Set-Pending Control Register （NVIC_ISPR）
Register
Offset
R/W
Description
Reset Value
NVIC_ISPR
SCS_BA+0x200 R/W
IRQ0 ~ IRQ31 Set-Pending Control Register
0x0000_0000
Table 5-20 Interrupt Set-Pending Control Register (ISPR, address 0xE000_E200)
Bits
Description
Set-Pending Control
Writing 1 to a bit forces pending state of the associated interrupt under software
control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number
from 16 ~ 47).
[31:0]
SETPEND
Writing 0 has no effect.
The register reads back with the current pending state.
Release Date: Mar 30, 2016
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IRQ0 ~ IRQ31 Clear-Pending Control Register （NVIC_ICPR）
Register
Offset
R/W
Description
Reset Value
NVIC_ICPR
SCS_BA+0x280 R/W
IRQ0 ~ IRQ31 Clear-Pending Control Register
0x0000_0000
Table 5-21 Interrupt Clear-Pending Control Register (ICPR, address 0xE000_E280)
Bits
Description
Clear-Pending Control
Writing 1 to a bit to clear the pending state of associated interrupt under software
control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number
from 16 ~ 47).
[31:0]
CLRPEND
Writing 0 has no effect.
The register reads back with the current pending state.
Release Date: Mar 30, 2016
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IRQ0 ~ IRQ3 Interrupt Priority Register （NVIC_IPR0）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR0
SCS_BA+0x400 R/W
IRQ0 ~ IRQ3 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_3
PRI_2
PRI_1
PRI_0
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-22 Interrupt Priority Register (IPR0, address 0xE000_E400)
Bits
Description
PRI_3
Priority of IRQ3
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ2
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_2
PRI_1
PRI_0
Priority of IRQ1
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ0
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ4 ~ IRQ7 Interrupt Priority Register （NVIC_IPR1）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR1
SCS_BA+0x404 R/W
IRQ4 ~ IRQ7 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_7
PRI_6
PRI_5
PRI_4
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-23 Interrupt Priority Register (IPR1, address 0xE000_E404)
Bits
Description
PRI_7
Priority of IRQ7
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ6
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_6
PRI_5
PRI_4
Priority of IRQ5
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ4
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ8 ~ IRQ11 Interrupt Priority Register （NVIC_IPR2）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR2
SCS_BA+0x408 R/W
IRQ8 ~ IRQ11 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_11
PRI_10
PRI_9
PRI_8
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-24 Interrupt Priority Register (IPR2, address 0xE000_E408)
Bits
Description
PRI_11
Priority of IRQ11
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ10
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_10
PRI_9
PRI_8
Priority of IRQ9
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ8
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ12 ~ IRQ15 Interrupt Priority Register （NVIC_IPR3）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR3
SCS_BA+0x40C R/W
IRQ12 ~ IRQ15 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_15
PRI_14
PRI_13
PRI_12
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-25 Interrupt Priority Register (IPR3, address 0xE000_E40C)
Bits
Description
PRI_15
Priority of IRQ15
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ14
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_14
PRI_13
PRI_12
Priority of IRQ13
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ12
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ16 ~ IRQ19 Interrupt Priority Register （NVIC_IPR4）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR4
SCS_BA+0x410 R/W
IRQ16 ~ IRQ19 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_19
PRI_18
PRI_17
PRI_16
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-26 Interrupt Priority Register (IPR4, address 0xE000_E410)
Bits
Description
PRI_19
Priority of IRQ19
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ18
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_18
PRI_17
PRI_16
Priority of IRQ17
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ16
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ20 ~ IRQ23 Interrupt Priority Register （NVIC_IPR5）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR5
SCS_BA+0x414 R/W
IRQ20 ~ IRQ23 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_23
PRI_22
PRI_21
PRI_20
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-27 Interrupt Priority Register (IPR5, address 0xE000_E414)
Bits
Description
PRI_23
Priority of IRQ23
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ22
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_22
PRI_21
PRI_20
Priority of IRQ21
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ20
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ24 ~ IRQ27 Interrupt Priority Register （NVIC_IPR6）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR6
SCS_BA+0x418 R/W
IRQ24 ~ IRQ27 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_27
PRI_26
PRI_25
PRI_24
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-28 Interrupt Priority Register (IPR6, address 0xE000_E418)
Bits
Description
PRI_27
Priority of IRQ27
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ26
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_26
PRI_25
PRI_24
Priority of IRQ25
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ24
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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IRQ28 ~ IRQ31 Interrupt Priority Register （NVIC_IPR7）
Register
Offset
R/W
Description
Reset Value
NVIC_IPR7
SCS_BA+0x41C R/W
IRQ28 ~ IRQ31 Priority Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_31
PRI_30
PRI_29
PRI_28
Reserved
Reserved
Reserved
Reserved
1
0
Table 5-29 Interrupt Priority Register (IPR7, address 0xE000_E41C)
Bits
Description
PRI_31
Priority of IRQ31
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
Priority of IRQ30
“0” denotes the highest priority and “3” denotes lowest priority
[23:22]
[15:14]
[7:6]
PRI_30
PRI_29
PRI_28
Priority of IRQ29
“0” denotes the highest priority and “3” denotes lowest priority
Priority of IRQ28
“0” denotes the highest priority and “3” denotes lowest priority
Release Date: Mar 30, 2016
Revision V1.41
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5.2.7.5 Interrupt Source Control Registers
Along with the interrupt control registers associated with the NVIC, the ISD9160 also implements
some specific control registers to facilitate the interrupt functions, including “interrupt source
identify”, ”NMI source selection” and “interrupt test mode”. They are described as below.
R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear
Register
Offset
R/W
Description
Reset Value
INT Base Address:
INT_BA = 0x5000_0300
IRQ0_SRC
IRQ1_SRC
IRQ2_SRC
IRQ3_SRC
IRQ4_SRC
IRQ5_SRC
IRQ6_SRC
IRQ7_SRC
IRQ8_SRC
IRQ9_SRC
IRQ10_SRC
IRQ11_SRC
IRQ12_SRC
IRQ13_SRC
IRQ14_SRC
IRQ15_SRC
IRQ16_SRC
IRQ17_SRC
IRQ18_SRC
IRQ19_SRC
IRQ20_SRC
IRQ21_SRC
IRQ22_SRC
INT_BA+0x00
INT_BA+0x04
INT_BA+0x08
INT_BA+0x0C
INT_BA+0x10
INT_BA+0x14
INT_BA+0x18
INT_BA+0x1C
INT_BA+0x20
INT_BA+0x24
INT_BA+0x28
INT_BA+0x2C
INT_BA+0x30
INT_BA+0x34
INT_BA+0x38
INT_BA+0x3C
INT_BA+0x40
INT_BA+0x44
INT_BA+0x48
INT_BA+0x4C
INT_BA+0x50
INT_BA+0x54
INT_BA+0x58
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
IRQ0 (BOD) Interrupt Source Identity Register
IRQ1 (WDT) Interrupt Source Identity Register
IRQ2 (EINT0) Interrupt Source Identity Register
IRQ3 (EINT1) Interrupt Source Identity Register
IRQ4 (GPA/B) Interrupt Source Identity Register
IRQ5 (ALC) Interrupt Source Identity Register
IRQ6 (PWMA) Interrupt Source Identity Register
IRQ7 (Reserved) Interrupt Source Identity Register
IRQ8 (TMR0) Interrupt Source Identity Register
IRQ9 (TMR1) Interrupt Source Identity Register
IRQ10 (Reserved) Interrupt Source Identity Register
IRQ11 (Reserved) Interrupt Source Identity Register
IRQ12 (UART0) Interrupt Source Identity Register
IRQ13 (Reserved) Interrupt Source Identity Register
IRQ14 (SPI0) Interrupt Source Identity Register
IRQ15 (Reserved) Interrupt Source Identity Register
IRQ16 (Reserved) Interrupt Source Identity Register
IRQ17 (Reserved) Interrupt Source Identity Register
IRQ18 (I2C0) Interrupt Source Identity Register
IRQ19 (Reserved) Interrupt Source Identity Register
IRQ20 (Reserved) Interrupt Source Identity Register
IRQ21 (TALARM) Interrupt Source Identity Register
IRQ22 (Reserved ) Interrupt Source Identity Register
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
Release Date: Mar 30, 2016
Revision V1.41
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IRQ23_SRC
IRQ24_SRC
IRQ25_SRC
IRQ26_SRC
IRQ27_SRC
IRQ28_SRC
IRQ29_SRC
IRQ30_SRC
IRQ31_SRC
NMI_SEL
INT_BA+0x5C
INT_BA+0x60
INT_BA+0x64
INT_BA+0x68
INT_BA+0x6C
INT_BA+0x70
INT_BA+0x74
INT_BA+0x78
INT_BA+0x7C
INT_BA+0x80
INT_BA+0x84
R
IRQ23 (Reserved) Interrupt Source Identity Register
IRQ24 (Reserved) Interrupt Source Identity Register
IRQ25 (ACMP) Interrupt Source Identity Register
IRQ26 (PDMA) Interrupt Source Identity Register
IRQ27 (I2S) Interrupt Source Identity Register
IRQ28 (CAPS) Interrupt Source Identity Register
IRQ29 (ADC) Interrupt Source Identity Register
IRQ30 (Reserved) Interrupt Source Identity Register
IRQ31 (RTC) Interrupt Source Identity Register
NMI Source Interrupt Select Control Register
MCU IRQ Number Identify Register
0xXXXX_XXXX
R
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0x0000_0000
R
R
R
R
R
R
R
R/W
R/W
MCU_IRQ
0x0000_0000
Release Date: Mar 30, 2016
Revision V1.41
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IRQ0(BOD) Interrupt Source Identify Register (IRQ0_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ0_SRC
INT_BA+0x00
R
IRQ0 (BOD) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: BOD_INT
Release Date: Mar 30, 2016
Revision V1.41
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IRQ1(WDT) Interrupt Source Identify Register (IRQ1_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ1_SRC
INT_BA+0x04
R
IRQ1 (WDT) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: WDT_INT
Release Date: Mar 30, 2016
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IRQ2(ENIT0) Interrupt Source Identify Register (IRQ2_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ2_SRC
INT_BA+0x08
R
IRQ2 (EINT0) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: INT0_INT
Release Date: Mar 30, 2016
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IRQ3(ENIT1) Interrupt Source Identify Register (IRQ3_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ3_SRC
INT_BA+0x0C
R
IRQ3 (EINT1) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: INT0_INT
Release Date: Mar 30, 2016
Revision V1.41
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IRQ4(GPA/B) Interrupt Source Identify Register (IRQ4_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ4_SRC
INT_BA+0x10
R
IRQ4 (GPA/B) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: GPB_INT
Bit0: GPA_INT
Release Date: Mar 30, 2016
Revision V1.41
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IRQ5(ALC) Interrupt Source Identify Register (IRQ5_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ5_SRC
INT_BA+0x14
R
IRQ5 (ALC) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: ALC_INT
Release Date: Mar 30, 2016
Revision V1.41
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IRQ6(PWMA) Interrupt Source Identify Register (IRQ6_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ6_SRC
INT_BA+0x18
R
IRQ6 (PWMA) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: PWM_INT
Release Date: Mar 30, 2016
Revision V1.41
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IRQ8(TMR0) Interrupt Source Identify Register (IRQ8_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ8_SRC
INT_BA+0x20
R
IRQ8 (TMR0) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: TMR0_INT
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IRQ9(TMR1) Interrupt Source Identify Register (IRQ9_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ9_SRC
INT_BA+0x24
R
IRQ9 (TMR1) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: TMR1_INT
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IRQ12(UART0) Interrupt Source Identify Register (IRQ8_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ12_SRC
INT_BA+0x30
R
IRQ12 (UART0) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: UART0_INT
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IRQ14(SPI0) Interrupt Source Identify Register (IRQ14_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ14_SRC
INT_BA+0x38
R
IRQ14 (SPI0) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: SPI0_INT
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IRQ18(I2C0) Interrupt Source Identify Register (IRQ18_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ18_SRC
INT_BA+0x48
R
IRQ18 (I2C0) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: I2C0_INT
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IRQ21(TALARM) Interrupt Source Identify Register (IRQ21_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ21_SRC
INT_BA+0x54
R
IRQ21 (TALARM) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: TALARM_INT
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IRQ25(TALARM) Interrupt Source Identify Register (IRQ25_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ25_SRC
INT_BA+0x64
R
IRQ25 (ACMP) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: TALARM_INT
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IRQ26(PDMA) Interrupt Source Identify Register (IRQ26_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ26_SRC
INT_BA+0x68
R
IRQ26 (PDMA) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: PDMA_INT
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IRQ27(I2S) Interrupt Source Identify Register (IRQ27_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ27_SRC
INT_BA+0x6C
R
IRQ27 (I2S) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: I2S_INT
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IRQ28(CAPS) Interrupt Source Identify Register (IRQ28_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ28_SRC
INT_BA+0x70
R
IRQ28 (CAPS) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: CAPS_INT
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IRQ29(ADC) Interrupt Source Identify Register (IRQ29_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ29_SRC
INT_BA+0x74
R
IRQ29 (ADC) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: ADC_INT
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IRQ31(RTC) Interrupt Source Identify Register (IRQ31_SRC)
Register
Offset
R/W
Description
Reset Value
IRQ31_SRC
INT_BA+0x7C
R
IRQ31 (RTC) Interrupt Source Identity Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
INT_SRC[2:0]
Bits
Description
INT_SRC
Interrupt Source Identity
Bit2: 0
[2:0]
Bit1: 0
Bit0: RTC_INT
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NMI Interrupt Source Select Control Register (NMI_SEL)
Register
NMI_SEL
Offset
R/W
Description
Reset Value
INT_BA+0x80
R/W
NMI Source Interrupt Select Control Register
0x0000_0000
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
2
1
0
IRQ_TM
Reserved
NMI_SEL[4:0]
Bits
Description
[31:7]
Reserved
Reserved
IRQ Test Mode
If set to 1 then peripheral IRQ signals (0-31) are replaced by the value in the
MCU_IRQ register. This is a protected register to program first issue the unlock
sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
[7]
IRQ_TM
NMI Source Interrupt Select
[4:0]
NMI_SEL
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]
The NMI_SEL bit[4:0] used to select the NMI interrupt source
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MCU Interrupt Request Source Test Mode Register (MCU_IRQ)
Register
Offset
R/W
Description
Reset Value
MCU_IRQ
INT_BA+0x84
R/W
MCU IRQ Number Identify Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
26
18
10
2
25
17
9
24
16
8
MCU_IRQ[31:24]
20
12
4
MCU_IRQ[23:16]
11
MCU_IRQ[15:8]
3
1
0
MCU_IRQ[7:0]
Bits
Description
MCU IRQ Source Test Mode
In Normal mode (NMI_SEL register bit [7] aaa 0) The device collects interrupts from
each peripheral and synchronizes them to interrupt the Cortex-M0.
In Test mode (NMI_SEL register bit [7] aaa 1), the interrupts from peripherals are
blocked, and the interrupts are replaces by MCU_IRQ[31:0].
[31:0]
MCU_IRQ
When MCU_IRQ[n] is “0” : Writing MCU_IRQ[n] “1” will generate an interrupt to
Cortex_M0 NVIC[n].
When MCU_IRQ[n] is “1” (meaning an interrupt is asserted) writing MCU_bit[n] ‘1’ will
clear the interrupt
Writing MCU_IRQ[n] “0” : has no effect.
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5.2.8 System Control Registers
Key control and status features of Coterx-M0 are managed centrally in a System Control Block within
the System Control Registers.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”.
R: read only, W: write only, R/W: both read and write, W&C: Write 1 clear
Register
Offset
R/W Description
Reset Value
SYSINFO Base Address:
SYSINFO_BA = 0xE000_E000
SYSCTL_CPUID
SYSCTL_ICSR
SYSCTL_AIRCTL
SYSCTL_SCR
SYSINFO_BA+0xD00
SYSINFO_BA+0xD04
SYSINFO_BA+0xD0C
SYSINFO_BA+0xD10
SYSINFO_BA+0xD1C
SYSINFO_BA+0xD20
R
CPUID Base Register
0x410C_C200
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
R/W Interrupt Control State Register
R/W Application Interrupt and Reset Control Register
R/W System Control Register
SYSCTL_SHPR2
SYSCTL_SHPR3
R/W System Handler Priority Register 2
R/W System Handler Priority Register 3
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CPUID Base Register (SYSCTL_CPUID)
Register
Offset
R/W
Description
Reset Value
SYSCTL_CPUID
SYSINFO_BA+0xD00
R
CPUID Base Register
0x410C_C200
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
IMPCODE[7:0]
19
26
18
10
2
25
17
9
24
16
8
Reserved
PARTNO
PART[3:0]
11
PARTNO
3
1
0
REVISION[3:0]
Bits
Description
IMPCODE
Implementer Code Assigned By ARM
[31:24]
ARM aaa 0x41.
[23:20]
[19:16]
Reserved
Reserved
ARMv6-M Parts
PART
Reads as 0xC for ARMv6-M parts
Part Number
[15:4]
[3:0]
PARTNO
Reads as 0xC20.
Revision
REVISION
Reads as 0x0
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Interrupt Control State Register (SYSCTL_ICSR)
Register
Offset
R/W
Description
Reset Value
SYSCTL_ICSR
SYSINFO_BA+0xD04
R/W
Interrupt Control State Register
0x0000_0000
31
NMIPNSET
23
30
22
29
28
27
PPSVICLR
19
26
25
PSTKICLR
17
24
Reserved
16
Reserved
PPSVISET
20
PSTKISET
21
Reserved
13
18
ISRPREEM
15
ISRPEND
14
VTPEND[8:4]
12
4
11
3
10
Reserved
2
9
1
8
VTACT[8]
0
VTPEND[3:0]
7
6
5
VTACT[7:0]
Bits
[31]
Description
NMIPNSET
NMI Pending Set Control
Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as
soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
Set A Pending PendSV Interrupt
This is normally used to request a context switch. Reads back with current state (1 if Pending, 0
if not).
[28]
[27]
PPSVISET
PPSVICLR
Clear A Pending PendSV Interrupt
Write 1 to clear a pending PendSV interrupt.
Set A pending SysTick
Reads back with current state (1 if Pending, 0 if not).
[26]
[25]
PSTKISET
PSTKICLR
Clear A pending SysTick
Write 1 to clear a pending SysTick.
ISR Preemptive
[23]
[22]
ISRPREEM
ISRPEND
If set, a pending exception will be serviced on exit from the debug halt state.
ISR Pending
Indicates if an external configurable (NVIC generated) interrupt is pending.
Vector Pending
Indicates the exception number for the highest priority pending exception. The pending state
includes the effect of memory-mapped enable and mask registers. It does not include the
PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
[20:12]
[8:0]
VTPEND
VTACT
Vector Active
0: Thread mode
Value > 1: the exception number for the current executing exception.
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Application Interrupt and Reset Control Register (SYSCTL_AIRCTL)
Register Offset R/W Description
Reset Value
Application Interrupt and Reset Control Register
SYSCTL_AIRCTL SYSINFO_BA+0xD0C
R/W
0x0000_0000
31
23
30
22
14
6
29
21
13
28
20
12
4
27
19
26
18
10
25
17
9
24
16
8
VTKEY
VTKEY
15
ENDIANES
7
11
Reserved
3
5
2
1
0
Reserved
SRSTREQ
CLRACTVT
Reserved
Bits
Description
VTKEY
Vector Key
[31:16]
[15]
The value 0x05FA must be written to this register, otherwise
a write to register is UNPREDICTABLE.
Endianess
ENDIANES
SRSTREQ
Read Only. Reads 0 indicating little endian machine.
System Reset Request
0 =do not request a reset.
1 =request reset.
[2]
[1]
Writing 1 to this bit asserts a signal to request a reset by the external system.
Clear All Active Vector
Clears all active state information for fixed and configurable exceptions.
0= do not clear state information.
1= clear state information.
The effect of writing a 1 to this bit if the processor is not halted in Debug, is
UNPREDICTABLE.
CLRACTVT
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System Control Register (SYSCTL_SCR)
Register
Offset
R/W Description
Reset Value
SYSCTL_SCR
SYSINFO_BA+0xD10
R/W System Control Register
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
6
3
2
1
0
Reserved
SEVNONPN
Reserved
SLPDEEP
SLPONEXC
Reserved
Bits
Description
SEVNONPN
Send Event On Pending Bit
0 = only enabled interrupts or events can wake-up the processor, disabled interrupts
are excluded.
1 = enabled events and all interrupts, including disabled interrupts, can wake-up the
processor.
When enabled, interrupt transitions from Inactive to Pending are included in the list of
wakeup events for the WFE instruction.
When an event or interrupt enters pending state, the event signal wakes up the
processor from WFE. If the processor is not waiting for an event, the event is
registered and affects the next WFE.
[4]
The processor also wakes up on execution of an SEV instruction.
Sleep Deep Control
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter
deeper power-down states than purely core sleep states.
[2]
[1]
SLPDEEP
Sleep On Exception
When set to 1, the core can enter a sleep state on an exception return to Thread
mode. This is the mode and exception level entered at reset, the base level of
execution. Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
SLPONEXC
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System Handler Priority Register 2 (SYSCTL_SHPR2)
Register
Offset
R/W Description
Reset Value
SYSCTL_SHPR2
SYSINFO_BA+0xD1C
R/W System Handler Priority Register 2
0x0000_0000
31
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI11
23
Reserved
Reserved
Reserved
Reserved
15
7
1
0
Bits
Description
PRI11
Priority Of System Handler 11 – SVCall
“0” denotes the highest priority and “3” denotes lowest priority
[31:30]
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System Handler Priority Register 3 (SYSCTL_SHPR3)
Register
Offset
R/W Description
Reset Value
SYSCTL_SHPR3
SYSINFO_BA+0xD20
R/W System Handler Priority Register 3
0x0000_0000
31
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI15
23
Reserved
Reserved
PRI14
15
Reserved
Reserved
7
1
0
Bits
Description
PRI15
Priority Of System Handler 15 – SysTick
[31:30]
“0” denotes the highest priority and “3” denotes lowest priority
Priority Of System Handler 14 – PendSV
[23:22]
PRI14
“0” denotes the highest priority and “3” denotes lowest priority
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5.3 Clock Controller and Power Management Unit (PMU)
The clock controller generates the clock sources for the whole device, including all AMBA interface
modules and all peripheral clocks. Clock gating is provided on all peripheral clocks to minimize power
consumption. The Power Management Unit (PMU) implements power control functions which can
place the device into various power saving modes. The device will enter these various modes by
requesting a power mode then requesting the Cortex-M0 to execute the WFI or the WFE instruction.
5.3.1 Clock Generator
The clock generator consists of 3 sources listed below:
An internal programmable high frequency oscillator factory trimmed to provide frequencies of
49.152MHz and 32.768MHz to 1% accuracy.
An external 32kHz crystal
An internal low power 16 kHz oscillator.
SYSCLK->PWRCON.XTL32K_EN
XI32K
CLK32K
XTL32K
XO32K
SYSCLK->CLKSEL0.OSCFSel
SYSCLK->PWRCON.OSC49M_EN
CLK48M
OSC49M
SYSCLK->PWRCON.OSC10K_EN
CLK10K
OSC10K
Figure 5-3 Clock generator block diagram
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5.3.2 System Clock & SysTick Clock
The system clock has 3 clock sources from clock generator block. The clock source switch depends
on the register HCLKSEL (CLK_CLKSEL0[2:0]). The clock is then divided by HCLKDIV+1 to produce
the master clock for the device.
SYSCLK->CLKSEL0.HCLK_S
CPUCLK
HCLK
CLK10K
CLK32K
CLK48M
010
001
000
CPU
AHB
APB
1/(HCLK_N+1)
PCLK
SYSCLK->CLKDIV.HCLK_N
Figure 5-4 System Clock Block Diagram
The SysTick clock (STCLK) has five clock sources. The clock source switch depends on the setting of
the register STCLKSEL (CLK_CLKSEL0[5:3]).
SYSCLK->CLKSEL0.STCLK_S
HCLK
1/2
1/2
1/2
1xx
011
010
001
000
CLK48M
CLK10K
CLK32K
CLK10K
STCLK
Figure 5-5 SysTick Clock Control Block Diagram
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5.3.3 Peripheral Clocks
Each peripheral has a selectable clock gate. The register CLK_APBCLK0 determines whether the
clock is active for each peripheral. In addition, the CLK_SLEEP register determines whether these
clocks remain on during M0 sleep mode. Certain peripheral clocks have selectable sources these are
controlled by the CLK_CLKSEL1 & CLK_CLKSEL2 register.
5.3.4 Power Management
The ISD9160 is equipped with a Power Management Unit (PMU) that implements a variety of power
saving modes. There are four levels of power control with increasing functionality (and power
consumption):
Level0 : Deep Power Down (DPD)
Level1 : Standby Power Down (SPD)
Level2 : Deep Sleep
Level3 : Sleep
Level4 : Normal Operation
Within each of these levels there are further options to optimize power consumption.
5.3.4.1 Level0: Deep Power Down (DPD)
Deep Power Down (DPD) is the lowest power state the device can obtain. In this state there is no
power provided to the logic domain and power consumption is only from the higher voltage chip supply
domain. All logic state in the Cortex-M0 is lost as is contents of all RAM. All IO pins of the device are
in a high impedance state. On a release from DPD the Cortex-M0 boots as if from a power-on reset.
There are certain registers that can be interrogated to allow software to determine that previous state
was a DPD state.
In DPD there are three ways to wake up the device:
1. A high to low transition on the WAKEUP pin.
2. A timed wakeup where the 16KHz oscillator is configured active and reaches a certain count.
3. A power cycle of main chip supply triggering a POR event.
To assist software in determining previous state of device before a DPD, a one-byte register is
available PD_STATE[7:0] that can be loaded with a value to be preserved before issuing a DPD
request.
To configure the device for DPD the user sets the following options:
CLK_PWRCTL.WKPINEN: If set to ‘1’ then the WAKEUP pin is disabled and will not wake up
the chip.
CLK_PWRCTL.LIRCDPDEN: If set to ‘1’ then the 16KHz oscillator will power down in DPD.
No timed wakeup is possible.
CLK_PWRCTL.SELWKTMR: Each bit in this register will trigger a wakeup event after a
certain number of OSC16K clock cycles.
When a WAKEUP event occurs the PMU will start the Cortex-M0 processor and execute the reset
vector. The condition that generated the WAKEUP event can be interrogated by reading the registers
CLK_PWRCTL.WKPINWKF, CLK_PWRCTL.TMRWKF and CLK_PWRCTL. PORWKF.
To enter the DPD state the user must set the register bit CLK_PWRCTL.DPDEN then execute a WFI
or WFE instruction. Note that when debug interface is active, device will not enter DPD. Also once
device enters DPD the debug interface will be inactive. It is possible that user could write code that
makes it impossible to activate the debug interface and reprogram device, for instance if device re-
enters DPD mode with insufficient time to allow an ICE tool to activate the SWD debug port. Especially
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during development it is recommended that some checks are placed in the boot sequence to prevent
device going to power down. A register bit, CLK_DBGPD.DISPDREQ is included for this purpose that
will disable power down features. A check such as:
void Reset_Handler(void){
/* check ICECLKST and ICEDATST to disable power down to the chip */
if ( CLK_DBGPD.ICECLKST == 0 && CLK_DBGPD.ICEDATST == 0)
CLK_DBGPD.DISPDREQ = 1;
__main();
}
Can check the SWD pin state on boot and prevent power down from occurring.
5.3.4.2 Level1: Standby Power Down (SPD) mode.
Standby Power Down mode is the lowest power state that some logic operation can be performed. In
this mode power is removed from the majority of the core logic, including the Cortex-M0 and main
RAM. A low power standby reference is enabled however that supplies power to a subset of logic
including the IO ring, GPIO control, RTC module, 32kHz Crystal Oscillator, Brownout Detector and a
256Byte Standby RAM.
In Standby mode there are three ways to wake up the device:
1. An interrupt from the GPIO block (exclude GPB0 & GPB1), for instance a pin transition.
2. An interrupt from the RTC module, for instance an alarm or timer event.
3. A power cycle of main chip supply triggering a POR event.
When a wake up event occurs the PMU will start the Cortex-M0 processor and execute the reset
vector. Software can determine whether the device woke up from SPD by interrogating the register bit
CLK_PWRSTSF.SPDF.
To enter the SPD state the user must set the register bit CLK_PWRCTL.PD then execute a WFI or
WFE instruction. Note that when debug interface is active, device will not enter SPD. Also once device
enters SPD the debug interface will be inactive.
5.3.4.3 Level2: Deep Sleep mode.
The Deep Sleep mode is the lowest power state where the Cortex-M0 and all logic state are
preserved. In Deep Sleep mode the CLK48M oscillator is shutdown and a low speed oscillator is
selected, if CLK32K is active this source is selected, if not then CLK16K is enabled and selected. All
clocks to the Cortex-M0 core are gated eliminating dynamic power in the core. Clocks to peripheral
are gated according to the CLK_SLEEP register, note however that HCLK is operating at a low
frequency and CLK48M is not available. Deep Sleep mode is entered by setting System Control
register bit 2: SCB->SCR |= (1UL << 2) and executing a WFI/WFE instruction. Software can determine
whether the device woke up from Deep Sleep by interrogating the register bit CLK_PWRSTSF.DSF.
5.3.4.4 Level3: Sleep mode.
The Sleep mode gates all clocks to the Cortex-M0 eliminating dynamic power in the core. In addition,
clocks to peripherals are gated according to the CLK_SLEEP register. The mode is entered by
executing a WFI/WFE instruction and is released when an event occurs. Peripheral functions,
including PDMA can be continued while in Sleep mode. Using this mode power consumption can be
minimized while waiting for events such as a PDMA operation collecting data from the ADC, once
PDMA has finished the core can be woken up to process the data.
5.3.5 Clock Control Register Map
R: read only, W: write only, R/W: both read and write
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Register
Offset
R/W
Description
Reset Value
CLK Base Address:
CLK_BA = 0x5000_0200
CLK_PWRCTL
CLK_AHBCLK
CLK_APBCLK0
CLK_DPDSTATE
CLK_CLKSEL0
CLK_CLKSEL1
CLK_CLKDIV0
CLK_CLKSEL2
CLK_SLEEPCTL
CLK_PWRSTSF
CLK_DBGPD
CLK_BA + 0x00 R/W
CLK_BA + 0x04 R/W
CLK_BA + 0x08 R/W
CLK_BA + 0x0C R/W
CLK_BA + 0x10 R/W
CLK_BA + 0x14 R/W
CLK_BA + 0x18 R/W
CLK_BA + 0x1C R/W
CLK_BA + 0x20 R/W
CLK_BA + 0x24 R/W
CLK_BA + 0x28 R/W
System Power Control Register
0xXX00_0006
0x0000_0005
0x0000_0000
0x0000_XX00
0x0000_0038
0x3300_771F
0x0000_0000
0xFFFF_FFFX
0xFFFF_FFFF
0x0000_0000
0x0000_00XX
AHB Device Clock Enable Control Register
APB Device Clock Enable Control Register
Deep Power Down State Register
Clock Source Select Control Register 0
Clock Source Select Control Register 1
Clock Divider Number Register
Clock Source Select Control Register 2
Sleep Clock Source Select Register
Power State Flag Register
Debug Port Power Down Disable Register
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5.3.6
Clock Control Register Description
System Power Control Register （CLK_PWRCTL）
This is a protected register, to write to register, first issue the unlock sequence (see Protected Register
Lock Key Register (SYS_REGLCTL))
Register
Offset
R/W
Description
Reset Value
CLK_PWRCTL
CLK_BA + 0x00 R/W
System Power Control Register
0xXX00_0006
Table 5-30 System Power Control Register （CLK_PWRCTL, address 0x5000_0200）
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
Reserved
19
26
PORWKF
18
25
TMRWKF
17
24
WKPINWKF
16
WKTMRSTS
SELWKTMR
Reserved
LIRCDPDEN
9
WKPINEN
8
11
DPDEN
3
10
SPDEN
2
STOP
1
Reserved
0
Reserved
LIRCEN
HIRCEN
LXTEN
Reserved
Table 5-31 System Power Control Register (CLK_PWRCTL, address 0x5000_0200) Bit Description.
Bits
Description
Current Wakeup Timer Setting
WKTMRSTS
Reserved
PORWKF
[31:28]
[27]
Read-Only. Read back of the current WAKEUP timer setting. This value is updated
with SELWKTMR upon entering DPD mode.
Reserved
POI Wakeup Flag
[26]
Read Only. This flag indicates that wakeup of device was requested with a power-on
reset. Flag is cleared when DPD mode is entered.
Timer Wakeup Flag
[25]
[24]
TMRWKF
Read Only. This flag indicates that wakeup of device was requested with TIMER count
of the 16Khz oscillator. Flag is cleared when DPD mode is entered.
Pin Wakeup Flag
WKPINWKF
Read Only. This flag indicates that wakeup of device was requested with a high to low
transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
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Select Wakeup Timer
SELWKTMR[0] aaa 1: WAKEUP after 128 OSC16K clocks (12.8 ms)
SELWKTMR[1] aaa 1: WAKEUP after 256 OSC16K clocks (25.6 ms)
SELWKTMR[2] aaa 1: WAKEUP after 512 OSC16K clocks (51.2 ms)
SELWKTMR[3] aaa 1: WAKEUP after 1024 OSC16K clocks (102.4ms)
[23:20]
SELWKTMR
[19:18]
[17]
Reserved
Reserved
OSC16K Enabled Control
Determines whether OSC16K is enabled in DPD mode. If OSC16K is disabled, device
cannot wake from DPD with SELWKTMR delay.
LIRCDPDEN
0 = enabled
1 = disabled
Wakeup Pin Enabled Control
Determines whether WAKEUP pin is enabled in DPD mode.
[16]
WKPINEN
0 = enabled
1 = disabled
[15:12]
[11]
Reserved
DPDEN
Reserved
Deep Power Down (DPD) Bit
Set to ‘1’ and issue WFI/WFE instruction to enter DPD mode.
Standby Power Down (SPD) Bit
[10]
SPDEN
Set to ‘1’ and issue WFI/WFE instruction to enter SPD mode.
Stop
[9]
STOP
Reserved – do not set to ‘1’
[8:4]
Reserved
Reserved
OSC16K Oscillator Enable Bit
0 = disable
[3]
[2]
LIRCEN
HIRCEN
1 = enable (default)
OSC49M Oscillator Enable Bit
0 = disable
1 = enable (default)
External 32.768 kHz Crystal Enable Bit
0 = disable (default)
[1]
[0]
LXTEN
1 = enable
Reserved
Reserved
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AHB Device Clock Enable Control Register （CLK_AHBCLK）
These register bits are used to enable/disable the clock source for AHB (Advanced High-Performance
Bus) blocks. This is a protected register, to write to register, first issue the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL))
Register
Offset
R/W
Description
Reset Value
CLK_AHBCLK
CLK_BA + 0x04 R/W
AHB Device Clock Enable Control Register
0x0000_0005
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
24
16
8
Reserved
Reserved
Reserved
9
2
1
0
ISPCKEN
PDMACKEN
HCLKEN
Table 5-32 AHB Device Clock Enable Register (CLK_AHBCLK, address 0x5000_0204) Bit
Description.
Bits
Description
[31:3]
Reserved
Reserved
Flash ISP Controller Clock Enable Control
0 = To disable the Flash ISP engine clock.
1 = To enable the Flash ISP engine clock.
[2]
ISPCKEN
PDMA Controller Clock Enable Control
0 = To disable the PDMA engine clock
1 = To enable the PDMA engine clock.
[1]
[0]
PDMACKEN
HCLKEN
CPU Clock Enable (HCLK)
Must be left as ‘1’ for normal operation.
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APB Device Clock Enable Control Register （CLK_APBCLK0）
These register bits are used to enable/disable clocks for APB (Advanced Peripheral Bus) peripherals.
To enable the clocks write ‘1’ to the appropriate bit. To reduce power consumption and disable the
peripheral, write ‘0’ to the appropriate bit.
Register
Offset
R/W
Description
Reset Value
CLK_APBCLK0
CLK_BA + 0x08 R/W
APB Device Clock Enable Control Register
0x0000_0000
31
Reserved
23
30
ANACKEN
22
29
I2S0CKEN
21
28
ADCCKEN
20
27
Reserved
19
26
SBRAMCKEN
18
25
Reserved
17
24
Reserved
16
PWM0CH01CKE
N
Reserved
ACMPCKEN
Reserved
CRCCKEN
BFALCKEN
Reserved
UARTCKEN
15
Reserved
7
14
Reserved
6
13
DPWMCKEN
5
12
11
10
9
8
SPI0CKEN
4
Reserved
3
Reserved
2
Reserved
1
I2C0CKEN
0
TMR1CKEN
TMR0CKEN
RTCCKEN
WDTCKEN
Reserved
Reserved
Reserved
Reserved
Table 5-33 APB Device Clock Enable Control Register (CLK_APBCLK0, address 0x5000_0208) Bit
Description.
Bits
[30]
Description
Analog Block Clock Enable Control
ANACKEN
I2S0CKEN
0=Disable
1=Enable
I2S Clock Enable Control
0=Disable
[29]
[28]
[26]
[22]
1=Enable
Audio Analog-Digital-Converter (ADC) Clock Enable Control
ADCCKEN
SBRAMCKEN
ACMPCKEN
0=Disable
1=Enable
Standby RAM Clock Enable Control
0=Disable
1=Enable
Analog Comparator Clock Enable Control
0=Disable
1=Enable
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PWM Block Clock Enable Control
[20]
[19]
[18]
[16]
[13]
[12]
[8]
PWM0CH01CKEN
CRCCKEN
0=Disable
1=Enable
Cyclic Redundancy Check Block Clock Enable Control
0=Disable
1=Enable
Biquad Filter And Automatic Level Control Block Clock Enable Control
BFALCKEN
UARTCKEN
DPWMCKEN
SPI0CKEN
0=Disable
1=Enable
UART0 Clock Enable Control
0=Disable
1=Enable
Differential PWM Speaker Driver Clock Enable Control
0=Disable
1=Enable
SPI0 Clock Enable Control
0=Disable
1=Enable
I2C0 Clock Enable Control
0=Disable
I2C0CKEN
1=Enable
Timer1 Clock Enable Control
0=Disable
[7]
TMR1CKEN
TMR0CKEN
RTCCKEN
1=Enable
Timer0 Clock Enable Control
0=Disable
[6]
1=Enable
Real-Time-Clock APB Interface Clock Control
[5]
0=Disable
1=Enable
Watchdog Clock Enable Control
0=Disable
[4]
WDTCKEN
1=Enable
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DPD State Register （CLK_DPDSTATE）
The Deep Power Down State register is a user settable register that is preserved during Deep Power
Down (DPD). Software can use this register to store a single byte during a DPD event. The
DPDSTSRD register reads back the current state of the CLK_DPDSTATE register. To write to this
register, set desired value in the DPDSTSWR register, this value will be latched in to the
CLK_DPDSTATE register on next DPD event.
Register
Offset
R/W
Description
Reset Value
CLK_DPDSTATE
CLK_BA + 0x0C R/W
Deep Power Down State Register
0x0000_XX00
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DPDSTSRD
DPDSTSWR
1
0
Table 5-34 DPD State Register (CLK_DPDSTATE, address 0x5000_020C) Bit Description.
Bits
Description
DPD State Read Back
DPDSTSRD
[15:8]
Read back of CLK_DPDSTATE register. This register was preserved from last DPD
event .
DPD State Write
DPDSTSWR
[7:0]
To set the CLK_DPDSTATE register, write value to this register. Data is latched on
next DPD event.
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Clock Source Select Control Register 0 （CLK_CLKSEL0）
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL0
CLK_BA + 0x10 R/W
Clock Source Select Control Register 0
0x0000_0038
7
6
5
4
3
2
1
0
Reserved
HIRCFSEL
STCLKSEL
HCLKSEL
Table 5-35 Clock Source Select Register 0 (CLK_CLKSEL0, address 0x5000_0210) Bit Description.
Bits
[6]
Description
OSC48M Frequency Select
Determines which trim setting to use for OSC48M internal oscillator. Oscillator is
factory trimmed within 1% to:
HIRCFSEL
0= 49.152MHz (Default)
1= 32.768MHz
MCU Cortex_M0 SysTick Clock Source Select
These bits are protected, to write to bits first perform the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL))
000 aaa clock source from 16 kHz internal clock
001 aaa clock source from external 32kHz crystal clock
STCLKSEL
[5:3]
010 aaa clock source from 16 kHz internal oscillator divided by 2
011 aaa clock source from OSC49M internal oscillator divided by 2
1xx aaa clock source from HCLK / 2 (Default)
Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR
must be set to 0.
HCLK Clock Source Select
Ensure that related clock sources (pre-select and new-select) are enabled before
updating register.
These bits are protected, to write to bits first perform the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL))
[2:0]
HCLKSEL
000 aaa clock source from internal OSC48M oscillator.
001 aaa clock source from external 32kHz crystal clock
010 aaa clock source from internal 16 kHz oscillator clock
Others aaa reserved
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Clock Source Select Control Register 1（CLK_CLKSEL1）
Clock multiplexors are a glitch free design to ensure smooth transitions between asynchronous clock
sources. As such, both the current clock source and the target clock source must be enabled for
switching to occur. Beware when switching from a low speed clock to a high speed clock that low
speed clock remains on for at least one period before disabling.
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL1
CLK_BA + 0x14 R/W
Clock Source Select Control Register 1
0x3300_771F
31
30
22
14
29
28
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
PWM0CH01CKSEL
Reserved
23
21
20
12
Reserved
15
Reserved
7
13
TMR1SEL
5
Reserved
3
TMR0SEL
1
6
4
0
Reserved
DPWMCKSEL
WDTSEL
Table 5-36 Clock Source Select Register 1 (CLK_CLKSEL1, address 0x5000_0214) Bit Description.
Bits
Description
PWM0 And PWM1 Clock Source Select
PWM0 and PWM1 uses the same clock source, and prescaler
00 = clock source from internal 16 kHz oscillator
PWM0CH01CKSEL
[29:28]
01 = clock source from external 32kHz crystal clock
10 = clock source from HCLK
11 = clock source from internal OSC48M oscillator clock
TIMER1 Clock Source Select
000 aaa clock source from internal 16 kHz oscillator
001 aaa clock source from external 32kHz crystal clock
[14:12]
TMR1SEL
010 aaa clock source from HCLK
011 aaa clock source from external pin (GPIOA[15])
1xx aaa clock source from internal OSC48M oscillator clock
TIMER0 Clock Source Select
000 aaa clock source from internal 16 kHz oscillator
001 aaa clock source from external 32kHz crystal clock
[10:8]
TMR0SEL
010 aaa clock source from HCLK
011 aaa clock source from external pin (GPIOA[14])
1xx aaa clock source from internal OSC48M oscillator clock
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Differential Speaker Driver PWM Clock Source Select
0 = OSC48M clock
[4]
DPWMCKSEL
WDTSEL
1 = 2x OSC48M clock
WDT CLK Clock Source Select
00 = clock source from internal OSC48M oscillator clock
01 = clock source from external 32kHz crystal clock
10 = clock source from HCLK/2048 clock
[1:0]
11 = clock source from internal 16 kHz oscillator clock
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Clock Divider Register (CLK_CLKDIV0)
Register
Offset
R/W
Description
Reset Value
CLK_CLKDIV0
CLK_BA + 0x18 R/W
Clock Divider Number Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
ADCDIV
Reserved
Reserved
UARTDIV
HCLKDIV
1
0
Table 5-37 Clock Divider Register (CLK_CLKDIV0, address 0x5000_0218) Bit Description.
Bits
Description
ADC Clock Divide Number From ADC Clock Source
ADCDIV
[23:16]
The ADC clock frequency aaa (ADC clock source frequency ) / (ADCDIV + 1)
UART Clock Divide Number From UART Clock Source
[11:8]
[3:0]
UARTDIV
HCLKDIV
The UART clock frequency aaa (UART clock source frequency ) / (UARTDIV + 1)
HCLK Clock Divide Number From HCLK Clock Source
The HCLK clock frequency aaa (HCLK clock source frequency) / (HCLKDIV + 1)
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Clock Source Select Control Register 2（CLK_CLKSEL2）
Before changing clock source, ensure that related clock sources (pre-select and new-select) are
enabled.
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL2
CLK_BA + 0x1C R/W
Clock Source Select Control Register 2
0xFFFF_FFFX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
I2S0SEL
Table 5-38 Clock Source Select Control Register 2 (CLK_CLKSEL2, address 0x5000_021C) Bit
Description.
Bits
Description
[31:2]
Reserved
Reserved
I2S Clock Source Select
00 = clock source from internal 16 kHz oscillator
01 = clock source from external 32kHz crystal clock
10 = clock source from HCLK
[1:0]
I2S0SEL
11 = clock source from internal OSC48M oscillator clock
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Sleep Clock Enable Control Register （CLK_SLEEPCTL）
These register bits are used to enable/disable clocks during sleep mode. It works in conjunction with
CLK_AHBCLK and CLK_APBCLK0 clock register to determine whether a clock source remains active
during CPU Sleep mode. For a clock to be active in Sleep mode, the appropriate clock must be
enabled in the CLK_AHBCLK or CLK_APBCLK0 register and the bit must also be enabled in the
CLK_SLEEPCTL register. In other words, to disable a clock in Sleep mode, write ‘0’ to the appropriate
bit in CLK_SLEEPCTL.
Register
Offset
R/W
Description
Reset Value
CLK_SLEEPCTL
CLK_BA + 0x20 R/W
Sleep Clock Source Select Register
0xFFFF_FFFF
Table 5-39 Sleep Clock Enable Control Register (CLK_SLEEPCTL, address 0x5000_0220). Bit
Description.
31
Reserved
23
30
ANACKEN
22
29
I2S0CKEN
21
28
ADCCKEN
20
27
Reserved
19
26
SBRAMCKEN
18
25
Reserved
17
24
Reserved
16
PWM0CH01CKE
N
Reserved
ACMPCKEN
Reserved
CRCCKEN
BFALCKEN
Reserved
UARTCKEN
15
Reserved
7
14
Reserved
6
13
DPWMCKEN
5
12
11
10
Reserved
2
9
8
SPI0CKEN
4
Reserved
3
Reserved
1
I2C0CKEN
0
TMR1CKEN
TMR0CKEN
RTCCKEN
WDTCKEN
Reserved
ISPCKEN
PDMACKEN
HCLKEN
Bits
[30]
Description
ANACKEN
Analog Block Sleep Clock Enable Control
0=Disable
1=Enable
I2S Sleep Clock Enable Control
0=Disable
[29]
[28]
[26]
[22]
I2S0CKEN
1=Enable
Audio Analog-Digital-Converter (ADC) Sleep Clock Enable Control
ADCCKEN
0=Disable
1=Enable
Standby RAM Sleep Clock Enable Control
SBRAMCKEN
ACMPCKEN
0=Disable
1=Enable
Analog Comparator Sleep Clock Enable Control
0=Disable
1=Enable
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PWM Block Sleep Clock Enable Control
[20]
[19]
[18]
[16]
[13]
[12]
[8]
PWM0CH01CKEN
CRCCKEN
0=Disable
1=Enable
Cyclic Redundancy Check Sleep Block Clock Enable Control
0=Disable
1=Enable
Biquad filter/ALC block Sleep Clock Enable Control
BFALCKEN
UARTCKEN
DPWMCKEN
SPI0CKEN
I2C0CKEN
0=Disable
1=Enable
UART0 Sleep Clock Enable Control
0=Disable
1=Enable
Differential PWM Speaker Driver Sleep Clock Enable Control
0=Disable
1=Enable
SPI0 Sleep Clock Enable Control
0=Disable
1=Enable
I2C0 Sleep Clock Enable Control
0=Disable
1=Enable
Timer1 Sleep Clock Enable Control
[7]
TMR1CKEN
TMR0CKEN
RTCCKEN
0=Disable
1=Enable
Timer0 Sleep Clock Enable Control
[6]
0=Disable
1=Enable
Real-Time- Sleep Clock APB Interface Clock Control
[5]
0=Disable
1=Enable
Watchdog Sleep Clock Enable Control
[4]
WDTCKEN
ISPCKEN
0=Disable
1=Enable
Flash ISP Controller Sleep Clock Enable Control
[2]
0=Disable
1=Enable
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PDMA Controller Sleep Clock Enable Control
[1]
[0]
PDMACKEN
HCLKEN
0=Disable
1=Enable
CPU Clock Sleep Enable (HCLK)
Must be left as ‘1’ for normal operation.
0=Disable
1=Enable
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Power State Flag Register (CLK_PWRSTSF)
Register
Offset
R/W
Description
Reset Value
CLK_PWRSTSF
CLK_BA + 0x24 R/W
Power State Flag Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
SPDF
STOPF
DSF
Table 5-40 Power State Flag Register (CLK_PWRSTSF, address 0x5000_0224) Bit Description.
Bits
[2]
Description
Powered Down Flag
SPDF
This flag is set if core logic was powered down to Standby (SPD). Write ‘1’ to clear
flag.
Stop Flag
[1]
[0]
STOPF
This flag is set if core logic was stopped but not powered down. Write ‘1’ to clear flag.
Deep Sleep Flag
DSF
This flag is set if core logic was placed in Deep Sleep mode. Write ‘1’ to clear flag.
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Debug Power Down Register (CLK_DBGPD)
Register
Offset
R/W
Description
Reset Value
CLK_DBGPD
CLK_BA + 0x28 R/W
Debug Port Power Down Disable Register
0x0000_00XX
Table 5-41 Debug Power Down Register (CLK_DBGPD, address 0x5000_0228) Bit Description.
7
6
5
4
3
2
1
0
ICEDATST
ICECLKST
Reserved
DISPDREQ
Bits
Description
ICEDATST
ICE_DAT Pin State
[7]
[6]
Read Only. Current state of ICE_DAT pin.
ICE_CLK Pin State
ICECLKST
DISPDREQ
Read Only. Current state of ICE_CLK pin.
Disable Power Down
[0]
0 = Enable power down requests.
1 = Disable power down requests.
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5.4 General Purpose I/O
5.4.1 Overview and Features
Up to 24 General Purpose I/O pins are available on the ISD9160. These are shared peripheral special
function pins under control of the alternate configuration registers. These 24 pins are arranged in 2
ports named with GPIOA, and GPIOB. GPIOA has sixteen pins and GPIOB has eight. Each one of the
24 pins is independent and has corresponding register bits to control the pin mode function and data.
The I/O type of each GPIO pin can be independently configured as an input, output, open-drain or in a
quasi-bidirectional mode. Upon chip reset, all GPIO pins are configured in quasi-bidirectional mode
and port data register resets high.
When device is in deep power down (DPD) mode, all GPIO pins become high impedance.
GPIO can generate interrupt signals to the core as either level sensitive or edge sensitive inputs. Edge
sensitive inputs can also be de-bounced.
In quasi-bidirectional mode, each GPIO pin has a weak pull-up resistor which is approximately
110K~300K for VDD from 5.0V to 2.4V.
Each pin can generate and interrupt exception to the Cortex M0 core. GPIOB[0] and GPIOB[1] can
generate interrupts to system interrupt number IRQ2 and IRQ3 respectively (see Table 5-15). All
other GPIO generate and exception to interrupt number IRQ4.
5.4.2 GPIO I/O Modes
The I/O mode of each GPIO pin is controlled by the register Px_MODE. (x=A or B). Each pin has two
bits of control giving four possible states:
5.4.2.1 Input Mode
For Px_MODE.MODEn = 00b the GPIOx port [n] pin is in Input Mode. The GPIO pin is in a tri-state
(high impedance) condition without output drive capability. The Px_PIN value reflects the status of the
corresponding port pins.
5.4.2.2 Output Mode
For Px_MODE.MODEn = 01b the GPIOx port [n] pin is in Output Mode. The GPIO pin supports a
digital output function with current source/sink capability. The bit value in the corresponding bit [n] of
Px_DOUT is driven to the pin.
VDD
P
Port Pin[n]
N
DOUT[n]
PIN[n]
Figure 5-6 Output Mode: Push-Pull Output
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5.4.2.3 Open-Drain Mode
For Px_MODE.MODEn = 10b the GPIOx port [n] pin is in Open-Drain mode. The GPIO pin supports a
digital output function but only with sink current capability, an additional pull-up resister is needed for
defining a high state. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, pin is driven low. If
the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin state is defined by the external
load on the pin.
Port Pin
Port Latch
Data
N
Input Data
Figure 5-7 Open-Drain Output
5.4.2.4 Quasi-bidirectional Mode Explanation
For Px_MODE.MODEn = 11b the GPIOx port [n] pin is in Quasi-bidirectional mode and the I/O pin
supports digital output and input function where the source current is only between 30-200uA. Before
input function is performed the corresponding bit in Px_DOUT must be set to 1. The quasi-bidirectional
output is common on the 80C51 and most of its derivatives. If the bit value in the corresponding bit [n]
of Px_DOUT is “0”, the pin will drive a “low” output to the pin. If the bit value in the corresponding bit
[n] of Px_DOUT is “1”, the pin will check the pin value. If pin value is high, no action is taken. If pin
state is low, then pin will drive a strong high for 2 clock cycles. After this the pin has an internal pull-up
resistor connected. Note that the source current capability in quasi-bidirectional mode is approximately
200uA to 30uA for VDD form 5.0V to 2.4V.
VDD
2 CPU
Clock Delay
Very
Weak
P
N
P
P
Strong
Weak
Port Pin
Port Latch
Data
Input Data
Figure 5-8 Quasi-bidirectional GPIO Mode
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5.4.3 GPIO Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
GPIO Base Address:
GPIO_BA = 0x5000_4000
PA_MODE
PA_DINOFF
PA_DOUT
PA_DATMSK
PA_PIN
GPIO_BA+0x000 R/W
GPIO_BA+0x004 R/W
GPIO_BA+0x008 R/W
GPIO_BA+0x00C R/W
GPIO Port A Pin I/O Mode Control
GPIO Port A Pin Digital Input Disable
GPIO Port A Data Output Value
GPIO Port A Data Output Write Mask
GPIO Port A Pin Value
0xFFFF_FFFF
0x0000_0000
0x0000_FFFF
0xXXXX_0000
0x0000_XXXX
0xXXXX_0000
0xXXXX_0000
0x0000_0000
GPIO_BA+0x010
R
PA_DBEN
PA_INTTYPE
PA_INTEN
GPIO_BA+0x014 R/W
GPIO_BA+0x018 R/W
GPIO_BA+0x01C R/W
GPIO Port A De-bounce Enable
GPIO Port A Interrupt Mode Control
GPIO Port A Interrupt Enable
GPIO Port
Indicator
A Interrupt Trigger Source
PA_INTSRC
GPIO_BA+0x020 R/W
0x0000_0000
PB_MODE
PB_DINOFF
PB_DOUT
PB_DATMSK
PB_PIN
GPIO_BA+0x040 R/W
GPIO_BA+0x044 R/W
GPIO_BA+0x048 R/W
GPIO_BA+0x04C R/W
GPIO Port B Pin I/O Mode Control
GPIO Port B Pin Digital Input Disable
GPIO Port B Data Output Value
GPIO Port B Data Output Write Mask
GPIO Port B Pin Value
0xFFFF_FFFF
0x0000_0000
0x0000_XXFF
0xXXXX_0000
0x0000_XXXX
0xXXXX_0000
0xXXXX_0000
0x0000_0000
GPIO_BA+0x050
R
PB_DBEN
PB_INTTYPE
PB_INTEN
GPIO_BA+0x054 R/W
GPIO_BA+0x058 R/W
GPIO_BA+0x05C R/W
GPIO Port B De-bounce Enable
GPIO Port B Interrupt Mode Control
GPIO Port B Interrupt Enable
GPIO Port
Indicator
B Interrupt Trigger Source
PB_INTSRC
GPIO_BA+0x060 R/W
GPIO_BA+0x180 R/W
0x0000_0000
0x0000_0020
GPIO_DBCTL
Interrupt De-bounce Control
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5.4.4
GPIO Control Register Description
GPIO Port [A/B] I/O Mode Control (Px_MODE)
Register
Offset
R/W
Description
Reset Value
0xFFFF_FFFF
0xFFFF_FFFF
PA_MODE
PB_MODE
GPIO_BA+0x000 R/W
GPIO_BA+0x040 R/W
GPIO Port A Pin I/O Mode Control
GPIO Port B Pin I/O Mode Control
Table 5-42 GPIO Mode Control Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
MODE15
MODE11
MODE7
MODE3
MODE14
MODE10
MODE6
MODE2
MODE13
MODE9
MODE5
MODE1
MODE12
16
8
MODE8
MODE4
MODE0
1
0
Bits
Description
GPIOx I/O Pin[n] Mode Control
Determine each I/O type of GPIOx pins.
00 = GPIO port [n] pin is in INPUT mode.
01 = GPIO port [n] pin is in OUTPUT mode.
[2n+1 :2n]
n=0,1..15
MODEn
10 = GPIO port [n] pin is in Open-Drain mode.
11 = GPIO port [n] pin is in Quasi-bidirectional mode.
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GPIO Port [A/B] Input Disable (Px_DINOFF)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
PA_DINOFF
PB_DINOFF
GPIO_BA+0x004 R/W
GPIO_BA+0x044 R/W
GPIO Port A Pin Digital Input Disable
GPIO Port B Pin Digital Input Disable
Table 5-43 GPIO Input Disable Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
DINOFF[31:24]
DINOFF[23:16]
Reserved
1
0
Reserved
Bits
Description
DINOFF
GPIOx Pin[n] OFF Digital Input Path Enable
0 = Enable IO digital input path (Default)
[n]
n=16,17..31
1 = Disable IO digital input path (low leakage mode)
[15:0]
Reserved
Reserved
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GPIO Port [A/B] Data Output Value (Px_DOUT)
Register
Offset
R/W
Description
Reset Value
0x0000_FFFF
0x0000_XXFF
PA_DOUT
PB_DOUT
GPIO_BA+0x008 R/W
GPIO_BA+0x048 R/W
GPIO Port A Data Output Value
GPIO Port B Data Output Value
Table 5-44 GPIO Data Output Register (Px_DOUT)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DOUT[15:8]
DOUT[7:0]
1
0
Bits
Description
DOUT
GPIOx Pin[n] Output Value
Each of these bits controls the status of a GPIO pin when the GPIO pin is configured
as output, open-drain or quasi-bidirectional mode.
[n]
n=0,1..15
0 = GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set.
1 = GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set.
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GPIO Port [A/B] Data Output Write Mask (Px_DATMSK)
Register
Offset
R/W
Description
Reset Value
0xXXXX_0000
0xXXXX_0000
PA_DATMSK
PB_DATMSK
GPIO_BA+0x00C R/W
GPIO_BA+0x04C R/W
GPIO Port A Data Output Write Mask
GPIO Port B Data Output Write Mask
Table 5-45 GPIO Data Output Write Mask Register (Px_DATMSK)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DATMSK[15:8]
DATMSK[7:0]
1
0
Bits
Description
DATMSK
Port [A/B] Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When
set the DATMSK bit[n] to “1”, the corresponding DOUTn bit is write-protected.
[n]
n=0,1..15
0 = The corresponding Px_DOUT[n] bit can be updated
1 = The corresponding Px_DOUT[n] bit is read only
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GPIO Port [A/B] Pin Value (Px_PIN)
Register
PA_PIN
PB_PIN
Offset
R/W
R
Description
Reset Value
0x0000_XXXX
0x0000_XXXX
GPIO_BA+0x010
GPIO_BA+0x050
GPIO Port A Pin Value
GPIO Port B Pin Value
R
Table 5-46 GPIO PIN Value Register (Px_PIN)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
PIN[15:8]
PIN[7:0]
1
0
Bits
Description
PIN
Port [A/B] Pin Values
[n]
The value read from each of these bit reflects the actual status of the respective GPIO
pin
n=0,1..15
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GPIO Port [A/B] De-bounce Enable (Px_DBEN)
Register
Offset
R/W
Description
Reset Value
0xXXXX_0000
0xXXXX_0000
PA_DBEN
PB_DBEN
GPIO_BA+0x014 R/W
GPIO_BA+0x054 R/W
GPIO Port A De-bounce Enable
GPIO Port B De-bounce Enable
Table 5-47 GPIO Debounce Enable Register (Px_DBEN)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DBEN[15:8]
DBEN[7:0]
1
0
Bits
Description
Port [A/B] Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. For an
edge triggered interrupt to be generated, input signal must be valid for two
consecutive de-bounce periods. The de-bounce time is controlled by the
GPIO_DBCTL register.
[n]
DBEN
n=0,1..15
The DBEN[n] is used for “edge-trigger” interrupt only; it is ignored for “level trigger”
interrupt
0 = The bit[n] de-bounce function is disabled
1 = The bit[n] de-bounce function is enabled
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GPIO Port [A/B] Interrupt Mode Control (Px_INTTYPE)
Register
Offset
R/W
Description
Reset Value
0xXXXX_0000
0xXXXX_0000
PA_INTTYPE
PB_INTTYPE
GPIO_BA+0x018 R/W
GPIO_BA+0x058 R/W
GPIO Port A Interrupt Mode Control
GPIO Port B Interrupt Mode Control
Table 5-48 GPIO Interrupt Mode Control (Px_INTTYPE)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
TYPE[15:8]
TYPE[7:0]
1
0
Bits
Description
Port [A/B] Edge Or Level Detection Interrupt Control
TYPE[n] used to control whether the interrupt mode is level triggered or edge
triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the
DBEN register. If the interrupt mode is level triggered, the input source is sampled
each clock to generate an interrupt.
[n]
TYPE
n=0,1..15
0 = Edge triggered interrupt
1 = Level triggered interrupt
If level triggered interrupt is selected, then only one level can be selected in the
Px_INTEN register. If both levels are set no interrupt will occur.
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GPIO Port [A/B] Interrupt Enable Control (Px_INTEN)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
PA_INTEN
PB_INTEN
GPIO_BA+0x01C R/W
GPIO_BA+0x05C R/W
GPIO Port A Interrupt Enable
GPIO Port B Interrupt Enable
Table 5-49 GPIO Interrupt Enable Control Register (Px_INTEN)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RHIEN[15:8]
RHIEN[7:0]
FLIEN[15:8]
FLIEN[7:0]
1
0
Bits
Description
Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High
RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding
GPIO pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level “high” will generate an
interrupt.
[n+16]
RHIEN
If the interrupt is configured in edge trigger mode, a state change from “low-to-high”
will generate an interrupt.
n=0,1..15
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO
trigger a single interrupt vector IRQ4.
0 = Disable GPIOx[n] for level-high or low-to-high interrupt.
1 = Enable GPIOx[n] for level-high or low-to-high interrupt
Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low
FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO
pins. It also enables the pin wakeup function.
If the interrupt is configured in level trigger mode, a level “low” will generate an
interrupt.
[n]
FLIEN
If the interrupt is configured in edge trigger mode, a state change from “high-to-low”
will generate an interrupt.
n=0,1..15
GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO
trigger a single interrupt vector IRQ4.
0 = Disable GPIOx[n] for low-level or high-to-low interrupt
1 = Enable GPIOx[n] for low-level or high-to-low interrupt
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GPIO Port [A/B] Interrupt Trigger Source (Px_INTSRC)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
PA_INTSRC
PB_INTSRC
GPIO_BA+0x020 R/W
GPIO_BA+0x060 R/W
GPIO Port A Interrupt Trigger Source Indicator
GPIO Port B Interrupt Trigger Source Indicator
Table 5-50 GPIO Interrupt Trigger Source Register (Px_INTSRC)
15
7
14
6
13
12
11
10
9
1
8
0
INTSRC[15:8]
INTSRC[7:0]
5
4
3
2
Bits
Description
INTSRC
Port [A/B] Interrupt Trigger Source Indicator
Read :
1 aaa Indicates GPIOx[n] generated an interrupt
0 aaa No interrupt from GPIOx[n]
Write :
[n]
n=0,1..15
1 aaa Clear the corresponding pending interrupt.
0 aaa No action
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Interrupt De-bounce Control (GPIO_DBCTL )
Register
Offset
R/W
Description
Reset Value
GPIO_DBCTL
GPIO_BA+0x180 R/W
Interrupt De-bounce Control
0x0000_0020
Table 5-51 GPIO Interrupt De-bounce Control Register (GPIO_DBCTL )
7
6
5
4
3
2
1
0
Reserved
ICLKON
DBCLKSRC
DBCLKSEL
Bits
[5]
Description
ICLKON
Interrupt Clock On Mode
Set this bit “0” will gate the clock to the interrupt generation circuit if the GPIOx[n]
interrupt is disabled.
0 = disable the clock if the GPIOx[n] interrupt is disabled
1 = Interrupt generation clock always active.
De-bounce Counter Clock Source Select
[4]
DBCLKSRC
DBCLKSEL
0 = De-bounce counter clock source is HCLK
1 = De-bounce counter clock source is the internal 16 kHz clock
De-bounce Sampling Cycle Selection.
For edge level interrupt GPIO state is sampled every 2^(DBCLKSEL) de-bounce
clocks. For example if DBCLKSRC aaa 6, then interrupt is sampled every 2^6 aaa 64
de-bounce clocks. If DBCLKSRC is 16KHz oscillator this would be a 64ms de-bounce.
[3:0]
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5.5 Brownout Detection and Temperature Alarm
The ISD9160 is equipped with a Brown-Out voltage detector and Over Temperature Alarm. The
Brown-Out detector features a configurable trigger level and can be configured by flash to be active
upon reset. The Brown-Out detector also has a power saving mode where detection can be set up to
be active for a configurable on and off time.
TALARM and BOD operation require that the OSC16K low power oscillator is enabled
( CLK_PWRCTL.LIRCDPDEN = 0).
The over temperature alarm is designed to protect the chip from dangerously high internal
temperatures, generally associated with excessive load (or short circuit) on the speaker driver. The
temperature alarm can generate an interrupt to which the CPU can respond and shut down the
speaker driver. It is recommended that users implement this function due to the drive strength of the
speaker driver has the capability of damaging the chip.
5.5.1 Brownout and Temperature Alarm Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
BOD Base Address:
BODTALM_BA = 0x4008_4000
BODTALM_BODSEL
BODTALM_BODCTL
BODTALM_TALMSEL
BODTALM_TALMCTL
BODTALM_BODDTMR
BODTALM_BA+0x00 R/W Brown Out Detector Select Register
BODTALM_BA+0x04 R/W Brown Out Detector Enable Register
BODTALM_BA+0x08 R/W Temperature Alarm Select Register
BODTALM_BA+0x0C R/W Temperature Alarm Enable Register
BODTALM_BA+0x10 R/W Brown Out Detector Timer Register
0x0000_0000
0x0000_00XX
0x0000_0000
0x0000_00XX
0x0003_03E3
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Brown-Out Detector Select Register (BODTALM_BODSEL)
Offset R/W Description
Register
Reset Value
BODTALM_BODSEL
BODTALM_BA+0x00 R/W Brown Out Detector Select Register
0x0000_0000
Table 5-52 Brownout Detector Select Register (BODTALM_BODSEL, address 0x4008_4000)
7
6
5
4
3
2
1
0
Reserved
BODHYS
BODVL
Bits
Description
[31:4]
Reserved
Reserved
BOD Hysteresis
[3]
BODHYS
0= Hysteresis Disabled.
1= Enable Hysteresis of BOD detection.
BOD Voltage Level
111b aaa
110b aaa
101b aaa
100b aaa
011b aaa
010b aaa
001b aaa
000b aaa
4.6V
3.0V
2.8V
2.625V
2.5V
2.4V
2.2V
2.1V
[2:0]
BODVL
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Brown-Out Detector Enable Register (BODTALM_BODCTL)
This register is initialized by user flash configuration bit config0[23] (see Section 6.7). If config0[23]=1,
then reset value of BODEN is 0x7. The effect of this is to generate a NMI interrupt (default NMI
interrupt is BOD interrupt) if BOD circuit detects a voltage below 2.1V. The NMI ISR can be defined by
the user to respond to this low voltage level.
Register
Offset
R/W Description
Reset Value
BODTALM_BODCTL
BODTALM_BA+0x04 R/W Brown Out Detector Enable Register
0x0000_00XX
Table 5-53 Detector Enable Register (BODTALM_BODCTL, address 0x4008_4004)
7
6
5
4
3
2
1
0
Reserved
BODOUT
BODIF
BODINTEN
BODEN
Bits
Description
[31:5]
Reserved
Reserved
Output of BOD Detection Block
[4]
[3]
BODOUT
BODIF
This signal can be monitored to determine the current state of the BOD comparator.
Read ‘1’ implies that VCC is less than BODVL.
Current Status Of Interrupt
Latched whenever a BOD event occurs and BODINTEN aaa 1. Write ‘1’ to clear.
BOD Interrupt Enable
0= Disable BOD Interrupt.
1= Enable BOD Interrupt.
[2]
BODINTEN
BODEN
BOD Enable
1xb aaa Enable continuous BOD detection.
[1:0]
01b aaa Enable time multiplexed BOD detection. See BODTALM_BODDTMR
register.
00b aaa Disable BOD Detection.
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Detection Time Multiplex Register (BODTALM_BODDTMR)
The BOD detector can be set up to take periodic samples of the supply voltage to minimize power
consumption. The circuit can be configured and used in Standby Power Down (SPD) mode and can
wake up the device if a BOD is event detected. The detection timer uses the OSC16K oscillator as
time base so this oscillator must be active for timer operation. When active the BOD circuit requires
~165uA.
With
default
timer
settings,
average
current
reduces
to
500nA
165uA*DURTON/(DURTON+DURTOFF).
Register
Offset
R/W Description
Reset Value
BODTALM_BODDTMR
BODTALM_BA+0x10 R/W Brown Out Detector Timer Register
0x0003_03E3
Table 5-54 Detection Time Multiplex Register (BODTALM_BODDTMR, address 0x4008_4010)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
DURTON[3:0]
DURTOFF[15:8]
4
3
1
0
DURTOFF[7:0]
Bits
Description
[31:20]
[19:16]
Reserved
Reserved
Time BOD Detector Is Active
DURTON
(DURTON+1) * 100us. Minimum value is 1. (default is 400us)
Time BOD Detector Is Off
[15:0]
DURTOFF
(DURTOFF+1)*100us . Minimum value is 7. (default is 99.6ms)
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Temperature Alarm Select Register (BODTALM_TALMSEL)
Offset R/W Description
Register
Reset Value
BODTALM_TALMSEL
BODTALM_BA+0x08 R/W Temperature Alarm Select Register
0x0000_0000
Table 5-55 Temperature Alarm Select Register (BODTALM_TALMSEL, address 0x4008_4008)
7
6
5
4
3
2
1
0
Reserved
TALMVL
Bits
Description
[31:4]
Reserved
Reserved
Temperature Alarm Sense Level
0000:105C
0001:115C
[3:0]
TALMVL
0010:125C
0100:135C
1000:145C
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Temperature Alarm Enable Register (BODTALM_TALMCTL)
Offset R/W Description
Register
Reset Value
BODTALM_TALMCTL
BODTALM_BA+0x0C R/W
0x0000_00XX
Temperature Alarm Enable Register
Table 5-56 Temperature Alarm Enable Register (BODTALM_TALMCTL, address 0x4008_400C)
7
6
5
4
3
2
1
0
Reserved
TALMIF
TALMIEN
TALMOUT
TALMEN
Bits
Description
[31:4]
Reserved
Reserved
Current status of interrupt
[3]
[2]
[1]
[0]
TALMIF
Latched whenever a Temperature Sense event occurs and IE aaa 1. Write ‘1’ to clear.
TALARM Interrupt Enable
0 = Disable TALARM Interrupt
1 = Enable TALARM Interrupt
TALMIEN
TALMOUT
TALMEN
Output of TALARM Block
Can be polled to determine whether TALARM active (be 1).
TALARM Enable
0 = Disable TALARM Detection
1 = Enable TALARM Detection
5.6 I2C Serial Interface Controller (Master/Slave)
5.6.1 Introduction
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision detection
and arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously. Serial, 8-bit oriented, bi-directional data transfers can be made up 1.0 Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-
by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the
MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled
during the high period of SCL; therefore, the SDA line may be changed only during the low period of
SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is
high is interpreted as a command (START or STOP). Please refer to Figure 5-9 for more detail I2C
BUS Timing.
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Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 5-9 I2C Bus Timing
The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1 in
I2C_CTL should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: I2C_SDA (which can
be configured as GPIOA[10], GPIOB[3] or GPIOA[3], serial data line) and I2C_SCL (which can be
configured as GPIOA[11], GPIOB[2] or GPIOA[1], serial clock line). See Error! Reference source not
found. and Error! Reference source not found. for alternate GPIO pin functions. Pull up resistor is
needed for these pins for I2C operation as these are open drain pins.
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the bus are:
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on the
bus
Serial clock synchronization allows devices with different bit rates to communicate via one serial
bus
Serial clock synchronization can be used as a handshake mechanism to suspend and resume
serial transfer
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up and timer-
out counter overflows.
External pull-up are needed for high output
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
I2C-bus controllers support multiple address recognition ( Four slave address with mask option)
5.6.1.1 I2C Protocol
Normally, a standard communication consists of four parts:
1) START or Repeated START signal generation
2) Slave address transfer
3) Data transfer
4) STOP signal generation
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SCL
SDA
1
2
7
8
9
1
2
3 - 7
8
9
P
NACK
ACK
A6
A5
A4 - A1
A0
R/W
ACK
D7
D6
D5 - D1
D0
Sr
S
or
Sr
P
or
Sr
MSB
LSB
MSB
LSB
Figure 5-10 I2C Protocol
5.6.1.2 Data transfer on the I2C-bus
A master-transmitter always begins by addressing a slave receiver with a 7-bit address. For a
transaction where the master-transmitter is sending data to the slave, the transfer direction is not
changed, master is always transmitting and slave acknowledges the data, see Figure 5-11.
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
data transfer
(n bytes + acknowledge)
'0'(write)
from master to slave
from slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
P = STOP condition
Figure 5-11 Master Transmits Data to Slave
For a master to read data from a slave, master addresses slave with the R/W bit set to ‘1’, immediately
after the first byte (address) is acknowledged by the slave the transfer direction is changed and slave
sends data to the master and master acknowledges the data transfer.
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A
P
data transfer
(n bytes + acknowledge)
'1'(read)
Figure 5-12 Master Reads Data from Slave
5.6.1.3 START or Repeated START signal
When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA lines
are high), a master can initiate a transfer by sending a START signal. A START signal, usually
referred to as the S-bit, is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH.
The START signal denotes the beginning of a new data transfer.
A Repeated START (Sr) is a START signal without first generating a STOP signal. The master uses
this method to communicate with another slave or the same slave in a different transfer direction (e.g.
from writing to a device to reading from a device) without releasing the bus.
STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal, usually
referred to as the P-bit, is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH.
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SCL
SDA
START condition
STOP condition
Figure 5-13 START and STOP condition
5.6.1.4 Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the slave
address. This is a 7-bits calling address followed by a RW bit. The RW bit signals the slave the data
transfer direction. No two slaves in the system can have the same address. Only the slave with an
address that matches the one transmitted by the master will respond by returning an acknowledge bit
by pulling the SDA low at the 9th SCL clock cycle.
5.6.1.5 Data Transfer
Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-
byte basis in the direction specified by the RW bit sent by the master. Each transferred byte is
followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a Not Acknowledge
(NACK), the master can generate a STOP signal to abort the data transfer or generate a Repeated
START signal and start a new transfer cycle.
If the master, as the receiving device, does Not Acknowledge (NACK) the slave, the slave releases
the SDA line for the master to generate a STOP or Repeated START signal.
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 5-14 Bit Transfer on the I2C bus
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clock pulse for
acknowledgement
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT BY
TRANSMITTER
not acknowledge
DATA OUTPUT BY
RECEIVER
S
acknowledge
START
condition
Figure 5-15 Acknowledge on the I2C bus
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5.6.2 I2C Protocol Registers
The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL
(control register), I2C_STATUS (status register), I2C_DAT (data register), ADDRn (address registers,
n=0~3), ADRMn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register) and I2C_TOCTL
(Time-out counter register). Bits 31~ bit 8 of these I2C special function registers are reserved. These
bits do not have any functions and are all zero if read back.
When I2C port is enabled by setting I2CEN ( I2C_CTL[6]) to high, the internal states will be controlled
by I2C_CTL and I2C logic hardware. Once a new status code is generated and stored in
I2C_STATUS, the I2C Interrupt Flag bit SI ( I2C_CTL[3]) will be set automatically. If the Enable
Interrupt bit EI ( I2C_CTL[7]) is set high at this time, the I2C interrupt will be generated. The bit field
I2C_STATUS[7:3] stores the internal state code, the lowest 3 bits of I2C_STATUS are always zero
and the contents are stable until SI is cleared by software. The base address of the I2C peripheral on
the ISD9160 is 0x4002_0000.
5.6.2.1 Address Registers ( ADDR)
I2C port is equipped with four slave address registers ADDRn (n=0~3). The contents of the register
are irrelevant when I2C is in master mode. In the slave mode, the bit field ADDRn[7:1] must be loaded
with the MCU’s own slave address. The I2C hardware will react if the contents of ADDR are matched
with the received slave address.
The I2C ports support the “General Call” function. If the GC bit ( ADDRn[0]) is set the I2C port
hardware will respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H after
Master send general call address to I2C bus, then it will follow status of GC mode. If it is in master
mode, the AA bit ( I2C_CTL[2], Assert Acknowledge control bit) must be cleared when it will send
general call address of 00H to I2C bus.
I2C-bus controllers support multiple address recognition with four address mask registers I2ADRMn
(n=0~3). When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to zero, that means the received corresponding register bit
should be exact the same as address register.
5.6.2.2 Data Register ( I2C_DAT)
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit ( I2C_DAT[7:0]) directly addressable SFR while it is not in
the process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag
(SI) is set. Data in I2C_DAT[7:0] remains stable as long as SI bit is set. While data is being shifted
out, data on the bus is simultaneously being shifted in; I2C_DAT[7:0] always contains the last data
byte present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to
slave receiver is made with the correct data in I2C_DAT[7:0].
I2C_DAT[7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by
the SIO hardware and cannot be accessed by the CPU. Serial data is shifted through the
acknowledge bit into I2C_DAT[7:0] on the rising edges of serial clock pulses on the SCL line. When a
byte has been shifted into I2C_DAT[7:0], the serial data is available in I2C_DAT[7:0], and the
acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse. Serial
data is shifted out from I2C_DAT[7:0] on the falling edges of SCL clock pulses, and is shifted into
I2C_DAT[7:0] on the rising edges of SCL clock pulses.
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I2C Data Register:
DATA.7 DATA.6 DATA.5 DATA.4 DATA.3 DATA.2 DATA.1 DATA.0
shifting direction
Figure 5-16 I2C Data Shift Direction
5.6.2.3 Control Register ( I2C_CTL)
The CPU can read from and write to this 8-bit field of I2C_CTL[7:0]. Two bits are affected by
hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is
cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS1 = "0".
INTEN
I2CEN
STA
Enable Interrupt.
Set to enable I2C serial function block. When ENS=1 the I2C serial function is enabled.
I2C START Control Bit. Setting STA to logic 1 enters master mode, the I2C hardware
sends a START or repeat START condition to bus when the bus is free.
STO
2C STOP Control Bit. In master mode, setting STO transmits a STOP condition to the
bus. The I2C hardware will check the bus condition and if a STOP condition is detected
this flag will be cleared by hardware. In a slave mode, setting STO resets I2C hardware to
the defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
SI
I2C Interrupt Flag. When a new SIO state is present in the I2C_STATUS register, the SI
flag is set by hardware, and if bit INTEN ( I2C_CTL[7]) is set, the I2C interrupt is
requested. SI must be cleared by software. Clear SI is by writing one to this bit.
AA
Assert Acknowledge Control Bit. When AA=1 prior to address or data received, an
acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on
the SCL line when:
1.) A slave is acknowledging the address sent from master,
2.) A receiver device is acknowledging the data sent by a transmitter.
When AA=0 prior to address or data received, a Not acknowledged (high level to SDA)
will be returned during the acknowledge clock pulse on the SCL line.
5.6.2.4 Status Register ( I2C_STATUS)
I2C_STATUS[7:0] is an 8-bit read-only register. The three least significant bits are always 0. The bit
field I2C_STATUS[7:3] contains the status code. There are 26 possible status codes. When
I2C_STATUS[7:0] contains F8H, no serial interrupt is requested. All other I2C_STATUS[7:3] values
correspond to defined SIO states. When each of these states is entered, a status interrupt is
requested (SI = 1). A valid status code is present in I2C_STATUS[7:3] one machine cycle after SI is
set by hardware and is still present one machine cycle after SI has been reset by software.
In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is
present at an illegal position in the format frame. Examples of illegal positions are during the serial
transfer of an address byte, a data byte or an acknowledge bit. To recover I2C from bus error, STO
should be set and SI should be clear to enter not addressed slave mode. Then clear STO to release
bus and to wait new communication. I2C bus cannot recognize stop condition during this action when
bus error occurs.
5.6.2.5 I2C Clock Baud Rate Bits ( I2C_CLKDIV)
The data baud rate of I2C is determined by I2C_CLKDIV[7:0] register when SIO is in a master mode.
It is not important when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize
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with any clock frequency up to 400 kHz from master I2C device.
Data Baud Rate of I2C = PCLK /(4x( I2C_CLKDIV[7:0]+1)). If PCLK=16MHz, the I2C_CLKDIV[7:0] =
40 (28H), data baud rate of I2C = 16MHz/(4x(40 +1)) = 97.5Kbits/sec.
5.6.2.6 The I2C Time-out Counter Register ( I2C_TOCTL)
There is a 14-bit time-out counter which can be configured to deal with an I2C bus hang-up. If the
time-out counter is enabled, the counter starts up-counting until it overflows (TIF=1) and generates I2C
interrupt to CPU or stops counting by clearing ENTI to 0. When time-out counter is enabled, setting
flag SI to high will reset counter. Counter will re-start after SI is cleared. If the I2C bus hangs up,
counter will overflow and generate a CPU interrupt. Refer to Figure 5-17 for the 14-bit time-out
counter. User can clear TIF by writing one to this bit.
Pclk
0
1
Enabl
e
14-bit Counter
TIF
To I2C Interrupt
1/4
Clear Counter
DIV4
SI
ENS1
ENTI
SI
Figure 5-17: I2C Time-out Count Block Diagram
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5.6.3 Register Mapping
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
I2C Base Address:
I2C_BA = 0x4002_0000
I2C_CTL
I2C_BA+0x00
I2C_BA+0x04
I2C_BA+0x08
I2C_BA+0x0C
I2C_BA+0x10
I2C_BA+0x14
I2C_BA+0x18
I2C_BA+0x1C
I2C_BA+0x20
I2C_BA+0x24
I2C_BA+0x28
I2C_BA+0x2C
I2C_BA+0x30
R/W
R/W
R/W
R
I2C Control Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
I2C_ADDR0
I2C_DAT
I2C Slave address Register0
I2C DATA Register
I2C_STATUS
I2C_CLKDIV
I2C_TOCTL
I2C Status Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I2C clock divided Register
I2C Time out control Register
I2C Slave address Register1
I2C Slave address Register2
I2C Slave address Register3
I2C Slave address Mask Register0
I2C Slave address Mask Register1
I2C Slave address Mask Register2
I2C Slave address Mask Register3
I2C_ADDR1
I2C_ADDR2
I2C_ADDR3
I2C_ADDRMSK0
I2C_ADDRMSK1
I2C_ADDRMSK2
I2C_ADDRMSK3
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5.6.4
Register Description
I2C CONTROL REGISTER ( I2C_CTL)
Register
I2C_CTL
Offset
R/W
Description
Reset Value
I2C_BA+0x00
R/W
I2C Control Register
0x0000_0000
7
6
5
4
3
2
1
0
INTEN
I2CEN
STA
STO
SI
AA
Reserved
Reserved
Bits
[7]
Description
INTEN
Enable Interrupt
0 = Disable interrupt.
1 = Enable interrupt CPU.
I2C Controller Enable Bit
0 = Disable
[6]
[5]
I2CEN
STA
1 = Enable
Set to enable I2C serial function block.
I2C START Control Bit
Setting STA to logic 1 will enter master mode, the I2C hardware sends a START or
repeat START condition to bus when the bus is free.
I2C STOP Control Bit
In master mode, set STO to transmit a STOP condition to bus. I2C hardware will
check the bus condition, when a STOP condition is detected this bit will be cleared by
hardware automatically. In slave mode, setting STO resets I2C hardware to the
defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode able receive data from the master transmit device.
[4]
[3]
STO
I2C Interrupt Flag
When a new SIO state is present in the I2C_STATUS register, the SI flag is set by
hardware, and if bit EI ( I2C_CTL[7]) is set, the I2C interrupt is requested. SI must be
cleared by software. Clear SI is by writing one to this bit.
SI
Assert Acknowledge Control Bit
When AA=1 prior to address or data received, an acknowledge (ACK - low level to
SDA) will be returned during the acknowledge clock pulse on the SCL line when:
[2]
AA
1. A slave is acknowledging the address sent from master,
2. The receiver devices are acknowledging the data sent by transmitter.
When AA aaa 0 prior to address or data received, a Not acknowledged (high level to
SDA) will be returned during the acknowledge clock pulse on the SCL line.
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I2C DATA REGISTER ( I2C_DAT)
Register
I2C_DAT
Offset
R/W
Description
Reset Value
I2C_BA+0x08
R/W
I2C DATA Register
0x0000_0000
7
6
5
4
3
2
1
0
DAT [7:0]
Bits
Description
DAT
I2C Data Register
During master or slave transmit mode, data to be transmitted is written to this register.
During master or slave receive mode, data that has been received may be read from
this register.
[7:0]
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I2C STATUS REGISTER ( I2C_STATUS )
Register
Offset
R/W
Description
Reset Value
I2C_STATUS
I2C_BA+0x0C
R
I2C Status Register
0x0000_0000
7
6
5
4
3
2
1
0
STATUS[7:0]
Bits
Description
I2C Status Register
The status register of I2C:
The three least significant bits are always 0. The five most significant bits contain the
status code. There are 26 possible status codes. When STATUS contains F8H, no
serial interrupt is requested. All other STATUS values correspond to defined I2C
states. When each of these states is entered, a status interrupt is requested (SI aaa
1). A valid status code is present in STATUS one PCLK cycle after SI is set by
hardware and is still present one PCLK cycle after SI has been reset by software. In
addition, states 00H stands for a Bus Error. A Bus Error occurs when a START or
STOP condition is present at an illegal position in the frame. Example of illegal
position are during the serial transfer of an address byte, a data byte or an
acknowledge bit.
[7:0]
STATUS
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I2C BAUD RATE CONTROL REGISTER ( I2C_CLKDIV)
Register
Offset
R/W
Description
Reset Value
I2C_CLKDIV
I2C_BA+0x10
R/W
I2C clock divided Register
0x0000_0000
7
6
5
4
3
2
1
0
DIVIDER[7:0]
Bits
Description
DIVIDER
I2C Clock Divided Register
The I2C clock rate bits: Data Baud Rate of I2C aaa PCLK /(4x( CLK+1)).
[7:0]
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I2C TIME-OUT COUNTER REGISTER ( I2C_TOCTL)
Register
Offset
R/W
Description
Reset Value
I2C_TOCTL
I2C_BA+0x14
R/W
I2C Time out control Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
TOCEN
TOCDIV4
TOIF
Bits
[2]
Description
TOCEN
Time-out Counter Control Bit
0 = Disable
1 = Enable
When enabled, the 14 bit time-out counter will start counting when SI is clear. Setting
flag SI to high will reset counter and re-start up counting after SI is cleared.
Time-Out Counter Input Clock Divide By 4
0 = Disable
[1]
[0]
TOCDIV4
TOIF
1 = Enable
When enabled, the time-out clock is PCLK/4.
Time-Out Flag
0 = No time-out.
1 = Time-out flag is set by H/W. It can interrupt CPU. Write 1 to clear..
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I2C SLAVE ADDRESS REGISTER (I2C_ADDRx)
Register
Offset
R/W
R/W
R/W
R/W
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
I2C_ADDR0
I2C_ADDR1
I2C_ADDR2
I2C_ADDR3
I2C_BA+0x04
I2C_BA+0x18
I2C_BA+0x1C
I2C_BA+0x20
I2C Slave address Register0
I2C Slave address Register1
I2C Slave address Register2
I2C Slave address Register3
7
6
5
4
3
2
1
0
ADDR[7:1]
GC
Bits
Description
ADDR
I2C Address Register
The content of this register is irrelevant when I2C is in master mode. In the slave
mode, the seven most significant bits must be loaded with the MCU’s own address.
The I2C hardware will react if any of the addresses are matched.
[7:1]
General Call Function
[0]
GC
0 = Disable General Call Function.
1 = Enable General Call Function.
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I2C SLAVE ADDRESS MASK REGISTER (I2C_ADDRMSKx)
Register
Offset
R/W
R/W
R/W
R/W
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
I2C_ADDRMSK0
I2C_ADDRMSK1
I2C_ADDRMSK2
I2C_ADDRMSK3
I2C_BA+0x24
I2C_BA+0x28
I2C_BA+0x2C
I2C_BA+0x30
I2C Slave address Mask Register0
I2C Slave address Mask Register1
I2C Slave address Mask Register2
I2C Slave address Mask Register3
7
6
5
4
3
2
1
0
ADDRMSKx[7:1]
Reserved
Bits
Description
ADDRMSK
I2C Address Mask register
0 = Mask disable.
[n]
1 = Mask enable (the received corresponding address bit is don’t care.)
n=1,2..7
I2C bus controllers support multiple-address recognition with four address mask
registers. Bits in this field mask the I2C_ADDRx registers masking bits from the
address comparison.
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5.6.5 Modes of Operation
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC call.
In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C port
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, and if the slave is willing to receive or transmit data from/to master (by setting the AA bit), an
acknowledge pulse will be transmitted out on the 9th clock. An interrupt is requested on both master
and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus master,
the hardware waits until the bus is free before the master mode is entered so that a possible slave
action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the slave
mode immediately and can detect its own slave address in the same serial transfer.
5.6.5.1 Master Transmitter Mode
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains
the slave address of the receiving device (7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic 0, and it is represented by “W” in the flow diagrams. Thus the first byte
transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an
acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
5.6.5.2 Master Receiver Mode
In this case the data direction bit (R/W) will be logic 1, and it is represented by “R” in the flow
diagrams. Thus the first byte transmitted is SLA+R. Serial data is received via SDA while SCL outputs
the serial clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit
is transmitted. START and STOP conditions are output to indicate the beginning and end of a serial
transfer.
5.6.5.3 Slave Receiver Mode
Serial data and the serial clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
5.6.5.4 Slave Transmitter Mode
The first byte is received and handled as in the slave receiver mode. However, in this mode, the
direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while
the serial clock is input through SCL. START and STOP conditions are recognized as the beginning
and end of a serial transfer.
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5.6.6 Data Transfer Flow in Five Operating Modes
The five operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter,
Slave/Receiver and GC Call. Bits STA, STO and AA in I2C_CTL register will determine the next state
of the SIO hardware after SI flag is cleared. Upon completion of the new action, a new status code will
be updated and the SI flag will be set. If the I2C interrupt control bit INTEN ( I2C_CTL[7]) is set,
appropriate action or software branch of the new status code can be performed in the Interrupt service
routine.
Data transfers in each mode are shown in the following figures.
*** Legend for the following five figures:
Software's access to I2DAT with respect to "Expected next action":
(1) Data byte will be transmitted:
08H
Last state
Last action is done
A START has been
transmitted.
Software should load the data byte (to be transmitted)
into I2DAT before new I2CON setting is done.
(2) SLA+W (R) will be transmitted:
Software should load the SLA+W/R (to be transmitted)
into I2DAT before new I2CON setting is done.
(3) Data byte will be received:
(STA,STO,SI,AA)=(0,0,0,X)
SLA+W will be transmitted;
ACK bit will be received.
Next setting in I2CON
Expected next action
Software can read the received data byte from I2DAT
while a new state is entered.
New state
next action is done
18H
SLA+W has been transmitted;
ACK has been received.
Figure 5-18 Legend for the following four figures
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Set STA to generate
a START.
From Slave Mode (C)
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,1,X)
SLA+W will be transmitted;
ACK bit will be received.
From Master/Receiver (B)
18H
SLA+W will be transmitted;
ACK bit will be received.
or
20H
SLA+W will be transmitted;
NOT ACK bit will be received.
(STA,STO,SI,AA)=(0,0,1,X)
Data byte will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,1,1,X)
A STOP will be transmitted;
STO flag will be reset.
(STA,STO,SI,AA)=(1,0,1,X)
A repeated START will be transmitted;
(STA,STO,SI,AA)=(1,1,1,X)
A STOP followed by a START will
be transmitted;
STO flag will be reset.
10H
28H
Send a STOP
A repeated START has
been transmitted.
Data byte in S1DAT has been transmitted;
ACK has been received.
Send a STOP
followed by a START
or
30H
Data byte in S1DAT has been transmitted;
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,1,X)
SLA+R will be transmitted;
ACK bit will be transmitted;
SIO1 will be switched to MST/REC mode.
38H
Arbitration lost in SLA+R/W or
Data byte.
To Master/Receiver (A)
(STA,STO,SI,AA)=(0,0,1,X)
I2C bus will be release;
Not address SLV mode will be entered.
(STA,STO,SI,AA)=(1,0,1,X)
A START will be transmitted when the
bus becomes free.
Enter NAslave
Send a START
when bus becomes free
Figure 5-19 Master Transmitter Mode
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Set STA to generate
a START.
From Slave Mode (C)
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,1,X)
SLA+R will be transmitted;
ACK bit will be received.
From Master/Transmitter (A)
48H
40H
SLA+R has been transmitted;
NOT ACK has been received.
SLA+R has been transmitted;
ACK has been received.
(STA,STO,SI,AA)=(0,0,1,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,1,1)
Data byte will be received;
ACK will be returned.
58H
50H
Data byte has been received;
NOT ACK has been returned.
Data byte has been received;
ACK has been returned.
(STA,STO,SI,AA)=(0,1,1,X)
A STOP will be transmitted;
STO flag will be reset.
(STA,STO,SI,AA)=(1,1,1,X)
A STOP followed by a START will
be transmitted;
(STA,STO,SI,AA)=(1,0,1,X)
A repeated START will be transmitted;
STO flag will be reset.
10H
Send a STOP
A repeated START has
been transmitted.
Send a STOP
followed by a START
38H
(STA,STO,SI,AA)=(0,0,1,X)
SLA+R will be transmitted;
ACK bit will be transmitted;
Arbitration lost in NOT ACK
bit.
SIO1 will be switched to MST/REC mode.
To Master/Transmitter (B)
(STA,STO,SI,AA)=(1,0,1,X)
A START will be transmitted;
when the bus becomes free
(STA,STO,SI,AA)=(0,0,1,X)
I2C bus will be release;
Not address SLV mode will be entered.
Send a START
Enter NAslave
when bus becomes free
Figure 5-20 Master Receiver Mode
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Set AA
A8H
Own SLA+R has been received;
ACK has been return.
or
B0H
Arbitration lost SLA+R/W as master;
Own SLA+R has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,1,0)
Last data byte will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,0,1,1)
Data byte will be transmitted;
ACK will be received.
C8H
Last data byte in S1DAT has been transmitted;
ACK has been received.
C0H
B8H
Data byte in S1DAT has been transmitted;
ACK has been received.
Data byte or Last data byte in S1DAT has been
transmitted;
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,1,0)
Last data will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,0,1,1)
Data byte will be transmitted;
ACK will be received.
A0H
A STOP or repeated START has been
received while still addressed as SLV/TRX.
(STA,STO,SI,AA)=(1,0,1,1)
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when the
bus becomes free.
(STA,STO,SI,AA)=(1,0,1,0)
(STA,STO,SI,AA)=(0,0,1,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,1,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 5-21 Slave Transmitter Mode
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Set AA
60H
Own SLA+W has been received;
ACK has been return.
or
68H
Arbitration lost SLA+R/W as master;
Own SLA+W has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,1,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,1,1)
Data byte will be received;
ACK will be returned.
80H
88H
Previously addressed with own SLA address;
Data has been received;
ACK has been returned.
Previously addressed with own SLA address;
NOT ACK has been returned.
(STA,STO,SI,AA)=(0,0,1,0)
Data will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,1,1)
Data will be received;
ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as SLV/REC.
(STA,STO,SI,AA)=(1,0,1,1)
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when
the bus becomes free.
(STA,STO,SI,AA)=(1,0,1,0)
(STA,STO,SI,AA)=(0,0,1,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,1,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 5-22 Slave Receiver Mode
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Set AA
70H
Reception of the general call address
and one or more data bytes;
ACK has been return.
or
78H
Arbitration lost SLA+R/W as master;
and address as SLA by general call;
ACK has been return.
(STA,STO,SI,AA)=(X,0,1,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(X,0,1,1)
Data byte will be received;
ACK will be returned.
90H
98H
Previously addressed with General Call;
Data has been received;
ACK has been returned.
Previously addressed with General Call;
Data byte has been received;
NOT ACK has been returned.
(STA,STO,SI,AA)=(X,0,1,0)
Data will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(X,0,1,1)
Data will be received;
ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as
SLV/REC.
(STA,STO,SI,AA)=(1,0,1,1)
(STA,STO,SI,AA)=(1,0,1,0)
(STA,STO,SI,AA)=(0,0,1,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,1,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when
the bus becomes free.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 5-23 GC Mode
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5.7 PWM Generator and Capture Timer
5.7.1 Introduction
The ISD9160 has a PWM Generator which can be configured as 2 independent PWM outputs,
PWM0~PWM1, or as a complementary PWM pair, (PWM0, PWM1) with a programmable dead-zone
generator. The PWM Generator has an 8-bit prescaler, a clock divider providing 5 divided frequencies
(1, 1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-counters
for PWM period control, two 16-bit comparators for PWM duty control and one dead-zone generator.
The PWM Generator provides PWM interrupt flags which are set by hardware when the corresponding
PWM period down counter reaches zero. Each PWM interrupt source, with its corresponding enable
bit, can generate a PWM interrupt request to the CPU. The PWM generator can be configured in one-
shot mode to produce only one PWM cycle signal or continuous mode to output a periodic PWM
waveform.
When PWM_CTL.DTEN01 is set, PWM0 and PWM1 perform complementary paired PWM function;
the paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0. Refer to Figure 5-25 for the architecture of PWM Timers.
To prevent PWM driving glitches to an output pin, the 16-bit period down-counter and 16-bit
comparator are implemented with a double buffer. When user writes data to the counter/comparator
registers, the updated value will not be load into the 16-bit down-counter/comparator until the down-
counter reaches zero.
When the 16-bit period down-counter reaches zero, the interrupt request is generated. If PWM timer is
configured in continuous mode, when the down counter reaches zero, it is reloaded with PWM
Counter Register (PWM_PERIODx) automatically and begins decrementing again. If the PWM timer is
configured in one-shot mode, the down counter will stop and generate a single interrupt request when
it reaches zero.
The value of PWM counter comparator is used for pulse width modulation. The counter control logic
inverts the output level when down-counter value matches the value of compare register.
The alternate function of the PWM-timer is as a digital input capture timer. If Capture function is
enabled the PWM output pin is switched as a capture input pin. The Capture0 and PWM0 share one
timer which is included in PWM0; and the Capture1 and PWM1 share PWM1 timer. User must setup
the PWM-timer before enabling the Capture feature. After the capture feature is enabled, the count is
latched to the Capture Rising Latch Register (PWM_RCAPDATx) when input channel has a rising
transition and latched to Capture Falling Latch Register (PWM_FCAPDATx) when input channel has a
falling transition. Capture channel 0 interrupt is programmable by setting PWM_CAPCTL01.CRLIEN0
(Rising latch Interrupt enable) and PWM_CAPCTL01.CFLIEN0 (Falling latch Interrupt enable) to
determine the condition of interrupt occurrence. Capture channel 1 has the same feature by setting
PWM_CAPCTL01.CRLIEN1and PWM_CAPCTL01.CFLIEN1. Whenever Capture issues interrupt, the
PWM counter will also be reloaded.
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5.7.2 Features
5.7.2.1 PWM function features:
PWM Generator, incorporating an 8-bit pre-scaler, clock divider, two PWM-timers (down
counters), a dead-zone generator and two PWM outputs.
Up to 2 PWM channels or a paired PWM channel.
16 bits resolution.
PWM Interrupt request synchronous with PWM period.
Single-shot or Continuous mode PWM.
Dead-Zone generator.
5.7.2.2 Capture Function Features:
Timing control logic shared with PWM Generators.
2 Capture input channels shared with 2 PWM output channels.
Each channel supports a rising latch register (RCAPDAT), a falling latch register (FCAPDAT)
and Capture interrupt flag (CAPIFx)
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5.7.3 PWM Generator Architecture
The following figures illustrate the architecture of the PWM.
PWM01_S(CLKSEL1[29:28])
PWM01_EN(APBCLK[20])
CLK48M
11
PWM01_CLK
HCLK
10
CLK32K
01
CLK10K
00
Figure 5-24 PWM Generator Clock Source Control
DZI01
Dead Zone
Generator 0
CSR0(CSR[2:0])
CNR0, CMR0,
PCR
1
100
1/2
000
1
0
PWM-
Timer0
Logic
PA.12/PWM0
1
1/4
001
0
1/8
Clock
Divider
010
011
POE.PWM0
1/16
CH0INV
1
PWMIE0 PWMIF0
1/2
1/4
1/8
1/16
8-bit
Prescaler
PPR.CP01
DZEN01
PWM01_CLK
(from clock
CNR1, CMR1,
PCR
controller)
1
100
000
001
010
011
1/2
1/4
1/8
1/16
1
0
PWM-
Timer1
Logic
PA.13/PWM1
1
0
POE.PWM1
CH1INV
PWMIE1 PWMIF1
CSR1(CSR[6:4])
Figure 5-25 PWM Generator Architecture Diagram
5.7.4 PWM-Timer Operation
The PWM period and duty control are configured by the PWM down-counter register
(PWM_PERIODx) and PWM comparator register (PWM_CMPDATx). Formulas for calculating the
pulse width modulation are shown below and demonstrated in Figure 5-26. Note that the
corresponding GPIO pins must be configured as the alternate function before PWM function is
enabled.
PWM frequency = PWM01_CLK/(prescale+1)*(clock divider)/(PERIOD+1);
Duty cycle = (CMP+1)/(PERIOD+1).
CMP >= PERIOD: PWM output is always high.
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CMP < PERIOD: PWM low width= (PERIOD-CMP) unit1; PWM high width = (CMP+1) unit.
CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit
Note: 1. Unit = one PWM clock cycle.
Start
Update
Initialize
PWM
new CMRx
+
-
PWM-Timer
Comparator
Output
CMRx+1
CNRx
CMRx
CNRx
PWM
Ouput
CMR+1
CNR+1
Note: x= 0~1.
Figure 5-26 PWM Generation Timing
The procedure to operate the PWM generator is shown in Figure 5-27. First initialize the PWM
settings. At the same time ensure that GPIO are configured to PWM function. Next step is to enable
PWM channel. After this, if PERIOD or CMP register is written by software, it is double buffered until
the next counter reload, at which time the registers are updated to new values.
Comparator
(CMR)
1
3
1
0
PWM
down-counter
3
0
2
4
2
1
4
3
1
0
PWM-Timer
output
CMR = 1
CNR = 3
Auto reload = 1
CMR = 0
CNR = 4
(S/W write new value)
(CHxMOD=1)
(Write initial setting)
Auto-load
(PWMIFx is set by H/W)
Auto-load
Set ChxEN=1
(PWM-Timer starts running)
(H/W update value)
(PWMIFx is set by H/W)
Figure 5-27 PWM-Timer Operation Timing
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5.7.5 PWM Double Buffering, Auto-reload and One-shot Operation
The ISD9160 PWM Timers are double buffered, the reload value is updated at the start of next period
without affecting current timer operation. The PWM counter reset value can be written into
PWM_PERIODx and current PWM counter value can be read from PWM_CNTx.
The bit CNTMODEx in PWM Control Register (PWM_CTL) determines whether PWMx operates in
auto-reload or one-shot mode. If CNTMODEx is set to one, the auto-reload operation loads PERIODx
to PWM counter when PWM counter reaches zero. If PERIODx is set to zero, PWM counter will halt
when PWM counter counts to zero. If CNTMODEx is set as zero, counter will stop immediately.
Write
CNR=150
CMR=50
Write
CNR=199
CMR=49
Write
CNR=99
CMR=0
Write
CNR=0
CMR=XX
Start
Stop
PWM
Waveform
51
50
1
write a nonzero number to
prescaler & setup clock
dividor
151
200
100
Figure 5-28 PWM Double Buffering.
5.7.6 Modulate Duty Cycle
The double buffering allows CMP to be written at any point in current cycle. The loaded value will take
effect from next cycle. This is demonstrated in Figure 5-29.
101
51
1
Write
CMR=100
CNR=150
Write
CMR=50
Write
CMR=0
1 PWM cycle = 151
1 PWM cycle = 151
1 PWM cycle = 151
Figure 5-29 PWM Controller Duty Cycle Modulation (PERIOD = 150).
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5.7.7 Dead-Zone Generator
The ISD9160 PWM generator includes a Dead Zone generator. This is used to ensure neither PWM
output is active simultaneously for power device protection. The function generates a programmable
time gap between rising PWM outputs. The user can program PWM_CLKPSC.DTCNT01 to determine
the Dead Zone interval. The Dead Zone generator behavior is demonstrated in Figure 5-30.
PWM-Timer
Output 0
PWM-Timer
Inversed output
1
Dead-Zone
Generator
output 0
Dead-Zone
Generator
output 1
Dead zone interval
Figure 5-30 Paired-PWM Output with Dead Zone Generation Operation
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5.7.8 Capture Timer Operation
Instead of using the PWM generator to output a modulated signal, it can be configured as a capture
timer to measure a modulated input. Capture channel 0 and PWM0 share one timer and Capture
channel 1 and PWM1 share another timer. The capture timer latches PWM-counter to RCAPDAT
when input channel has a rising transition and latches PWM-counter to FCAPDAT when input channel
has a falling transition. Capture channel 0 interrupt is programmable by setting PWM_CAPCTL01[1]
(Rising latch Interrupt enable) and PWM_CAPCTL01[2] (Falling latch Interrupt enable) to decide the
condition of interrupt occurrence. Capture channel 1 has the same feature by setting
PWM_CAPCTL01[17] and PWM_CAPCTL01[18]. Whenever the Capture module issues a capture
interrupt, the corresponding PWM counter will be reloaded with PERIODx at this moment. Note that
the corresponding GPIO pins must be configured as their alternate function before Capture function is
enabled.
PWM Counter
3
2
1
8
7
6
5
8
Reload
7
6
5
4
Reload
No reload due to
no CAPIFx
(If CNRx = 8)
Capture Input x
CAPCHxEN
CFLRx
1
7
CRLRx
5
CFL_IEx
CRL_IEx
CAPIFx
Clear by S/W
Clear by S/W
Set by H/W
Set by H/W
CFLRIx
Set by H/W
Clear by S/W
CRLRIx
Note: X=0~1
Figure 5-31 Capture Operation Timing
Figure 5-31 demonstrates the case where PERIOD = 8:
1. The PWM counter will be reloaded with PERIODx=8 when a capture interrupt flag (CAPIFx) is
set by a transition on the capture input.
2. The channel low pulse width is given by (PERIOD - RCAPDAT).
3. The channel high pulse width is given by (PERIOD - FCAPDAT).
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5.7.9 PWM-Timer Interrupt Architecture
There are two PWM interrupts, PWM0_INT, PWM1_INT, which are multiplexed into PWM_IRQ. PWM
0 and Capture 0 share one interrupt, PWM1 and Capture 1 share the same interrupt. Figure 5-32
demonstrates the architecture of PWM-Timer interrupts.
PWMIF0
PWM0_INT
CAPIF0
PWMA_IRQ
PWMIF1
PWM1_INT
CAPIF1
Figure 5-32 PWM-Timer Interrupt Architecture Diagram
5.7.10 PWM-Timer Initialization Procedure
The following procedure is recommended for starting a PWM generator.
1. Setup clock selector (PWM_CLKDIV)
2. Setup prescaler (PWM_CLKPSC)
3. Setup inverter on/off, dead zone generator on/off, auto-reload/one-shot mode and Stop PWM-
timer (PWM_CTL)
4. Setup comparator register (PWM_CMPDATx) to set PWM duty cycle.
5. Setup PWM down-counter register (PWM_PERIODx) to set PWM period.
6. Setup interrupt enable register (PWM_INTEN)
7. Setup PWM output enable (PWM_POEN)
8. Setup the corresponding GPIO pins to PWM function (SYS_GPA_MFP)
9. Enable PWM timer start (Set CNTENx = 1 in PWM_CTL)
5.7.11
PWM-Timer Stop Procedure
Method 1:
Set 16-bit down counter (PERIOD) as 0, and monitor CNT (current value of 16-bit down-counter).
When CNT reaches to 0, disable PWM-Timer (CNTENx in PWM_CTL). (Recommended)
Method 2:
Set 16-bit down counter (PERIOD) as 0. When interrupt request occurs, disable PWM-Timer
(CNTENx in PWM_CTL). (Recommended)
Method 3:
Disable PWM-Timer directly (CNTENx in PWM_CTL). (Not recommended)
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5.7.12 Capture Start Procedure
1.
2.
3.
Setup clock selector (PWM_CLKDIV)
Setup prescaler (PWM_CLKPSC)
Setup channel enable, rising/falling interrupt enable and input signal inverter on/off
(PWM_CAPCTL01)
4.
5.
6.
7.
Setup PWM down-counter (PWM_PERIODx)
Set Capture Input Enable Register (PWM_CAPINEN)
Setup the corresponding GPIO pins to PWM function (SYS_GPA_MFP)
Enable PWM timer start running (Set CNTENx = 1 in PWM_CTL)
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5.7.13 Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
Register
Offset
R/W Description
Reset Value
PWMA Base Address:
PWM_BA = 0x4004_0000
PWM_CLKPSC
PWM_CLKDIV
PWM_CTL
PWM_BA+0x000
PWM_BA+0x004
PWM_BA+0x008
PWM_BA+0x00C
PWM_BA+0x010
PWM_BA+0x014
PWM_BA+0x018
PWM_BA+0x01C
PWM_BA+0x020
PWM_BA+0x040
PWM_BA+0x044
PWM_BA+0x050
PWM_BA+0x058
PWM_BA+0x05C
PWM_BA+0x060
PWM_BA+0x064
PWM_BA+0x078
R/W PWM Prescaler Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
R/W
PWM Clock Select Register
R/W PWM Control Register
PWM_PERIOD0
PWM_CMPDAT0
PWM_CNT0
R/W PWM Counter Register 0
R/W PWM Comparator Register 0
R
PWM Data Register 0
PWM_PERIOD1
PWM_CMPDAT1
PWM_CNT1
R/W PWM Counter Register 1
R/W PWM Comparator Register 1
R
PWM Data Register 1
PWM_INTEN
R/W PWM Interrupt Enable Register
R/W PWM Interrupt Flag Register
R/W Capture Control Register 0
PWM_INTSTS
PWM_CAPCTL01
PWM_RCAPDAT0
PWM_FCAPDAT0
PWM_RCAPDAT1
PWM_FCAPDAT1
PWM_CAPINEN
PWM_POEN
R
R
R
R
Capture Rising Latch Register (Channel 0)
Capture Falling Latch Register (Channel 0)
Capture Rising Latch Register (Channel 1)
Capture Falling Latch Register (Channel 1)
R/W Capture Input Enable Register
R/W PWM
Output
Enable
Register
for
PWM_BA+0x07C
0x0000_0000
PWM0~PWM1
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5.7.14
Register Description
PWM Pre-Scale Register (PWM_CLKPSC)
Register
Offset
R/W
Description
Reset Value
PWM_CLKPSC
PWM_BA+0x000 R/W
PWM Prescaler Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
Reserved
DTCNT01
Reserved
CLKPSC01
19
11
3
1
0
Table 5-57 PWM Pre-Scaler Register (PWM_CLKPSC, address 0x4004_0000).
Bits
Description
[31:24]
Reserved
DTCNT01
Reserved
Reserved
Dead Zone Interval Register For Pair Of PWM0 And PWM1
These 8 bits determine dead zone length.
[23:16]
[15:8]
The unit time of dead zone length is that from clock selector 0.
Reserved
Clock Pre-scaler
Clock input is divided by (CLKPSC01 + 1).
If CLKPSC01 aaa 0, then the pre-scaler output clock will be stopped.
This implies PWM counter 0 and 1 will also be stopped.
[7:0]
CLKPSC01
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PWM Clock Select Register (PWM_CLKDIV)
Register
Offset
R/W
Description
Reset Value
PWM_CLKDIV
PWM_BA+0x004 R/W
PWM Clock Select Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
CLKDIV1
Reserved
CLKDIV0
Table 5-58 PWM Clock Select Register (PWM_CLKDIV, address 0x4004_0004).
Bits
Description
[31:7]
Reserved
Reserved
Timer 1 Clock Source Selection
Value
:
Input clock divided by
0
1
2
3
4
:
2
4
[6:4]
[2:0]
CLKDIV1
:
:
:
:
8
16
1
Timer 0 Clock Source Selection
CLKDIV0
(Table is as CLKDIV1)
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PWM Control Register (PWM_CTL)
Register
Offset
R/W
Description
Reset Value
PWM_CTL
PWM_BA+0x008 R/W
PWM Control Register
0x0000_0000
15
7
14
6
13
5
12
11
10
PINV1
2
9
8
Reserved
CNTMODE1
3
Reserved
1
CNTEN1
0
4
Reserved
DTEN01
CNTMODE0
PINV0
Reserved
CNTEN0
Table 5-59 PWM Control Register (PWM_CTL, address 0x4004_008).
Description
Bits
[11]
PWM-Timer 1 Auto-reload/One-Shot Mode
0 = One-Shot Mode
CNTMODE1
1 = Auto-load Mode
Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to
be cleared.
PWM-Timer 1 Output Inverter ON/OFF
0 = Inverter OFF
[10]
[8]
PINV1
1 = Inverter ON
PWM-Timer 1 Enable/Disable Start Run
0 = Stop PWM-Timer 1
CNTEN1
1 = Enable PWM-Timer 1 Start/Run
Dead-Zone 0 Generator Enable/Disable
0 = Disable
1 = Enable
[4]
DTEN01
Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 become
a complementary pair.
PWM-Timer 0 Auto-reload/One-Shot Mode
0 = One-Shot Mode
[3]
[2]
CH0MOD
CH0INV
1 = Auto-reload Mode
Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to
be cleared.
PWM-Timer 0 Output Inverter ON/OFF
0 = Inverter OFF
1 = Inverter ON
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PWM-Timer 0 Enable/Disable Start Run
0 = Stop PWM-Timer 0 Running
[0]
CNTEN0
1 = Enable PWM-Timer 0 Start/Run
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PWM Counter Register 1-0 (PWM_PERIODx)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
PWM_PERIOD0
PWM_PERIOD1
PWM_BA+0x00C R/W
PWM_BA+0x018 R/W
PWM Counter Register 0
PWM Counter Register 1
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
19
11
3
PERIOD [15:8]
PERIOD [7:0]
1
0
Table 5-60 PWM Counter Register (PWM_PERIODx, address 0x4004_00C+C*x).
Bits
Description
PWM Counter/Timer Reload Value
PERIOD determines the PWM period.
PWM frequency aaa PWM01_CLK/(prescale+1)*(clock divider)/(PERIOD+1);
Duty ratio aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
[15:0]
PERIOD
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit; PWM high width aaa
(CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit; PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note:
Any write to PERIOD will take effect in next PWM cycle.
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PWM Comparator Register (PWM_CMPDATx)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
PWM_CMPDAT0
PWM_CMPDAT1
PWM_BA+0x010 R/W
PWM_BA+0x01C R/W
PWM Comparator Register 0
PWM Comparator Register 1
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
CMP[15:8]
CMP[7:0]
1
0
Table 5-61 PWM Comparator Register (PWM_CMPDATx, address 0x4004_0010 + C*x).
Bits
Description
PWM Comparator Register
CMP determines the PWM duty cycle.
PWM frequency aaa PWM01_CLK/(prescale+1)*(clock divider)/(PERIOD+1);
Duty Cycle aaa (CMP+1)/(PERIOD+1).
CMP > aaa PERIOD: PWM output is always high.
[15:0]
CMP
CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit; PWM high width aaa
(CMP+1) unit.
CMP aaa 0: PWM low width aaa (PERIOD) unit; PWM high width aaa 1 unit
(Unit aaa one PWM clock cycle)
Note: Any write to CMP will take effect in next PWM cycle.
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PWM Data Register 1-0 (PWM_CNTx)
Register
Offset
R/W
R
Description
Reset Value
0x0000_0000
0x0000_0000
PWM_CNT0
PWM_CNT1
PWM_BA+0x014
PWM_BA+0x020
PWM Data Register 0
PWM Data Register 1
R
15
7
14
6
13
12
11
3
10
2
9
1
8
0
CNT[15:8]
5
4
CNT[7:0]
Table 5-62 PWM Data Register (PWM_CNTx, address 0x4004_0014 + C*x).
Bits
Description
PWM Data Register
CNT
[15:0]
Reports the current value of the 16-bit down counter.
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PWM Interrupt Enable Register (PWM_INTEN)
Register
Offset
R/W
Description
Reset Value
PWM_INTEN
PWM_BA+0x040 R/W
PWM Interrupt Enable Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
PIEN1
PIEN0
Table 5-63 PWM Interrupt Enable Register (PWM_INTEN, address 0x4004_0040).
Bits
[1]
Description
PWM Timer 1 Interrupt Enable
PIEN1
PIEN0
0 = Disable
1 = Enable
PWM Timer 0 Interrupt Enable
0 = Disable
[0]
1 = Enable
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PWM Interrupt Flag Register (PWM_INTSTS)
Register
Offset
R/W
Description
Reset Value
PWM_INTSTS
PWM_BA+0x044 R/W
PWM Interrupt Flag Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
PIF1
PIF0
Table 5-64 PWM Interrupt Flag Register (PWM_INTSTS, address 0x4004_0044).
Bits
[1]
Description
PWM Timer 1 Interrupt Flag
PIF1
Flag is set by hardware when PWM1 down counter reaches zero, software can clear
this bit by writing ‘1’ to it.
PWM Timer 0 Interrupt Flag
[0]
PIF0
Flag is set by hardware when PWM0 down counter reaches zero, software can clear
this bit by writing ‘1’ to it.
Note: User can clear each interrupt flag by writing a one to corresponding bit in PWM_INTSTS.
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Capture Control Register (PWM_CAPCTL01)
Register
Offset
R/W
Description
Reset Value
PWM_CAPCTL01
PWM_BA+0x050 R/W
Capture Control Register 0
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
Reserved
23
CFLIF1
15
22
CRLIF1
14
21
Reserved
13
20
CAPIF1
12
19
CAPEN1
11
18
CFLIEN1
10
17
CRLIEN1
9
16
CAPINV1
8
7
6
5
4
3
2
1
0
CFLIF0
CRLIF0
Reserved
CAPIF0
CAPEN0
CFLIEN0
CRLIEN0
CAPINV0
Table 5-65 Capture Control Register (PWM_CAPCTL01, address 0x4004_0050).
Bits
[23]
Description
PWM_FCAPDAT1 Latched Indicator Bit
When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the
value of PWM down-counter and this bit is set by hardware, software can clear this bit
by writing a zero to it.
CFLIF1
CRLIF1
PWM_RCAPDAT1 Latched Indicator Bit
When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the
value of PWM down-counter and this bit is set by hardware, software can clear this bit
by writing a zero to it.
[22]
[20]
Capture1 Interrupt Indication Flag
If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1), a rising transition at
input channel 1 will result in CAPIF1 to high; Similarly, a falling transition will cause
CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN1 aaa 1).
This flag is cleared by software writing a ‘1’ to it.
CAPIF1
Capture Channel 1 Transition Enable/Disable
0 = Disable capture function on channel 1
1 = Enable capture function on channel 1.
[19]
[18]
CAPEN1
CFLIEN1
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch)
and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
Channel 1 Falling Latch Interrupt Enable
0 = Disable falling edge latch interrupt
1 = Enable falling edge latch interrupt.
When enabled, capture block generates an interrupt on falling edge of input.
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Channel 1 Rising Latch Interrupt Enable
0 = Disable rising edge latch interrupt
[17]
CRLIEN1
1 = Enable rising edge latch interrupt.
When enabled, capture block generates an interrupt on rising edge of input.
Channel 1 Inverter ON/OFF
[16]
[7]
CAPINV1
CFLIF0
0 = Inverter OFF
1 = Inverter ON. Reverse the input signal from GPIO before Capture timer
PWM_FCAPDAT0 Latched Indicator Bit
When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the
value of PWM down-counter and this bit is set by hardware, software can clear this bit
by writing a zero to it.
PWM_RCAPDAT0 Latched Indicator Bit
When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the
value of PWM down-counter and this bit is set by hardware, software can clear this bit
by writing a zero to it.
[6]
[4]
CRLIF0
CAPIF0
Capture0 Interrupt Indication Flag
If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1), a rising transition at
input channel 0 will result in CAPIF0 to high; Similarly, a falling transition will cause
CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFLIEN0 aaa 1).
This flag is cleared by software writing a ‘1’ to it.
Capture Channel 0 transition Enable/Disable
0 = Disable capture function on channel 0
1 = Enable capture function on channel 0.
[3]
[2]
CAPEN0
CFLIEN0
When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch)
and FCAPDAT (Falling latch) registers on input edge transition.
When disabled, Capture function is inactive as is interrupt.
Channel 0 Falling Latch Interrupt Enable ON/OFF
0 = Disable falling latch interrupt
1 = Enable falling latch interrupt.
When enabled, capture block generates an interrupt on falling edge of input.
Channel 0 Rising Latch Interrupt Enable ON/OFF
0 = Disable rising latch interrupt
[1]
[0]
CRLIEN0
CAPINV0
1 = Enable rising latch interrupt.
When enabled, capture block generates an interrupt on rising edge of input.
Channel 0 Inverter ON/OFF
0 = Inverter OFF
1 = Inverter ON. Reverse the input signal from GPIO before Capture timer
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Capture Rising Latch Register1-0 (PWM_RCAPDATx)
Register
Offset
R/W Description
Reset Value
PWM_RCAPDAT0
PWM_RCAPDAT1
PWM_BA+0x058
PWM_BA+0x060
R
R
Capture Rising Latch Register (Channel 0)
Capture Rising Latch Register (Channel 1)
0x0000_0000
0x0000_0000
15
7
14
6
13
12
11
3
10
2
9
1
8
0
RCAPDAT[15:8]
5
4
RCAPDAT[7:0]
Table 5-66 Capture Rising Latch Register (PWM_RCAPDATx, address 0x4004_0058 +C*x).
Bits
Description
Capture Rising Latch Register
[15:0]
RCAPDAT
In Capture mode, this register is latched with the value of the PWM counter on a rising
edge of the input signal.
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Capture Falling Latch Register1-0 (PWM_FCAPDATx)
Register
Offset
R/W
R
Description
Reset Value
0x0000_0000
0x0000_0000
PWM_FCAPDAT0
PWM_FCAPDAT1
PWM_BA+0x05C
PWM_BA+0x064
Capture Falling Latch Register (Channel 0)
Capture Falling Latch Register (Channel 1)
R
15
7
14
6
13
5
12
11
3
10
2
9
1
8
0
FCAPDAT[15:8]
4
FCAPDAT[7:0]
Table 5-67 Capture Falling Latch Register (PWM_FCAPDATx, address 0x4004_005C + C*x).
Bits
Description
Capture Falling Latch Register
[15:0]
FCAPDAT
In Capture mode, this register is latched with the value of the PWM counter on a
falling edge of the input signal.
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Capture Input Enable Register (PWM_CAPINEN)
Register
Offset
R/W
Description
Reset Value
PWM_CAPINEN
PWM_BA+0x078 R/W
Capture Input Enable Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
CAPINEN[1:0]
Table 5-68 Capture Input Enable Register (PWM_CAPINEN, address 0x4004_0078).
Bits
Description
Capture Input Enable Register
0 : OFF (PA[13:12] pin input disconnected from Capture block)
1 : ON (PA[13:12] pin, if in PWM alternative function, will be configured as an input
and fed to capture function)
[1:0]
CAPINEN
CAPINEN[1:0]
Bit 10
Bit x1 : Capture channel 0 is from PA [12]
Bit 1x : Capture channel 1 is from PA [13]
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PWM Output Enable Register (PWM_POEN)
Register
Offset
R/W Description
R/W PWM Output Enable Register for PWM0~PWM1
Reset Value
PWM_POEN
PWM_BA+0x07C
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
POEN1
POEN0
Table 5-69 PWM Output Enable (PWM_POEN, address 0x4004_007C).
Description
Bits
[1]
PWM1 Output Enable Register
0 = Disable PWM1 output to pin.
1 = Enable PWM1 output to pin.
POEN1
POEN0
Note: The corresponding GPIO pin also must be switched to PWM function (refer to
SYS_GPA_MFP Error! Reference source not found.)
PWM0 Output Enable Register
0 = Disable PWM0 output to pin.
1 = Enable PWM0 output to pin.
[0]
Note: The corresponding GPIO pin also must be switched to PWM function (refer to
SYS_GPA_MFP Error! Reference source not found.)
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5.8 Real Time Clock (RTC)
5.8.1 Overview
Real Time Clock (RTC) unit provides real time clock, calendar and alarm functions. The clock source
of the RTC is an external 32.768 kHz crystal connected at pins XI32K and XO32K or from an external
32.768 kHz oscillator output fed to pin XI32K. The RTC unit provides the time (second, minute, hour)
in Time Load Register (RTC_TIME) as well as calendar (day, month, year) in Calendar Load Register
(RTC_CAL). The data is expressed in BCD (Binary Coded Decimal) format. The unit offers an alarm
function whereby the user can preset the alarm time in the Time Alarm Register (RTC_TALM) and
alarm calendar in Calendar Alarm Register (RTC_CALM).
The RTC unit supports periodic Time-Tick and Alarm-Match interrupts. The periodic interrupt has 8
period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by
RTC_TICK.TICKSEL. When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting
registers RTC_TALM and RTC_CALM, the alarm interrupt flag (RTC_INTSTS.AIF) is set and the
alarm interrupt is requested if the alarm interrupt is enabled (RTC_INTEN.ALMIEN=1). The RTC Time
Tick and Alarm Match can wake the CPU from sleep mode or Standby Power-Down (SPD) mode if the
Wakeup CPU function is enabled (RTC_TICK.TWKEN).
5.8.2 RTC Features
Consists of a time counter (second, minute, hour) and calendar counter (day, month, year).
Alarm register (second, minute, hour, day, month, year).
12-hour or 24-hour mode is selectable.
Automatic leap year compensation.
Day of week counter.
Frequency compensate register (FCR).
All time and calendar registers are expressed in BCD code.
Support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and
1 second.
Support RTC Time-Tick and Alarm-Match interrupt
Support CPU wakeup from sleep or standby power-down mode.
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5.8.3 RTC Block Diagram
Time Alarm
Calendar Alarm
AIER(RIER[0])
Register (TAR) Register (CAR)
AIF(RIIR[0])
Alarm
Interrupt
Compare
Operation
Time Load
Calendar Load
Register (TLR) Register (CLR)
Wakeup CPU from
Power-down mode
(sec)
1/128 change
1/64 change
1/32 change
1/16 change
1/8 change
1/4 change
1/2 change
1 change
111
110
101
100
011
010
001
000
Leap Year Indicator (LIP)
TSSR.24Hr/12Hr
TWKE(TTR[3])
TIER(RIER[1])
Day of Week
(DWR)
TIF(RIIR[1])
Periodic
Interrupt
RTC Time Counter
Control Unit
Initiation/Enable
(INIR/AER)
Frequency
Compensation
Clock Source
32776 ~32761
TTR(TTR[2:0])
Frequency
Compensation
Register (FCR)
Figure 5-33 RTC Block Diagram
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5.8.4 RTC Function Description
5.8.4.1 Access to RTC register
Due to clock frequency difference between RTC clock and system clock, when the user writes new
data to any one of the RTC registers, the register will not be updated until 2 RTC clock periods later
(60us). The programmer should take this into consideration for determining access sequence between
RTC_CLKFMT, RTC_TALM and RTC_TIME.
In addition, the RTC block does not check whether written data is out of bounds for a valid BCD time
or calendar load. RTC does not check validity of RTC_WEEKDAY and RTC_CAL write either.
5.8.4.2 RTC Initiation
When RTC block is powered on, programmer must write 0xA5EB1357 to RTC_INIT register to reset
all logic. RTC_INIT acts as a hardware reset circuit. Once RTC_INIT has been set to 0xA5EB1357,
internal reset operation begins. When reset operation is finished, RTC_INIT[0] is set by hardware and
RTC is ready for operation.
5.8.4.3 RTC Read/Write Enable
Register RTC_RWEN[15:0] serves as the RTC read/write password to protect RTC registers.
RTC_RWEN[15:0] have to be set to 0xA965 to enable access. Once set, it will take effect 512 RTC
clocks later (about 15ms). Programmer can read RTC enabled status flag in RTC_RWEN.RWENF to
check whether RTC is access enabled. Access is automatically cleared after 200ms.
5.8.4.4 Frequency Compensation
The RTC Frequency Compensation Register (RTC_FREQADJ) allows software to configure digital
compensation to the 32768Hz clock input. The RTC_FREQADJ allows compensation of a clock input
in the range from 32761Hz to 32776Hz. If desired, RTC clock can be measured during manufacture
from a GPIO pin and compensation value calculated and stored in flash memory for retrieval when the
product is first powered on. Following are compensation examples for a higher or lower measured
frequency clock input.
Example 1:
Frequency counter measurement : 32773.65Hz ( > 32768 Hz)
Integer part: 32773 = 0x8005
RTC_FREQADJ. INTEGER = (32773 – 32761) = 12 = 0x0C
Fractional part: 0.65 x 60 = 39 = 0x27
RTC_FREQADJ. FRACTION = 0x27
Example 2
Frequency counter measurement : 32765.27Hz ( < 32768 Hz)
Integer part: 32765 = 0x7ffd
RTC_FREQADJ.INTEGER = (32765 – 32761) = 4 = 0x04
Fractional part: 0.27 x 60 = 16.2 = 0x10
RTC_FREQADJ.FRACTION = 0x10
5.8.4.5 Time and Calendar counter
RTC_TIME and RTC_CAL are used to load the time and calendar. RTC_TALM and RTC_CALM are
used to set the alarm. They are all represented by a BCD format, see register descriptions for digit
assignments.
5.8.4.6 12/24 hour Time Scale Selection
RTC can be selected to report time in either a 12 or 24hour time scale. If 12 hour mode is selected
then AM/PM indication is provided by the hour digit being >=2, see register description Table 5-76 for
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details. The 12/24 hour time scale selection depends on RTC_CLKFMT bit 0.
5.8.4.7 Day of the week counter
The RTC unit provides day of week in Day of the Week Register (RTC_WEEKDAY). The value is
defined from 0 to 6 to represent Sunday to Saturday respectively.
5.8.4.8 Periodic Time Tick Interrupt
The periodic interrupt has 8 period option 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are
selected by RTC_TICK.TICKSEL. When periodic time tick interrupt is enabled by setting
RTC_INTEN.TICKIEN to 1, the Periodic Time Tick Interrupt is requested as selected by RTC_TICK
register.
5.8.4.9 Alarm Time Interrupt
When RTC counter in RTC_TIME and RTC_CAL is equal to alarm setting in RTC_TALM and
RTC_CALM the alarm interrupt flag (RTC_INTSTS.AIF) is set. If alarm interrupt is enabled
(RTC_INTEN.ALMIEN=1) the alarm interrupt is also requested.
5.8.4.10 Additional Notes
1. RTC_TALM, RTC_CALM, RTC_TIME and RTC_CAL registers are all BCD counter.
2. Programmer has to make sure that values loaded are reasonable. For example, some invalid
RTC_CAL values would be 201a (year), 13 (month), 00 (day).
3. Reset state :
Register
Reset State
RTC_RWEN
RTC_CAL
0
05/1/1 (year/month/day)
00:00:00 (hour : minute : second)
00/00/00 (year/month/day)
00:00:00 (hour : minute : second)
1 (24 hr. mode)
RTC_TIME
RTC_CALM
RTC_TALM
RTC_CLKFMT
RTC_WEEKDAY 6 (Saturday)
RTC_INTEN
0
0
0
0
RTC_INTSTS
RTC_LEAPYEAR
RTC_TICK
4. In RTC_TIME and RTC_TALM, only 2 BCD digits are used to express “year”. It is assumed that 2
BCD digits of xY denote 20xY, but not 19xY or 21xY.
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5.8.5 Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
Register
Offset
R/W Description
Reset Value
RTC Base Address:
RTC_BA = 0x4000_8000
RTC_INIT
RTC_BA+0x000 R/W RTC Initialization Register
RTC_BA+0x004 R/W RTC Access Enable Register
0x0000_0000
0x0000_0000
RTC_RWEN
RTC_FREQADJ
RTC_TIME
RTC_BA+0x008 R/W RTC Frequency Compensation Register 0x0000_0700
RTC_BA+0x00C R/W Time Load Register
RTC_BA+0x010 R/W Calendar Load Register
RTC_BA+0x014 R/W Time Scale Selection Register
RTC_BA+0x018 R/W Day of the Week Register
RTC_BA+0x01C R/W Time Alarm Register
RTC_BA+0x020 R/W Calendar Alarm Register
0x0000_0000
0x0005_0101
0x0000_0001
0x0000_0006
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
RTC_CAL
RTC_CLKFMT
RTC_WEEKDAY
RTC_TALM
RTC_CALM
RTC_LEAPYEAR
RTC_INTEN
RTC_INTSTS
RTC_TICK
RTC_BA+0x024
R
Leap year Indicator Register
RTC_BA+0x028 R/W RTC Interrupt Enable Register
RTC_BA+0x02C R/W RTC Interrupt Indicator Register
RTC_BA+0x030 R/W RTC Time Tick Register
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5.8.6
Register Description
RTC Initiation Register (RTC_INIT)
Register
Offset
R/W
Description
Reset Value
RTC_INIT
RTC_BA+0x000 R/W
RTC Initialization Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
8
INIT
INIT
INIT
4
1
0
INIT
ATVSTS
Table 5-70 RTC Initialization Register (RTC_INIT, address 0x4000_8000).
Bits
Description
RTC Initialization
INIT
[31:1]
After a power-on reset (POR) RTC block should be initialized by writing 0xA5EB1357
to INIT. This will force a hardware reset then release all logic and counters.
RTC Active Status (Read only)
0: RTC is in reset state
[0]
ATVSTS
1: RTC is in normal active state.
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RTC Access Enable Register (RTC_RWEN)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x004
RTC_RWEN
R/W
RTC Access Enable Register
0x0000_0000
23
15
7
22
14
6
21
13
5
20
Reserved
12
19
11
3
18
10
2
17
9
16
RWENF
8
RWEN
RWEN
4
1
0
Table 5-71 RTC Access Enable Register (RTC_RWEN, address 0x4000_8004).
Bits
Description
RTC Register Access Enable Flag (Read only)
1 = RTC register read/write enable.
0 = RTC register read/write disable
This bit will be set after RWEN[15:0] register is set to 0xA965, it will clear automatically in 512
RTC clock cycles or RWEN[15:0] ! aaa 0xA965. The effect of RTC_RWEN.RWENF on access to
each register is given Table 5-72.
Table 5-72 RTC_RWEN.RWENF Register Access Effect.
Register
:
RWENF aaa 1 : RWENF aaa 0
RTC_INIT
:
R/W
:
R/W
RTC_FREQADJ
RTC_TIME
:
R/W
:
R
R
-
[16]
RWENF
:
R/W
:
:
RTC_CAL
:
R/W
RTC_CLKFMT
:
R/W
:
R/W
RTC_WEEKDAY
RTC_TALM
:
R/W
:
R
:
R/W
:
-
RTC_CALM
:
R/W
:
:
-
RTC_LEAPYEAR
R
:
R
RTC_INTEN
RTC_INTSTS
RTC_TICK
:
R/W
:
R/W
: R/W
:
R/W
R/W
:
:
-
RTC Register Access Enable Password (Write only)
0xA965 aaa Enable RTC access
[15:0]
RWEN
Others aaa Disable RTC access
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RTC Frequency Compensation Register (RTC_FREQADJ)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x008
RTC_FREQADJ
R/W
RTC Frequency Compensation Register
0x0000_0700
31
23
15
7
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
14
Reserved
6
INTEGER
1
0
Reserved
FRACTION
Table 5-73 RTC Frequency Compensation Register (RTC_FREQADJ, address 0x4000_8008).
Bits
Description
Integer Part
Register should contain the value (INT(Factual) – 32761)
[11:8]
INTEGER
Ex: Integer part of detected value aaa 32772,
RTC_FREQADJ.INTEGER aaa 32772-32761 aaa 11 (1011b)
The range between 32761 and 32776
Fractional Part
[5:0]
FRACTION
Formula aaa (fraction part of detected value) x 60
Refer to 5.8.4.4 for the examples.
Note: This register can be read back after the RTC enable is active.
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RTC Time Load Register (RTC_TIME)
This register is Read Only until access enable password is written to RTC_RWEN register. The
register returns the current time.
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x00C
RTC_TIME
R/W
Time Load Register
0x0000_0000
23
15
22
14
6
21
20
19
11
3
18
10
2
17
9
16
8
Reserved
TENHR
HR
MIN
SEC
13
TENMIN
5
12
4
Reserved
7
1
0
Reserved
TENSEC
Table 5-74 RTC Time Load Register (RTC_TIME, address 0x4000_800C).
Bits
Description
[21:20]
[19:16]
[14:12]
[11:8]
[6:4]
TENHR
HR
10 Hour Time Digit (0~3)
1 Hour Time Digit (0~9)
10 Min Time Digit (0~5)
1 Min Time Digit (0~9)
10 Sec Time Digit (0~5)
1 Sec Time Digit (0~9)
TENMIN
MIN
TENSEC
SEC
[3:0]
Note:
1.
2.
RTC_TIME is a BCD counter and RTC will not check loaded data for validity.
Valid range is listed in the parenthesis.
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RTC Calendar Load Register (RTC_CAL)
This register is Read Only until access enable password is written to RTC_RWEN register. The
register returns the current date.
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x010
RTC_CAL
R/W
Calendar Load Register
0x0005_0101
31
23
15
7
30
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
20
22
TENYEAR
14
YEAR
MON
DAY
12
TENMON
4
Reserved
6
1
0
Reserved
TENDAY
Table 5-75 RTC Calendar Load Register (RTC_CAL, address 0x4000_80010).
Bits
Description
[23:20]
[19:16]
[12]
TENYEAR
YEAR
10-Year Calendar Digit (0~9)
1-Year Calendar Digit (0~9)
10-Month Calendar Digit (0~1)
1-Month Calendar Digit (0~9)
10-Day Calendar Digit (0~3)
1-Day Calendar Digit (0~9)
TENMON
MON
[11:8]
[5:4]
TENDAY
DAY
[3:0]
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RTC Time Scale Selection Register (RTC_CLKFMT)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x014
RTC_CLKFMT
R/W
Time Scale Selection Register
0x0000_0001
Table 5-76 RTC Time Scale Selection Register (RTC_CLKFMT, address 0x4000_8014).
7
6
5
4
3
2
1
0
Reserved
24HEN
Bits
Description
24-Hour / 12-Hour Mode Selection
Determines whether RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour
mode
1 = select 24-hour time scale
0 = select 12-hour time scale with AM and PM indication
[0]
24HEN
The range of 24-hour time scale is between 0 and 23.
12-hour time scale:
01(AM01), 02(AM02), 03(AM03), 04(AM04), 05(AM05), 06(AM06)
07(AM07), 08(AM08), 09(AM09), 10(AM10), 11(AM11), 12(AM12)
21(PM01), 22(PM02), 23(PM03), 24(PM04), 25(PM05), 26(PM06)
27(PM07), 28(PM08), 29(PM09), 30(PM10), 31(PM11), 32(PM12)
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RTC Day of the Week Register (RTC_WEEKDAY)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x018
RTC_WEEKDAY
R/W
Day of the Week Register
0x0000_0006
7
6
5
4
3
2
1
0
Reserved
WEEKDAY
Table 5-77 RTC Day of Week Register (RTC_WEEKDAY, address 0x4000_8018).
Bits
Description
Day of the Week Register
[2:0]
WEEKDAY
0 (Sunday), 1 (Monday), 2 (Tuesday), 3 (Wednesday)
4 (Thursday), 5 (Friday), 6 (Saturday)
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RTC Time Alarm Register (RTC_TALM)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x01C
RTC_TALM
R/W
Time Alarm Register
0x0000_0000
31
23
15
30
22
14
6
29
21
28
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
20
Reserved
TENHR
HR
MIN
SEC
13
TENMIN
5
12
4
Reserved
7
1
0
Reserved
TENSEC
Table 5-78 RTC Time Alarm Register (RTC_TALM, address 0x4000_801C).
Bits
Description
[21:20]
[19:16]
[14:12]
[11:8]
[6:4]
TENHR
HR
10 Hour Time Digit of Alarm Setting (0~3)
1 Hour Time Digit of Alarm Setting (0~9)
10 Min Time Digit of Alarm Setting (0~5)
1 Min Time Digit of Alarm Setting (0~9)
10 Sec Time Digit of Alarm Setting (0~5)
1 Sec Time Digit of Alarm Setting (0~9)
TENMIN
MIN
TENSEC
SEC
[3:0]
Note:
1.
2.
RTC_TALM is a BCD digit counter and RTC will not check validity of loaded data. Valid range is listed in the parenthesis.
This register can be read back after the RTC unit is active.
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RTC Calendar Alarm Register (RTC_CALM)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x020
RTC_CALM
R/W
Calendar Alarm Register
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
27
26
18
10
2
25
17
9
24
16
8
Reserved
22
TENYEAR
14
19
11
3
YEAR
MON
DAY
Reserved
6
TENMON
4
1
0
Reserved
TENDAY
Table 5-79 RTC Calendar Alarm Register (RTC_CALM, address 0x4000_8020).
Bits
Description
[23:20]
[19:16]
[12]
TENYEAR
YEAR
10-Year Calendar Digit of Alarm Setting (0~9)
1-Year Calendar Digit of Alarm Setting (0~9)
10-Month Calendar Digit of Alarm Setting (0~1)
1-Month Calendar Digit of Alarm Setting (0~9)
10-Day Calendar Digit of Alarm Setting (0~3)
1-Day Calendar Digit of Alarm Setting (0~9)
TENMON
MON
[11:8]
[5:4]
TENDAY
DAY
[3:0]
Note:
1.
RTC_TIME is a BCD digit counter and RTC will not check validity loaded data, valid range is listed in the parenthesis.
This register can be read back after the RTC unit is active.
2.
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RTC Leap year Indication Register (RTC_LEAPYEAR)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x024
RTC_LEAPYEAR
R
Leap year Indicator Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
LEAPYEAR
Table 5-80 RTC Leap Year Indicator Register (RTC_LEAPYEAR, address 0x4000_8024).
Bits
[0]
Description
Leap Year Indication Register (read only)
LEAPYEAR
0 = Current year is not a leap year
1 = Current year is leap year
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RTC Interrupt Enable Register (RTC_INTEN)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x028
RTC_INTEN
R/W
RTC Interrupt Enable Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
TICKIEN
ALMIEN
Table 5-81 RTC Interrupt Enable Register (RTC_INTEN, address 0x4000_8028).
Description
Bits
[1]
Time-Tick Interrupt and Wakeup-by-Tick Enable
TICKIEN
ALMIEN
0 = RTC Time-Tick Interrupt is disabled.
1 = RTC Time-Tick Interrupt is enabled.
Alarm Interrupt Enable
[0]
0 = RTC Alarm Interrupt is disabled
1 = RTC Alarm Interrupt is enabled
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RTC Interrupt Indication Register (RTC_INTSTS)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x02C
RTC_INTSTS
R/W
RTC Interrupt Indicator Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
TICKIF
ALMIF
Table 5-82 RTC Interrupt Indication Register (RTC_INTSTS, address 0x4000_802C).
Bits
[1]
Description
RTC Time-Tick Interrupt Flag
When RTC Time-Tick Interrupt is enabled (RTC_INTEN.TICKIEN=1), RTC unit will set
TIF high at the rate selected by RTC_TICK[2:0]. This bit cleared/acknowledged by
writing 1 to it.
TICKIF
0= Indicates no Time-Tick Interrupt condition.
1= Indicates RTC Time-Tick Interrupt generated.
RTC Alarm Interrupt Flag
When RTC Alarm Interrupt is enabled (RTC_INTEN.ALMIEN=1), RTC unit will set AIF
to high once the RTC real time counters RTC_TIME and RTC_CAL reach the alarm
setting time registers RTC_TALM and RTC_CALM. This bit cleared/acknowledged by
writing 1 to it.
[0]
ALMIF
0= Indicates no Alarm Interrupt condition.
1= Indicates RTC Alarm Interrupt generated.
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RTC Time-Tick Register (RTC_TICK)
Register
Offset
R/W
Description
Reset Value
RTC_BA+0x030
RTC_TICK
R/W
RTC Time Tick Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
TWKEN
TICKSEL
Table 5-83 RTC Time-Tick Register (RTC_TICK, address 0x4000_8030).
Description
Bits
[3]
RTC Timer Wakeup CPU Function Enable Bit
If TWKEN is set before CPU is in power-down mode, when a RTC Time-Tick or Alarm
Match occurs, CPU will wake up.
TWKEN
0= Disable Wakeup CPU function.
1= Enable the Wakeup function.
Time Tick Register
The RTC time tick period for Periodic Time-Tick Interrupt request.
Time Tick (second) : 1 / (2^TICKSEL)
[2:0]
TICKSEL
Note: This register can be read back after the RTC is active.
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5.9 Serial Peripheral Interface (SPI) Controller
5.9.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-directional
interface. The ISD9160 contains an SPI controller performing a serial-to-parallel conversion of data
received from an external device, and a parallel-to-serial conversion of data transmitted to an external
device. The SPI controller can be set as a master with up to 2 slave select (SSB) address lines to
access two slave devices; it also can be set as a slave controlled by an off-chip master device.
5.9.2 Features
Supports master or slave mode operation.
Supports one or two channels of serial data.
Configurable word length of up to 32 bits. Up to two words can be transmitted per a transaction,
giving a maximum of 64 bits for each data transaction.
Provide burst mode operation.
MSB or LSB first transfer.
2 device/slave select lines in master mode, single device/slave select line in slave mode.
Byte or word Sleep Suspend Mode .
Support dual FIFO mode.
PDMA access support.
5.9.3 SPI Block Diagram
Clock Generator
SPI_SCLK
SPI_SSB0
SPI_SSB1
SPI_MOSI0
SPI_MOSI1
SPI_MISO0
SPI_MISO1
APB
IF
(32-bits)
Status/Control
Register
Core Logic
PIO
TX Bufer/
Shifter
PDMA
Control
RX Bufer/
Shifter
Figure 5-34 SPI Block Diagram
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5.9.4
SPI Function Descriptions
Master/Slave Mode
This SPI controller can be configured as in master or slave mode by setting the SLAVE bit
(SPI_CTL.SLAVE). In master mode the ISD9160 generates SCLK and SSB signals to access one or
more slave devices. In slave mode the ISD9160 monitors SCLK and SSB signals to respond to data
transactions from an off-chip master. The signal directions are summarized in the application block
diagrams of Figure 5-35 and Figure 5-36.
SCLK
MISO
MOSI
SS
SCLK
MISO
Slave 0
ISD9160
SPI Controller MOSI
Master
SSB0
SSB1
SCLK
MISO
MOSI
SS
Slave 1
Figure 5-35 SPI Master Mode Application Block Diagram
SCLK
MISO
MOSI
SS
SCLK
MISO
Master
ISD9160
SPI Controller MOSI
Slave
SSB0
SSB1
Figure 5-36 SPI Slave Mode Application Block Diagram
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Slave Select
In master mode, the SPI controller can address up to two off-chip slave devices through the slave
select output pins SPI_SSB0 and SPI_SSB1. Only one slave can be addressed at any one time. If
more slave address lines are required, GPIO pins can be manually configured to provide additional
SSB lines. In slave mode, the off-chip master device drives the slave select signal SPI_SSB0 to
address the SPI controller. The slave select signal can be programmed to be active low or active high
via the SPI_SSCTL.SSACTPOL bit. In addition the SPI_SSCTL.LVTRGEN bit defines whether the
slave select signals are level triggered or edge triggered. The selection of trigger condition depends on
what type of peripheral slave/master device is connected.
Automatic Slave Select
In master mode, if the bit SPI_SSCTL.AUTOSS is set, the slave select signals will be generated
automatically and output to SPI_SSB0 and SPI_SSB1 pins according to registers SPI_SSCTL.SS[0]
and SPI_SSCTL.SS[1]. In this mode, SPI controller will assert SSB when transaction is triggered and
de-assert when data transfer is finished. If the SPI_SSCTL.AUTOSS bit is cleared, the slave select
output signals are asserted and de-asserted by manual setting and clearing the related bits in the
SPI_SSCTL.SS[1:0] register. The active level of the slave select output signals is specified by the
SPI_SSCTL. SSACTPOL bit.
Serial Clock
In master mode, writing a divisor into the SPI_CLKDIV.DIVIDER0 register will program the output
frequency of serial clock to the SPI_SCLK output port. In slave mode, the off-chip master device
drives the serial clock through the SPI_SCLK.
Clock Polarity
The SPI_CTL.CLKPOL bit defines the serial clock idle state in master mode. If CLKPOL = 1, the
output SPI_SCLK is high in idle state. If CLKPOL=0,it is low in idle state.
Transmit/Receive Bit Length
The bit length of a transfer word is defined in SPI_CTL.DWIDTH bit field. It is set to define the length
of a transfer word and can be up to 32 bits in length. DWIDTH=0x0 enables 32bit word length.
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Burst Mode
The SPI controller has a burst mode controlled by the SPI_CTL.TXCNT field. If set to 0x01, SPI
controller will burst two transactions from the SPI_TX0 and SPI_TX1 registers as shown in the
waveform below:
Word suspend
CLK =0
SPICLK
CLK =1
MS
Tx0[31]
LSB
Tx1[0]
Tx0[30]
Rx0[30]
Tx0[0]
Rx0[0]
Tx1[31]
Rx1[31]
Tx1[30]
Rx1[30]
MISO
MOSI
MS
Rx0[31]
LSB
Rx1[0]
2
nd Transaction Word
1st Transaction Word
Figure 5-37 Two Transactions in One Transfer (Burst Mode)
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LSB First
The SPI_CTL.LSB bit defines the bit order of data transmission. If LSB=0 then MSB of transfer word
is sent first in time. If LSB=1 then LSB of transfer word is sent first in time.
Transmit Edge
The SPI_CTL.TXNEG bit determines whether transmit data is changed on the positive or negative
edge of the SPI_SCLK serial clock. If TXNEG=0 then transmitted data will change state on the rising
edge of SPI_SCLK. If TXNEG=1 then transmitted data will change state on the falling edge of
SPI_SCLK.
Receive Edge
The SPI_CTL.RXNET bit determines whether data is received at either the negative edge or positive
edge of serial clock SPI_SCLK. If RXNET=1 then data is clocked in on the falling edge of SPI_SCLK.
If RXNET=0 data is clocked in on the rising edge of SPI_SCLK. Note that RXNET should be the
inverse of TXNEG for standard SPI operation.
Word Sleep Suspend
The bit field SPI_CTL.SUSPITV provides a configurable suspend interval of SUSPITV+2 serial clock
periods between successive word transfers in master mode. The suspend interval is from the last
falling clock edge of the preceding transfer word to the first rising clock edge of the following transfer
word if CLKPOL = 0. If CLKPOL = 1, the interval is from the rising clock edge of the preceding transfer
word to the falling clock edge of the following transfer word. The default value of SUSPITV is 0x0 (2
serial clock cycles). Word Sleep only occurs when TXCNT=1. For TXCNT=0, this parameter will
determine a Byte Sleep condition if the BYTEITV bit is set.
Word
Sleep
CLKP=0
SPICLK
CLKP=1
MSB
Tx0[31]
LSB
Tx1[0]
Tx0[30]
Rx0[30]
Tx0[0]
Rx0[0]
Tx1[31]
Rx1[31]
Tx1[30]
Rx1[30]
MISO
MOSI
MSB
Rx0[31]
LSB
Rx1[0]
2nd Transfer Word
1st Transfer Word
Figure 5-38 Word Sleep Suspend Mode
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Byte Endian
APB access to the SPI controller is via the 32bit wide TX and RX registers. When the transfer is set as
MSB first ( SPI_CTL.LSB = 0) and the SPI_CTL.REORDER bit is set, the data stored in the TX buffer
and RX buffer will be rearranged such that the least significant physical byte is processed first. For
DWIDTH =0 (32 bits transfer), the sequence of transmitted/received data will be BYTE0, BYTE1,
BYTE2, and then BYTE3. If DWIDTH is set to 24-bits, the sequence will be BYTE0, BYTE1, and
BYTE2. The rule of 16-bits mode is the same as above, see Figure 5-39.
BYTE_ENDIAN = 1
BYTE_ENDIAN = 0
SPI->TX[0]/SPI->RX[0]
TX/RX Buffer
TX/RX Buffer
MSB first
MSB first
MSB first
LSB = 0 (MSB first)
Byte3 Byte2 Byte1 Byte0
[31:24] [23:16] [15:8] [7:0]
Byte0 Byte1 Byte2 Byte3
TX_BIT_LEN = 32 bits
MSB first
Byte3 Byte2 Byte1 Byte0
TX_BIT_LEN = 32 bits
MSB first
N/A Byte0 Byte1 Byte2
N/A Byte2 Byte1 Byte0
TX_BIT_LEN = 24 bits
TX_BIT_LEN = 24 bits
MSB first
MSB first
N/A
N/A Byte0 Byte1
N/A
N/A Byte1 Byte0
TX_BIT_LEN = 16 bits
TX_BIT_LEN = 16 bits
MSB first
MSB first
N/A
N/A
N/A Byte0
N/A
N/A
N/A Byte0
TX_BIT_LEN = 8 bits
TX_BIT_LEN = 8 bits
Time
Figure 5-39 Byte Re-Ordering Transfer
Byte ordering can be a confusing issue when converting from arrays of data processed by the CPU for
transmission out the SPI port. The CortexM0 stores data in a little endian format; that is the LSB of a
multi-byte word or half-word are stored first in memory. Consider how the CortexM0 stores the
following arrays in memory:
1. unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
2. unsigned int uiSPI_DATA[]={0x01020304, 0x05060708};
unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
unsigned int uiSPI_DATA[]={0x01020304, 0x05060708};
RAM Address
RAM Contents
Byte0 Byte1 Byte2 Byte3
0x20000014
0x20000010
0x2000000c
0x20000008
0x20000004
Byte0 Byte1 Byte2 Byte3
0x08 0x07 0x06 0x05
0x04 0x03 0x02 0x01
0x05 0x06 0x07 0x08
0x01 0x02 0x03 0x04
uiSPI_DATA[]→
ucSPI_DATA[]→
0x20000000
APB Data Bus
[7:0]
[15:8] [23:16] [31:24]
Figure 5-40 Byte Order in Memory
It can be seen from Figure 5-40 that byte order for an array of bytes is different than that of an array of
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words. Now consider if this data were to be sent to the SPI port; the user could:
1. Set DWIDTH=8 and send data byte-by-byte SPI_TX0 = ucSPI_DATA[i++]
2. Set DWIDTH=32 and send word-by-word SPI_TX0 = uiSPI_DATA[i++]
Both of these would result in the byte stream {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08} being
sent.
It would be common that a byte array of data is constructed but user, for efficiency, wishes to transfer
data to SPI via word transfers. Consider the situation of Figure 5-41 where a int pointer points to the
byte data array.
unsigned char ucSPI_DATA[]={0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
unsigned int *uiSPI_DATA = (unsigned int *)ucSPI_DATA[];
RAM Address
RAM Contents
Byte0 Byte1 Byte2 Byte3
Byte0 Byte1 Byte2 Byte3
0x08 0x07 0x06 0x05
0x04 0x03 0x02 0x01
0x05 0x06 0x07 0x08
0x01 0x02 0x03 0x04
0x20000014
0x20000010
0x2000000c
0x20000008
0x20000004
0x20000000
ucSPI_DATA[]→
APB Data Bus
Figure 5-41 Byte Order in Memory
uiSPI_DATA[]→
[7:0]
[15:8] [23:16] [31:24]
Now if we set DWIDTH=32 and sent word-by-word SPI_TX0 = uiSPI_DATA[i++], the order
transmitted would be {0x04, 0x03, 0x02, 0x01, 0x08, 0x07, 0x06, 0x05}. However if we set
REORDER=1, we would reverse this order to the desired stream: {0x01, 0x02, 0x03, 0x04, 0x05,
0x06, 0x07, 0x08}.
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Byte Sleep Suspend
In master mode, if SPI_CTL.BYTEITV is set to 1, the hardware will insert a suspend interval of
SPI_CTL.SUSPITV+2 serial clock periods between two successive bytes in a transfer word. Note that
the byte suspend function is only valid for 32bit word transfers, that is DWIDTH=0x00.
Byte
Byte
Sleep
Sleep
CLKP=0
CLKP=1
SPICLK
MSB
Tx0[31]
Tx0[30]
Rx0[30]
Tx0[24]
Rx0[24]
Tx0[23]
Rx0[23]
Tx0[22]
Rx0[22]
Tx0[16]
Rx0[16]
MISO
MOSI
MSB
Rx0[31]
2nd Transfer Byte
1st Transfer Byte
Transfer Word
Figure 5-42 Byte Suspend Mode
Interrupt
The SPI controller can generate a CPU interrupt when data transfer is finished. When a transfer
request triggered by BUSY is finished, the interrupt flag ( SPI_CTL.UNITIF) will be set by hardware. If
the SPI interrupt is enabled ( SPI_CTL.UNITIEN) this will also generate a CPU interrupt. To clear the
interrupt event flag, software must write a ‘1’ to it.
FIFO Mode
The SPI controller supports a dual buffer mode when SPI_CTL.FIFOEN is set as 1. In normal mode,
software can only update the transmitted data when the current transmission is done. In FIFO mode,
the next transmitted data can be written into the SPI_TX buffer at any time when in master mode or
the BUSY bit is set in slave mode. This data will load into the transmit buffer when the current
transmission done.
After the FIFO bit is set, transmission is repeated automatically when the transmitted data is updated
in time and it will continue until this bit is cleared. When cleared, the transmission will finish when the
current transmission done. The user can also read the received data at any time before the next
transmission is complete, wherein the receive buffer will be updated with new received data. If
transmit data isn’t updated before the current transmission is done, the transaction will stop. The
transmission will resume automatically when transmit data is written into this buffer again.
Before the FIFO bit is set, the user can write first data into SPI_TX buffer. Setting FIFO active will load
the first data into the current transmission buffer. A subsequent write to SPI_TX will load the TX FIFO
which will be loaded into the transmission buffer after the 1st transmission is done.
This function is also supported in slave mode. The BUSY must be set as 1 before the external serial
clock input and it will keep going until the FIFO is cleared.
The delay period between two transmissions is programmable. It is the same as the suspend interval
on SUSPITV parameter.
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Two Channel Mode
The SPI controller supports a two channel mode where data can be sent and received on alternate
MOSI1 and MISO1 lines concurrently with data on MOSI0 and MISO0. The data for this second
channel is the SPI_RX1 and SPI_TX1 buffers. Mode is enabled by setting the SPI_CTL.TWOBIT bit.
This mode is only available when TXCNT=0.
SS_LVL=1
SPI_SS
SS_LVL=0
CLKP=0
SPICLK
CLKP=1
MSB
Tx0[31]
LSB
Tx0[0]
Tx0[30]
Rx0[30]
Tx1[30]
Rx1[30]
Tx0[16]
Rx0[16]
Tx1[16]
Rx1[16]
Tx0[15]
Rx0[15]
Tx1[15]
Rx1[15]
Tx0[14]
Rx0[14]
Tx1[14]
Rx1[14]
MISOx0
MOSIx0
MISOx1
MOSIx1
MSB
Rx0[31]
LSB
Rx0[0]
MSB
Tx1[31]
LSB
Tx1[0]
MSB
Rx1[31]
LSB
Rx1[0]
Figure 5-43 Two Bits Transfer Mode
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Variable Serial Clock Frequency
In master mode 16 bit transfers, the output of serial clock can be programmed as variable frequency
pattern if the Variable Clock Enable bit SPI_CTL.VARCLKEN is enabled. The frequency pattern
format is defined in SPI_VARCLK register. If the bit content of VARCLK is ‘0’ the output period for that
bit is determined by setting of SPI_CLKDIV.DIVIDER0, if the bit content of VARCLK is ‘1’, the output
period for that bit is determined by the SPI_CLKDIV.DIVIDER1 register. The following figure shows
the timing relationships of serial clock (SCLK), to the VARCLK, the DIVIDER0 and the DIVIDER1
registers. A two-bit combination in the VARCLK defines one clock cycle. The bit field VARCLK[31:30]
defines the first clock cycle of SCLK. The bit field VARCLK[29:28] defines the second clock cycle of
SCLK and so on. The clock source selections are defined in SPI_VARCLK and must be set 1 cycle
before the next clock option. For example, if there are 5 CLK1 cycle in SPICLK, the SPI_VARCLK
shall set 9 ‘0’ in the MSB of SPI_VARCLK. The 10th shall be set as ‘1’ in order to switch the next clock
source is CLK2. Note that when VARCLKEN bit is set, the setting of DWIDTH must be programmed
as 0x10 (16 bits mode only).
SPICLK
VARCLK
00000000011111111111111110000111
CLK1 (DIV)
CLK2 (DIV2)
Figure 5-44 Variable Serial Clock Frequency
5.9.5 SPI Timing Diagram
In master/slave mode, the device address/slave select (SPI_SSB0/1) signal can be configured as
active low or active high by the SPI_SSCTL.SSACTPOL bit. In slave mode, the
SPI_SSCTL.LVTRGEN will determine whether the slave select signal is treated as a level triggered
or edge triggered signal.
The serial clock phase and polarity is controlled by CLKPOL, RXNET and TXNEG bits. The bit length
of a transfer word is configured by the DWIDTH parameter. Whether data transmission is MSB first or
LSB first is controlled by the SPI_CTL.LSB bit. Four examples of SPI timing diagrams for master/slave
operations and the related settings are shown as below.
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SS_LVL=1
SS_LVL=0
SPI_SS
CLKP=0
SPICLK
CLKP=1
MSB
Tx0[7]
LSB
Tx0[0]
Tx0[6]
Rx0[6]
Tx0[5]
Rx0[5]
Tx0[4]
Rx0[4]
Tx0[3]
Rx0[3]
Tx0[2]
Rx0[2]
Tx0[1]
Rx0[1]
MOSI
MISO
MSB
Rx0[7]
LSB
Rx0[0]
Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08
1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0 or
2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1
Figure 5-45 SPI Timing in Master Mode
SS_LVL=1
SS_LVL=0
SPI_SS
CLKP=0
SPICLK
CLKP=1
LSB
Tx0[0]
MSB
Tx0[7]
Tx0[1]
Rx0[1]
Tx0[2]
Rx0[2]
Tx0[3]
Rx0[3]
Tx0[4]
Rx0[4]
Tx0[5]
Rx0[5]
Tx0[6]
Rx0[6]
MOSI
LSB
Rx0[0]
MSB
Rx0[7]
MISO
Master Mode: CNTRL[SLVAE]=0, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08
1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1 or
2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0
Figure 5-46 SPI Timing in Master Mode (Alternate Phase of SPICLK)
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SS_LVL=1
SS_LVL=0
SPI_SS
CLKP=0
SPICLK
CLKP=1
MSB
Tx0[7]
LSB
Tx1[0]
Tx0[6]
Rx0[6]
Tx0[0]
Rx0[0]
Tx1[7]
Rx1[7]
Tx1[6]
Rx1[6]
MISO
MOSI
MSB
Rx0[7]
LSB
Rx1[0]
Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x01, CNTRL[Tx_BIT_LEN]=0x08
1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0 or
2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1
Figure 5-47 SPI Timing in Slave Mode
SS_LVL=1
SS_LVL=0
SPI_SS
CLKP=0
SPICLK
CLKP=1
LSB
Tx0[0]
MSB
Tx1[7]
Tx0[1]
Rx0[1]
Tx0[7]
Rx0[7]
Tx1[0]
Rx1[0]
Tx1[6]
Rx1[6]
MISO
LSB
Rx0[0]
MSB
Rx1[7]
MOSI
Slave Mode: CNTRL[SLVAE]=1, CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x01, CNTRL[Tx_BIT_LEN]=0x08
1. CNTRL[CLKP]=0, CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1 or
2. CNTRL[CLKP]=1, CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0
Figure 5-48 SPI Timing in Slave Mode (Alternate Phase of SPICLK)
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5.9.6 SPI Configuration Examples
Example 1, SPI controller is set as a master to access an off-chip slave device with following
specifications:
Data bit latched on positive edge of serial clock
Data bit driven on negative edge of serial clock
Data be transferred from MSB first
SCLK low in idle state
Only one byte data be transmitted/received in a transfer
Slave select signal is active low
SCLK frequency is 10MHz
To configure the SPI interface to the above specifications perform the following steps:
1) Write a divisor into the SPI_CLKDIV register to determine the output frequency of serial clock.
Driver function DrvSPI_SetClock(0,10000000,0) can be used to achieve this.
2) Configure the SPI_SSCTL register to address device. For example to manually address, set SPI-
SPI_SSCTL.AUTOSS=0, SPI_SSCTL.SS_LVL=0 for active low SS. When software wishes to
address device it will set SPI_SSCTL.SS=1 to output an active SS on SPI_SSB0 pin.
3) Configure the SPI_CTL register. Set SPI_CTL.SLAVE=0 for master mode, set
SPI_CTL.CLKPOL=0 for SCLK polarity normally low, set SPI_CTL.TXNEG=1 so that data
changes on falling edge of SCLK, set SPI_CTL.RXNET=0 so that data is latched into device on
positive edge of SCLK, set SPI_CTL.DWIDTH=8 and SPI_CTL.TXCNT=0 for a single byte
transfer and finally set SPI_CTL.LSB=0 for MSB first transfer.
4) If manually selecting slave device set SPI_SSCTL.SS=1.
5) To transmit one byte of data, write data to SPI_TX0 register. If only doing a receive, write a
dummy byte to SPI_TX0 register.
6) Enable the SPI_CTL.BUSY bit to start the data transfer over the SPI interface.
-- Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI_CTL.UNITIEN bit
is set) or by polling the BUSY bit which will be cleared to 0 by hardware automatically at end of
transmission. --
7) Read out the received one byte data from SPI_RX0
8) Go to 5) to continue another data transfer or set SPI_SSCTL.SS=0 to deactivate the off-chip
slave devices.
Example 2, SPI controller is set as a slave device that controlled by an off-chip master device
with the following characteristics:
Data bit latched on positive edge of serial clock
Data bit driven on negative edge of serial clock
Data be transferred from LSB first
SCLK high in idle state
Only one byte data be transmitted/received in a transfer
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Slave select signal is active high level trigger
To configure the SPI interface to the above specifications perform the following steps:
1) Configure the SPI_SSCTL register. SPI_SSCTL.SSACTPOL=1 for active high slave select,
SPI_SSCTL.LVTRGEN=1 for level sensitive trigger.
2) Configure the SPI_CTL register. Set SPI_CTL.SLAVE=1 for slave mode, set
SPI_CTL.CLKPOL=1 for SCLK polarity idle high, set SPI_CTL.TXNEG=1 so that data changes
on falling edge of SCLK, set SPI_CTL.RXNET=0 so that data is latched into device on positive
edge of SCLK, set SPI_CTL.DWIDTH=8 and SPI_CTL.TXCNT=0 for a single byte transfer and
finally set SPI_CTL.LSB=1 for LSB first transfer.
3) If SPI slave is to transmit one byte of data to the off-chip master device, write first byte to SPI_TX0
register. If no data to be transmitted write a dummy byte.
4) Enable the BUSY bit to wait for the slave select trigger input and serial clock input from the off-
chip master device to start the data transfer at the SPI interface.
-- -- Wait for SPI transfer to finish. Can be interrupt driven (if the interrupt enable SPI_CTL.UNITIEN
bit is set) or by polling the BUSY bit which will be cleared to 0 by hardware automatically at end of
transmission. --
5) Read out the received data from SPI_RX0 register.
6) Go to 3) to continue another data transfer or disable the BUSY bit to stop data transfer.
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5.9.7 SPI Serial Interface Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
SPI0 Base Address:
SPI0_BA = 0x4003_0000
SPI_CTL
SPI0_BA + 0x00 R/W
SPI0_BA + 0x04 R/W
SPI0_BA + 0x08 R/W
Control and Status Register
0x0000_0004
SPI_CLKDIV
SPI_SSCTL
SPI_RX0
Clock Divider Register (Master Only) 0x0000_0000
Slave Select Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x007F_FF87
0x0000_0000
SPI0_BA + 0x10
SPI0_BA + 0x14
SPI0_BA + 0x20
SPI0_BA + 0x24
R
Data Receive Register 0
Data Receive Register 1
Data Transmit Register 0
Data Transmit Register 1
Variable Clock Pattern Register
SPI DMA Control Register
SPI_RX1
R
SPI_TX0
W
W
SPI_TX1
SPI_VARCLK
SPI_PDMACTL
SPI0_BA + 0x34 R/W
SPI0_BA + 0x38 R/W
NOTE 1: When software programs SPI_CTL, the BUSY bit should be written last.
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5.9.8
SPI Control Register Description
SPI Control and Status Register (SPI_CTL)
Register
SPI_CTL
Offset
R/W
Description
Reset Value
SPI0_BA + 0x00 R/W
Control and Status Register
0x0000_0004
31
23
30
Reserved
22
29
28
PDMASSEN
20
27
TXFULL
19
26
TXEMPTY
18
25
RXFULL
17
24
RXEMPTY
16
21
FIFOEN
13
VARCLKEN
TWOBIT
14
REORDER
12
BYTEITV
11
SLAVE
10
UNITIEN
9
UNITIF
8
15
SUSPITV
CLKPOL
3
LSB
TXNUM
7
6
5
4
2
1
0
DWIDTH
TXNEG
RXNET
GOBUSY
Table 5-84 SPI Control and Status Register (SPI_CTL, address 0x4003_0000)
Bits
Description
[31:28]
[28]
Reserved
Reserved
Enable DMA Automatic SS function
PDMASSEN
When enabled, interface will automatically generate a SS signal for an entire PDMA
access transaction.
Transmit FIFO Full Status
0 = The transmit data FIFO is not full.
[27]
[26]
[25]
[24]
TXFULL
1 = The transmit data FIFO is full.
Transmit FIFO Empty Status
0 = The transmit data FIFO is not empty.
TXEMPTY
RXFULL
RXEMPTY
1 = The transmit data FIFO is empty.
Receive FIFO Full Status
0 = The receive data FIFO is not full.
1 = The receive data FIFO is full.
Receive FIFO Empty Status
0 = The receive data FIFO is not empty.
1 = The receive data FIFO is empty.
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Variable Clock Enable (Master Only)
0 = The serial clock output frequency is fixed and determined only by the value of
DIVIDER0.
[23]
VARCLKEN
1 = SCLK output frequency is variable. The output frequency is determined by the
value of SPI_VARCLK, DIVIDER0, and DIVIDER1.
Note that when enabled, the setting of DWIDTH must be programmed as 0x10 (16 bits
mode)
Two Bits Transfer Mode
0 = Disable two-bit transfer mode.
1 = Enable two-bit transfer mode.
[22]
TWOBIT
Note that when enabled in master mode, MOSI0 data comes from SPI_TX0 and
MOSI1 data from SPI_TX1. Likewise SPI_RX0 receives bit stream from MISO0 and
SPI_RX1 from MISO1. Note that when enabled, the setting of TXCNT must be
programmed as 0x00
FIFO Mode
0 = No FIFO present on transmit and receive buffer.
[21]
[20]
[19]
FIFOEN
1 = Enable FIFO on transmit and receive buffer.
Byte Endian Reorder Function
REORDER
BYTEITV
This function changes the order of bytes sent/received to be least significant physical
byte first.
Insert Sleep Interval Between Bytes
This function is only valid for 32bit transfers (DWIDTH aaa 0). If set then a pause of
(SUSPITV+2) SCLK cycles is inserted between each byte transmitted.
Master Slave Mode Control
0 = Master mode.
[18]
[17]
SLAVE
1 = Slave mode.
Interrupt Enable
UNITIEN
0 = Disable SPI Interrupt.
1 = Enable SPI Interrupt to CPU.
Interrupt Flag
0 = Indicates the transfer is not finished yet.
1 = Indicates that the transfer is complete. Interrupt is generated to CPU if enabled.
NOTE: This bit is cleared by writing 1 to itself.
[16]
UNITIF
Suspend Interval (Master Only)
These four bits provide configurable suspend interval between two successive
transmit/receive transactions in a transfer. The suspend interval is from the last falling
clock edge of the current transaction to the first rising clock edge of the successive
transaction if CLKPOL aaa 0. If CLKPOL aaa 1, the interval is from the rising clock
edge to the falling clock edge. The default value is 0x0. When TXCNT aaa 00b,
setting this field has no effect on transfer except as determined by REORDER[0]
setting. The suspend interval is determined according to the following equation:
[15:12]
SUSPITV
(SUSPITV[3:0] + 2) * period of SCLK
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Clock Polarity
[11]
[10]
CLKPOL
0 = SCLK idle low.
1 = SCLK idle high.
LSB First
0 = The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1
register that is depends on the DWIDTH field).
LSB
1 = The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from
the line will be put in the LSB position in the Rx register (bit 0 of SPI_RX0/1).
Transmit/Receive Word Numbers
This field specifies how many transmit/receive word numbers should be executed in
one transfer.
00 = Only one transmit/receive word will be executed in one transfer.
01 = Two successive transmit/receive word will be executed in one transfer.
10 = Reserved.
[9:8]
TXNUM
11 = Reserved.
Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32
bits can be transmitted.
DWIDTH aaa 0x01 --- 1 bit
DWIDTH aaa 0x02 --- 2 bits
----
[7:3]
DWIDTH
DWIDTH aaa 0x1f --- 31 bits
DWIDTH aaa 0x00 --- 32 bits
Transmit At Negative Edge
[2]
[1]
TXNEG
RXNET
0 = The transmitted data output signal is changed at the rising edge of SCLK.
1 = The transmitted data output signal is changed at the falling edge of SCLK.
Receive At Negative Edge
0 = The received data input signal is latched at the rising edge of SCLK.
1 = The received data input signal is latched at the falling edge of SCLK.
Go and Busy Status
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit starts the transfer. This bit remains set during the transfer and
is automatically cleared after transfer finished.
[0]
GOBUSY
NOTE: All registers should be set before writing 1 to this BUSY bit. When a transfer is
in progress, writing to any register of the SPI master/slave core has no effect.
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SPI Divider Register (SPI_CLKDIV)
Register
Offset
R/W
Description
Reset Value
SPI_CLKDIV
SPI0_BA + 0x04 R/W
Clock Divider Register (Master Only)
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
11
26
18
10
2
25
17
9
24
16
8
DIVIDER1[15:8]
20
12
DIVIDER1[7:0]
DIVIDER0[15:8]
4
3
1
0
DIVIDER0[7:0]
Table 5-85 SPI Clock Divider Register (SPI_CLKDIV, address 0x4003_0004)
Description
Bits
Clock Divider 2 Register (master only)
The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate
the serial clock on the output SCLK. The desired frequency is obtained according to the
following equation:
[31:16]
DIVIDER1
Fsclk aaa Fpclk / ((DIVIDER1+1) * 2)
Clock Divider Register (master only)
The value in this field is the frequency division of the system clock, PCLK, to generate the
serial clock on the output SCLK. The desired frequency is obtained according to the
following equation:
Fsclk aaa Fpclk / ((DIVIDER0+1) * 2)
[15:0]
DIVIDER0
In slave mode, the period of SPI clock driven by a master shall satisfy
Fsclk < aaa (Fpclk / 5)
In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral
clock.
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SPI Slave Select Register (SPI_SSCTL)
Register
Offset
R/W
Description
Reset Value
SPI_SSCTL
SPI0_BA + 0x08 R/W
Slave Select Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
LVTRGSTS
LVTRGEN
AUTOSS
SSACTPOL
SS[1:0]
Table 5-86 SPI Slave Select Register (SPI_SSCTL, address 0x4003_0008)
Bits
Description
Reserved
Reserved
[31:6]
Level Trigger Flag
When the LVTRGEN bit is set in slave mode, this bit can be read to indicate the
received bit number is met the requirement or not.
0=One of the received number and the received bit length doesn’t meet the
requirement in one transfer.
[5]
LVTRGSTS
1=The received number and received bits met the requirement which defines in
TXCNT and DWIDTH among one transfer.
Note: This bit is READ only
Slave Select Level Trigger (Slave only)
0= The input slave select signal is edge-trigger. This is the default value.
[4]
[3]
LVTRGEN
AUTOSS
1= The slave select signal will be level-trigger. It depends on SSACTPOL to decide
the signal is active low or active high.
Automatic Slave Select (Master only)
0 = If this bit is cleared, slave select signals are asserted and de-asserted by setting
and clearing related bits in SPI_SSCTL[1:0] register.
1 = If this bit is set, SPISSx0/1 signals are generated automatically. It means that
device/slave select signal, which is set in SPI_SSCTL[1:0] register is asserted by the
SPI controller when transmit/receive is started by setting BUSY, and is de-asserted
after each transmit/receive is finished.
Slave Select Active Level
It defines the active level of device/slave select signal (SPISSx0/1).
0 = The slave select signal SPISSx0/1 is active at low-level/falling-edge.
1 = The slave select signal SPISSx0/1 is active at high-level/rising-edge.
[2]
SSACTPOL
Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper
SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate
SPISSx0/1 line to be automatically driven to active state for the duration of the
transmit/receive, and will be driven to inactive state for the rest of the time. (The active
level of SPISSx0/1 is specified in SSACTPOL).
[1:0]
SS
Note: SPISSx0 is always defined as device/slave select input signal in slave mode.
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SPI Data Receive Register (RX)
Register
SPI_RX0
SPI_RX1
Offset
R/W
R
Description
Reset Value
SPI0_BA + 0x10
SPI0_BA + 0x14
Data Receive Register 0
Data Receive Register 1
0x0000_0000
0x0000_0000
R
Table 5-87 SPI Data Receive Register (SPI_RX0/SPI_RX1, address 0x4003_0010/0x4003_0014)
Bits
Description
Data Receive Register
The Data Receive Registers hold the value of received data of the last executed
transfer. Valid bits depend on the transmit bit length field in the SPI_CTL register. For
example, if DWIDTH is set to 0x08 and TXCNT is set to 0x0, bit Rx0[7:0] holds the
[31:0]
RX
received data.
NOTE: The Data Receive Registers are read only registers.
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SPI Data Transmit Register (TX)
Register
SPI_TX0
SPI_TX1
Offset
R/W
W
Description
Reset Value
0x0000_0000
0x0000_0000
SPI0_BA + 0x20
SPI0_BA + 0x24
Data Transmit Register 0
Data Transmit Register 1
W
Table 5-88 SPI Data Transmit Register (SPI_TX0/SPI_TX1, address 0x4003_0020/0x4003_0024)
Bits
Description
Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid
bits depend on the transmit bit length field in the SPI_CTL register. For example, if
DWIDTH is set to 0x08 and the TXCNT is set to 0x0, the bit TX0[7:0] will be
[31:0]
TX
transmitted in next transfer. If DWIDTH is set to 0x00 and TXCNT is set to 0x1, the
core will perform two 32-bit transmit/receive successive using the same setting (the
order is TX0[31:0], TX1[31:0]).
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SPI Variable Clock Pattern Flag Register (SPI_VARCLK)
Register
Offset
R/W Description
Reset Value
SPI_VARCLK
SPI0_BA + 0x34
R/W Variable Clock Pattern Register
0x007F_FF87
Table 5-89 SPI Variable Clock Pattern Register (SPI_VARCLK, address 0x4003_0034)
Bits
Description
Variable Clock Pattern
The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK
is ‘0’, the output frequency of SCLK is given by the value of DIVIDER0. If the bit field of
VARCLK is ‘1’, the output frequency of SCLK is given by the value of DIVIDER1. Refer to
register DIVIDER0.
[31:0]
VARCLK
Refer to Variable Serial Clock Frequency paragraph for detailed description.
Note: Used for CLKPOL = 0 only, 16 bit transmission.
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DMA Control Register (SPI_PDMACTL)
Register
Offset
R/W
Description
Reset Value
SPI_PDMACTL
SPI0_BA + 0x38 R/W
SPI DMA Control Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
RXPDMAEN
TXPDMAEN
Table 5-90 SPI DMA Control Register (SPI_PDMACTL, address 0x4003_0038)
Bits
[1]
Description
Receive DMA Start
RXPDMAEN
Set this bit to 1 will start the receive DMA process. SPI module will issue request to
DMA module automatically.
Transmit DMA Start
Set this bit to 1 will start the transmit DMA process. SPI module will issue request to
DMA module automatically.
[0]
TXPDMAEN
If using DMA mode to transfer data, remember not to set BUSY bit of SPI_CTL
register. The DMA controller inside SPI module will set it automatically whenever
necessary.
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5.10 Timer Controller
5.10.1 General Timer Controller
The ISD9160 provides two general 24bit timer modules, TIMER0 and TIMER1. They allow the user to
implement event counting or provide timing control for applications. The timer can perform functions
such as frequency measurement, event counting, interval measurement, clock generation and delay
timing. The timer can generates an interrupt signal upon timeout and provide the current value of
count during operation.
5.10.2 Features
Independent clock source for each channel (TMR0_CLK, TMR1_CLK).
Time out period = (Period of timer clock input) * (8-bit prescale + 1) * (24-bit CMPDAT)
Maximum count cycle time = (1 / TMR_CLK) * (2^8) * (2^24).
Internal 24-bit up counter is readable through TIMERx_CNT (Timer Data Register).
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5.10.3 Timer Controller Block Diagram
Each channel is equipped with an 8-bit pre-scale counter, a 24-bit up-counter, a 24-bit compare
register and an interrupt request signal. Refer to Figure 5-49 for the timer controller block diagram.
There are five options of clock source for each channel, Figure 5-50 illustrate the clock source control
function.
24-bit TDR
TCSR.CRST
latch TCSR.TDR_EN
Clear bit
Reset counter
TCSR.CEN
Reset counter in
MODE=00/01
TMRx_CLK
Timer Interrupt
TISR.TIF
8-bit Prescale
24-bit up-counter
24-bit TCMPR
SET
CLR
D
Q
Q
+
=
-
Figure 5-49 Timer Controller Block Diagram
SYSCLK->CLKSEL1.TMRx_S
SYSCLK->APBCLK.TMRx_EN
OSC48M
TMx(GPIO)
HCLK
1xx
011
010
001
000
TMRx_CLK
OSC32K
OSC10K
Figure 5-50 Clock Source of Timer Controller
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5.10.4 Timer Controller Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
TMR Base Address:
TMRn_BA=0x4001_0000+(0x20*n)
n=0,1
TIMERx_CTL
TIMERx_CMP
TIMERx_INTSTS
TIMERx_CNT
TMRn_BA+0x00 R/W
TMRn_BA+0x04 R/W
TMRn_BA+0x08 R/W
TMRn_BA+0x0C R/W
Timer Control and Status Register
Timer Compare Register
0x0000_0005
0x0000_0000
0x0000_0000
0x0000_0000
Timer Interrupt Status Register
Timer Data Register
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Timer Control Register (TIMERx_CTL)
Register
Offset
R/W
Description
Reset Value
TIMERx_CTL
TMRn_BA+0x00 R/W
Timer Control and Status Register
0x0000_0005
31
Reserved
23
30
CNTEN
22
29
INTEN
21
28
20
27
19
11
3
26
RSTCNT
18
25
ACTSTS
17
24
Reserved
16
OPMODE[1:0]
Reserved
12
CNTDATEN
8
15
7
14
6
13
5
10
2
9
1
Reserved
4
0
PSC[7:0]
Table 5-91 Timer Control and Status Register (TIMERx_CTL, address 0x4001_0000 + x *0x20).
Bits
[31]
Description
Reserved
Reserved
Counter Enable Bit
0 = Stops/Suspends counting
1 = Starts counting
[30]
CNTEN
Note1: Setting CNTEN aaa 1 enables 24-bit counter. It continues count from last
value.
Note2: This bit is auto-cleared by hardware in one-shot mode (OPMODE aaa 00b)
when the timer interrupt is generated (INTEN aaa 1b).
Interrupt Enable Bit
0 = Disable TIMER Interrupt.
1 = Enable TIMER Interrupt.
[29]
INTEN
If timer interrupt is enabled, the timer asserts its interrupt signal when the count is
equal to TIMERx_CMP.
Timer Operating Mode
0 = The timer is operating in the one-shot mode. The associated interrupt signal is
generated once (if INTEN is enabled) and CNTEN is automatically cleared by
hardware.
1 = The timer is operating in the periodic mode. The associated interrupt signal is
generated periodically (if INTEN is enabled).
[28:27]
OPMODE
2 = Reserved.
3 = The timer is operating in continuous counting mode. The associated interrupt
signal is generated when CNT = CMPDAT (if INTEN is enabled); however, the 24-bit
up-counter counts continuously without reset.
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Counter Reset Bit
Set this bit will reset the timer counter, prescale and also force CNTEN to 0.
0 = No effect.
[26]
RSTCNT
1 = Reset Timer’s prescale counter, internal 24-bit up-counter and CNTEN bit.
Timer Active Status Bit (Read only)
This bit indicates the counter status of timer.
0 = Timer is not active.
[25]
ACTSTS
1 = Timer is active.
[24:17]
Reserved
Reserved
Data Latch Enable
When CNTDATEN is set, TIMERx_CNT (Timer Data Register) will be updated
continuously with the 24-bit up-counter value as the timer is counting.
[16]
CNTDATEN
1 = Timer Data Register update enable.
0 = Timer Data Register update disable.
[15:8]
[7:0]
Reserved
Reserved
Pre-scale Counter
PSC
Clock input is divided by PSC+1 before it is fed to the counter. If PSC aaa 0, then
there is no scaling.
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Timer Compare Register (TIMERx_CMP)
Register
Offset
R/W
Description
Reset Value
TIMERx_CMP
TMRn_BA+0x04 R/W
Timer Compare Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
27
26
18
10
2
25
17
9
24
16
8
Reserved
19
CMPDAT[23:16]
12 11
CMPDAT [15:8]
4
3
1
0
CMPDAT[7:0]
Table 5-92 Timer Compare Register (TIMERx_CMP, address 0x4001_0004 + x * 0x20)
Bits
Description
Timer Comparison Value
CMPDAT is a 24-bit comparison register. When the 24-bit up-counter is enabled and
its value is equal to CMPDAT value, a Timer Interrupt is requested if the timer interrupt
is enabled with TIMERx_CTL.INTEN aaa 1. The CMPDAT value defines the timer
cycle time.
[24:0]
CMPDAT
Time out period aaa (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT)
NOTE1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.
NOTE2: Regardless of CNTEN state, whenever a new value is written to this register,
TIMER will restart counting using this new value and abort previous count.
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Timer Interrupt Status Register (TIMERx_INTSTS)
Register
Offset
R/W
Description
Reset Value
TIMERx_INTSTS
TMRn_BA+0x08 R/W
Timer Interrupt Status Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
TIF
Table 5-93 Timer Interrupt Status Register (TIMERx_INTSTS, address 0x4001_0008 + x * 0x20)
Bits
Description
[31:1]
Reserved
Reserved
Timer Interrupt Flag
This bit indicates the interrupt status of Timer.
[0]
TIF
TIF bit is set by hardware when the 24-bit counter matches the timer comparison
value (CMPDAT). It is cleared by writing 1.
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Timer Data Register (TIMERx_CNT)
Register
Offset
R/W
Description
Reset Value
TIMERx_CNT
TMRn_BA+0x0C R/W
Timer Data Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
20
CNT[23:16]
12
CNT[15:8]
4
1
0
CNT[7:0]
Table 5-94 Timer Data Register (TIMERx_CNT, address 0x4001_000C + x *0x20).
Bits
Description
[31:24]
Reserved
Reserved
Timer Data Register
[23:0]
CNT
When TIMERx_CTL.CNTDATEN is set to 1, the internal 24-bit timer up-counter value
will be latched into CNT. User can read this register for the up-counter value.
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5.11 Watchdog Timer
The purpose of Watchdog Timer is to perform a system reset if software is not responding as
designed. This prevents system from hanging for an infinite period of time. The watchdog timer
includes a 18-bit free running counter with programmable time-out intervals.
Setting WDTEN enables the watchdog timer and the WDT counter starts counting up. When the
counter reaches the selected time-out interval, Watchdog timer interrupt flag IF will be set immediately
to request a WDT interrupt if the watchdog timer interrupt enable bit INTEN is set, in the meantime, a
specified delay time follows the time-out event. User must set RSTCNT (Watchdog timer reset) high to
reset the 18-bit WDT counter to prevent Watchdog timer reset before the delay time expires. RSTCNT
bit is auto cleared by hardware after WDT counter is reset. There are eight time-out intervals with
specific delay time which are selected by Watchdog timer interval select bits TOUTSEL. If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (RSTF) high and reset CPU. This reset will last 64 WDT clocks then CPU
restarts executing program from reset vector (0x0000 0000). RSTF will not be cleared by Watchdog
reset. User may poll WTFR by software to recognize the reset source.
If the application uses any sleep modes (calling wfi or wfe instructions), the watchdog reset may not
fully reset the M0 core due to parts of the core being un-clocked. In this case application should detect
the RSTF in boot sequence and perform a Deep Power Down (DPD) to ensure complete reset. See
the Timer driver sample code for example.
Table 5-95 Watchdog Timeout Interval Selection
RSTCNT Timeout
Interval
(WDT_CLK=49.152
MHz)
RSTCNT Timeout
Interval
(WDT_CLK=32kHz)
Interrupt
Timeout
Watchdog Reset
Timeout
TOUTSEL
000
001
010
011
100
101
110
111
24 WDT_CLK
26 WDT_CLK
28 WDT_CLK
210 WDT_CLK
212 WDT_CLK
214 WDT_CLK
216 WDT_CLK
218 WDT_CLK
(24 + 1024) WDT_CLK
(26 + 1024) WDT_CLK
(28 + 1024) WDT_CLK
(210 + 1024) WDT_CLK
(212 + 1024) WDT_CLK
(214 + 1024) WDT_CLK
(216 + 1024) WDT_CLK
(218 + 1024) WDT_CLK
21.2 us
22.1 us
26.0 us
41.7 us
104.2 us
354.2 us
1.4 ms
31.7 ms
33.2 ms
39 ms
64 ms
160 ms
544 ms
2080 ms
8224 ms
5.4 ms
SYSCLK->CLKSEL1.WDG_S
SYSCLK->APBCLK.WDG_EN
10KHz
11
10
01
00
WDT_CLK
HCLK/2048
32K
OSC48M
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Figure 5-51 Watchdog Timer Clock Control
WTR
Reset WDT
Counter
Watchdog
Interrupt
WTIF
18-bit WDT Counter
WTIE
0
..
4
…...
15
16
17
000
001
:
Delay
1024
WDT
clocks
Time-
out
select
Watchdog
Reset[1]
:
110
111
WTRE
WDT_CLK
WTE
WTRF
WTIS
Note:
1. Watchdog timer resets CPU and lasts 64 WDT_CLK.
Figure 5-52 Watchdog Timer Block Diagram
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5.11.1 Watchdog Timer Control Registers Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
WDT Base Address:
WDT_BA = 0x4000_4000
WDT_CTL
WDT_BA+0x00
R/W
Watchdog Timer Control Register
0x0000_0700
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Watchdog Timer Control Register (WDT_CTL)
This is a protected register, to write to register, first issue the unlock sequence (see Protected Register Lock
Key Register (SYS_REGLCTL)). Only flag bits, IF and RSTF are unprotected and can be write-cleared at any
time.
Register
Offset
R/W
Description
Reset Value
WDT_CTL
WDT_BA+0x00
R/W
Watchdog Timer Control Register
0x0000_0700
31
23
15
30
22
14
29
21
28
20
12
4
27
19
11
26
18
10
25
17
24
16
8
Reserved
Reserved
13
Reserved
5
9
TOUTSEL
1
7
6
3
2
0
WDTEN
INTEN
Reserved
IF
RSTF
RSTEN
RSTCNT
Bits
Description
[31:11]
Reserved
Reserved
Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur
1024 clock cycles later if WDG not reset. The timeout is given by:
[10:8]
TOUTSEL
Interrupt Timeout aaa 2^(2xWTIS+4) x WDT_CLK
Reset Timeout aaa (2^(2xWTIS+4) +1024) x WDT_CLK
Where WDT_CLK is the period of the Watchdog Timer clock source.
Watchdog Timer Enable
[7]
[6]
WDTEN
INTEN
0 = Disable the Watchdog timer (This action will reset the internal counter)
1 = Enable the Watchdog timer
Watchdog Timer Interrupt Enable
0 = Disable the Watchdog timer interrupt
1 = Enable the Watchdog timer interrupt
Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the
Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit
indicates that a timeout period has elapsed.
[3]
IF
0 = Watchdog timer interrupt has not occurred.
1 = Watchdog timer interrupt has occurred.
NOTE: This bit is cleared by writing 1 to this bit.
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Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by
software to determine the source of reset. Software is responsible to clear it manually by writing 1
to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
[2]
RSTF
0 = Watchdog timer reset has not occurred.
1= Watchdog timer reset has occurred.
NOTE: This bit is cleared by writing 1 to this bit.
Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
0 = Disable Watchdog timer reset function
1= Enable Watchdog timer reset function
[1]
[0]
RSTEN
Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
0 = Writing 0 to this bit has no effect
1 = Reset the contents of the Watchdog timer
NOTE: This bit will auto clear after few clock cycle
RSTCNT
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5.12 UART Interface Controller
The ISD9160 includes a Universal Asynchronous Receiver/Transmitter (UART). The UART supports
high speed operation and flow control functions as well as protocols for Serial Infrared (IrDA) and
Local interconnect Network (LIN).
5.12.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on
data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the
CPU. The UART controller also supports LIN (Local Interconnect Network) master mode function and
IrDA SIR (Serial Infrared) function. The UART channel supports seven types of interrupts including
transmitter FIFO empty interrupt (THERINT), receiver threshold level interrupt (RDAINT), line status
interrupt (overrun error or parity error or framing error or break interrupt) (RLSINT), time out interrupt
(RXTOINT), MODEM status interrupt (MODEMINT), Buffer error interrupt (BUFERRINT) and LIN
receiver break field detected interrupt.
The UART has a 8-byte transmit FIFO (TX_FIFO) and a 8-byte receive FIFO (RX_FIFO) that reduces
the number of interrupts presented to the CPU. The CPU can read the status of the UART at any time
during the operation. The reported status information includes the type and condition of the transfer
operations being performed by the UART, as well as 4 error conditions (parity error, overrun error,
framing error and break interrupt) that can occur while receiving data. The UART includes a
programmable baud rate generator that is capable of dividing master clock input by divisors to
produce the baud rate clock. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2],
where M and BRD are defined in Baud Rate Divider Register ( BAUD). Table 5-96 lists the equations
under various conditions.
The UART controller supports auto-flow control function that uses two active-low signals, CTS (clear-
to-send) and RTS (request-to-send), to control the flow of data transfer between the UART and
external devices (e.g. Modem). When auto-flow is enabled, the UART will not receive data until the
UART asserts /RTS to external device. When the number of bytes in the Rx FIFO equals the value of
UART_FIFO.RTSTRGLV, the RTS is de-asserted. The UART sends data out when UART controller
detects CTS is asserted from external device. If CTS is not detected the UART controller will not send
data out.
The UART controller also provides Serial IrDA (SIR, Serial Infrared) function ( UART_FUNCSEL.
IRDAEN =1 to enable IrDA function). The SIR specification defines a short-range infrared
asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The maximum
data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR Protocol
encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and receive data at
the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer delay between
transmission and reception. This delay must be implemented by software.
The alternate function of UART controller is LIN (Local Interconnect Network) function. The LIN mode
is selected by setting the UART_FUNCSEL.LINEN bit. In LIN mode, one start bit, 8-bit data format
with 1-bit stop bit are generated in accordance with the LIN standard.
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Table 5-96 UART Baud Rate Equation
Mode
BAUDM1
BAUDM0
EDIVM1[3:0] BRD[15:0] Baud rate equation
0
1
2
0
1
1
0
0
1
B
B
A
A
A
UART_CLK / [16 * (A+2)]
UART_CLK / [(B+1) * (A+2)] , B ≥ 8
UART_CLK / (A+2), A ≥ 3
Don’t care
Table 5-97 UART Baud Rate Setting Table
System clock = 49.152MHz
Baud rate
921600
Mode0 %err
Mode1
%err
Mode2
A=51
%err
-0.6
x
x
A=4,B=8
1.2
1.2
460800
230400
A=10,B=8
A=104
A=211
0.3
1.2
1.2
A=22,B=8
A=7,B=11
x
-0.2
0.5
0.5
A=37,B=10
A=31,B=12
115200
57600
A=25
1.2
A=425
A=851
0.1
0.0
0.1
0.2
A=59,B=13
A=93,B=8
A=51 -0.6
0.0
0.0
A=126,B=9
A=78,B=15
38400
A=78
0.0
A=1278
0.0
A=254,B=9
A=158,B=15
0.0
0.0
19200
9600
4800
A=158 0.0
A=318 0.0
A=638 0.0
A=2558
A=5118
A=10238
0.0
0.0
0.0
A=510,B=9
A=318,B=15
0.0
0.0
0.0
0.0
A=1022,B=9
A=638,B=15
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5.12.2 Features of UART controller
UART supports 8 byte FIFO for receive and transmit data payloads.
PDMA access support.
Auto flow control function (/CTS, /RTS) supported.
Programmable baud-rate generator.
Fully programmable serial-interface characteristics:
o
o
o
o
o
5-, 6-, 7-, or 8-bit character.
Even, odd, or no-parity bit generation and detection.
1-, 1&1/2, or 2-stop bit generation.
Baud rate generation.
False start bit detection.
IrDA SIR Function.
LIN master mode.
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5.12.3 Block Diagram
The UART clock control and block diagram are shown as following.
SYSCLK->APBCLK.UART0_EN
UART0_CLK
HCLK
1/(UART_N+1)
SYSCLK->CLKDIV.UART_N
Figure 5-53 UART Clock Control Diagram
APB BUS
8
8
8
Status & control
Status & control
Control and
Status registers
TX_FIFO
RX_FIFO
TX shift register
RX shift register
Baud Rate
Generator
Baud out
Baud out
Serial Data Out
UART0_CLK
Serial Data In
Figure 5-54 UART Block Diagram
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TX_FIFO
The transmitter is buffered with an 8 byte FIFO to reduce the number of interrupts presented to the
CPU.
RX_FIFO
The receiver is buffered with an 8 byte FIFO (plus three error bits per byte) to reduce the number of
interrupts presented to the CPU.
TX shift Register
Shifts the transmit data out serially
RX shift Register
Shifts the receive data in serially
Modem Control Register
This register controls the interface to the MODEM or data set (or a peripheral device emulating a
MODEM).
Baud Rate Generator
Divides the UART0_CLK clock by the divisor to get the desired baud rate clock. Refer to Table 5-96
for the baud rate equation.
Control and Status Register
This is a register set, including the FIFO control registers (UART_FIFO), FIFO status registers
(UART_FIFOSTS), and line control register (UART_LINE) for transmitter and receiver. The time out
control register (UART_TOUT) identifies the condition of time out interrupt. This register set also
includes the interrupt enable register (UART_INTEN) and interrupt status register (UART_INTSTS) to
enable or disable the responding interrupt and to identify the occurrence of the responding interrupt.
There are six types of interrupts, transmitter FIFO empty interrupt(THERINT), receiver threshold level
reaching interrupt (RDAINT), line status interrupt (overrun error or parity error or framing error or break
interrupt) (RLSINT) , time out interrupt (RXTOINT), MODEM status interrupt (MODEMINT) and Buffer
error interrupt (BUFERRINT).
Figure 5-55 demonstrates the auto-flow control block diagram.
TX
Parallel to Serial
Tx FIFO
/CTS
Flow Control
APB
BUS
RX
Serial to Parallel
Flow Control
Rx FIFO
/RTS
Figure 5-55 Auto Flow Control Block Diagram
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5.12.4 IrDA Mode
The UART supports IrDA SIR (Serial Infrared) Transmit Encoder and Receive Decoder. IrDA mode is
selected by setting the UART_FUNCSEL.IRDAEN bit.
When in IrDA mode, the UART_BAUD.BAUDM1 register must be zero and baud rate is given by:
Baud Rate = UART_CLK / (16 * BRD), where BRD is Baud Rate Divider in the UART_BAUD.BRD
register.
TX pin
RX pin
Emit Infrared ray
SOUT
TX
RX
IR_SOUT
IrDA
SIR
IR
UART
IRCR
Transceiver
Detect Infrared ray
SIN
IR_SIN
BAUD
IrDA_EN
TX_SELECT
INV_TX
INV_RX
Figure 5-56 IrDA Block Diagram
5.12.4.1 IrDA SIR Transmit Encoder
The IrDA SIR Transmit Encoder modulates Non-Return-to Zero (NRZ) transmission bit stream from
UART serial output. The IrDA SIR physical layer specifies use of Return-to-Zero, Inverted (RZI)
modulation scheme which represents logic 0 as an infrared light pulse. The modulated output pulse
stream is transmitted to an external output driver and infrared LED (Light Emitting Diode). In normal
mode, the transmitted pulse width is specified as 3/16 the period of the baud rate.
5.12.4.2 IrDA SIR Receive Decoder
The IrDA SIR Receive Decoder demodulates the return-to-zero bit stream from the input detector and
outputs the NRZ serial bit stream to the UART received data input. The IR_SIN decoder input is
normally high in the idle state. Because of this, UART_IRDA.RXINV should be set 1 by default). A
start bit is detected when the IR_SIN decoder input is LOW.
5.12.4.3 IrDA SIR Operation
The IrDA SIR Encoder/decoder provides functionality which converts between UART data stream and
half duplex serial SIR interface. Figure 5-57 shows the IrDA encoder/decoder waveform:
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STOP BIT
START BIT
SOUT
(from uart TX)
0
0
1
0
1
1
1
0
0
1
1
Tx
Timing
IR_SOUT
(encoder output)
3/16 bit width
IR_SIN
(decorder input)
Rx
Timing
3/16 bit width
SIN
(To uart RX)
1
0
1
0
0
1
0
1
0
0
1
START BIT
STOP BIT
Bit pulse width
Figure 5-57 IrDA Tx/Rx Timing Diagram
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5.12.5 LIN (Local Interconnection Network) mode
The UART supports a Local Interconnection Network (LIN) function. LIN mode is selected by setting
the UART_FUNCSEL.LINEN bit. In LIN mode, each byte field is initiated by a start bit with value zero
(dominant), followed by 8 data bits (LSB is first) and ended by 1 stop bit with value one (recessive) in
accordance with the LIN standard (http://www.lin-subbus.org/ ).
Frame slot
Frame
Inter-
frame
space
Response
space
Header
Response
Protected
Identifier
field
Check
Sum
Data 1
Data 2
Data N
Break
Field
Synch
field
Figure 5-58 Structure of LIN Frame
The program flow of LIN Bus Transmit transfer (Tx) is shown as following
1.
2.
3.
4.
5.
Set the UART_FUNCSEL.LINEN bit to enable LIN Bus mode.
Set UART_ALTCTL.BRKFL to choose break field length. The break field length is BRKFL+2.
Fill 0x55 to UART_DAT to request synch field transmission.
Request Identifier Field transmission by writing the protected identifier value to UART_DAT
Set the UART_ALTCTL.LINTX_EN bit to start transmission (When break filed operation is
finished, LINTX_EN will be cleared automatically).
6.
7.
When the STOP bit of the last byte UART_DAT has been sent to bus, hardware will set flag
UART_FIFOSTS.TXEMPTYF to 1.
Fill N bytes data and Checksum to UART_DAT then repeat step 5 and 6 to transmit the data.
The program flow of LIN Bus Receiver transfer (Rx) is show as following
1.
2.
3.
4.
Set the UART_FUNCSEL.LINEN bit to enable LIN Bus mode.
Set the UART_ALTCTL.LINRX_EN bit register to enable LIN Rx mode.
Wait for the flag UART_INTSTS.LINIF to indicate Rx received Break field or not.
Wait for the flag UART_INTSTS.RDAIF read back the UART_DAT register.
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5.12.6 UART Interface Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
UART0 Base Address:
UART0_BA = 0x4005_0000
UART_DAT
UART0_BA + 0x00
UART0_BA + 0x04
UART0_BA + 0x08
UART0_BA + 0x0C
UART0_BA + 0x10
UART0_BA + 0x14
UART0_BA + 0x18
UART0_BA + 0x1C
UART0_BA + 0x20
UART0_BA + 0x24
UART0_BA + 0x28
UART0_BA + 0x2C
UART0_BA + 0x30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UART0 Receive/Transfer FIFO Register.
UART0 Interrupt Enable Register.
UART0 FIFO Control Register.
UART0 Line Control Register.
UART0 Modem Control Register.
UART0 Modem Status Register.
UART0 FIFO Status Register.
UART0 Interrupt Status Register.
UART0 Time Out Register
Undefined
UART_INTEN
UART_FIFO
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x1040_4000
0x0000_0002
0x0000_0000
0x0F00_0000
0x0000_0040
0x0000_0000
0x0000_0000
UART_LINE
UART_MODEM
UART_MODEMSTS
UART_FIFOSTS
UART_INTSTS
UART_TOUT
UART0 Baud Rate Divisor Register
UART0 IrDA Control Register.
UART0 LIN Control Register.
UART_BAUD
UART_IRDA
UART_ALTCTL
UART_FUNCSEL
UART0 Function Select Register.
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5.12.7
UART Interface Control Register Description
Receive FIFO Data Register (UART_DAT)
Register
Offset
R/W Description
Reset Value
UART_DAT
UART0_BA + 0x00 R/W UART0 Receive/Transfer FIFO Register.
Undefined
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
DAT
1
0
Table 5-98 UART Receive FIFO Data Register (UART_DAT, address 0x4005_0000)
Bits
Description
Receive FIFO Register
DAT
[7:0]
Reading this register will return data from the receive data FIFO. By reading this
register, the UART will return the 8-bit data received from Rx pin (LSB first).
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Interrupt Enable Register (UART_INTEN)
Offset R/W Description
Register
Reset Value
UART_INTEN
UART0_BA + 0x04 R/W UART0 Interrupt Enable Register.
0x0000_0000
31
23
30
22
29
21
28
20
27
19
26
18
25
17
9
24
16
Reserved
Reserved
15
DMARXEN
7
14
DMATXEN
6
13
12
11
10
8
ATOCTSEN
5
ATORTSEN
4
TOCNTEN
3
Reserved
LINIEN
0
2
1
Reserved
BUFERRIEN
RXTOIEN
MODEMIEN
RLSIEN
THREIEN
RDAIEN
Table 5-99 UART Interrupt Enable Register (UART_INTEN, address 0x4005_0004)
Bits
Description
[31:16]
Reserved
Reserved
Receive DMA Enable
[15]
[14]
DMARXEN
If enabled, the UART will request DMA service when data is available in receive FIFO.
Transmit DMA Enable
DMATXEN
If enabled, the UART will request DMA service when space is available in transmit
FIFO.
CTS Auto Flow Control Enable
0 = Disable CTS auto flow control.
1 = Enable.
[13]
[12]
ATOCTSEN
When CTS auto-flow is enabled, the UART will send data to external device when
CTS input is asserted (UART will not send data to device until CTS is asserted).
RTS Auto Flow Control Enable
0 = Disable RTS auto flow control.
1 = Enable.
ATORTSEN
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals
UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.
Time-Out Counter Enable
0 = Disable Time-out counter.
1 = Enable.
[11]
TOCNTEN
[10:9]
Reserved
Reserved
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LIN RX Break Field Detected Interrupt Enable
0 = Mask off Lin bus Rx break field interrupt.
1 = Enable Lin bus Rx break field interrupt.
[8]
LINIEN
[7:6]
[5]
Reserved
BUFERRIEN
Reserved
Buffer Error Interrupt Enable
0 = Mask off BUFERRINT
1 = Enable IBUFERRINT
Receive Time out Interrupt Enable
0 = Mask off RXTOINT
[4]
[3]
[2]
[1]
[0]
RXTOIEN
MODEMIEN
RLSIEN
1 = Enable RXTOINT
Modem Status Interrupt Enable
0 = Mask off MODEMINT
1 = Enable MODEMINT
Receive Line Status Interrupt Enable
0 = Mask off RLSINT
1 = Enable RLSINT
Transmit FIFO Register Empty Interrupt Enable
0 = Mask off THERINT
THREIEN
RDAIEN
1 = Enable THERINT
Receive Data Available Interrupt Enable.
0 = Mask off RDAINT
1 = Enable RDAINT
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FIFO Control Register (UART_FIFO)
Offset R/W Description
Register
Reset Value
UART_FIFO
UART0_BA + 0x08 R/W UART0 FIFO Control Register.
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
RTSTRGLV
1
0
RFITL
Reserved
TXRST
RXRST
Reserved
Table 5-100 UART FIFO Control Register (UART_FIFO, address 0x4005_0008)
Description
Bits
[31:20]
Reserved
Reserved
RTS Trigger Level for Auto-flow Control
Sets the FIFO trigger level when auto-flow control will de-assert RTS (request-to-send).
Value
:
:
:
:
Trigger Level (Bytes)
[19:16]
RTSTRGLV
0
1
2
1
4
8
Receive FIFO Interrupt (RDAINT) Trigger Level
When the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set
and, if enabled, an RDAINT interrupt will generated.
Value
:
:
:
:
INTR_RDA Trigger Level (Bytes)
[7:4]
RFITL
0
1
2
1
4
8
[3]
[2]
Reserved
Reserved
Transmit FIFO Reset
When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state
machine is reset.
TXRST
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the transmitting internal state machine and pointers.
Note: This bit will auto-clear after 3 UART engine clock cycles.
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Receive FIFO Reset
When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state
machine is reset.
[1]
[0]
RXRST
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the receiving internal state machine and pointers.
Note: This bit will auto-clear after 3 UART engine clock cycles.
Reserved
Reserved
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Line Control Register (UART_LINE)
Offset R/W Description
Register
Reset Value
UART_LINE
UART0_BA + 0x0C R/W UART0 Line Control Register.
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
BCB
SPE
EPE
PBE
NSB
WLS
Table 5-101 UART Line Control Register (UART_LINE, address 0x4005_000C)
Description
Bits
[31:7]
Reserved
Reserved
Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the ‘Space’ state (logic 0).
Normal condition is serial data output is ‘Mark’ state. This bit acts only on Tx and has no effect on
the transmitter logic.
[6]
[5]
BCB
Stick Parity Enable
0 = Disable stick parity
SPE
EPE
PBE
1 = When bits PBE and SPE are set ‘Stick Parity’ is enabled. If EPE=0 the parity bit is transmitted
and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared.
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in the data word and parity bits.
1 = Even number of logic 1’s are transmitted or checked in the data word and parity bits.
This bit has effect only when PBE (parity bit enable) is set.
[4]
[3]
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked (receive data) during transfer.
1 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial
data.
Number of STOP bits
0= One “STOP bit” is generated after the transmitted data
[2]
NSB
WLS
1= Two “STOP bits” are generated when 6-, 7- and 8-bit word length is selected; One and a half
“STOP bits” are generated in the transmitted data when 5-bit word length is selected;
Word Length Select
[1:0]
0 (5bits), 1(6bits), 2(7bits), 3(8bits)
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MODEM Control Register (UART_MODEM)
Offset R/W Description
Register
Reset Value
UART_MODEM
UART0_BA + 0x10 R/W UART0 Modem Control Register.
0x0000_0000
31
23
15
30
22
14
29
21
28
20
12
27
19
11
26
18
10
2
25
17
24
16
Reserved
Reserved
13
RTSSTS
5
9
RTSACTLV
1
8
Reserved
Reserved
3
Reserved
0
7
6
4
Reserved
LBMEN
Reserved
RTS
Reserved
Table 5-102 UART Modem Control Register (UART_MODEM, address 0x4005_0010)
Bits
Description
[31:14]
[13]
Reserved
RTSSTS
Reserved
Reserved
RTS Pin State (read only)
This bit is the pin status of RTS.
[12:10]
Reserved
Request-to-Send (RTS) Active Trigger Level
This bit can change the RTS trigger level.
0= RTS is active low level.
[9]
RTSACTLV
1= RTS is active high level
[8:5]
[4]
Reserved
LBMEN
Reserved
Loopback Mode Enable
0=Disable
1=Enable
[3:2]
Reserved
Reserved
RTS (Request-To-Send) Signal
If UART_INTEN.ATORTSEN aaa 0, this bit controls whether RTS pin is active or not.
0 = Drive RTS inactive ( aaa ~RTSACTLV).
[1]
RTS
1 = Drive RTS active ( aaa RTSACTLV).
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Modem Status Register (UART_MODEMSTS)
Offset R/W Description
Register
Reset Value
UART_MODEMSTS
UART0_BA + 0x14 R/W UART0 Modem Status Register.
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
25
17
9
24
16
Reserved
Reserved
8
Reserved
4
CTSACTLV
0
2
1
Reserved
CTSSTS
Reserved
CTSDETF
Table 5-103 UART Modem Status Register (UART_MODEMSTS, address 0x4005_0014)
Bits
Description
[31:9]
Reserved
Reserved
Clear-to-Send (CTS) Active Trigger Level
This bit can change the CTS trigger level.
0= CTS is active low level.
[8]
CTSACTLV
1= CTS is active high level
[7:5]
[4]
Reserved
CTSSTS
Reserved
Reserved
CTS Pin Status (read only)
This bit is the pin status of CTS.
[3:1]
Reserved
Detect CTS State Change Flag
This bit is set whenever CTS input has state change. It will generate Modem interrupt
to CPU when UART_INTEN.MODEMIEN aaa 1
[0]
CTSDETF
NOTE: This bit is cleared by writing 1 to itself.
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FIFO Status Register (UART_FIFOSTS)
Register
Offset
R/W Description
R/W UART0 FIFO Status Register.
Reset Value
UART_FIFOSTS
UART0_BA + 0x18
0x1040_4000
31
30
Reserved
22
29
21
13
5
28
TXEMPTYF
20
27
19
11
3
26
Reserved
18
25
17
9
24
TXOVIF
16
23
TXFULL
15
TXEMPTY
14
TXPTR
12
10
8
RXFULL
7
RXEMPTY
6
RXPTR
4
2
1
0
Reserved
BIF
FEF
PEF
Reserved
RXOVIF
Table 5-104 UART FIFO Status Register (UART_FIFOSTS, address 0x4005_0018)
Bits
Description
[31:29]
Reserved
Reserved
Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has
been transmitted.
[28]
TXEMPTYF
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission
has not completed.
NOTE: This bit is read only.
Reserved
[27:25]
[24]
Reserved
Tx Overflow Error Interrupt Flag
If the Tx FIFO ( UART_DAT) is full, an additional write to UART_DAT will cause an
overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event
and interrupt if enabled.
TXOVIF
NOTE: This bit is cleared by writing 1 to itself.
Transmit FIFO Full (Read Only)
This bit indicates whether the Tx FIFO is full or not.
[23]
[22]
TXFULL
This bit is set when Tx FIFO is full; otherwise it is cleared by hardware. TXFULL=0
indicates there is room to write more data to Tx FIFO.
Transmit FIFO Empty (Read Only)
This bit indicates whether the Tx FIFO is empty or not.
TXEMPTY
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register,
hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not
empty).
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Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx
FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the
Transmit Shift Register, TXPTR is decremented.
[21:16]
[15]
TXPTR
Receive FIFO Full (Read Only)
RXFULL
This bit indicates whether the Rx FIFO is full or not.
This bit is set when Rx FIFO is full; otherwise it is cleared by hardware.
Receive FIFO Empty (Read Only)
This bit indicates whether the Rx FIFO is empty or not.
[14]
RXEMPTY
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It
will be cleared when UART receives any new data.
Rx FIFO pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for
read in the Rx FIFO. When UART receives one byte from external device, RXPTR is
incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
[13:8]
[7]
RXPTR
Reserved
Reserved
Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input (Rx) is held in the "space”
state (logic 0) for longer than a full word transmission time (that is, the total time of
start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this
bit.
[6]
[5]
BIF
Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid "stop
bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0),
and is reset whenever the CPU writes 1 to this bit.
FEF
Parity Error Flag
[4]
PEF
This bit is set to logic 1 whenever the received character does not have a valid "parity
bit", and is reset whenever the CPU writes 1 to this bit.
[3:1]
Reserved
Reserved
Rx Overflow Error Interrupt Flag
If the Rx FIFO ( UART_DAT) is full, and an additional byte is received by the UART,
an overflow condition will occur and set this bit to logic 1. It will also generate a
BUFERRIF event and interrupt if enabled.
[0]
RXOVIF
NOTE: This bit is cleared by writing 1 to itself.
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Interrupt Status Register (UART_INTSTS)
Register
Offset
R/W Description
R/W UART0 Interrupt Status Register.
Reset Value
UART_INTSTS
UART0_BA + 0x1C
0x0000_0002
31
DLININT
23
30
29
28
DRXTOINT
20
27
DMODEMI
19
26
DRLSINT
18
25
17
9
24
Reserved
22
DBERRINT
Reserved
21
DBERRIF
13
16
DLINIF
15
Reserved
14
DRXTOIF
12
DMODEMIF
11
DRLSIF
10
Reserved
8
RDAINT
0
LININT
7
Reserved
6
BUF_ERR _INT
5
RXTOINT
4
MODEMINT
3
RLSINT
2
THERINT
1
LINIF
Reserved
BUFERRIF
RXTOIF
MODENIF
RLSIF
THREIF
RDAIF
Table 5-105 UART Interrupt Status Register (UART_INTSTS, address 0x4005_001C)
Bits
[31]
[30]
[29]
Description
DMA MODE LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt
Controller
DLININT
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DLINIF.
RESERVED
RESERVED
DBERRINT
DMA MODE Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and
DBERRIF.
DMA MODE Time Out Interrupt Indicator to Interrupt Controller
[28]
DRXTOINT
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and
DRXTOIF.
DMA MODE MODEM Status Interrupt Indicator to Interrupt
[27]
[26]
DMODEMI
DRLSINT
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and
DMODENIF.
DMA MODE Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.DMARXEN or UART_INTEN.DMATXEN and DRLSIF.
[25]
[24]
RESERVED
RESERVED
RESERVED
RESERVED
DMA MODE LIN Bus Rx Break Field Detected Flag
[23]
[22]
DLINIF
This bit is set when LIN controller detects a break field. This bit is cleared by writing a
1.
RESERVED
RESERVED
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DMA MODE Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or
UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be
corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be
generated.
[21]
DBERRIF
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and
UART_FIFOSTS.RXOVIF are cleared.
DMA MODE Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO
and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU
interrupt request will be generated.
[20]
[19]
DRXTOIF
NOTE: This bit is read only and user can read FIFO to clear it.
DMA MODE MODEM Interrupt Flag (Read Only)
This
bit
is
set
when
the
CTS
pin
has
changed
state
(UART_MODEMSTS.CTSDETF=1). If UART_INTEN.MODEMIEN is enabled, a CPU
interrupt request will be generated.
DMODEMIF
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is
cleared by a write 1.
DMA MODE Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least
one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is
set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
[18]
DRLSIF
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are
cleared.
[17:16]
[15]
RESERVED
LININT
RESERVED
LIN Bus Rx Break Field Detected Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.LINIEN and LINIF.
[14]
Reserved
BUFERRINT
Reserved
Buffer Error Interrupt Indicator to Interrupt Controller
[13]
Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.
Time Out Interrupt Indicator to Interrupt Controller
[12]
[11]
[10]
[9]
RXTOINT
MODEMINT
RLSINT
Logical AND of UART_INTEN.RXTOIEN and RXTOIF.
MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.MODEMIEN and MODENIF.
Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RLSIEN and RLSIF.
Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller
THERINT
RDAINT
Logical AND of UART_INTEN.THREIEN and THREIF.
Receive Data Available Interrupt Indicator to Interrupt Controller
[8]
Logical AND of UART_INTEN.RDAIEN and RDAIF.
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LIN Bus Rx Break Field Detected Flag
[7]
[6]
LINIF
This bit is set when LIN controller detects a break field. This bit is cleared by writing a
1.
Reserved
Reserved
Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or
UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be
corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be
generated.
[5]
BUFERRIF
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and
UART_FIFOSTS.RXOVIF are cleared.
Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO
and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU
interrupt request will be generated.
[4]
[3]
RXTOIF
NOTE: This bit is read only and user can read FIFO to clear it.
MODEM Interrupt Flag (Read Only)
This
bit
is
set
when
the
CTS
pin
has
changed
state
(UART_MODEMSTS.CTSDETF=1). If UART_INTEN.MODEMIEN is enabled, a CPU
interrupt request will be generated.
MODENIF
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is
cleared by a write 1.
Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least
one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is
set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
[2]
RLSIF
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are
cleared.
Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift
Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.
[1]
[0]
THREIF
RDAIF
NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF
will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.
NOTE: This bit is read only and it will be cleared when the number of unread bytes of
Rx FIFO drops below the threshold level (RFITL).
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When the DMA controller is used to transmit or receive data to the UART, an alternate set of flags and
interrupt indicators are generated. These are equivalent to the normal mode set above and are
summarized in Table 5-106.
Table 5-106 UART Interrupt Sources and Flags Table In DMA Mode
UART Interrupt Interrupt Enable
Interrupt Indicator
to Interrupt
Controller
Interrupt Flag
DLINIF
Flag Cleared by
Source
Bit
LIN RX Break
Field Detected
interrupt
LINIEN
DLININT
Write ‘1’ to LINIF
DMA_BUFERRIF =
(TXOVIF or RXOVIF)
Buffer Error
Interrupt
BUFERRINT
BUFERRIEN
RXTOIEN
MODEMIEN
RLSIEN
DBERRINT
DRXTOINT
DMODEMI
DRLSINT
Write ‘1’ to
TXOVIF/ RXOVIF
DRXTOIF
Rx Timeout
Interrupt
RXTOINT
Read data FIFO
DMODEMIF =
(CTSDETF)
Modem Status
Interrupt
MODEMINT
Write ‘1’ to
CTSDETF
DRLSIF =
(BIF or FEF or PEF)
Receive Line
Status Interrupt
RLSINT
Write ‘1’ to
BIF/FEF/PEF
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Table 5-107 UART Interrupt Sources and Flags Table In Software Mode
UART Interrupt Source
Interrupt Enable
Bit
Interrupt Indicator Interrupt Flag
to Interrupt
Flag Cleared by
Controller
LINIF
LIN RX Break Field
Detected interrupt
LINIEN
LININT
Write ‘1’ to LINIF
BUFERRIF =
(TXOVIF or
RXOVIF)
Buffer Error Interrupt
BUFERRINT
BUFERRIEN
BUFERRINT
Write ‘1’ to
TXOVIF/ RXOVIF
RXTOIF
Rx Timeout Interrupt
RXTOINT
RXTOIEN
MODEMIEN
RLSIEN
RXTOINT
MODEMINT
RLSINT
Read data FIFO
MODENIF =
(CTSDETF)
Modem Status Interrupt
MODEMINT
Write ‘1’ to
CTSDETF
RLSIF =
(BIF or FEF or
PEF)
Receive Line Status
Interrupt
RLSINT
Write ‘1’ to
BIF/FEF/PEF
THREIF
RDAIF
Transmit Holding Register
Empty Interrupt
THERINT
THREIEN
RDAIEN
THERINT
RDAINT
Write data FIFO
Read data FIFO
Receive Data Available
Interrupt
RDAINT
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Time Out Register (UART_TOUT)
Register
Offset
R/W Description
Reset Value
R/W UART0 Time Out Register
UART_TOUT
UART0_BA + 0x20
0x0000_0000
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
3
1
0
Reserved
TOIC
Table 5-108 UART Time Out Register (UART_TOUT, address 0x4005_0020)
Bits
Description
[31:7]
Reserved
Reserved
Time Out Interrupt Comparator
The time out counter resets and starts counting whenever the Rx FIFO receives a new
data word. Once the content of time out counter (TOUT_CNT) is equal to that of time
out interrupt comparator (TOIC), a receiver time out interrupt (RXTOINT) is generated
if UART_INTEN.RXTOIEN is set. A new incoming data word or RX FIFO empty clears
RXTOIF. The period of the time out counter is the baud rate.
[6:0]
TOIC
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Baud Rate Divider Register (UART_BAUD)
Register
Offset
R/W Description
R/W UART0 Baud Rate Divisor Register
Reset Value
0x0F00_0000
UART_BAUD
UART0_BA + 0x24
The baud rate generator takes the UART master clock UART_CLK and divides it to produce the baud
rate (bit rate) clock. The divider has two division stages controlled by BRD and EDIVM1 fields. These
are configured in three modes depending on the selections of BAUDM1 and BAUDM0. These modes
and the baud rate equations for them are described in Table 5-110.
31
23
15
7
30
22
14
6
29
BAUDM1
21
28
BAUDM0
20
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
EDIVM1
Reserved
13
5
12
4
BRD[15:0]
BRD[7:0]
1
0
Table 5-109 UART Baud Rate Divider Register (UART_BAUD, address 0x4005_0024)
Bits
[31:30]
Description
Reserved
Reserved
Divider X Enable
The baud rate equation is:
Baud Rate aaa UART_CLK / [ M * (BRD + 2) ] ; The default value of M is 16.
0 = Disable divider X ( M aaa 16)
[29]
BAUDM1
1 = Enable divider X (M aaa EDIVM1+1, with EDIVM1 ≥ 8).
Refer to Table 5-110 for more information.
NOTE: When in IrDA mode, this bit must disabled.
Divider X equal 1
0: M aaa EDIVM1+1, with restriction EDIVM1 ≥ 8.
1: M aaa 1, with restriction BRD[15:0] ≥ 3.
Refer to Table 5-110 for more information.
[28]
BAUDM0
Divider X
[27:24]
[23:16]
[15:0]
EDIVM1
Reserved
BRD
The baud rate divider M aaa EDIVM1+1.
Reserved
Baud Rate Divider
Refer to Table 5-110 for more information.
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Table 5-110 Baud Rate Equations.
Mode BAUDM1
BAUDM0
EDIVM1[ BRD[15:0] Baud rate equation
3:0]
0
1
2
0
1
1
0
0
1
B
B
A
A
A
UART_CLK / [16 * (A+2)]
UART_CLK / [(B+1) * (A+2)] , requires B ≥ 8
UART_CLK / (A+2), requires A ≥ 3
Don’t care
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IrDA Control Register (UART_IRDA)
Offset R/W Description
Register
Reset Value
UART_IRDA
UART0_BA + 0x28 R/W UART0 IrDA Control Register.
0x0000_0040
7
6
5
4
3
2
1
0
Reserved
RXINV
TXINV
Reserved
LOOPBACK
TXEN
Reserved
Table 5-111 UART IrDA Control Register (UART_IRDA, address 0x4005_0028)
Bits
Description
[31:7]
Reserved
Reserved
Receive Inversion Enable
0= No inversion
[6]
[5]
RXINV
1= Invert Rx input signal
Transmit inversion enable
0= No inversion
TXINV
1= Invert Tx output signal
[4:3]
[2]
Reserved
Reserved
IrDA Loopback Test Mode
LOOPBACK
Loopback Tx to Rx.
Transmit/Receive Selection
0=Enable IrDA receiver.
[1]
[0]
TXEN
1= Enable IrDA transmitter.
Reserved
Reserved
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UART LIN Network Control Register (UART_ALTCTL)
Register
Offset
R/W Description
R/W UART0 LIN Control Register.
Reset Value
UART_ALTCTL
UART0_BA + 0x2C
0x0000_0000
31
23
15
30
22
14
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
6
1
0
LINTXEN
LINRXEN
Reserved
BRKFL
Table 5-112 UART LIN Network Control Register (UART_ALTCTL, address 0x4005_002C)
Bits
Description
Reserved
Reserved
[31:8]
LIN TX Break Mode Enable
0 = Disable LIN Tx Break Mode.
1 = Enable LIN Tx Break Mode.
LINTXEN
[7]
NOTE: When Tx break field transfer operation finished, this bit will be cleared
automatically.
LIN RX Enable
LINRXEN
BRKFL
[6]
0 = Disable LIN Rx mode.
1 = Enable LIN Rx mode.
UART LIN Break Field Length Count
[3:0]
This field indicates a 4-bit LIN Tx break field count.
NOTE: This break field length is BRKFL + 2
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UART Function Select Register (UART_FUNCSEL)
Register
Offset
R/W Description
R/W UART0 Function Select Register.
Reset Value
UART_FUNCSEL
UART0_BA + 0x30
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
IRDAEN
LINEN
Table 5-113 UART Function Select Register (UART_FUNCSEL, address 0x4005_0030)
Bits
Description
[31:2]
Reserved
Reserved
Enable IrDA Function
0 = UART Function.
[1]
[0]
IRDAEN
1 = Enable IrDA Function.
Enable LIN Function
0 = UART Function.
LINEN
1 = Enable LIN Function.
Note that IrDA and LIN functions are mutually exclusive: both cannot be active at
same time.
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5.13 I2S Audio PCM Controller
5.13.1 Overview
The I2S controller is a peripheral for serial transmission and reception of audio PCM (Pulse-Code
Modulated) signals across a 4-wire bus. The bus consists of a bit clock (I2S_BCLK) a frame
synchronization clock (I2S_FS) and serial data in (I2S_SDI) and out (I2S_SDO) lines. This peripheral
allows communication with an external audio CODEC or DSP. The peripheral is capable of mono or
stereo audio transmission with 8-32bit word sizes. Audio data is buffered in 8 word deep FIFO buffers
and has DMA capability.
5.13.2 Features
I2S can operate as either master or slave
Master clock generation for slave device synchronization.
Capable of handling 8, 16, 24 and 32 bit word sizes.
Mono and stereo audio data supported.
I2S and MSB justified data format supported.
8 word FIFO data buffers for transmit and receive.
Generates interrupt requests when buffer levels crosses programmable boundary.
Two DMA requests, one for transmit and one for receive.
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5.13.3 I2S Block Diagram
SYSCLK->CLKSEL2.I2S_S
SYSCLK->APBCLK.I2S_EN
OSC10K
OSC32K
HCLK
00
I2S_CLK
01
10
11
OSC48M
Figure 5-59 I2S Clock Control Diagram
I2S_MCLK
I2S_FS
I2S_CLK_GEN
WS
MUX
Transmit
Contrl
&
I2S_SDO
Tx Shift Register
TXFIFO
APB
Interface
&
I2S_BCLK
Shift Clock
dma_req
MUX
Control
Registers
dma_ack
Receive
Control
&
Rx Shift Register
I2S_SDI
RXFIFO
SLAVE_MODE
Figure 5-60 I2S Controller Block Diagram
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5.13.4 I2S Operation
//
I2S_BCLK
I2S_FS
//
//
I2S_SDI
I2S_SDO
LSB
LSB
MSB
MSB
Word N
//
Word N-1
Word N
Right Channel
Left Channel
Right Channel
Figure 5-61 I2S Bus Timing Diagram (Format =0)
//
I2S_BCLK
I2S_FS
//
//
I2S_SDI
I2S_SDO
LSB
LSB
MSB
MSB
//
Word N-1
Word N
Word N
Right Channel
Left Channel
Right Channel
Figure 5-62 MSB Justified Timing Diagram (Format=1)
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5.13.5 FIFO operation
Mono 8-bit data mode
N+3
N+2
N+1
N
7
0
7
7
0
0
0
0
7
7
0
0
7
7
0
0
0
0
Stereo 8-bit data mode
LEFT+1
RIGHT+1
LEFT
RIGHT
7
0
Mono 16-bit data mode
N+1
N
15
15
15
Stereo 16-bit data mode
LEFT
RIGHT
15
Mono 24-bit data mode
N
23
Stereo 24-bit data mode
0
LEFT
N
23
0
0
RIGHT
N+1
23
Mono 32-bit data mode
31
N
0
Stereo 32-bit data mode
LEFT
N
31
0
0
RIGHT
N+1
31
Figure 5-63 FIFO contents for various I2S modes
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5.13.6 I2S Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
I2S Base Address:
I2S_BA = 0x400A_0000
I2S_CTL
I2S_CLKDIV
I2S_IEN
I2S_BA + 0x00
I2S_BA + 0x04
I2S_BA + 0x08
I2S_BA + 0x0C
I2S_BA + 0x10
I2S_BA + 0x14
R/W
R/W
R/W
R/W
W
I2S Control Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0014_1000
0x0000_0000
0x0000_0000
I2S Clock Divider Register
I2S Interrupt Enable Register
I2S Status Register
I2S_STATUS
I2S_TX
I2S Transmit FIFO Register
I2S Receive FIFO Register
I2S_RX
R
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5.13.7
I2S Control Register Description
I2S Control Register (I2S_CTL)
Register
I2S_CTL
Offset
R/W
Description
Reset Value
I2S_BA + 0x00
R/W
I2S Control Register
0x0000_0000
31
23
30
29
28
27
26
25
24
Reserved
20
22
Reserved
14
21
19
18
17
LZCEN
9
16
RXCLR
TXCLR
Reserved
RXPDMAEN
TXPDMAEN
12
RZCEN
15
MCLKEN
7
13
RXTH
5
11
10
TXTH
2
8
SLAVE
0
6
4
3
1
FORMAT
MONO
WDWIDTH
MUTE
RXEN
TXEN
I2SEN
Table 5-114 I2S Control Register (I2S_CTL, address 0x400A_0000)
Description
Bits
[31:22]
Reserved
Reserved
Enable Receive DMA
When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to
SRAM if FIFO is not empty.
[21]
[20]
RXPDMAEN
0 = Disable RX DMA
1 = Enable RX DMA
Enable Transmit DMA
When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit
FIFO if FIFO is not full.
TXPDMAEN
0 = Disable TX DMA
1 = Enable TX DMA
Clear Receive FIFO
Write 1 to clear receiving FIFO, internal pointer is reset to FIFO start point, and RXTH
returns to zero and receive FIFO becomes empty.
RXCLR
TXCLR
[19]
[18]
This bit is cleared by hardware automatically when clear operation complete.
Clear Transmit FIFO
Write 1 to clear transmitting FIFO, internal pointer is reset to FIFO start point, and
TXTH returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not
changed.
This bit is cleared by hardware automatically when clear operation complete.
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Left Channel Zero Cross Detect Enable
If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero,
the LZCIF flag in I2S_STATUS register will be set to 1.
[17]
[16]
LZCEN
RZCEN
0 = Disable left channel zero cross detect
1 = Enable left channel zero cross detect
Right Channel Zero Cross Detect Enable
If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero,
the RZCIF flag in I2S_STATUS register will be set to 1.
0 = Disable right channel zero cross detect
1 = Enable right channel zero cross detect
Master Clock Enable
The ISD91xx can generate a master clock signal to an external audio CODEC to
synchronize the audio devices. If audio devices are not synchronous, then data will be
periodically corrupted. Software needs to implement a way to drop/repeat or
interpolate samples in a jitter buffer if devices are not synchronized. The master clock
frequency is determined by the I2S_CLKDIV.MCLKDIV register.
[15]
MCLKEN
0 = Disable master clock
1 = Enable master clock
Receive FIFO Threshold Level
When received data word(s) in buffer is equal or higher than threshold level then
RXTHI flag is set.
[14:12]
[11:9]
RXTH
TXTH
Threshold = RXTH+1 words of data in receive FIFO.
Transmit FIFO Threshold Level
If remaining data words in transmit FIFO less than or equal to the threshold level then
TXTHI flag is set.
Threshold = TXTH words remaining in transmit FIFO
Slave Mode
I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins
are outputs and send bit clock and frame sync from ISD91xx. In slave mode,
I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from
external audio device.
[8]
SLAVE
0 = Master mode
1 = Slave mode
Data format
0 = I2S data format
1 = MSB justified data format
[7]
[6]
FORMAT
MONO
See Figure 5-61 and Figure 5-62 for timing differences.
Monaural data
This parameter sets whether mono or stereo data is processed. See Figure 5-63 for
details of how data is formatted in transmit and receive FIFO.
0 = Data is stereo format
1 = Data is monaural format
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Word Width
This parameter sets the word width of audio data. See Figure 5-63 for details of how
data is formatted in transmit and receive FIFO.
00 = data is 8 bit
01 = data is 16 bit
10 = data is 24 bit
11 = data is 32 bit
[5:4]
WDWIDTH
Transmit Mute Enable
0 = Transmit data is shifted from FIFO
1= Transmit channel zero
[3]
[2]
[1]
[0]
MUTE
RXEN
TXEN
I2SEN
Receive Enable
0 = Disable data receive
1 = Enable data receive
Transmit Enable
0 = Disable data transmit
1 = Enable data transmit
Enable I2S Controller
0 = Disable
1 = Enable
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I2S Clock Divider (I2S_CLKDIV)
Register
Offset
R/W
Description
Reset Value
I2S_CLKDIV
I2S_BA + 0x04
R/W
I2S Clock Divider Register
0x0000_0000
15
7
14
6
13
12
4
11
3
10
2
9
8
0
BCLKDIV
5
1
Reserved
MCLKDIV
Table 5-115 I2S Clock Divider Register (I2S_CLKDIV, address 0x400A_0004)
Bits
Description
[31:16]
Reserved
Reserved
Bit Clock Divider
If I2S operates in master mode, bit clock is provided by ISD91xx. Software can
program these bits to generate bit clock frequency for the desired sample rate.
For sample rate Fs, the desired bit clock frequency is:
F(BCLK) aaa Fs x Word_width_in_bytes x 16
For example if Fs aaa 16kHz, and word width is 2-bytes (16bit) then desired bit clock
frequency is 512kHz.
[15:8]
BCLKDIV
The bit clock frequency is given by:
F(BCLK) aaa F(I2S_CLK) / 2x(BCLKDIV+1)
Or,
BCLKDIV aaa F(I2S_CLK) / (2 x F(BCLK)) -1
So if F(I2S_CLK) aaa HCLK aaa 49.152MHz , desired F(BCLK) aaa 512kHz then
BCLKDIV aaa 47
[7:3]
[2:0]
Reserved
Reserved
Master Clock Divider
ISD9160 can generate a master clock to synchronously drive an external audio
device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLK clock input, otherwise
MCLK frequency is given by:
MCLKDIV
F(MCLK) aaa F(I2S_CLK) / (2xMCLKDIV)
Or,
MCLKDIV aaa F(I2S_CLK) / (2 x F(MCLK))
If the desired MCLK frequency is 254Fs and Fs aaa 16kHz then MCLKDIV aaa 6
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I2S Interrupt Enable Register (I2S_IEN)
Register
I2S_IEN
Offset
R/W
Description
Reset Value
I2S_BA + 0x08
R/W
I2S Interrupt Enable Register
0x0000_0000
15
7
14
Reserved
6
13
12
11
10
9
8
LZCIEN
4
RZCIEN
3
TXTHIEN
2
TXOVIEN
1
TXUDIEN
0
5
Reserved
RXTHIEN
RXOVIEN
RXUDIEN
Table 5-116 I2S Interrupt Enable Register (I2S_IEN, address 0x400A_0008)
Description
Bits
Left Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and left channel has zero cross event
[12]
[11]
[10]
LZCIEN
RZCIEN
TXTHIEN
0 = Disable interrupt
1 = Enable interrupt
Right Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and right channel has zero cross event
0 = Disable interrupt
1 = Enable interrupt
Transmit FIFO Threshold Level Interrupt Enable
Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].
0 = Disable interrupt
1 = Enable interrupt
Transmit FIFO Overflow Interrupt Enable
Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
0 = Disable interrupt
[9]
[8]
TXOVIEN
TXUDIEN
1 = Enable interrupt
Transmit FIFO Underflow Interrupt Enable
Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
0 = Disable interrupt
1 = Enable interrupt
Receive FIFO Threshold Level Interrupt
Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal
to RXTH[2:0].
[2]
RXTHIEN
0 = Disable interrupt
1 = Enable interrupt
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Receive FIFO Overflow Interrupt Enable
0 = Disable interrupt
[1]
[0]
RXOVIEN
RXUDIEN
1 = Enable interrupt
Receive FIFO Underflow Interrupt Enable
If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is
set to 1.
0 = Disable interrupt
1 = Enable interrupt
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I2S Status Register (I2S_STATUS)
Register
Offset
R/W
Description
Reset Value
I2S_STATUS
I2S_BA + 0x0C
R/W
I2S Status Register
0x0014_1000
31
30
TXCNT
22
29
28
27
26
25
24
RXCNT
23
LZCIF
15
21
TXBUSY
13
20
TXEMPTY
12
19
TXFULL
11
18
TXTHIF
10
17
TXOVIF
9
16
TXUDIF
8
RZCIF
14
Reserved
6
RXEMPTY
4
RXFULL
3
RXTHIF
2
RXOVIF
1
RXUDIF
0
5
7
Reserved
RIGHT
TXIF
RXIF
I2SIF
Table 5-117 I2S Status Register (I2S_STATUS, address 0x400A_000C)
Description
Bits
Transmit FIFO level (Read Only)
[31:28]
TXCNT
RXCNT
TXCNT = number of words in transmit FIFO.
Receive FIFO level (Read Only)
[27:24]
[23]
RXCNT = number of words in receive FIFO.
Left channel zero cross flag (write ‘1’ to clear, or clear LZCEN)
0 = No zero cross detected.
LZCIF
RZCIF
1 = Left channel zero cross is detected
Right channel zero cross flag (write ‘1’ to clear, or clear RZCEN)
0 = No zero cross
[22]
[21]
1 = Right channel zero cross is detected
Transmit Busy (Read Only)
This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It
is set when first data is loaded to Tx shift register.
TXBUSY
0 = Transmit shift register is empty
1 = Transmit shift register is busy
Transmit FIFO Empty (Read Only)
This is set when transmit FIFO is empty.
0 = Not empty
[20]
TXEMPTY
1 = Empty
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Transmit FIFO Full (Read Only)
This bit is set when transmit FIFO is full.
0 = Not full.
[19]
[18]
[17]
TXFULL
TXTHIF
TXOVIF
1 = Full.
Transmit FIFO Threshold Flag (Read Only)
When data word(s) in transmit FIFO is less than or equal to the threshold value set in
TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is
greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold
exceeded.
0 = Data word(s) in FIFO is greater than threshold level
1 = Data word(s) in FIFO is less than or equal to threshold level
Transmit FIFO Overflow Flag (Write ‘1’ to clear)
This flag is set if data is written to transmit FIFO when it is full.
0 = No overflow
1 = Overflow
Transmit FIFO underflow flag (Write ‘1’ to clear)
This flag is set if I2S controller requests data when transmit FIFO is empty.
0 = No underflow
[16]
[15:13]
[12]
TXUDIF
1 = Underflow
Reserved
Reserved
Receive FIFO empty (Read Only)
This is set when receive FIFO is empty.
RXEMPTY
RXFULL
0 = Not empty
1 = Empty
Receive FIFO full (Read Only)
This bit is set when receive FIFO is full.
[11]
[10]
[9]
0 = Not full.
1 = Full.
Receive FIFO Threshold Flag (Read Only)
When data word(s) in receive FIFO is greater than or equal to threshold value set in
RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less
than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.
RXTHIF
RXOVIF
0 = Data word(s) in FIFO is less than threshold level
1 = Data word(s) in FIFO is greater than or equal to threshold level
Receive FIFO Overflow Flag (Write ‘1’ to clear)
This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.
0 = No overflow
1 = Overflow
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Receive FIFO Underflow Flag (Write ‘1’ to clear)
This flag is set if attempt is made to read receive FIFO while it is empty.
[8]
RXUDIF
0 = No underflow
1 = Underflow
Reserved
Reserved
[7:4]
[3]
Right Channel Active (Read Only)
This bit indicates current data being transmitted/received belongs to right channel
RIGHT
0 = Left channel
1 = Right channel
I2S Transmit Interrupt (Read Only)
This indicates that there is an active transmit interrupt source. This could be TXOVIF,
TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To
clear interrupt the corresponding source(s) must be cleared.
[2]
TXIF
0 = No transmit interrupt
1 = Transmit interrupt occurred.
I2S Receive Interrupt (Read Only)
This indicates that there is an active receive interrupt source. This could be RXOVIF,
RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt
the corresponding source(s) must be cleared.
[1]
[0]
RXIF
I2SIF
0 = No receive interrupt
1 = Receive interrupt occurred
I2S Interrupt (Read Only)
This bit is set if any enabled I2S interrupt is active.
0 = No I2S interrupt
1 = I2S interrupt active
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I2S Transmit FIFO (I2S_TX)
Register
I2S_TX
Offset
R/W
Description
Reset Value
0x0000_0000
I2S_BA + 0x10
W
I2S Transmit FIFO Register
Table 5-118 I2S Transmit FIFO Register (I2S_TX, address 0x400A_0010)
Description
Bits
Transmit FIFO Register (Write Only)
A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight
words deep. The number of words currently in the FIFO can be determined by reading
I2S_STATUS.TXCNT.
[31:0]
TX
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I2S Receive FIFO (I2S_RX)
Register
I2S_RX
Offset
R/W
Description
Reset Value
0x0000_0000
I2S_BA + 0x14
R
I2S Receive FIFO Register
Table 5-119 I2S Receive FIFO Register (I2S_RX, address 0x400A_0014)
Description
Bits
Receive FIFO Register (Read Only)
A read of this register will pop data from the receive FIFO. The receive FIFO is eight
words deep. The number of words currently in the FIFO can be determined by reading
I2S_STATUS.RXCNT.
[31:0]
RX
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5.14 Cyclic Redundancy Check (CRC) Controller
5.14.1 Overview and Features
The ISD9160 contains a hardware CRC Generator for checking validity of data streams. The CRC
function supported is CRC-16-CCITT (x16 + x12 + x5 + 1). The hardware CRC allows very fast CRC
calculation without utilizing any CPU cycles.
The CRC Controller takes input of even sized packets (2, 4, 8 etc.) of up to 512 bytes long and
produces a 16bit CRC output. Input to the CRC Controller is via word access of 4 bytes (32 bits) at a
time. This word is configurable to either MSB first or LSB first format
5.14.2 Operation
The procedure to use the CRC Generator is as follows:
Write to CRC_CTL.MODE register to determine data format. A write to this register initializes
the packet counter.
Write to CRC_CTL.PKTLEN register to set the packet length (up to 512 bytes, even sizes
only, e.g. 2,4,8). A write to this register resets the CRC value to 0xFFFF.
A read of CRC_CHECKSUM will return 0xFFFF
Send data to CRC Generator (CRC_DAT) one (32bit) word at a time. CRC Generator extracts
bytes from the word in the order specified by the CRC_CTL.MODE control bit.
Current CRC result is available from CRC_CHECKSUM register four clock cycles after input
word written, including intermediate results. The CRC Generator will stop processing data
after CRC_CTL.PKTLEN+1 bytes are sent.
5.14.3 Example
The following is an example of using CRC Generation and Checking with a packet length of 4 bytes.
If the following code was executed:
CRC_CTL.PKTLEN = 3; // Initialize the CRC Generator for a 4 byte packet.
CRC_DAT = 0x2dcf4633; // Note data is sent MSB first in this mode.
Internally the CRC generator would perform the following CRC calculations:
Data In
initial
0x2D
0xCF
0x46
CRC
0xffff
0x143f
0x4516
0x2663
0x2194
0x33
The CRC result is 0x2194 after the byte sequence 0x2D, 0xCF, 0x46, 0x33 is processed by the
generator.
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The 2 byte result can be appended to the original data for checking as shown in the following table.
CRC_CTL.PKTLEN = 5; // Initialize the CRC Generator for a 6 byte packet.
CRC_DAT = 0x2dcf4633; // Note data is sent MSB first in this mode.
CRC_DAT = 0x21940000; // Note data is sent MSB first in this mode.
Data In
initial
0x2D
0xCF
0x46
CRC
0xffff
0x143f
0x4516
0x2663
0x2194
0x9400
0x0000
0x33
0x21
0x94
After parsing the 4 bytes data + 2 bytes of CRC result through the CRC Generator, the final result
should be 0 which indicates correct data has been transferred.
5.14.4 CRC Controller Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
CRC Base Address:
CRC_BA = 0x4009_0000
CRC_CTL
CRC_BA+0x00
CRC_BA+0x04
CRC_BA+0x08
R/W
R/W
R
CRC Enable Control Register
CRC Input Register
0x0000_0000
0x0000_0000
0x0000_FFFF
CRC_DAT
CRC_CHECKSUM
CRC Output Register
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5.14.5
CRC Control Register Description
CRC Enable Control
Register
Offset
R/W
Description
Reset Value
CRC_CTL
CRC_BA+0x00
R/W
CRC Enable Control Register
0x0000_0000
Table 5-120 CRC Enable Control Register
31
23
15
7
30
22
14
6
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
Reserved
20
16
Reserved
MODE
12
Reserved
4
8
PKTLEN[8]
0
1
PKTLEN[7:0]
Bits
[16]
Description
CRC LSB mode
Determines whether CRC Generator processes input words (32bit/4Bytes) LSB (least
significant byte) first or MSB (most significant byte) first.
0 = CRC input is MSB first (default).
1 = CRC input is LSB first.
MODE
For example if MODE aaa 1, and 0x01020304 is written to CRC_DAT, bytes will be
processed in order 0x04, 0x03, 0x02, 0x01. If MODE aaa 0, then order would be 0x01,
0x02, 0x3, 0x04.
Writing any value to this register will flush all previous calculations and restart a new
CRC calculation.
CRC Packet Length
Indicates number of bytes of CRC input to process. CRC calculation will stop once
input number of bytes aaa PKTLEN+1. Maximum packet size is 512 bytes, for
PKTLEN aaa 511.
[8:0]
PKTLEN
Writing any value to this register will flush all previous calculations and restart a new
CRC calculation.
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CRC Input
Offset
Register
R/W
Description
Reset Value
CRC_DAT
CRC_BA+0x04
R/W
CRC Input Register
0x0000_0000
Table 5-121 CRC Input Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
1
0
Bits
Description
CRC Input
The string of bytes to perform CRC calculation on.
When MODE aaa 0, CRC performs calculation byte by byte in the order DATA[31:24],
DATA[23:16], DATA[15:8], DATA[7:0].
When MODE aaa 1, CRC performs calculation byte by byte in the order DATA[7:0],
DATA[15:8], DATA[23:16], DATA[31:24].
[31:0]
DATA
If number of input bytes exceeds CRC Packet Length (CRC_CTL[8:0]+1), any
additional input bytes will be ignored.
The CRC generator takes four clock cycles to process the CRC input. Software must
ensure that at least four clock cycles occur between writes of CRC_DAT. Compiled
assembly language can be examined to ensure this requirement is met.
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CRC Output
Offset
Register
R/W
Description
Reset Value
CRC_CHECKSUM
CRC_BA+0x08
R
CRC Output Register
0x0000_FFFF
Table 5-122 CRC Output Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
CHECKSUM[15:8]
4
3
1
0
CHECKSUM[7:0]
Bits
Description
CHECKSUM
CRC Output
[15:0]
The result of CRC computation. The result is valid four clock cycles after last
CRC_DAT input data is written to CRC generator.
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5.15 PDMA Controller
5.15.1 Overview
The ISD9160 incorporates a Peripheral Direct Memory Access (PDMA) controller that transfers data
between SRAM and APB devices. The PDMA has four channels of DMA PDMA CH0~CH3). PDMA
transfers are unidirectional and can be Peripheral-to-SRAM, SRAM-to-Peripheral or SRAM-to-SRAM.
The peripherals available for PDMA transfer are SPI, UART, I2S, ADC and DPWM.
PDMA operation is controlled for each channel by configuring a source and destination address and
specifying a number of bytes to transfer. Source and destination addresses can be fixed, automatically
increment or wrap around a circular buffer. When PDMA operation is complete, controller can be
configured to provide CPU with an interrupt.
5.15.2 Features
Provides access to SPI, UART, I2S, ADC and DPWM peripherals.
AMBA AHB master/slave interface, transfers can occur concurrently with CPU access to flash
memory.
PDMA source and destination addressing modes allow fixed, incrementing, and wrap-around
addressing.
5.15.3 Block Diagram
SRAM
CortexM0
APB Bridge
AHB ARB
APB Bus
To
Peripherals
AHB ARB
AHB BUS1
AHB BUS2
PDMA
Service
Request
Signals
from
PDMA
Controller
Peripherals
PDMA
Control
Registers
Figure 5-64 PDMA Controller Block Diagram
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5.15.4 Function Description
The PDMA controller has four channels of DMA, each channel can be configured to one of the
following transfer types: Peripheral-to-SRAM SRAM-to-Peripheral or SRAM-to-SRAM. The SRAM and
the AHB-APB bus bridge each have an AHB bus arbiter that allows AHB bus access to occur either
from the CPU or the PDMA controller. The PDMA controller requests bus transfers over the AHB bus
from one address into a single word buffer within the PDMA controller then writes this buffer to another
address over the AHB bus. Peripherals with PDMA capability generate control signals to the PDMA
block requesting service when they need data (Rx request) or have data to transfer (Tx request). The
PDMA control registers reside in address space on the AHB bus.
Transfer completion can be determined by polling of status registers or by generation of PDMA
interrupt to CPU. A transfer is set up as a specified number of bytes from a source address to a
destination address. Both source and destination address can be configured as a fixed address, an
incrementing address or a wrap-around buffer address.
The general procedure to operate a DMA channel is as follows:
Enable PDMA channel n clock by setting PDMA_GLOCTL.CHCKEN
Enable PDMA channel n by setting PDMA_DSCTn_CTL.CHEN
Set source address in PDMA_DSCTn_ENDSA
Set destination address in PDMA_DSCTn_ENDDA
Set the transfer count in PDMA_TXBCCHn
Set transfer mode and address increment mode in PDMA_DSCTn_CTL
Route peripheral PDMA request signal to channel n in service selection register.
Trigger transfer PDMA_DSCTn_CTL.TXEN
If the source or destination address is not in wraparound mode, the PDMA will continue the transfer
until PDMA_CURBCCHn decrements to zero (CURBC is initialized to PDMA_TXBCCHn, in
wraparound mode, CURBC will reload and continue until CHEN is disabled). If an error occurs during
the PDMA operation, the channel stops until software clears the error condition and sets the
PDMA_DSCTn_CTL.SWRST bit to reset the PDMA channel. After reset the CHEN and TXEN bits
would need to be set to start a new operation.
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5.15.5 PDMA Controller Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
Register
Offset
R/W Description
Reset Value
PDMA Base Address:
PDMA_BA = 0x5000_8000+(0x100*x)
PDMA_DSCT0_CTL
PDMA_BA+0x00
PDMA_BA+0x04
R/W PDMA Control Register of Channel 0
0x0000_0000
PDMA Transfer Source Address Register of
Channel 0
PDMA_DSCT0_ENDSA
R/W
R/W
R/W
R
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XX00
0x0000_0000
0x0000_0000
PDMA Transfer Destination Address Register of
Channel 0
PDMA_DSCT0_ENDDA
PDMA_TXBCCH0
PDMA_BA+0x08
PDMA_BA+0x0C
PDMA_BA+0x10
PDMA_BA+0x14
PDMA Transfer Byte Count Register of Channel
0
PDMA Internal Buffer Pointer Register of
Channel 0
PDMA_INLBPCH0
PDMA_CURSACH0
PDMA Current Source Address Register of
Channel 0
R
PDMA Current Destination Address Register of
Channel 0
PDMA_CURDACH0
PDMA_CURBCCH0
PDMA_INTENCH0
PDMA_BA+0x18
PDMA_BA+0x1C
PDMA_BA+0x20
PDMA_BA+0x24
R
R
PDMA Current Byte Count Register of Channel 0 0x0000_0000
PDMA Interrupt Enable Control Register of
R/W
0x0000_0001
Channel 0
PDMA_CH0IF
R/W PDMA Interrupt Status Register of Channel 0
0x0000_0000
0x0000_0000
PDMA_DSCT1_CTL
PDMA_BA+0x100 R/W PDMA Control Register of Channel 1
PDMA Transfer Source Address Register of
PDMA_DSCT1_ENDSA
PDMA_DSCT1_ENDDA
PDMA_TXBCCH1
PDMA_BA+0x104 R/W
Channel 1
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XX00
0x0000_0000
0x0000_0000
PDMA Transfer Destination Address Register of
PDMA_BA+0x108 R/W
Channel 1
PDMA Transfer Byte Count Register of Channel
PDMA_BA+0x10C R/W
1
PDMA Internal Buffer Pointer Register of
Channel 1
PDMA_INLBPCH1
PDMA_BA+0x110
PDMA_BA+0x114
R
R
PDMA Current Source Address Register of
Channel 1
PDMA_CURSACH1
PDMA Current Destination Address Register of
Channel 1
PDMA_CURDACH1
PDMA_CURBCCH1
PDMA_INTENCH1
PDMA_BA+0x118
PDMA_BA+0x11C
R
R
PDMA Current Byte Count Register of Channel 1 0x0000_0000
PDMA Interrupt Enable Control Register of
PDMA_BA+0x120 R/W
0x0000_0001
Channel 1
PDMA_CH1IF
PDMA_BA+0x124 R/W PDMA Interrupt Status Register of Channel 1
PDMA_BA+0x200 R/W PDMA Control Register of Channel 2
0x0000_0000
0x0000_0000
PDMA_DSCT2_CTL
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PDMA Transfer Source Address Register of
Channel 2
PDMA_DSCT2_ENDSA
PDMA_DSCT2_ENDDA
PDMA_TXBCCH2
PDMA_BA+0x204 R/W
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XX00
0x0000_0000
0x0000_0000
PDMA Transfer Destination Address Register of
Channel 2
PDMA_BA+0x208 R/W
PDMA_BA+0x20C R/W
PDMA Transfer Byte Count Register of Channel
2
PDMA Internal Buffer Pointer Register of
Channel 2
PDMA_INLBPCH2
PDMA_BA+0x210
PDMA_BA+0x214
R
R
PDMA Current Source Address Register of
Channel 2
PDMA_CURSACH2
PDMA Current Destination Address Register of
Channel 2
PDMA_CURDACH2
PDMA_CURBCCH2
PDMA_INTENCH2
PDMA_BA+0x218
PDMA_BA+0x21C
R
R
PDMA Current Byte Count Register of Channel 2 0x0000_0000
PDMA Interrupt Enable Control Register of
PDMA_BA+0x220 R/W
0x0000_0001
Channel 2
PDMA_CH2IF
PDMA_BA+0x224 R/W PDMA Interrupt Status Register of Channel 2
PDMA_BA+0x300 R/W PDMA Control Register of Channel 3
0x0000_0000
0x0000_0000
PDMA_DSCT3_CTL
PDMA Transfer Source Address Register of
PDMA_DSCT3_ENDSA
PDMA_DSCT3_ENDDA
PDMA_TXBCCH3
PDMA_BA+0x304 R/W
Channel 3
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XX00
0x0000_0000
0x0000_0000
PDMA Transfer Destination Address Register of
PDMA_BA+0x308 R/W
Channel 3
PDMA Transfer Byte Count Register of Channel
PDMA_BA+0x30C R/W
3
PDMA Internal Buffer Pointer Register of
Channel 3
PDMA_INLBPCH3
PDMA_BA+0x310
PDMA_BA+0x314
R
R
PDMA Current Source Address Register of
Channel 3
PDMA_CURSACH3
PDMA Current Destination Address Register of
Channel 3
PDMA_CURDACH3
PDMA_CURBCCH3
PDMA_INTENCH3
PDMA_BA+0x318
PDMA_BA+0x31C
R
R
PDMA Current Byte Count Register of Channel 3 0x0000_0000
PDMA Interrupt Enable Control Register of
PDMA_BA+0x320 R/W
0x0000_0001
Channel 3
PDMA_CH3IF
PDMA_BA+0x324 R/W PDMA Interrupt Status Register of Channel 3
PDMA_BA+0xF00 R/W PDMA Global Control Register
0x0000_0000
0x0000_0000
0xFFFF_FFFF
0x0000_0000
PDMA_GLOCTL
PDMA_SVCSEL
PDMA_GLOBALIF
PDMA_BA+0xF04 R/W PDMA Service Selection Control Register
PDMA_BA+0xF0C
R
PDMA Global Interrupt Status Register
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5.15.6
PDMA Control Register Description
PDMA Control TXENl and Status Register (PDMA_DSCTn_CTL)(n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_DSCT0_CTL
PDMA_DSCT1_CTL
PDMA_DSCT2_CTL
PDMA_DSCT3_CTL
PDMA_BA+0x00 R/W
PDMA_BA+0x100 R/W
PDMA_BA+0x200 R/W
PDMA_BA+0x300 R/W
PDMA Control Register of Channel 0
PDMA Control Register of Channel 1
PDMA Control Register of Channel 2
PDMA Control Register of Channel 3
31
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
Reserved
TWIDTH
23
TXEN
15
17
Reserved
9
Reserved
WAINTSEL
Reserved
7
1
0
DASEL
SASEL
MODESEL
SWRST
CHEN
Table 5-123 PDMA Control and Status Register (PDMA_DSCTn_CTL, address 0x5000_8000 + n *
0x100)
Bits
[23]
Description
Trigger Enable – Start a PDMA operation
0 = Write: no effect. Read: Idle/Finished.
1 = Enable PDMA data read or write transfer.
TXEN
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA
channel, and then trigger again.
Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer
operation.
00 = One word (32 bits) is transferred for every PDMA operation.
[20:19]
TWIDTH
01 = One byte (8 bits) is transferred for every PDMA operation.
10 = One half-word (16 bits) is transferred for every PDMA operation.
11 = Reserved.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-
Memory) or Memory to IP mode (Memory-to-APB).
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Wrap Interrupt Select
x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated
when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt
could be generated when 16 bytes were sent.
WAINTSEL
[15:12]
xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated
when each PDMA transfer is wrapped. For example if BYTECNT aaa 32 then an interrupt could
be generated when 32 bytes were sent and PDMA wraps around.
x1x1: Both half and w interrupts generated.
Destination Address Select
This parameter determines the behavior of the current destination address register
with each PDMA transfer. It can either be fixed, incremented or wrapped.
00 = Transfer Destination Address is incremented.
01 = Reserved.
10 = Transfer Destination Address is fixed (Used when data transferred from multiple
addresses to a single destination such as peripheral FIFO input).
[7:6]
DASEL
11 = Transfer Destination Address is wrapped. When PDMA_CURBCCHn (Current
Byte Count) equals zero, the PDMA_CURDACHn (Current Destination Address) and
PDMA_CURBCCHn registers will be reloaded from the PDMA_DSCTn_ENDDA
(Destination Address) and PDMA_TXBCCHn (Byte Count) registers automatically and
PDMA will start another transfer. Cycle continues until software sets PDMACKEN=0.
When PDMACKEN is disabled, the PDMA will complete the active transfer but the
remaining data in the SBUF will not be transferred to the destination address.
Source Address Select
This parameter determines the behavior of the current source address register with
each PDMA transfer. It can either be fixed, incremented or wrapped.
00 = Transfer Source address is incremented.
01 = Reserved.
10 = Transfer Source address is fixed
[5:4]
SASEL
11 = Transfer Source address is wrapped. When PDMA_CURBCCHn (Current Byte
Count) equals zero, the PDMA_CURSACHn (Current Source Address) and
PDMA_CURBCCHn registers will be reloaded from the PDMA_DSCTn_ENDSA
(Source Address) and PDMA_TXBCCHn (Byte Count) registers automatically and
PDMA will start another transfer. Cycle continues until software sets PDMACKEN aaa
0. When PDMACKEN is disabled, the PDMA will complete the active transfer but the
remaining data in the SBUF will not be transferred to the destination address.
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
00 = Memory to Memory mode (SRAM-to-SRAM).
01 = IP to Memory mode (APB-to-SRAM).
[3:2]
MODESEL
10 = Memory to IP mode (SRAM-to-APB).
Software Engine Reset
0 = Writing 0 to this bit has no effect.
[1]
SWRST
1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents
of the control register will not be cleared. This bit will auto clear after a few clock
cycles.
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PDMA Channel Enable
Setting this bit to 1 enables PDMA’s operation. If this bit is cleared, PDMA will ignore
all PDMA request and force Bus Master into IDLE state.
[0]
CHEN
Note: SWRST will clear this bit.
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PDMA Transfer Source Address Register (PDMA_DSCTn_ENDSA)(n=0~3)
Offset R/W Description
Register
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_DSCT0_ENDSA
PDMA_DSCT1_ENDSA
PDMA_DSCT2_ENDSA
PDMA_DSCT3_ENDSA
PDMA_BA+0x04 R/W PDMA Transfer Source Address Register of Channel 0
PDMA_BA+0x104 R/W PDMA Transfer Source Address Register of Channel 1
PDMA_BA+0x204 R/W PDMA Transfer Source Address Register of Channel 2
PDMA_BA+0x304 R/W PDMA Transfer Source Address Register of Channel 3
Table 5-124 PDMA Source Address Register (PDMA_DSCTn_ENDSA, address 0x5000_8004 +
n*0x100)
Bits
Description
PDMA Transfer Source Address Register
[31:0]
ENDSA
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
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PDMA Transfer Destination Address Register (PDMA_DSCTn_ENDDA)(n=0~3)
Register
Offset
R/W Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_DSCT0_ENDDA
PDMA_DSCT1_ENDDA
PDMA_DSCT2_ENDDA
PDMA_DSCT3_ENDDA
PDMA_BA+0x08 R/W PDMA Transfer Destination Address Register of Channel 0
PDMA_BA+0x108 R/W PDMA Transfer Destination Address Register of Channel 1
PDMA_BA+0x208 R/W PDMA Transfer Destination Address Register of Channel 2
PDMA_BA+0x308 R/W PDMA Transfer Destination Address Register of Channel 3
Table 5-125 PDMA Destination Address Register (PDMA_DSCTn_ENDDA, address 0x5000_8008 +
n*0x100)
Bits
Description
PDMA Transfer Destination Address Register
[31:0]
ENDDA
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
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PDMA Transfer Byte Count Register (PDMA_TXBCCHn)(n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_TXBCCH0
PDMA_TXBCCH1
PDMA_TXBCCH2
PDMA_TXBCCH3
PDMA_BA+0x0C R/W
PDMA_BA+0x10C R/W
PDMA_BA+0x20C R/W
PDMA_BA+0x30C R/W
PDMA Transfer Byte Count Register of Channel 0
PDMA Transfer Byte Count Register of Channel 1
PDMA Transfer Byte Count Register of Channel 2
PDMA Transfer Byte Count Register of Channel 3
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
BYTECNT [15:8]
4
3
1
0
BYTECNT [7:0]
Table 5-126 PDMA Transfer Byte Count Register (PDMA_TXBCCHn, address 0x5000_800C +
n*0x100)
Bits
Description
[31:24]
Reserved
Reserved
PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
[15:0]
BYTECNT
Note: When in memory-to-memory (PDMA_DSCTn_CTL.MODESEL aaa 00b) mode,
the transfer byte count must be word aligned, that is multiples of 4bytes.
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PDMA Internal Buffer Pointer Register (PDMA_INLBPCHn)(n=0~3)
Register
Offset
R/W
Description
Reset Value
PDMA_INLBPCH0 PDMA_BA+0x10
R
PDMA Internal Buffer Pointer Register of Channel 0
PDMA Internal Buffer Pointer Register of Channel 1
PDMA Internal Buffer Pointer Register of Channel 2
PDMA Internal Buffer Pointer Register of Channel 3
0xXXXX_XX00
0xXXXX_XX00
0xXXXX_XX00
0xXXXX_XX00
PDMA_INLBPCH1
PDMA_INLBPCH2
PDMA_INLBPCH3
PDMA_BA+0x110 R
PDMA_BA+0x210 R
PDMA_BA+0x310 R
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
BUFPTR
Table 5-127 PDMA Internal Buffer Point Register (PDMA_INLBPCHn, address 0x5000_8010 +
n*0x100)
Bits
Description
[31:4]
Reserved
Reserved
PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a
write to the destination address. Internally this data is buffered in a 32bit register. If
transaction width between the read and write transactions are different, this register
tracks which byte/half-word of the internal buffer is being processed by the current
transaction.
[3:0]
BUFPTR
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PDMA Current Source Address Register (PDMA_CURSACHn) (n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_CURSACH0
PDMA_CURSACH1
PDMA_CURSACH2
PDMA_CURSACH3
PDMA_BA+0x14
R
PDMA Current Source Address Register of Channel 0
PDMA Current Source Address Register of Channel 1
PDMA Current Source Address Register of Channel 2
PDMA Current Source Address Register of Channel 3
PDMA_BA+0x114 R
PDMA_BA+0x214 R
PDMA_BA+0x314 R
Table 5-128 PDMA Current Source Address Register (PDMA_CURSACHn, address 0x5000_8014 +
n*0x100)
Bits
Description
PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring.
This register is loaded from PDMA_DSCTn_ENDSA when PDMA is triggered or when
a wraparound occurs.
[31:0]
CURSA
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PDMA Current Destination Address Register (PDMA_CURDACHn) (n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_CURDACH0
PDMA_CURDACH1
PDMA_CURDACH2
PDMA_CURDACH3
PDMA_BA+0x18
R
PDMA Current Destination Address Register of Channel 0
PDMA Current Destination Address Register of Channel 1
PDMA Current Destination Address Register of Channel 2
PDMA Current Destination Address Register of Channel 3
PDMA_BA+0x118 R
PDMA_BA+0x218 R
PDMA_BA+0x318 R
Table 5-129 PDMA Current Destination Address Register (PDMA_CURDACHn, address
0x5000_8018 + n*0x100)
Bits
Description
PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring.
This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when
a wraparound occurs.
[31:0]
CURDA
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PDMA Current Byte Count Register (PDMA_CURBCCHn) (n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_CURBCCH0
PDMA_CURBCCH1
PDMA_CURBCCH2
PDMA_CURBCCH3
PDMA_BA+0x1C
R
PDMA Current Byte Count Register of Channel 0
PDMA Current Byte Count Register of Channel 1
PDMA Current Byte Count Register of Channel 2
PDMA Current Byte Count Register of Channel 3
PDMA_BA+0x11C R
PDMA_BA+0x21C R
PDMA_BA+0x31C R
Table 5-130 PDMA Current Byte Count Register (PDMA_CURBCCHn, address 0x5000_801C +
n*0x100)
Bits
Description
[31:16]
Reserved
Reserved
PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is
initialized with PDMA_TXBCCHn register when PDMA is triggered or when a
wraparound occurs
[15:0]
CURBC
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PDMA Interrupt Enable Control Register (PDMA_INTENCHn) (n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0001
0x0000_0001
0x0000_0001
0x0000_0001
PDMA_INTENCH0
PDMA_INTENCH1
PDMA_INTENCH2
PDMA_INTENCH3
PDMA_BA+0x20 R/W
PDMA_BA+0x120 R/W
PDMA_BA+0x220 R/W
PDMA_BA+0x320 R/W
PDMA Interrupt Enable Control Register of Channel 0
PDMA Interrupt Enable Control Register of Channel 1
PDMA Interrupt Enable Control Register of Channel 2
PDMA Interrupt Enable Control Register of Channel 3
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
2
1
0
Reserved
WAINTEN
TXOKIEN
TXABTIEN
Table 5-131 PDMA Interrupt Enable Control Register (PDMA_INTENCHn, address 0x5000_8020 +
n*0x100)
Bits
Description
[31:3]
Reserved
Reserved
Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the
PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has
finished and has wrapped around and/or when the transaction is half way in progress.
This allows the efficient implementation of circular buffers for DMA.
[2]
WAINTEN
0 = Disable Wraparound PDMA interrupt generation.
1 = Enable Wraparound interrupt generation.
PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the
requested PDMA transfer is complete.
[1]
TXOKIEN
0 = Disable PDMA transfer done interrupt generation.
1 = Enable PDMA transfer done interrupt generation.
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PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a
PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel
must be reset to resume DMA operation.
[0]
TXABTIEN
0 = Disable PDMA transfer target abort interrupt generation.
1 = Enable PDMA transfer target abort interrupt generation.
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PDMA Interrupt Status Register (PDMA_CHnIF) (n=0~3)
Register
Offset
R/W
Description
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMA_CH0IF
PDMA_CH1IF
PDMA_CH2IF
PDMA_CH3IF
PDMA_BA+0x24 R/W
PDMA_BA+0x124 R/W
PDMA_BA+0x224 R/W
PDMA_BA+0x324 R/W
PDMA Interrupt Status Register of Channel 0
PDMA Interrupt Status Register of Channel 1
PDMA Interrupt Status Register of Channel 2
PDMA Interrupt Status Register of Channel 3
31
INTSTS
23
30
22
14
6
29
21
13
5
28
20
12
4
27
Reserved
19
26
18
10
2
25
17
9
24
16
8
Reserved
15
7
11
3
Reserved
WAIF
1
0
Reserved
TXOKIF
TXABTIF
Table 5-132 PDMA Interrupt Enable Status Register (PDMA_CHnIF, address 0x5000_8024 +
n*0x100)
Bits
Description
Interrupt Pin Status (Read Only)
INTSTS
[31]
This bit is the Interrupt pin status of PDMA channel.
[30:12]
Reserved
Reserved
Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or
half complete) are met. They are cleared by writing one to the bits.
[11:8]
WAIF
0001 aaa Current transfer finished flag (CURBC aaaaaa 0).
0100 aaa Current transfer half complete flag (CURBC aaaaaa BYTECNT/2).
Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It
is cleared by writing 1 to the bit.
[1]
TXOKIF
0 = Transfer ongoing or Idle.
1 = Transfer Complete.
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PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can
happen if attempt is made to read/write from invalid or non-existent memory space. It
occurs when PDMA controller receives a bus error from AHB master. Upon
occurrence PDMA will stop transfer and go to idle state. To resume, software must
reset PDMA channel and initiate transfer again.
[0]
TXABTIF
0 = No bus ERROR response received.
1 = Bus ERROR response received.
NOTE: This bit is cleared by writing 1 to itself.
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PDMA Global Control Register (PDMA_GLOCTL)
Register
Offset
R/W
Description
Reset Value
PDMA_GLOCTL
PDMA_BA+0xF00
R/W
PDMA Global Control Register
0x0000_0000
31
23
15
7
30
22
29
21
13
5
28
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
20
12
4
14
Reserved
6
CHCKEN
1
0
Reserved
SWRST
Table 5-133 PDMA Global Control Register (PDMA_GLOCTL, address 0x5000_8F00)
Bits
Description
[31:17]
Reserved
CHCKEN
Reserved
Reserved
PDMA Controller Channel Clock Enable Control
To enable clock for channel n CHCKEN[n] must be set.
CHCKEN[n] aaa 1: Enable Channel n clock
[11:8]
[7:1]
CHCKEN[n] aaa 0: Disable Channel n clock
Reserved
PDMA Software Reset
0 = Writing 0 to this bit has no effect.
[0]
SWRST
1 = Writing 1 to this bit will reset the internal state machine and pointers. The contents
of control register will not be cleared. This bit will auto clear after several clock cycles.
Note: This bit can reset all channels (global reset).
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PDMA Service Selection Control Register (PDMA_SVCSEL)
Register
Offset
R/W Description
Reset Value
PDMA_SVCSEL
PDMA_BA+0xF04
R/W PDMA Service Selection Control Register
0xFFFF_FFFF
PDMA peripherals have transmit and/or receive request signals to control dataflow during PDMA
transfers. These signals must be connected to the PDMA channel assigned by software for use with
that peripheral. For instance if PDMA Channel 3 is to be used to transfer data from memory to DPWM
peripheral, then DPWMTXSEL should be set to 3. This will route the DPWM transmit request signal to
PDMA channel 3, whenever DPWM has space in FIFO it will request transmission of data from PDMA.
When not used the selection should be set to 0xFF.
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
I2STXSEL
UARTXSEL
DPWMTXSEL
SPITXSEL
I2SRXSEL
UARTRXSEL
ADCRXSEL
SPIRXSEL
1
0
Table 5-134 PDMA Service Selection Control Register (PDMA_SVCSEL, address 0x5000_8F04)
Bits
Description
PDMA I2S Transmit Selection
I2STXSEL
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA
destination) request.
PDMA I2S Receive Selection
I2SRXSEL
This field defines which PDMA channel is connected to I2S peripheral receive (PDMA
source) request.
PDMA UART0 Transmit Selection
UARTXSEL
UARTRXSEL
DPWMTXSEL
This field defines which PDMA channel is connected to UART0 peripheral transmit
(PDMA destination) request.
PDMA UART0 Receive Selection
This field defines which PDMA channel is connected to UART0 peripheral receive
(PDMA source) request.
PDMA DPWM Transmit Selection
This field defines which PDMA channel is connected to DPWM peripheral transmit
(PDMA destination) request.
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PDMA ADC Receive Selection
[11:8]
[7:4]
[3:0]
ADCRXSEL
SPITXSEL
SPIRXSEL
This field defines which PDMA channel is connected to ADC peripheral receive
(PDMA source) request.
PDMA SPI0 Transmit Selection
This field defines which PDMA channel is connected to SPI0 peripheral transmit
(PDMA destination) request.
PDMA SPI0 Receive Selection
This field defines which PDMA channel is connected to SPI0 peripheral receive
(PDMA source) request.
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PDMA Global Interrupt Status Register (PDMA_GLOBALIF)
Register
Offset
R/W Description
PDMA Global Interrupt Status Register
Reset Value
PDMA_GLOBALIF
PDMA_BA+0xF0C
R
0x0000_0000
Table 5-135 PDMA Global Interrupt Status Register (PDMA_GLOBALIF, address 0x5000_8F0C)
Bits
Description
Interrupt Pin Status (Read Only)
GLOBALIF
[3:0]
GLOBALIF[n] is the interrupt status of PDMA channel n.
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6
FLASH MEMORY CONTROLLER (FMC)
6.1 Overview
The ISD9160 is available with 141K bytes of on-chip embedded Flash EEPROM for application
program and data flash memory. The memory can be updated through procedures for In-Circuit
Programming (ICP) through the ARM Serial-Wire Debug (SWD) port or via In-System Programming
(ISP) functions under software control. In-System Programming (ISP) functions enable user to update
program memory when chip is soldered onto PCB.
Main flash memory is divided into two partitions: Application Program ROM (APROM) and Data flash
(DATAF). In addition there are two other partitions, a 4K Byte Boot Loader ROM (LDROM), and
Configuration ROM (CONFIG).
Upon chip power-on, the Cortex-M0 CPU fetches code from APROM or LDROM determined by a boot
select configuration in CONFIG.
The boundary between APROM and user DATA Flash can be configured to any sector address
boundary. Erasable sector size is 1K Byte. This boundary is also specified in the CONFIG memory.
LDROM is a fixed 4K Byte in size, but if not required can be incorporated into the APROM address
space of the 141K Byte device for a total device memory of 145K Byte.
6.2 Features
AHB interface compatible
Runs up to 50 MHz with zero wait-state for continuous address read access
141KB application program memory (APROM)
4KB in system programming (ISP) boot loader program memory (LDROM)
Configurable data flash with 1k Bytes sector erase unit
Programmable data flash start address.
In System Program (ISP) capability to update on chip Flash EEPROM
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6.3 Flash Memory Controller Block Diagram
The flash memory controller consist of AHB slave interface, ISP control logic, writer interface and flash
macro interface timing control logic. The block diagram of flash memory controller is shown as
following:
Cortex-M0
Debug
Access
Port
AHB Lite
interface
AHB Bus
0x0002_33FF
AHB Slave
Interface
ICP
Writer
Interface
ISP
Controller
Flash
Operation
Control
Power On
Initialization
0x0000_0FFF
0x0000_0000
Application Memory
(APROM+DATA)
CBS=1
ISP Program
Memory (LDROM)
CBS=0
Data Out
Control
CONFIG &
MAP
0x0000_0000
Figure 6-1 Flash Memory Control Block Diagram
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6.4 Flash Memory Organization
The ISD9160 flash memory consists of Application Program (APROM) memory (141KB), data flash
(DATAF), ISP boot loader (LDROM) program memory (4KB), user configuration (CONFIG). User
configuration block provides 2 words that control system configuration, like flash security lock, boot
select, brown out voltage level and data flash base address. An additional 504Bytes are available in
CONFIG memory for the user to store custom configuration data. The first two CONFIG words are
loaded from CONFIG memory at power-on into device control registers to initialize certain chip
functions. The data flash start address (FMC_DFBA) is defined in CONFIG memory and determines
the relative size of the APROM and DATAF partitions.
Table 6-1 Memory Address Map
Block Name
APROM
Size
Start Address
0x0000_0000
End Address
141 KB
0x0002_33FF (141KB)
OR
DFBADR-1 if DFEN!=0
DATAF
LDROM
CONFIG
User Configurable
DFBADR
0x0002_33FF (141KB)
0x0010_0FFF
4 KB
512B
0x0010_0000
0x0030_0000
0x0030_01FF
The Flash memory organization is shown as below:
0x0030_01FF
User Configuration
CONFIG
0x0030_0000
0x0010_0FFF
ISP Loader
Program Memory
LDROM
0x0010_0000
Reserved
ISD9160: 0x0002_33FF
Data Flash
DATAF
DFBADR
Application
Program Memory
APROM
CONFIG1
0x0030_0004
0x0030_0000
CONFIG0
0x0000_0000
Figure 6-2 Flash Memory Organization
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6.5 Boot Selection
The ISD9160 provides an in-system programming (ISP) feature to enable user to update the
application program memory when the chip is mounted on a PCB. A dedicated 4KB boot loader
program memory is used to store ISP firmware. The user customizes this firmware to implement a
protocol specific to their system to download updated application code. This firmware could utilize
device peripherals such as UART, SPI or I2C to fetch new application code. The memory area from
which the ISD9160 boots is controlled by the CBS bit in Config0 register.
6.6 Data Flash (DATAF)
The ISD9160 provides a data flash partition for user to store non-volatile data such as audio
recordings. It accessed through ISP procedures via the Flash Memory Controller (FMC). The size of
each erasable sector is 1Kbyte and minimum write size is one word (4Bytes). An erase operation
resets all memory in sector to value 0xFF. A write operation can only change a ‘1’ bit to a ‘0’ bit. If a
subset of the sector needs to be changed, the entire 1KB sector must be copied to another page or
into SRAM in advance as entire sector must be erased before modification. Data flash and application
program memory share the same memory space. If DFENB bit in Config0 is enabled (‘0’), the data
flash base address is defined by FMC_DFBA and application program memory size is (X-N)KB and
data flash size is N KB, where X is the total device memory size (141KB) and N is number of Kbytes
(sectors) reserved for data flash. In addition, for the 141KB device, the LDROM partition can be
disabled and included in APROM/DATAF memory by setting the LDROM_EN configuration bit low
allowing a total of 145KB of memory available to APROM/DATAF.
ISD9160: 0x0002_43FF
X=
ISD9160: 0x0002_33FF
ISD9160: 141
Data Flash
DATAF
(N Kbytes)
Data Flash
DATAF
(N Kbytes)
DFBADR[31:0]=N*1024
Application
Program Memory
APROM
Application
Program Memory
APROM
Application
Program Memory
APROM
(145-N Kbytes)
(X-N Kbytes)
(X Kbytes)
0x0000_0000
DFENB=0,
LDROM_EN=0
DFENB=0
DFENB=1
Figure 6-3 Flash Memory Structure
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6.7 User Configuration (CONFIG)
6.7.1 Config0 (ISP Address = 0x0030_0000)
31
30
29
28
27
-
26
25
24
-
-
-
-
-
-
-
23
22
-
21
-
20
-
19
-
18
17
16
CBODEN
-
-
-
15
-
14
-
13
-
12
-
11
-
10
9
8
-
-
1
-
0
7
6
5
4
3
2
CBS
-
-
-
-
LDROMEN
LOCK
DFEN
Table 6-2 User Configuration Register 0 (Config0, address 0x0030_0000 accessible through ISP only)
Config0
Address = 0x0030_0000
Description
Bits
[31:23]
[23]
Reserved
Reserved
CBODEN
Brown Out Detector Enable
If set to ‘1’ the Brown Out Detector (BOD) will be enabled after power up. It will be
configured at lowest voltage (2.1V) and if brown out condition detected will trigger the
NMI interrupt to processor.
0=Disable brown out detect after power on
1= Enable
[22:8]
[7]
Reserved
Reserved
CBS
Configuration Boot Selection
0 = Chip will boot from LDROM,
1 = Chip will boot from APROM
[6:3]
[2]
Reserved
Reserved
LDROMEN
LDROM Control Bit
0=disable
1= enable
[1]
LOCK
Security Lock
0 = Flash data is locked,
1 = Flash data is not locked.
When flash data is locked, only device ID, Config0 and Config1 can be read by ICP
through serial debug interface. Other data is locked as 0xFFFFFFFF. Once locked no
SWD debugging is possible. ISP can read data anywhere regardless of LOCK bit
value.
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[0]
DFENB
Data Flash Enable Bar
When data flash is enabled, flash memory is partitioned between APROM and DATAF
memory depending on the setting of data flash base address in Config1 register. If set
to ‘0’ then no DATAF partition exists.
0 = Enable data flash
1 = Disable data flash
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6.7.2 Config1 (Address = 0x0030_0004)
Table 6-3 User Configuration Register 1 (Config1, address 0x0030_0004 accessible through ISP only)
Config1
Address = 0x0030_0004
Description
Bits
[31:20]
Reserved
Reserved
It is mandatory to program 0x00 to these Reserved bits
[19:0]
DFBADR
Data Flash Base Address
This pointer sets the address for the start of data flash memory. Address must be on a
1KB sector boundary so DFBADR[9:0] must be 0x000.
6.8 In-System Programming (ISP)
The program and data flash memory support both in hardware In-Circuit Programming (ICP) and
firmware based In-System programming (ISP). Hardware ICP programming mode uses the Serial-
Wire Debug (SWD) port to program chip. Dedicated ICE Debug hardware or ICP gang-writers are
available to reduce programming and manufacturing costs. For firmware updates in the field, the
ISD9160 provides an ISP mode allowing a device to be reprogrammed under software control.
ISP is performed without removing the device from the system. Various interfaces enable LDROM
firmware to fetch new program code from an external source. A common method to perform ISP would
be via a UART controlled by firmware in LDROM. In this scenario, a PC could transfer new APROM
code through a serial port. The LDROM firmware receives it and re-programs APROM through ISP
commands. An alternative might be to fetch new firmware from an attached SD-Card via the SPI
interface.
6.8.1 ISP Procedure
The ISD9160 will boot from APROM or LDROM from a power-on reset as defined by user
configuration bit CBS. If user desires to update application program in APROM, the FMC_ISPCTL.BS
can be set to ’1’ and a software reset issued. This will cause the chip to boot from LDROM. An
example flow diagram of the ISP sequence is shown in Figure 6-5.
The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL)) to gain access. This procedure is to protect the
flash memory from unintentional access.
To enable ISP functionality software must first ensure the ISP clock (CLK_AHBCLK.ISPCKEN) is
present then set the FMC_ISPCTL.ISPEN bit.
Several error conditions are checked after software writes the ISPTRIG register. If an error condition
occurs, ISP operation is not started and the ISP fail flag (FMC_ISPCTL.ISPFF) will be set instead. The
ISPFF flag will remain set until it is cleared by software. Subsequent ISP procedure can be started
even if ISPFF is set. It is recommended that software check ISPFF bit and clear it after each ISP
operation if set.
When ISPTRIG register is set, the CoretxM0 CPU will wait for ISP operation to finish, during this
period; peripherals operate as usual. If any interrupt requests occur, CPU will not service them until
ISP operation finishes. As the ISP functions affect the operation of the flash memory M0 instruction
pipeline should be flushed with an ISB (Instruction Synchronization Barrier) instruction after the ISP is
triggered.
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CPU writes ISPTRIG
HCLK
ss
HREADY
ss
ISP operation
CPU is halted but other peripherials keep working
Figure 6-4 ISP Operation Timing
Power
On
A
NO
CBS = 1 ?
Enable ISPEN
YES
C
Write
ISPADR/ ISPCMD/
ISPDAT
Fetch code from
LDROM
Fetch code from
APROM
Set ISPTRIG = 1
Update LD-ROM or
write DataFlash
Execute ISP?
End of Flash Operation
A
B
A
B
(Read ISPDAT)
Check ISPFF = 1?
Clear BS to 0 and set
SWRST = 1 to reboot in
APROM
End of ISP
operation
?
Clear ISPEN and return
to main program
NO
YES
B
C
Figure 6-5 Boot Sequence and ISP Procedure
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The ISP command set is shown in Table 6-4. Three registers determine the action of a command:
FMC_ISPCMD is the command register and accepts commands for reading ID registers and
read/write/erase of flash memory. The FMC_ISPADDR is the address register where the flash
memory address for access is written. FMC_ISPDAT is the data register that input data is written to
and return data read from. An ISP command is executed by setting FMC_ISPCMD, FMC_ISPDAT and
FMC_ISPADDR then writing to the trigger register ISPTRIG.
There is an ISP command to read the device ID register. This register returns a code that reports the
memory configuration of the ISD9160 part as given in Table 6-5.
Table 6-4 ISP Command Set
FMC_ISPCMD
CMD[5:0]
0x3x
FMC_ISPADDR
FMC_ISPDAT
ISP Mode
A21
x
A20
A[19:0]
D[31:0]
Standby
x
x
x
x
x
x
Read Company ID
Read Device ID
FLASH Page Erase
FLASH Program
FLASH Read
0x0B
x
Returns 0x0000_00DA
0x0C
x
0x00000 0x1D00_01nn. See Table 6-5
0x22
0
A[20] A[19:0]
A[20] A[19:0]
A[20] A[19:0]
x
0x21
0
Data input
Data output
x
0x00
0
CONFIG Page Erase 0x22
1
1
1
1
A[19:0]
A[19:0]
A[19:0]
CONFIG Program
CONFIG Read
0x21
0x00
1
Data input
Data output
1
Table 6-5 Device ID Memory Size
DID[7:4] Flash Size (KB)
145
DID[3:0]
RAM Size (KB)
8
3
12
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6.9 Flash Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
FMC Base Address:
FMC_BA=0x5000_C000
FMC_ISPCTL
FMC_ISPADDR
FMC_ISPDAT
FMC_ISPCMD
FMC_ISPTRG
FMC_DFBA
FMC_BA+0x00
FMC_BA+0x04
FMC_BA+0x08
FMC_BA+0x0C
FMC_BA+0x10
FMC_BA+0x14
R/W
R/W
R/W
R/W
R/W
R
ISP Control Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0xXXXX_XXXX
ISP Address Register
ISP Data Register
ISP Command Register
ISP Trigger Control Register
Data Flash Base Address
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6.10 Flash Control Register Description
ISP Control Register (FMC_ISPCTL)
The FMC_ISPCTL register is a protected register, user must first follow the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL)) to gain access.
Register
Offset
R/W
Description
Reset Value
FMC_ISPCTL
FMC_BA+0x00
R/W
ISP Control Register
0x0000_0000
7
6
5
4
3
-
2
-
1
0
SWRST
ISPFF
LDUEN
CFGUEN
BS
ISPEN
Table 6-6 ISP Control Register (FMC_ISPCTL, address 0x5000_C000)
Description
Bits
[7]
Software Reset
SWRST
Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset.
ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
[6]
[5]
ISPFF
(2) LDROM writes to itself.
(3) Destination address is illegal, such as over an available range.
Write 1 to clear.
LDROM Update Enable
LDROM update enable bit.
LDUEN
0 = LDROM cannot be updated
1 = LDROM can be updated when the MCU runs in APROM.
CONFIG Update Enable
0 = Disable
[4]
CFGUEN
1 = Enable
When enabled, ISP functions can access the CONFIG address space and modify
device configuration area.
[3:2]
Reserved
Reserved
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Boot Select
0 = APROM
1 = LDROM
[1]
[0]
BS
Modify this bit to select which ROM next boot is to occur. This bit also functions as
MCU boot status flag, which can be used to check where MCU booted from. This bit is
initialized after power-on reset with the inverse of CBS in Config0; It is not reset for
any other reset event.
ISP Enable
ISPEN
0 = Disable ISP function
1 = Enable ISP function
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ISP Address Register (FMC_ISPADDR)
Register
Offset
R/W
Description
Reset Value
FMC_ISPADDR
FMC_BA+0x04
R/W
ISP Address Register
0x0000_0000
Table 6-7 ISP Address Register (FMC_ISPADDR, address 0x5000_C004)
Bits
Description
ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP
operation are carried out on 32bit words only, consequently ISPARD[1:0] must be 00b
for correct ISP operation.
[31:0]
ISPADDR
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ISP Data Register (FMC_ISPDAT)
Register
Offset
R/W
Description
Reset Value
FMC_ISPDAT
FMC_BA+0x08
R/W
ISP Data Register
0x0000_0000
Table 6-8 ISP Data Register (FMC_ISPDAT, address 0x5000_C008)
Description
Bits
ISP Data Register
[31:0]
ISPDAT
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
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ISP Command (FMC_ISPCMD)
Register
Offset
R/W
Description
Reset Value
FMC_ISPCMD
FMC_BA+0x0C
R/W
ISP Command Register
0x0000_0000
Table 6-9 ISP Data Register (FMC_ISPCMD, address 0x5000_C00C)
Description
Bits
[31:6]
Reserved
Reserved
ISP Command
Operation Mode : CMD
Standby
Read
:
0x3X
0x00
0x21
0x22
0x0B
0x0C
:
[5:0]
CMD
Program
Page Erase
Read CID
Read DID
:
:
:
:
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ISP Trigger Control Register (FMC_ISPTRG)
The FMC_ISPTRG register is a protected register, user must first follow the unlock sequence (see
Protected Register Lock Key Register (SYS_REGLCTL)) to gain access.
Register
Offset
R/W
Description
Reset Value
FMC_ISPTRG
FMC_BA+0x10
R/W
ISP Trigger Control Register
0x0000_0000
Table 6-10 ISP Trigger Control Register (FMC_ISPTRG, address 0x5000_C010)
Bits
Description
[31:1]
Reserved
Reserved
ISP Start Trigger
Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically
when ISP operation is finished.
0 = ISP operation is finished
1 = ISP is on going
[0]
ISPGO
After triggering an ISP function M0 instruction pipeline should be flushed with a ISB
instruction to guarantee data integrity.
This is a protected register, user must first follow the unlock sequence (see Protected
Register Lock Key Register (SYS_REGLCTL)) to gain access.
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Data Flash Base Address Register (FMC_DFBA)
Register
Offset
R/W
Description
Reset Value
FMC_DFBA
FMC_BA+0x14
R
Data Flash Base Address
0xXXXX_XXXX
Table 6-11 Data Flash Base Address Register (FMC_DFBA, address 0x5000_C014)
Bits
Description
Data Flash Base Address
This register reports the data flash starting address. It is a read only register.
[31:0]
DFBA
Data flash size is defined by user’s configuration; register content is loaded from
Config1 when chip is reset.
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7
ANALOG SIGNAL PATH BLOCKS
This section describes the functional blocks that perform analog signal functions on the ISD9160. This
includes the ADC, DPWM Speaker Driver, PGA Gain Amplifier, Automatic Gain Control and a variety
of auxiliary analog functional blocks.
7.1 Audio Analog-to-Digital Converter (ADC)
7.1.1 Functional Description
The ISD9160 includes a 2nd Order Delta-Sigma Audio Analog-to-Digital converter providing SNR
>85dB and THD >70dB. The converter can run at sampling rates up to 6.144MHz while a configurable
decimation filter allows oversampling ratios of 64/128/192 and 384. This provides support for standard
audio sampling rates from 8kHz to 48kHz.
7.1.2 Features
Front-end PGA providing gain range of -12dB – 35dB.
Boost Gain stage of 0dD or 26dB.
Configurable OSR (Over Sampling Ratio) of 64/128/192/384
Configurable clock rate through master oscillator integer division.
Decimation signal can be used directly or passed to biquad filter for further filtering.
Audio data buffered to 8 word FIFO, accessible via APB and PDMA.
7.1.3 Block Diagram
Rate Convert/Decimator
-12dB
to 35dB
0dB/
26dB
PGA_INP
PGA_INN
From
MUX
SD
ADC
SINC
Filter
BIQUAD
FILTER
FIFO
PGA
BOOST
APB Bus
PDMA Interface
ALC
Figure 7-1 ADC Signal Path Block Diagram
SYSCLK->APBCLK.ADC_EN (APBCLK[28])
ADC_CLK
SD_CLK
HCLK
÷ (ADC_N+1)
SYSCLK->CLKDIV.ADC_N
(CLKDIV[23:16])
÷ CLK_DIV
SDADC->CLKDIV
Figure 7-2 ADC Clock Control
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7.1.4 Operation
The ADC is an Audio Delta-Sigma converter that operates by oversampling the analog input at low
resolution and decimating the result by an over-sampling ratio to obtain a high resolution output which
is pushed into the FIFO. The ultimate data rate is determined by the converter clock frequency
SDCLK, and the oversampling ratio.
The data stream generated by the ADC is most conveniently handled by PDMA which can load data
into a streaming audio buffer for further processing. Alternatively an interrupt driven approach can be
used to monitor the FIFO.
If FIFO is not serviced then oldest data is over-written such that the FIFO always contains the eight
most recent samples.
7.1.4.1 Determining Sample Rate
The maximum clock rate of the Delta-Sigma Converter is 6.144MHz. Best performance is gained with
clocks rates between 1.024MHz and 4.096MHz. Sample rate is given by the following formula:
Tables of common audio sample rates are provided below.
Table 7-1 Sample Rates for HCLK=49.152MHz
HCLK=49.152MHz
Sample Rate (Hz) for OSR
SD_CLK
ADC CLKDIV
64
128
192
384
16,000
8,000
5,333
4,000
2,667
8
6,144,000
3,072,000
2,048,000
1,536,000
1,024,000
96,000
48,000
32,000
24,000
16,000
48,000
24,000
16,000
12,000
8,000
32,000
16,000
10,667
8,000
16
24
32
48
5,333
Table 7-2 Sample Rates for HCLK=32.768MHz
Sample Rate (Hz) for OSR
HCLK=32.768MHz
SD_CLK
ADC CLKDIV
64
128
192
384
10,667
5,333
3,556
2,667
8
4,096,000
2,048,000
1,365,333
1,024,000
64,000
32,000
21,333
16,000
32,000
16,000
10,667
8,000
21,333
10,667
7,111
5,333
16
24
32
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Table 7-3 Sample Rates for HCLK=24.576MHz
Sample Rate (Hz) for OSR
HCLK=24.576MHz
SD_CLK
ADC CLKDIV
64
128
192
384
8
3,072,000
2,048,000
1,536,000
1,024,000
48,000
32,000
24,000
16,000
24,000
16,000
12,000
8,000
16,000
10,667
8,000
5,333
8,000
5,333
4,000
2,667
12
16
24
Table 7-4 Sample Rates for HCLK=16.384MHz
Sample Rate (Hz) for OSR
HCLK=16.384MHz
SD_CLK
ADC CLKDIV
64
128
192
384
10,667
5,333
2,667
1,778
1,333
4
4,096,000
2,048,000
1,024,000
682,667
64,000
32,000
16,000
10,667
8,000
32,000
16,000
8,000
5,333
4,000
21,333
10,667
5,333
3,556
2,667
8
16
24
32
512,000
7.1.4.2 Configuring Analog Path
To operate the ADC the entire analog path from analog input to ADC needs to be configured for
correct operation. This involves:
Selecting and powering up VMID reference.
Powering up modulator and reference buffers.
Selecting an input source with the analog MUX.
Configure sample rate and ADC clock source.
7.1.4.3 Interrupt Sources
The ADC can be configured to generate an interrupt when the data level in the FIFO exceeds a
defined threshold. The interrupt condition is only cleared by disabling the interrupt or reading values
from the FIFO. In addition two comparators can monitor the ADC FIFO output to generate interrupts
when set levels are exceeded.
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FIFO > INT.FIFO_IE_LEV
INT.IE
CMPF0
ADC_IRQ
ADCMPR[0].CMPIE
CMPF1
ADCMPR[1].CMPIE
Figure 7-3 SDADC Controller Interrupt
7.1.4.4 Peripheral DMA Request
Normal use of the ADC is with PDMA. In this mode ADC requests PDMA service whenever data is in
FIFO. PDMA channel will copy this data to a buffer and alert the CPU when buffer is full. In this way
an entire buffer of data can be collected without any CPU intervention.
7.1.5 ADC Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
Register
Offset
R/W
Description
Reset Value
ADC Base Address:
ADC_BA = 0x400E_0000
ADC_DAT
ADC_BA+0x00
ADC_BA+0x04
ADC_BA+0x08
ADC_BA+0x0C
ADC_BA+0x10
ADC_BA+0x14
ADC_BA+0x18
ADC_BA+0x1C
R
ADC FIFO Data Out.
0x0000_XXXX
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
ADC_CHEN
ADC_CLKDIV
ADC_DCICTL
ADC_INTCTL
ADC_PDMACTL
ADC_CMP0
ADC_CMP1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADC Enable Register
ADC Clock Divider Register
ADC Decimation Control Register
ADC Interrupt Control Register
ADC PDMA Control Register
ADC Comparator 0 Control Register
ADC Comparator 1 Control Register
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7.1.6 ADC Register Description
FIFO Audio Data Register (ADC_DAT)
Register
Offset
R/W
Description
Reset Value
ADC_DAT
ADC_BA+0x00
R
ADC FIFO Data Out.
0x0000_XXXX
Table 7-5 FIFO Audio Data Register (ADC_DAT, address 0x400E_0000)
Description
Bits
[31:16]
Reserved
Reserved
ADC Audio Data FIFO Read
A read of this register will read data from the audio FIFO and increment the read
pointer. A read past empty will repeat the last data. Can be used with FIFOINTLV
interrupt to determine if valid data is present in FIFO.
[15:0]
RESULT
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ADC Enable Register (ADC_CHEN)
Register
Offset
R/W
Description
Reset Value
ADC_CHEN
ADC_BA+0x04
R/W
ADC Enable Register
0x0000_0000
Table 7-6 ADC Enable Register (ADC_CHEN, address 0x400E_0004)
Description
Bits
[31:1]
Reserved
Reserved
ADC Enable
[0]
CHEN
0 = Conversion stopped and ADC is reset including FIFO pointers.
1 = ADC Conversion enabled.
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ADC Clock Division Register (ADC_CLKDIV)
Register
Offset
R/W
Description
Reset Value
ADC_CLKDIV
ADC_BA+0x08
R/W
ADC Clock Divider Register
0x0000_0000
Table 7-7 ADC Clock Divider Register (ADC_CLKDIV, address 0x400E_0008)
Bits
Description
[31:8]
Reserved
Reserved
ADC Clock Divider
This register determines the clock division ration between the incoming ADC_CLK
(aaa HCLK by default) and the Delta-Sigma sampling clock of the ADC. This together
with the over-sampling ratio (OSR) determines the audio sample rate of the converter.
CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz.
[7:0]
CLKDIV
CLKDIV must be greater than 2.
SD_CLK frequency aaa HCLK / CLKDIV
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ADC Decimation Control Register (ADC_DCICTL)
Register
Offset
R/W
Description
Reset Value
ADC_DCICTL
ADC_BA+0x0C
R/W
ADC Decimation Control Register
0x0000_0000
Table 7-8 ADC Decimation Control Register (ADC_DCICTL, address 0x400E_000C)
Bits
Description
CIC Filter Additional Gain
This should normally remain default 0. Can be set to non-zero values to provide
additional digital gain from the decimation filter. An additional gain is applied to signal
of GAIN/2.
GAIN
[19:16]
Decimation Over-Sampling Ratio
This term determines the over-sampling ratio of the decimation filter. Valid values are:
0: OVSPLRAT aaa 64
[3:0]
OVSPLRAT
1: OVSPLRAT aaa 128
2: OVSPLRAT aaa 192
3: OVSPLRAT aaa 384
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ADC Interrupt Control Register (ADC_INTCTL)
Register
Offset
R/W
Description
Reset Value
ADC_INTCTL
ADC_BA+0x10
R/W
ADC Interrupt Control Register
0x0000_0000
Table 7-9 ADC Interrupt Control Register (ADC_INTCTL, address 0x400E_0010)
Description
Bits
[31]
Interrupt Enable
INTEN
If set to ‘1’ an interrupt is generated whenever FIFO level exceeds that set in
FIFOINTLV.
FIFO Interrupt Level
Determines at what level the ADC FIFO will generate a servicing interrupt to the CPU.
Interrupt will be generated when number of words present in ADC FIFO is >
FIFOINTLV.
[2:0]
FIFOINTLV
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ADC PDMA Control Register (ADC_PDMACTL)
Register
Offset
R/W
Description
Reset Value
ADC_PDMACTL
ADC_BA+0x14
R/W
ADC PDMA Control Register
0x0000_0000
Table 7-10 ADC PDMA Control Register (ADC_PDMACTL, address 0x400E_0014)
Bits
[0]
Description
Enable ADC PDMA Receive Channel
RXDMAEN
Enable ADC PDMA. If set, then ADC will request PDMA service when data is
available.
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A/D Compare Register 0(ADCMPR0)
Register
Offset
R/W
Description
Reset Value
ADC_CMP0
ADC_BA+0x18
R/W
ADC Comparator 0 Control Register
0x0000_0000
31
23
15
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CMPDAT[15:8]
CMPDAT[7:0]
14
Reserved
6
CMPMCNT
7
1
0
CMPFLAG
Reserved
CMPCOND
ADCMPIE
CPMEN
Table 7-11 ADC Comparator Control Registers (ADC_CMP0, address 0x400E_0018)
Description
Bits
Comparison Data
[31:16]
[11:8]
CMPDAT
16 bit value to compare to FIFO output word.
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match
counter will increase by 1. When the internal counter reaches the value to (CMPMCNT +1), the
CMPFLAG bit will be set.
CMPMCNT
CMPFLAG
Compare Flag
[7]
[2]
When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1
to self.
Compare Condition
0= Set the compare condition that result is less than CMPDAT
1= Set the compare condition that result is greater or equal to CMPDAT
Note: When the internal counter reaches the value (CMPMCNT +1), the CMPFLAG bit will be set.
CMPCOND
ADCMPIE
ADCMPEN
Compare Interrupt Enable
0 = Disable compare function interrupt.
1 = Enable compare function interrupt.
[1]
[0]
If the compare function is enabled and the compare condition matches the setting of CMPCOND and
CMPMCNT, CMPFLAG bit will be asserted, if ADCMPIE is set to 1, a compare interrupt request is
generated.
Compare Enable
0 = Disable compare.
1 = Enable compare.
Set this bit to 1 to enable compare CMPDAT with FIFO data output.
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A/D Compare Register 1 (ADCMPR1)
Register
Offset
R/W
Description
Reset Value
ADC_CMP1
ADC_BA+0x1C
R/W
ADC Comparator 1 Control Register
0x0000_0000
31
23
15
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CMPDAT[15:8]
CMPDAT[7:0]
14
Reserved
6
CMPMCNT
7
1
0
CMPFLAG
Reserved
CMPCOND
ADCMPIE
CPMEN
Table 7-12 ADC Comparator Control Registers (ADC_CMP1, address 0x400E_001C)
Description
Bits
Comparison Data
[31:16]
[11:8]
CMPDAT
16 bit value to compare to FIFO output word.
Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match
counter will increase by 1. When the internal counter reaches the value to (CMPMCNT +1), the
CMPFLAG bit will be set.
CMPMCNT
CMPFLAG
Compare Flag
[7]
[2]
When the conversion result meets condition in ADCMPR0 this bit is set to 1. It is cleared by writing 1
to self.
Compare Condition
0= Set the compare condition that result is less than CMPDAT
1= Set the compare condition that result is greater or equal to CMPDAT
Note: When the internal counter reaches the value (CMPMCNT +1), the CMPFLAG bit will be set.
CMPCOND
ADCMPIE
ADCMPEN
Compare Interrupt Enable
0 = Disable compare function interrupt.
1 = Enable compare function interrupt.
[1]
[0]
If the compare function is enabled and the compare condition matches the setting of CMPCOND and
CMPMCNT, CMPFLAG bit will be asserted, if ADCMPIE is set to 1, a compare interrupt request is
generated.
Compare Enable
0 = Disable compare.
1 = Enable compare.
Set this bit to 1 to enable compare CMPDAT with FIFO data output.
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7.2 Audio Class D Speaker Driver (DPWM)
7.2.1 Functional Description
The ISD9160 includes a differential Class D (PWM) speaker driver capable of delivering 1W into an
8Ω load at 5V supply voltage. The driver works by up-sampling and modulating a PCM input to
differentially drive the SPK+ and SPK- pins. The speaker driver operates from its own independent
supply VCCSPK and VSSSPK. This supply should be well decoupled as peak currents from speaker
driver are large.
7.2.2 Features
Differential Bridge-Tied-Load structure to directly drive 8Ω Speaker.
Power delivery up to 1W @5V into 8Ω.
Power efficiency of up to 85%.
Configurable input sample rate.
16 Sample FIFO for audio output.
PDMA data channel for streaming of PCM audio data.
7.2.3 Block Diagram
VCCSPK
Non-
overlap
Gen.
SPK+
DPWM->CTRL
DPWM->ZOH_DIV
APB Bus
PDMA
Interface
VSSSPK
VCCSPK
CIC
Filter
SD
Modulator
FIFO
ZOH
Non-
overlap
Gen.
HCLK
SPK-
DPWM_CLK
VSSSPK
Figure 7-4 DPWM Block Diagram
7.2.4 Operation
The DPWM block receives audio data by writing 16bit PCM audio to the FIFO. FIFO is accessed
through PDMA for ease of streaming. The audio stream is sampled by a zero-order hold and fed to an
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up-sampling Cascaded Integrator Comb (CIC) filter with an up-sampling ratio of 64. The signal is then
modulated and sent to the driver stage through a non-overlap circuit. Master clock rate of the Delta-
Sigma modulator is controlled by DPWM_CLK. This clock is generated by the internal oscillator
(OSC48M) and operates at the frequency of OSC48M or 2x the frequency of OSC48M (See
CLK_CLKSEL1 register Table 5-36). Ultimate SNR (Signal-to-Noise Ratio) is determined by the time
resolution of the master clock.
7.2.4.1 Determining Sample Rate
The sample rate at which the DPWM block consumes audio data is given by:
Where HCLK is the master CPU clock rate and ZOHDIV is the divider control register. A table of
common audio sample rates is provided below.
Table 7-13 DPWM Sample Rates for Various HCLK
HCLK (MHz)
ZOHDIV
Sample
Rate (Hz)
49.152
49.152
49.152
32.768
32.768
32.768
24.576
24.576
24.576
24
48
96
16
32
64
12
24
48
32,000
16,000
8,000
32,000
16,000
8,000
32,000
16,000
8,000
7.2.4.2 Configuring Speaker Driver
To operate the speaker driver the following configuration is recommended:
Enable
DPWM
clock
source
(CLK_APBCLK0.DPWMCKEN
Table
5-33,
CLK_CLKSEL1.DPWMCKSEL Table 5-36).
Reset DPWM IP block. (SYS_IPRST1.DPWM_RST Table 5-4)
Select sample rate based on current HCLK frequency.
Setup PDMA channel to provide data to DPWM.
Enable PDMA Request.
Enable Driver.
7.2.4.3 Peripheral DMA Request
Normal use of the DPWM is with PDMA. In this mode DPWM requests PDMA service whenever there
is space in FIFO. PDMA channel will copy data from a streaming buffer to the DPWM and alert the
CPU when buffer is empty. In this way an entire buffer of data can be sent to DPWM without any CPU
intervention.
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7.2.5 DPWM Register Map
R: read only, W: write only, R/W: both read and write.
Register
Offset
R/W
Description
Reset Value
DPWM Base Address:
DPWM_BA = 0x4007_0000
DPWM_CTL
DPWM_BA+0x00 R/W
DPWM Control Register
0x0000_0000
0x0000_0002
0x0000_0000
0x0000_0000
0x0000_0030
DPWM_STS
DPWM_BA+0x04
R
DPWM FIFO Status Register
DPWM PDMA Control Register
DPWM FIFO Input
DPWM_DMACTL
DPWM_DATA
DPWM_ZOHDIV
DPWM_BA+0x08 R/W
DPWM_BA+0x0C
DPWM_BA+0x10 R/W
W
DPWM Zero Order Hold Division Register
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7.2.6 DPWM Register Description
DPWM Control Register (DPWM_CTL)
Register
Offset
R/W
Description
Reset Value
DPWM_CTL
DPWM_BA+0x00 R/W
DPWM Control Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
DPWMEN
DITHEREN
DEADTIME
MODUFRQ
Table 7-14 DPWM Control Register (DPWM_CTL, address 0x4007_0000)
Description
Bits
[6]
DPWM Enable
0= Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset
(FIFO data is not reset).
DPWMEN
1= Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO.
DPWM Signal Dither Control
To prevent structured noise on PWM output due to DC offsets in the input signal it is
possible to add random dither to the PWM signal. These bits control the dither:
[5:4]
DITHEREN
DEADTIME
0 = No dither.
1 = +/- 1 bit dither
3 = +/- 2 bit dither
DPWM Driver Deadtime Control
[3]
Enabling this bit will insert an additional clock cycle deadtime into the switching of
PMOS and NMOS driver transistors.
DPWM Modulation Frequency
This parameter controls the carrier modulation frequency of the PWM signal as a
proportion of DPWM_CLK.
MODUFRQ : DPWM_CLK Division : Frequency for DPWM_CLK aaa 98.304MHZ
0
1
2
3
4
5
6
7
:
:
:
:
:
:
:
:
228
156
76
:
:
:
:
:
:
:
:
431158
630154
1293474
1890462
126031
187603
248242
366806
[2:0]
MODUFRQ
52
780
524
396
268
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DPWM FIFO Status Register (DPWM_STS)
Register
Offset
R/W
Description
Reset Value
DPWM_STS
DPWM_BA+0x04 R
DPWM FIFO Status Register
0x0000_0002
Table 7-15 DPWM FIFO Status Register (DPWM_STS, address 0x4007_0004)
Bits
[1]
Description
FIFO Empty
EMPTY
0= FIFO is not empty
1= FIFO is empty
FIFO Full
[0]
FULL
0 = FIFO is not full.
1 = FIFO is full.
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DPWM PDMA Control Register (DPWM_DMACTL)
Register
Offset
R/W
Description
Reset Value
DPWM_DMACTL
DPWM_BA+0x08 R/W
DPWM PDMA Control Register
0x0000_0000
Table 7-16 DPWM PDMA Control Register (DPWM_DMACTL, address 0x4007_0008)
Bits
Description
[31:8]
Reserved
-
Enable DPWM DMA Interface
0= Disable PDMA. No requests will be made to PDMA controller.
[0]
DMAEN
1= Enable PDMA. Block will request data from PDMA controller whenever FIFO is not
empty.
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DPWM FIFO Input (DPWM_DATA)
Register
Offset
R/W
Description
Reset Value
DPWM_DATA
DPWM_BA+0x0C W
DPWM FIFO Input
0x0000_0000
Table 7-17 DPWM FIFO Input (DPWM_DATA, address 0x4007_000C)
Description
Bits
DPWM FIFO Audio Data Input
[15:0]
INDATA
A write to this register pushes data onto the DPWM FIFO and increments the write
pointer. This is the address that PDMA writes audio data to.
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DPWM ZOH Division (DPWM_ZOHDIV)
Register
Offset
R/W
Description
Reset Value
DPWM_ZOHDIV
DPWM_BA+0x10 R/W
DPWM Zero Order Hold Division Register
0x0000_0030
Table 7-18 DPWM Zero Order Hold Division Register (DPWM_ZOHDIV, address 0x4007_0010)
Bits
Description
DPWM Zero Order Hold, Down-Sampling Divisor
The input sample rate of the DPWM is set by HCLK frequency and the divisor set in
this register by the following formula:
[7:0]
ZOHDIV
Fs aaa HCLK/ZOHDIV/64
Valid range is 1 to 255. Default is 48, which gives a sample rate of 16kHz for a
49.152MHz (default) HCLK.
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7.3 Analog Comparator
7.3.1 Functional Description
ISD9160 contains two analog comparators. The comparator output is a logical one when positive input
greater than negative input, otherwise the output is a zero. Each comparator can be configured to
cause an interrupt when the comparator output value changes. The block diagram is shown in Figure
7-5.
Note that the analog input port pins must be configured as input type or analog alternate function
before Analog Comparator function is enabled.
7.3.2 Features
Analog input voltage range: 0~5.0V
Comparator 0 multiplexed to all analog enabled GPIO (GPIOB[7:0]).
Comparator 0 can compare against VBG or VMID.
Comparator 1 can compare GPIOB[7] to GPIOB[6] or VBG.
Single comparator interrupt requested by either comparator.
Can be used in conjunction with Capacitive Touch Sensing block for capacitive touch sensing.
7.3.3 Block Diagram
CMPSEL
CMP0CR.EN
+
GPIOB[7:0]
MUX
CMPSR.CO0
Comparator 0
-
VMID
VBG
M
U
X
CMP0CR.CN
CMP1CR.EN
GPIOB[6]
GPIOB[7]
+
CMPSR.CO1
M
U
X
-
VBG
Comparator 1
VBG = 1.2V
VMID = VCCA/2
CMP1CR.CN
Figure 7-5 Analog Comparator Block Diagram
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7.3.4
Operational Procedure
Setup Procedure
To use the Analog Comparator block, use the following sequence:
1. Configure GPIO for use as analog input by setting type to input.
2. Enable the peripheral clock (CLK_APBCLK0.ACMPCKEN)
3. Reset the Comparator block (SYS_IPRST1.ACMPRST, Table 5-4)
4. If using VMID ensure that VMID block is powered up (Section 7.4.4)
5. Select comparison sources with CMPnCR and ACMP_POSSEL.
6. Enable comparators and appropriate interrupts with CMPnCR.
7. Enables system interrupt if appropriate (e.g. NVIC_EnableIRQ(ACMP_IRQn); )
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Interrupt Sources
The comparator generates an output COn (n=0,1) which is reported in ACMP_STATUS register. If
CMPnCR.IE bit is set then a state change on the comparator output COn will cause comparator flag
CMPFn to go high and the comparator interrupt is requested. Software can write a one to CMPFn to
clear flag and interrupt request.
CMPSR.CMPF0
CMP0CR.IE
ACMP_IRQ
CMPSR.CMPF1
CMP1CR.IE
Figure 7-6 Comparator Controller Interrupt Sources
7.3.5 Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
ACMP Base Address:
ACMP_BA = 0x400D_0000
ACMP_CTL0
ACMP_BA+0x00 R/W
ACMP_BA+0x04 R/W
ACMP_BA+0x08 R/W
ACMP_BA+0x0C R/W
Analog Comparator 0 Control Register 0x0000_0000
Analog Comparator 1 Control Register 0x0000_0000
ACMP_CTL1
ACMP_STATUS
ACMP_POSSEL
Comparator Status Register
Comparator Select Register
0x0000_00XX
0x0000_0000
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7.3.6 Register Description
Comparator 0 Control Register (ACMP_CTL0)
Register
Offset
R/W
Description
Reset Value
ACMP_CTL0
ACMP_BA+0x00 R/W
Analog Comparator 0 Control Register
0x0000_0000
7
-
6
-
5
-
4
3
-
2
1
0
NEGSEL
ACMPIE
ACMPEN
Table 7-19 Comparator 0 Control Register (ACMP_CTL0, address 0x400D_0000).
Bits
[4]
Description
Comparator0 Negative Input Select
NEGSEL
ACMPIE
ACMPEN
0 = VBG, Bandgap reference voltage aaa 1.2V
1 = VMID reference voltage aaa VCCA/2
CMP0 Interrupt Enable
[1]
[0]
0 = Disable CMP0 interrupt function
1 = Enable CMP0 interrupt function
Comparator Enable
0 = Disable
1 = Enable
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Comparator 1 Control Register (ACMP_CTL1)
Register
Offset
R/W
Description
Reset Value
ACMP_CTL1
ACMP_BA+0x04 R/W
Analog Comparator 1 Control Register
0x0000_0000
7
-
6
-
5
-
4
3
-
2
1
0
NEGSEL
ACMPIE
ACMPEN
Table 7-20 Comparator 1 Control Register (ACMP_CTL1, address 0x400D_0004).
Bits
[4]
Description
Comparator1 Negative Input Select
NEGSEL
ACMPIE
ACMPEN
0 = GPIOB[7]
1 = VBG, Bandgap reference voltage aaa 1.2V
CMP1 Interrupt Enable
[1]
[0]
0 = Disable CMP1interrupt function
1 = Enable CMP1 interrupt function
Comparator Enable
0 = Disable
1 = Enable
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CMP Status Register (ACMP_STATUS)
Register
Offset
R/W
Description
Reset Value
ACMP_STATUS
ACMP_BA+0x08 R/W
Comparator Status Register
0x0000_00XX
7
6
5
4
3
2
1
0
Reserved
ACMPO1
ACMPO0
ACMPIF1
ACMPIF0
Table 7-21 CMP Status Register (ACMP_STATUS, address 0x400D_0008).
Bits
[3]
Description
Comparator1 Output
ACMPO1
Synchronized to the APB clock to allow reading by software. Cleared when the
comparator is disabled (CMP1EN aaa 0).
Comparator0 Output
[2]
[1]
[0]
ACMPO0
ACMPIF1
ACMPIF0
Synchronized to the APB clock to allow reading by software. Cleared when the
comparator is disabled (CMP0EN aaa 0).
Compare 1 Flag
This bit is set by hardware whenever the comparator output changes state. This bit will
cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
Compare 0 Flag
This bit is set by hardware whenever the comparator output changes state. This bit will
cause a hardware interrupt if enabled. This bit is cleared by writing 1 to itself.
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CMP Select Register (ACMP_POSSEL)
Register
Offset
R/W
Description
Reset Value
ACMP_POSSEL
ACMP_BA+0x0C R/W
Comparator Select Register
0x0000_0000
Table 7-22 CMP Select Register (ACMP_POSSEL, address 0x400D_000C).
Bits
Description
Comparator0 GPIO Selection
POSSEL
[2:0]
GPIOB[POSSEL] is the active analog GPIO input selected to Comparator 0 positive
input.
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7.4 Analog Functional Blocks
7.4.1 Overview
The ISD9160 contains a variety of analog functional blocks that facilitate audio processing, enable
analog GPIO functions (current source, relaxation oscillator, and comparator), adjust and measure
internal oscillator and provide voltage regulation. These blocks are controlled by registers in the
analog block address space. This section describes these functions and registers.
7.4.2 Features
VMID reference voltage generation.
Current source generation for AGPIO (Analog enabled GPIO).
LDO control for GPIOA[7:0] power domain and external device use.
Microphone Bias generator.
Analog Multiplexor.
Programmable Gain Amplifier (PGA).
OSC48M Frequency Control.
Capacitive Touch Sensing Relaxation Oscillator.
Oscillator Frequency Measurement block.
7.4.3 Register Map
R: read only, W: write only, R/W: read/write
Register
Offset
R/W Description
Reset Value
ANA Base Address:
ANA_BA = 0x4008_0000
ANA_VMID
ANA_BA+0x00
ANA_BA+0x08
ANA_BA+0x20
ANA_BA+0x24
ANA_BA+0x28
ANA_BA+0x2C
ANA_BA+0x50
ANA_BA+0x60
ANA_BA+0x64
ANA_BA+0x68
ANA_BA+0x84
ANA_BA+0x8C
R/W VMID Reference Control Register
0x0000_0007
0x0000_0000
0x0000_0000
0x0000_0001
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0010
0x0000_XXXX
0x0000_0000
ANA_CURCTL0
ANA_LDOSEL
ANA_LDOPD
ANA_MICBSEL
ANA_MICBEN
ANA_MUXCTL
ANA_PGACTL
ANA_SIGCTL
ANA_PGAGAIN
ANA_TRIM
R/W
Current Source Control Register
R/W LDO Voltage Select Register
R/W LDO Power Down Register
R/W Microphone Bias Select Register
R/W Microphone Bias Enable Register
R/W Analog Multiplexer Control Register
R/W PGA Enable Register
R/W Signal Path Control Register
R/W PGA Gain Select Register
R/W Oscillator Trim Register
ANA_CAPSCTL
R/W Capacitive Touch Sensing Control Register
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ANA_CAPSCNT
ANA_FQMMCTL
ANA_FQMMCNT
R
Capacitive Touch Sensing Count Register
R/W Frequency Measurement Control Register
Frequency Measurement Count Register
ANA_BA+0x90
ANA_BA+0x94
ANA_BA+0x98
0x0000_0000
0x0000_0001
0x0000_0000
R
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7.4.4 VMID Reference Voltage Generation
The analog path and blocks require a low noise, mid-rail, Voltage reference for operation, the VMID
generation block provides this. Control of this block allows user to power down the block, select its
power down condition and control over the reference impedance. The block consists of a switchable
resistive divider connected to the device VMID pin. A 4.7µF capacitor should be placed on this pin and
returned to analog ground (VSSA) as shown in Figure 7-7.
Before using the ADC, PGA or other analog blocks, the VMID reference needs to be enabled. A low
impedance option allows fast charging of the external noise de-coupling capacitor, while a higher
impedance options provides lower power consumption. A pulldown option allows the reference to be
discharged when off.
VCCA
Internal
Reference
R
R
VMID
VSSA
4.7uF
Figure 7-7 VMID Reference Generation
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VMID Control Register (ANA_VMID)
Register
Offset
R/W
Description
Reset Value
ANA_VMID
ANA_BA+0x00
R/W
VMID Reference Control Register
0x0000_0007
7
6
5
4
3
2
1
0
Reserved
PDHIRES
PDLORES
PULLDOWN
Table 7-23 VMID Control Register (ANA_VMID, address 0x4008_0000).
Bits
[2]
Description
Power Down High (360kΩ) Resistance Reference
PDHIRES
0= Connect the High Resistance reference to VMID. Use this setting for minimum power consumption.
1= The High Resistance reference is disconnected from VMID. Default power down and reset condition.
Power Down Low (4.8kΩ) Resistance Reference
0= Connect the Low Resistance reference to VMID. Use this setting for fast power up of VMID. Can be
turned off after 50ms to save power.
[1]
[0]
PDLORES
PULLDOWN
1= The Low Resistance reference is disconnected from VMID. Default power down and reset condition.
VMID Pulldown
0= Release VMID pin for reference operation.
1= Pull VMID pin to ground. Default power down and reset condition.
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7.4.5 GPIO Current Source Generation
The GPIOB port consists of analog enabled GPIO. One of the features of these pins is the ability to route a
current source to the pin. This is useful for a variety of purposes such as providing a current load to a sensor
such as a photo-transistor or CDS cell. It can also be used to do capacitive touch sensing in combination with
the relaxation oscillator control circuit.
The current generation block consists of
a
programmable current source controlled by
ANA_CURCTL0.VALSEL and individual switches to each of the GPIOB pins as shown in Figure 7-8. Power
control for this block is merged with the analog comparator, this block must be enabled to use current source
(ACMP_CTL0.ACMPEN=1).
Analog peripheral clock must be enabled before register can be written. At least one of the analog
comparators must be enabled to enable current source.
VCCA
ISRC.VAL[1:0]
ISRC.EN[0]
ISRC.EN[7]
GPIOB[7]
GPIOB[0]
Figure 7-8 GPIOB Current Source Generation
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Current Source Control Register (ANA_CURCTL0)
Register
Offset
R/W
Description
Reset Value
ANA_CURCTL0
ANA_BA+0x08
R/W
Current Source Control Register
0x0000_0000
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
Reserved
VALSEL
0
CURSRCEN
Table 7-24 GPIO Current Source Control Register (ANA_CURCTL0, address 0x4008_0008).
Bits
Description
[31:10]
Reserved
Reserved
Current Source Value
Select master current for source generation
0= 0.5 uA
1= 1 uA
[9:8]
[7:0]
VALSEL
2= 2.5 uA
3= 5 uA
Enable Current Source to GPIOB[x]
Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source.
CURSRCEN
0 = Disable
1 = Enable current source to pin GPIOB[x]
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7.4.6 LDO Power Domain Control
The ISD9160 provides a Low Dropout Regulator (LDO) that provides power to the I/O domain of GPIOA[7:0].
Using this regulator device can operate from a 5V supply rail and generate a 2.4-3.3V regulated supply to
operate the GPIOA[7:0] domain and external loads up to 30mA. The supply pin for the LDO is the VCCLDO
pin which should be connected to VCCD. If the LDO is not used, both VCCLDO and VD33 should be tied to
VCCD. Upon POR or reset the default condition of the LDO is off, meaning supply will be high impedance.
Software must configure the LDO before GPIOA[7:0] is usable (unless VD33=VCCD).
VCCLDO
LDOSET[1:0]
LDO
LDOPD[1:0]
To load
VD33
GPIOA[7]
0.1µF
1µF
GPIOA[0]
VSSD
Figure 7-9 LDO Power Domain
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LDO Voltage Control Register (ANA_LDOSEL)
Register
Offset
R/W
Description
Reset Value
ANA_LDOSEL
ANA_BA+0x20
R/W
LDO Voltage Select Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
LDOSEL
Table 7-25 LDO Voltage Control Register (ANA_LDOSEL, address 0x4008_0020).
Description
Reserved
Bits
[31:2]
Reserved
Select LDO Output Voltage
Note that maximum I/O pad operation speed only specified for voltage >2.4V.
0= 3.0V
1= 1.8V
2= 2.4V
3= 3.3V
[1:0]
LDOSEL
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LDO Power Down Register (ANA_LDOPD)
Register
Offset
R/W
Description
Reset Value
ANA_LDOPD
ANA_BA+0x24
R/W
LDO Power Down Register
0x0000_0001
7
6
5
4
3
2
1
0
Reserved
DISCHAR
PD
Table 7-26 LDO Power Down Control Register (ANA_LDOPD, address 0x4008_0024).
Bits
[1]
Description
Discharge
DISCHAR
0 = No load on VD33
1 = Switch discharge resistor to VD33.
Power Down LDO
When powered down no current delivered to VD33.
0= Enable LDO
[0]
PD
1= Power Down.
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7.4.7 Microphone Bias Generator
The ISD9160 provides a microphone bias generator (MICBIAS) for improved recording quality. The MICBIAS
can provide a maximum current of 1mA with a -60dB power supply rejection. The MICBIAS output voltage
can be configured with ANA_MICBSEL[1:0] to select bias voltages from 50% to 90% of the VCCA supply
voltage (see description below). The user should consider the microphone manufacturers specification in
deciding on the optimum MICBIAS voltage to use. Generally, a microphone will require a current of 0.1mA to
a maximum 0.5mA and a voltage of 1V to 3V across it.
Referring to the application diagram of Figure 7-11, external resistor
the current to a maximum that can be provided by MICBIAS; 1mA. On the ISD9160, the minimum total
resistance is 4Kohms. MICBIAS output voltage should be such that the following condition is met:
and
values are selected to limit
where is the desired voltage across the microphone from specification and
microphone (0.1-0.5mA)
is the current through the
From Figure 7-11, MIC_IN1 and MIC_IN2 are AC coupled to the ISD9160 MIC+ and MIC- respectively for
differential inputs. In single-ended operation, MIC_IN1 should go to MIC- of the ISD9160. and are AC
increased to at least 4Kohms.
to provide additional rejection from ground noise.
coupling capacitors. In single-ended application,
can be removed and
For improved performance, it is recommended to keep
VREF
MICBIAS
R
R
MICBSEL[1:0]
Figure 7-10 MICBIAS Block Diagram
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MICBIAS
MICBIAS
C3
4.7µF
R1
C1
1µF
MIC_IN1
MIC+
MIC-
C2
1µF
VS
MIC_IN2
R2
Figure 7-11 MICBIAS Application Diagram
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Microphone Bias Select (ANA_MICBSEL)
Register
Offset
R/W
Description
Reset Value
ANA_MICBSEL
ANA_BA+0x28
R/W
Microphone Bias Select Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
2
1
0
Reserved
REFSEL
VOLSEL
Table 7-27 Microphone Bias Selection Register (ANA_MICBSEL, address 0x4008_0028).
Description
Bits
[31:3]
Reserved
Reserved
Select Reference Source For MICBIAS Generator
VMID provides superior noise performance for MICBIAS generation and should be used unless fixed
voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used
as reference.
[2]
REFSEL
0= VMID aaa VCCA/2 is reference source.
1= VBG (bandgap voltage reference) is reference source.
Select Microphone Bias Voltage
MICBMODE aaa 0
0: 90% VCCA
1: 65% VCCA
2: 75% VCCA
3: 50% VCCA
MICBMODE aaa 1
0: 2.4V
[1:0]
VOLSEL
1: 1.7V
2: 2.0V
3: 1.3V
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Microphone Bias Enable Register (ANA_MICBEN)
Register
Offset
R/W
Description
Reset Value
ANA_MICBEN
ANA_BA+0x2C
R/W
0x0000_0000
Microphone Bias Enable Register
7
6
5
4
3
2
1
0
Reserved
MUXEN
Table 7-28 Microphone Bias Enable Register (ANA_MICBEN, address 0x4008_002C)
Bits
[0]
Description
Enable Microphone Bias Generator
MICBEN
0 = Powered Down.
1 = Enabled.
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7.4.8 Analog Multiplexer
The ISD9160 provides an analog multiplexer (AMUX) which allows the PGA input to be switched from the
dedicated MICP/MICN analog inputs to any of the analog enabled GPIO (GPIOB[7:0]). The negative input of
the PGA connects to GPIOB[7:0], while the positive PGA input connects to the odd numbered GPIOB[7:1].
Figure 7-12 shows the multiplexer block diagram and Table 7-29 shows the multiplexer control signals.
ANALOG MUX
MIC_INN
GPIOB[0]
MIC_INP
GPIOB[1]
GPIOB[3]
GPIOB[1]
GPIOB[2]
GPIOB[3]
PGA_INP
PGA_INN
GPIOB[5]
GPIOB[7]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]
I_PTAT
Figure 7-12 Analog Multiplexer Block Diagram
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Analog Multiplexer Control Register (ANA_MUXCTL)
Register
Offset
R/W
Description
Reset Value
ANA_MUXCTL
ANA_BA+0x50
R/W
Analog Multiplexer Control Register
0x0000_0000
15
Reserved
7
14
MUXEN
6
13
PGAINSEL
5
12
PTATCUR
4
11
3
10
2
9
1
8
0
POSINSEL
NEGINSEL
Table 7-29 Analog Multiplexer Control Register (ANA_MUXCTL, address 0x4008_0050).
Bits
Description
Reserved
[31:15]
Reserved
Enable The Analog Multiplexer
0 = All channels disabled
[14]
MUXEN
1 = Selection determined by register setting.
[13]
[12]
PGAINSEL
PTATCUR
Select MICP/MICN To PGA Inputs
Select PTAT Current
I_PTAT, to PGA_INN, negative input to PGA, for temperature measurement.
Selects Connection Of GPIOB[7,5,3,1] To PGA_INP, Positive Input Of PGA
1000b: GPIOB[7] connected to PGA_INP
[11:8]
[7:0]
POSINSEL
NEGINSEL
0100b: GPIOB[5] connected to PGA_INP
0010b: GPIOB[3] connected to PGA_INP
0001b: GPIOB[1] connected to PGA_INP
Selects Connection Of GPIOB[7:0] To PGA_INN, Negative Input Of PGA
If NEGINSEL[n] aaa 1 then GPIOB[n] is connected to PGA_INN.
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Temperature Sensor Measurement
In addition, the multiplexer can route a PTC (positive temperature coefficient) current, PTAT current, to the
ADC to perform temperature measurements. To configure the signal path to do temperature measurement,
configure the ADC path as follows:
1) Enable the multiplexer, PGA, IPBOOST, and sigma-delta modulator. (See Section 7.4.9, Section 7.1).
2) Have the multiplexer select I_PTAT current as input and choose VBG (bandgap voltage ) as reference
(REFSEL).
3) Set the 6-bit ANA_PGAGAIN[5:0] gain value to hex 0x17 and choose 0dB gain setting for IPBOOST gain
block.
4) The temperature can be inferred by the information given in Table 7-30 and equation below.
T (°C) = 27 + (ADC_VAL-0x42EA)/50. (Equation 7-1)
The settings corresponding to this configuration are:
ANA_SIGCTL=0x1E, ANA_PGACTL=0x07, ANA_MUXCTL=0x5000, ANA_PGAGAIN=0x17
Table 7-30 Temperature Sensor Measurement.
Specification (Reference)
Test Condition
Parameter
Min.
Typ.
Max.
Unit
Code
LSB/oC
At 27o C
Temperature Sensor Output
0x42EA
Temperature Sensor Delta Coefficient
(number of bits per degree oC)**
50
Relative to 27oC
**LSB is the least significant bit of a 16-bit ADC with a defined full-scale RMS input voltage of 0.77V
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7.4.9 Programmable Gain Amplifier
The ISD9160 provides a Programmable Gain Amplifier (PGA) as the front-end to the ADC to allow the
adjustment of signal path gain. It is used in conjunction with the ALC block to provide automatic level control
of incoming audio signals. Figure 7-13 shows the signal path diagram. The PGA provides a gain from -12dB
to 35.25dB in increments of 0.75dB steps using a 6-bit control, ANA_PGAGAIN[5:0]. The gain is
monotonically increasing with 0x00 for lowest gain (-12dB) and 0x3f for the maximum gain (35.25dB). The
signal path is enabled by powering up the gain elements (PUPGA, PUBOOST). The PGA and IP BOOST
blocks can be muted with the ANA_SIGCTL register. Input to the PGA can be either differential or single-
ended on the PGA_INN input. The Analog MUX controls connection of the signal path to external pins. PGA
input impedance varies based on the gain setting. Table 7-31 shows a table of input impedance for different
gain setting.
The IP BOOST block can provide 0dB or 26dB of gain to provide a maximum gain of 61dB in the signal path.
Front-end anti-alias filtering for the sigma-delta ADC is also provided by PGA/IP-BOOST blocks with an
attenuation of -45dB at 6MHz frequency. The signal path defaults to have VCCA/2 as the reference voltage.
Rate Convert/ Decimator
PGA_INN
2nd SD
ADC
Sinc
Filter
Digital
Decimator
Digital
Filter
IPBOOST
PGA
MUX
PGA_INP
0dB/
-12dB to
26dB
35.25dB
in
ALC
0.75dB
step
Figure 7-13 PGA Signal Path Block Diagram
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Mute
PGA_GAIN_SEL[5:0]
R
PGA_GAIN_SEL[5:0]
R
PGA_INN
PGA_INP
`
R
To
IPBOOST
-12 dB to +35.25 dB
PGA_GAIN_SEL[5:0]
R
VREF
Figure 7-14 PGA Structure
Table 7-31 PGA Input Impedance Variation with Gain Setting
Gain (dB)
-12
-9
-6
-3
0
3
6
9
12
18
30
35.2
MICN Impedance (kΩ) 75
MICP Impedance (kΩ) 94
69
94
63
94
55
94
47
94
35
94
31
94
25
94
19
94
11
94
2.9
94
1.6
94
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PGA Enable Register (ANA_PGACTL)
Register
Offset
R/W
Description
Reset Value
ANA_PGACTL
ANA_BA+0x60
R/W
PGA Enable Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
BSTGAIN
PUBOOST
PUPGA
REFSEL
Table 7-32 PGA Enable and Control Register (ANA_PGACTL, address 0x4008_0060)
Bits
[3]
Description
Boost Stage Gain Setting
BSTGAIN
0 = Gain aaa 0dB.
1 = Gain aaa 26dB
Power Up Control For Boost Stage Amplifier
This amplifier must be powered up for signal path operation.
0 = Power Down.
[2]
[1]
PUBOOST
PUPGA
1 = Power up.
Power Up Control For PGA Amplifier
This amplifier must be powered up for signal path operation.
0 = Power Down.
1 = Power up.
Select Reference For Analog Path
Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to
VBG aaa 1.2V.
[0]
REFSEL
0 = Select VMID voltage as analog ground reference.
1 = Select Bandgap voltage as analog ground reference.
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Signal Path Control Register (ANA_SIGCTL)
Register
Offset
R/W
Description
Reset Value
ANA_SIGCTL
ANA_BA+0x64
R/W
Signal Path Control Register
0x0000_0000
7
6
5
4
3
2
1
0
Reserved
MUTEBST
MUTEPGA
PUADCOP
PUCURB
PUBUFADC
PUBUFPGA
PUZCDCMP
Table 7-33 Signal Path Mute Control Register (ANA_SIGCTL, address 0x4008_0064)
Bits Description
Boost Stage Mute Control
0 = Normal.
[6]
[5]
MUTEBST
MUTEPGA
1 = Signal Muted.
PGA Mute Control
0 = Normal.
1 = Signal Muted.
Power Up ADC ΣΔ Modulator
This block must be powered up for ADC operation.
0 = Power down.
[4]
[3]
[2]
[1]
PUADCOP
PUCURB
1 = Power up.
Power Up Control For Current Bias Generation
This block must be powered up for signal path operation.
0 = Power down.
1 = Power up.
Power Up Control For ADC Reference Buffer
This block must be powered up for signal path operation.
0 = Power down.
PUBUFADC
PUBUFPGA
1 = Power up.
Power Up Control For PGA Reference Buffer
This block must be powered up for signal path operation.
0 = Power down.
1 = Power up.
Power Up And Enable Control For Zero Cross Detect Comparator
When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal
threshold. To operate ZCD the ALC peripheral clock (CLK_APBCLK0.BFALCKEN) must also be
enabled and BIQ_CTL.DLCOEFF aaa 1 to allow ZCD clocks to be generated.
[0]
PUZCDCMP
0 = Power down.
1 = Power up and enable zero cross detection.
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PGA GAIN Control Register (ANA_PGAGAIN)
Register
Offset
R/W
Description
Reset Value
ANA_PGAGAIN
ANA_BA+0x68
R/W
PGA Gain Select Register
0x0000_0010
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
GAINREAD
GAINSET
7
1
0
Reserved
Table 7-34 PGA Gain Control Register (ANA_PGAGAIN, address 0x4008_0068)
Description
Bits
Current PGA Gain
[13:8]
GAINREAD
GAINSET
Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA
gain.
Select The PGA Gain Setting
[5:0]
From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is
largest gain at 35.25dB.
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7.4.10 Capacitive Touch Sensing Relaxation Oscillator/Counter
The ISD9160 provides a functional unit that is used with analog GPIO functions to form a relaxation oscillator.
The major application of this function is to measure the capacitive load on a GPIO pin. This measurement
allows the user to implement a capacitive touch sensing scheme. With appropriate touch sensor design, the
capacitance of the sensor will change appreciably in the presence of a finger, and the Capacitive Touch
Sensing Relaxation Oscillator can measure this.
This block us used in conjunction with the analog comparator block and current source block to form a
relaxation oscillator and counter circuit that can sense capacitance changes. A block diagram of the system is
shown in Figure 7-15.
GPIOB[n]
VCCA
CO0
ISRC.VAL[1:0]
GPIOB_OEN[n]
ISRC Current Source
PCLK
ISRC.EN[n]
0
CAPS_CNT
n
GPIOB_OEN[n]
ENB
GPIOB[n]
GPIOB_ALT[n]=2
Csense
Cpar
CYCLE_CNT
LOW_TIME
ANA->CAPS_CNT
CAPS_IRQ
EN
Prog. One shot
TRIG
PCLK
Counter
+
CO1
RESET_CNT
VREF
-
ACMP Comparator 0
Figure 7-15 Capacitive Touch Sensing Function Block Diagram
7.4.10.1 Functional Description
The principle behind the operation of this block is that a certain capacitance is present on one of the
analog enabled GPIO (GPIOB[7:0]). This capacitance consists of a certain parasitic capacitance
and the capacitor that is to be sensed
. The GPIO is configured into the Capacitive Touch
Sensing mode by setting SYS_GPB_MFP.GPBn = 2 and enabling a current source to this pin
(ANA_CURCTL0.CURSRCEN = 2^n). The Analog Comparator 0 is also setup to compare the voltage
at the pin to a reference voltage (ACMP_POSSEL = n, ACMP_CTL0.ACMPEN = 1).
In this configuration the circuit will charge the total capacitance with current ANA_CURCTL0.VALSEL
= 0.5µA-5µA. When the voltage reaches the reference voltage (normally set to VBG=1.2V), the
Capacitive Touch Sensing block will reset the GPIO pin to 0V. The circuit can be configured to do this
2^CYCLECNT times before generating an interrupt. While the capacitor is charging, a 24bit counter is
also enabled such that the total charge time is recorded. After completion of 2^CYCLES_CNT cycles
the software can read the ANA_CAPSCNT register to get a value proportional to the total capacitance
on the pin. Once this is done, the count can be reset with RSTCNT and a new measurement started
either on the same GPIO or selecting a different GPIO.
7.4.10.2 Design Considerations
Selecting parameters for capacitive touch sensing measurement is a trade-off between speed and
accuracy/noise immunity. The higher the current source setting, the faster the oscillation but lower the
resolution. The higher the cycle count the slower the measurement but the higher the accuracy and
noise immunity.
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7.4.10.3 Register Descriptions
Capacitive Touch Sensing Control Register (ANA_CAPSCTL)
Register
Offset
R/W
Description
Reset Value
ANA_CAPSCTL
ANA_BA+0x8C
R/W
Capacitive Touch Sensing Control Register
0x0000_0000
31
CAPSEN
23
30
INTEN
22
29
RSTCNT
21
28
20
12
4
27
19
11
3
26
Reserved
18
25
17
9
24
16
8
Reserved
CLKDIV
15
7
14
6
13
10
2
5
1
0
Reserved
CLKMODE
CYCLECNT
LOWTIME
Table 7-35 Capacitive Touch Sensing Control Register (ANA_CAPSCTL, address 0x4008_008C).
Bits
[31]
Description
Enable
CAPSEN
0 = Disable/Reset block.
1 = Enable Block.
Interrupt Enable
[30]
[29]
INTEN
0 = Disable/Reset CAPS_IRQ interrupt.
1 = Enable CAPS_IRQ interrupt.
Reset Count
RSTCNT
0: Release/Activate ANA_CAPSCNT
1: Set high to reset ANA_CAPSCNT.
Reference Clock Divider
[15:8] CLKDIV
Circuit can be used to generate a reference clock output of SDCLK/2/(CLKDIV+1) instead of a
Capacitive Touch Sensing reset signal.
Reference Clock Mode
[5]
CLKMODE
0 = Capacitive Touch Sensing Mode.
1 = Circuit is in Reference clock generation mode.
Number of Relaxation Cycles
[4:2]
CYCLECNT
Peripheral performs 2^(CYCLECNT) relaxation cycles before generating interrupt.
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Output Low Time
Number of PCLK cycles to discharge external capacitor.
0=1cycle
LOWTIME
[1:0]
1=2cycles
2=8cycles
3=16cycles
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Capacitive Touch Sensing Count Register (ANA_CAPSCNT)
Register
Offset
R/W
Description
Reset Value
ANA_CAPSCNT
ANA_BA+0x90
R
Capacitive Touch Sensing Count Register
0x0000_0000
Table 7-36 Capacitive Touch Sensing Count Register (ANA_CAPSCNT, address 0x4008_0090).
Bits
Description
[23:0]
CAPSCNT
Counter Read Back Value Of Capacitive Touch Sensing Block
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7.4.11 Oscillator Frequency Measurement and Control
The ISD9160 provides a functional unit that can be used to measure PCLK frequency given a reference
frequency such as the 32.768kHz crystal or an I2S frame synchronization signal. This is simply a special
purpose timer/counter as shown in Figure 7-16.
X032K
OSC10K
FREQ_CNT[15:0]
M
U
X
FM_CYCLE[7:0]
OSC32K
EN
Counter
16 bits
CYCLE_CNT
8 bits
PCLK
XI32K
FM_SEL[1:0]
FM_DONE
I2S_WS
Figure 7-16 Oscillator Frequency Measurement Block Diagram
The block can be used to trim/measure the internal high frequency oscillator to the reference frequency of the
32.768kHz oscillator or an external reference frequency fed in on the I2S frame sync input. With this the
internal clock can be set at arbitrary frequencies, other than those trimmed at manufacturing, or can be
periodically trimmed to account for temperature variation. The block can also be used to measure the 16kHz
oscillator frequency relative to the internal master oscillator.
An example of use would be to measure the internal oscillator with reference to the 32768Hz crystal. To do
this:
CLK_APBCLK0.ANACKEN = 1;
/* Turn on analog peripheral clock */
ANA_FQMMCTL.CLKSEL = 1; // Select reference source as 32kHz XTAL input
ANA_FQMMCTL.CYCLESEL = DRVOSC_NUM_CYCLES-1;
ANA_FQMMCTL.FQMMEN = TRUE;
while( (ANA_FQMMCTL.MMSTS != 1) && (Timeout++ < 0x100000));
if(
Timeout >= 0x100000)
return(E_DRVOSC_MEAS_TIMEOUT);
Freq = ANA_FQMMCNT;
ANA_FQMMCTL.FQMMEN = FALSE;
Freq = Freq*32768 /DRVOSC_NUM_CYCLES;
To adjust the oscillator the user can write to the SYS_IRCTCTL register (see Table 5-11). In addition, to
obtain frequencies in between SYS_IRCTCTL trim settings a SUPERFINE function is available. The
SUPERFINE function dithers the trim setting between the current setting and FINE trim settings above and
below the current setting. An example of how the SUPERFINE trim register can adjust the measured
oscillator frequency is shown in the figure below
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49400000
49300000
49200000
49100000
49000000
48900000
48800000
48700000
48600000
Oscillator Frequency (Hz)
V
SUPERFINE trim value
-128
-96
-64
-32
0
32
64
96
128
SUPERFINE
Figure 7-17 Example SUPERFINE Trim Frequency Adjustment.
79872000
76800000
73728000
70656000
67584000
64512000
61440000
58368000
55296000
52224000
49152000
46080000
43008000
39936000
36864000
33792000
30720000
27648000
24576000
21504000
18432000
15360000
RANGE=0
RANGE=1
TARG32M
TARG48M
0
32
64
96
128
160
192
224
256
OSCTRIM
Figure 7-18 Typical Oscillator Frequency versus SYS_IRCTCTL Setting.
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Oscillator Trim Register (ANA_TRIM)
Register
Offset
R/W
Description
Reset Value
ANA_TRIM
ANA_BA+0x84
R/W
0x0000_XXXX
Oscillator Trim Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
SUPERFINE
COARSE
1
0
OSCTRIM
Table 7-37 Oscillator Trim Register (ANA_TRIM, address 0x4008_0084).
Bits
Description
Superfine
The superfine trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE
trim setting between the current setting and one setting above (values 1,127) or below (values -1, -128)
the current trim setting. Each step effectively moves the frequency 1/128th of the full FINE trim step
size.
[23:16
]
SUPERFINE
COARSE
[15:8]
[7:0]
COARSE
OSCTRIM
Current coarse range setting of the oscillator. Read Only
Oscillator Trim
Reads current oscillator trim setting. Read Only.
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Frequency Measurement Control Register (ANA_FQMMCTL)
Register
Offset
R/W
Description
Reset Value
ANA_FQMMCTL
ANA_BA+0x94
R/W
Frequency Measurement Control Register
0x0000_0001
31
FQMMEN
23
30
22
14
6
29
21
13
28
20
12
4
27
Reserved
19
26
18
10
25
17
9
24
16
8
CYCLESEL
15
7
11
3
Reserved
5
2
1
0
Reserved
MMSTS
CLKSEL
Table 7-38 Frequency Measurement Control Register (ANA_FQMMCTL, address 0x4008_0094).
Bits
[31]
Description
FQMMEN
FQMMEN
CYCLESEL
MMSTS
0 = Disable/Reset block.
1 = Start Frequency Measurement.
Frequency Measurement Cycles
Number of reference clock periods plus one to measure target clock (PCLK). For example if reference
clock is OSC32K (T is 30.5175us), set CYCLESEL to 7, then measurement period would be
30.5175*(7+1), 244.1us.
[23:16]
[2]
Measurement Done
0 = Measurement Ongoing.
1 = Measurement Complete.
Reference Clock Source
00b: OSC16K,
[1:0]
CLKSEL
01b: OSC32K (default),
1xb: I2S_WS – can be GPIOA[4,8,12] according to SYS_GPA_MFP register, configure I2S in SLAVE
mode to enable.
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Frequency Measurement Count (ANA_FQMMCNT)
Register
Offset
R/W
Description
Reset Value
ANA_FQMMCNT
ANA_BA+0x98
R
Frequency Measurement Count Register
0x0000_0000
Table 7-39 Frequency Measurement Count Register (ANA_FQMMCNT, address 0x4008_0098).
Bits
Description
Frequency Measurement Count
When MMSTS aaa 1 and G0 aaa 1, this is number of PCLK periods counted for frequency
measurement.
[15:0]
FQMMCNT
The frequency will be PCLK aaa FQMMCNT * Fref /(CYCLESEL+1) Hz
Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz
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7.5 Automatic Level Control (ALC)
7.5.1 Overview and Features
The ALC seeks to control the PGA gain such that the PGA output maintains a constant envelope. This
helps to prevent clipping at the input of the sigma delta ADC while maximizing the full dynamic range
of the ADC. The ALC monitors the output of the ADC biquad output when that filter is enabled in the
ADC path, or the output of the SINC filter otherwise. The ADC output is fed into a peak detector, which
updates the measured peak value whenever the absolute value of the input signal is higher than the
current measured peak. The measured peak gradually decays to zero unless a new peak is detected,
allowing for an accurate measurement of the signal envelope. Based on a comparison between the
measured peak value and the target value, the ALC block adjusts the gain control, which is fed back to
the PGA.
Decimator
SINC
Filter
Biquad
Filter
Input
Pin
Digital
Filter
PGA
ADC
ALC
Figure 7-19 ALC Block Diagram
The ALC is enabled by setting ALCEN. The ALC shares a clock source with the Biquad filter so
CLK_APBCLK0.BFALCKEN must be set to operate ALC. The ALC has two functional modes, which is
set by MODESEL.
Normal mode (MODESEL = LOW)
Peak Limiter mode (MODESEL = HIGH)
When the ALC is disabled, the input PGA returns to the PGA gain setting held in
ANA_PGAGAIN.GAINSET. In order to have a smooth transition when disabling the ALC, the user may
prefer to fetch the ALC trained gain setting from ANA_PGAGAIN.GAINREAD and write that value to
ANA_PGAGAIN.GAINSET prior to disabling the ALC. An input gain update must be made by writing
to GAINSET[5:0]. A digital peak detector monitors the input signal amplitude and compares it to a
register defined threshold level TARGETLV[3:0].
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ALC operation range
Target TARGETLV – 6dB
Input< noise
gate threshold
Gain (Attenuation) clipped
at MINGAIN -12dB
+33 dB
NGEN = 1
NGTH = -39dB
PGA Gain
MIC Boost Gain= 0dB
-
= -12dB
MAXGAIN = +35.25dB
0 dB
TARGETLV
MINGAIN
=
6dB
-12 dB
-39dB
-39dB
-6dB +6dB
Input Level
Figure 7-20: ALC Response Graph
The registers listed in the following sections allow configuration of ALC operation with respect to:
ALC target level
Gain increment and decrement rates
Minimum and maximum PGA gain values for ALC operating range
Hold time before gain increments in response to input signal
Inhibition of gain increment during noise inputs
Limiter mode operation
The operating range of the ALC is set by MAXGAIN and MINGAIN bits such that the PGA gain
generated by the ALC is constrained to be between the programmed minimum and maximum levels.
When the ALC is enabled, the PGA gain setting from PGASEL has no effect.
In Normal mode, the MAXGAIN bits set the maximum level for the PGA but in the Limiter mode
MAXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon
enabling of the ALC.
7.5.1.1 Normal Mode
Normal mode is selected when MODESEL is set LOW and the ALC is enabled by setting ALCEN
HIGH. This block adjusts the PGA gain setting up and down in response to the input level. A peak
detector circuit measures the envelope of the input signal and compares it to the target level set by
TARGETLV. The ALC increases the gain when the measured envelope is less than (target – 1.5dB)
and decreases the gain when the measured envelope is greater than the target. The following
waveform illustrates the behavior of the ALC.
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PGA Input
PGA Output
PGA Gain
Figure 7-21: ALC Normal Mode Operation
7.5.1.2 ALC Hold Time (Normal mode Only)
The hold parameter HOLDTIME configures the time between detection of the input signal envelope being below
the target range and the actual gain increase.
Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter
for optimal performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods
of silence such as those that may appear in music recordings; having a shorter hold time, on the other hand, may
be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with
different volumes. The waveform below shows the operation of the HOLDTIME parameter.
PGA Input
PGA Output
PGA Gain
Hold Delay
Change
Figure 7-22: ALC Hold Time
7.5.1.3 Peak Limiter Mode
Peak Limiter mode is selected when MODESEL is set to HIGH and the ALC is enabled by setting
ALCEN. In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at the
time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in
normal mode as indicated by the different lookup tables for these parameters for limiter mode. The
following waveform illustrates the behavior of the ALC in Limiter mode in response to changes in
various ALC parameters.
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PGA Input
PGA
Output
PGA Gain
Limiter
Enabled
Figure 7-23: ALC Limiter Mode Operations
When the input signal exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the
maximum attack rate (ATKSEL=0000) regardless of the mode and attack rate settings until the ADC
output level has been reduced below the threshold. This limits ADC clipping if there is a sudden
increase in the input signal level.
7.5.1.4 Attack Time
When the absolute value of the ADC output exceeds the level set by the ALC threshold, TARGETLV,
attack mode is initiated at a rate controlled by the attack rate register ATKSEL. The peak detector in
the ALC block loads the ADC output value when the absolute value of the ADC output exceeds the
current measured peak; otherwise, the peak decays towards zero, until a new peak has been
identified. This sequence is continuously running. If the peak is ever below the target threshold, then
there is no gain decrease at the next attack timer time; if it is ever above the target-1.5dB, then there
is no gain increase at the next decay timer time.
7.5.1.5 Decay Times
The decay time DECAYSEL is the time constant used when the gain is increasing. In limiter mode,
the time constants are faster than in ALC mode.
7.5.1.6 Noise gate (normal mode only)
A noise gate is used when there is no input signal or the noise level is below the noise gate threshold.
The noise gate is enabled by setting NGEN to HIGH. It does not remove noise from the signal. The
noise gate threshold NGTHBST is set to a desired level so when there is no signal or a very quiet
signal (pause), which is composed mostly of noise, the ALC holds the gain constant instead of
amplifying the signal towards the target threshold. The noise gate only operates in conjunction with
the ALC (ALCEN HIGH) and ONLY in Normal mode. The noise gate flag is asserted when
(Signal at ADC – PGA gain – MIC Boost gain) < NGTHBST (dB)
Levels at the extremes of the range may cause inappropriate operation, so care should be taken when
setting up the function.
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PGA Input
PGA Output
PGA Gain
Figure 7-24: ALC Operation with Noise Gate disabled
PGA Input
Noise Gate Threshold
PGA Output
PGA Gain
Figure 7-25: ALC Operation with Noise Gate Enabled
7.5.1.7 Zero Crossing
The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register
setting when the ALC is disabled. Zero crossing detection may be enabled to cause PGA gain
changes to occur only at an input zero crossing. Enabling zero crossing detection limits clicks and
pops that may occur if the gain changes while the input signal has a high volume.
There are two zero crossing detection enables:
Register ZCEN – is only relevant when the ALC is enabled.
Register ANA_SIGCTL.PUZCDCMP – is only relevant when the ALC is disabled.
If the zero crossing function is enabled (using either register), the zero cross timeout function may take
effect. If the zero crossing flag does not change polarity within 0.25 seconds of a PGA gain update
(either via ALC update or PGA gain register update), then the gain will update. This backup system
prevents the gain from locking up if the input signal has a small swing and a DC offset that prevents
the zero crossing flag from toggling.
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7.5.2 ALC Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
ALC Base Address:
ALC_BA = 0x400B_0048
ALC_CTL
ALC_BA+0x00
ALC_BA+0x04
ALC_BA+0x08
ALC_BA+0x0C
R/W
R
ALC Control Register
ALC status register
0x0E01_6320
0x0000_0000
0x0000_0000
0x0000_0000
ALC_STS
ALC_INTSTS
ALC_INTCTL
R/W
R/W
ALC interrupt register
ALC interrupt enable register
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7.5.3 ALC Control Register Description
ALC Control Register (ALC_CTL)
Register
Offset
R/W
Description
Reset Value
ALC_CTL
ALC_BA+0x00
R/W
ALC Control Register
0x0E01_6320
Table 7-40 ALC Control Register (ALC_CTL, address 0x400B_0048)
31
PKLIMEN
23
30
PKSEL
22
29
NGPKSEL
21
28
ALCEN
20
27
19
11
26
MAXGAIN
18
25
17
9
24
MINGAIN
16
MINGAIN
ZCEN
13
HOLDTIME
TARGETLV[3]
8
15
7
14
12
MODESEL
4
10
2
TARGETLV[2:0]
6
DECAYSEL
5
3
1
0
ATKSEL
NGEN
NGTHBST
Bits
[31]
Description
PKLIMEN
ALC peak limiter enable
0 = enable fast decrement when signal exceeds 87.5% of full scale (default)
1 = disable fast decrement when signal exceeds 87.5% of full scale
ALC gain peak detector select
[30]
[29]
[28]
PKSEL
0 = use absolute peak value for ALC training (default)
1 = use peak-to-peak value for ALC training
ALC noise gate peak detector select
NGPKSEL
ALCEN
0 = use peak-to-peak value for noise gate threshold determination (default)
1 = use absolute peak value for noise gate threshold determination
ALC select
0 = ALC disabled (default)
1 = ALC enabled
ALC Maximum Gain
0 = -6.75 dB
1 = -0.75 dB
2 = +5.25 dB
[27:25]
MAXGAIN
3 = +11.25 dB
4 = +17.25 dB
5 = +23.25 dB
6 = +29.25 dB
7 = +35.25 dB
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ALC Minimum Gain
0 = -12 dB
1 = -6 dB
2 = 0 dB
[24:22]
MINGAIN
3 = 6 dB
4 = 12 dB
5 = 18 dB
6 = 24 dB
7 = 30 dB
ALC Zero Crossing
[21]
ZCEN
0 = zero crossing disabled
1 = zero crossing enabled
ALC Hold Time
[20:17]
HOLDTIME
(Value: 0~10). Hold Time aaa (2^HOLDTIME) ms
ALC Target Level
0 = -28.5 dB
1 = -27 dB
2 = -25.5 dB
3 = -24 dB
4 = -22.5 dB
5 = -21 dB
6 = -19.5 dB
7 = -18 dB
[16:13]
TARGETLV
8 = -16.5 dB
9 = -15 dB
10 = -13.5 dB
11 = -12 dB
12 = -10.5 dB
13 = -9 dB
14 = -7.5 dB
15 = -6 dB
ALC Mode
[12]
MODESEL
0 = ALC normal operation mode
1 = ALC limiter mode
ALC Decay Time
(Value: 0~10)
[11:8]
DECAYSEL
When MODESEL aaa 0, Range: 125us to 128ms
When MODESEL aaa 1, Range: 31us to 32ms (time doubles with every step)
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ALC Attack Time
(Value: 0~10)
[7:4]
ATKSEL
When MODESEL aaa 0, Range: 500us to 512ms
When MODESEL aaa 1,Range: 125us to 128ms (Both ALC time doubles with every
step)
Noise Gate Enable
[3]
NGEN
0 = Noise gate disabled
1 = Noise gate enabled
Noise Gate Threshold
[2:0]
NGTHBST
Boost disabled: Threshold aaa (-81+6xNGTHBST) dB
Boost enabled: Threshold aaa (-87+6xNGTHBST) dB
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ALC Status Register (ALC_STS)
Register
Offset
R/W
Description
Reset Value
ALC_STS
ALC_BA+0x04
R
ALC status register
0x0000_0000
Table 7-41 ALC Status Register (ALC_STS, address 0x400B_004C)
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
PEAKVAL[8:5]
PEAKVAL[4:0]
5
P2PVAL[8:6]
1
0
P2PVAL[5:0]
NOISEF
CLIPFLAG
Bits
Description
Reserved
[31:19]
Reserved
Peak Value
[18:11]
[10:2]
[1]
PEAKVAL
P2PVAL
9 MSBs of measured absolute peak value
Peak-To-Peak Value
9 MSBs of measured peak-to-peak value
Noise Flag
NOISEF
Asserted when signal level is detected to be below NGTHBST
Clipping Flag
[0]
CLIPFLAG
Asserted when signal level is detected to be above 87.5% of full scale
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ALC Interrupt Register (ALC_INTSTS)
Register
Offset
R/W
Description
Reset Value
ALC_INTSTS
ALC_BA+0x08
R/W
ALC interrupt register
0x0000_0000
Table 7-42 ALC Interrupt Register (ALC_INTSTS, address 0x400B_0050)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
INTFLAG
Bits
[0]
Description
INTFLAG
ALC interrupt flag
This interrupt flag asserts whenever the interrupt is enabled and the PGA gain is
updated, either through an ALC change with the ALC enabled or through a PGA gain
write with the ALC disabled.
Write a 1 to this register to clear.
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ALC Interrupt Enable Register
Register
Offset
R/W
Description
Reset Value
ALC_INTCTL
ALC_BA+0x0C
R/W
ALC interrupt enable register
0x0000_0000
Table 7-43 ALC Interrupt Enable Register (ALC_INTCTL, address 0x400B_0054)
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
INTEN
Bits
Description
INTEN
ALC Interrupt Enable
0 = ALC INT disabled
1 = ALC INT enabled
[0]
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7.6 Biquad Filter (BIQ)
7.6.1 Overview and Features
A coefficient programmable 3-stage Biquad filter (6th-Order IIR filter) is available which can be used on
either ADC path or DPWM path to further reduce unwanted noise or filter the signal. Each biquad filter
has the transfer function as H(z) and is implemented in Direct Form II Transpose structure as.
Upon power on reset or when the BIQ_CTL.DLCOEFF=0 is released, a set of default coefficients bn0,
bn1, bn2, an1, an2 (n = 1,2,3 which is the stage number of the filter) will be written to the coefficient RAM
automatically. And these coefficients can be over-written by the processor for different filter
specifications.
Note that the fixed point coefficients have the format of 3.16 (19 bits) and are stored in the coefficient
RAM under normal operation. It takes 32 internal system clocks for the automatic write to finish when
the BIQ_CTL.DLCOEFF bit is released; it is important that the processor has enough delay before
start the coefficient programming or enabling biquad (BIQ_CTL.BIQEN). Attempting to program the
coefficients before the auto programming is done will result in unsuccessful programming. The default
coefficient setting is a low pass filter with 3db cut-off frequency at 7/16 Fs (Sample Rate).
Biquad is released from reset by setting BIQ_CTL.DLCOEFF=1. After 32 clock cycles, processor can
setup other Biquad parameters or re-program coefficients before enabling filter.
The BIQ_CTL.PATHSEL register bit determines which path the BIQ is going to use. The default value
is 0 which is the microphone ADC path, by setting this bit 1, the BIQ will be used in DPWM path.
The operating Sample Rate of the filter can be setup by the following registers: The default value of
BIQ_CTL.SRDIV (sample rate divider) is 3071, when the chip is running at HCLK=49.152Mhz, the
operating SR of BIQ can be calculated by equation HCLK/(SRDIV+1) = 16Khz. The processor can
change the operating sample rate (SR) by changing the SRDIV register.
If the BIQ is intended to be used in DPWM path, the BIQ can up sample the data rate by programming
BIQ_CTL.DPWMPUSR register which has default value at 3. The final BIQ sampling rate for DPWM
path is based on both SRDIV and BIQ_CTL.DPWMPUSR registers which is equal to SR*
(BIQ_CTL.DPWMPUSR+1) . So the default DPWM operating sample rate is 16*(3+1) = 64Khz.
The BIQ filter is in reset state in default. To use the BIQ function, the following sequence is
recommended:
1. Set BIQ_CTL.DLCOEFF bit. By releasing the reset, the filter controller will download default
coefficients automatically to the RAM.
2. Turn on the BIQ_CTL.PRGCOEFF bit if intending to change the coefficients. Otherwise skip to
next step.
3. Setup the BIQ operation sample rate by program DPWMPUSR or SRDIV register bits if
necessary.
4. Decide the ADC or DPWM path to be used for the BIQ by programming PATHSEL, and turn
off PRGCOEFF bit (if it was turned on in step #2).
5. Turn on BIQ_CTL.BIQEN. BIQ will start filter function.
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7.6.2 BIQ Control Register Map
7.6.2.1 BIQ filter coefficients registers
Register
Offset
R/W
Description
Reset Value
BIQ Base Address:
BIQ_BA = 0x400B_0000
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0000_d010
BIQ_COEFF0
BIQ_COEFF1
BIQ_COEFF2
BIQ_COEFF3
BIQ_COEFF4
BIQ_COEFF5
BIQ_COEFF6
BIQ_COEFF7
BIQ_COEFF8
BIQ_COEFF9
BIQ_COEFF10
BIQ_COEFF11
BIQ_COEFF12
BIQ_COEFF13
BIQ_BA + 0x00
BIQ_BA+0x004
BIQ_BA+0x008
BIQ_BA+0x00c
BIQ_BA+0x010
BIQ_BA + 0x14
BIQ_BA+0x018
BIQ_BA+0x01c
BIQ_BA+0x020
BIQ_BA+0x024
BIQ_BA + 0x28
BIQ_BA+0x02c
BIQ_BA+0x030
BIQ_BA+0x034
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0001_c020
0x0001_c020
0x0001_ad66
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
Coefficient a1 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
Coefficient a2 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0000_d1dc
0x0000_c1d0
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
0x0001_83a0
0x0000_c1d0
0x0001_7445
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
Coefficient a1 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
Coefficient a2 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
0x0000_92f6
0x0000_b3cc
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
0x0001_6798
0x0000_b3cc
0x0001_595d
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
Coefficient a1 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
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Coefficient a2 In H(z) Transfer Function
0x0000_75d2
BIQ_COEFF14
BIQ_CTL
BIQ_BA+0x038
BIQ_BA+0x040
R/W
R/W
(3.16 format) - 3rd stage BIQ Coefficients
BIQ Control Register
0x0BFF_0030
7.6.3 Register Description
BIQ Control Register (BIQ_CTL)
Register
BIQ_CTL
Offset
R/W
Description
Reset Value
BIQ_BA+0x040
R/W
BIQ Control Register
0x0BFF_0030
Table 7-44 BIQ Control Register (BIQ_CTL, address 0x400B_0040)
31
23
15
7
30
Reserved
22
29
21
13
28
20
12
4
27
19
11
3
26
SRDIV[12:8]
18
25
17
9
24
16
8
SRDIV[7:0]
Reserved
14
6
10
5
2
1
0
Reserved
DPWMPUSR
DLCOEFF
PRGCOEFF
PATHSEL
BIQEN
Bits
Description
SRDIV
Sample Rate Divider
This register is used to program the operating sampling rate of the biquad filter. The
sample rate is defined as
[28:16]
HCLK/(SRDIV+1).
Default to 3071 so the sampling rate is 16K when HCLK is 49.152MHz.
DPWM Path Up Sample Rate (From SRDIV Result)
This register is only used when PATHSEL is set to 1. The operating sample rate for
the biquad filter will be
[6:4]
DPWMPUSR
(DPWMPUSR+1)*HCLK/(SRDIV+1).
Default value for this register is 3.
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Move BIQ Out Of Reset State
0 = BIQ filter is in reset state.
[3]
[2]
DLCOEFF
1 = When this bit is on, the default coefficients will be downloaded to the coefficient
ram automatically in 32 internal system clocks. Processor must delay enough time
before changing the coefficients or turn the BIQ on.
Programming Mode Coefficient Control Bit
0 = Coefficient RAM is in normal mode.
PRGCOEFF
1 = coefficient RAM is under programming mode.
This bit must be turned off when BIQEN in on.
AC Path Selection For BIQ
0 = used in ADC path
[1]
[0]
PATHSEL
BIQEN
1 = used in DPWM path
BIQ Filter Start To Run
0 = BIQ filter is not processing
1 = BIQ filter is on.
BIQ Coefficient (BIQ_COEFFn)
Register
Offset
R/W
Description
Reset Value
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0000_d010
BIQ_COEFF0
BIQ_BA + 0x00
R/W
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
BIQ_COEFF1
BIQ_COEFF2
BIQ_COEFF3
BIQ_COEFF4
BIQ_COEFF5
BIQ_COEFF6
BIQ_BA+0x004
BIQ_BA+0x008
BIQ_BA+0x00c
BIQ_BA+0x010
BIQ_BA + 0x14
BIQ_BA+0x018
R/W
R/W
R/W
R/W
R/W
R/W
0x0001_c020
0x0001_c020
0x0001_ad66
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
Coefficient a1 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
Coefficient a2 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
0x0000_d1dc
0x0000_c1d0
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
0x0001_83a0
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 2nd stage BIQ Coefficients
BIQ_COEFF7
BIQ_COEFF8
BIQ_BA+0x01c
BIQ_BA+0x020
R/W
R/W
0x0000_c1d0
0x0001_7445
Coefficient a1 In H(z) Transfer Function
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(3.16 format) - 2nd stage BIQ Coefficients
Coefficient a2 In H(z) Transfer Function
0x0000_92f6
BIQ_COEFF9
BIQ_COEFF10
BIQ_COEFF11
BIQ_COEFF12
BIQ_COEFF13
BIQ_COEFF14
BIQ_BA+0x024
BIQ_BA + 0x28
BIQ_BA+0x02c
BIQ_BA+0x030
BIQ_BA+0x034
BIQ_BA+0x038
R/W
R/W
R/W
R/W
R/W
R/W
(3.16 format) - 2nd stage BIQ Coefficients
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
0x0000_b3cc
Coefficient b1 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
0x0001_6798
0x0000_b3cc
0x0001_595d
0x0000_75d2
Coefficient b2 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
Coefficient a1 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
Coefficient a2 In H(z) Transfer Function
(3.16 format) - 3rd stage BIQ Coefficients
Bits
Description
COEFFDAT
[31:0]
Coefficient Data
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8
APPLICATION DIAGRAM
VCCD
35
10
25
VCCLDO
VCCD
VSSD
0.1uF
47
uF
0.1
uF
30
31
32
33
34
PA.3/SPI_MISO0
PA.2/SPI_SSB0
VDD33
PA.1/SPI_SCLK
PA.0/SPI_MOSI0
VCCD
1uF
17
21
CSB
DO
VCC
VCCSPK
VCCSPK
HOLDB
47
uF
0.1
uF
WPB
GND
CLK
DIO
19
18
VSSSPK
SPK+
W25Q
20
SPK-
ISD9160
LQFP48
40
39
XI32K
32.768K
XO32K
20pF
20pF
4.7uF
0.1uF
2.2 K
11
45
43
MICBIAS
MIC+
VREG
1uF
MIC
44
MIC-
0.1uF
2.2 K
VCCA
46
41
VCCA
VSSA
42
47
uF
0.1
uF
VMID
4.7uF
: Digital ground;
: Analog ground;
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9
ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
Input Voltage
PARAMETER
MIN
-0.3
MAX
+6.0
UNIT
V
VDDVSS
VIN
VSS-0.3
VDD+0.3
V
Oscillator Frequency
1/tCLCL
TA
0
40
MHz
Operating Temperature
-40
+85
C
Storage Temperature
TST
-55
-
+150
120
120
35
C
Maximum Current into VDD
Maximum Current out of VSS
mA
mA
mA
Maximum Current sunk by a
I/O pin
Maximum Current sourced by
a I/O pin
35
mA
mA
mA
Maximum Current sunk by
total I/O pins
100
100
Maximum Current sourced by
total I/O pins
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
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9.2 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 49.152 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
UNI
T
MIN.
2.4
-0.3
0
TYP.
MAX.
Operation voltage
VDD
5.5
V
V
V
V
VDD =2.4V ~ 5.5V up to 50 MHz
VSS
AVSS
Power Ground
Analog Operating Voltage
Analog Reference Voltage
AVDD
Vref
VDD
0
AVDD
VDD= 5.5V,
Enable all IP.
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
24.8
19.7
23.6
18.3
18.8
15.0
17.6
13.8
mA
mA
mA
mA
mA
mA
mA
mA
VDD=5.5V,
disable all IP
Operating Current
Normal Run Mode
@ 49.152 MHz
VDD = 3V,
enable all IP
VDD = 3V,
disable all IP
VDD = 5.5V
enable all IP
VDD = 5.5V,
disable all IP
Operating Current
Normal Run Mode
@ 32.768MHz
VDD = 3V
enable all IP
VDD = 3V,
disable all
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VDD = 5.5V,
Enable all IP.
IDD13
IDD14
IDD15
IDD16
IDD9
12.5
10.3
11.4
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
VDD = 5.5V,
Disable all IP.
Operating Current
Normal Run Mode
@ 12.288Mhz
VDD = 3V,
Enable all IP.
VDD = 3V,
Disable all IP.
VDD = 5.5V,
Enable all IP.
9.7
8.1
8.7
7.0
10
9
VDD = 5.5V,
Disable all IP.
IDD10
IDD11
IDD12
IIDLE1
IIDLE1
IIDLE1
IIDLE1
IIDLE1
IIDLE1
IIDLE1
IIDLE1
Operating Current
Normal Run Mode
@ 4.9152Mhz
VDD = 3V,
Enable all IP.
VDD = 3V,
Disable all IP.
VDD= 5.5V
Operating Current
Sleep Mode
VDD= 3.3V
VDD=5.5V
10
8
Operating Current
Deep Sleep Mode
VDD= 3.3V
VDD=3.3V 32K running with RTC
VDD= 3.3V 16K running
VDD=3.3V Wakeup with16K
VDD= 3.3V wakeup with wakeup pin
3
Standby Power down
mode(SPD)
1
uA
500
nA
Operating Current
Deep Power down mode(DPD)
nA
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Input Current PA, PB
(Quasi-bidirectional mode)
IIN1
-60
-
+15
VDD = 5.5V, VIN = 0V or VIN=VDD
A
Input Current at /RESET [1]
IIN2
ILK
-55
-2
-45
-
-30
+2
VDD = 3.3V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
A
A
Input Leakage Current PA, PB
Logic 1 to 0 Transition Current
PA~PB (Quasi-bidirectional
mode)
[3]
ITL
-650
-
-200
VDD = 5.5V, VIN<2.0V
A
-0.3
-0.3
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
Input Low Voltage PA, PB (TTL
input)
VIL1
VIH1
VIL3
VIH3
V
VDD
+0.2
2.0
1.5
-
-
VDD = 5.5V
VDD =3.0V
Input High Voltage PA, PB (TTL
input)
V
VDD
+0.2
Input Low Voltage XT1[*2]
0
0
-
-
0.8
0.4
VDD = 4.5V
VDD = 3.0V
V
V
VDD
+0.2
3.5
2.4
-
VDD = 5.5V
VDD = 3.0V
Input High Voltage XT1[*2]
Input Low Voltage X32I[*2]
VDD
+0.2
-
-
VIL4
VIH4
0
0.4
2.5
V
V
Input High Voltage X32I[*2]
Negative going threshold
(Schmitt input), /REST
Positive going threshold
(Schmitt input), /REST
1.7
VILS
-0.5
-
0.3VDD
V
VDD+0.
5
VIHS
0.7VDD
-
V
V
Hysteresis voltage of
PA~PB(Schmitt input)
0.2VDD
VHY
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ISR11
-300
-370
-450
VDD = 4.5V, VS = 2.4V
A
Source Current PA, PB
ISR12
ISR12
ISR21
-50
-40
-20
-70
-60
-24
-90
-80
-28
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
VDD = 4.5V, VS = 2.4V
A
A
Quasi-bidirectional Mode)
mA
Source Current PA, PB (Push-
pull Mode)
ISR22
ISR22
-4
-3
-6
-5
-8
-7
mA
mA
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
ISK1
ISK1
ISK1
10
7
16
10
9
20
13
12
mA
mA
mA
VDD = 4.5V, VS = 0.45V
VDD = 2.7V, VS = 0.45V
VDD = 2.5V, VS = 0.45V
Sink Current PA, PB
(Quasi-bidirectional and Push-
pull Mode)
6
Brownout voltage with
BOV_VL [2:0] =000b
VBO2.1
VBO2.2
VBO2.4
VBO2.5
VBO2.7
VBO2.8
VBO3.0
VBO4.5
2.15
2.25
2.45
2.55
2.7
V
V
V
V
V
V
V
V
Brownout voltage with
BOV_VL [2:0] =001b
Brownout voltage with
BOV_VL [2:0] =010b
Brownout voltage with
BOV_VL [2:0] =011b
Brownout voltage with
BOV_VL [2:0] =100b
Brownout voltage with
BOV_VL [2:0] =101b
2.8
Brownout voltage with
BOV_VL [2:0] =110b
3.0
Brownout voltage with
BOV_VL [2:0] =111b
4.55
Notes:
1. /REST pin is a Schmitt trigger input. For power on, needs to keep low before all power stable. For MCU IO control,
programmer needs to consider the reset circuit and IO sink capability. These will impact the low timing of Reset pin
2. Crystal Input is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD=5.5V, 5he transition current reaches its maximum value when Vin approximates to 2V.
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9.3 AC Electrical Characteristics
9.3.1 External 32kHz XTAL Oscillator
PARAMETER
Input clock frequency
Temperature
CONDITION
MIN.
-
TYP.
MAX.
-
UNIT
kHz
℃
External crystal
32.768
-
-
-40
2.4
-
-
85
VDD
5.5
V
9.3.2 Internal 49.152MHz Oscillator
PARAMETER
Supply voltage[1]
CONDITION
MIN.
TYP.
MAX.
UNIT
-
2.4
-
-
5.5
V
MHz
%
Center Frequency
-
49.152
Calibrated Internal Oscillator
Frequency
-1
-4
-
-
1
4
+25C; VDD =5V
%
-40C~+85C;
VDD=2.5V~5.5V
9.3.3 Internal 16 kHz Oscillator
PARAMETER
Supply voltage
CONDITION
MIN.
TYP.
MAX.
UNIT
-
2.4
-
-
16
-
5.5
-
V
kHz
%
Center Frequency
-
Calibrated Internal Oscillator
Frequency
-10
-20
10
20
+25C; VDD =5V
-
%
-40C~+85C;
VDD=2.5V~5.5V
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9.4 Analog Characteristics
9.4.1 Specification of ADC and Speaker Driver
Conditions: VCCD = 3.3V, VCCA = 3.3V, TA = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless
otherwise stated.
Comments/Condition
s
Parameter
Symbol
Min
Typ
Max
Units
Analog to Digital Converter (ADC)
Full scale input signal 1
VINFS
PGABST = 0dB
1.0
Vrms
dBV
dB
PGAGAIN = 0dB
0
Signal-to-noise ratio
Total harmonic distortion 2
SNR
Gain = 0dB, A-weighted
Input = -3dB FS input
92
-80
THD+N
dB
PWM Speaker Output (8Ω bridge-tied-load)
Full scale output 4
Total harmonic distortion 2
SPKBST = 1
VCCSPK / 3.3
*63
Vrms
dB
THD+N
Po
VDDSPK=3.3V
Po
VDDSPK = 3.3V
Po
VDDSPK = 5V
Po
=
200mW,
320mW,
860mW,
1000mW,
=
-64
-60
-36
91
dB
dB
dB
dB
=
=
VDDSPK = 5V
Signal-to-noise ratio
SNR
VDDSPK = 3.3V
VDDSPK=5V
90
dB
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9.4.2 Specification of PGA and BOOST
Conditions: VCCD = 3.3V, VCCA = 3.3V, TA = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless
otherwise stated.
Comments/Condition
s
Parameter
Symbol
Min
Typ
Max
Units
Microphone Inputs (MICP, MICN) and Programmable Gain Amplifier (PGA)
Full scale input signal 1
PGABST = 0dB
PGAGAIN = 0dB
1.0
Vrms
dBV
dB
0
Programmable gain
Programmable gain step size
Mute Attenuation
-12
35.25
Guaranteed Monotonic
0.75
120
dB
dB
Input resistance
Inverting Input
PGA Gain = 35.25dB
PGA Gain = 0dB
PGA Gain = -12dB
Non-inverting Input
1.6
47
kΩ
kΩ
kΩ
kΩ
pF
µV
75
94
Input capacitance
10
PGA equivalent input noise
0 to 20kHz, Gain set to
35.25dB
120
Input Boost
Gain boost
Boost disabled
Boost enabled
0
dB
dB
26
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ISD9160 Technical Reference Manual
9.4.3 Specification of ALC an MICBIAS
Conditions: VCCD = 3.3V, VCCA = 3.3V, TA = +25°C, 1kHz signal, fs = 16kHz, 16-bit audio data, unless
otherwise stated.
Parameter
Symbol Comments/Conditions
Min
Typ
Max
Units
Automatic Level Control (ALC) & Limiter:
Target record level
-22.5
-12
-1.5
35.25
dBFS
dB
Programmable gain
Gain hold time 3
tHOLD
tDCY
Doubles every gain step,
with 16 steps total
0 / 2.67 / 5.33 / … / 43691
ms
Gain ramp-up (decay) 3
ALC Mode
ALC = 0
4 / 8 / 16 / … / 4096
ms
ms
ms
ms
dB
Limiter Mode
ALC = 1
1 / 2 / 4 / … / 1024
1 / 2 / 4 / … / 1024
0.25 / 0.5 / 1 / … / 128
120
Gain ramp-down (attack) 3
tATK
ALC Mode
ALC = 0
Limiter Mode
ALC = 1
Mute Attenuation
Microphone Bias
Bias voltage
VMICBIAS
0.90, 0.65 ,0.75, 0.50,
VDDA
V
2.4, 1.7,2.0
Bias current source
Output noise voltage
IMICBIAS
Vn
3
mA
1kHz to 20kHz
14
nV/√Hz
Notes
1. Full Scale is relative to the magnitude of VCCA and can be calculated as FS = VDDA/3.3.
2. Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The
signal level for distortion measurements is at 3dB below full scale, unless otherwise noted.
3. Time values scale proportionally with HCLK. Complete descriptions and definitions for these values are
contained in the detailed descriptions of the ALC functionality.
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ISD9160 Technical Reference Manual
9.4.4 Specification of LDO & Power management
PARAMETER
MIN
TYP
MAX
UNIT
NOTE
Input Voltage
2.4
5
5.5
V
V
VDD input voltage
VDD > 1.8V
Output Voltage
-10%
1.8
+10%
Note:
1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected
between VCCD and the VSSD pin of the device.
2. For ensuring power stability, a 1.0uF or higher capacitor must be connected between LDO pin
and the VSSD pin of the device. Also a 100nF bypass capacitor between LDO and VSSD will
help suppress output noise.
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9.4.5 Specification of Brownout Detector
PARAMETER
Operation voltage
Quiescent current
Temperature
CONDITION
MIN.
2.2
-
TYP.
MAX.
5.5
UNIT
V
-
-
-
AVDD=5.5V
-
125
85
μA
℃
-40
25
BOV_VL[1:0]=11
BOV_VL [1:0]=10
BOV_VL [1:0]=01
BOV_VL [1:0]=00
BOV_VL [2:0]=011
BOV_VL[2:0]=010
BOV_VL [2:0]=001
BOV_VL [2:0]=000
-
2.15
2.25
2.45
2.55
2.7
V
V
V
V
V
V
V
V
V
Brown-out voltage
2.8
3.0
4.55
Hysteresis
9.4.6 Specification of Power-On Reset (VCCD)
PARAMETER
Temperature
CONDITION
-
MIN.
-40
-
TYP.
25
MAX.
UNIT
℃
85
-
Reset voltage
VCC ramping down
VCC ramping up
Vin>reset voltage
1.0
1.5
60
V
Reset Release voltage
Quiescent current
V
-
-
nA
Release Date: Mar 30, 2016
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ISD9160 Technical Reference Manual
9.4.7 Specification of Temperature Sensor
PARAMETER
Supply voltage[1]
Temperature
Current consumption
Gain
MIN
2.4
TYP
MAX
5.5
UNIT
V
CONDITIONS
-
-
-40
125
℃
uA
mV/℃
mV
Offset
Temp=0 ℃
Notes:
1. Internal operation voltage comes from LDO.
9.4.8 Specification of Comparator
PARAMETER
Temperature
VCCA
MIN.
TYP.
MAX.
85℃
5.5
CONDITION
-40℃
25 ℃
3
-
2.4
-
VCCA current
Input offset voltage
-
-
20uA
5mV
40uA
15mV
20uA@VDD=3V
-
Input common mode
range
0.1
-
VDD-1.2
-
DC gain
-
-
70dB
-
-
-
Propagation delay
200ns
@VCM=1.2V & VDIFF=0.1V
20mV@VCM=1V
50mV@VCM=0.1V
Comparison voltage
10mV
20mV
-
50mV@VCM=VDD-1.2
@10mV for non-hysteresis
One bit control
Hysteresis
-
-
±10mV
-
-
W/O & W. hysteresis
@VCM=0.4V ~ VDD-1.2V
@CINP=1.3V
CINN=1.2V
Wake up time
2us
9.5 Reset Characteristics
(VDD-VSS=5V, TA = 25C, FOSC = 49.152 MHz unless otherwise specified.)
Parameter
Parameter Parameter Name
No.
Min Typ
1.7
Max
Unit
R1
VTH
Reset threshold
1
2
V
Release Date: Mar 30, 2016
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Supply voltage (VDD) rise time (0V-5V),
power on reset
R2
TVDDRISE
-
-
100
ms
R3
R4
R5
TPOR
TIRPOR
TMIN
Power-On Reset timeout
Internal reset timeout after POR
Minimum RESETN pulse width
-
-
-
-
12
45
-
µs
µs
ns
100
-
Internal reset timeout after hardware reset
(RESETN pin)
R6
TIRHWR
-
-
20
µs
Internal reset timeout after software-initiated
system reset
R7
R8
TIRSWR
TIRWDR
-
-
-
2
µs
µs
Internal reset timeout after watchdog reset
3 *1
-
*Notes:
1. It will be 6500us when use OSC_10K as the WDG clock.
9.5.1.1 Power-On Reset Timing
R1
VCCD
R3
R2
POR
(Internal)
R4
Reset
(Internal)
9.5.1.2 External Reset Timing (RESETN)
RESETN
R5
R6
Reset
(Internal)
9.5.1.3 Software Reset Timing
SW Reset
R7
Reset
(Internal)
Release Date: Mar 30, 2016
Revision V1.41
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ISD9160 Technical Reference Manual
9.5.1.4 Watchdog Reset Timing
WDOG Reset
(Internal)
R8
Reset
(Internal)
Release Date: Mar 30, 2016
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ISD9160 Technical Reference Manual
10 PACKAGE DIMENSIONS
10.1.1 48L LQFP (7x7x1.4mm footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Max
Min
Max Min
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.45
0.25
0.20
7.10
7.10
0.65
9.10
1.40
0.20
A
0.006
0.004
0.272
0.272
0.014
0.350
0.350
0.018
0.15
0.008 0.010
b
c
D
0.006
0.276
0.276
0.020
0.10 0.15
0.008
0.280
0.280
0.026
0.358
7.00
7.00
6.90
6.90
0.35
8.90
E
0.50
9.00
e
H
D
0.354
0.358
0.030
8.90
0.45
9.00
0.60
1.00
9.10
0.75
0.354
0.024
E
H
L
L
Y
0.039
1
0.004
7
0.10
7
0
0
0
Release Date: Mar 30, 2016
Revision V1.41
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ISD9160 Technical Reference Manual
10.1.2 33-pin QFN
5x5 mm2, Thickness 0.8mm (MAX), Pitch 0.5 mm (SAW Type), EP SIZE 3.5X3.5 mm
Release Date: Mar 30, 2016
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ISD9160 Technical Reference Manual
11 ORDERING INFORMATION
I 9 1 x x x x I
ISD Audio Product Family
Product Series
91: Cortex-M0
Flash ROM
Temperature
I: -40°C ~ +85°C
Package
F: LQFP-48
Y: QFN-33
3: 68KB
4: 100KB
6: 145KB
SRAM
SW Feature
Blank: Standard
C: Voice Recognition
0: 12KB
Release Date: Mar 30, 2016
Revision V1.41
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ISD9160 Technical Reference Manual
12 REVISION HISTORY
PAGE/
CHAP.
VERSION
DATE
DESCRIPTION
V1.01
V1.41
Sep 01, 2014
Mar 30, 2016
-
-
First Release.
Add QFN33 pin package. Add ordering info.
Release Date: Mar 30, 2016
Revision V1.41
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ISD9160 Technical Reference Manual
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of
Nuvoton products could result or lead to a situation where personal injury, death or severe
property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
Please note that all data and specifications are subject to change without notice. All the
trademarks of products and companies mentioned in this datasheet belong to their respective
owners.
Release Date: Mar 30, 2016
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Revision V1.41
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