M030GTC1AE [NUVOTON]
NuMicro® Family Arm® 32-bit Cortex®-M0 Microcontroller;
| 型号： | M030GTC1AE |
| 厂家： | 
NUVOTON |
| 描述： | NuMicro® Family Arm® 32-bit Cortex®-M0 Microcontroller 微控制器 |
| 文件： | 总118页 (文件大小：2744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M030G/M031G Series
NuMicro® Family
Arm® 32-bit Cortex® -M0 Microcontroller
M030G/M031G Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller and
microprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 31, 2021
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TABLE OF CONTENTS
1 GENERAL DESCRIPTION.............................................................................. 9
2 FEATURES.....................................................................................................10
2.1 M030G/M031G Features............................................................................................10
3 PARTS INFORMATION .................................................................................15
3.1 Package Type...............................................................................................................15
3.2 M030G/M031G Series Naming Rule ........................................................................16
3.3 M030G/M031G Series Selection Guide...................................................................17
4 PIN CONFIGURATION...................................................................................18
4.1 Pin Configuration..........................................................................................................18
4.1.1 M030G/M031G Series Pin Diagram............................................................................ 18
4.1.2 M030G Series Multi-function Pin Diagram................................................................. 20
4.1.3 M031G Series Multi-function Pin Diagram................................................................. 24
4.2 Pin Mapping..................................................................................................................28
4.3 Pin Functional Description..........................................................................................30
5 BLOCK DIAGRAM.........................................................................................34
6 FUNCTIONAL DESCRIPTION .......................................................................35
6.1 Arm® Cortex®-M0 Core................................................................................................35
6.2 System Manager..........................................................................................................37
6.2.1 Overview ......................................................................................................................... 37
6.2.2 System Reset ................................................................................................................. 37
6.2.3 System Power Distribution ........................................................................................... 43
6.2.4 Power Modes and Wake-up Sources.......................................................................... 45
6.2.5 System Memory Map..................................................................................................... 47
6.2.6 SRAM Memory Organization........................................................................................ 49
6.2.7 Chip Bus Matrix.............................................................................................................. 49
6.2.8 Temperature Sensor...................................................................................................... 50
6.2.9 Internal Voltage Reference (INT_VREF) .................................................................... 51
6.2.10MANCH_TXD Modulation with BPWM1..................................................................... 51
6.2.11Register Lock Control.................................................................................................... 52
6.2.12System Timer (SysTick) ................................................................................................ 53
6.2.13Nested Vectored Interrupt Controller (NVIC) ............................................................. 54
6.3 Clock Controller............................................................................................................58
6.3.1 Overview ......................................................................................................................... 58
6.3.2 Clock Generator............................................................................................................. 59
6.3.3 System Clock and SysTick Clock ................................................................................ 60
6.3.4 Peripherals Clock........................................................................................................... 61
6.3.5 Power-down Mode Clock.............................................................................................. 61
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6.3.6 Clock Output................................................................................................................... 61
6.4 Flash Memory Controller (FMC)................................................................................63
6.4.1 Overview ......................................................................................................................... 63
6.4.2 Features .......................................................................................................................... 63
6.5 General Purpose I/O (GPIO)......................................................................................64
6.5.1 Overview ......................................................................................................................... 64
6.5.2 Features .......................................................................................................................... 64
6.6 PDMA Controller (PDMA)...........................................................................................65
6.6.1 Overview ......................................................................................................................... 65
6.6.2 Features .......................................................................................................................... 65
6.7 Timer Controller (TMR) ...............................................................................................66
6.7.1 Overview ......................................................................................................................... 66
6.7.2 Features .......................................................................................................................... 66
6.8 Watchdog Timer (WDT) ..............................................................................................67
6.8.1 Overview ......................................................................................................................... 67
6.8.2 Features .......................................................................................................................... 67
6.9 Window Watchdog Timer (WWDT) ...........................................................................68
6.9.1 Overview ......................................................................................................................... 68
6.9.2 Features .......................................................................................................................... 68
6.10 Basic PWM Generator and Capture Timer (BPWM) ........................................69
6.10.1Overview ......................................................................................................................... 69
6.10.2Features .......................................................................................................................... 69
6.11 UART Interface Controller (UART)......................................................................70
6.11.1Overview ......................................................................................................................... 70
6.11.2Features .......................................................................................................................... 70
6.12 Serial Peripheral Interface (SPI)..........................................................................72
6.12.1Overview ......................................................................................................................... 72
6.12.2Features .......................................................................................................................... 72
6.13 I2C Serial Interface Controller (I2C) .....................................................................73
6.13.1Overview ......................................................................................................................... 73
6.13.2Features .......................................................................................................................... 73
6.14 CRC Controller (CRC)...........................................................................................74
6.14.1Overview ......................................................................................................................... 74
6.14.2Features .......................................................................................................................... 74
6.15 CRC Controller (CRC) - Configurable.................................................................75
6.15.1Overview ......................................................................................................................... 75
6.15.2Features .......................................................................................................................... 75
6.16 Manchester Controller (MANCH).........................................................................76
6.16.1Overview ......................................................................................................................... 76
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6.16.2Features .......................................................................................................................... 76
6.17 Analog-to-Digital Converter (ADC)......................................................................77
6.17.1Overview ......................................................................................................................... 77
6.17.2Features .......................................................................................................................... 77
6.18 Digital to Analog Converter (DAC).......................................................................79
6.18.1Overview ......................................................................................................................... 79
6.18.2Features .......................................................................................................................... 79
6.19 Peripherals Interconnection..................................................................................80
6.19.1Overview ......................................................................................................................... 80
6.19.2Peripherals Interconnect Matrix table ......................................................................... 80
7 APPLICATION CIRCUIT ................................................................................81
7.1 Power Supply Scheme................................................................................................81
7.2 Peripheral Application Scheme..................................................................................82
8 ELECTRICAL CHARACTERISTICS..............................................................83
8.1 Absolute Maximum Ratings........................................................................................83
8.1.1 Voltage Characteristics ................................................................................................. 83
8.1.2 Current Characteristics ................................................................................................. 83
8.1.3 Thermal Characteristics................................................................................................ 84
8.1.4 EMC Characteristics...................................................................................................... 85
8.1.5 Package Moisture Sensitivity(MSL) ............................................................................ 85
8.1.6 Soldering Profile............................................................................................................. 87
8.2 General Operating Conditions ...................................................................................88
8.3 DC Electrical Characteristics......................................................................................89
8.3.1 Supply Current Characteristics .................................................................................... 89
8.3.2 On-Chip Peripheral Current Consumption ................................................................. 92
8.3.3 Wakeup Time from Low-Power Modes....................................................................... 93
8.3.4 I/O Current Injection Characteristics ........................................................................... 94
8.3.5 I/O DC Characteristics................................................................................................... 94
8.4 AC Electrical Characteristics......................................................................................96
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) .................................................. 96
8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC).................................................. 98
8.4.3 PLL Characteristics........................................................................................................ 98
8.4.4 I/O AC Characteristics................................................................................................... 98
8.5 Analog Characteristics ..............................................................................................100
8.5.1 Reset and Power Control Block Characteristics...................................................... 100
8.5.2 12-bit SAR ADC............................................................................................................ 102
8.5.3 Digital to Analog Converter (DAC)............................................................................. 104
8.5.4 Internal Voltage Reference for M030G ..................................................................... 105
8.5.5 Internal Voltage Reference for M031G ..................................................................... 106
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8.5.6 Temperature Sensor.................................................................................................... 106
8.6 Communications Characteristics.............................................................................108
8.6.1 SPI Dynamic Characteristics...................................................................................... 108
8.6.2 I2C Dynamic Characteristics....................................................................................... 111
8.7 Flash DC Electrical Characteristics.........................................................................112
9 PACKAGE DIMENSIONS ............................................................................113
9.1 QFN 24L (3x3x0.9 mm Pitch:0.40 mm)..................................................................113
9.2 QFN 33L (4x4x0.8 mm Pitch:0.40 mm)..................................................................114
10ABBREVIATIONS ........................................................................................115
10.1 Abbreviations........................................................................................................115
11REVISION HISTORY....................................................................................117
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LIST OF FIGURES
Figure 4.1-1 M030G/M031G Series QFN 24-pin Diagram.............................................................18
Figure 4.1-2 M030G/M031G Series QFN 33-pin Diagram.............................................................19
Figure 4.1-3 M030G Series QFN 24-pin Multi-function Pin Diagram .............................................20
Figure 4.1-4 M030GTC1AE and M030GTD1AE Multi-function Pin Diagram.................................22
Figure 4.1-5 M031G Series QFN 24-pin Multi-function Pin Diagram .............................................24
Figure 4.1-6 M031GTD2AE and M031GTC2AE Multi-function Pin Diagram.................................26
Figure 5-1 NuMicro M030G/M031G Block Diagram.......................................................................34
Figure 6.1-1 Functional Block Diagram ..........................................................................................35
Figure 6.2-1 System Reset Sources...............................................................................................38
Figure 6.2-2 nRESET Reset Waveform .........................................................................................40
Figure 6.2-3 Power-on Reset (POR) Waveform.............................................................................41
Figure 6.2-4 Low Voltage Reset (LVR) Waveform .........................................................................41
Figure 6.2-5 Brown-out Detector (BOD) Waveform .......................................................................42
Figure 6.2-6 NuMicro® M030G/M031G Power Distribution Diagram .............................................44
Figure 6.2-7 Power Mode State Machine.......................................................................................46
Figure 6.2-8 SRAM Memory Organization .....................................................................................49
Figure 6.2-9 NuMicro® M030G/M031G Bus Matrix Diagram..........................................................49
Figure 6.2-10 Temperature Sensor Conversion Waveform ...........................................................50
Figure 6.2-11 MANCH_TXD Modulated with BPWM1_CHn..........................................................52
Figure 6.3-1 Clock Generator Global View Diagram ......................................................................59
Figure 6.3-2 Clock Generator Block Diagram.................................................................................60
Figure 6.3-3 System Clock Block Diagram.....................................................................................60
Figure 6.3-4 SysTick Clock Control Block Diagram .......................................................................61
Figure 6.3-5 Clock Output Block Diagram......................................................................................62
Figure 8.1-1 Soldering Profile from J-STD-020C ...........................................................................87
Figure 8.4-1 HIRC vs. Temperature ...............................................................................................97
Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................101
Figure 8.5-2 Typical connection with internal voltage reference ..................................................105
Figure 8.5-3 Typical connection with internal voltage reference ..................................................106
Figure 8.6-1 SPI Master Mode Timing Diagram...........................................................................108
Figure 8.6-2 SPI Slave Mode Timing Diagram.............................................................................110
Figure 8.6-3 I2C Timing Diagram..................................................................................................111
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List of Tables
Table 2.1-1 NuMicro M030G/M031G Series Key Features Support Table......................................9
Table 4.1-1 M030GGC1AE and M030GGD1AE Multi-function Pin Table .....................................21
Table 4.1-2 M030GTC1AE and M030GTD1AE Pin Multi-function Pin Table ................................23
Table 4.1-3 M031GGD2AE and M031GGC2AE Multi-function Pin Table .....................................25
Table 4.1-4 M031GTD2AE and M031GTC2AE Pin Multi-function Pin Table ................................27
Table 6.2-1 Reset Value of Registers.............................................................................................39
Table 6.2-2 DAC Reset Retention Value of Registers ...................................................................40
Table 6.2-3 GPIO Reset Retention Value of Registers ..................................................................40
Table 6.2-4 Power Mode Table ......................................................................................................45
Table 6.2-5 Power Mode Entry Setting Table.................................................................................45
Table 6.2-6 Power Mode Difference Table.....................................................................................45
Table 6.2-7 Clocks in Power Modes...............................................................................................46
Table 6.2-8 Condition of Entering Power-down Mode Again .........................................................47
Table 6.2-9 Address Space Assignments for On-Chip Controllers ................................................48
Table 6.2-10 Temperature Data Truth Table..................................................................................51
Table 6.2-11 Exception Model........................................................................................................55
Table 6.2-12 Interrupt Number Table .............................................................................................56
Table 6.2-13 Vector Figure Format ................................................................................................56
Table 6.11-1 NuMicro® M030G/M031G Series UART Features ....................................................71
Table 6.19-1 Peripherals Interconnect Matrix table........................................................................80
Table 8.1-1 Voltage Characteristics ...............................................................................................83
Table 8.1-2 Current Characteristics................................................................................................83
Table 8.1-3 Thermal Characteristics ..............................................................................................84
Table 8.1-4 EMC Characteristics....................................................................................................85
Table 8.1-5 Package Moisture Sensitivity (MSL) ...........................................................................86
Table 8.1-6 Soldering Profile ..........................................................................................................87
Table 8.2-1 General Operating Conditions.....................................................................................88
Table 8.3-1 Current Consumption in Normal Run Mode................................................................89
Table 8.3-2 Current Consumption in Idle Mode .............................................................................90
Table 8.3-3 Chip Current Consumption in Power-down Mode.......................................................91
Table 8.3-4 Peripheral Current Consumption.................................................................................92
Table 8.3-5 Low-power Mode Wakeup Timings.............................................................................93
Table 8.3-6 I/O Current Injection Characteristics ...........................................................................94
Table 8.3-7 I/O Input Characteristics..............................................................................................94
Table 8.3-8 I/O Output Characteristics...........................................................................................95
Table 8.3-9 nRESET Input Characteristics.....................................................................................95
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Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics.............................96
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics.............................98
Table 8.4-3 PLL characteristics......................................................................................................98
Table 8.4-4 I/O AC Characteristics.................................................................................................99
Table 8.5-1 Reset and Power Control Unit...................................................................................100
Table 8.6-1 SPI Master Mode Characteristics..............................................................................108
Table 8.6-2 SPI Slave Mode Characteristics................................................................................109
Table 8.6-3 I2C Characteristics.....................................................................................................111
Table 8.7-1 Flash DC Electrical Characteristics...........................................................................112
Table 10.1-1 List of Abbreviations................................................................................................116
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1 GENERAL DESCRIPTION
The NuMicro® M030G/M031G 32-bit microcontroller series is designed for Optical Transceiver Module
applications, both of the M030G and the M031G series have a built-in temperature sensor with ±1.6°C
deviation from 0°C to 70°C and ±2°C deviation from -40°C to 105°C. Especially, the M031G series
supports the “Pilot Tone Modulation” to realize the required OAM functions for the optical path network.
Therefore, the M031G series is equipped with a high flexibility programmable Hardware Manchester
Codec with CRC to encode and decode low-frequency dither signal and 1 set of DAC with “Auto Data
Generation” function to generate the smooth sine waveform for the pilot tone modulation of optical path
network up to 500kHz.
The M030G/M031G series is based on Arm® Cortex® -M0 core with 32-bit hardware multiplier/divider. It
runs up to 48/72 MHz and features 32 Kbytes and 64 Kbytes Flash, 4 Kbytes and 8 Kbytes SRAM, 2.7V
~ 3.6V operating voltage, 5V I/O tolerant, and -40°C to +105°C operating temperature.
The M030G/M031G series provides plenty of peripherals including up to 6 sets of 32-bit timers, 1 set of
UART with the RS485 and One-Wire mode, 1 set of SPI, 2 sets of I2C supporting 1 MHz Slave Mode,
and up to 7 channels of PDMA to offload CPU loading. Furthermore, both of these 2 series support I2C
bootloader for Optical Transceiver Module applications to program the application code into the
M030/M031G series MCU through the I2C interface.
The M030G/M031G series also provides rich analog peripherals including internal voltage reference that
can output 2.5V, up to 16 channels of 1.4 MSPS 12-bit SAR ADC and 4 sets of 12-bit DAC. In addition,
1 set of DAC in the M031G series supports Auto Data Generation function.
In order to fit the small form factor requirement of the optical module, the M030G/M031G series provides
the QFN 24-pin (3x3 mm) and QFN 33-pin (4x4 mm) small form factor package by pin-compatible across
these 2 series to make the system design and change parts easily.
For the development system, Nuvoton provides the NuMaker evaluation board and Nuvoton Nu-Link
debugger. The 3rd Party IDE such as Keil MDK, IAR EWARM, Eclippse IDE with GNU GCC compilers
are also supported.
* 1 set of DAC with Auto Data Generation function
Temp. Internal MANCH
Product Line
UART
I2C
SPI/ I2S Timer BPWM PDMA
ADC
DAC
CRC
Sensor VREF
Codec
√
√
√
√
√
√
M030G
M031G
1
1
2
2
1
1
2
6
6
6
5
7
16
16
4
√
4*
Table 2.1-1 NuMicro M030G/M031G Series Key Features Support Table
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2 FEATURES
2.1 M030G/M031G Features
Core and System
Arm® Cortex® -M0 core, running up to 72 MHz
Built-in Nested Vectored Interrupt Controller (NVIC)
24-bit system tick timer
Arm® Cortex® -M0
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Brown-out Detector
(BOD)
Two-level BOD with brown-out interrupt and reset option
(2.7V/2.5V)
Low Voltage Reset (LVR)
Security
LVR with 2.3V threshold voltage level
96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
Memories
Up to 64/32 KB on-chip Application ROM (APROM)
Up to 2 KB on-chip Flash for user-defined loader (LDROM)
Up to 512 bytes non-readable Security Protection ROM (SPROM)
All on-chip Flash support 512 bytes page erase
Flash
Fast Flash programming verification with CRC-32 checksum
calculation
On-chip Flash programming with In-Chip Programming (ICP), In-
System Programming (ISP) and In-Application Programming (IAP)
capabilities
2-wired ICP Flash updating through SWD/ICE interface
Up to 8 KB on-chip SRAM
Byte-, half-word- and word-access
PDMA operation
SRAM
Supports 8-bits, 16-bits and 32-bits configurable polynomials
Programmable initial value and seed value
Programmable order reverse setting and one’s complement setting
Cyclic Redundancy
Calculation (CRC) -
Configurable
for input data and CRC checksum
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
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Uses DMA to write data with performing CRC operation
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
Programmable initial value and seed value
Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC)
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
Up to 7 independent and configurable channels for automatic data
transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using Scatter-
Gather Transfer mode
Peripheral DMA (PDMA)
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
48 MHz High-speed Internal RC oscillator (HIRC)
38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wake-up operation
Internal Clock Source
Up to 144 MHz on-chip PLL, allows CPU operation up to the
maximim CPU frequency without the need for a high-frequency
crystal
Timers
Up to 6 sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Supports event counting function to count the event from external
pins
32-bit Timer
Supports external capture pin for interval measurement and
resetting 24-bit up counter
Supports chip wake-up function, if a timer interrupt signal is
generated
16-bit counters with 12-bit clock pre-scale for 144 MHz PWM output
channels
Basic PWM (BPWM)
Up to 6 independent input capture channels with 16-bit resolution
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counter
Up, down or up-down PWM counter type
Mask function and tri-state output for each PWM channel
Able to trigger ADC to start conversion
Able to trigger DAC to start conversion
20-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection),
HCLK/2048 with 9 selectable time-out period
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Watchdog
Supports four WDT reset delay periods, including 1026, 130, 18 or
3 WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset
Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale
Window Watchdog
Suspended in Idle/Power-down mode
Analog Interfaces
Internal built-in reference has 2.048V and 2.5V two voltage level
selection for ADC, DAC or external devices
Voltage Reference
Supports ADC and DAC references voltage from internal built-in
reference voltage, or external VREF pin
Analog input voltage range: 0 ~ AVDD
One 12-bit, up to 1.4 MSPS SAR ADC with up to 16 single-ended
input channels or 8 differential input pairs; 10-bit accuracy is
guaranteed
Internal channels for band-gap VBG input
Supports external VREF pin or internal built-in reference voltage
Supports calibration capability
Four operation modes: Single mode, Burst mode, Single-cycle
Scan mode and Continuous Scan mode
ADC
Analog-to-Digital conversion can be triggered by software (ADST),
external pin (STADC), Timer 0~1 overflow pulse trigger, and
BPWM1 trigger
Each conversion result is held in data register of each channel with
valid and overrun indicators
Supports conversion result monitor by compare mode function
Configurable ADC external sampling time
PDMA operation
Supports floating detect function
DAC
Analog input voltage range: 0 ~ AVDD
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Supports four 12-bit, 1 MSPS voltage type DAC
Supports 12- or 8-bit output mode
Supports external VREF pin or internal built-in reference voltage
Digital-to-Analog conversion can be triggered by software
(SWTRG), Timer 0~5 overflow pulse trigger, and BPWM1 trigger
Supports PDMA mode
Supports group mode of synchronized update capability for two
DACs
Supports DAC output retention when system reset
1 set of DAC Supports Auto Data Generation function in M031G
series
Built-in calibrated temperature sensor
Supported temperature range: –40°C to 105°C
Precision: ±2 °C
Temperature Sensor
Communication Interfaces
Low-power UARTs with up to 7.2 MHz baud rate
Auto-Baud Rate measurement function
Supports low power UART (LPUART): baud rate clock from LIRC
(38.4 kHz) with 9600bps in Power-down mode even system clock
is stopped
1-byte FIFOs with programmable level trigger
Auto flow control (nCTS and nRTS)
Supports IrDA (SIR) function
Supports RS-485 9-bit mode and direction control
Supports nCTS and incoming data wake-up function in idle mode
Low-power UART
Supports hardware or software enables to program nRTS pin to
control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and receive/transmit
FIFO overflow detection functions
PDMA operation
Supports Single-wire function mode
Supports two sets of I2C devices with Master/Slave mode
Supports Standard mode (100 kbps), Fast mode (400 kbps), Fast
mode plus (1 Mbps)
I2C
Supports 7 bits mode
Programmable clocks allowing for versatile rate control
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Supports multiple address recognition (four slave address with
mask option)
Supports multi-address power-down wake-up function
PDMA operation
Supports receiving continuous data bytes in none stretch mode
Up to 36 MHz in Master mode and up to 16 MHz in Slave mode at
2.7V~3.6V system voltage
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and
receive FIFO buffers
MSB first or LSB first transfer sequence
Byte reorder function
SPI
Supports Byte or Word Suspend mode
Supports one data channel half-duplex transfer
Supports receive-only mode
PDMA operation
Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode
Configured as interrupt source with edge/level trigger setting
Supports 5V-tolerance function except analog I/O (PA.0 ~ PA.3,
PB.0~PB.15, PF0)
GPIO
Enabling the pin interrupt function will also enable the wake-up
function
Input schmitt trigger function
Supports independent pull-up control
Supports encode/decode Manchester code
Supports different modulation signal format
–
Programmable Idle pattern
–
–
Programmable preamble style and its transmitted number
Programmable data size in a frame
Manchester Codec
Supports configurable Manchester bit rate
Supports selectable deglitch time function
Supports PDMA for receiving/transmitting
Supports Manchester encoded edge function to trigger Timer
Controller
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3 PARTS INFORMATION
3.1 Package Type
QFN24
QFN33
M030GTC1AE
M030GTD1AE
M031GTC2AE
M031GTD2AE
M030GGC1AE
M030GGD1AE
M031GGC2AE
M031GGD2AE
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3.2
M030G/M031G Series Naming Rule
M0
30G
Line
T
D
1
A
E
Core
Package
Flash
SRAM
Reserve
Temperature
E:-40°C ~ 105°C
Cortex-M0
30: Base
G: QFN24
C: 32 KB
D: 64 KB
1: 4 KB
2: 8 KB
31: with
Manchester
encode/decode
(3x3x0.9 mm)
T: QFN33
(4x4x0.8 mm)
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3.3 M030G/M031G Series Selection Guide
M030G (Base)
Part Number
M031G (Manchester)
GC1AE
GD1AE
TC1AE
TD1AE
GC2AE
GD2AE
TC2AE
TD2AE
Flash (KB)
SRAM (KB)
32
64
32
64
32
64
32
64
4
2
8
2
LDROM (KB)
SPROM (Bytes)
System Frequency (MHz)
PLL (MHz)
512
48
-
512
72
144
I/O
19
28
19
28
32-bit Timer
2
1
1
2
6
1
UART
SPI/I2S
1
2
√
I²C/SMBus
Manchester
BPWM
-
6
5
√
-
6
7
-
PDMA
CRC
CRC- Configurable
12-bit SAR ADC
12-bit DAC
√
11
16
11
16
4
√
√
4*
√
Temperature Sensor
Internal Voltage Reference
Package
√
QFN24
QFN33
QFN24
QFN33
DAC*: 1 set supports Auto Data Generation function
May 31, 2021
Page 17 of 118
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M030G/M031G Series
4 PIN CONFIGURATION
Users can find pin configuration information in the M030G/M031G Multi-function Pin diagram sections
or by using NuTool - PinConfigure. The NuTool - PinConfigure contains all NuMicro® Family chip series
with all part number, and helps users configure GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1
M030G/M031G Series Pin Diagram
M030G/M031G Series QFN 24-Pin Diagram
Corresponding Part Number: M030GGC1AE, M030GGD1AE, M031GGD2AE, M031GGC2AE
20
21
22
23
24
12
11
10
9
PB.4
PB.3
PB.2
PC.1
PB.1
PB.11
PB.12
PA.0
Top transparent view
QFN24
PA.1
8
PA.2
Figure 4.1-1 M030G/M031G Series QFN 24-pin Diagram
May 31, 2021
Page 18 of 118
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M030G/M031G Series
M030G/M031G Series QFN 33-Pin Diagram
Corresponding Part Number: M030GTC1AE, M030GTD1AE, M031GTD2AE, M031GTC2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
PB.3
PB.2
PF.3
Top transparent view
PB.11
PB.12
PB.13
PB.14
PB.15
PA.0
PC.1
PB.1
QFN33
PA.14
PA.12
PA.13
PB.0
33 EPAD
PA.1
Figure 4.1-2 M030G/M031G Series QFN 33-pin Diagram
May 31, 2021
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Rev 1.00
M030G/M031G Series
4.1.2
M030G Series Multi-function Pin Diagram
M030G Series QFN 24-Pin Multi-function Pin Diagram
Corresponding Part Number: M030GGC1AE, M030GGD1AE
20
21
22
23
24
12
11
10
9
INT1 / TM1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3
INT3 / TM1 / BPWM1_CH3 / I2C1_SDA / ADC0_CH2 / PB.2
ADC0_ST / I2C0_SCL / PC.1
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD
Top transparent view
QFN24
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD
8
BPWM1_CH4 / I2C1_SCL / UART0_RXD / ADC0_CH1 / PB.1
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA
Figure 4.1-3 M030G Series QFN 24-pin Multi-function Pin Diagram
Pin Pin Function
PB.0 / ADC0_CH0 / I2C1_SDA
1
2
3
4
5
6
7
VREF
VSS
VDD
nRESET/ICE_CLK
PF.0 / ICE_DAT
PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / CLKO
May 31, 2021
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M030G/M031G Series
Pin Pin Function
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA
8
9
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0
PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1
VSS
PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5
PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4
PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1
PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / INT2
PB.2 / ADC0_CH2 / I2C1_SDA / BPWM1_CH3 / TM1 / INT3
PC.1 / I2C0_SCL / ADC0_ST
PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SCL / BPWM1_CH4
Table 4.1-1 M030GGC1AE and M030GGD1AE Multi-function Pin Table
May 31, 2021
Page 21 of 118
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M030G/M031G Series
M030G Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M030GTC1AE, M030GTD1AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
INT2 / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3
INT3 / TM1 / BPWM1_CH3 / I2C1_SDA / ADC0_CH2 / PB.2
ADC0_ST / I2C0_SCL / PC.1
PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
Top transparent view
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM0_EXT
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD
BPWM1_CH4 / I2C1_SCL / UART0_RXD / ADC0_CH1 / PB.1
BPWM1_CH4 / UART0_TXD / PA.14
QFN33
BPWM1_CH2 / I2C1_SCL / PA.12
BPWM1_CH3 / I2C1_SDA / PA.13
33 EPAD
I2C1_SDA / ADC0_CH0 / PB.0
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD
Figure 4.1-4 M030GTC1AE and M030GTD1AE Multi-function Pin Diagram
Pin Pin Function
1
2
3
4
5
6
VREF
VDD
AVDD
nRESET/ICE_CLK
PF.0 / ICE_DAT
PA.15 / UART0_RXD / BPWM1_CH5
May 31, 2021
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M030G/M031G Series
Pin Pin Function
7
8
9
PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / CLKO
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD
10 PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD
11 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT
12 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
13 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM0_EXT
14 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM1_EXT
15 PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0
16 PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
17 PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1
18 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1
19 PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2
20 PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3
21 PB.7 / ADC0_CH7 / BPWM1_CH4 / INT5
22 PB.6 / ADC0_CH6 / BPWM1_CH5 / INT4
23 PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
24 PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1
25 PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / INT2
26 PB.2 / ADC0_CH2 / I2C1_SDA / BPWM1_CH3 / TM1 / INT3
27 PC.1 / I2C0_SCL / ADC0_ST
28 PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SCL / BPWM1_CH4
29 PA.14 / UART0_TXD / BPWM1_CH4
30 PA.12 / I2C1_SCL / BPWM1_CH2
31 PA.13 / I2C1_SDA / BPWM1_CH3
32 PB.0 / ADC0_CH0 / I2C1_SDA
33 EPAD
Table 4.1-2 M030GTC1AE and M030GTD1AE Pin Multi-function Pin Table
May 31, 2021
Page 23 of 118
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M030G/M031G Series
4.1.3
M031G Series Multi-function Pin Diagram
M031G Series QFN 24-Pin Multi-function Pin Diagram
Corresponding Part Number: M031GGD2AE, M031GGC2AE
20
21
22
23
24
12
11
10
9
INT1 / TM1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM2 / MANCH_TXD / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3
INT3 / TM3 / MANCH_RXD / TM1 / BPWM1_CH3 / I2C1_SCL / TM5 / I2C1_SDA / ADC0_CH2 / PB.2
ADC0_ST / I2C0_SCL / I2C1_SCL / PC.1
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4
Top transparent view
QFN24
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD
8
BPWM1_CH4 / I2C1_SCL / I2C1_SDA / UART0_RXD / ADC0_CH1 / PB.1
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD
Figure 4.1-5 M031G Series QFN 24-pin Multi-function Pin Diagram
Pin Pin Function
PB.0 / ADC0_CH0 / I2C1_SDA
1
2
3
4
VREF
VSS
VDD
May 31, 2021
Page 24 of 118
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M030G/M031G Series
Pin Pin Function
nRESET/ICE_CLK
PF.0 / ICE_DAT
5
6
7
PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / BPWM1_CH3 / CLKO / BPWM1_CH5
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD
PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1
VSS
PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5
PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4
PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1
PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / MANCH_TXD / TM2 / INT2
PB.2 / ADC0_CH2 / I2C1_SDA / TM5 / I2C1_SCL / BPWM1_CH3 / TM1 / MANCH_RXD / TM3 / INT3
PC.1 / I2C1_SCL / I2C0_SCL / ADC0_ST
PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SDA / I2C1_SCL / BPWM1_CH4
Table 4.1-3 M031GGD2AE and M031GGC2AE Multi-function Pin Table
May 31, 2021
Page 25 of 118
Rev 1.00
M030G/M031G Series
M031G Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M031GTD2AE, M031GTC2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
INT2 / TM2 / MANCH_TXD / TM0 / BPWM1_CH2 / I2C1_SCL / ADC0_CH3 / PB.3
INT3 / TM3 / MANCH_RXD / TM1 / BPWM1_CH3 / I2C1_SCL / TM5 / I2C1_SDA / ADC0_CH2 / PB.2
ADC0_ST / I2C0_SCL / I2C1_SCL / PC.1
PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
Top transparent view
PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM4_EXT / TM2_EXT / TM0_EXT
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
BPWM1_CH4 / I2C1_SCL / I2C1_SDA / UART0_RXD / ADC0_CH1 / PB.1
TM4_EXT / BPWM1_CH4 / I2C1_SCL / UART0_TXD / PA.14
TM4 / BPWM1_CH2 / I2C1_SCL / PA.12
QFN33
PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT
TM5 / BPWM1_CH3 / I2C1_SDA / PA.13
PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD
33 EPAD
I2C1_SDA / ADC0_CH0 / PB.0
Figure 4.1-6 M031GTD2AE and M031GTC2AE Multi-function Pin Diagram
Pin Pin Function
1
2
3
4
5
VREF
VDD
AVDD
nRESET/ICE_CLK
PF.0 / ICE_DAT
May 31, 2021
Page 26 of 118
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M030G/M031G Series
Pin Pin Function
6
7
8
9
PA.15 / UART0_RXD / BPWM1_CH5 / TM5_EXT
PA.3 / DAC3_OUT / SPI0_SS / I2C0_SMBAL / I2C1_SCL / BPWM1_CH3 / CLKO / BPWM1_CH5
PA.2 / DAC2_OUT / SPI0_CLK / I2C0_SMBSUS / I2C1_SDA / BPWM1_CH2 / MANCH_TXD
PA.1 / DAC1_OUT / SPI0_MISO / UART0_TXD / BPWM1_CH1 / MANCH_RXD
10 PA.0 / DAC0_OUT / SPI0_MOSI / UART0_RXD / BPWM1_CH0 / BPWM1_CH4
11 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT
12 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
13 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM4_EXT / TM2_EXT / TM0_EXT
14 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM5_EXT / TM3_EXT / TM1_EXT / MANCH_TXD
15 PB.11 / ADC0_CH11 / UART0_nCTS / UART0_TXD / I2C1_SCL / BPWM1_CH0 / MANCH_RXD
16 PF.3 / UART0_TXD / I2C0_SCL / BPWM1_CH0
17 PF.2 / UART0_RXD / I2C0_SDA / BPWM1_CH1
18 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA / BPWM1_CH1
19 PB.9 / ADC0_CH9 / UART0_TXD / BPWM1_CH2
20 PB.8 / ADC0_CH8 / UART0_RXD / BPWM1_CH3
21 PB.7 / ADC0_CH7 / MANCH_TXD / BPWM1_CH4 / INT5
22 PB.6 / ADC0_CH6 / MANCH_RXD / BPWM1_CH5 / INT4
23 PB.5 / ADC0_CH5 / I2C0_SCL / TM0 / INT0
24 PB.4 / ADC0_CH4 / I2C0_SDA / TM1 / INT1
25 PB.3 / ADC0_CH3 / I2C1_SCL / BPWM1_CH2 / TM0 / MANCH_TXD / TM2 / INT2
26 PB.2 / ADC0_CH2 / I2C1_SDA / TM5 / I2C1_SCL / BPWM1_CH3 / TM1 / MANCH_RXD / TM3 / INT3
27 PC.1 / I2C1_SCL / I2C0_SCL / ADC0_ST
28 PB.1 / ADC0_CH1 / UART0_RXD / I2C1_SDA / I2C1_SCL / BPWM1_CH4
29 PA.14 / UART0_TXD / I2C1_SCL / BPWM1_CH4 / TM4_EXT
30 PA.12 / I2C1_SCL / BPWM1_CH2 / TM4
31 PA.13 / I2C1_SDA / BPWM1_CH3 / TM5
32 PB.0 / ADC0_CH0 / I2C1_SDA
33 EPAD
Table 4.1-4 M031GTD2AE and M031GTC2AE Pin Multi-function Pin Table
May 31, 2021
Page 27 of 118
Rev 1.00
M030G/M031G Series
4.2 Pin Mapping
Different part number with same package might has different function. Please refer to the
M030G/M031G Series Selection Guide, Pin Configuration section or NuTool - PinConfig.
Corresponding Part Number: M030GxC, M030GxD, M031GxC, M031GxD series.
M030G/M031G Series
Pin Name
VREF
24 Pin
33 Pin
1
2
3
4
VSS
VDD
2
3
AVDD
nRESET/ICE_CLK
PF.0
5
6
4
5
PA.15
PA.3
6
7
8
7
PA.2
8
PA.1
9
9
PA.0
10
10
11
12
13
14
15
16
17
18
19
PB.15
PB.14
PB.13
PB.12
PB.11
PF.3
11
12
13
14
PF.2
PB.10
PB.9
VSS
15
16
17
18
19
20
21
22
23
PB.8
20
21
22
23
24
25
26
27
PB.7
PB.6
PB.5
PB.4
PB.3
PB.2
PC.1
May 31, 2021
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M030G/M031G Series
PB.1
PA.14
PA.12
PA.13
PB.0
24
28
29
30
31
32
33
1
EPAD
May 31, 2021
Page 29 of 118
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M030G/M031G Series
4.3 Pin Functional Description
Corresponding Part Number: M030GxC, M030GxD, M031GxC, M031GxD series.
Group
Pin Name
ADC0_CH0
Type
Description
A
ADC0 channel 0 analog input.
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
ADC0_CH12
ADC0_CH13
ADC0_CH14
ADC0_CH15
ADC0_ST
A
A
ADC0 channel 1 analog input.
ADC0 channel 2 analog input.
ADC0 channel 3 analog input.
ADC0 channel 4 analog input.
ADC0 channel 5 analog input.
ADC0 channel 6 analog input.
ADC0 channel 7 analog input.
ADC0 channel 8 analog input.
ADC0 channel 9 analog input.
ADC0 channel 10 analog input.
ADC0 channel 11 analog input.
ADC0 channel 12 analog input.
ADC0 channel 13 analog input.
ADC0 channel 14 analog input.
ADC0 channel 15 analog input.
ADC0 external trigger input pin.
BPWM1 channel 0 output/capture input.
BPWM1 channel 1 output/capture input.
A
A
A
A
A
ADC0
A
A
A
A
A
A
A
A
I
BPWM1_CH0
BPWM1_CH1
I/O
I/O
BPWM1
May 31, 2021
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Rev 1.00
M030G/M031G Series
Group
Pin Name
BPWM1_CH2
Type
Description
I/O
BPWM1 channel 2 output/capture input.
BPWM1 channel 3 output/capture input.
BPWM1 channel 4 output/capture input.
BPWM1 channel 5 output/capture input.
Clock Out
BPWM1_CH3
BPWM1_CH4
BPWM1_CH5
CLKO
I/O
I/O
I/O
O
CLKO
DAC0
DAC1
DAC2
DAC3
DAC0_OUT
DAC1_OUT
DAC2_OUT
DAC3_OUT
I2C0_SCL
A
DAC0 channel analog output.
DAC1 channel analog output.
DAC2 channel analog output.
DAC3 channel analog output.
I2C0 clock pin.
A
A
A
I/O
I/O
O
I2C0_SDA
I2C0 data input/output pin.
I2C0
I2C0_SMBAL
I2C0_SMBSUS
I2C1_SCL
I2C0 SMBus SMBALTER pin
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1 clock pin.
O
I/O
I/O
I2C1
I2C1_SDA
I2C1 data input/output pin.
Serial wired debugger clock pin
ICE_CLK
I
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK
pin
nRESET : External reset input, active LOW with an internal pull-up. Set
this pin low reset to initial state.
ICE
nRESET /ICE_DAT
I/O
ICE_DAT : Serial wired debugger data pin.
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT
pin.
INT0
INT1
INT0
INT1
INT2
I
I
I
External interrupt 0 input pin.
External interrupt 1 input pin.
External interrupt 2 input pin.
INT2
May 31, 2021
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Rev 1.00
M030G/M031G Series
Group
INT3
Pin Name
Type
Description
INT3
INT4
INT5
I
External interrupt 3 input pin.
INT4
INT5
I
External interrupt 4 input pin.
External interrupt 5 input pin.
I
MANCH_RXD
MANCH_TXD
VDD
I
Manchester data receiver input pin.
MANCH
O
Manchester data transmitter output pin.
Power supply for I/O ports and LDO source for internal PLL and digital
circuit.
P
VSS
P
Ground pin for digital circuit.
AVDD
P
Power supply for internal analog circuit.
Ground pin for analog circuit.
Power
AVSS
P
ADC and DAC reference voltage input.
VREF
A
Note: This pin needs to be connected with a 1uF capacitor.
EPAD
P
Exposed pad served as ground pin (VSS).
SPI0 serial clock pin.
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SS
TM0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI0 MISO (Master In, Slave Out) pin.
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 slave select pin.
SPI0
Timer0 event counter input/toggle output pin.
Timer0 external capture input/toggle output pin.
Timer1 event counter input/toggle output pin.
Timer1 external capture input/toggle output pin.
Timer2 event counter input/toggle output pin.
Timer2 external capture input/toggle output pin.
TM0
TM1
TM0_EXT
TM1
TM1_EXT
TM2
I/O
I/O
TM2
I/O
TM2_EXT
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Group
Pin Name
Type
Description
I/O
TM3
Timer3 event counter input/toggle output pin.
Timer3 external capture input/toggle output pin.
Timer4 event counter input/toggle output pin.
Timer4 external capture input/toggle output pin.
Timer5 event counter input/toggle output pin.
Timer5 external capture input/toggle output pin.
UART0 data receiver input pin.
TM3
I/O
I/O
I/O
I/O
I/O
TM3_EXT
TM4
TM4
TM5
TM4_EXT
TM5
TM5_EXT
UART0_RXD
UART0_TXD
UART0_nCTS
UART0_nRTS
I
O
I
UART0 data transmitter output pin.
UART0
UART0 clear to Send input pin.
O
UART0 request to Send output pin.
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5 BLOCK DIAGRAM
* Only in M031G Series
** M031G Series is equipped with 1 set of DAC with Auto Data Generation function
Figure 5-1 NuMicro M030G/M031G Block Diagram
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6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality.
The processor can execute Thumb code and is compatible with other Cortex® -M profile processor. The
profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an
exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset,
and can be entered as a result of an exception return. Figure 6.1-1 shows the functional controller of
processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
– Arm® 6-M Thumb® instruction set
– Thumb-2 technology
– Arm® 6-M compliant 24-bit SysTick timer
– A 32-bit hardware multiplier
– System interface supported with little-endian data accesses
– Ability to have deterministic, fixed-latency, interrupt handling
– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
– C Application Binary Interface compliant exception model. This is the Armv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use of
pure C functions as interrupt handlers
– Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
– 32 external interrupt inputs, each with four levels of priority
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– Dedicated Non-maskable Interrupt (NMI) input
– Supports for both level-sensitive and pulse-sensitive interrupt lines
– Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Debug support:
– Four hardware breakpoints
– Two watchpoints
– Program Counter Sampling Register (PCSR) for non-intrusive code profiling
– Single step and vector catch capabilities
Bus interfaces:
– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
– Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be read
from SYS_RSTSTS register to determine the reset source. Hardware reset sources are from peripheral
signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M0 core only by writing 1 to CPURST (SYS_IPRST0[1])
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Hardware Reset Sources
nRESET
Glitch Filter
NRESET Reset
POR Reset
33 us
~50k ohm
@3.3v
Power-on
Reset
POROFF(SYS_PORCTL[15:0])
Reset Pulse Width
~3.2ms
VDD
LVREN(SYS_BODCTL[7])
LVR Reset
Low Voltage
Reset
Reset Pulse Width
~3.2ms
AVDD
BODRSTEN(SYS_BODCTL[3])
BOD Reset
WDT Reset
Brown-out
Reset
Reset Pulse Width
~3.2ms
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
Lockup Reset
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
Software Reset Sources
CHIP Reset
MCU Reset
CPU Reset
CHIP Reset
CHIPRST(SYS_IPRST0[0])
Reset Pulse Width
2 system clocks
Reset Pulse Width
2 system clocks
MCU Reset
SYSRSTREQ(AIRCR[2])
CPU Reset
CPURST(SYS_IPRST0[1])
Reset Pulse Width
2 system clocks
Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there are
some registers with particularly different reset sources. Table 6.2-1 lists these differences.
Reset Sources
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1
CHIPRST
0x0
0x0
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
0x1
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
0x1
0x0
0x1
(SYS_BODCTL[0])
BODVL
(SYS_BODCTL[16])
BODRSTEN
(SYS_BODCTL[3])
WDTCKEN
0x1
0x7
-
0x1
0x7
-
-
-
0x1
0x7
-
(CLK_APBCLK0[0])
HCLKSEL
0x7
0x7
0x7
0x7
0x7
-
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(CLK_CLKSEL0[2:0])
WDTSEL
0x3
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HIRCSTB
(CLK_STATUS[4])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG
0
(WDT_CTL[1])
-
-
-
-
-
-
CONFIG CONFIG CONFIG CONFIG CONFIG
0
WDTEN
0
0
0
0
(WDT_CTL[7])
WDT_CTL
0x0800 0x0800
0x0800 0x0800
0x0800
0x0800
except bit 1 and bit 7.
WDT_ALTCTL
0x0000 0x0000
0x0000 0x0000
0x0000 0x0000
0x0000 0x0000
0x0000
0x0000
-
-
0x0000
0x0000
-
-
-
-
WWDT_RLDCNT
0x3F080 0x3F080 0x3F080 0x3F080 0x3F080
0x3F080
0
WWDT_CTL
-
-
-
0
0
0
0
0
WWDT_STATUS
WWDT_CNT
0x0000 0x0000
0x0000 0x0000
0x0000
0x3F
-
-
0x0000
0x3F
-
-
-
-
0x3F
0x3F
0x3F
0x3F
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG
0
BS
-
-
-
-
-
-
-
-
-
-
-
-
CONFIG CONFIG CONFIG CONFIG CONFIG
0
(FMC_ISPCTL[1])
0
0
0
0
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG
1
FMC_DFBA
CONFIG CONFIG CONFIG CONFIG CONFIG
1
1
1
1
1
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG
0
CBS
CONFIG CONFIG CONFIG CONFIG CONFIG
0
(FMC_ISPSTS[2:1))
0
0
0
0
Reload
Reload
Reload
Reload
Reload
Reload
base on
CONFIG
0
VECMAP
base on base on base on base on base on
CONFIG CONFIG CONFIG CONFIG CONFIG
0
(FMC_ISPSTS[23:9])
0
0
0
0
DAC IP Registers
Refer to Table 6.2-2 for DAC Reset Retention source and reset value.
(RETEN, DAC0_CTL[24]=1)
DAC IP Registers
Reset Value
-
(RETEN, DAC0_CTL[24]=0)
GPIO IP Registers
Refer to Table 6.2-3 for GPIO Reset Retention source and reset value.
Reset Value
(RETEN (GPIO_RET[0]) = 1)
GPIO IP Registers
-
-
(RETEN (GPIO_RET[0]) = 0)
Other Peripheral Registers
FMC Registers
Reset Value
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
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Reset Sources
Register
POR
Reset
NRESET
WDT
LVR
Reset
BOD
Reset
Lockup
CHIP
MCU
CPU
Reset
Value
DAC Registers
-
-
-
-
-
-
-
-
-
Value
Value
Value
SCPDIS
0x0
-
-
-
-
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
(SYS_VREFCTL[8])
PRELOADEN
0x0
0x0
0x0
0x0
-
-
-
-
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
(SYS_VREFCTL[6])
VREFSEL
(SYS_VREFCTL[1])
VREFEN
(SYS_VREFCTL[0])
TSBGEN
(SYS_TSCTL[1])
Table 6.2-2 DAC Reset Retention Value of Registers
Reset Sources
Register
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Reset
Value
Reset
Value
Reset
Value
Reset
Value
GPIO Registers
-
-
-
-
-
Table 6.2-3 GPIO Reset Retention Value of Registers
nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 33 us (glitch filter), chip will be reset. The nRESET
reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps
longer than 33 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source
is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
33 us
0.2 VDD
33 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
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Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be
reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR
module will detect the rising voltage and generate reset signal to system until the voltage is ready for
MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a POR
reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows the
power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function will
be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is lower
than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]),
chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above
VLVR and the state keeps longer than De-glitch time set by LVRDGSEL (SYS_BODCTL[14:12]). The
default setting of Low Voltage Reset is enabled without De-glitch function. Figure 6.2-4 shows the Low
Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
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Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL (SYS_BODCTL[16])
and the state keeps longer than De-glitch time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be
reset. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the
state keeps longer than De-glitch time set by BODDGSEL. Figure 6.2-5 shows the Brown-out Detector
waveform.
AVDD
VBODH
Hysteresis
VBODL
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to
check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog time-
out. User may decide to enable system reset during watchdog time-out to recover the system and take
action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
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CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3
System Power Distribution
In this chip, power distribution is divided into three segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which provides
a fixed 1.8V power for digital operation and I/O pins.
M030G/M031G package connect AVSS and VSS together.
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Internal
Reference
Voltage
12-bit ADC
12-bit DAC0~3
AVDD
AVSS
Low Voltage
Reset
Brown-out
Detector
Temperature
Sensor
SRAM
Flash
Digital Logic
1.8V
48 MHz
HIRC
38.4 kHz
LIRC
PLL
POR18
Oscillator
Oscillator
VDD to 1.8V
LDO
Power On
Control
POR33
IO Cell
Figure 6.2-6 NuMicro® M030G/M031G Power Distribution Diagram
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6.2.4
Power Modes and Wake-up Sources
This chip has a power manager unit to support several operating modes for saving power. Table 6.2-4
lists all power modes in the M030G/M031G series.
Mode
CPU Operating Maximum Speed ( MHz) LDO (V)
Clock Disable
Normal mode
Idle mode
72/48
1.8
1.8
1.8
All clocks are disabled by control register.
Only CPU clock is disabled.
CPU enters Sleep mode
Power-down mode CPU enters Power-down mode
All clocks are disabled, except LIRC. And only
WDT/Timer/UART peripheral clocks still enable
if their clock sources are selected as LIRC.
Table 6.2-4 Power Mode Table
There are different power mode entry settings and leaving condition for each power mode. Table 6.2-5
shows the entry setting for each power mode. When chip power-on, chip is running in normal mode.
User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCTL[7]) and execute
WFI instruction.
Register/Instruction
Mode
SLEEPDEEP
(SCR[2])
PDEN
CPU Run WFI Instruction
(CLK_PWRCTL[7])
Normal mode
0
0
0
0
NO
Idle mode
YES
(CPU enters Sleep mode)
Power-down mode
1
1
YES
(CPU enters Deep Sleep mode)
Table 6.2-5 Power Mode Entry Setting Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-6 lists the available
clocks for each power mode.
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all clocks stop
except LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode
after system reset released instruction.
CPU executes WFI
CPU sets sleep mode enable and power
down enable and executes WFI
instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD, GPIO
and EINT
Available Clocks
After Wake-up
All
All except CPU clock
LIRC
N/A
CPU back to normal mode CPU back to normal mode
Table 6.2-6 Power Mode Difference Table
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System reset released
Normal Mode
CPU Clock ON
PLL, HIRC, LIRC, HCLK, PCLK ON
Flash ON
1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
Wake-up events
occur
CPU executes WFI
Interrupts occur
PDWKIF (CLK_PWRCTL[6]) = 1
3. CPU executes WFI
Power-down Mode
CPU Clock OFF
PLL, HIRC, HCLK, PCLK OFF
LIRC ON
Idle Mode
CPU Clock OFF
PLL, HIRC, LIRC, HCLK, PCLK ON
Flash Halt
Flash Halt
Figure 6.2-7 Power Mode State Machine
Normal Mode
Idle Mode
ON
Power-Down Mode
HIRC48 (48 MHz OSC)
LIRC (38.4 kHz OSC)
PLL
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
Halt
HCLK/PCLK
CPU
ON
Halt
Halt
ON
Halt
SRAM retention
FLASH
ON
ON
Halt
TIMER
ON
ON/OFF1
ON/OFF2
ON/OFF3
Halt
WDT
ON
UART
ON
Others
ON
Table 6.2-7 Clocks in Power Modes
Note:
1. If TIMER clock source is selected as LIRC.
2. If WDT clock source is selected as LIRC.
3. If UART clock source is selected as LIRC.
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, BOD and GPIO
After chip enters power down, the following wake-up sources can wake up chip to normal mode. Table
6.2-8 lists the condition about how to enter Power-down mode again for each peripheral.
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User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear BODIF (SYS_BODCTL[4]).
INT
External Interrupt
GPIO Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
TIMER
WDT
Timer Interrupt
WDT Interrupt
nCTS wake-up
RX Data wake-up
Address match
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
After software writes 1 to clear WKIF (I2C_WKSTS[0]).
UART
I2C
Table 6.2-8 Condition of Entering Power-down Mode Again
System Memory Map
6.2.5
This chip provides 4G-byte addressing space. The memory locations assigned to each on-chip
controllers are shown in Table 6.2-9. The detailed register definition, memory space, and programming
will be described in the following sections for each on-chip peripheral. The M030G/M031G series only
supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_FFFF
0x2000_0000 – 0x2000_1FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (64 Kbytes)
SRAM Memory Space (8 Kbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4003_1000 – 0x4003_1FFF
SYS_BA
CLK_BA
NMI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO_BA
PDMA_BA
FMC_BA
CRC_BA
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
CRC Generator Registers
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_3000 – 0x4004_3FFF
0x4004_7000 – 0x4004_7FFF
0x4004_B000 – 0x400B_7FFF
0x4005_0000 – 0x4005_0FFF
WDT_BA
Watchdog Timer Control Registers
Analog-Digital-Converter (ADC) Control Registers
DAC01 Control Registers
ADC_BA
DAC01_BA
DAC23_BA
TMR01_BA
DAC23 Control Registers
Timer0/Timer1 Control Registers
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0x4005_1000 – 0x4005_1FFF
0x4005_2000 – 0x4005_2FFF
0x4005_B000 – 0x4005_BFFF
0x4006_1000 – 0x4006_1FFF
0x4007_0000 – 0x4007_0FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x400B_C000 – 0x400B_CFFF
TMR23_BA
TMR45_BA
BPWM1_BA
SPI0_BA
Timer2/Timer3 Control Registers
Timer4/Timer5 Control Registers
BPWM Control Registers
SPI0 Control Registers
UART_BA
I2C0_BA
UART0 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
MANCH_BA
Manchester Codec Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-9 Address Space Assignments for On-Chip Controllers
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6.2.6
SRAM Memory Organization
This chip supports embedded 4/8 Kbytes size SRAM:
Supports 4/8 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
Figure 6.2-8 shows the M030G/M031G series SRAM organization. The address between 0x2000_2000
to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses.
0x3FFF_FFFF
Reserved
Reserved
0x2000_2000
8K byte
0x2000_1000
SRAM bank0
4K byte
SRAM bank0
0x2000_0000
4K byte device
8K byte device
Figure 6.2-8 SRAM Memory Organization
6.2.7
Chip Bus Matrix
This chip supports Bus Matrix to manage the access arbitration between masters. The access arbitration
uses round-robin algorithm as the bus priority.
M1
PDMA
M0
Cortex® -M0
S0
S1
S2
APB0
S3
APB1
S4
AHB
(ctrl)
FLASH
SRAM
Figure 6.2-9 NuMicro® M030G/M031G Bus Matrix Diagram
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6.2.8
Temperature Sensor
This chip is equipped with an on-chip temperature sensor. Temperature sensor control registers are
located in SYS_TSCTL and SYS_TSDATA.
User should set both TSEN(SYS_TSCTL[0]) and TSBGEN(SYS_TSCTL[1]) bits to 1 to enable the
temperature sensor. User needs to wait 200us for temperatre sensor to be stable, and then set
TSST(SYS_TSCTL[2]) bit to 1 to start temperature sensor conversion.
After temperature sensor conversion is finished, TSEOC(SYS_TSDATA[0]) bit will be set to 1
automatically, and TSDATA(SYS_TSDATA[27:16]) will present the temperature sensor data. Figure
6.2-10 shows the timing waveform of temperature sensor conversion.
Tstartup
Tconversion
Tconversion
( > 200 us)
( < 100 ms)
( < 100 ms)
TSEN
(SYS_TSCTL[0])
TSBGEN
(SYS_TSCTL[1])
1st conversion
2nd conversion
Clear by
Clear by
hardware
hardware
TSST
(SYS_TSCTL[2])
Clear by software
Clear by software
TSEOC
(SYS_TSDATA[0])
TSDATA
(SYS_TSDATA[27:16])
1st Temperature Data[11:0]
2nd Temperature Data[11:0]
Figure 6.2-10 Temperature Sensor Conversion Waveform
Table 6.2-10 is a reference table for the relationship between temperature and TSDATA. Negative
temperature is represented in TSDATA(SYS_TSDATA[27:16]) by twos complement format, and per LSB
difference is equivalent to 0.0625 ° C.
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Temperature (°C)
Temperature Data (TSDATA)
128
127.9375
100
80
0x7FF
0x7FF
0x640
0x500
0x4B0
0x320
0x190
0x004
0x000
0xFFC
0xE70
0xC90
75
50
25
0.25
0
-0.25
-25
-55
Table 6.2-10 Temperature Data Truth Table
6.2.9
Internal Voltage Reference (INT_VREF)
This chip supports internal voltage reference (INT_VREF) to provide the voltage reference for ADC and
DACs. The INT_VREF routes to VREF pin. User can set VREFEN(SYS_VREFCTL[0]) to select ADC and
DACs reference voltage sourcing from external VREF pin supply or internal INT_VREF. If using external
VREF source, VREFEN needs to be set to 0, and INT_VREF will output floating.
When VREFEN is set to 1, INT_VREF will be enabled. In addition, user can select INT_VREF output
voltage level 2.048V or 2.5V by VREFSEL(SYS_VREFCTL[1]). However, VREFSEL must be decided
before VREFEN is set to 1.
When VREFEN is set to 1, PRELOADEN(SYS_VREFCTL[6]) will be set automatically to shorten VREF
discharge and stable time. User needs to disable PRELOADEN function after stable time, otherwise it
will affect the maximum load current that INT_VREF can provide.
6.2.10 MANCH_TXD Modulation with BPWM1
This chip supports MANCH_TXD to modulate with BPWM1_CH0 ~ BPWM1_CH5. User can set
MANCHMODEN (SYS_MODCTL[21:16]) to enable modulation function with each BPWM1 channel and
set MANCHMODL (SYS_MODCTL[29:24]) to select MANCH_TXD data high or low to modulate with
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BPWM1 channels. The Manchester modulation example waveform is shown in Figure 6.2-11.
BPWM1_CHn
MANCH_TXD
Modulated MANCH_TXD :
MANCHMODE[n] = 0
MANCHMODL[n] = x
&
MANCHMODE[n] = 1
&
MANCHMODH[n] = 0
MANCHMODE[n] = 1
&
MANCHMODH[n] = 1
Note: n=0, 1 .. 5
Figure 6.2-11 MANCH_TXD Modulated with BPWM1_CHn
6.2.11 Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip
operation. These system control registers are protected after the power-on reset till user to disable
register protection. For user to program these protected registers, a register protection disable sequence
needs to be followed by a special programming. The register protection disable sequence is writing the
data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100 continuously. Any
different data value, different sequence or any other write to other address during these three data writing
will abort the whole sequence. All proteced control registers are noted “(Write Protect)” and add an note
“Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in register description field.
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6.2.12 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-
write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used
as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer enable
bit.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
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6.2.13 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and
provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When an
interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from
a vector table in memory. There is no need to determine which interrupt is accepted and branch to the
starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also
automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At
the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal
execution. Thus it will take less and deterministic time to process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR
at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of
concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute
(at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one
without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
Exception Model and System Interrupt Map
Table 6.2-11 lists the exception model supported by the M030G/M031G series. Software can set four
levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-
configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after
three system exceptions “Reset”, “NMI” and “Hard Fault”.
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Exception Name
Vector Number
Priority
Reset
1
-3
NMI
Hard Fault
Reserved
2
3
-2
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
Reserved
12 ~ 13
14
PendSV
SysTick
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-11 Exception Model
Interrupt Number
Vector
Number
Interrupt Name
Interrupt
Interrupt Description
(Bit
In
Registers)
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
-
System exceptions
0
BODOUT
WDT_INT
EINT024
Brown-Out low voltage detected interrupt
Watchdog Timer interrupt
External interrupt fromEINT0,2,4.
External interrupt fromEINT1.3.5
External interrupt from PA, PB pin
External interrupt from PC, PF pin
Timer 4 interrupt
1
2
3
EINT135
4
GPAB_INT
GPCF_INT
TMR4_INT
TMR5_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
Reserved
SPI0_INT
Reserved
Reserved
5
6
7
Timer 5 interrupt
8
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
15
16
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
Reserved
SPI0 interrupt
Reserved
Reserved
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33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MANCH_INT
I2C0_INT
Manchester Codec interrupt
I2C0 interrupt
I2C1_INT
I2C1 interrupt
Reserved
Reserved
BPWM_INT
Reserved
BPWM interrupt
Reserved
DAC01_INT
DAC23_INT
TEMP_INT
PDMA_INT
Reserved
DAC0/1 device interrupt
DAC2/3 device interrupt
TEMP interrupt
PDMA interrupt
Reserved
PWRWU_INT
ADC_INT
Clock controller interrupt for chip wake-up from power-down state
ADC interrupt
Reserved
Reserved
Reserved
Reserved
Table 6.2-12 Interrupt Number Table
Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt
service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base address is fixed
at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the
entry point addresses for all exception handlers. The vector number on previous page defines the order
of entries in the vector table associated with exception handler entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Vector Number
Table 6.2-13 Vector Figure Format
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear policy,
both registers reading back the current enabled state of the corresponding interrupts. When an interrupt
is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not
be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by
reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively.
The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current
pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution
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status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting
four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the System
Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M0 core executes the
WFI instruction. After that, chip enters Power-down mode and waits for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 48 MHz
internal high speed RC oscillator (HIRC) and Programmable PLL output clock frequency (PLLFOUT) to
reduce the overall system power consumption. Figure 6.3-1 shows the clock generator and the overview
of the clock source control.
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HIRC
LIRC
48MHz
38.4 kHz
PCLK1
PCLK0
/1,/2,/4,/8,/16
I2C0
ADC
I2C1
HIRC
PLLFOUT
1/4
PLL FOUT
TMR0
CPU
CRC
TMR1
TMR2
TMR3
BPWM1
DAC0/1
DAC2/3
SPI0
TMR4
TMR5
FMC
HIRC
111
010
HCLK
1/(HCLKDIV+1)
PDMA
SRAM
UART0
WDT
PLLFOUT
Manchester
CLK_CLKSEL0[2:0]
/1,/2,/4,/8,/16
HCLK
LIRC
LIRC
11
10
11
10
WDT
WWDT
HCLK
1/2048
1/2048
CLK_CLKSEL1[3:2]
CLK_CLKSEL1[1:0]
CPUCLK
PLLFOUT
LIRC
1
HIRC
HCLK
001
SysTick
1/2
1/2
111
011
0
101
100
011
PCLK0
HIRC
1/(UART0DIV+1)
UART0
SYST_CTRL[2]
CLK_CLKSEL0[5:3]
CLK_CLKSEL1[26:24]
DIV1EN
(CLK_CLKOCTL[5])
PLLFOUT
HIRC
110
PLLFOUT
PCLK1
HIRC
01
101
100
011
010
LIRC
1/(ADCDIV + 1)
ADC
/2(CLK_CLKOCTL[3:0]+1)
0
10
11
CLKO
HIRC
HCLK
1
ADCSEL
(CLKSEL2[21:20])
CLK_CLKSEL1[6:4]
HIRC
LIRC
111
HIRC
111
101
011
010
101
011
010
LIRC
TMR2
TMR3
TMR0
TMR1
TM2/TM3
TM0/TM1
PCLK1
PCLK0
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1[10:8]
CLK_CLKSEL1[14:12]
HIRC
LIRC
HIRC
11
111
101
011
010
PCLK1
10
1/(SPI0_CLKDIV[8:0]+1)
SPI0
TMR4
TMR5
PLLFOUT
01
TM4/TM5
PCLK0
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[14:12]
CLK_CLKSEL2[18:16]
PCLK1
1
0
BPWM 1
PLLFOUT
CLK_CLKSEL2[9]
Figure 6.3-1 Clock Generator Global View Diagram
6.3.2
Clock Generator
The clock generator consists of 2 clock sources, which are listed below:
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48 MHz internal high speed RC oscillator (HIRC)
Programmable PLL output clock frequency (PLLFOUT) – PLL source is selected from 48
MHz internal high speed oscillator (HIRC/4)
HIRCEN (CLK_PWRCTL[2])
PLLFOUT
PLL
/4
Internal 48 MHz
HIRC
Oscillator
(HIRC)
Internal 38.4
LIRC
kHz Oscillator
(LIRC)
Figure 6.3-2 Clock Generator Block Diagram
6.3.3
System Clock and SysTick Clock
The system clock has 2 clock sources generated from clock generator block The clock source switch
depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 6.3-3.
HCLKSEL
(CLK_CLKSEL0[2:0])
CPUCLK
HCLK
HIRC
CPU
AHB
111
010
PLLFOUT
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
PCLK0
PCLK1
APB0
APB1
/1,/2,/4,/8,/16
APB0DIV
CPU in Power Down Mode
(CLK_PCLKDIV[3:0])
APB1DIV
(CLK_PCLKDIV[[6:4])
Figure 6.3-3 System Clock Block Diagram
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The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock (SYST_CTRL[2]).
If using external clock, the SysTick clock (STCLK) has 2 clock sources. The clock source switch depends
on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure
6.3-4.
CPUCLK
1
HIRC
SysTick
1/2
1/2
111
011
0
HCLK
SYST_CTRL[2]
STCLKSEL
CLK_CLKSEL0[5:3]
Figure 6.3-4 SysTick Clock Control Block Diagram
Peripherals Clock
6.3.4
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSELx register description.
6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
The clock that is still kept active is listed below:
Peripherals Clock (when the modules adopt LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider composed by 16 chained divide-by-2 shift
registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to
CLKO function pin. Therefore, there are 16 options of power-of-2 divided clocks with the frequency from
Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state
and stays in low state.
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CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
FREQSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
PLLFOUT
DIV1EN
(CLK_CLKOCTL[5])
1/22
1/23
…...
1/215 1/216
110
100
011
010
1/2
LIRC
HIRC
HCLK
0000
0001
:
16 to 1
MUX
CLKO
0
1
:
1110
1111
CLKOSEL (CLK_CLKSEL1[6:4])
Figure 6.3-5 Clock Output Block Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
This chip is equipped with 32/64 Kbytes on-chip embedded Flash. A User Configuration block is provided
for system initialization. A loader ROM (LDROM) is used for In-System-Programming (ISP) function. A
security protection ROM (SPROM) can conceal user program. This chip also supports In-Application-
Programming (IAP) function. User switches the code executing without the chip reset after the
embedded Flash is updated.
6.4.2
Features
Supports 32/64 Kbytes application ROM (APROM).
Supports 512 bytes page size for 32/64 Kbytes Flash.
Supports 2 Kbytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports 512 bytes security protection ROM (SPROM) to conceal user program.
Supports 12 bytes User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded Flash.
Supports CRC-32 checksum calculation function.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 28 General Purpose I/O pins to be shared with other function pins depending on the
chip configuration. These 28 pins are arranged in 4 ports named as PA, PB, PC, PF. PA has 8 pins on
port. PB has 16 pins on port. PC has 1 pin on port. PF has 3 pins on port. Each of the 28 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
dependent on CIOINI (CONFIG0[10]).
6.5.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
I/O pin can be configured as interrupt source with edge/level setting
Input schmitt trigger function
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Supports independent pull-up control
Enabling the pin interrupt function will also enable the wake-up function
Supports 5V-tolerance function except analog I/O (PA0~PA3, PB0~15, PF0)
GPIO output can be configured to retention when system reset
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This has
the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The
PDMA controller has a total of 7 channels and each channel can perform transfer between memory and
peripherals or between memory and memory.
6.6.2
Features
Supports 7 independently configurable channels
Selectable 2 level of priorities (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size to be byte, half-word, word or no
increment
Supports software and I2C, SPI, UART, ADC, DAC, MANCH and TIMER request
Supports Scatter-Gather mode to implement complex transmission by using descriptor
link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes up to six 32-bit timers, Timer0 ~ Timer5, allowing user to easily implement
a timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
6.7.2
Features
Timer Function Features
Up to six sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit
prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports internal capture triggered while LIRC transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer5 time-out interrupt signal or capture interrupt signal to trigger
ADC, DAC, PDMA, BPWM function
Supports Inter-Timer trigger mode
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer also
supports the function to wake up system from Idle/Power-down mode.
6.8.2
Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if
WDT_CLK = 38.4 kHz (LIRC)
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.9.2
Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.10 Basic PWM Generator and Capture Timer (BPWM)
6.10.1 Overview
This chip provides one BPWM generator (BPWM1). BPWM supports 6 channels of BPWM output or
input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit BPWM counter with 16-
bit comparator. The BPWM counter supports up, down and up-down counter types, all 6 channels share
one counter. BPWM uses the comparator compared with counter to generate events. These events are
used to generate BPWM pulse, interrupt and trigger signal for ADC, DAC to start conversion. For BPWM
output control unit, it supports polarity output, independent pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.10.2 Features
6.10.2.1 BPWM Function Features
Supports maximum clock frequency up to 144 MHz
Supports one BPWM modules and provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter, the module provides 1 BPWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
– BPWM counter matches 0, period value or compared value
Supports trigger DAC
Supports trigger ADC in the following events:
– BPWM counter matches 0, period value or compared value
6.10.2.2 Capture Function Features
Supports up to 6 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.11 UART Interface Controller (UART)
6.11.1 Overview
The chip provides one channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs serial-to-parallel conversion on data received from the peripheral and parallel-to-
serial conversion on data transmitted from the CPU. Each UART controller channel supports ten types
of interrupts. The UART controller supports flow control function. The UART controller also supports
IrDA SIR, RS-485, and Single-wire function modes and auto-baud rate measuring function.
6.11.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 1/1 byte entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS and incoming data wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT[15:8])
Supports Auto-Baud Rate measurement function
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
Support Single-wire function mode
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UART Feature
FIFO
UART0
1 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
-
LIN
RS-485 Function Mode
nCTS Wake-up
Incoming Data Wake-up
√
√
√
Received Data FIFO reached threshold
Wake-up
-
-
RS-485 Address Match (AAD mode)
Wake-up
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
1, 1.5, 2 bit
5, 6, 7, 8 bits
Even / Odd Parity
Stick Bit
√
√
Table 6.11-1 NuMicro® M030G/M031G Series UART Features
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6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one set of SPI controller performing a serial-to-parallel conversion on data received from
a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each
SPI controller can be configured as a master or a slave device and supports the PDMA function to
access the data buffer.
6.12.2 Features
SPI Mode
– Supports one set of SPI controller
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depends on SPI setting of data width
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD
=
1.8~3.6V)
– Supports one data channel half-duplex transfer
– Supports receive-only mode
– Supports PDMA transfer
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6.13 I2C Serial Interface Controller (I2C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and arbitration
that prevents data corruption if two or more masters attempt to control the bus simultaneously.
There are two sets of I2C controllers that support Power-down wake-up function.
6.13.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports two-level buffer function (only supported in slave mode)
Supports setup/hold time programmable
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6.14 CRC Controller (CRC)
6.14.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.14.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.15 CRC Controller (CRC) - Configurable
6.15.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with 8-bits, 16-bits and
32-bits configurable polynomials.
6.15.2 Features
Supports 8-bits, 16-bits and 32-bits configurable polynomials
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.16 Manchester Controller (MANCH)
6.16.1 Overview
The Manchester code is used to transmit a plenty of continuous data in a single bus without synchronous
clock. In each encoded data bit, there is an edge transition in the middle to synchronize the internal
clock. Hence, the clock deviation between receiver and transmitter will not affect the communication.
The Manchester Controller supports encode and decode function with at least 2 modulation signal
formats (Mode 1 and Mode 2). The Manchester Controller also supports programmable format. The
format of the preamble of the data packet and the idle pattern of bus can be defined. The Manchester
Controller supports three 4-level FIFO for transmit, encoded and decoded data. To read/write the data
from/into FIFO, PDMA can be used and combined with other peripherals. The Manchester encoded
edge function can also trigger Timer Controller and interconnect with PDMA and DAC.
6.16.2 Features
Supports encode/decode Manchester code
Supports different modulation signal format
– Mode 1
– Mode 2
– Programmable format
Programmable Idle pattern
Programmable preamble style and its transmitted number
Programmable data size in a frame
Supports configurable Manchester bit rate
Supports selectable deglitch time function
Supports three 4-level FIFO for transmit, encoded and decoded data
Supports PDMA for data receiving/transmitting individually
Supports Manchester encoded edge function to trigger Timer Controller
Supports bit detect error, receive FIFO overflow, receive frame done and transmit frame
done interrupt
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6.17 Analog-to-Digital Converter (ADC)
6.17.1 Overview
The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D converter)
with 16 input channels. The A/D converter supports four operation modes: Single, Burst, Single-cycle
Scan and Continuous Scan mode. The A/D converter can be started by software, external pin (STADC),
timer0~timer5 overflow pulse trigger or BPWM trigger.
6.17.2 Features
Operating voltage: 1.8V~3.6V.
Analog input voltage: 0 ~ AVDD
.
Supports external reference voltage from VREF pin.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels or 8 differential analog input channels.
Maximum ADC peripheral clock frequency is 34 MHz.
Up to 1.4 MSPS sampling rate.
Scan on enabled channels
Threshold voltage detection
Four operation modes:
– Single mode: A/D conversion is performed one time on a specified channel.
– Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
– Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
– Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
– Software Write 1 to ADST bit
– External pin (STADC)
– Timer 0~timer5 overflow pulse trigger
– BPWM trigger
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Supports extend sample time function (0~255 ADC clock).
One internal channel from band-gap voltage (VBG).
One internal channel from internal pull-up/down circuit.
Supports PDMA transfer mode.
Supports Calibration mode.
Supports Floating Detect Function
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Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note2: If the internal channel for band-gap voltage is active, the maximum sampling rate will be 300
KSPS.
Note3: The ADC Clock frequency must be slower than or equal to PCLK.
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6.18 Digital to Analog Converter (DAC)
6.18.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12-or 8-
bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a voltage
output buffer that can be used to reduce output impendence and drive external loads directly without
having to add an external operational amplifier.
6.18.2 Features
Analog output voltage range: 0~AVDD
Supports 12-or 8-bit output mode.
Rail to rail settle time 5us.
.
Supports up to four 12-bit 1 MSPS voltage type DAC.
Reference voltage from internal reference voltage (INT_VREF), VREF pin.
DAC maximum conversion updating rate 1 MSPS.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger, including Timer0~5,BPWM1 trigger to start DAC
conversion.
Supports PDMA mode.
Supports group mode of synchronized update capability for two DACs.
DAC output can be configured to retention when system reset.
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6.19 Peripherals Interconnection
6.19.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous action
between peripherals without needing to involve the CPU. Peripherals interact without CPU saves CPU
resources, reduces power consumption, operates with no software latency and fast responds.
6.19.2 Peripherals Interconnect Matrix table
Destination
Source
ADC
DAC
PWM
Timer
LIRC
BPWM
-
-
-
-
4
-
1
1
2
2
6
Timer
3
5
7
Manchester Codec
Table 6.19-1 Peripherals Interconnect Matrix table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
as close to AVDD as possible
L=30Z
EXT_PWR
AVDD
AVSS
1uF+0.1uF+0.01uF
L=30Z
as close to the
EXT_PWR as possible
10uF+0.1uF
VREF
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
VDD
VSS / EPAD
EXT_VSS
0.1uF*N
as close to VDD as possible
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7.2 Peripheral Application Scheme
DVCC
DVCC
100K
100K
VDD
ICE_DAT
nRESET/ICE_CLK
VSS/EPAD
CS
CLK
MISO
MOSI
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
VDD
SPI Device
SWD
Interface
VSS
DVCC
DVCC
M030G/M031G Series
4.7
K
4.7
K
CLK
DIO
VDD
VSS
I2C_SCL
I2C Device
I2C_SDA
RS 232 Transceiver
PC COM Port
RIN
ROUT
TIN
UART_RXD
UART_TXD
UART
TOUT
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The limiting
values are stress ratings only and cannot be used to functional operation of the device. Exposure to the
absolute maximum ratings may affect device reliability and proper operation is not guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
4.0
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
ΔVDD
|VDD –AVDD
ΔVSS
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance I/O
-
mV
mV
mV
mV
V
|
-
50
-
50
|VSS - AVSS
|
-
50
VSS-0.3
VSS-0.3
5.5
4.0
VIN
Input voltage on any other pin[*2]
V
Note:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance I/O includes PA.0 ~ 3; PB.0 ~ 15; PF.0; nRESET pin. VIN maximum value must be respected to avoid
permanent damage. Refer to Table 8.1-2 for the values of the maximum allowed injected current
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
150
100
20
Unit
[*1]
ΣIDD
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
IIO
mA
100
100
±5
[*3]
IINJ(PIN)
[*3]
ΣIINJ(PIN)
±25
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be exceeded.
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
Table 8.1-2 Current Characteristics
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8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (°C)
θJA = thermal resistance junction-ambient (°C/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
105
125
150
Unit
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
T
J
-40
-65
°C
T
ST
Thermal resistance junction-ambient
24-pin QFN(3x3 mm)
°C/Watt
°C/Watt
-
-
30
28
-
-
[*1]
θJA
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
Note:
1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal Characteristics
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8.1.4
EMC Characteristics
Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of
narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-7000
-1000
-400
Typ
Max
+7000
+1000
+400
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4]
VEFT
-4.4
Fast transient voltage burst
+4.4
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test, the performace cretia class is 4A.
Table 8.1-4 EMC Characteristics
8.1.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
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Pacakge
24-pin QFN(3x3 mm) [*1]
MSL
MSL 3
MSL 3
33-pin QFN(4x4 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-5 Package Moisture Sensitivity (MSL)
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8.1.6
Soldering Profile
Figure 8.1-1 Soldering Profile from J-STD-020C
Porfile Feature
Pb Free Package
Average ramp-up rate (217°C to peak)
Preheat temperature 150°C ~200°C
Temperature maintained above 217°C
Time with 5°C of actual peak temperature
Peak temperature range
3°C/sec. max
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260°C
Ramp-down rate
6°C/sec ax.
8 min. max
Time 25°C to peak temperature
Note:
1.Determined according to J-STD-020C
Table 8.1-6 Soldering Profile
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8.2
General Operating Conditions
(VDD-VSS = 2.7 ~ 3.6V, TA = 25C, HCLK = 48/72 MHz unless otherwise specified.)
Symbol
TA
Parameter
Temperature
Min
-40
-
Typ
Max
105
72
Unit
°C
Test Conditions
-
-
fHCLK
Internal AHB clock frequency
MHz
VDD = 2.7V~3.6V
VDD > BOD detect voltage
while chip power on [*4]
VDD
Operation voltage
2.7
-
3.6
[*1]
AVDD
Analog operation voltage
VDD
VREF <= AVDD - 0.2V,
when VREFEN
(SYS_VREFCTL[0]) =1’b1.
V
VREF
Analog reference voltage
Band-gap voltage
2.048
-
AVDD
VREF <= AVDD
,
when VREFEN
(SYS_VREFCTL[0]) =1’b0.
[*3]
VBG
1.16
20
1.23
-
1.31
-
ADC sampling time when reading
the band-gap voltage
[*3]
TVBG_ADC
S
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
[*2]
IRUSH
-
-
150
200
mA
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
VDD = 2.7 V, TA = 105 °C,
IRUSH = 150 mA for 15 us
[*2]
ERUSH
2.25
3.00
µC
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation.
2.Guaranteed by design, not tested in production
3.Based on characterization, not tested in production unless otherwise specified.
4.BOD brown-out detect function is default enabled and BODVL is set to 0. While chip power up, VDD and AVDD should
higher than BOD detect voltage, otherwise, chip will remain at reset stage.
Table 8.2-1 General Operating Conditions
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8.3
DC Electrical Characteristics
Supply Current Characteristics
8.3.1
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 2.7V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run while(1) code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
72 MHz
14.30
14.65
14.80
15.05
Normal run mode, executed
from Flash, all peripherals
disable
9.80
6.40
4.70
3.50
9.95
6.50
4.75
3.55
10.25
6.80
5.00
3.75
10.50
7.00
5.20
3.95
48 MHz
24 MHz
12 MHz
4 MHz
HIRC, PLL clock
IDD_RUN
mA
72 MHz
22.65
23.05
23.50
23.85
Normal run mode, executed
from Flash, all peripherals
enable
15.45
9.35
6.25
4.15
15.75
9.55
6.35
4.20
16.20
9.85
6.65
4.45
16.45
10.10
6.85
48 MHz
24 MHz
12 MHz
4 MHz
HIRC, PLL clock
4.65
Note:
1. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-1 Current Consumption in Normal Run Mode
May 31, 2021
Page 89 of 118
Rev 1.00
M030G/M031G Series
Typ
Max[*1] [*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
72 MHz
6.90
7.00
7.25
7.50
Idle mode, all peripherals
disable
4.05
3.55
3.25
3.00
4.10
3.60
3.25
3.05
4.35
3.80
3.50
3.25
4.55
4.00
3.60
3.45
48 MHz
24 MHz
12 MHz
4 MHz
HIRC, PLL clock
IDD_IDLE
mA
72 MHz
15.15
15.45
15.90
16.25
Idle mode, all peripherals
enable
9.60
6.30
4.60
3.50
9.75
6.40
4.70
3.55
10.15
6.70
4.95
3.75
10.40
6.95
5.15
3.95
48 MHz
24 MHz
12 MHz
4 MHz
HIRC, PLL clock
Note:
1. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an additional
power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-2 Current Consumption in Idle Mode
May 31, 2021
Page 90 of 118
Rev 1.00
M030G/M031G Series
Typ[*1]
Max[*2][*3]
Unit
Symbol
Test Conditions
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
1730
1820[*4]
2080
2350[*4]
Power-down mode, all peripherals disable
IDD_PD
µA
1730
1825
2085
2355
Power-down mode, UART/Timer/WDT use LIRC
Note:
1. VDD = AVDD = 3.3V, LVR23 enabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. When analog peripheral blocks such as ADC, DAC, Temperature Sensor, INT_VREF, PLL, HIRC are ON, an additional
power consumption should be considered.
4. Based on characterization, tested in production.
Table 8.3-3 Chip Current Consumption in Power-down Mode
May 31, 2021
Page 91 of 118
Rev 1.00
M030G/M031G Series
8.3.2
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[*1]
Peripheral
PDMA
ISP
IDD
Unit
305
0.1
44
CRC
120
270
260
315
320
290
270
75
WDT/WWDT
TMR0
TMR1
TMR2
TMR3
TMR4
TMR5
CLKO
I2C0
uA
60
55
I2C1
665
505
530
SPI0
UART0
ADC[*2]
BPWM1
615
85
[*3]
DAC0
[*3]
DAC1
70
Manch. Codec
675
0.1
[*4]
Temperature Sensor
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the DAC is turned on, add an additional power consumption per DAC for the analog part.
4. Temperature Sensor doesn’t have clock enable bit for this test item. When the Temperature Sensor is turned on, add
an additional power consumption per Temperature Sensor for the analog part.
Table 8.3-4 Peripheral Current Consumption
May 31, 2021
Page 92 of 118
Rev 1.00
M030G/M031G Series
8.3.3
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.3-5 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
Symbol
Parameter
Typ
5
Max
Unit
cycles
µs
tWU_IDLE
Wakeup from IDLE mode
Wakeup from normal power down mode
6
-
[*1][*2]
tWU_NPD
13
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
instruction.
3. Guaranteed by design.
Table 8.3-5 Low-power Mode Wakeup Timings
May 31, 2021
Page 93 of 118
Rev 1.00
M030G/M031G Series
8.3.4
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece I/O
should be avoided during normal product operation. However, the analog compoenent of the MCU is
most likely to be affected by the injection current , but it is not easily clarified when abnormal injection
accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to VDD) to pins
that include analog function which may potentially injection currents.
Negative
injection
Positive
injection
Symbol
Parameter
Unit
Test Condition
-0
-0
0
0
Injected current on nReset pins
Injected current on PA0~PA3 and
PB0~PB15 for analog input function
Injected current by a I/O Pin
mA
IINJ(PIN)
Injected current on any other 5V-
tolerance I/O
-5
+5
Table 8.3-6 I/O Current Injection Characteristics
I/O DC Characteristics
8.3.5
PIN Input Characteristics
Symbol
VIL
Parameter
Input low voltage
Min
Typ
Max
0.3*VDD
VDD
Unit
V
Test Conditions
0
-
VIH
Input high voltage
0.7*VDD
-
-
V
[*1]
VHY
Hysteresis voltage of schmitt input
0.2*VDD
-
V
VSS < VIN < VDD
,
-1
-1
-
-
1
1
Open-drain or input only mode
[*2]
ILK
Input leakage current
Pull up resistor
A
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
32
45
38
60
54
79
VDD = 3.6 V, Input mode
VDD = 2.7 V, input mode
[*1]
RPU
kΩ
Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
Table 8.3-7 I/O Input Characteristics
May 31, 2021
Page 94 of 118
Rev 1.00
M030G/M031G Series
I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 3.3 V
-25.5
-28
-32
µA
VIN=(VDD-0.4) V
Source current for quasi-
bidirectional mode and
high level
VDD = 2.7 V
-18
-22
-24
µA
VIN=(VDD-0.4) V
[*1] [*2]
ISR
VDD = 3.3 V
-8
-6
-10
-8
9
-15
-13
mA
mA
mA
VIN=(VDD-0.4) V
Source current for push-
pull mode and high level
VDD = 2.7 V
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
7.5
14.5
Sink current for push-pull
mode and low level
[*1] [*2]
ISK
VDD = 2.7 V
VIN= 0.4 V
6
-
7.5
5
13
-
mA
pF
[*1]
CIO
I/O pin capacitance
Note:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.3-8 I/O Output Characteristics
nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Min
-
Typ
-
Max Unit
Test Conditions
0.3*VDD
V
V
VIHR
0.7*VDD
32
-
-
38
60
54
79
VDD = 3.6 V
VDD = 2.7 V
[*1]
RRST
Internal nRESET pull up resistor
nRESET input filtered pulse time
KΩ
45
Normal run and Idle mode
32us=3*512*HIRC
-
32
-
-
[*1]
tFR
µS
31.36
32.64
Power down mode
Note:
1. Guaranteed by characterization result, not tested in production.
Table 8.3-9 nRESET Input Characteristics
May 31, 2021
Page 95 of 118
Rev 1.00
M030G/M031G Series
8.4
AC Electrical Characteristics
8.4.1
48 MHz Internal High Speed RC Oscillator (HIRC)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
2.7
3.3
3.6
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
-
48
-
-
MHz
%
TA = 25 °C,
VDD = 3.3V
-0.5
-0.7
-1
+0.5
+0.7
+1
[*1]
fHRC
TA = 0C ~ +70 °C,
-
%
VDD = 3.3V
Frequency drift over temperarure and
volatge
TA = -20C ~ +105 °C,
-
%
VDD = 3.3V
TA = -40C ~ +105 °C,
-2
-
-
500
-
+2
700
20
%
µA
µs
VDD = 2.7 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
TA = -40C ~ +105 °C,
[*2]
TS
-
VDD = 2.7 ~ 3.6V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
Frequency Drift Over Temperarure when VDD = 3.6 V
2.00%
1.50%
1.00%
0.50%
0.00%
-0.50%
Max
Min
-1.00%
-1.50%
-2.00%
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
(a) Test Condition: VDD = 3.6 V, Temp. = -40 ~ 125 °C
May 31, 2021
Page 96 of 118
Rev 1.00
M030G/M031G Series
Frequency Drift Over Temperarure when VDD = 3.3 V
2.00%
1.50%
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
Max
Min
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
(b) Test Condition: VDD = 3.3 V, Temp. = -40 ~ 125 °C
Frequency Drift Over Temperarure when VDD = 2.5 V
2.00%
1.50%
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
Max
Min
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
(c) Test Condition: VDD = 2.5 V, Temp. = -40 ~ 125 °C
Note:
1. The graph is a statistical result using a limited number of samples. For the actual characetristic range, please refer
to Table 8.4-1.
Figure 8.4-1 HIRC vs. Temperature
May 31, 2021
Page 97 of 118
Rev 1.00
M030G/M031G Series
8.4.2
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
VDD
Parameter
Operating voltage
Test Conditions
2.7
-
3.3
3.6
-
V
Oscillator frequnecy
38.4
kHz
TA = 25 °C,
VDD = 3.3V
-
1
-
-
%
%
[*2]
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105 °C
-50
+50
VDD=2.7V~3.6V
Without software calibration
ILRC
TS
Operating current
Stable time
-
-
1
1.1
-
µA
VDD = 3.3V
TA=-40~105 °C
VDD=2.7V~3.6V
100
μs
Note:
1.Guaranteed by characterization, not tested in production.
2.The 38.4 kHz low speed RC oscillator can be calibrated by user.
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
8.4.3
PLL Characteristics
Symbol
Parameter
PLL input clock
Min[*1]
3.2
50
Typ
Max[*1]
32
Unit
MHz
MHz
MHz
MHz
µS
Test Conditions
fPLL_in
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
-
-
-
-
-
PLL multiplier output clock
PLL reference clock
144
8
0.8
200
-
PLL voltage controlled oscillator
PLL locking time
500
500
Jitter[*2]
Cycle-to-cycle Jitter
Power consumption
-
-
200
5
350
9
pS
f
VDD =3.3V @ PLL_OUT = 144
IDD
mA
MHz
Notes:
1.Guaranteed by characterization, not tested in production
2.Guaranteed by design, not tested in production
The fPLL_OUT must meet the restrictions of CPU and peripheral.
Table 8.4-3 PLL characteristics
8.4.4
I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
ns
Test Conditions[*2]
-
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
>= 2.7 V
>= 2.7 V
>= 2.7 V
6
3.5
6
DD
DD
DD
tf(IO)out
Output high (90%) to low level (10%) fall time
Output low (10%) to high level (90%) rise time
-
-
tr(IO)out
ns
May 31, 2021
Page 98 of 118
Rev 1.00
M030G/M031G Series
-
-
CL = 10 pF, V
CL = 30 pF, V
>= 2.7 V
= 3.3 V,
3.5
DD
DD
2.77
f(IO)out = 24 MHz
[*4]
IDIO
I/O dynamic current consumption
mA
CL = 10 pF, V
= 3.3 V,
DD
-
1.19
f(IO)out = 24 MHz
Note:
1.Guaranteed by characterization result, not tested in production.
2.CL is a external capacitive load to simulate PCB and device loading.
3.The I/O dynamic current consumption is defined by 퐼퐷ꢀ푂 = 푉퐷퐷 × 푓 × (퐶ꢀ푂 + 퐶퐿)
ꢀ푂
Table 8.4-4 I/O AC Characteristics
May 31, 2021
Page 99 of 118
Rev 1.00
M030G/M031G Series
8.5
Analog Characteristics
8.5.1
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
POR reset voltage
Min
Typ
20
2
Max
30
Unit
Test Conditions
AVDD = 3.6V
[*1]
IPOR
-
-
-
µA
[*1]
ILVR
3.6
5.5
AVDD = 3.6V
[*1]
IBOD
3
AVDD = 3.6V
VPOR
VLVR
2
2.2
2.3
2.4
V
-
2.16
2.44
LVR reset voltage
-
2.35
2.54
2.65
2.86
VBOD
BOD brown-out detect voltage
2.5
2.7
140
9
BODVL = 0
BODVL = 1
[*1]
TLVR_SU
LVR startup time
LVR respond time
BOD startup time
BOD respond time
VDD rise time rate
-
-
240
12
µs
-
-
-
-
[*1]
TLVR_RE
[*1]
TBOD_SU
-
1000
100
-
1740
165
-
[*1]
TBOD_RE
-
[*1]
RVDDR
10
µs/V
POR/LVR/BOD
Enabled
(BODVL=0)
[*1]
RVDDF
VDD fall time rate
10
80
-
-
-
-
-
-
-
-
POR Enabled
LVR Enabled
470
305
BOD 2.5V Enabled
BOD 2.7V Enabled
Note:
1.Guaranteed by characterization, not tested in production.
2.Design for specified applcaiton.
Table 8.5-1 Reset and Power Control Unit
May 31, 2021
Page 100 of 118
Rev 1.00
M030G/M031G Series
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
May 31, 2021
Page 101 of 118
Rev 1.00
M030G/M031G Series
8.5.2
12-bit SAR ADC
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
TA
Temperature
-40
-
125
°C
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
2.7
2.048
0
3.6
V
V
V
V
-
VDD
DD
-
-
AVDD
VREF
ADC channel input voltage
Common-Mode Input Range
VCM
VREF/2
Full differential input
AVDD = VDD =VREF = 3.3 V
FADC = 24 MHz
[*1]
IADC
Operating current (AVDD + VREF current)
46.8
165
176
24
µA
TCONV = 17 * TADC
NR
Resolution
12
-
Bit
[*1]
FADC
ADC Clock frequency
4
MHz
1/TADC
TSMP
=
TSMP
Sampling Time
Conversion time
1
-
-
256
272
1/FADC (EXTSMPT(ADC_ESMPCTL[7:0])
+ 1 ) * TADC
TCONV
17
1/FADC TCONV = TSMP + 16 * TADC
FSPS = FADC / TCONV
[*1]
FSPS
Sampling Rate
-
-
1.4
MSPS
EXTSMPT(ADC_ESMPCTL[7:0])
= 0
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
-2
-1
-4
-4
-4
-
-
2
2
4
4
4
-
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
bits FADC = 24 MHz
DNL[*1]
-
[*1]
EG
0.5
0.5
0.5
10.4
64.3
[*1]
EO
Offset error
T
[*1]
EA
Absolute Error
ENOB[*1]
SNR[*1]
THD[*1]
Effective number of bits
Signal-to-noise ratio
Total harmonic distortion
AVDD = VDD =VREF = 3.3 V
-
-
Input Frequency = 10 kHz
TA = 25 °C
-
-70.7
-
[*1]
CIN
Internal Capacitance
-
-
-
2.9
0.95
-
-
pF
kΩ
kΩ
[*1]
RIN
Internal Switch Resistance
External input impedance
2
[*1]
REX
50
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
푘
푅퐸푋
=
− 푅ꢀ푁
푓
퐴퐷ꢁ
× 퐶ꢀ푁 × ln(2푁ꢂꢃ
)
May 31, 2021
Page 102 of 118
Rev 1.00
M030G/M031G Series
VDD
EADC_CHx
CEX
RIN
REX
12-bit
Converter
VEX
CIN
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is recommended
to add Schottky diodes (pin to ground and pin to power) to analog pins which may potentially inject
currents.
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain
error from the actual transfer curve.
May 31, 2021
Page 103 of 118
Rev 1.00
M030G/M031G Series
8.5.3
Digital to Analog Converter (DAC)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Min
Typ
Max
Unit
V
Test Condition
AVDD
2.7
3.3
3.6
NR
Resolution
12
-
bit
AVDD
VREF
VREF ≤ AVDD
Reference supply voltage
2.048
V
DNL[*2] Differential non-linearity error
INL[*2] Integral non-linearity error
±1
±2
-
±3
±5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
-
12-bit mode
12-bit mode
-
-
-
-
-
-
-
12-bit mode
DACOUT buffer ON
±10
±5
OE[*2] Offset Error
GE[*2] Gain Error
AE[*2] Absolute Error
12-bit mode
DACOUT buffer OFF
12-bit mode
DACOUT buffer ON
-
-
±10
±5
12-bit mode
DACOUT buffer OFF
12-bit mode
DACOUT buffer ON
-
-
±10
±4
12-bit mode
DACOUT buffer OFF
-
-
Monotonic
10-bit guaranteed
-
AVDD
-
DACOUT buffer ON
0.2
-
-
V
V
0.2
[*1]
VO
Output Voltage
VREF
-
DACOUT buffer OFF
1*LSB
1*LSB
[*2] [*3]
[*2]
RLOAD
Resistive load
DACOUT buffer ON
DACOUT buffer OFF
DACOUT buffer OFF
DACOUT buffer ON
5
-
-
kΩ
kΩ
pF
pF
RO
Output impedance
8
-
20
20
50
-
[*2] [*4]
CLOAD
Capacitive load
-
-
AV
DD = 3.6V, no load, DACOUT
buffer ON, lowest code (0x000)
[*2]
IDAC_AVDD
DAC operating current on AVDD supply
-
250
360
200
6
A
A
μS
AV
DD = 3.6V, no load, DACOUT
buffer ON, middle code (0x800)
VREF =2.5V, no load, worst case code
(0x800)
[*2]
IDAC_VREF
DAC operating current on VREF supply
-
-
Full scale: for a 12-bit input code
transition between the lowest and the
highest input codes when DAC_OUT
reaches final value +/-1 LSB,
CLOAD ≤ 50pF, RLOAD ≥ 5kΩ, Buffer
ON, VREF = 2.5V
[*2]
TB
Settling Time
-
5
May 31, 2021
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M030G/M031G Series
Max. frequency for a correct
MSPS DAC_OUT change from core i to
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
FS
PSRR[*1] Power Supply Rejection Ratio
Update Rate
-
-
1
-
No RLOAD, CLOAD = 50pF
dB
-60
-40
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production.
3. Resistive load between DACOUT and AVSS
.
4. Capacitive load at DACOUT pin.
8.5.4
Internal Voltage Reference for M030G
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
AVDD >= 2.7 V
2.017 2.048
2.079
VREF_INT Internal reference voltage
V
2.463
-
2.5
-
2.538
2
AVDD >= 2.7 V
CL =4.7 uF, VREF initial=0, Preload is
enabled.
mS
mS
µS
-
-
-
-
-
-
15
CL =4.7 uF, VREF initial=3.6, Preload is
enabled.
Ts[*1]
Stable time
480
CL =1 uF, VREF initial=0, Preload is
enabled.
3000
CL =1 uF, VREF initial=3.6, Preload is
enabled.
µS
µA
[*1]
IREF_INT
VREF_INT operating current
-
-
160
-
220
1.5
IREF_LOAD VREF_INT output loading current
Note:
mA
1. Guaranteed by characterization, not tested in production
VREF
1uF
Note: VREF_INT is only supported while package includes VREF pin with external capacitor.
Figure 8.5-2 Typical connection with internal voltage reference
May 31, 2021
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M030G/M031G Series
8.5.5
Internal Voltage Reference for M031G
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
AVDD >= 2.7 V
2.017 2.048
2.079
VREF_INT Internal reference voltage
V
2.463
-
2.5
-
2.538
2
AVDD >= 2.7 V
CL =4.7 uF, VREF initial=0, Preload is
enabled.
mS
mS
µS
-
-
-
-
-
-
15
CL =4.7 uF, VREF initial=3.6, Preload is
enabled.
Ts[*1]
Stable time
900
CL =2.2 uF, VREF initial=0, Preload is
enabled.
6000
CL =2.2 uF, VREF initial=3.6, Preload is
enabled.
µS
µA
[*1]
IREF_INT
VREF_INT operating current
-
-
300
-
360
3
IREF_LOAD VREF_INT output loading current
Note:
mA
1. Guaranteed by characterization, not tested in production
VREF
2.2uF
Note: VREF_INT is only supported while package includes VREF pin with external capacitor.
Figure 8.5-3 Typical connection with internal voltage reference
8.5.6
Temperature Sensor
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
AVDD
Analog supply voltage
2.7
3.3
3.6
V
-40
-
-
105
-
TA
Temperature
°C
ITEMP
Temperature Sensor operating current
200
µA
T = 0 °C to 70 °C
VDD = 3.3 V
[*1]
TTEMP_ERR
Internal Temperature Deviation
-1.6
-
+1.6
°C
May 31, 2021
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M030G/M031G Series
T = -40 °C to 105 °C
VDD = 2.7 V to 3.6 V
-2
-
+2
°C
TR
Temperature Resolution
Conversion Time
-
-
0.0625
84
-
°C
TCONV
100
ms
Note:
1. Guaranteed by characterization, not tested in production
May 31, 2021
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M030G/M031G Series
8.6
Communications Characteristics
SPI Dynamic Characteristics
8.6.1
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
-
Typ
-
Max
24
Unit
FSPICLK
SPI clock frequency
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1/ TSPICLK
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
Data output valid time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
ns
ns
ns
tDH
tV
5
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
Note:
1.
Guaranteed by design.
Table 8.6-1 SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-1 SPI Master Mode Timing Diagram
May 31, 2021
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M030G/M031G Series
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
FSPICLK
1/ TSPICLK
SPI clock frequency
-
-
16
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tCLKH
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
tCLKL
1
tSS
Slave select setup time
Slave select hold time
TSPICLK
+ 2ns
-
-
-
-
ns
ns
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1
tSH
TSPICLK
tDS
tDH
tV
Data input setup time
Data input hold time
Data output valid time
1.5
3.5
-
-
-
-
-
-
ns
ns
ns
17.5
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
Note:
1.
Guaranteed by design.
Table 8.6-2 SPI Slave Mode Characteristics
May 31, 2021
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M030G/M031G Series
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-2 SPI Slave Mode Timing Diagram
May 31, 2021
Page 110 of 118
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M030G/M031G Series
8.6.2
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-3 I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
tBUF
tLOW
tr
tf
SCL
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-3 I2C Timing Diagram
May 31, 2021
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M030G/M031G Series
8.7
Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.8
20
60
7
Max
Unit
V
Test Condition
[1]
VFLA
1.62
1.98
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
-
-
-
-
-
-
-
-
-
-
ms
µs
TA = 25°C
mA
mA
mA
IDD2
Program current
Erase current
8
IDD3
12
NENDUR
Endurance
20,000
-
-
-
cycles[2]
year
TJ = -40°C~125°C
20 kcycle[3] TJ = 85°C
20 kcycle[3] TJ = 105°C
10
2
-
-
TRET
Data retention
year
Note:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Table 8.7-1 Flash DC Electrical Characteristics
May 31, 2021
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M030G/M031G Series
9 PACKAGE DIMENSIONS
9.1 QFN 24L (3x3x0.9 mm Pitch:0.40 mm)
May 31, 2021
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M030G/M031G Series
9.2 QFN 33L (4x4x0.8 mm Pitch:0.40 mm)
May 31, 2021
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Rev 1.00
M030G/M031G Series
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EADC
EBI
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~32 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
May 31, 2021
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M030G/M031G Series
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
May 31, 2021
Page 116 of 118
Rev 1.00
M030G/M031G Series
11 REVISION HISTORY
Date
Revision
Description
2021.5.31
1.00
Initial version.
May 31, 2021
Page 117 of 118
Rev 1.00
M030G/M031G Series
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and
liabilities thus incurred by Nuvoton.
May 31, 2021
Page 118 of 118
Rev 1.00
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