M031BTXD [NUVOTON]
Arm® Cortex®-M 32-bit Microcontroller;
| 型号： | M031BTXD |
| 厂家： | 
NUVOTON |
| 描述： | Arm® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总140页 (文件大小：2933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M031BT
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M031BT Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Aug. 18, 2020
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M031BT
TABLE OF CONTENTS
1 GENERAL DESCRIPTION ..............................................................................9
2 FEATURES....................................................................................................10
2.1 M031BT Features........................................................................................................ 10
3 PARTS INFORMATION.................................................................................16
3.1 Package Type .............................................................................................................. 16
3.2 M031BT Series Selection Guide............................................................................... 17
3.2.1 M031BT Series (M031BTYx)........................................................................................17
3.2.2 Naming Rule ...................................................................................................................18
4 PIN CONFIGURATION ..................................................................................19
4.1 Pin Configuration......................................................................................................... 19
4.1.1 M031BT Series Pin Diagram ........................................................................................19
4.1.2 M031BT Series Multi-function Pin Diagram................................................................20
4.2 Pin Mapping ................................................................................................................. 23
4.3 Pin Function Description ............................................................................................ 25
5 BLOCK DIAGRAM.........................................................................................29
6 FUNCTIONAL DESCRIPTION.......................................................................30
6.1 Arm® Cortex®-M0 Core............................................................................................... 30
6.2 System Manager ......................................................................................................... 32
6.2.1 Overview..........................................................................................................................32
6.2.2 System Reset..................................................................................................................32
6.2.3 System Power Distribution............................................................................................38
6.2.4 Power Modes and Wake-up Sources..........................................................................38
6.2.5 System Memory Map.....................................................................................................41
6.2.6 SRAM Memory Orginization .........................................................................................43
6.2.7 Chip Bus Matrix ..............................................................................................................44
6.2.8 IRC Auto Trim..................................................................................................................44
6.2.9 Register Lock Control ....................................................................................................45
6.2.10UART0_TXD/USCI0_DAT1 modulation with PWM...................................................50
6.2.11System Timer (SysTick).................................................................................................51
6.2.12Nested Vectored Interrupt Controller (NVIC)..............................................................52
6.3 Clock Controller ........................................................................................................... 55
6.3.1 Overview..........................................................................................................................55
6.3.2 Clock Generator..............................................................................................................57
6.3.3 System Clock and SysTick Clock.................................................................................58
6.3.4 Peripherals Clock ...........................................................................................................59
6.3.5 Power-down Mode Clock ..............................................................................................59
6.3.6 Clock Output ...................................................................................................................60
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6.4 Flash Memory Controller (FMC)................................................................................ 61
6.4.1 Overview..........................................................................................................................61
6.4.2 Features...........................................................................................................................61
6.5 General Purpose I/O (GPIO) ..................................................................................... 62
6.5.1 Overview..........................................................................................................................62
6.5.2 Features...........................................................................................................................62
6.6 PDMA Controller (PDMA)........................................................................................... 63
6.6.1 Overview..........................................................................................................................63
6.6.2 Features...........................................................................................................................63
6.7 Timer Controller (TMR)............................................................................................... 64
6.7.1 Overview..........................................................................................................................64
6.7.2 Features...........................................................................................................................64
6.8 Watchdog Timer (WDT).............................................................................................. 65
6.8.1 Overview..........................................................................................................................65
6.8.2 Features...........................................................................................................................65
6.9 Window Watchdog Timer (WWDT)........................................................................... 66
6.9.1 Overview..........................................................................................................................66
6.9.2 Features...........................................................................................................................66
6.10 PWM Generator and Capture Timer (PWM) ..................................................... 67
6.10.1Overview..........................................................................................................................67
6.10.2Features...........................................................................................................................67
6.11 UART Interface Controller (UART) ..................................................................... 69
6.11.1Overview..........................................................................................................................69
6.11.2Features...........................................................................................................................69
6.12 Serial Peripheral Interface (SPI) ......................................................................... 71
6.12.1Overview..........................................................................................................................71
6.12.2Features...........................................................................................................................71
6.13 I2C Serial Interface Controller (I2C)..................................................................... 72
6.13.1Overview..........................................................................................................................72
6.13.2Features...........................................................................................................................72
6.14 USCI - Universal Serial Control Interface Controller (USCI)........................... 73
6.14.1Overview..........................................................................................................................73
6.14.2Features...........................................................................................................................73
6.15 USCI – UART Mode.............................................................................................. 74
6.15.1Overview..........................................................................................................................74
6.15.2Features...........................................................................................................................74
6.16 USCI - SPI Mode................................................................................................... 75
6.16.1Overview..........................................................................................................................75
6.16.2Features...........................................................................................................................75
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6.17 USCI - I2C Mode .................................................................................................... 77
6.17.1Overview..........................................................................................................................77
6.17.2Features...........................................................................................................................77
6.18 CRC Controller (CRC) .......................................................................................... 78
6.18.1Overview..........................................................................................................................78
6.18.2Features...........................................................................................................................78
6.19 Hardware Divider (HDIV)...................................................................................... 79
6.19.1Overview..........................................................................................................................79
6.19.2Features...........................................................................................................................79
6.20 Analog-to-Digital Converter (ADC) ..................................................................... 80
6.20.1Overview..........................................................................................................................80
6.20.2Features...........................................................................................................................80
6.21 Analog Comparator Controller (ACMP).............................................................. 82
6.21.1Overview..........................................................................................................................82
6.21.2Features...........................................................................................................................82
6.22 Radio ....................................................................................................................... 83
6.22.1Overview..........................................................................................................................83
6.22.2Features...........................................................................................................................83
6.23 Peripherals Interconnection ................................................................................. 84
6.23.1Overview..........................................................................................................................84
6.23.2Peripherals Interconnect Matrix Table.........................................................................84
7 APPLICATION CIRCUIT................................................................................85
7.1 Power Supply Scheme (DC-to-DC Mode)............................................................... 85
7.2 Power Supply Scheme (LDO Mode) ........................................................................ 86
7.3 Peripheral Application Scheme (M031BTxE).......................................................... 87
7.4 Peripheral Application Scheme (M031BTxD).......................................................... 88
7.5 PCB Layout Guide....................................................................................................... 89
8 ELECTRICAL CHARACTERISTICS..............................................................91
8.1 Absolute Maximum Ratings....................................................................................... 91
8.1.1 Voltage Characteristics..................................................................................................91
8.1.2 Current Characteristics..................................................................................................91
8.1.3 Thermal Characteristics.................................................................................................93
8.1.4 EMC Characteristics ......................................................................................................94
8.1.5 Package Moisture Sensitivity(MSL).............................................................................95
8.1.6 Soldering Profile .............................................................................................................96
8.2 General Operating Conditions................................................................................... 97
8.3 DC Electrical Characteristics..................................................................................... 98
8.3.1 Supply Current Characteristics.....................................................................................98
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8.3.2 On-Chip Peripheral Current Consumption................................................................101
8.3.3 RF Supply Current Characteristics ............................................................................102
8.3.4 RF Operating Mode Switching Times........................................................................102
8.3.5 Wakeup Time from Low-Power Modes .....................................................................103
8.3.6 I/O Current Injection Characteristics..........................................................................103
8.3.7 I/O DC Characteristics.................................................................................................103
8.4 AC Electrical Characteristics ................................................................................... 106
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC).................................................106
8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................109
8.4.3 32 kHz Internal RF Low Speed RC Oscillator..........................................................112
8.4.4 External 16/32 MHz RF High Speed Crystal characteristics .................................112
8.4.6 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
114
8.4.7 External 4~32 MHz High Speed Clock Input Signal Characteristics ....................116
8.4.8 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
117
8.4.9 External 32.768 kHz Low Speed Clock Input Signal Characteristics ...................118
8.4.10PLL Characteristics ......................................................................................................119
8.4.11I/O AC Characteristics .................................................................................................120
8.5 Analog Characteristics.............................................................................................. 121
8.5.1 LDO ................................................................................................................................121
8.5.2 Reset and Power Control Block Characteristics......................................................121
8.5.3 12-bit SAR ADC............................................................................................................123
8.5.4 Analog Comparator Controller (ACMP).....................................................................126
8.5.5 RF Characteristics........................................................................................................127
8.6 Communications Characteristics ............................................................................ 130
8.6.1 I2C Dynamic Characteristics .......................................................................................130
8.6.2 USCI - SPI Dynamic Characteristics .........................................................................131
8.6.3 USCI-I2C Dynamic Characteristics ............................................................................134
8.7 Flash DC Electrical Characteristics ........................................................................ 135
9 PACKAGE DIMENSIONS............................................................................136
9.1 QFN 48-pin (5X5x0.9 mm Pitch:0.35 mm) ............................................................ 136
10ABBREVIATIONS........................................................................................137
10.1 Abbreviations........................................................................................................ 137
11REVISION HISTORY ...................................................................................139
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LIST OF FIGURES
Figure 4.1-1 M031BT Series QFN 48-pin Diagram........................................................................ 19
Figure 4.1-2 M031BTYE3AN / M031BTYD2AN Multi-function Pin Diagram................................. 20
Figure 5-1 NuMicro® M031BT Block Diagram ............................................................................... 29
Figure 6.1-1 Functional Block Diagram.......................................................................................... 30
Figure 6.2-1 System Reset Sources .............................................................................................. 33
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 35
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 35
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 36
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 37
Figure 6.2-6 NuMicro® M031 Power Distribution Diagram............................................................. 38
Figure 6.2-7 Power Mode State Machine ...................................................................................... 39
Figure 6.2-8 SRAM Memory Organization..................................................................................... 43
Figure 6.2-9 NuMicro® M031 Bus Matrix Diagram......................................................................... 44
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 56
Figure 6.3-2 Clock Generator Block Diagram................................................................................ 57
Figure 6.3-3 System Clock Block Diagram .................................................................................... 58
Figure 6.3-4 HXT Stop Protect Procedure..................................................................................... 59
Figure 6.3-5 SysTick Clock Control Block Diagram....................................................................... 59
Figure 6.3-6 Clock Output Block Diagram ..................................................................................... 60
Figure 6.16-1 SPI Master Mode Application Block Diagram.......................................................... 75
Figure 6.16-2 SPI Slave Mode Application Block Diagram............................................................ 75
Figure 6.17-1 I2C Bus Timing......................................................................................................... 77
Figure 8.1-1 Soldering Profile from J-STD-020C........................................................................... 96
Figure 8.4-1 HIRC vs. Temperature............................................................................................. 108
Figure 8.4-2 LIRC vs. Temperature ............................................................................................. 111
Figure 8.4-3 Typical Crystal Application Circuit ........................................................................... 113
Figure 8.4-4 Typical Crystal Application Circuit ........................................................................... 115
Figure 8.4-5 Typical 32.768 kHz Crystal Application Circuit........................................................ 117
Figure 8.5-1 Power Ramp Up/Down Condition............................................................................ 122
Figure 8.6-1 I2C Timing Diagram ................................................................................................. 130
Figure 8.6-2 USCI-SPI Master Mode Timing Diagram................................................................. 131
Figure 8.6-3 USCI-SPI Slave Mode Timing Diagram................................................................... 133
Figure 8.6-4 USCI-I2C Timing Diagram........................................................................................ 134
Table 10.1-1 List of Abbreviations................................................................................................ 138
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List of Tables
Table 1-1 NuMicro® M031BT Series Key Features Support Table.................................................. 9
Table 4.1-1 M031BTYE3AN / M031BTYD2AN Multi-function Pin Table....................................... 22
Table 6.2-1 Reset Value of Registers............................................................................................ 34
Table 6.2-2 Power Mode Table...................................................................................................... 38
Table 6.2-3 Power Mode Difference Table .................................................................................... 38
Table 6.2-4 Power Mode Difference Table .................................................................................... 39
Table 6.2-5 Clocks in Power Modes .............................................................................................. 40
Table 6.2-6 Condition of Entering Power-down Mode Again......................................................... 41
Table 6.2-7 Address Space Assignments for On-Chip Controllers................................................ 42
Table 6.2-8 Protected Register List ............................................................................................... 49
Table 6.2-9 Exception Model ......................................................................................................... 53
Table 6.2-10 Interrupt Number Table............................................................................................. 54
Table 6.2-11 Vector Figure Format................................................................................................ 54
Table 6.11-1 NuMicro® M031 Series UART Features ................................................................... 70
Table 6.23-1 Peripherals Interconnect Matrix Table...................................................................... 84
Table 8.1-1 Voltage Characteristics............................................................................................... 91
Table 8.1-2 Current Characteristics ............................................................................................... 92
Table 8.1-3 Thermal Characteristics.............................................................................................. 93
Table 8.1-4 EMC Characteristics ................................................................................................... 94
Table 8.1-5 Package Moisture Sensitivity (MSL)........................................................................... 95
Table 8.1-6 Soldering Profile.......................................................................................................... 96
Table 8.2-1 General Operating Conditions .................................................................................... 97
Table 8.3-1 Current Consumption in Normal Run Mode ............................................................... 99
Table 8.3-2 Current Consumption in Idle Mode............................................................................. 99
Table 8.3-3 Chip Current Consumption in Power-down Mode .................................................... 100
Table 8.3-4 Peripheral Current Consumption .............................................................................. 101
Table 8.3-5 RF DC Characteristics .............................................................................................. 102
Table 8.3-6 RF Operating Mode Switching Times....................................................................... 102
Table 8.3-7 Low-power Mode Wakeup Timings .......................................................................... 103
Table 8.3-8 I/O Current Injection Characteristics......................................................................... 103
Table 8.3-9 I/O Input Characteristics ........................................................................................... 104
Table 8.3-10 I/O Output Characteristics ...................................................................................... 105
Table 8.3-11 nRESET Input Characteristics................................................................................ 105
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics.......................... 106
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics .......................... 109
Table 8.4-3 32 kHz Internal RF Low Speed RC Oscillator Characteristics.................................. 112
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Table 8.4-4 External 16 MHz RF High Speed Crystal Characteristics ........................................ 112
Table 8.4-5 External 32 MHz RF High Speed Crystal Characteristics ........................................ 113
Table 8.4-6 External 4~32 MHz High Speed Crystal (HXT) Oscillator ........................................ 114
Table 8.4-7 External 4~32 MHz High Speed Crystal Characteristics .......................................... 115
Table 8.4-8 External 4~32 MHz High Speed Clock Input Signal ................................................. 116
Table 8.4-9 External 32.768 kHz Low Speed Crystal (LXT) Oscillator........................................ 117
Table 8.4-10 External 32.768 kHz Low Speed Crystal Characteristics ....................................... 117
Table 8.4-11 External 32.768 kHz Low Speed Clock Input Signal .............................................. 118
Table 8.4-12 PLL Characteristics................................................................................................. 119
Table 8.4-13 I/O AC Characteristics ............................................................................................ 120
Table 8.5-1 Reset and Power Control Unit .................................................................................. 121
Table 8.5-2 ACMP Characteristics............................................................................................... 126
Table 8.5-3 RF Transmitter Characteristics................................................................................. 127
Table 8.5-4 RF Receiver Characteristics..................................................................................... 129
Table 8.6-1 I2C Characteristics .................................................................................................... 130
Table 8.6-2 USCI-SPI Master Mode Characteristics ................................................................... 131
Table 8.6-3 USCI-SPI Slave Mode Characteristics ..................................................................... 132
Table 8.6-4 USCI-I2C Characteristics .......................................................................................... 134
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1
GENERAL DESCRIPTION
The M031BT series microcontroller (MCU) is based on Arm® Cortex® -M0 core with built-in Bluetooth
Low Energy 5.0 (BLE 5.0) with rich peripherals and analog functions for applications that need
wireless connectivity with multiple control functions. The M031BT series is compliant with the BLE 5.0
standard supporting data rates up to 2 Mbps, offering 2.4 GHz proprietary stacks to achieve more
possibility for wireless connectivity and Over-the-Air (OTA) for firmware upgrade. The M031BT series
solution allows those microcontroller applications to be the Internet of Things (IoT) devices with
wireless connectivity.
The M031BT series runs up to 48 MHz for efficient computation within -40°C ~ 85°C, operating from
1.8 ~ 3.6 V supply voltages, and supports 5V I/O tolerant. There are 2 memory configurations of
Flash/SRAM by 64 KB/8 KB and 128 KB/16 KB respectively, and a 512 bytes security protection ROM
(SPROM) provides a secure code execution area to protect the intellectual property of developers.
The M031BT series provides a solution for applications that need the connection with enhanced 2
MSPS fast conversion rate 12-bit ADC, 2 comparators and up-to 12-ch 96 MHz PWM control. The
M031BT supports a fast and precise data conversion for the voltage, current, and sensor data, then
fast response control to the external device. Additionally, the M031BT series also provides plenty of
peripherals including a Universal Serial Control Interface (USCI) that can be set as UART/SPI/I2C
flexibly, 2 sets of I2C, 3 sets of UART, and 1-wire UART interface for data communication between
master and slave devices.
For the development, Nuvoton provides the NuMaker evaluation board and Nuvoton Nu-Link
debugger. The 3rd Party IDE such as Keil MDK, IAR EWARM, Eclipse IDE with GNU GCC compilers
are also supported.
The M031BT series supports small form factor package QFN 48-pin (5 mm x 5 mm) that makes the
PCB design to be compact size.
Product Line
UART
I2C
USCI
Timer
PWM
PDMA
CRC
HDIV
ACMP
ADC
M031BT
3
2
1
4
12
5
√
√
2
16
Table 1-1 NuMicro® M031BT Series Key Features Support Table
The NuMicro® M031BT series is suitable for a wide range of applications such as:
IoT edge device
Personal healthcare device with wireless connectivity
Smart home appliances with remote control
Dual mode gaming keyboard/ mouse
Assess tracking devices
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2 FEATURES
2.1 M031BT Features
Core and System
Arm® Cortex® -M0 processor, running up to 48 MHz
– 48 MHz at 1.8V-3.6V
Built-in Nested Vectored Interrupt Controller (NVIC)
24-bit system tick timer
Arm® Cortex® -M0
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Two-level BOD with brown-out interrupt and reset option.
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
(2.5V/2.0V)
LVR with 1.7V threshold voltage level.
96-bit Unique ID (UID).
Security
128-bit Unique Customer ID (UCID).
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit H/W Divider(HDIV)
32-bit quotient and 32-bit remainder outputs (16-bit remainder with
sign extends to 32-bit)
Memories
Up to 128 KB on-chip Application ROM (APROM).
Up to 4 KB on-chip Flash for user-defined loader (LDROM)
512 bytes execution-only Security Protection ROM (SPROM)
All on-chip Flash support 512 bytes page erase
Flash
Fast Flash programming verification with CRC-32 checksum
calculation
On-chip Flash programming with In-Chip Programming (ICP), In-
System Programming (ISP) and In-Application Programming (IAP)
capabilities
2-wired ICP Flash updating through SWD/ICE interface
Up to 16 KB on-chip SRAM
Byte-, half-word- and word-access
PDMA operation
SRAM
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
Programmable initial value and seed value
Cyclic Redundancy
Calculation (CRC)
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Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
Up to 5 independent and configurable channels for automatic data
transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using Scatter-
Gather Transfer mode
Peripheral DMA (PDMA)
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
4~32 MHz High-speed eXternal crystal oscillator (HXT) for precise
timing operation
32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC
function and low-power system operation
External Clock Source
16/32 MHz eXternal crystal oscillator(RF_XTAL) for RF transceiver
Supports clock failure detection for external crystal oscillators and
exception generatation (NMI)
48 MHz High-speed Internal RC oscillator (HIRC).
38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wakeup operation
32 kHz low-power on-chip RC oscillator for RF transceiver with
Internal Clock Source
deviation less than ± 500 ppm
Up to 96 MHz on-chip PLL, sourced from HIRC or HXT, allows CPU
operation up to the maximim CPU frequency without the need for a
high-frequency crystal
Timers
Up to 4 sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation
modes
32-bit Timer
Supports event counting function to count the event from external
pins
Supports external capture pin for interval measurement and
resetting 24-bit up counter
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Supports chip wake-up function, if a timer interrupt signal is
generated
Up to two PWM modules, each module provides three 16-bit
counter and 6 output channels.
Up to 12 independent input capture channels with 16-bit resolution
counter
Supports dead time with maximum divided 12-bit prescale
Up, down or up-down PWM counter type
PWM (PWM)
Supports complementary mode for 3 complementary paired PWM
output channels
Counter synchronous start function
Brake function with auto recovery mechanism
Mask function and tri-state output for each PWM channel
Able to trigger ADC to start conversion
20-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection),
HCLK/2048 and LXT with 9 selectable time-out period
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Watchdog
Supports four WDT reset delay periods, including 1026, 130, 18 or
3 WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset.
Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale
Window Watchdog
Suspended in Idle/Power-down mode
Analog Interfaces
Analog input voltage range: 0 ~ AVDD
One 12-bit, 2 MSPS SAR ADC with up to 16 single-ended input
channels or 8 differential input pairs; 10-bit accuracy is guaranteed.
Internal channels for band-gap VBG input.
Supports calibration capability.
Four operation modes: Single mode, Burst mode, Single-cycle Scan
mode and Continuous Scan mode.
ADC
Analog-to-Digital conversion can be triggered by software enable
(ADST), external pin (STADC), Timer 0~3 overflow pulse trigger,
PWM trigger.
Each conversion result is held in data register of each channel with
valid and overrun indicators.
Supports conversion result monitor by compare mode function.
Configurable ADC external sampling time.
PDMA operation.
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Two Analog Comparators
Supports three multiplexed I/O pins at positive input
Supports I/O pins, band-gap, and 16-level Voltage divider from
AVDD at negative input
Analog Comparator
(ACMP)
Supports wake up from Power-down by interrupt
Supports triggers for brake events and cycle-by-cycle control for
PWM
Supports window compare mode and window latch mode
Supports hysteresis function
Modem with Integrated RF Radio for 2.4 GHz Bluetooth
communication link
Compliant with Bluetooth 5 Low Energy Specification
Supports proprietary 2.4 GHz protocols
High TX power with low current (+8 dBm, 8 mA)
Rx Sensitivity: -94 dBm at 1 Mbps
Radio
Immune to interference (image rejection, -25dBm)
Data rate: 1Mbps and 2Mbps
Integrated security: CRC, AES-128, AES-CCM for real-time
processing of the data stream
RSSI read-out
Two power supply modes (DC-DC converter and LDO regulator) for
RF transceiver
Communication Interfaces
Low-power UARTs with up to 4.8 MHz baud rate.
Auto-Baud Rate measurement and baud rate compensation
function.
Supports low power UART (LPUART): baud rate clock from LXT
(32.768 kHz) with 9600bps in Power-down mode even system clock
is stopped.
16-byte FIFOs with programmable level trigger
Auto flow control (nCTS and nRTS)
Low-power UART
Supports IrDA (SIR) function
Supports RS-485 9-bit mode and direction control
Supports nCTS, incoming data, Received Data FIFO reached
threshold and RS-485 Address Match (AAD mode) wake-up
function in idle mode.
Supports hardware or software enables to program nRTS pin to
control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
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Supports break error, frame error, parity error and receive/transmit
FIFO overflow detection function
PDMA operation.
Supports Single-wire function mode.
Two sets of I2C devices with Master/Slave mode.
Supports Standard mode (100 kbps), Fast mode (400 kbps), Fast
mode plus (1 Mbps)
Supports 7 bits mode
I2C
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with
mask option)
Supports multi-address power-down wake-up function
PDMA operation
Dedicated SPI controller for RF transceiver.
Up to 16 MHz at 1.8V~3.6V system voltage.
Configurable bit length of a transfer word from 8 to 32-bit.
Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and
receive FIFO buffers.
MSB first or LSB first transfer sequence.
Byte reorder function.
SPI
Supports Byte or Word Suspend mode.
Supports one data channel half-duplex transfer.
Supports receive-only mode.
PDMA operation.
One set of USCI, configured as UART, SPI or I2C function.
Supports single byte TX and RX buffer mode
UART
Supports one transmit buffer and two receive buffers for data
payload.
9-bit Data Transfer.
Baud rate detection by built-in capture event of baud rate generator.
Universal Serial Control
Interface (USCI)
Supports wake-up function.
PDMA operation.
SPI
Supports Master or Slave mode operation.
Supports one transmit buffer and two receive buffer for data
payload.
Configurable bit length of a transfer word from 4 to 16-bit.
Supports MSB first or LSB first transfer sequence.
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Supports Word Suspend function.
Supports 3-wire, no slave select signal, bi-direction interface.
PDMA operation.
Supports one data channel half-duplex transfer.
I2C
Supports master and slave device capability.
Supports one transmit buffer and two receive buffer for data
payload.
Communication in standard mode (100 kbps), fast mode (up to 400
kbps), and Fast mode plus (1 Mbps).
Supports 7-bit mode (10-bit mode not supported).
Supports 10-bit bus time out capability.
Supports bus monitor mode.
Supports power-down wake-up by data toggle or address match.
Supports multiple address recognition.
Supports device address flag.
Programmable setup/hold time.
Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode.
Configured as interrupt source with edge/level trigger setting.
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional
I/O mode.
GPIO
Supports 5V-tolerance function except analog IO (PB.0~PB.15,
PF.2~PF.5).
Enabling the pin interrupt function will also enable the wake-up
function.
Input schmitt trigger function.
Aug. 18, 2020
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M031BT
3
PARTS INFORMATION
3.1 Package Type
Part No.
QFN48
M031BTxD
M031BTxE
M031BTYD2AN
M031BTYE3AN
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M031BT
3.2 M031BT Series Selection Guide
3.2.1 M031BT Series (M031BTYx)
M031BT
Part Number
YD2AN
YE3AN
128
16
Flash (KB)
SRAM (KB)
64
8
LDROM (KB)
SPROM(Bytes)
2
4
512
System Frequency (MHz)
48
PLL ( MHz)
96
I/O
32-bit Timer
USCI
29
4
1
UART
3
I²C
2
PWM
12
PDMA
5
CRC
√
HDIV
√
2
Analog Comparator
12-bit SAR ADC
Package
16
QFN48
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M031BT
3.2.2
Naming Rule
31BT
M0
Core
Y
E
3
A
N
Line
Package
Flash
SRAM
Reserve
Temperature
N:-40°C ~ 85°C
Cortex®-M0 31BT: RF
Y: QFN48
(5x5 mm)
D: 64 KB
2: 8 KB
3: 16 KB
E: 128 KB
Aug. 18, 2020
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4 PIN CONFIGURATION
Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfig. The
NuTool - PinConfigure contains all Nuvoton NuMicro® Family chip series with all part number, and
helps users configure GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1
M031BT Series Pin Diagram
4.1.1.1 M031BT Series QFN 48-Pin Diagram
Corresponding Part Number: M031BTYE3AN, M031BTYD2AN
24
23
22
21
20
19
18
17
16
15
14
13
12
11
35
PF.15
PB.15
36
PA.0
PB.14
Top transparent view
37
PA.1
PB.13
38
PA.2
PB.12
39
VSS
AVDD
40
PA.3
AVSS
QFN48
41
RF_BUCK_OUT
RF_BUCK_FB
RF_AVDD1V2
RF_XT_OUT
RF_XT_IN
PF.2
PB.11
42
PB.10
43
PB.9
4340
PB.8
45
PB.7
49 VSS
46
PB.6
47
PF.3
PB.5
48
PF.4
PB.4
Figure 4.1-1 M031BT Series QFN 48-pin Diagram
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4.1.2
M031BT Series Multi-function Pin Diagram
4.1.2.1 M031BT Series QFN 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M031BTYE3AN, M031BTYD2AN
35
36
37
38
39
4206
41
42
4239
44
4351
4362
47
48
24
23
22
21
20
19
18
17
16
15
14
13
12
11
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / UART1_RXD / I2C1_SDA / PWM0_CH3
VSS
Top transparent view
AVSS
PA.3 / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
RF_BUCK_OUT
QFN48
I2C1_SCL / UART0_nCTS / ADC0_CH11 / PB.11
I2C1_SDA / UART0_nRTS / ADC0_CH10 / PB.10
RF_BUCK_FB
UART1_nCTS / UART0_TXD / ADC0_CH9 / PB.9
RF_AVDD1V2
UART1_nRTS / UART0_RXD / ADC0_CH8 / PB.8
RF_XTAL_OUT
ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7
ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_N / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP1_P1 / ADC0_CH4 / PB.4
RF_XTAL_IN
49 VSS
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
Figure 4.1-2 M031BTYE3AN / M031BTYD2AN Multi-function Pin Diagram
Pin M031BTYE3AN / M031BTYD2AN Pin Function
1
2
3
4
5
6
7
8
9
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
RF_AVDD1V2
VSS
RF_IO
VSS
RF_VDDPA
Aug. 18, 2020
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Pin M031BTYE3AN / M031BTYD2AN Pin Function
10 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
11 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
14 RF_XTAL_IN
15 RF_XTAL_OUT
16 RF_AVDD1V2
17 RF_BUCK_FB
18 RF_BUCK_OUT
19 PA.3 / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
20 VSS
21 PA.2 / UART1_RXD / I2C1_SDA / PWM0_CH3
22 PA.1 / UART0_TXD / UART1_nCTS / PWM0_CH4
23 PA.0 / UART0_RXD / UART1_nRTS / PWM0_CH5
24 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
25 nRESET
26 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
27 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
28 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
29 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
30 RF_VDD
31 RF_CLKO
32 VSS
33 LDO_CAP
34 VDD
35 PB.15 / ADC0_CH15 / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
36 PB.14 / ADC0_CH14 / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
37 PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / USCI0_DAT0 / UART0_TXD / PWM1_CH2 / TM2_EXT
38 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
39 AVDD
40 AVSS
41 PB.11 / ADC0_CH11 / UART0_nCTS / I2C1_SCL
42 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA
43 PB.9 / ADC0_CH9 / UART0_TXD / UART1_nCTS
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Pin M031BTYE3AN / M031BTYD2AN Pin Function
44 PB.8 / ADC0_CH8 / UART0_RXD / UART1_nRTS
45 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
46 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
47 PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
48 PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
Table 4.1-1 M031BTYE3AN / M031BTYD2AN Multi-function Pin Table
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Page 22 of 140
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M031BT
4.2 Pin Mapping
Different part number with the same package might have different function. Please refer to the
selection guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfig.
Corresponding Part Number: M031BTxD, M031BTxE series.
M031BT series
Pin Name
PB.3
48 Pin
1
PB.2
2
PB.1
3
PB.0
4
RF_AVDD1V2
VSS
5
6
RF_IO
VSS
7
8
RF_VDDPA
PF.5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PF.4
PF.3
PF.2
RF_XTAL_IN
RF_XTAL_OUT
RF_AVDD1V2
RF_BUCK_FB
RF_BUCK_OUT
PA.3
VSS
PA.2
PA.1
PA.0
PF.15
nRESET
PF.0
PF.1
PC.1
PC.0
Aug. 18, 2020
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M031BT
M031BT series
Pin Name
RF_VDD
RF_CLKO
VSS
48 Pin
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
LDO_CAP
VDD
PB.15
PB.14
PB.13
PB.12
AVDD
AVSS
PB.11
PB.10
PB.9
PB.8
PB.7
PB.6
PB.5
PB.4
VSS
Aug. 18, 2020
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M031BT
4.3 Pin Function Description
Group
Pin Name
Type Description
ACMP0_N
A
O
A
A
A
A
I
Analog comparator 0 negative input pin.
ACMP0_O
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
Analog comparator 0 output pin.
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
Analog comparator 1 output pin.
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
ADC0 channel 0 analog input.
ACMP0
A
O
A
A
A
A
I
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
ADC0_CH12
ADC0_CH13
ADC0_CH14
ADC0_CH15
ADC0_ST
ACMP1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I
ADC0 channel 1 analog input.
ADC0 channel 2 analog input.
ADC0 channel 3 analog input.
ADC0 channel 4 analog input.
ADC0 channel 5 analog input.
ADC0 channel 6 analog input.
ADC0 channel 7 analog input.
ADC0
ADC0 channel 8 analog input.
ADC0 channel 9 analog input.
ADC0 channel 10 analog input.
ADC0 channel 11 analog input.
ADC0 channel 12 analog input.
ADC0 channel 13 analog input.
ADC0 channel 14 analog input.
ADC0 channel 15 analog input.
ADC0 external trigger input.
CLKO
GPIO
CLKO
O
Clock Out
PA.x~PH.x
I/O General purpose digital I/O pin.
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M031BT
Group
Pin Name
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
Type Description
I/O I2C0 clock pin.
I2C0
I/O I2C0 data input/output pin.
I/O I2C1 clock pin.
I2C1
I/O I2C1 data input/output pin.
Serial wired debugger clock pin.
ICE_CLK
ICE_DAT
I
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
Serial wired debugger data pin.
O
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
ICE
External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial
state.
nRESET
I
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET
pin.
INT0
INT1
INT2
INT3
INT4
INT5
INT0
I
I
I
I
I
I
I
I
External interrupt 0 input pin.
External interrupt 1 input pin.
External interrupt 2 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
PWM0 Brake 0 input pin.
INT1
INT2
INT3
INT4
INT5
PWM0_BRAKE0
PWM0_BRAKE1
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM1_BRAKE0
PWM1_BRAKE1
PWM1_CH0
PWM1_CH1
PWM1_CH2
PWM1_CH3
PWM1_CH4
PWM1_CH5
VDD
PWM0 Brake 1 input pin.
I/O PWM0 channel 0 output/capture input.
I/O PWM0 channel 1 output/capture input.
I/O PWM0 channel 2 output/capture input.
I/O PWM0 channel 3 output/capture input.
I/O PWM0 channel 4 output/capture input.
I/O PWM0 channel 5 output/capture input.
PWM0
I
I
PWM1 Brake 0 input pin.
PWM1 Brake 1 input pin.
I/O PWM1 channel 0 output/capture input.
I/O PWM1 channel 1 output/capture input.
I/O PWM1 channel 2 output/capture input.
I/O PWM1 channel 3 output/capture input.
I/O PWM1 channel 4 output/capture input.
I/O PWM1 channel 5 output/capture input.
PWM1
P
P
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
Ground pin for digital circuit.
Power
VSS
Aug. 18, 2020
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M031BT
Group
Pin Name
AVDD
Type Description
P
P
Power supply for internal analog circuit.
AVSS
Ground pin for analog circuit.
LDO output pin.
Note: This pin needs to be connected with a 1uF capacitor.
LDO_CAP
A
RF power supply
Note: This pin needs to be connected with a 1uF capacitor.
Power supply for RF signal power amplifier
Note: This pin needs to be connected with a 0.1uF capacitor.
RF Transceiver 1.2 V power supply pin
Note: This pin needs to be connected with a 1uF capacitor.
RF input/output signal
Note: The impedance of this RF transmission line needs to be 50 Ω.
RF_VDD
P
P
P
A
RF_VDDPA
RF_AVDD1V2
RF_IO
RF
RF_BUCK_OUT
RF_BUCK_FB
RF_CLKO
P
P
O
RF DC-DC converter 1.2 V output
RF DC-DC converter feedback
RF 16 MHz clock out.
RF_XTAL_IN
RF_XTAL_OUT
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SS
I
RF high speed crystal input pin.
RF high speed crystal output pin.
O
I/O SPI0 serial clock pin.
I/O SPI0 MISO (Master In, Slave Out) pin.
I/O SPI0 MOSI (Master Out, Slave In) pin.
I/O SPI0 slave select pin.
SPI0
TM0
I/O Timer0 event counter input/toggle output pin.
I/O Timer0 external capture input/toggle output pin.
I/O Timer1 event counter input/toggle output pin.
I/O Timer1 external capture input/toggle output pin.
I/O Timer2 event counter input/toggle output pin.
I/O Timer2 external capture input/toggle output pin.
I/O Timer3 event counter input/toggle output pin.
I/O Timer3 external capture input/toggle output pin.
TM0
TM1
TM2
TM3
TM0_EXT
TM1
TM1_EXT
TM2
TM2_EXT
TM3
TM3_EXT
UART0_RXD
UART0_TXD
UART0_nCTS
UART0_nRTS
UART1_RXD
UART1_TXD
UART1_nCTS
UART1_nRTS
UART2_RXD
UART2_TXD
I
O
I
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART0 clear to Send input pin.
UART0 request to Send output pin.
UART1 data receiver input pin.
UART1 data transmitter output pin.
UART1 clear to Send input pin.
UART1 request to Send output pin.
UART2 data receiver input pin.
UART2 data transmitter output pin.
UART0
O
I
O
I
UART1
UART2
O
I
O
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M031BT
Group
Pin Name
Type Description
UART2_nCTS
UART2_nRTS
USCI0_CLK
USCI0_CTL1
USCI0_DAT0
USCI0_DAT1
X32_IN
I
UART2 clear to Send input pin.
UART2 request to Send output pin.
O
I/O USCI0 clock pin.
I/O USCI0 control 1 pin.
I/O USCI0 data 0 pin.
I/O USCI0 data 1 pin.
USCI0
I
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
External high speed crystal input pin.
External high speed crystal output pin.
X32
XT1
X32_OUT
O
I
XT1_IN
XT1_OUT
O
Aug. 18, 2020
Page 28 of 140
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M031BT
5
BLOCK DIAGRAM
Figure 5-1 NuMicro® M031BT Block Diagram
Aug. 18, 2020
Page 29 of 140
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M031BT
6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an A
MbytesA AHB-Lite interface and includes an NVIC component. It also has optional hardware
debug functionality. The processor can execute Thumb code and is compatible with other
Cortex® -M profile processor. The profile supports two modes -Thread mode and Handler mode.
Handler mode is entered as a result of an exception. An exception return can only be issued in
Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception
return. Figure 6.1-1 shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
–
–
–
–
–
–
–
Arm® 6-M Thumb® instruction set
Thumb-2 technology
Arm® 6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
–
–
C Application Binary Interface compliant exception model. This is the Armv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
Aug. 18, 2020
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M031BT
NVIC:
–
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
–
–
Supports for both level-sensitive and pulse-sensitive interrupt lines
–
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support:
–
–
–
–
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
–
Single 32-bit A MbytesA-3 AHB-Lite system interface that provides simple
integration to all system peripherals and memory
–
Single 32-bit slave port that supports the DAP (Debug Access Port)
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M031BT
6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
–
–
–
–
–
–
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
CPU Lockup Reset
Software Reset Sources
–
–
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM
by writing 1 to SYSRESETREQ (AIRCR[2])
–
–
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
nRESET glitch filter time 32us
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M031BT
Glitch Filter
32 us
nRESET
~50k ohm
@3.3v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there are
small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
POR
0x001
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[16])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
0x1
(CLK_APBCLK0[0])
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HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
-
Reload
base
CONFIG0
-
-
-
on base on base on base on
on
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
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6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Table 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is
ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3
shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
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AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
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6.2.3
System Power Distribution
In this chip, power distribution is divided into three segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8V power for digital operation and I/O pins.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be
located close to the corresponding pin. Figure 6.2-6 shows the NuMicro® M031 power distribution.
Figure 6.2-6 NuMicro® M031 Power Distribution Diagram
6.2.4
Power Modes and Wake-up Sources
The M031 series has power manager unit to support several operating modes for saving power. Table
6.2-2 lists all power mode in the M031 series.
Mode
CPU Operating Maximum
Speed( MHz)
LDO_CAP(V)
Clock Disable
Normal mode
Idle mode
48
1.8
1.8
1.8
All clocks are disabled by control register.
Only CPU clock is disabled.
CPU enter Sleep mode
Power-down mode
CPU enters Power-down
mode
Most clocks are disabled except LIRC/LXT,
and only WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected
as LIRC/LXT.
Table 6.2-2 Power Mode Table
There are different power mode entry settings and leaving condition for each power mode. Table 6.2-3
shows the entry setting for each power mode. When chip power-on, chip is running in normal mode.
User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT:[7]) and execute
WFI instruction.
Register/Instruction
Mode
SLEEPDEEP
(SCR[2])
PDEN
CPU Run WFI Instruction
(CLK_PWRCTL[7])
Normal mode
0
0
0
0
NO
Idle mode
YES
(CPU enter Sleep mode)
Power-down mode
1
1
YES
(CPU enters Deep Sleep
mode)
Table 6.2-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
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Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD,
GPIO, EINT, USCI, , and
ACMP
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-4 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC , HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[6]) = 1
3. CPU executes WFI
Wake-up events
occur
Idle Mode
CPU Clock OFF
HXT, HIRC, LXT , LIRC , HCLK, PCLK ON
Flash Halt
Power-down Mode
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.2-7 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode.
2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If UART clock source is selected as LXT and LXT is on.
Normal Mode
Idle Mode
ON
Power-Down Mode
HXT (4~32 MHz XTL)
HIRC48 (48 MHz OSC)
LXT (32768 Hz XTL)
LIRC (38.4 kHz OSC)
PLL
ON
ON
Halt
Halt
ON
ON
ON
ON/OFF1
ON/OFF2
Halt
ON
ON
ON/OFF
ON
ON/OFF
ON
LDO
ON
CPU
ON
Halt
Halt
HCLK/PCLK
SRAM retention
FLASH
ON
ON
Halt
ON
ON
ON
ON
ON
Halt
GPIO
ON
ON
Halt
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PDMA
TIMER
PWM
WDT
WWDT
UART
USCI
I2C
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON/OFF3
Halt
ON/OFF4
Halt
ON/OFF6
Halt
Halt
SPI
Halt
ADC
Halt
ACMP
Halt
Table 6.2-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, USCI, BOD, GPIO, and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-5 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear (SYS_BODCTL[4]).
INT
External Interrupt
GPIO Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
TIMER
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
Timer Interrupt
WDT
WDT Interrupt
nCTS wake-up
RX Data wake-up
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
Received FIFO Threshold
Wake-up
After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]).
UART0/1
RS-485 AAD Mode Wake-up After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]).
Received FIFO Threshold
After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]).
Time-out Wake-up
nCTS wake-up
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
UART2
I2C
RX Data wake-up
Address match or GC mode
match wake-up.
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
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ACMP
Comparator Power-Down After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1
Wake-Up Interrupt
(ACMP_STATUS[9]).
Table 6.2-6 Condition of Entering Power-down Mode Again
6.2.5
System Memory Map
The NuMicro® M031 series provides 4G-byte addressing space. The memory locations assigned to
each on-chip controllers are shown inTable 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The M031 series
only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
SRAM0_BA
EXTMEM_BA
FLASH Memory Space (192 Kbytes)
SRAM Memory Space (16 Kbytes)
External Memory Space (256 Mbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4001_4000 – 0x4001_7FFF
0x4003_1000 – 0x4003_1FFF
SYS_BA
CLK_BA
NMI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO_BA
PDMA_BA
FMC_BA
HDIV_BA
CRC_BA
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
Hardware Divider Register
CRC Generator Registers
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4006_1000 – 0x4006_0FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4008_0000 – 0x4008_0FFF
WDT_BA
Watchdog Timer Control Registers
Analog-Digital-Converter (ADC) Control Registers
Analog Comparator 0/ 1 Control Registers
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
PWM0 Control Registers
ADC_BA
ACMP01_BA
TMR01_BA
TMR23_BA
PWM0_BA
PWM1_BA
SPI0_BA
PWM1 Control Registers
SPI0 Control Registers
UART0_BA
UART1_BA
UART2_BA
I2C0_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
I2C0 Control Registers
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0x4008_1000 – 0x4008_1FFF
0x400D_0000 – 0x400D_0FFF
I2C1_BA
I2C1 Control Registers
USCI0_BA
USCI0 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Controllers
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6.2.6
SRAM Memory Orginization
The M031 supports embedded SRAM with total 16 Kbytes size
Supports total 16 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
Table 6.2-10 shows the SRAM organization of M031. The address between 0x2000_4000 to
0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses.
0x3FFF_FFFF
Reserved
Reserved
Reserved
Reserved
0x2000_4000
0x2000_2000
0x2000_1000
16K byte
SRAM bank0
8K byte
SRAM bank0
4K byte
SRAM bank0
0x2000_0800
2K byte
SRAM bank0
0x2000_0000
4K byte device
16K byte device
8K byte device
2K byte device
Figure 6.2-8 SRAM Memory Organization
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6.2.7
Chip Bus Matrix
The M031 series supports Bus Matrix to manage the access arbitration between masters. The access
arbitration use round-robin algorithm as the bus priority.
M1
PDMA
M0
Cortex® -M0
S0
S1
S2
APB0
S3
APB1
S4
S5
EBI
AHB
(ctrl)
FLASH
SRAM
Figure 6.2-9 NuMicro® M031 Bus Matrix Diagram
6.2.8
IRC Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
external 32.768 kHz crystal oscillator, automatically gets accurate output frequency, 0.25 % deviation
within all temperature ranges.
In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_HIRCTRIMCTL [10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTRIMCTL [1:0]
trim frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_HIRCTRIMSTS[0] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation.
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6.2.9
Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence. All proteced control registers are noted “(Write
Protect)” and add an note “Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in
register description field.
Register
Bit
Description
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_PORCTL
SYS_SRAM_BISTCTL
SYS_PORDISAN
NMIEN
[7] CRCRST
[4] HDIV_RST
[2] PDMARST
[1] CPURST
CRC Calculation Controller Reset (Write Protect)
HDIV Controller Reset (Write Protect)
PDMA Controller Reset (Write Protect)
Processor Core One-shot Reset (Write Protect)
Chip One-shot Reset (Write Protect)
[0] CHIPRST
[20] LVRVL
LVR Detector Threshold Voltage Selection (Write Protect)
Brown-out Detector Threshold Voltage Selection (Write Protect)
LVR Output De-glitch Time Select (Write Protect)
Brown-out Detector Output De-glitch Time Select (Write Protect)
Low Voltage Reset Enable Bit (Write Protect)
Brown-out Detector Low Power Mode (Write Protect)
Brown-out Reset Enable Bit (Write Protect)
Brown-out Detector Enable Bit (Write Protect)
Power-on Reset Enable Bit (Write Protect)
PDMA BIST Enable Bit (Write Protect)
[16] BODVL
[14:12] LVRDGSEL
[10:8] BODDGSEL
[7] LVREN
[5] BODLPM
[3] BODRSTEN
[0] BODEN
[15:0] POROFF
[7] PDMABIST
[15:0] POROFFAN
[15] UART1_INT
[14] UART0_INT
[13] EINT5
Power-on Reset Enable Bit (Write Protect)
UART1 NMI Source Enable (Write Protect)
UART0 NMI Source Enable (Write Protect)
NMIEN
NMIEN
External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write
Protect)
NMIEN
NMIEN
NMIEN
NMIEN
NMIEN
[12] EINT4
[11] EINT3
[10] EINT2
[9] EINT1
[8] EINT0
External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable
(Write Protect)
External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write
Protect)
External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write
Protect)
External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable
(Write Protect)
External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write
Protect)
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NMIEN
[4] CLKFAIL
Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable
(Write Protect)
NMIEN
[2] PWRWU_INT
[1] IRC_INT
[0] BODOUT
[26:25] LXTGAIN
[22:20] HXTGAIN
[7] PDEN
Power-down Mode Wake-up NMI Source Enable (Write Protect)
IRC TRIM NMI Source Enable (Write Protect)
BOD NMI Source Enable (Write Protect)
LXT Gain Control Bit (Write Protect)
NMIEN
NMIEN
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_APBCLK0
CLK_CLKSEL0
CLK_CLKSEL0
CLK_CLKSEL1
CLK_CLKSEL1
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_CLKDSTS
CLK_CLKDSTS
CLK_CLKDSTS
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
HXT Gain Control Bit (Write Protect)
System Power-down Enable (Write Protect)
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Enable the Wake-up Delay Counter (Write Protect)
LIRC Enable Bit (Write Protect)
[5] PDWKIEN
[4] PDWKDLY
[3] LIRCEN
[2] HIRCEN
[1] LXTEN
HIRC Enable Bit (Write Protect)
LXT Enable Bit (Write Protect)
[0] HXTEN
HXT Enable Bit (Write Protect)
[0] WDTCKEN
[5:3] STCLKSEL
[2:0] HCLKSEL
[3:2] WWDTSEL
[1:0] WDTSEL
[23] STBSEL
[19] PLLSRC
[18] OE
Watchdog Timer Clock Enable Bit (Write Protect)
Cortex® -M0 SysTick Clock Source Selection (Write Protect)
HCLK Clock Source Selection (Write Protect)
Window Watchdog Timer Clock Source Selection (Write Protect)
Watchdog Timer Clock Source Selection (Write Protect)
PLL Stable Counter Selection (Write Protect)
PLL Source Clock Selection (Write Protect)
PLL OE (FOUT Enable) Pin Control (Write Protect)
PLL Bypass Control (Write Protect)
[17] BP
[16] PD
Power-down Mode (Write Protect)
[15:14] OUTDIV
[13:9] INDIV
[8:0] FBDIV
[8] HXTFQIF
[1] LXTFIF
PLL Output Divider Control (Write Protect)
PLL Input Divider Control (Write Protect)
PLL Feedback Divider Control (Write Protect)
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
LXT Clock Fail Interrupt Flag (Write Protect)
HXT Clock Fail Interrupt Flag (Write Protect)
ISP Fail Flag (Write Protect)
[0] HXTFIF
[6] ISPFF
[5] LDUEN
LDROM Update Enable Bit (Write Protect)
CONFIG Update Enable Bit (Write Protect)
APROM Update Enable Bit (Write Protect)
SPROM Update Enable Bit (Write Protect)
Boot Select (Write Protect)
[4] CFGUEN
[3] APUEN
[2] SPUEN
[1] BS
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FMC_ISPCTL
FMC_ISPTRG
FMC_FTCTL
FMC_ISPSTS
TIMER0_CTL
TIMER1_CTL
TIMER2_CTL
TIMER3_CTL
WDT_CTL
[0] ISPEN
ISP Enable Bit (Write Protect)
[0] ISPGO
ISP Start Trigger (Write Protect)
Frequency Optimization Mode (Write Protect)
ISP Fail Flag (Write Protect)
[6:4] FOM
[6] ISPFF
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[11:8] TOUTSEL
[7] WDTEN
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
WDT Time-out Interval Selection (Write Protect)
WDT Enable Bit (Write Protect)
WDT_CTL
WDT_CTL
WDT_CTL
[6] INTEN
WDT Time-out Interrupt Enable Bit (Write Protect)
WDT Time-out Wake-up Flag (Write Protect)
WDT_CTL
[5] WKF
WDT_CTL
[4] WKEN
WDT Time-out Wake-up Function Control (Write Protect)
WDT Time-out Reset Enable Bit (Write Protect)
WDT Reset Delay Selection (Write Protect)
WDT_CTL
[1] RSTEN
WDT_ALTCTL
PWM_CTL0
PWM_CTL0
PWM_DTCTL0_1
PWM_DTCTL0_1
[1:0] RSTDSEL
[31] DBGTRIOFF
[30] DBGHALT
[24] DTCKSEL
[16] DTEN
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Counter Halt (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL0_1
PWM_DTCTL2_3
PWM_DTCTL2_3
[11:0] DTCNT
[24] DTCKSEL
[16] DTEN
Dead-time Counter (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL2_3
PWM_DTCTL4_5
PWM_DTCTL4_5
[11:0] DTCNT
[24] DTCKSEL
[16] DTEN
Dead-time Counter (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL4_5
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[11:0] DTCNT
Dead-time Counter (Write Protect)
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
[12] BRKP0LEN
[9] CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
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PWM_BRKCTL0_1
[8] CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[7] SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
[5] BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[4] BRKP0EEN
[1] CPO1EBEN
[0] CPO0EBEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
[12] BRKP0LEN
[9] CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
[8] CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[7] SYSEBEN
[5] BRKP1EEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[4] BRKP0EEN
[1] CPO1EBEN
[0] CPO0EBEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
[12] BRKP0LEN
[9] CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
[8] CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
PWM_BRKCTL4_5
[7] SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
[5] BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
[4] BRKP0EEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
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PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_SWBRK
[1] CPO1EBEN
[0] CPO0EBEN
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
[8+n/2]
PWM Level Brake Software Trigger (Write Only) (Write Protect)
n=0,2,4 BRKLTRGn
PWM_SWBRK
[n/2]
PWM Edge Brake Software Trigger (Write Only) (Write Protect)
n=0,2,4 BRKETRGn
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTSTS1
[10] BRKLIEN4_5
[9] BRKLIEN2_3
[8] BRKLIEN0_1
[2] BRKEIEN4_5
[1] BRKEIEN2_3
[0] BRKEIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write
Protect)
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write
Protect)
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write
Protect)
[8+n]
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)
ADC RESET (Write Protect)
n=0,1..5 BRKLIFn
PWM_INTSTS1
ADC_ADCR
[n]
n=0,1..5 BRKEIFn
[12] RESET
Table 6.2-8 Protected Register List
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6.2.10 UART0_TXD/USCI0_DAT1 modulation with PWM
This chip supports UART0_TXD/USCI_DAT1 to modulate with PWM channel. User can set
MODPWMSEL(SYS_MODCTL[7:4]) to choose which PWM0 channel to modulate with
UART0_TXD/USCI0_DAT1 and set MODEN(SYS_MODCTL[0]) to enable modulation function. User
can set TXDINV(UART_LINE[8]) to inverse UART0_TXD or DATOINV(UUART_LINECTL[5]) to
inverse USCI0_DAT1 before modulating with PWM.
PWM0_CHx
UART0_TXD/USCI0_DAT0
TXDINV = 0 & MODH = 0
TXDINV = 0 & MODH = 1
TXDINV = 1 & MODH = 0
TXDINV = 1 & MODH = 1
Figure 6.2-11 UART0_TXD/USCI0_DAT1 Modulated with PWM Channel
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6.2.11 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
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6.2.12 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and
provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When
an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and branch
to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC
will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the
stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the
normal execution. Thus it will take less and deterministic time to process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to pending
ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of
concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to
execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the
higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
6.2.12.1 Exception Model and System Interrupt Map
Table 6.2-9 lists the exception model supported by the M031 series. Software can set four levels of
priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority
is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-
configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after
three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
3
-2
Hard Fault
Reserved
SVCall
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Reserved
PendSV
12 ~ 13
14
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SysTick
15
Configurable
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-9 Exception Model
Interrupt Number
Vector
Number
Interrupt Name
Interrupt
Interrupt Description
(Bit
In
Registers)
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-
-
System exceptions
0
BODOUT
WDT_INT
EINT024
Brown-Out low voltage detected interrupt
Watchdog Timer interrupt
External interrupt fromEINT0,2,4.
External interrupt fromEINT1.3.5
External interrupt from PA, PB pin
External interrupt from PC, PB pin
PWM0 interrupt
1
2
3
EINT135
4
GPAB_INT
GPCDEF_INT
PWM0_INT
PWM1_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
SPI0_INT
Reserved
Reserved
Reserved
I2C0_INT
I2C1_INT
Reserved
Reserved
USCI0
5
6
7
PWM1 interrupt
8
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Timer 2 interrupt
Timer 3 interrupt
UART0,2 interrupt
UART1 interrupt
SPI0 interrupt
Reserved
Reserved
Reserved
I2C0 interrupt
I2C1 interrupt
Reserved
Reserved
USCI0 interrupt
Reserved
Reserved
ACMP01_INT
PDMA_INT
ACMP0 and ACMP1 interrupt
PDMA interrupt
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43
44
45
46
47
27
28
29
30
31
Reserved
PWRWU_INT
ADC_INT
CLKFAIL
Reserved
Clock controller interrupt for chip wake-up from power-down state
ADC interrupt
Clock fail detected or IRC Auto Trim interrupt
Reserved
Reserved
Table 6.2-10 Interrupt Number Table
6.2.12.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer
on reset, and the entry point addresses for all exception handlers. The vector number on previous
page defines the order of entries in the vector table associated with exception handler entry as
illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Vector Number
Table 6.2-11 Vector Figure Format
6.2.12.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state
until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M0 core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~32
MHz external high speed crystal (HXT) and 48 MHz internal high speed RC oscillator (HIRC) to
reduce the overall system power consumption
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HIRC
HXT
LXT
LIRC
48MHz
4~32MHz
32.768 kHz
38.4 kHz
HIRC
1/4
PCLK0
PCLK1
1
0
PLLFOUT
/1,/2,/4,/8,/16
I2C0
PWM0
TMR0
TMR1
UART0
UART2
USCI0
WDT
ACMP
ADC
PLL FOUT
HXT
CLK_PLLCTL[19]
I2C1
CPU
CRC
PWM1
SPI0
FMC
HIRC
111
011
010
001
000
PDMA
SRAM
HDIV
TMR2
TMR3
UART1
LIRC
PLLFOUT
HCLK
1/(HCLKDIV+1)
LXT
HXT
/1,/2,/4,/8,/16
LIRC
CLK_CLKSEL0[2:0]
101
100
011
010
001
000
LIRC
PCLK0/PCLK1
HIRC
11
10
01
UART0
UART1
UART2
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
HCLK
1/2048
LXT
WDT
LXT
PLLOUT
HXT
CLK_CLKSEL1[1:0]
LIRC
CLK_CLKSEL1[26:24]
CLK_CLKSEL1[30:28]
CLK_CLKSEL3[26:24]
11
10
WWDT
HCLK
1/2048
CLK_CLKSEL1[3:2]
HIRC
1/2
111
011
010
001
000
CPUCLK
HCLK
1/2
1
0
SysTick
HXT
1/2
LXT
HIRC
PCLK1
PLLFOUT
HXT
11
10
01
00
SYST_CTRL[2]
HXT
1/(ADCDIV + 1)
ADC
CLK_CLKSEL0[5:3]
DIV1EN
(CLK_CLKOCTL[5])
ADCSEL
(CLKSEL2[21:20])
PLLFOUT
HIRC
110
101
100
LIRC
/2(CLK_CLKOCTL[3:0]+1)
HIRC
CLKO
0
1
HIRC
HCLK
LXT
11
011
010
001
PCLK1
10
01
00
1/(SPI0_CLKDIV[8:0]+1)
SPI0
PLLFOUT
HXT
HXT
000
CLK_CLKSEL1[6:4]
CLK_CLKSEL2[5:4]
PCLK0
1
0
PWM 0
PCLK1
PLLFOUT
1
0
PWM 1
PLLFOUT
CLK_CLKSEL2[0]
CLK_CLKSEL2[1]
HIRC
HIRC
LIRC
111
101
011
010
001
000
111
101
011
010
001
000
LIRC
TM0/TM1
TM2/TM3
TMR0
TMR1
TMR2
TMR3
PCLK0
LXT
PCLK1
LXT
HXT
HXT
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2
Clock Generator
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~32 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~32 MHz external high speed crystal (HXT) or 48 MHz internal high speed
oscillator (HIRC/4)
48 MHz internal high speed RC oscillator (HIRC)
38.4 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
LXT
(LXT)
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~32
PLLSRC (CLK_PLLCTL[19])
MHz Crystal
(HXT)
XT1_OUT
0
1
HIRCEN (CLK_PWRCTL[2])
PLL FOUT
PLL
/4
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRCEN (CLK_PWRCTL[3])
Internal 38.4
kHz Oscillator
(LIRC)
LIRC
Figure 6.3-2 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.3-3
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN (CLK_CLKDCTL[5]) is
set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Figure 6.3-5 SysTick Clock Control Block Diagram
Peripherals Clock
6.3.4
The peripherals clock has different clock source switch setting, which depends on the different
peripheral.
6.3.5
Power-down Mode Clock
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When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
–
–
38.4 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0
to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.
CLKOEN
Enable
(CLK_CLKOCTL[4])
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
PLL
110
0000
0001
:
LIRC
HIRC
100
011
010
001
000
16 to 1
MUX
CLKO
0
1
:
1110
HCLK
LXT
1111
HXT
CLKOSEL (CLK_CLKSEL1[6:4])
Figure 6.3-6 Clock Output Block Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
This chip is equipped with 64/128 Kbytes on-chip embedded Flash for application and Data Flash to
store some application dependent data. A User Configuration block provides for system initialization. A
2/4 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function with 128 Kbytes
Flash and 2 Kbytes LDROM for other size Flash. A 512 bytes security protection ROM (SPROM) can
conceal user program. This chip also supports In-Application-Programming (IAP) function, user
switches the code executing without the chip reset after the embedded Flash updated.
6.4.2
Features
Supports 64/128 Kbytes application ROM (APROM).
Supports 2/4 Kbytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports 512 bytes security protection ROM (SPROM) to conceal user program.
Supports 12 bytes User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded Flash.
Supports CRC-32 checksum calculation function.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 29 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 29 pins are arranged in 5 ports named as PA, PB, PC, PD and PF. PA
and PB. Each of the 29 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).
6.5.2
Features
Four I/O modes:
–
–
–
–
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input
I/O pin can be configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
–
–
CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
Supports input 5V tolerance, except analog pin (PA.10 ~ 11; PB.0 ~ 15; PF.2 ~ 5;
nRESET pin).
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 5 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.6.2
Features
Supports 5 independently configurable channels
Selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and I2C, SPI, UART, USCI, ADC, PWM and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
6.7.2
Features
6.7.2.1 Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports internal capture triggered while internal ACMP output signal and LIRC transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
PWM, ADC, PDMA function
Supports Inter-Timer trigger mode
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.8.2
Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if
WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.9.2
Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.10 PWM Generator and Capture Timer (PWM)
6.10.1 Overview
The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of
PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM
counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.
PWM uses comparator compared with counter to generate events. These events use to generate
PWM pulse, interrupt and trigger signal for ADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. In Complementary mode, there are two
comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control
unit, it supports polarity output, independent pin mask and brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.10.2 Features
6.10.2.1 PWM Function Features
Supports maximum clock frequency up to 96 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
–
–
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution PWM counter
–
Up, down and up-down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
–
Brake source from pin and system safety events (clock failed, Brown-out
detection and CPU lockup)
–
–
–
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
–
–
PWM counter matches 0, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter matches 0, period value or compared value
6.10.2.2 Capture Function Features
–
Supports up to 12 capture input channels with 16-bit resolution
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Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.11 UART Interface Controller (UART)
6.11.1 Overview
The chip provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The
UART controller performs Normal Speed UART and supports flow control function. The UART
controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-
to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten
types of interrupts. The UART controller also supports IrDA SIR, RS-485 and Single-wire function
modes and auto-baud rate measuring function.
6.11.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Support Single-wire function mode.
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function (Only UART0 /UART1 with Received Data
FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function)
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
–
Support 9600 bps for UART_CLK is selected LXT. (Only UART0 /UART1 with
this feature)
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
–
–
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
–
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
–
Supports for 3/16 bit duration for normal mode
Supports RS-485 function mode
–
–
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
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UART Feature
UART0/ UART1
UART2
USCI-UART
TX: 1byte
RX: 2byte
FIFO
16 Bytes
1 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
-
√
√
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Imcoming Data Wake-up
√
√
√
√
√
√
√
√
√
-
Received Data FIFO reached threshold Wake-
up
√
-
RS-485 Address Match (AAD mode) Wake-up
Auto-Baud Rate Measurement
STOP Bit Length
√
-
-
√
√
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
Word Length
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
√
√
√
√
√
Stick Bit
-
Note: √= Supported
Table 6.11-1 NuMicro® M031 Series UART Features
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6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one set of SPI controller performing a serial-to-parallel conversion on data received from
a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Each SPI controller can be configured as a master or a slave device and supports the PDMA function
to access the data buffer.
6.12.2 Features
SPI Mode
–
–
–
–
Supports one set of SPI controller
Dedicated SPI controller for RF transceiver.
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive
FIFO buffers which depended on SPI setting of data width
–
–
–
–
–
–
–
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Master mode up to 16 MHz (when chip works at VDD = 1.8~3.6V)
Supports one data channel half-duplex transfer
Supports receive-only mode
Supports PDMA transfer
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6.13 I2C Serial Interface Controller (I2C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.13.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps) and Fast mode (400 kbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
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6.14 USCI - Universal Serial Control Interface Controller (USCI)
6.14.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.14.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
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6.15 USCI – UART Mode
6.15.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the system.
6.15.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.16 USCI - SPI Mode
6.16.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as Master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in Master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0
Note: M031BT series doesn’t support USCIx_CTL0 pin. User needs to use GPIO as SPI_SS pin.
Figure 6.16-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0
Figure 6.16-2 SPI Slave Mode Application Block Diagram
6.16.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2,
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Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.17 USCI - I2C Mode
6.17.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on
the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.17-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.17-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode .
6.17.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.18 CRC Controller (CRC)
6.18.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.18.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
–
–
–
–
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X
+ 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
–
–
–
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.19 Hardware Divider (HDIV)
6.19.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a
signed, integer divider with both quotient and remainder outputs.
6.19.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
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6.20 Analog-to-Digital Converter (ADC)
6.20.1 Overview
The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D
converter) with 16 input channels. The A/D converter supports four operation modes: Single, Burst,
Single-cycle Scan and Continuous Scan mode. The A/D converter can be started by software,
external pin (STADC/PF.5), timer0~3 overflow pulse trigger and PWM trigger.
6.20.2 Features
Operating voltage: 1.8V~3.6V.
Analog input voltage: 0 ~ AVDD.
Supports external reference voltage from VREF pin.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels or 8 differential analog input channels.
Maximum ADC peripheral clock frequency is 34 MHz.
Up to 2 MSPS sampling rate.
Scan on enabled channels
Threshold voltage detection
Four operation modes:
–
–
Single mode: A/D conversion is performed one time on a specified channel.
Burst mode: A/D converter samples and converts the specified single channel
and sequentially stores the result in FIFO.
–
–
Single-cycle Scan mode: A/D conversion is performed only one cycle on all
specified channels with the sequence from the smallest numbered channel to
the largest numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan
mode until software stops A/D conversion.
An A/D conversion can be started by:
–
–
–
–
Software Write 1 to ADST bit.
External pin (STADC).
Timer 0~3 overflow pulse trigger.
PWM trigger.
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Supports extend sample time function (0~255 ADC clock).
One internal channel from band-gap voltage (VBG).
Supports PDMA transfer mode.
Supports Calibration mode.
Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
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Note2: If the internal channel for band-gap voltage is active, the maximum sampling rate will be 300 k
SPS.
Note3: The ADC Clock frequency must be slower than or equal to PCLK.
Aug. 18, 2020
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6.21 Analog Comparator Controller (ACMP)
6.21.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.21.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two analog comparators
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports:
–
4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
3 negative sources:
–
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
ACMP1 supports
4 multiplexed I/O pins at positive sources:
–
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
3 negative sources:
–
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
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6.22 Radio
6.22.1 Overview
This chip is equipped with an RF transceiver for wireless application use. The RF transceiver includes
an RF radio and modulator/demodulator. It is fully compliant with the Bluetooth 5.0 standard and also
supports proprietary 2.4 GHz protocols.
6.22.2 Features
Modem with Integrated RF radio for 2.4 GHz Bluetooth communication link
Compliant with Bluetooth 5 Low Energy Specification
Supports proprietary 2.4 GHz protocols
High TX power with low current (+8 dBm, 8 mA)
Programmable output power from -20 dBm to +8 dBm
Rx Sensitivity : -94 dBm at 1 Mbps
Data rate: 1Mbps and 2Mbps
Immune to interference (image rejection, -25 dBm)
32 kHz low speed on-chip RC oscillator with deviation less than ± 500 ppm
Dedicated 16/32 MHz high speed crystal
RSSI read-out
Integrated security engine for real-time processing of the data stream
– AES-CCM
– AES-128
– CRC
Two power modes for RF transceiver
– DC-to-DC mode
– LDO mode
Five operating modes:
– Deep Sleep
– Sleep
– Standby
– Receive
– Transmit
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6.23 Peripherals Interconnection
6.23.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interaction without CPU
saves CPU resources, reduces power consumption, and allows for operation with no software latency
and fast responds.
6.23.2 Peripherals Interconnect Matrix Table
Destination
Source
ADC
HIRC TRIM
PWM
Timer
UART/USCI
ACMP
BOD
-
-
-
-
3
3
3
3
-
6
-
-
-
-
-
-
Clock Fail
CPU Lockup
LIRC
-
-
-
-
-
-
-
-
6
-
HXT
-
-
-
LXT
-
2
-
-
-
PWM
1
1
4
5
-
8
-
Timer
-
7
Table 6.23-1 Peripherals Interconnect Matrix Table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme (DC-to-DC Mode)
Sunlord/ SDCL1005C15N
Murata/ LQM18FN100M00D
as close to AVDD as possible
L=30Z
as close as possible
EXT_PWR
RF_BUCK_FB
RF_AVDDV1V2
AVDD
L=10 uH L=15 nH
AVSS
1uF+0.1uF+0.01uF
L=30Z
RF_BUCK_OUT
VSS
1uF
as close to the
VREF
EXT_PWR as possible
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
10uF+0.1uF
LDO_CAP
as close to RF_VDD / RF_VDDas
possible
0.1uF
VSS
RF_VDDPA
1uF
as close to LDO as possible
L=30Z
VDD
RF_VDD
EXT_PWR
EXT_VSS
VSS
VSS
1uF
EXT_VSS
0.1uF*N
as close to VDD as possible
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7.2 Power Supply Scheme (LDO Mode)
as close to AVDD as possible
L=30Z
as close as possible
EXT_PWR
RF_BUCK_FB
RF_AVDDV1V2
AVDD
AVSS
1uF+0.1uF+0.01uF
L=30Z
RF_BUCK_OUT
VSS
1uF
as close to the
VREF
EXT_PWR as possible
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
10uF+0.1uF
LDO_CAP
as close to RF_VDD / RF_VDDPA as
possible
0.1uF
VSS
RF_VDDPA
1uF
as close to LDO as possible
L=30Z
VDD
RF_VDD
EXT_PWR
EXT_VSS
VSS
VSS
1uF
EXT_VSS
0.1uF*N
as close to VDD as possible
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M031BT
7.3 Peripheral Application Scheme (M031BTxE)
DVCC
100K
100K
DVCC
VDD
ICE_DAT
SWD
Interface
CS
GPIO*
ICE_CLK
nRESET
VDD
VSS
USPI_CLK
USPI_MISO
USPI_MOSI
CLK
MISO
MOSI
VSS
20pF
20pF
20pF
20pF
XT1_IN
SPI Device
4~32 MHz
crystal
DVCC
DVCC
XT1_OUT
X32_IN
4.7K
4.7K
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
Crystal
32.768 kHz
crystal
I2C Device
X32_OUT
PC COM Port
RS 232 Transceiver
M031BTxE Series
15pF
15pF
UART_RXD
ROUT RIN
RF_XTAL_IN
UART_TXD
TIN
TOUT
16 MHz
crystal
± 10 ppm
UART
RF_XTAL_OUT
DVCC
Reset
Circuit
Antenna
Murata
10K
LQG15HS1N8B02
10 pF
1.8 nH
nRESET
RF_IO
10 uF
0.5 pF
0.5 pF
0.5 pF
0.5 pF
LDO_CAP
1.0 nH
Sunlord
SDCL1005C1NOSTDF
1.0 nH
Sunlord
SDCL1005C1NOSTDF
1 uF
LDO
Notch Filter
Notch Filter
Note 1: M031BT series doesn’t support USCIx_CTL0 pin. User needs to use GPIO as SPI_SS pin.
Note 2: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 3: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
Aug. 18, 2020
Page 87 of 140
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M031BT
7.4 Peripheral Application Scheme (M031BTxD)
DVCC
100K
100K
DVCC
VDD
ICE_DAT
SWD
Interface
CS
GPIO*
ICE_CLK
nRESET
VDD
VSS
USPI_CLK
USPI_MISO
USPI_MOSI
CLK
MISO
MOSI
VSS
20pF
20pF
20pF
20pF
XT1_IN
SPI Device
4~32 MHz
crystal
DVCC
DVCC
XT1_OUT
X32_IN
4.7K
4.7K
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
Crystal
32.768 kHz
crystal
I2C Device
X32_OUT
PC COM Port
RS 232 Transceiver
M031BTxD Series
15pF
15pF
UART_RXD
ROUT RIN
RF_XTAL_IN
UART_TXD
TIN
TOUT
16 MHz
crystal
± 10 ppm
UART
RF_XTAL_OUT
DVCC
Reset
Circuit
Antenna
Murata
10K
LQG15HS3N3S02D
10 pF
3.3 nH
nRESET
RF_IO
10 uF
0.5 pF
0.5 pF
LDO_CAP
1.0 nH
1.0 nH
Sunlord
SDCL1005C1NOSTDF
Sunlord
SDCL1005C1NOSTDF
1 uF
LDO
Notch Filter
Notch Filter
Note 1: M031BT series doesn’t support USCIx_CTL0 pin. User needs to use GPIO as SPI_SS pin.
Note 2: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 3: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
Aug. 18, 2020
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7.5 PCB Layout Guide
1. Pin-7( RF_IO) path is 50 ohm. The path should be as short as possible, And Pin-6 (VSS) and Pin-8
(VSS) should be connected to GND, but not directly connected to Pin-49 (VSS). Do not have any
lines underneath, and it is best to have GND for isolation.
2. The power capacitor closed to chip is better.
3. The crystal ground is better to stay away from RF_IO path. After the crystal ground and capacitor
ground are connected to confluence, pull a path out of PCB ground. Do not have a ground via in
this path.
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4. Pin-17 (RF_BUCK_FB) & Pin-18 (RF_BUCK_OUT) DC-to-DC path closed to chip is better. After
C37 ground and Pin-20 are connected to confluence, pull a path out of PCB ground. Do not have
a ground via in this path and Pin-20 (VSS) cannot be directly connected to Pin-49 (VSS) .
Aug. 18, 2020
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
4.0
4.0
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
[*1]
RF_VDD-VSS
Power supply for RF transceiver
-0.3
V
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance I/O
-
mV
mV
mV
mV
V
ΔVDD
|VDD –AVDD
|
-
50
-
50
ΔVSS
|VSS - AVSS
|
-
50
VSS-0.3
VSS-0.3
5.5
4.0
VIN
Input voltage on any other pin[*2]
V
Note:
1. All main power (VDD, RF_VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance I/O includes; PB.0 ~ 15; PF.2, 3, 4, 5. VIN maximum value must be respected to avoid permanent
damage. Refer to Table 8.1-2 for the values of the maximum allowed injected current
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
150
100
20
Unit
[*1]
ΣIDD
ΣISS
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
-
-
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
IIO
mA
100
100
±5
[*3]
IINJ(PIN)
[*3]
ΣIINJ(PIN)
±25
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
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Table 8.1-2 Current Characteristics
Aug. 18, 2020
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8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (°C)
θJA = thermal resistance junction-ambient (°C/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
85
Unit
°C
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
T
J
-40
-65
-
125
150
T
ST
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
°C/Watt
38
30
-
-
-
-
-
-
-
-
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
-
-
-
-
-
-
-
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
28
Thermal resistance junction-ambient
40-pin QFN(5x5 mm)
37.8
37.8
60
[*1]
θJA
Thermal resistance junction-ambient
48-pin QFN(5x5 mm)
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
58
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)
38.5
Note:
1.
Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal Characteristics
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M031BT
8.1.4
EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
Symbol
Description
Min
-2000
-400
Typ
Max
+2000
+400
Unit
V
[*1]
VHBM
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
-
-
-
[*2]
VCDM
LU[*3]
-100
mA
+100
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. The performace cretia class is 4A.
Table 8.1-4 EMC Characteristics
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8.1.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge
20-pin TSSOP(4.4x6.5 mm)[*1]
28-pin TSSOP(4.4x9.7 mm) [*1]
33-pin QFN(4x4 mm) [*1]
MSL
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
40-pin QFN(5x5 mm) [*1]
48-pin QFN(5x5 mm) [*1]
48-pin LQFP(7x7 mm) [*1]
64-pin LQFP(7x7 mm) [*1]
128-pin LQFP(14x14 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-5 Package Moisture Sensitivity (MSL)
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M031BT
8.1.6
Soldering Profile
Figure 8.1-1 Soldering Profile from J-STD-020C
Porfile Feature
Pb Free Package
3°C/sec. max
Average ramp-up rate (217°C to peak)
Preheat temperature 150°C ~200°C
Temperature maintained above 217°C
Time with 5°C of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260°C
Ramp-down rate
6°C/sec ax.
8 min. max
Time 25°C to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.1-6 Soldering Profile
Aug. 18, 2020
Page 96 of 140
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M031BT
8.2 General Operating Conditions
(VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 48 MHz unless otherwise specified.)
Test Conditions
Min
-40
-
Typ
Max
85
Unit
°C
Symbol
TA
Parameter
Temperature
-
-
-
fHCLK
Internal AHB clock frequency
Operation voltage
48
MHz
VDD = 1.8 V~3.6 V
f
VDD
1.8
2.3
1.8
3.6
3.6
3.6
HCLK up to 48 MHz
-
DC-to-DC mode
LDO mode
RF_VDD
RF_VDDPA
RF transceiver operation voltage
-
RF_VDD
1.2
VDD
-
RF power amplifier operation voltage
V
RF_AVDD1V2 RF Transceiver 1.2 V voltage
-
-
[*1]
AVDD
VREF
VLDO
Analog operation voltage
Analog reference voltage
LDO output voltage
1.8
-
AVDD
-
AVDD − VREF < 1.2 V
1.8
1.23
1
[*4]
VBG
CLDO
RESR
Band-gap voltage
1.16
1.31
[*2]
[*3]
LDO output capacitor on each pin
ESR of CLDO output capacitor
μF
0.1
-
-
10
-
Ω
InRush current on voltage regulator
power-on (POR or wakeup from
Standby)
[*3]
IRUSH
150
mA
InRush energy on voltage regulator
power-on (POR or wakeup from
Standby)
VDD = 1.8 V, TA = 85 °C,
IRUSH = 150 mA for 15 us
[*3]
ERUSH
-
2.25
-
µC
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3.Guaranteed by design, not tested in production
4.Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 General Operating Conditions
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M031BT
8.3 DC Electrical Characteristics
8.3.1 Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T = 85 °C
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
8.8
6.2
5
10.1
7.1
5.8
4.1
2.8
10.5
7.6
6.0
4.4
3.0
Normal run mode, executed from
Flash, all peripherals disable
3.6
2.4
38.4 kHz
32.768 kHz
48 MHz
0.105
0.104
20
0.121
0.120
23.0
0.275
0.273
23.7
32 MHz
24 MHz
12 MHz
4 MHz
12.9
11.2
6.7
14.8
12.9
7.7
15.5
13.3
8.0
IDD_RUN
mA
Normal run mode, executed from
Flash, all peripherals enable
3.9
4.5
4.7
38.4 kHz
32.768 kHz
48 MHz
32 MHz
24 MHz
12 MHz
0.111
0.110
11.4
7.8
0.128
0.127
13.11
8.97
7.36
4.83
0.283
0.281
13.5
9.5
Normal run mode, executed from
Flash, Timer1/SPI0/PDMA enable
6.4
7.7
4.2
5.1
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT, LXT and RF transceiver are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
3. The RF transceiver operates in deep sleep mode.
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Table 8.3-1 Current Consumption in Normal Run Mode
Typ
Max[*1] [*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T = 85 °C
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
3.85
3.15
2.74
1.83
1.74
4.43
3.62
3.15
2.10
2.00
4.68
4.01
3.36
2.30
2.19
Idle mode, all peripherals disable
38.4 kHz
32.768 kHz
48 MHz
0.098
0.099
15.45
0.113
0.114
17.77
0.266
0.267
18.36
32 MHz
24 MHz
12 MHz
4 MHz
10.02
8.81
5.46
3.23
0.108
0.107
6.45
5.83
5.15
4.5
11.52
10.13
6.28
12.15
10.53
6.57
IDD_IDLE
mA
Idle mode, all peripherals enable
3.71
3.94
38.4 kHz
32.768 kHz
48 MHz
32 MHz
24 MHz
12 MHz
0.124
0.123
7.42
0.279
0.277
7.73
6.70
7.14
Idle mode, Timer1/SPI0/PDMA
enable
5.92
6.17
5.18
5.39
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT, LXT and RF transceiver are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
3. The RF transceiver operates in deep sleep mode.
Table 8.3-2 Current Consumption in Idle Mode
Aug. 18, 2020
Page 99 of 140
Rev. 1.01
M031BT
Typ[*2]
= 25
Max[*3][*4]
LXT[*1] LIRC
Symbol
Test Conditions
Unit
32.768
kHz
38.4
kHz
T
T
=
T =
A
A
A
°C
25 °C 85 °C
Power-down mode, all peripherals disable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT use LIRC, UART/Timer use LXT
-
V
-
-
-
13
25
28
27
29
355
365
370
380
15.5
14.5
16.5
IDD_PD
µA
V
V
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as ADC, ACMP and RF transceiver are ON, an additional power consumption
should be considered.
5. Based on characterization, tested in production.
6. The RF transceiver operates in deep sleep mode.
Table 8.3-3 Chip Current Consumption in Power-down Mode
Aug. 18, 2020
Page 100 of 140
Rev. 1.01
M031BT
8.3.2
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[*1]
Peripheral
PDMA
ISP
IDD
Unit
0.721
0.0002
0.135
0.119
0.122
0.125
0.332
0.303
0.299
0.292
0.095
0.243
0.159
0.122
1.878
0.629
0.575
0.631
0.962
0.638
0.445
1.257
1.26
HDIV
CRC
SRAM0IDLE
WDT/WWDT
TMR0
TMR1
TMR2
TMR3
CLKO
ACMP01[*3]
I2C0
mA
I2C1
SPI
UART0
UART1
UART2
ADC[*2]
USCI0
USCI1
PWM0
PWM1
Radio[*4]
0.0004
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
4. The RF transceiver operates in deep sleep mode.
Table 8.3-4 Peripheral Current Consumption
Aug. 18, 2020
Page 101 of 140
Rev. 1.01
M031BT
8.3.3
RF Supply Current Characteristics
Tast condition: DC-to-DC Mode, TA= 25 °C, RF_VDD = 3.3V, RF_VDDPA = 3.3V, VDD = 3.3 V and AVDD = 3.3 V.
Symbol
IRF_DeepSleep
IRF_Sleep
IRF_Standby
IRF_RX
Parameter
Min
Typ
0.4
0.7
1.3
6.6
5.5
6.5
8.2
Max
Unit
Test Conditions
Deep Sleep
Sleep
µA
µA
Standby
Radio RX
Radio TX
Radio TX
Radio TX
mA
mA 2 Mbps
IRF_TX+0
mA 0-dBm, 2 Mbps
mA 4-dBm, 2 Mbps
mA 8-dBm, 2 Mbps
IRF_TX+4
IRF_TX+8
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.3-5 RF DC Characteristics
RF Operating Mode Switching Times
8.3.4
The switching times given in Table 8.3-6 is measured on a switching phase with a with a 48 MHz
HIRC.
To
Deep Sleep
Sleep
Standby
Receive
Transmit
From
Deep Sleep
Sleep
-
X
X
-
3 ms
3 ms
-
X
X
X
X
Standby
Receive
Transmit
Note:
1 ms
X
1 ms
X
100 µs
100 µs
0 µs
0 µs
-
X
-
X
X
X
1. X: not allowed
Table 8.3-6 RF Operating Mode Switching Times
Aug. 18, 2020
Page 102 of 140
Rev. 1.01
M031BT
8.3.5
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.3-7 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
Symbol
Parameter
Typ
5
Max
6
Unit
cycles
µs
tWU_IDLE
Wakeup from IDLE mode
Wakeup from normal power down mode
[*1][*2]
tWU_NPD
12
25
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-7 Low-power Mode Wakeup Timings
8.3.6
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece
I/O should be avoided during normal product operation. However, the analog compoenent of the MCU
is most likely to be affected by the injection current , but it is not easily clarified when abnormal
injection accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to
VDD) to pins that include analog function which may potentially injection currents.
Negative
injection
Positive
injection
Symbol
Parameter
Unit
Test Condition
-0
-0
0
0
Injected current on nReset pins
Injected current on PF2~PF5, and
PB0~PB15 for analog input function
Injected current by a I/O Pin
mA
IINJ(PIN)
Injected current on any other 5V-
tolerance I/O
-5
NA
Table 8.3-8 I/O Current Injection Characteristics
8.3.7
I/O DC Characteristics
8.3.7.1 PIN Input Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
0.3*VDD
VDD
Unit
V
Test Conditions
Input low voltage
Input high voltage
0
-
VIH
0.7*VDD
-
-
V
[*1]
VHY
Hysteresis voltage of schmitt input
0.2*VDD
-
V
VSS < VIN < VDD
,
-1
-1
1
1
Open-drain or input only mode
[*2]
ILK
Input leakage current
A
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
Aug. 18, 2020
Page 103 of 140
Rev. 1.01
M031BT
-
-
45
-
-
VDD = 3.3 V, Quasi mode
[*1] [*3]
RPU
Pull up resistor
kΩ
120
VDD = 1.8 V, Quasi mode
Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher
than the maximum value, if positive current is injected on adjacent pins
Table 8.3-9 I/O Input Characteristics
Aug. 18, 2020
Page 104 of 140
Rev. 1.01
M031BT
8.3.7.2 I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 3.3 V
-25.5
-28
-31
µA
VIN=(VDD-0.4) V
Source current for quasi-
bidirectional mode and
high level
VDD = 2.5 V
-19
-10.5
-8
-22
-13
-10
-8
-24
-16
µA
µA
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
[*1] [*2]
ISR
VDD = 3.3 V
-15
mA
mA
mA
mA
mA
VIN=(VDD-0.4) V
VDD = 2.5 V
Source current for push-
pull mode and high level
-6
-13
VIN=(VDD-0.4) V
VDD = 1.8 V
-3.5
7.5
6
-5.5
9
-10.5
14.5
13
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
VDD = 2.5 V
VIN= 0.4 V
Sink current for push-
pull mode and low level
[*1] [*2]
ISK
7.5
VDD = 1.8 V
VIN= 0.4 V
3.5
-
5
5
10.5
-
mA
pF
[*1]
CIO
I/O pin capacitance
Note:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.3-10 I/O Output Characteristics
8.3.7.3 nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Min
Typ
-
Max Unit
Test Conditions
-
0.3*VDD
V
V
VIHR
0.7*VDD
-
-
-
-
45
120
32
-
-
VDD = 3.3 V
[*1]
RRST
Internal nRESET pull up resistor
nRESET input filtered pulse time
KΩ
-
-
VDD = 1.8 V
-
Normal run and Idle mode
Power down mode
[*1]
tFR
µs
75
155
Note:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.3-11 nRESET Input Characteristics
Aug. 18, 2020
Page 105 of 140
Rev. 1.01
M031BT
8.4 AC Electrical Characteristics
8.4.1
48 MHz Internal High Speed RC Oscillator (HIRC)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.8
-
3.6
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
47.52
-1
48
-
48.48
1
MHz
%
fHRC
TA = 25 °C,
VDD = 3.3V
Frequency drift over temperarure and
volatge
TA = -40C ~ +85 °C,
-2[*1]
-
2[*1]
-
%
µA
µs
VDD = 1.8 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
-
-
1655
11
TA = -40C ~ +85 °C,
[*2]
TS
15
VDD = 1.8 ~ 3.6V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
Aug. 18, 2020
Page 106 of 140
Rev. 1.01
M031BT
(a) Test condition: VDD=3.6 V, Temp = -40~125°C
(b) Test condition: VDD=2.7 V, Temp = -40~125°C
Aug. 18, 2020
Page 107 of 140
Rev. 1.01
M031BT
(c) Test condition: VDD=1.8 V, Temp = -40~125°C
Note:
1. The graph is a statistical result using a limited number of samples. For the actual characteristic range, please refer to
Table 8.4-1.
Figure 8.4-1 HIRC vs. Temperature
Aug. 18, 2020
Page 108 of 140
Rev. 1.01
M031BT
8.4.2
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.8
-
3.6
V
Oscillator frequnecy
38.016
38.4
38.784
kHz
TA = 25 °C,
VDD = 3.3V
-1
-
-
1
%
%
[*2]
FLRC
Frequency drift over temperarure
and volatge
TA=-40~85 °C
-15
15
VDD=1.8V~3.6V
Without software calibration
ILRC
TS
Operating current
Stable time
-
-
1
-
-
µA
VDD = 3.3V
TA=-40~85 °C
500
μs
VDD=1.8V~3.6V
Note:
1. Guaranteed by characterization, not tested in production.
2. The 38.4 kHz low speed RC oscillator can be calibrated by user.
3. Guaranteed by design.
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
Aug. 18, 2020
Page 109 of 140
Rev. 1.01
M031BT
(a) Test condition: VDD=3.6 V, Temp = -40~125°C
(b) Test condition: VDD=2.7 V, Temp = -40~125°C
Aug. 18, 2020
Page 110 of 140
Rev. 1.01
M031BT
(c) Test condition: VDD=1.8 V, Temp = -40~125°C
Note:
1. The graph is a statistical result using a limited number of samples. For the actual characteristic range, please refer to
Table 8.4-2.
Figure 8.4-2 LIRC vs. Temperature
Aug. 18, 2020
Page 111 of 140
Rev. 1.01
M031BT
8.4.3
32 kHz Internal RF Low Speed RC Oscillator
Min
Typ
Max
Unit
Symbol
Parameter
Test Conditions
FRF_LRC Oscillator frequnecy
32
kHz
FCAL
FTC
TS
Frequency Accuracy
Temperature Coefficient
Stable time
-
-
-
500
200
300
-
-
-
ppm TA= 25°C
ppm/°C
μs
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-3 32 kHz Internal RF Low Speed RC Oscillator Characteristics
8.4.4
External 16/32 MHz RF High Speed Crystal characteristics
The RF high-speed external clock can be supplied with a 16 or 32 MHz crystal oscillator. All the
information given in this secion are based on characterization results obtained with typical external
components. In the application, the external components have to be placed as close as possible to the
RF_XTAL_IN and RF_ XTAL_OUT pins and must not be connected to any other devices in order to
minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Parameter
Oscillator frequency
Min[*1]
Typ
16
-
Max[*1]
Unit
MHz
Test Conditions
fRF_XT
Frequency Tolerance
Equivalent Series Resistance (ESR)
Drive Level
-50
50
ppm
TA= 25°C
Rs
100
ohm
0.1
mW
Load Capacitance
9
pF
Frequency vs. Temperature
Aging
-20
-3
20
3
ppm
TA= -20 ~ +85°C
ppm/year
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-4 External 16 MHz RF High Speed Crystal Characteristics
Symbol
fRF_XT
Parameter
Oscillator frequency
Min[*1]
Typ
32
-
Max[*1]
Unit
MHz
Test Conditions
Frequency Tolerance
Equivalent Series Resistance (ESR)
Drive Level
-50
50
ppm
TA= 25°C
60
ohm
0.1
mW
Load Capacitance
10
pF
Frequency vs. Temperature
Aging
-20
-3
20
3
ppm
TA= -20 ~ +85°C
ppm/year
Aug. 18, 2020
Page 112 of 140
Rev. 1.01
M031BT
Symbol
Note:
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
1. Guaranteed by characterization, not tested in production.
Table 8.4-5 External 32 MHz RF High Speed Crystal Characteristics
8.4.4.1 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (3 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
16 MHz
C1
C2
R1
10 ~ 25 pF
10 ~ 25 pF
10 ~ 25 pF
10 ~ 25 pF
without
without
32 MHz
RF_XTAL_OUT
RF_XTl_IN
R1
C1
C2
Figure 8.4-3 Typical Crystal Application Circuit
Aug. 18, 2020
Page 113 of 140
Rev. 1.01
M031BT
8.4.6
External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[*1]
Typ
-
Max[*1]
Unit
V
Test Conditions
1.8
-
3.6
-
Rf
Internal feedback resister
Oscillator frequency
200
kΩ
fHXT
4
-
-
32
MHz
120
200
4 MHz, Gain = L0
170
250
350
500
650
1700
900
600
450
400
350
300
450
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
4 MHz, Gain = L0
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
-
-
IHXT
Current consumption
A
600
850
-
-
1100
2200
1100
740
-
-
-
-
TS
Stable time
s
650
600
550
DuHXT
Vpp
Duty cycle
40
-
-
60
-
%
V
Peak-to-peak amplitude
1
Note:
1.
Guaranteed by characterization, not tested in production.
Table 8.4-6 External 4~32 MHz High Speed Crystal (HXT) Oscillator
Aug. 18, 2020
Page 114 of 140
Rev. 1.01
M031BT
Symbol
Parameter
Min[*1]
Typ
Max[*1]
150
50
Unit
Test Conditions
Crystal @4 MHz
-
-
-
-
-
-
-
-
-
-
Crystal @12 MHz
Crystal @16 MHz
Crystal @24 MHz
Crystal @32 MHz
Rs
Equivalent series resisotr(ESR)
40
Ω
40
40
Note:
1. Guaranteed by characterization, not tested in production.
2. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life.
If Safety factor isn’t enough, the HXT gain should be increased.
ꢃꢄ
ꢐꢂꢄ
ꢑ
ꢁꢂꢄ
ꢎꢏꢏꢂ
ꢁꢂ
ꢀ
ꢅꢆꢇꢈꢉꢊꢋꢂꢌꢍꢄ
ꢄ
ꢑ
RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is
only used to measure Safety factor (Sf) and is not suitable for mass production.
XT1_OUT
XT1_IN
RADD
C2
C1
Table 8.4-7 External 4~32 MHz High Speed Crystal Characteristics
8.4.6.2 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 32 MHz
10 ~ 25 pF
10 ~ 25 pF
without
XT1_OUT
XT1_IN
R1
C1
C2
Figure 8.4-4 Typical Crystal Application Circuit
Aug. 18, 2020
Page 115 of 140
Rev. 1.01
M031BT
8.4.7
External 4~32 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
1
-
32
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
ns
ns
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
ns
ns
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-8 External 4~32 MHz High Speed Clock Input Signal
Aug. 18, 2020
Page 116 of 140
Rev. 1.01
M031BT
8.4.8
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Min[*1]
1.8
-40
-
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
3.6
85
-
V
Temperature range
TLXT
C
Rf
Internal feedback resistor
Oscillator frequency
6.5
32.768
1.5
2
MΩ
kHz
FLXT
-
-
6
6
ESR=35 kΩ, Gain = L1
ESR=70 kΩ, Gain = L2
ILXT
Current consumption
A
TsLXT
DuLXT
Vpp
Stable time
-
500
-
900
70
-
ms
%
Duty cycle
30
TBD
Peak-to-peak amplitude
500
mV
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-9 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Min
Typ
Max
Unit
Test Conditions
Equivalnet Series Resisotr(ESR)
-
35
70
kΩ
Crystal @32.768 kHz
Table 8.4-10 External 32.768 kHz Low Speed Crystal Characteristics
8.4.8.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20 pF
20 pF
without
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-5 Typical 32.768 kHz Crystal Application Circuit
Aug. 18, 2020
Page 117 of 140
Rev. 1.01
M031BT
8.4.9
External 32.768 kHz Low Speed Clock Input Signal Characteristics
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
fLXT
Parameter
External clock source frequency
Clock high time
Min[*1]
-
Typ
Max[*1]
Unit
kHz
ns
Test Conditions
32.768
-
-
-
tCHCX
tCLCX
450
450
-
-
Clock low time
ns
tCLCH
Clock rise time
Low (10%) to high level (90%)
rise time
-
-
-
-
50
50
ns
ns
tCHCL
Clock fall time
High (90%) to low level (10%) fall
time
DuE_LXT
Xin_VIH
Xin_VIL
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
LXT input pin input high voltage
LXT input pin input low voltage
0.3*VDD
V
External
clock source
X32_IN
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by design, not tested in production
Table 8.4-11 External 32.768 kHz Low Speed Clock Input Signal
Aug. 18, 2020
Page 118 of 140
Rev. 1.01
M031BT
8.4.10 PLL Characteristics
Symbol
fPLL_in
Parameter
PLL input clock
Min[*1]
3.2
50
Typ
Max[*1]
32
Unit
MHz
MHz
MHz
MHz
µs
Test Conditions
-
-
-
-
-
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
PLL multiplier output clock
PLL reference clock
96
0.8
200
-
8
PLL voltage controlled oscillator
PLL locking time
500
500
Jitter[*2]
Cycle-to-cycle Jitter
Power consumption
-
-
200
3.1
350
5
ps
IDD
f
mA
VDD =3.3V @ PLL_OUT = 96 MHz
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
Table 8.4-12 PLL Characteristics
Aug. 18, 2020
Page 119 of 140
Rev. 1.01
M031BT
8.4.11 I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
Test Conditions[*2]
-
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
= 3.3 V,
5.5
3
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
-
-
-
-
-
-
-
-
-
-
-
tf(IO)out
Output high (90%) to low level (10%) fall time
Output low (10%) to high level (90%) rise time
I/O maximum frequency
ns
8.5
4.5
5.5
3
tr(IO)out
ns
8.5
4.5
60
110
40
75
[*3]
fmax(IO)out
MHz
2.77
-
f(IO)out = 24 MHz
CL = 10 pF, V
= 3.3 V,
= 3.3 V,
DD
f(IO)out = 24 MHz
CL = 30 pF, V
1.19
0.69
-
-
[*4]
IDIO
I/O dynamic current consumption
mA
DD
f(IO)out = 6 MHz
CL = 10 pF, V
= 3.3 V,
DD
f(IO)out = 6 MHz
0.3
-
Note:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢕ
3. The maximum frequency is defined by ꢒꢓꢊꢔ ꢁꢂꢖꢂꢗꢂꢘꢉ ꢐꢉ ꢛꢂ.
ꢙ
ꢚ
4. The I/O dynamic current consumption is defined by ꢜꢝꢞꢟ ꢁ ꢠꢝꢝ ꢂꢗꢂꢒꢞꢟ ꢂꢗ ꢘꢡꢞꢟ ꢢꢂꢡꢣꢛ
Table 8.4-13 I/O AC Characteristics
Aug. 18, 2020
Page 120 of 140
Rev. 1.01
M031BT
8.5 Analog Characteristics
8.5.1 LDO
Symbol
VDD
Parameter
Power supply
Min
1.8
-
Typ
Max
3.6
-
Unit
V
Test Condition
-
1.8
-
VLDO
TA
Output voltage
Temperature
V
-40
85
°C
Note
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
8.5.2
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
POR reset voltage
Min
-
Typ
20
2
Max
Unit
Test Conditions
AVDD = 3.6V
[*1]
IPOR
30
µA
[*1]
ILVR
-
3.6
AVDD = 3.6V
AVDD = 3.6V
-
[*1]
IBOD
-
3
5.5
VPOR
VLVR
VBOD
1.35
1.6
1.8
2.3
-
1.5
1.7
2.0
2.5
200
16
1000
120
-
1.65
V
LVR reset voltage
1.8
BOD brown-out detect voltage
2.2
BODVL = 0
2.7
BODVL = 1
[*1]
TLVR_SU
LVR startup time
LVR respond time
BOD startup time
BOD respond time
VDD rise time rate
VDD fall time rate
-
-
-
-
-
-
-
-
-
µs
-
[*1]
TLVR_RE
-
-
[*1]
TBOD_SU
-
-
[*1]
TBOD_RE
-
-
[*1]
RVDDR
10
10
80
250
150
µs/V
POR Enabled
POR Enabled
LVR Enabled
BOD 2.0V Enabled
BOD 2.5V Enabled
[*1]
RVDDF
-
-
-
-
Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.5-1 Reset and Power Control Unit
Aug. 18, 2020
Page 121 of 140
Rev. 1.01
M031BT
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
Aug. 18, 2020
Page 122 of 140
Rev. 1.01
M031BT
8.5.3
12-bit SAR ADC
Min
Typ
Max
Unit
Symbol
TA
Parameter
Test Conditions
Temperature
-40
85
-
-
°C
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.8
1.8
0
3.6
V
V
V
V
VDD
DD
AVDD
VREF
-
-
ADC channel input voltage
Common-Mode Input Range
VCM
VREF/2
Full differential input
AVDD = VDD =VREF = 3.3 V
FADC = 34 MHz
[*1]
IADC
Operating current (AVDD + VREF current)
-
-
355
34
µA
TCONV = 17 * TADC
NR
Resolution
12
-
Bit
[*1]
FADC
ADC Clock frequency
4
MHz
1/TADC
TSMP
=
TSMP
Sampling Time
Conversion time
1
-
-
256
272
1/FADC ( EXTSMPT(ADC_ESMPCTL[7:0])
+ 1 ) * TADC
TCONV
17
1/FADC TCONV = TSMP + 16 * TADC
FSPS = FADC / TCONV
[*1]
FSPS
Sampling Rate
0.236
-
2
MSPS
EXTSMPT(ADC_ESMPCTL[7:0])
= 0
TEN
Enable to ready time
20
-2
-
-
-
μs
VREF = AVDD
,
+2
LSB
except TSSOP20 and TSSOP28
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
VREF = AVDD
-4
-1
+4
+2
+4
+4
+4
+4
+10
+4
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TSSOP20 and TSSOP28
VREF = AVDD
,
-
-
-
-
except TSSOP20 and TSSOP28
DNL[*1]
VREF = AVDD
-1
TSSOP20 and TSSOP28
VREF = AVDD
,
-4
except TSSOP20 and TSSOP28
[*1]
EG
VREF = AVDD
-10
-4
TSSOP20 and TSSOP28
VREF = AVDD
,
except TSSOP20 and TSSOP28
[*1]
EO
Offset error
T
VREF = AVDD
-4
TSSOP20 and TSSOP28
[*1]
EA
Absolute Error
VREF = AVDD,
-4
except TSSOP20 and TSSOP28
Aug. 18, 2020
Page 123 of 140
Rev. 1.01
ꢒ
ꢧꢝꢅ ꢂꢗꢂꢡꢞꢨ ꢂꢗ ꢩꢪ ꢛ
ꢘꢫꢨꢐꢕ
M031BT
Min
Typ
Max
Unit
Symbol
Parameter
Test Conditions
VREF = AVDD
TSSOP20 and TSSOP28
-8
+8
LSB
ENOB[*1]
SINAD[*1]
SNR[*1]
Effective number of bits
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
-
bits FADC = 34 MHz
AVDD = VDD =VREF = 3.3 V
Signal-to-noise and distortion ratio
Signal-to-noise ratio
-
Input Frequency = 20 kHz
TA = 25 °C
-
dB
THD[*1]
Total harmonic distortion
Internal Capacitance
-
2.9
-
[*1]
CIN
pF
kΩ
kΩ
[*1]
RIN
Internal Switch Resistance
External input impedance
2
[*1]
REX
-
50
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
ꢦ
ꢤꢌꢥ ꢁꢂ
ꢬꢂꢤꢞꢨ
VDD
EADC_CHx
RIN
REX
12-bit
Converter
VEX
CIN
CEX
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
Aug. 18, 2020
Page 124 of 140
Rev. 1.01
M031BT
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Aug. 18, 2020
Page 125 of 140
Rev. 1.01
M031BT
8.5.4
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Min
1.8
-40
-
Typ
-
Max Unit
Test Conditions
VDD = AVDD
Parameter
Analog supply voltage
Temperature
AVDD
3.6
85
45
V
°C
A
TA
-
IDD
Operating current
30
1/2 AVDD
AVDD -0.3
[*2]
VCM
Input common mode voltage range
0.35
[*2]
VDI
Differential input voltage sensitivity
Input offset voltage
Hysteresis window
DC voltage Gain
10
-
20
10
90
65
-
-
mV Hysteresis disable
mV Hysteresis disable,
[*2]
Voffset
20
[*2]
Vhys
40
45
-
140 mV
Av[*1]
75
400
4
dB
nS
uS
%
[*2]
Td
Propagation delay
Setup time
[*2]
TSetup
-
-
[*2]
ACRV
CRV output voltage
Unit resistor value
Setup time
-5
-
-
5
AVDD x (1/6+CRVCTL/24)
[*2]
RCRV
4.2
-
-
kΩ
[*2]
TSETUP_CRV
-
350
45
µS CRV output voltage settle to ±5%
[*2]
IDD_CRV
Operating current
-
30
A
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production
Table 8.5-2 ACMP Characteristics
Aug. 18, 2020
Page 126 of 140
Rev. 1.01
M031BT
8.5.5
RF Characteristics
8.5.5.1 Transmitter Characteristics
Tast condition: TA= 25 °C, RF_VDD = 3.3V, RF_VDDPA = 3.3V, VDD = 3.3 V and AVDD = 3.3 V.
Values
Symbol
Parameter
Unit
Condition
Min
-20
2.4
Typ
Max
8
POUT
RF Output Power
-
dBm
GHz
kHz
kHz
FOPERATING Operating Frequency
2.5
< ± 50
< ± 50
1 Mbps data rate
2 Mbps data rate
ΔF
FΔF
Δf1
Frequency Drift
kHz
/50µs
Frequency Drift Rate
< ± 20
1 Mbps & 2 Mbps data rates
225
450
185
370
80
260
500
275
550
kHz
kHz
kHz
kHz
%
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
Average Frequency Deviation
(data pattern = 111000…)
Instantaneous Deviation
(data pattern = 10101010…)
Δf2
Δf2 / Δf1
Deviation Ratio
80
%
Spectrum Mask with Adjacent
Channel Offset: ± 2 MHz
-20
-30
-20
-20
-30
dBc
dBc
dBc
dBc
dBc
1 Mbps data rate
1 Mbps data rate
2 Mbps data rate
2 Mbps data rate
2 Mbps data rate
Spectrum Mask with Adjacent
Channel Offset: ≥ 3 MHz
Spectrum Mask with Adjacent
Channel Offset: ± 4 MHz
Spectrum Mask with Adjacent
Channel Offset: ± 5 MHz
Spectrum Mask with Adjacent
Channel Offset: ± 6 MHz
Table 8.5-3 RF Transmitter Characteristics
Aug. 18, 2020
Page 127 of 140
Rev. 1.01
M031BT
8.5.5.2 Receiver Characteristics
Tast condition: TA= 25 °C, RF_VDD = 3.3V, RF_VDDPA = 3.3V, VDD = 3.3 V and AVDD = 3.3 V.
Values
Symbol
Parameter
Unit
Condition
Min
Typ
-94
-91
8
Max
dBm
dBm
dB
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
RF Sensitivity, NF = 6 dB, +1.2VDC
core supply
Carrier-to-Interference:
C/I CO-CHANNEL
C/I – 1 MHz
C/I + 1 MHz
C/I – 2 MHz
C/I + 2 MHz
C/I – 3 MHz
C/I + 3 MHz
C/I – 4 MHz
C/I + 4MHz
C/I – 6 MHz
C/I + 6 MHz
C/I IMAGE
Co-Channel Selectivity
9
dB
Carrier-to-Interference:
-4
dB
dB
1 Mbps data rate
1 Mbps data rate
- 1 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
-8.5
+ 1 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
-36
-2.5
-26
-8
dB
dB
dB
dB
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
- 2 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
+ 2 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
-40
-37
-35
-25
-39
-38
dB
dB
dB
dB
dB
dB
1 Mbps data rate
1 Mbps data rate
2 Mbps data rate
2 Mbps data rate
2 Mbps data rate
2 Mbps data rate
- 3 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
+ 3 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
- 4 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
+ 4 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
- 6 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
+ 6 MHz Adjacent Channel Selectivity
Carrier-to-Interference:
-26
-25
dB
dB
1 Mbps data rate
2 Mbps data rate
Image Channel Selectivity
Carrier-to-Interference:
-37
-38
-37
-25
-15
dB
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
C/I IMAGE1 MHz
Image
1
MHz Adjacent Channel
dB
Selectivity
dBm
dBm
dBm
IM
Intermodulation Interferer Level
Out-of-band Blocking: Interferer
OOB
Aug. 18, 2020
Page 128 of 140
Rev. 1.01
M031BT
Values
Typ
Symbol
Parameter
Unit
Condition
Min
Max
30 MHz ≤ f ≤ 2000 MHz
-16
-22
-25
-20
-21
-10
-10
-10
-10
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
1 Mbps data rate
2 Mbps data rate
30 MHz, 2000 MHz
OOB
Out-of-band Blocking: Interferer
2003 MHz ≤ f ≤ 2399 MHz
Out-of-band Blocking: Interferer
2484 MHz ≤ f ≤ 2997 MHz
Out-of-band Blocking: Interferer
2997 MHz ≤ f ≤ 6 GHz
2000 MHz, 2399 MHz
OOB
2484 MHz, 2997 MHz
OOB
2997 MHz, 6 GHz
OOB
Out-of-band Blocking: Interferer
6 GHz ≤ f ≤ 12.75 GHz
6 GHz, 12.75 GHz
Table 8.5-4 RF Receiver Characteristics
Aug. 18, 2020
Page 129 of 140
Rev. 1.01
M031BT
8.6
Communications Characteristics
8.6.1
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-1 I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-1 I2C Timing Diagram
Aug. 18, 2020
Page 130 of 140
Rev. 1.01
M031BT
8.6.2
USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
24
Unit
Test Conditions
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
24
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tDH
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
5
tV
Data output valid time
-
8.5
Note:
1. Guaranteed by design.
Table 8.6-2 USCI-SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-2 USCI-SPI Master Mode Timing Diagram
Aug. 18, 2020
Page 131 of 140
Rev. 1.01
M031BT
Symbol
FSPICLK
Parameter
Min[*1]
Typ
Max[*1] Unit
Test Conditions
-
-
-
7
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
SPI clock frequency
MHz
7
1/ TSPICLK
-
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
1
TSPICLK
+ 2ns
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSS
Slave select setup time
ns
1
TSPICLK
+ 3ns
-
-
-
1
tSH
tDS
tDH
Slave select hold time
-
ns
TSPICLK
Data input setup time
Data input hold time
2
4
-
-
-
-
-
-
ns
ns
-
65
70
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
ns
-
Note:
1. Guaranteed by design.
Table 8.6-3 USCI-SPI Slave Mode Characteristics
Aug. 18, 2020
Page 132 of 140
Rev. 1.01
M031BT
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-3 USCI-SPI Slave Mode Timing Diagram
Aug. 18, 2020
Page 133 of 140
Rev. 1.01
M031BT
8.6.3
USCI-I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-4 USCI-I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-4 USCI-I2C Timing Diagram
Aug. 18, 2020
Page 134 of 140
Rev. 1.01
M031BT
8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
TERASE
TPROG
IDD1
Parameter
Page erase time
Min
Typ
20
60
7
Max
Unit
ms
Test Condition
-
-
-
-
-
-
-
-
-
-
Program time
Read current
Program current
Erase current
µs
mA
mA
mA
IDD2
8
IDD3
12
NENDUR
Endurance
20,000
65
-
-
-
cycles[1]
year
TJ = -40°C~85°C
20 kcycle[2] TJ = 55°C
20 kcycle[2] TJ = 85°C
-
-
TRET
Data retention
10
year
Note:
1. Number of program/erase cycles.
2. Guaranteed by design.
Aug. 18, 2020
Page 135 of 140
Rev. 1.01
M031BT
9 PACKAGE DIMENSIONS
9.1 QFN 48-pin (5X5x0.9 mm Pitch:0.35 mm)
Aug. 18, 2020
Page 136 of 140
Rev. 1.01
M031BT
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
CAN
DAP
DES
ADC
EBI
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~32 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
38.4 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
Aug. 18, 2020
Page 137 of 140
Rev. 1.01
M031BT
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
Aug. 18, 2020
Page 138 of 140
Rev. 1.01
M031BT
11 REVISION HISTORY
Date
Revision
Description
2020.07.21
2020.08.18
1.00
Initial version.
1.01
Updated Multi-function Pin Diagram in section 4.1.2.1.
Aug. 18, 2020
Page 139 of 140
Rev. 1.01
M031BT
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Aug. 18, 2020
Page 140 of 140
Rev. 1.01
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