M031TE2AE [NUVOTON]
Arm® Cortex®-M 32-bit Microcontroller;
| 型号： | M031TE2AE |
| 厂家： | 
NUVOTON |
| 描述： | Arm® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总288页 (文件大小：4781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M031/M032
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M031/M032 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Sep. 29, 2020
Page 1 of 288
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M031/M032
TABLE OF CONTENTS
1 GENERAL DESCRIPTION ............................................................................13
2 FEATURES....................................................................................................14
2.1 M031/M032 Features.................................................................................................. 14
3 PARTS INFORMATION.................................................................................22
3.1 Package Type .............................................................................................................. 22
3.2 M031/M032 Series Selection Guide......................................................................... 23
3.2.1 M031 Base Series (M031Fx / M031Ex / M031Tx) ....................................................23
3.2.2 M031 Base Series (M031Lx)........................................................................................24
3.2.3 M031 Base Series (M031Sx)........................................................................................25
3.2.4 M031 Base Series (M031Kx)........................................................................................26
3.2.5 M032 USB Series (M032Fx / M032Ex / M032Tx) .....................................................27
3.2.6 M032 USB Series (M032Lx).........................................................................................28
3.2.7 M032 USB Series (M032Sx).........................................................................................29
3.2.8 M032 USB Series (M032Kx).........................................................................................30
3.2.9 Naming Rule ...................................................................................................................31
3.3 M031/M032 Series Feature Comparison Table...................................................... 32
4 PIN CONFIGURATION ..................................................................................33
4.1 Pin Configuration......................................................................................................... 33
4.1.1 M031 Series Pin Diagram .............................................................................................33
4.1.2 M031 Series Multi-function Pin Diagram ....................................................................39
4.1.3 M032 Series Pin Diagram ...........................................................................................101
4.1.4 M032 Series Multi-function Pin Diagram ..................................................................107
4.2 Pin Mapping ............................................................................................................... 156
4.3 Pin Function Description .......................................................................................... 161
5 BLOCK DIAGRAM.......................................................................................167
6 FUNCTIONAL DESCRIPTION.....................................................................168
6.1 Arm® Cortex®-M0 Core............................................................................................. 168
6.2 Clock Controller ......................................................................................................... 170
6.2.1 Overview........................................................................................................................170
6.2.2 Clock Generator............................................................................................................172
6.2.3 System Clock and SysTick Clock...............................................................................174
6.2.4 Peripherals Clock .........................................................................................................176
6.2.5 Power-down Mode Clock ............................................................................................176
6.2.6 Clock Output .................................................................................................................177
6.2.7 USB Clock Source........................................................................................................177
6.3 System Manager ....................................................................................................... 179
6.3.1 Overview........................................................................................................................179
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6.3.2 System Reset................................................................................................................179
6.3.3 System Power Distribution..........................................................................................185
6.3.4 Power Modes and Wake-up Sources........................................................................185
6.3.5 System Memory Map...................................................................................................189
6.3.6 SRAM Memory Organization......................................................................................191
6.3.7 SRAM Memory Organization with parity function....................................................191
6.3.8 Chip Bus Matrix ............................................................................................................193
6.3.9 IRC Auto Trim................................................................................................................193
6.3.10Register Lock Control ..................................................................................................194
6.3.11UART0_TXD/USCI0_DAT0 modulation with PWM.................................................194
6.3.12System Timer (SysTick)...............................................................................................195
6.3.13Nested Vectored Interrupt Controller (NVIC)............................................................196
6.4 Flash Memory Controller (FMC).............................................................................. 199
6.4.1 Overview........................................................................................................................199
6.5 General Purpose I/O (GPIO) ................................................................................... 200
6.5.1 Overview........................................................................................................................200
6.5.2 Features.........................................................................................................................200
6.6 PDMA Controller (PDMA)......................................................................................... 201
6.6.1 Overview........................................................................................................................201
6.6.2 Features.........................................................................................................................201
6.7 Timer Controller (TMR)............................................................................................. 202
6.7.1 Overview........................................................................................................................202
6.7.2 Features.........................................................................................................................202
6.8 Watchdog Timer (WDT)............................................................................................ 203
6.8.1 Overview........................................................................................................................203
6.8.2 Features.........................................................................................................................203
6.9 Window Watchdog Timer (WWDT)......................................................................... 204
6.9.1 Overview........................................................................................................................204
6.9.2 Features.........................................................................................................................204
6.10 Real Time Clock (RTC)....................................................................................... 205
6.10.1Overview........................................................................................................................205
6.10.2Features.........................................................................................................................205
6.11 Basic PWM Generator and Capture Timer (BPWM)...................................... 206
6.11.1Overview........................................................................................................................206
6.11.2Features.........................................................................................................................206
6.12 PWM Generator and Capture Timer (PWM) ................................................... 207
6.12.1Overview........................................................................................................................207
6.12.2Features.........................................................................................................................207
6.13 UART Interface Controller (UART) ................................................................... 209
6.13.1Overview........................................................................................................................209
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6.13.2Features.........................................................................................................................209
6.14 Serial Peripheral Interface (SPI) ....................................................................... 211
6.14.1Overview........................................................................................................................211
6.14.2Features.........................................................................................................................211
6.15 Quad Serial Peripheral Interface (QSPI).......................................................... 212
6.15.1Overview........................................................................................................................212
6.15.2Features.........................................................................................................................212
6.16 I2C Serial Interface Controller (I2C)................................................................... 213
6.16.1Overview........................................................................................................................213
6.16.2Features.........................................................................................................................213
6.17 USCI - Universal Serial Control Interface Controller (USCI)......................... 215
6.17.1Overview........................................................................................................................215
6.17.2Features.........................................................................................................................215
6.18 USCI – UART Mode............................................................................................ 216
6.18.1Overview........................................................................................................................216
6.18.2Features.........................................................................................................................216
6.19 USCI - SPI Mode................................................................................................. 217
6.19.1Overview........................................................................................................................217
6.19.2Features.........................................................................................................................217
6.20 USCI - I2C Mode .................................................................................................. 219
6.20.1Overview........................................................................................................................219
6.20.2Features.........................................................................................................................219
6.21 External Bus Interface (EBI) .............................................................................. 220
6.21.1Overview........................................................................................................................220
6.21.2Features.........................................................................................................................220
6.22 USB 2.0 Full-Speed Device Controller (USBD).............................................. 221
6.22.1Overview........................................................................................................................221
6.22.2Features.........................................................................................................................221
6.23 CRC Controller (CRC) ........................................................................................ 222
6.23.1Overview........................................................................................................................222
6.23.2Features.........................................................................................................................222
6.24 Hardware Divider (HDIV).................................................................................... 223
6.24.1Overview........................................................................................................................223
6.24.2Features.........................................................................................................................223
6.25 Analog-to-Digital Converter (ADC) ................................................................... 224
6.25.1Overview........................................................................................................................224
6.25.2Features.........................................................................................................................224
6.26 Analog Comparator Controller (ACMP)............................................................ 226
6.26.1Overview........................................................................................................................226
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6.26.2Features.........................................................................................................................226
6.27 Peripherals Interconnection ............................................................................... 227
6.27.1Overview........................................................................................................................227
6.27.2Peripherals Interconnect Matrix table........................................................................227
7 APPLICATION CIRCUIT..............................................................................228
7.1 Power Supply Scheme ............................................................................................. 228
7.2 Peripheral Application Scheme ............................................................................... 229
8 ELECTRICAL CHARACTERISTICS............................................................230
8.1 Absolute Maximum Ratings..................................................................................... 230
8.1.1 Voltage Characteristics................................................................................................230
8.1.2 Current Characteristics................................................................................................230
8.1.3 Thermal Characteristics...............................................................................................232
8.1.4 EMC Characteristics ....................................................................................................233
8.1.5 Package Moisture Sensitivity(MSL)...........................................................................234
8.1.6 Soldering Profile ...........................................................................................................235
8.2 General Operating Conditions................................................................................. 236
8.3 DC Electrical Characteristics................................................................................... 237
8.3.1 Supply Current Characteristics for M03xB/M03xC/M03xD/M03xE.......................237
8.3.2 Supply Current Characteristics for M03xG/M03xI ...................................................240
8.3.3 On-Chip Peripheral Current Consumption................................................................243
8.3.4 Wakeup Time from Low-Power Modes .....................................................................245
8.3.5 I/O Current Injection Characteristics..........................................................................246
8.3.6 I/O DC Characteristics.................................................................................................246
8.4 AC Electrical Characteristics ................................................................................... 248
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC).................................................248
8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................251
8.4.3 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
254
8.4.4 External 4~32 MHz High Speed Clock Input Signal Characteristics ....................256
8.4.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
257
8.4.6 External 32.768 kHz Low Speed Clock Input Signal Characteristics ...................258
8.4.7 PLL Characteristics ......................................................................................................259
8.4.8 I/O AC Characteristics .................................................................................................260
8.5 Analog Characteristics.............................................................................................. 261
8.5.1 LDO ................................................................................................................................261
8.5.2 Reset and Power Control Block Characteristics......................................................261
8.5.3 12-bit SAR ADC............................................................................................................263
8.5.4 Analog Comparator Controller (ACMP).....................................................................266
8.6 Communications Characteristics ............................................................................ 267
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8.6.1 QSPI/SPI Dynamic Characteristics............................................................................267
8.6.2 SPI - I2S Dynamic Characteristics .............................................................................270
8.6.3 I2C Dynamic Characteristics .......................................................................................272
8.6.4 USCI - SPI Dynamic Characteristics .........................................................................273
8.6.5 USCI - I2C Dynamic Characteristics ..........................................................................276
8.6.6 USB Characteristics.....................................................................................................277
8.7 Flash DC Electrical Characteristics ........................................................................ 278
9 PACKAGE DIMENSIONS............................................................................279
9.1 TSSOP 20 (4.4x6.5x0.9 mm)................................................................................... 279
9.2 TSSOP 28 (4.4x9.7x1.0 mm)................................................................................... 280
9.3 QFN 33L (4X4x0.8 mm Pitch:0.40 mm)................................................................. 281
9.4 LQFP 48L (7x7x1.4 mm Footprint 2.0mm)............................................................ 282
9.5 LQFP 64L (7x7x1.4 mm Footprint 2.0 mm)........................................................... 283
9.6 LQFP 128L (14x14x1.4 mm Footprint 2.0 mm) .................................................... 284
10ABBREVIATIONS........................................................................................285
10.1 Abbreviations........................................................................................................ 285
11REVISION HISTORY ...................................................................................287
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LIST OF FIGURES
Figure 4.1-1 M031 Series TSSOP 20-pin Diagram........................................................................ 33
Figure 4.1-2 M031 Series TSSOP 28-pin Diagram........................................................................ 34
Figure 4.1-3 M031 Series QFN 33-pin Diagram ............................................................................ 35
Figure 4.1-4 M031 Series LQFP 48-pin Diagram .......................................................................... 36
Figure 4.1-5 M031 Series LQFP 64-pin Diagram .......................................................................... 37
Figure 4.1-6 M031 Series LQFP 128-pin Diagram ........................................................................ 38
Figure 4.1-7 M031FB0AE Multi-function Pin Diagram................................................................... 39
Figure 4.1-8 M031FC1AE Multi-function Pin Diagram................................................................... 40
Figure 4.1-9 M031EB0AE Multi-function Pin Diagram................................................................... 41
Figure 4.1-10 M031EC1AE Multi-function Pin Diagram ................................................................ 42
Figure 4.1-11 M031TB0AE Multi-function Pin Diagram................................................................. 44
Figure 4.1-12 M031TC1AE Multi-function Pin Diagram................................................................. 46
Figure 4.1-13 M031TD2AE Multi-function Pin Diagram................................................................. 48
Figure 4.1-14 M031TE3AE Multi-function Pin Diagram................................................................. 50
Figure 4.1-15 M031LC2AE Multi-function Pin Diagram................................................................. 52
Figure 4.1-16 M031LD2AE Multi-function Pin Diagram................................................................. 55
Figure 4.1-17 M031LE3AE Multi-function Pin Diagram ................................................................. 58
Figure 4.1-18 M031LG6AE Multi-function Pin Diagram................................................................. 61
Figure 4.1-19 M031LG8AE Multi-function Pin Diagram................................................................. 64
Figure 4.1-20 M031SC2AE Multi-function Pin Diagram ................................................................ 67
Figure 4.1-21 M031SD2AE Multi-function Pin Diagram ................................................................ 70
Figure 4.1-22 M031SE3AE Multi-function Pin Diagram................................................................. 73
Figure 4.1-23 M031SG6AE Multi-function Pin Diagram ................................................................ 76
Figure 4.1-24 M031SG8AE Multi-function Pin Diagram ................................................................ 79
Figure 4.1-25 M031SIAAE Multi-function Pin Diagram.................................................................. 82
Figure 4.1-26 M031KG6AE Multi-function Pin Diagram ................................................................ 86
Figure 4.1-27 M031KG8AE Multi-function Pin Diagram ................................................................ 91
Figure 4.1-28 M031KIAAE Multi-function Pin Diagram.................................................................. 96
Figure 4.1-29 M032 Series TSSOP 20-pin Diagram.................................................................... 101
Figure 4.1-30 M032 Series TSSOP 28-pin Diagram.................................................................... 102
Figure 4.1-31 M032 Series QFN 33-pin Diagram ........................................................................ 103
Figure 4.1-32 M032 Series LQFP 48-pin Diagram ...................................................................... 104
Figure 4.1-33 M032 Series LQFP 64-pin Diagram ...................................................................... 105
Figure 4.1-34 M032 Series LQFP 128-pin Diagram .................................................................... 106
Figure 4.1-35 M032FC1AE Multi-function Pin Diagram............................................................... 107
Figure 4.1-36 M032EC1AE Multi-function Pin Diagram .............................................................. 108
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Figure 4.1-37 M032TC1AE Multi-function Pin Diagram............................................................... 110
Figure 4.1-38 M032TD2AE Multi-function Pin Diagram............................................................... 112
Figure 4.1-39 M032LC2AE Multi-function Pin Diagram............................................................... 114
Figure 4.1-40 M032LD2AE Multi-function Pin Diagram............................................................... 117
Figure 4.1-41 M032LE3AE Multi-function Pin Diagram ............................................................... 120
Figure 4.1-42 M032LG6AE Multi-function Pin Diagram............................................................... 123
Figure 4.1-43 M032LG8AE Multi-function Pin Diagram............................................................... 126
Figure 4.1-44 M032SE3AE Multi-function Pin Diagram............................................................... 129
Figure 4.1-45 M032SG6AE Multi-function Pin Diagram .............................................................. 132
Figure 4.1-46 M032SG8AE Multi-function Pin Diagram .............................................................. 135
Figure 4.1-47 M032SIAAE Multi-function Pin Diagram................................................................ 138
Figure 4.1-48 M032KG6AE Multi-function Pin Diagram .............................................................. 141
Figure 4.1-49 M032KG8AE Multi-function Pin Diagram .............................................................. 146
Figure 4.1-50 M032KIAAE Multi-function Pin Diagram................................................................ 151
Figure 5-1 NuMicro® M031/M032 Block Diagram........................................................................ 167
Figure 6-1 Functional Block Diagram........................................................................................... 168
Figure 6.2-1 Clock Generator Global View Diagram (1/2)........................................................... 171
Figure 6.2-2 Clock Generator Global View Diagram (2/2)........................................................... 172
Figure 6.2-3 Clock Generator Block Diagram.............................................................................. 173
Figure 6.2-4 System Clock Block Diagram .................................................................................. 174
Figure 6.2-5 HXT Stop Protect Procedure................................................................................... 175
Figure 6.2-6 LXT Stop Protect Procedure.................................................................................... 176
Figure 6.2-7 SysTick Clock Control Block Diagram..................................................................... 176
Figure 6.2-8 Clock Output Block Diagram ................................................................................... 177
Figure 6.2-9 USBD Clock Source ................................................................................................ 178
Figure 6.3-1 System Reset Sources ............................................................................................ 180
Figure 6.3-2 nRESET Reset Waveform....................................................................................... 182
Figure 6.3-3 Power-on Reset (POR) Waveform .......................................................................... 182
Figure 6.3-4 Low Voltage Reset (LVR) Waveform....................................................................... 183
Figure 6.3-5 Brown-out Detector (BOD) Waveform..................................................................... 184
Figure 6.3-6 NuMicro® M031 Power Distribution Diagram........................................................... 185
Figure 6.3-7 Power Mode State Machine .................................................................................... 187
Figure 6.3-8 SRAM Memory Organization................................................................................... 191
Figure 6.3-9 NuMicro® M031 Bus Matrix Diagram....................................................................... 193
Figure 6.19-1 SPI Master Mode Application Block Diagram........................................................ 217
Figure 6.19-2 SPI Slave Mode Application Block Diagram.......................................................... 217
Figure 6.20-1 I2C Bus Timing....................................................................................................... 219
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Figure 8.1-1 Soldering Profile from J-STD-020C......................................................................... 235
Figure 8.4-1 HIRC vs. Temperature............................................................................................. 250
Figure 8.4-2 LIRC vs. Temperature ............................................................................................. 253
Figure 8.4-2 Typical Crystal Application Circuit ........................................................................... 255
Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit........................................................ 257
Figure 8.5-1 Power Ramp Up/Down Condition............................................................................ 262
Figure 8.6-1 QSPI/SPI Master Mode Timing Diagram................................................................. 267
Figure 8.6-2 QSPI/SPI Slave Mode Timing Diagram................................................................... 269
Figure 8.6-3 I2S Master Mode Timing Diagram ........................................................................... 270
Figure 8.6-4 I2S Slave Mode Timing Diagram ............................................................................. 271
Figure 8.6-5 I2C Timing Diagram ................................................................................................. 272
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram................................................................. 273
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram................................................................... 275
Figure 8.6-8 USCI-I2C Timing Diagram........................................................................................ 276
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List of Tables
Table 1-1 NuMicro® M031/M032 Series Key Features Support Table .......................................... 13
Table 4.1-1 M031FB0AE Multi-function Pin Table......................................................................... 39
Table 4.1-2 M031FC1AE Multi-function Pin Table......................................................................... 40
Table 4.1-3 M031EB0AE Multi-function Pin Table......................................................................... 42
Table 4.1-4 M031EC1AE Multi-function Pin Table ........................................................................ 43
Table 4.1-5 M031TB0AE Multi-function Pin Table......................................................................... 45
Table 4.1-6 M031TC1AE Multi-function Pin Table......................................................................... 47
Table 4.1-7 M031TD2AE Multi-function Pin Table......................................................................... 49
Table 4.1-8 M031TE3AE Multi-function Pin Table......................................................................... 51
Table 4.1-9 M031LC2AE Multi-function Pin Table......................................................................... 54
Table 4.1-10 M031LD2AE Multi-function Pin Table....................................................................... 57
Table 4.1-11 M031LE3AE Multi-function Pin Table....................................................................... 60
Table 4.1-12 M031LG6AE Multi-function Pin Table....................................................................... 63
Table 4.1-13 M031LG8AE Multi-function Pin Table....................................................................... 66
Table 4.1-14 M031SC2AE Multi-function Pin Table ...................................................................... 69
Table 4.1-15 M031SD2AE Multi-function Pin Table ...................................................................... 72
Table 4.1-16 M031SE3AE Multi-function Pin Table....................................................................... 75
Table 4.1-17 M031SG6AE Multi-function Pin Table ...................................................................... 78
Table 4.1-18 M031SG8AE Multi-function Pin Table ...................................................................... 81
Table 4.1-19 M031SIAAE Multi-function Pin Table........................................................................ 84
Table 4.1-20 M031KG6AE Multi-function Pin Table ...................................................................... 90
Table 4.1-21 M031KG8AE Multi-function Pin Table ...................................................................... 95
Table 4.1-22 M031KIAAE Multi-function Pin Table...................................................................... 100
Table 4.1-23 M032FC1AE Multi-function Pin Table..................................................................... 107
Table 4.1-24 M032EC1AE Multi-function Pin Table .................................................................... 109
Table 4.1-25 M032TC1AE Multi-function Pin Table..................................................................... 111
Table 4.1-26 M032TD2AE Multi-function Pin Table..................................................................... 113
Table 4.1-27 M032LC2AE Multi-function Pin Table..................................................................... 116
Table 4.1-28 M032LD2AE Multi-function Pin Table..................................................................... 119
Table 4.1-29 M032LE3AE Multi-function Pin Table..................................................................... 122
Table 4.1-30 M032LG6AE Multi-function Pin Table..................................................................... 125
Table 4.1-31 M032LG8AE Multi-function Pin Table..................................................................... 128
Table 4.1-32 M032SE2AE Multi-function Pin Table..................................................................... 131
Table 4.1-33 M032SG6AE Multi-function Pin Table .................................................................... 134
Table 4.1-34 M032SG8AE Multi-function Pin Table .................................................................... 137
Table 4.1-35 M032SIAAE Multi-function Pin Table...................................................................... 140
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Table 4.1-36 M032KG6AE Multi-function Pin Table .................................................................... 145
Table 4.1-37 M032KG8AE Multi-function Pin Table .................................................................... 150
Table 4.1-38 M032KIAAE Multi-function Pin Table...................................................................... 155
Table 6.3-1 Reset Value of Registers.......................................................................................... 182
Table 6.3-2 Power Mode Table.................................................................................................... 186
Table 6.3-3 Power Mode Difference Table .................................................................................. 186
Table 6.3-4 Power Mode Difference Table .................................................................................. 186
Table 6.3-5 Clocks in Power Modes ............................................................................................ 188
Table 6.3-6 Condition of Entering Power-down Mode Again....................................................... 189
Table 6.3-7 Address Space Assignments for On-Chip Controllers.............................................. 190
Table 6.3-8 Exception Model ....................................................................................................... 197
Table 6.3-9 Interrupt Number Table............................................................................................. 198
Table 6.13-1 NuMicro® M031/M032 Series UART Features ....................................................... 210
Table 6.16-1 I2C Feature Comparison Table at Different Chip.................................................... 214
Table 6.21-1 EBI Features Comparison Table ............................................................................ 220
Table 6.25-1 ADC Features Comparison Table........................................................................... 225
Table 6.26-1 Calibration Function Features Comparison Table at Different Chip....................... 226
Table 6.27-1 Peripherals Interconnect Matrix table ..................................................................... 227
Table 8.1-1 Voltage Characteristics............................................................................................. 230
Table 8.1-2 Current Characteristics ............................................................................................. 231
Table 8.1-3 Thermal Characteristics............................................................................................ 232
Table 8.1-4 EMC Characteristics for M03xB/M03xC/M03xD/M03xE .......................................... 233
Table 8.1-5 EMC Characteristics for M03xG/M03xI .................................................................... 234
Table 8.1-6 Package Moisture Sensitivity (MSL)......................................................................... 234
Table 8.1-7 Soldering Profile........................................................................................................ 235
Table 8.2-1 General Operating Conditions .................................................................................. 236
Table 8.3-1 Current Consumption in Normal Run Mode ............................................................. 237
Table 8.3-2 Current Consumption in Idle Mode........................................................................... 238
Table 8.3-3 Chip Current Consumption in Power-down Mode .................................................... 239
Table 8.3-4 Current Consumption in Normal Run Mode ............................................................. 240
Table 8.3-5 Current Consumption in Idle Mode........................................................................... 241
Table 8.3-6 Chip Current Consumption in Power-down Mode .................................................... 242
Table 8.3-7 Peripheral Current Consumption .............................................................................. 244
Table 8.3-8 Low-power Mode Wakeup Timings .......................................................................... 245
Table 8.3-9 I/O Current Injection Characteristics......................................................................... 246
Table 8.3-10 I/O Input Characteristics ......................................................................................... 246
Table 8.3-11 I/O Output Characteristics ...................................................................................... 247
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Table 8.3-12 nRESET Input Characteristics................................................................................ 247
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics.......................... 248
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics .......................... 251
Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator ........................................ 254
Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics .......................................... 255
Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal ................................................. 256
Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator........................................ 257
Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics ......................................... 257
Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal ................................................ 258
Table 8.4-9 PLL Characteristics................................................................................................... 259
Table 8.4-10 I/O AC Characteristics ............................................................................................ 260
Table 8.5-1 Reset and Power Control Unit .................................................................................. 261
Table 8.5-2 ACMP Characteristics............................................................................................... 266
Table 8.6-1 QSPI/SPI Master Mode Characteristics.................................................................... 267
Table 8.6-2 QSPI/SPI Slave Mode Characteristics...................................................................... 268
Table 8.6-3 I2S Characteristics .................................................................................................... 270
Table 8.6-4 I2C Characteristics .................................................................................................... 272
Table 8.6-5 USCI-SPI Master Mode Characteristics ................................................................... 273
Table 8.6-6 USCI-SPI Slave Mode Characteristics ..................................................................... 274
Table 8.6-7 USCI-I2C Characteristics .......................................................................................... 276
Table 8.6-8 USB Full-Speed Characteristics ............................................................................... 277
Table 8.6-9 USB Full-Speed PHY Characteristics....................................................................... 277
Table 10.1-1 List of Abbreviations................................................................................................ 286
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1
GENERAL DESCRIPTION
The NuMicro® M031/M032 series 32-bit microcontroller is based on Arm® Cortex® -M0 core with 32-bit
hardware multiplier/divider. It features 1.8 ~ 3.6 V operating voltage, 5 V I/O tolerant, and runs up to
48/72 MHz within -40°C ~105°C.
The M031/M032 series provides a solution for the applications that need 1.8 V low-voltage interface
connection with enhanced fast 2 MSPS conversion rate 12-bit ADC, comparators and up-to 24-ch
96/144 MHz PWM control. It supports a fast and precise data conversion for the voltage, current, and
sensor data, then fast response control to the external device. Additionally, the M031/M032 series also
provides plenty of peripherals including Universal Serial Control Interface(USCI) that can be set as
UART/SPI/I2C flexibly, up to 10 sets of UART, 4 sets of SPI, 4 sets of I2C, and 1-wire UART interface
for data communication between master and slave devices.
The M031/M032 series provides Flash size from 16 Kbytes to 512 Kbytes, SRAM size from 2 Kbytes
to 96 Kbytes. Supported packages from small form factor TSSOP 20-pin, TSSOP 28-pin, QFN 33-pin,
LQFP 48-pin to LQFP 64-pin and LQFP 128-pin with pin-compatible for different part numbers makes
the system design and parts change easily.
Part Numbers with the M032 series are all based on the M031 series and enhanced with the crystal-
less USB 2.0 full-speed device feature for USB related applications.
For the development, Nuvoton provides the NuMaker-PFM evaluation board and Nuvoton Nu-Link
debugger. The 3rd Party IDE such as Keil® MDK, IAR EWArm, Eclippse IDE with GNU GCC compilers
are also supported.
SPI/
Product Line
UART I2C
QSPI USCI Timer PWM RTC PDMA EBI ADC ACMP Divider USBD IEC60730
I2S
M031/M032
8
2
1
1
2
4
24
1
9
1
16
2
1
√
√
Table 1-1 NuMicro® M031/M032 Series Key Features Support Table
The NuMicro® M031/M032 series is suitable for a wide range of applications such as:
Laser Distance Meter
Air Detector/Cleaner
Mobile LCD Panel Controller
IoT Sensing Device
HMI Controller
Micro Printer
Gaming Keyboard and Mouse
WPC Wireless Charger
Sep. 29, 2020
Page 13 of 288
Rev 2.02
M031/M032
2 FEATURES
2.1 M031/M032 Features
Core and System
Arm® Cortex® -M0 processor, running up to 72 MHz
– 72 MHz at 2.0V-3.6V
– 48 MHz at 1.8V-3.6V
Arm® Cortex® -M0
Built-in Nested Vectored Interrupt Controller (NVIC)
24-bit system tick timer
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Two-level BOD with brown-out interrupt and reset option.
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
(2.5V/2.0V)
LVR with 1.7V threshold voltage level.
96-bit Unique ID (UID).
Security
128-bit Unique Customer ID (UCID).
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit H/W Divider(HDIV)
32-bit quotient and 32-bit remainder outputs (16-bit remainder with
sign extends to 32-bit)
Memories
Dual bank 512 KB on-chip Application ROM (APROM) for Over-
The-Air (OTA) upgrade.
Single bank up to 256 KB on-chip Application ROM (APROM).
Up to 8 KB on-chip Flash for user-defined loader (LDROM)
Up to 2048 bytes execution-only Security Protection ROM
(SPROM)
Flash
All on-chip Flash support 512 bytes or 2048 bytes page erase
Fast Flash programming verification with CRC-32 checksum
calculation
On-chip Flash programming with In-Chip Programming (ICP), In-
System Programming (ISP) and In-Application Programming (IAP)
capabilities
2-wired ICP Flash updating through SWD/ICE interface
Up to 96 KB on-chip SRAM
SRAM
– 32 KB SRAM located in bank 0 that supports hardware parity
check and retenion mode
Sep. 29, 2020
Page 14 of 288
Rev 2.02
M031/M032
– 32/32 KB SRAM located in bank 1 and bank 2
Byte-, half-word- and word-access
PDMA operation
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
Programmable initial value and seed value
Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC)
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
Up to 9 independent and configurable channels for automatic data
transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using Scatter-
Gather Transfer mode
Peripheral DMA (PDMA)
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
4~32 MHz High-speed eXternal crystal oscillator (HXT) for precise
timing operation
32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC
External Clock Source
function and low-power system operation
Supports clock failure detection for external crystal oscillators and
exception generatation (NMI)
48 MHz High-speed Internal RC oscillator (HIRC) dedicated for
crystal-less USB.
38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
Internal Clock Source
timer and wakeup operation
Up to 144 MHz on-chip PLL, sourced from HIRC or HXT, allows
CPU operation up to the maximim CPU frequency without the need
for a high-frequency crystal
The RTC clock source includes Low-speed external crystal
oscillator (LXT)
Real-Time Clock (RTC)
Able to wake up CPU from idle or power-down mode
Supports ±5ppm within 5 seconds software clock accuracy
compensation
Sep. 29, 2020
Page 15 of 288
Rev 2.02
M031/M032
Supports Alarm registers (second, minute, hour, day, month, year)
Supports RTC Time Tick and Alarm Match interrupt
Automatic leap year recognition
Supports 1 Hz clock output for calibration
Timers
Up to 4 sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Supports event counting function to count the event from external
32-bit Timer
pins
Supports external capture pin for interval measurement and
resetting 24-bit up counter
Supports chip wake-up function, if a timer interrupt signal is
generated
Up to two PWM modules, each module provides three 16-bit
counter and 6 output channels.
Up to 12 independent input capture channels with 16-bit resolution
counter
Supports dead time with maximum divided 12-bit prescale
Up, down or up-down PWM counter type
PWM (PWM)
Supports complementary mode for 3 complementary paired PWM
output channels
Counter synchronous start function
Brake function with auto recovery mechanism
Mask function and tri-state output for each PWM channel
Able to trigger ADC to start conversion
Two 16-bit counters with 12-bit clock prescale for twelve 144 MHz
PWM output channels.
Up to 6 independent input capture channels with 16-bit resolution
counter
Basic PWM (BPWM)
Up, down or up-down PWM counter type
Counter synchronous start function
Mask function and tri-state output for each PWM channel
Able to trigger ADC to start conversion
20-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection),
HCLK/2048 and LXT with 9 selectable time-out period
Watchdog
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Supports four WDT reset delay periods, including 1026, 130, 18 or
Sep. 29, 2020
Page 16 of 288
Rev 2.02
M031/M032
3 WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset.
Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
counter with 11-bit prescale
Window Watchdog
Suspended in Idle/Power-down mode
Analog Interfaces
Analog input voltage range: 0 ~ AVDD
One 12-bit, 2 MSPS SAR ADC with up to 16 single-ended input
channels or 8 differential input pairs; 10-bit accuracy is guaranteed.
Internal channels for band-gap VBG input.
Supports external VREF pin.
Supports calibration capability.
Four operation modes: Single mode, Burst mode, Single-cycle Scan
mode and Continuous Scan mode.
ADC
Analog-to-Digital conversion can be triggered by software enable
(ADST), external pin (STADC), Timer 0~3 overflow pulse trigger,
PWM trigger or BPWM trigger.
Each conversion result is held in data register of each channel with
valid and overrun indicators.
Supports conversion result monitor by compare mode function.
Configurable ADC external sampling time.
PDMA operation.
Supports floating detect function.
Two Analog Comparators
Supports four multiplexed I/O pins at positive input
Supports I/O pins, band-gap, and 16-level Voltage divider from
AVDD or VREF at negative input
Supports wake up from Power-down by interrupt
Analog Comparator
(ACMP)
Supports triggers for brake events and cycle-by-cycle control for
PWM
Supports window compare mode and window latch mode
Supports hysteresis function
Supports calibration function
Communication Interfaces
Low-power UARTs with up to 7.2 MHz baud rate.
Auto-Baud Rate measurement and baud rate compensation
Low-power UART
function.
Supports low power UART (LPUART): baud rate clock from LXT
(32.768 kHz) with 9600bps in Power-down mode even system clock
Sep. 29, 2020
Page 17 of 288
Rev 2.02
M031/M032
is stopped.
16-byte FIFOs with programmable level trigger
Auto flow control (nCTS and nRTS)
Supports IrDA (SIR) function
Supports RS-485 9-bit mode and direction control
Supports nCTS, incoming data, Received Data FIFO reached
threshold and RS-485 Address Match (AAD mode) wake-up
function in idle mode.
Supports hardware or software enables to program nRTS pin to
control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and receive/transmit
FIFO overflow detection function
PDMA operation.
Supports Single-wire function mode.
Three sets of I2C devices with Master/Slave mode.
Supports Standard mode (100 kbps), Fast mode (400 kbps), Fast
mode plus (1 Mbps)
Supports 7 bits mode
Programmable clocks allowing for versatile rate control
I2C
Supports multiple address recognition (four slave address with
mask option)
Supports multi-address power-down wake-up function
PDMA operation
I2C Port0 supports SMBus and PMBus
SPI Quad controller with Master/Slave mode.
Up to 24 MHz in Master mode and up to 16 MHz in Slave mode at
1.8V~3.6V system voltage.
Supports Dual and Quad I/O Transfer mode.
Supports one data channel half-duplex transfer.
Supports receive-only mode.
Configurable bit length of a transfer word from 8 to 32-bit.
Provides separate 8-level depth transmit and receive FIFO buffers.
Supports MSB first or LSB first transfer sequence.
Supports the byte reorder function.
Quad SPI
Supports Byte or Word Suspend mode.
Supports 3-wired, no slave select signal, bi-direction interface.
PDMA operation.
Sep. 29, 2020
Page 18 of 288
Rev 2.02
M031/M032
Supports 2-bit Transfer mode.
SPI/I2S controllers with Master/Slave mode.
SPI
Up to 24 MHz in Master mode and up to 16 MHz in Slave mode at
1.8V~3.6V system voltage.
Configurable bit length of a transfer word from 8 to 32-bit.
Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and
receive FIFO buffers.
MSB first or LSB first transfer sequence.
Byte reorder function.
Supports Byte or Word Suspend mode.
Supports one data channel half-duplex transfer.
Supports receive-only mode.
PDMA operation.
SPI/I2S
I2S
Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit
audio data sizes.
Provides separate 4-level depth transmit and receive FIFO buffers.
Supports PCM mode A, PCM mode B, I2S and MSB justified data
format.
PDMA operation.
Generates interrupt requests when buffer levels cross as
programmable boundary
Two sets of USCI, configured as UART, SPI or I2C function.
Supports single byte TX and RX buffer mode
UART
Supports one transmit buffer and two receive buffers for data
payload.
Supports hardware auto flow control function and programmable
flow control trigger level.
9-bit Data Transfer.
Baud rate detection by built-in capture event of baud rate generator.
Universal Serial Control
Interface (USCI)
Supports wake-up function.
PDMA operation.
SPI
Supports Master or Slave mode operation.
Supports one transmit buffer and two receive buffer for data
payload.
Configurable bit length of a transfer word from 4 to 16-bit.
Supports MSB first or LSB first transfer sequence.
Supports Word Suspend function.
Sep. 29, 2020
Page 19 of 288
Rev 2.02
M031/M032
Supports 3-wire, no slave select signal, bi-direction interface.
Supports wake-up function: input slave select transition.
PDMA operation.
Supports one data channel half-duplex transfer.
I2C
Supports master and slave device capability.
Supports one transmit buffer and two receive buffer for data
payload.
Communication in standard mode (100 kbps), fast mode (up to 400
kbps), and Fast mode plus (1 Mbps).
Supports 7-bit mode (10-bit mode not supported).
Supports 10-bit bus time out capability.
Supports bus monitor mode.
Supports power-down wake-up by data toggle or address match.
Supports multiple address recognition.
Supports device address flag.
Programmable setup/hold time.
Supports up to two memory banks with individual adjustment of
timing parameter.
Each bank supports dedicated external chip select pin with polarity
control and up to 1 MB addressing space.
8-/16-bit data width.
Supports byte write in 16-bit data width mode.
External Bus Interface
(EBI)
Configurable idle cycle for different access condition: Idle of Write
command finish (W2X) and Idle of Read-to-Read (R2R).
Supports Address/Data multiplexed mode.
Supports address bus and data bus separate mode.
Supports LCD interface i80 mode.
PDMA operation.
Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode.
Configured as interrupt source with edge/level trigger setting.
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional
I/O mode.
GPIO
Supports 5V-tolerance function except analog IO (PA.10, PA.11,
PB.0~PB.15, PF.2~PF.5).
Enabling the pin interrupt function will also enable the wake-up
function.
Input schmitt trigger function.
Advanced Connectivity
Sep. 29, 2020
Page 20 of 288
Rev 2.02
M031/M032
Compliant with USB Revision 2.0 Specification.
Supports suspend function when no bus activity existing for 3 ms.
8 configurable endpoints for configurable Isochronous, Bulk,
Interrupt and Control transfer types.
USB 2.0 Full Speed with
on-chip
512 bytes configurable RAM for endpoint buffer.
Remote wake-up capability.
transceiver
Supports Crystal-less function
Start of Frame (SOF) locked clock pulse generation
USB 2.0 link power management.
Sep. 29, 2020
Page 21 of 288
Rev 2.02
M031/M032
3 PARTS INFORMATION
3.1 Package Type
Part No.
M031xB
TSSOP20
TSSOP28
QFN33
LQFP48
LQFP64
LQFP128
M031FB0AE
M031EB0AE
M031TB0AE
M031FC1AE
M031EC1AE
M031TC1AE
M031TD2AE
M031LC2AE
M031LD2AE
M031SC2AE
M031SD2AE
M031xC
M031xD
M031TE3AE
M031LE3AE
M031SE3AE
M031xE
M031LG6AE
M031LG8AE
M031SG6AE
M031SG8AE
M031KG6AE
M031KG8AE
M031xG
M031xI
M031SIAAE
M031KIAAE
M032FC1AE
M032EC1AE
M032TC1AE
M032TD2AE
M032LC2AE
M032LD2AE
M032xC
M032xD
M032LE3AE
M032SE3AE
M032xE
M032LG6AE
M032LG8AE
M032SG6AE
M032SG8AE
M032KG6AE
M032KG8AE
M032xG
M032xI
M032SIAAE
M032KIAAE
Sep. 29, 2020
Page 22 of 288
Rev 2.02
M031/M032
3.2 M031/M032 Series Selection Guide
3.2.1 M031 Base Series (M031Fx / M031Ex / M031Tx)
M031
Part Number
FB0AE
FC1AE
EB0AE
EC1AE
TB0AE
TC1AE
TD2AE
TE3AE
128
16
Flash (KB)
16
2
32
4
16
2
32
4
16
2
32
4
64
8
SRAM (KB)
LDROM (KB)
2
2
2
2
2
2
2
4
SPROM (Bytes)
512
48
System Frequency (MHz)
PLL (MHz)
I/O
-
-
-
-
-
-
96
27
96
27
15
15
23
23
27
27
32-bit Timer
2
-
4
-
2
-
4
-
2
-
4
-
4
1
4
1
USCI
UART
SPI/I2S
QSPI
3
1
-
I²C/SMBus
USB FS
PWM
2/0
-
6
-
6
2
6
-
6
2
6
-
6
2
12
5
12
5
BPWM
PDMA
EBI
-
-
HDIV
√
√
-
CRC
IEC-60730
HXT
√
LXT
-
-
-
-
-
-
√
√
√
RTC
-
Analog Comparator
12-bit SAR ADC
-
-
-
-
-
2
2
7
7
9
9
10
10
10
10
Package TSSOP20 TSSOP20 TSSOP28 TSSOP28
QFN33
QFN33
QFN33
QFN33
Sep. 29, 2020
Page 23 of 288
Rev 2.02
M031/M032
3.2.2
M031 Base Series (M031Lx)
M031
Part Number
LC2AE
32
LD2AE
64
LE3AE
LG6AE
256
32
LG8AE
256
64
Flash (KB)
SRAM (KB)
128
8
8
16
LDROM (KB)
SPROM (Bytes)
2
2
4
4
4
512
48
512
48
512
2048
72
2048
72
System Frequency (MHz)
48
PLL (MHz)
I/O
96
96
96
144
144
42
32-bit Timer
USCI
4
1
3
1
3
1
2
6
2
6
UART
3
SPI/I2S
1
QSPI
-
2/0
-
-
2/0
-
-
1
2/1
-
1
2/1
-
I²C/SMBus
USB FS
PWM
2/0
-
12
BPWM
-
5
-
-
5
-
-
12
7
12
7
PDMA
5
EBI
√
√
√
CRC
√
HDIV
√
IEC-60730
HXT
-
-
-
-
-
√
√
√
√
√
LXT
√
RTC
-
2
Analog Comparator
12-bit SAR ADC
Package
12
LQFP48
Sep. 29, 2020
Page 24 of 288
Rev 2.02
M031/M032
3.2.3
M031 Base Series (M031Sx)
M031
Part Number
SC2AE
32
SD2AE
64
SE3AE
128
16
SG6AE
256
32
SG8AE
SIAAE
512
96
Flash (KB)
SRAM (KB)
256
64
8
8
LDROM (KB)
SPROM (Bytes)
2
2
4
4
4
8
512
48
512
48
512
48
2048
72
2048
72
2048
72
System Frequency (MHz)
PLL (MHz)
I/O
96
96
96
144
144
144
55
4
32-bit Timer
USCI
1
3
1
3
1
3
2
6
2
6
2
8
UART
SPI/I2S
1
QSPI
-
-
-
1
1
1
I²C/SMBus
USB FS
PWM
2/0
2/0
2/0
2/1
2/1
2/1
-
12
BPWM
-
5
-
-
5
-
-
12
7
12
7
12
9
PDMA
5
√
EBI
√
√
√
CRC
√
√
HDIV
IEC-60730
HXT
-
-
-
-
-
-
√
√
√
√
√
√
√
√
LXT
RTC
Analog Comparator
12-bit SAR ADC
Package
2
16
LQFP64
Sep. 29, 2020
Page 25 of 288
Rev 2.02
M031/M032
3.2.4
M031 Base Series (M031Kx)
M031
Part Number
KG6AE
256
32
KG8AE
KIAAE
512
96
Flash (KB)
SRAM (KB)
256
64
LDROM (KB)
SPROM (Bytes)
4
4
8
2048
System Frequency (MHz)
72
PLL (MHz)
I/O
144
111
32-bit Timer
USCI
4
2
UART
6
6
8
SPI/I2S
1
QSPI
1
I²C/SMBus
USB FS
PWM
2/1
-
12
BPWM
12
PDMA
7
7
9
EBI
√
CRC
√
HDIV
√
IEC-60730
HXT
√
√
LXT
√
RTC
√
Analog Comparator
12-bit SAR ADC
Package
2
16
LQFP128
Sep. 29, 2020
Page 26 of 288
Rev 2.02
M031/M032
3.2.5
M032 USB Series (M032Fx / M032Ex / M032Tx)
M032
Part Number
FC1AE
EC1AE
TC1AE
TD2AE
Flash (KB)
32
4
32
4
32
4
64
8
SRAM (KB)
LDROM (KB)
2
512
48
-
SPROM (Bytes)
System Frequency (MHz)
PLL (MHz)
I/O
11
2
19
2
23
2
23
4
32-bit Timer
USCI
1
1
1
2
UART
1
1
SPI/I2S
QSPI
-
-
-
1
I²C/SMBus
USB FS
PWM
-
√
-
BPWM
6
-
6
-
6
-
12
5
PDMA
EBI
-
-
CRC
HDIV
-
-
-
√
IEC-60730
HXT
-
-
-
-
-
LXT
RTC
Analog Comparator
12-bit SAR ADC
Package
3
9
10
10
TSSOP20
TSSOP28
QFN33
QFN33
Sep. 29, 2020
Page 27 of 288
Rev 2.02
M031/M032
3.2.6
M032 USB Series (M032Lx)
M032
Part Number
LC2AE
LD2AE
LE3AE
LG6AE
256
32
LG8AE
256
64
Flash (KB)
SRAM (KB)
32
8
64
8
128
16
LDROM (KB)
SPROM (Bytes)
2
2
4
4
4
512
48
-
512
48
-
512
2048
72
2048
72
System Frequency (MHz)
48
PLL (MHz)
I/O
96
144
144
38
32-bit Timer
USCI
4
2
1
2
1
1
2
6
2
6
UART
3
SPI/I2S
1
QSPI
1
-
1
-
-
1
1
I²C/SMBus
USB FS
PWM
2/0
2/1
2/1
√
-
12
5
-
-
12
5
-
12
12
12
7
12
12
7
BPWM
-
PDMA
5
EBI
√
√
√
CRC
-
-
√
√
√
HDIV
√
IEC-60730
HXT
-
-
-
-
-
-
-
-
-
-
-
√
√
√
√
2
√
√
√
√
2
√
LXT
√
RTC
-
2
Analog Comparator
12-bit SAR ADC
Package
12
LQFP48
Sep. 29, 2020
Page 28 of 288
Rev 2.02
M031/M032
3.2.7
M032 USB Series (M032Sx)
M032
Part Number
SE3AE
128
16
SG6AE
256
32
SG8AE
256
64
SIAAE
512
96
Flash (KB)
SRAM (KB)
LDROM (KB)
SPROM (Bytes)
4
4
4
8
512
48
2048
72
2048
72
2048
72
System Frequency (MHz)
PLL (MHz)
I/O
96
144
144
144
51
4
32-bit Timer
USCI
1
3
2
6
2
6
2
8
UART
SPI/I2S
1
QSPI
-
1
1
1
I²C/SMBus
USB FS
PWM
2/0
2/1
2/1
2/1
√
12
BPWM
-
12
7
12
7
12
9
PDMA
5
EBI
√
√
√
CRC
HDIV
IEC-60730
HXT
-
-
√
√
√
√
√
√
√
√
LXT
RTC
Analog Comparator
12-bit SAR ADC
Package
2
16
LQFP64
Sep. 29, 2020
Page 29 of 288
Rev 2.02
M031/M032
3.2.8
M032 USB Series (M032Kx)
M032
Part Number
KG6AE
256
32
KG8AE
KIAAE
512
96
Flash (KB)
SRAM (KB)
256
64
LDROM (KB)
SPROM (Bytes)
4
4
8
2048
System Frequency (MHz)
72
PLL (MHz)
I/O
144
107
32-bit Timer
USCI
4
2
UART
6
6
8
SPI/I2S
1
QSPI
1
I²C/SMBus
USB FS
PWM
2/1
√
12
BPWM
12
PDMA
7
7
9
EBI
√
CRC
√
HDIV
√
IEC-60730
HXT
√
√
LXT
√
RTC
√
Analog Comparator
12-bit SAR ADC
Package
2
16
LQFP128
Sep. 29, 2020
Page 30 of 288
Rev 2.02
M031/M032
3.2.9
Naming Rule
32
M0
Core
K
I
A
A
E
Line
Package
Flash
SRAM
Reserve
Temperature
E:-40°C ~ 105°C
Cortex®-M0 31: Base
32: USB
F: TSSOP20
(4.4x6.5 mm)
E: TSSOP28
(4.4x9.7 mm)
T: QFN33
(4x4 mm)
B: 16 KB
C: 32 KB
D: 64 KB
E: 128 KB
G: 256 KB
I: 512 KB
0: 2 KB
1: 4 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
8: 64 KB
A: 96 KB
L: LQFP48
(7x7 mm)
S: LQFP64
(7x7 mm)
K: LQFP128
(14x14 mm)
Sep. 29, 2020
Page 31 of 288
Rev 2.02
M031/M032
3.3 M031/M032 Series Feature Comparison Table
-
M031xB/C/D/E M031xG/I
Section
Sub-section
M032xC/D
M032xE
M032xG/I
6.3.6 SRAM Memory Organization
●
●
-
System Manager
6.3.7 SRAM Memory Organization with parity function
6.4.4.3 Physical and Virtual Address Concept
-
-
-
-
●
●
6.4.4.4 APROM Reboot Address Operation Model
Selection
-
-
-
-
-/●
6.4.4.14 Cache Memory Controller
●
6.4.4.15 Embedded Flash Memory Programming
64-bit Programming and Multi-word Programming
FMC
-
-
-
●
●
6.4.4.17 Flash All-One Verification
-
ISP Control Register (FMC_ISPCTL)
INTEN (FMC_ISPCTL[24])
-
-
●
6.25.5.11 PWM trigger
●
●
●
●
-
ADC
6.25.5.12 BPWM trigger
●
●
-
6.25.5.17 Floating Detect Function
6.16.5.2 Operation Modes
- Bus Management (SMBus/PMBus Compatiable)
- Device Identification – Slave Address
- Bus Protocols
- Address Resolution Protocol (ARP)
- Received Command and Data acknowledge control
- Host Notify Protocol
I2C
-
-
●
- Bus Management Alert
- Packet Error Checking
- Time-out
- Bus Management Time-out:
- Bus Clock Low Time-out:
- Bus Idle Detection
ACMP
EBI
6.26.5.7 Calibration function
-
-
-/-/-/●
●
●
6.21.5.3 EBI Data Width Connection - Address Bus
and Data Bus Separate Mode
-
6.21.5.4 EBI Operating Control - Continuous Data
Access Mode
-
-
-
●
6.22.7 Register Description
USBD
USB Configuration Register (USB_CFGx)
DSQSYNC OUT Token Transaction
●
-
Sep. 29, 2020
Page 32 of 288
Rev 2.02
M031/M032
4 PIN CONFIGURATION
Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfig. The
NuTool - PinConfigure contains all Nuvoton NuMicro® Family chip series with all part number, and
helps users configure GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1
M031 Series Pin Diagram
4.1.1.1 M031 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M031FB0AE, M031FC1AE
1
20
19
18
17
VSS
PF.1
2
3
LDO_CAP
VDD
PF.0
nRESET
PA.0
4
PB.14
PB.13
PB.12
AVDD
5
16 PA.1
15 PA.2
6
PA.3
PF.2
PF.3
PB.2
7
14
13
12
11
PB.5
8
PB.4
9
PB.3
10
Figure 4.1-1 M031 Series TSSOP 20-pin Diagram
Sep. 29, 2020
Page 33 of 288
Rev 2.02
M031/M032
4.1.1.2 M031 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M031EB0AE, M031EC1AE
1
28
27
26
25
24
23
PA.12
PC.0
2
PA.13
PC.1
3
PA.14
PF.1
4
5
PA.15
VSS
PF.0
nRESET
PA.0
6
LDO_CAP
VDD
7
22 PA.1
21 PA.2
PB.14
PB.13
PB.12
AVDD
8
PA.3
PF.2
PF.3
PB.0
PB.1
PB.2
9
20
19
18
17
16
15
10
11
12
13
14
PB.5
PB.4
PB.3
Figure 4.1-2 M031 Series TSSOP 28-pin Diagram
Sep. 29, 2020
Page 34 of 288
Rev 2.02
M031/M032
4.1.1.3 M031 Series QFN 33-Pin Diagram
Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE, M031TE3AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
Top transparent view
PB.15
PA.1
QFN33
PB.14
PA.2
PB.13
PA.3
PB.12
PF.2
33 VSS
AVDD
PF.3
Figure 4.1-3 M031 Series QFN 33-pin Diagram
Sep. 29, 2020
Page 35 of 288
Rev 2.02
M031/M032
4.1.1.4 M031 Series LQFP 48-Pin Diagram
Corresponding Part Number: M031LC2AE, M031LD2AE, M031LE3AE, M031LG6AE,
M031LG8AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP48
AVSS
PB.7
PB.6
PF.3
Figure 4.1-4 M031 Series LQFP 48-pin Diagram
Sep. 29, 2020
Page 36 of 288
Rev 2.02
M031/M032
4.1.1.5 M031 Series LQFP 64-Pin Diagram
Corresponding Part Number: M031SC2AE, M031SD2AE, M031SE3AE, M031SG6AE,
M031SG8AE, M031SIAAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP64
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PA.6
PA.7
PC.6
PC.7
PF.2
PB.8
PB.7
Figure 4.1-5 M031 Series LQFP 64-pin Diagram
Sep. 29, 2020
Page 37 of 288
Rev 2.02
M031/M032
4.1.1.6 M031 Series LQFP 128-Pin Diagram
Corresponding Part Number: M031KG6AE, M031KG8AE, M031KIAAE
97
64
PE.7
PE.6
nRESET
PE.15
PE.14
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
98
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
99
PE.5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PE.4
PE.3
PE.2
VSS
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
VSS
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
VDD
LQFP128
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
PB.8
PB.7
PB.6
Figure 4.1-6 M031 Series LQFP 128-pin Diagram
Sep. 29, 2020
Page 38 of 288
Rev 2.02
M031/M032
4.1.2
M031 Series Multi-function Pin Diagram
4.1.2.1 M031 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M031FB0AE, M031FC1AE
M031FB0AE
1
2
20
19
18
VSS
LDO_CAP
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
VDD
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
5
6
7
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
9
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
10
Figure 4.1-7 M031FB0AE Multi-function Pin Diagram
Pin M031FB0AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD
AVDD
PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
10 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2
11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
18 nRESET
19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
Table 4.1-1 M031FB0AE Multi-function Pin Table
Sep. 29, 2020
Page 39 of 288
Rev 2.02
M031/M032
M031FC1AE
1
2
20
19
18
VSS
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
LDO_CAP
VDD
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
5
6
7
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
9
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
10
Figure 4.1-8 M031FC1AE Multi-function Pin Diagram
Pin M031FC1AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT
AVDD
PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
10 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
11 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
12 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
13 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
18 nRESET
19 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
20 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
Table 4.1-2 M031FC1AE Multi-function Pin Table
Sep. 29, 2020
Page 40 of 288
Rev 2.02
M031/M032
4.1.2.2 M031 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M031EB0AE, M031EC1AE
M031EB0AE
1
2
28
27
26
25
I2C1_SCL / PA.12
PC.0 / UART2_RXD / I2C0_SDA
I2C1_SDA / PA.13
PC.1 / UART2_TXD / I2C0_SCL
3
UART0_TXD / PA.14
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / PA.15
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
VDD
7
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
8
9
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
Figure 4.1-9 M031EB0AE Multi-function Pin Diagram
Pin M031EB0AE Pin Function
1
2
3
4
5
6
7
8
9
PA.12 / I2C1_SCL
PA.13 / I2C1_SDA
PA.14 / UART0_TXD
PA.15 / UART0_RXD
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD
10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD
11 AVDD
12 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
13 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
14 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2
15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
Sep. 29, 2020
Page 41 of 288
Rev 2.02
M031/M032
Pin M031EB0AE Pin Function
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.1 / UART2_TXD / I2C0_SCL
28 PC.0 / UART2_RXD / I2C0_SDA
Table 4.1-3 M031EB0AE Multi-function Pin Table
M031EC1AE
1
2
28
27
26
25
I2C1_SCL / PA.12
PC.0 / UART2_RXD / I2C0_SDA
I2C1_SDA / PA.13
PC.1 / UART2_TXD / I2C0_SCL
3
UART0_TXD / PA.14
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / PA.15
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
VDD
7
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
8
9
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
Figure 4.1-10 M031EC1AE Multi-function Pin Diagram
Pin M031EC1AE Pin Function
1
2
3
4
5
6
7
8
9
PA.12 / I2C1_SCL
PA.13 / I2C1_SDA
PA.14 / UART0_TXD
PA.15 / UART0_RXD
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT
10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT
11 AVDD
12 PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
13 PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
14 PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
Sep. 29, 2020
Page 42 of 288
Rev 2.02
M031/M032
Pin M031EC1AE Pin Function
15 PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
16 PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
17 PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
18 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
19 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.1 / UART2_TXD / I2C0_SCL
28 PC.0 / UART2_RXD / I2C0_SDA
Table 4.1-4 M031EC1AE Multi-function Pin Table
Sep. 29, 2020
Page 43 of 288
Rev 2.02
M031/M032
4.1.2.3 M031 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE
M031TB0AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
Top transparent view
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-11 M031TB0AE Multi-function Pin Diagram
Pin M031TB0AE Pin Function
1
2
3
PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / INT2
Sep. 29, 2020
Page 44 of 288
Rev 2.02
M031/M032
Pin M031TB0AE Pin Function
4
5
6
7
8
9
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / ADC0_ST
PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / CLKO / INT4
16 nRESET
17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 PC.1 / UART2_TXD / I2C0_SCL
20 PC.0 / UART2_RXD / I2C0_SDA
21 PA.12 / I2C1_SCL
22 PA.13 / I2C1_SDA
23 PA.14 / UART0_TXD
24 PA.15 / UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT / PWM0_BRAKE1
29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD
31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD
32 AVDD
Table 4.1-5 M031TB0AE Multi-function Pin Table
Sep. 29, 2020
Page 45 of 288
Rev 2.02
M031/M032
M031TC1AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
Top transparent view
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-12 M031TC1AE Multi-function Pin Diagram
Pin M031TC1AE Pin Function
1
2
3
4
PB.5 / ADC0_CH5 / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 46 of 288
Rev 2.02
M031/M032
Pin M031TC1AE Pin Function
5
6
7
8
9
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
16 nRESET
17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 PC.1 / UART2_TXD / I2C0_SCL
20 PC.0 / UART2_RXD / I2C0_SDA
21 PA.12 / I2C1_SCL
22 PA.13 / I2C1_SDA
23 PA.14 / UART0_TXD
24 PA.15 / UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / TM0_EXT / PWM0_BRAKE1
29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / TM1_EXT / CLKO
30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / TM2_EXT
31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / TM3_EXT
32 AVDD
Table 4.1-6 M031TC1AE Multi-function Pin Table
Sep. 29, 2020
Page 47 of 288
Rev 2.02
M031/M032
M031TD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
Top transparent view
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
QFN33
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-13 M031TD2AE Multi-function Pin Diagram
Pin M031TD2AE Pin Function
1
2
3
4
5
6
7
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
Sep. 29, 2020
Page 48 of 288
Rev 2.02
M031/M032
Pin M031TD2AE Pin Function
8
9
PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
16 nRESET
17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
20 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
21 PA.12 / I2C1_SCL
22 PA.13 / I2C1_SDA
23 PA.14 / UART0_TXD
24 PA.15 / UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
29 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
30
31 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
32 AVDD
Table 4.1-7 M031TD2AE Multi-function Pin Table
Sep. 29, 2020
Page 49 of 288
Rev 2.02
M031/M032
M031TE3AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
Top transparent view
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
QFN33
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-14 M031TE3AE Multi-function Pin Diagram
Pin M031TE3AE Pin Function
1
2
3
4
5
6
7
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
Sep. 29, 2020
Page 50 of 288
Rev 2.02
M031/M032
Pin M031TE3AE Pin Function
8
9
PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
11 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
12 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
13 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
14 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
15 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
16 nRESET
17 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
18 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
20 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
21 PA.12 / I2C1_SCL
22 PA.13 / I2C1_SDA
23 PA.14 / UART0_TXD
24 PA.15 / UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
29 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
30
31 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
32 AVDD
Table 4.1-8 M031TE3AE Multi-function Pin Table
Sep. 29, 2020
Page 51 of 288
Rev 2.02
M031/M032
4.1.2.4 M031 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M031LC2AE, M031LD2AE, M031LE3AE, M031LG6AE,
M031LG8AE
M031LC2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
LQFP48
AVSS
ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7
ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-15 M031LC2AE Multi-function Pin Diagram
Pin M031LC2AE Pin Function
1
2
3
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
Sep. 29, 2020
Page 52 of 288
Rev 2.02
M031/M032
Pin M031LC2AE Pin Function
4
5
6
7
8
9
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT
PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT
10 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 PC.3 / UART2_nRTS / PWM1_CH2
30 PC.2 / UART2_nCTS / PWM1_CH3
31 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
32 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 PA.12 / I2C1_SCL
34 PA.13 / I2C1_SDA
35 PA.14 / UART0_TXD
36 PA.15 / UART0_RXD
37 VSS
Sep. 29, 2020
Page 53 of 288
Rev 2.02
M031/M032
Pin M031LC2AE Pin Function
38 LDO_CAP
39 VDD
40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
43
44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
48 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-9 M031LC2AE Multi-function Pin Table
Sep. 29, 2020
Page 54 of 288
Rev 2.02
M031/M032
M031LD2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
LQFP48
AVSS
ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7
ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-16 M031LD2AE Multi-function Pin Diagram
Pin M031LD2AE Pin Function
1
2
3
4
5
6
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
Sep. 29, 2020
Page 55 of 288
Rev 2.02
M031/M032
Pin M031LD2AE Pin Function
7
8
9
PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT
PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT
10 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
13 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
14 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
15 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 PC.3 / UART2_nRTS / PWM1_CH2
30 PC.2 / UART2_nCTS / PWM1_CH3
31 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
32 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 PA.12 / I2C1_SCL
34 PA.13 / I2C1_SDA
35 PA.14 / UART0_TXD
36 PA.15 / UART0_RXD
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
Sep. 29, 2020
Page 56 of 288
Rev 2.02
M031/M032
Pin M031LD2AE Pin Function
41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
43
44 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
48 PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-10 M031LD2AE Multi-function Pin Table
Sep. 29, 2020
Page 57 of 288
Rev 2.02
M031/M032
M031LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
/
I2C1_SDA
I2C1_SCL
UART0_RXD
/
PWM0_CH3
PWM0_CH2
I2C0_SDA
PWM0_CH0
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA XT1_OUT
/
/
INT4
/
/
/
/
/
/
I2C0_SCL / XT1_IN
Figure 4.1-17 M031LE3AE Multi-function Pin Diagram
Sep. 29, 2020
Page 58 of 288
Rev 2.02
M031/M032
Pin M031LE3AE Pin Function
1
2
3
4
5
6
7
8
9
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2
30 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3
31 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
32 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 PA.12 / I2C1_SCL
Sep. 29, 2020
Page 59 of 288
Rev 2.02
M031/M032
Pin M031LE3AE Pin Function
34 PA.13 / I2C1_SDA
35 PA.14 / UART0_TXD
36 PA.15 / UART0_RXD
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
PWM1_CH2 / TM2_EXT
43
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3
/ TM3_EXT
44
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
48 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-11 M031LE3AE Multi-function Pin Table
Sep. 29, 2020
Page 60 of 288
Rev 2.02
M031/M032
M031LG6AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0
/
PWM0_CH5
PWM0_CH4
I2C1_SDA BPWM0_CH2
I2C1_SCL BPWM0_CH3 PWM0_CH2
I2C0_SDA UART5_RXD BPWM0_CH4 PWM0_CH1
UART5_TXD PWM0_CH0
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 /
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD USCI0_CLK
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
/
I2C0_SMBSUS
/
UART1_RXD
/
/
/
PWM0_CH3
CLKO / PWM1_BRAKE1
CLKO
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
/
/
/
LQFP48
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
/
/
/
/
BPWM0_CH5
/
TM3
TM2
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-18 M031LG6AE Multi-function Pin Diagram
Pin M031LG6AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 61 of 288
Rev 2.02
M031/M032
Pin M031LG6AE Pin Function
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
5
6
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
7
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
18
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
19
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
20
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
34 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
35 PA.14 / UART0_TXD / BPWM1_CH4
36 PA.15 / UART0_RXD / BPWM1_CH5
Sep. 29, 2020
Page 62 of 288
Rev 2.02
M031/M032
Pin M031LG6AE Pin Function
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42
43
44
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
47
48
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-12 M031LG6AE Multi-function Pin Table
Sep. 29, 2020
Page 63 of 288
Rev 2.02
M031/M032
M031LG8AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0
/
PWM0_CH5
PWM0_CH4
I2C1_SDA BPWM0_CH2
I2C1_SCL BPWM0_CH3 PWM0_CH2
I2C0_SDA UART5_RXD BPWM0_CH4 PWM0_CH1
UART5_TXD PWM0_CH0
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 /
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD USCI0_CLK
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
/
I2C0_SMBSUS
/
UART1_RXD
/
/
/
PWM0_CH3
CLKO / PWM1_BRAKE1
CLKO
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
/
/
/
LQFP48
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
/
/
/
/
BPWM0_CH5
/
TM3
TM2
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-19 M031LG8AE Multi-function Pin Diagram
Pin M031LG8AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 64 of 288
Rev 2.02
M031/M032
Pin M031LG8AE Pin Function
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
5
6
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
7
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
18
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
19
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
20
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
34 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
35 PA.14 / UART0_TXD / BPWM1_CH4
36 PA.15 / UART0_RXD / BPWM1_CH5
Sep. 29, 2020
Page 65 of 288
Rev 2.02
M031/M032
Pin M031LG8AE Pin Function
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42
43
44
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
47
48
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-13 M031LG8AE Multi-function Pin Table
Sep. 29, 2020
Page 66 of 288
Rev 2.02
M031/M032
4.1.2.5 M031 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M031SC2AE, M031SD2AE, M031SE3AE, M031SG6AE,
M031SG8AE, M031SIAAE
M031SC2AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
PWM0_CH5
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
UART1_TXD
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
PWM1_CH3
PWM1_CH2
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-20 M031SC2AE Multi-function Pin Diagram
Pin M031SC2AE Pin Function
1
2
3
PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
Sep. 29, 2020
Page 67 of 288
Rev 2.02
M031/M032
Pin M031SC2AE Pin Function
4
5
6
7
8
9
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT
10 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT
11 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
12 PF.6 / SPI0_MOSI
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
16 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
17 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
18 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3
19 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2
20 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
36 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
37 PC.3 / UART2_nRTS / PWM1_CH2
Sep. 29, 2020
Page 68 of 288
Rev 2.02
M031/M032
Pin M031SC2AE Pin Function
38 PC.2 / UART2_nCTS / PWM1_CH3
39 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
40 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD
42 PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD
43 PD.1 / USCI0_DAT0 / SPI0_MISO
44 PD.0 / USCI0_CLK / SPI0_MOSI / TM2
45 PA.12 / I2C1_SCL
46 PA.13 / I2C1_SDA
47 PA.14 / UART0_TXD
48 PA.15 / UART0_RXD
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
53 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
54 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
55
56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK
61 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA
62 PB.9 / ADC0_CH9 / UART0_TXD / UART1_nCTS
63 PB.8 / ADC0_CH8 / UART0_RXD / UART1_nRTS
64 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
Table 4.1-14 M031SC2AE Multi-function Pin Table
Sep. 29, 2020
Page 69 of 288
Rev 2.02
M031/M032
M031SD2AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
PWM0_CH5
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
UART1_TXD
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
PWM1_CH3
PWM1_CH2
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-21 M031SD2AE Multi-function Pin Diagram
Pin M031SD2AE Pin Function
1
2
3
4
5
PB.6 / ADC0_CH6 / UART1_RXD / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 70 of 288
Rev 2.02
M031/M032
Pin M031SD2AE Pin Function
6
7
8
9
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / USCI0_DAT0 / TM1_EXT
10 PA.9 / USCI0_DAT1 / UART1_TXD / TM2_EXT
11 PA.8 / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
12 PF.6 / SPI0_MOSI
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
16 PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
17 PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
18 PC.7 / UART0_nCTS / PWM1_CH2 / TM0 / INT3
19 PC.6 / UART0_nRTS / PWM1_CH3 / TM1 / INT2
20 PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 PC.5 / UART2_TXD / I2C1_SCL / PWM1_CH0
36 PC.4 / UART2_RXD / I2C1_SDA / PWM1_CH1
37 PC.3 / UART2_nRTS / PWM1_CH2
38 PC.2 / UART2_nCTS / PWM1_CH3
39 PC.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
Sep. 29, 2020
Page 71 of 288
Rev 2.02
M031/M032
Pin M031SD2AE Pin Function
40 PC.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / USCI0_CTL1 / SPI0_SS / UART0_TXD
42 PD.2 / USCI0_DAT1 / SPI0_CLK / UART0_RXD
43 PD.1 / USCI0_DAT0 / SPI0_MISO
44 PD.0 / USCI0_CLK / SPI0_MOSI / TM2
45 PA.12 / I2C1_SCL
46 PA.13 / I2C1_SDA
47 PA.14 / UART0_TXD
48 PA.15 / UART0_RXD
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
53 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT / PWM0_BRAKE1
54 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / PWM1_CH2 /
TM2_EXT
55
56 PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3 / TM3_EXT
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK
61 PB.10 / ADC0_CH10 / UART0_nRTS / I2C1_SDA
62 PB.9 / ADC0_CH9 / UART0_TXD / UART1_nCTS
63 PB.8 / ADC0_CH8 / UART0_RXD / UART1_nRTS
64 PB.7 / ADC0_CH7 / UART1_TXD / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
Table 4.1-15 M031SD2AE Multi-function Pin Table
Sep. 29, 2020
Page 72 of 288
Rev 2.02
M031/M032
M031SE3AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
EBI_ADR16
EBI_ADR17
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
PWM1_CH3
PWM1_CH2
I2C0_SDA
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
EBI_nCS0
/
UART1_TXD
/
EBI_nWRL
EBI_nCS1
/
UART0_RXD
/
XT1_OUT
Figure 4.1-22 M031SE3AE Multi-function Pin Diagram
Pin M031SE3AE Pin Function
1
2
3
4
5
6
PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
Sep. 29, 2020
Page 73 of 288
Rev 2.02
M031/M032
Pin M031SE3AE Pin Function
7
8
9
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT
18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0
36 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1
37 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2
38 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3
39 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
40 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
Sep. 29, 2020
Page 74 of 288
Rev 2.02
M031/M032
Pin M031SE3AE Pin Function
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2
45 PA.12 / I2C1_SCL
46 PA.13 / I2C1_SDA
47 PA.14 / UART0_TXD
48 PA.15 / UART0_RXD
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3
/ TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK
61 PB.10 / ADC0_CH10 / EBI_ADR17 / UART0_nRTS / I2C1_SDA
62 PB.9 / ADC0_CH9 / EBI_ADR18 / UART0_TXD / UART1_nCTS
63 PB.8 / ADC0_CH8 / EBI_ADR19 / UART0_RXD / UART1_nRTS
64 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
Table 4.1-16 M031SE3AE Multi-function Pin Table
Sep. 29, 2020
Page 75 of 288
Rev 2.02
M031/M032
M031SG6AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-23 M031SG6AE Multi-function Pin Diagram
Pin M031SG6AE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
3
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 76 of 288
Rev 2.02
M031/M032
Pin M031SG6AE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
4
5
6
7
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
Sep. 29, 2020
Page 77 of 288
Rev 2.02
M031/M032
Pin M031SG6AE Pin Function
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
47 PA.14 / UART0_TXD / BPWM1_CH4
48 PA.15 / UART0_RXD / BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-17 M031SG6AE Multi-function Pin Table
Sep. 29, 2020
Page 78 of 288
Rev 2.02
M031/M032
M031SG8AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-24 M031SG8AE Multi-function Pin Diagram
Pin M031SG8AE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
3
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 79 of 288
Rev 2.02
M031/M032
Pin M031SG8AE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
4
5
6
7
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
Sep. 29, 2020
Page 80 of 288
Rev 2.02
M031/M032
Pin M031SG8AE Pin Function
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
47 PA.14 / UART0_TXD / BPWM1_CH4
48 PA.15 / UART0_RXD / BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-18 M031SG8AE Multi-function Pin Table
Sep. 29, 2020
Page 81 of 288
Rev 2.02
M031/M032
M031SIAAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART7_TXD
UART7_RXD
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
BPWM1_CH2
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
UART6_RXD
UART6_TXD
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
BPWM1_CH3
/
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-25 M031SIAAE Multi-function Pin Diagram
Pin M031SIAAE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
3
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 82 of 288
Rev 2.02
M031/M032
Pin M031SIAAE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
4
5
6
7
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
Sep. 29, 2020
Page 83 of 288
Rev 2.02
M031/M032
Pin M031SIAAE Pin Function
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
46 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
47 PA.14 / UART0_TXD / BPWM1_CH4
48 PA.15 / UART0_RXD / BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-19 M031SIAAE Multi-function Pin Table
Sep. 29, 2020
Page 84 of 288
Rev 2.02
M031/M032
Sep. 29, 2020
Page 85 of 288
Rev 2.02
M031/M032
4.1.2.6 M031 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M031KG6AE, M031KG8AE, M031KIAAE
M031KG6AE
BPWM0_CH5
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
BPWM0_CH3
BPWM0_CH2
BPWM0_CH1
BPWM0_CH0
/
PWM0_CH1
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH2
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
PWM0_CH5 USCI0_CLK
/
EBI_nRD
EBI_nWR
99
/
PWM0_CH3
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PWM0_CH4
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
UART3_nCTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
UART1_RXD
/
PWM1_CH1
/
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
UART1_nRTS
/
UART1_TXD
/
PWM0_CH5
/
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-26 M031KG6AE Multi-function Pin Diagram
Pin M031KG6AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 86 of 288
Rev 2.02
M031/M032
Pin M031KG6AE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
3
4
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3
34 PH.5 / EBI_ADR2
Sep. 29, 2020
Page 87 of 288
Rev 2.02
M031/M032
Pin M031KG6AE Pin Function
35 PH.6 / EBI_ADR1
36 PH.7 / EBI_ADR0
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD
63 PE.15 / EBI_AD9 / UART2_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS
Sep. 29, 2020
Page 88 of 288
Rev 2.02
M031/M032
Pin M031KG6AE Pin Function
68 PD.8 / EBI_AD6 / UART2_nRTS
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / BPWM0_CH3
80 PG.12 / EBI_AD3 / BPWM0_CH2
81 PG.13 / EBI_AD4 / BPWM0_CH1
82 PG.14 / EBI_AD5 / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
95 PA.14 / UART0_TXD / BPWM1_CH4
96 PA.15 / UART0_RXD / BPWM1_CH5
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1
Sep. 29, 2020
Page 89 of 288
Rev 2.02
M031/M032
Pin M031KG6AE Pin Function
102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-20 M031KG6AE Multi-function Pin Table
Sep. 29, 2020
Page 90 of 288
Rev 2.02
M031/M032
M031KG8AE
BPWM0_CH5
PWM0_CH1
UART7_nRTS UART6_TXD
UART7_nCTS UART6_RXD
UART7_TXD UART6_nRTS
PWM0_CH5 UART7_RXD UART6_nCTS
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
PWM0_CH2
PWM0_CH3
PWM0_CH4
/
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD UART6_RXD
/
BPWM0_CH3
BPWM0_CH2
/
/
/
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
USCI0_CLK
/
EBI_nRD
EBI_nWR
99
UART2_TXD / UART6_TXD
/
/
/
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
BPWM0_CH1
/
/
/
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
BPWM0_CH0
/
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
UART3_nCTS
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
UART6_RXD
UART6_TXD
UART1_RXD
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
PWM1_CH1 / BPWM1_CH4
/
BPWM1_CH1
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
/ UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
BPWM1_CH2
/
I2C1_SDA
UART7_TXD
UART7_RXD
BPWM1_CH4
BPWM1_CH5
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
/
UART7_RXD
UART7_TXD
BPWM1_CH3
/
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
UART7_nCTS
UART7_nRTS
/
/
UART6_RXD
UART6_TXD
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-27 M031KG8AE Multi-function Pin Diagram
Pin M031KG8AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 91 of 288
Rev 2.02
M031/M032
Pin M031KG8AE Pin Function
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3
34 PH.5 / EBI_ADR2
35 PH.6 / EBI_ADR1
36 PH.7 / EBI_ADR0
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Sep. 29, 2020
Page 92 of 288
Rev 2.02
M031/M032
Pin M031KG8AE Pin Function
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD
63 PE.15 / EBI_AD9 / UART2_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS
68 PD.8 / EBI_AD6 / UART2_nRTS
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
Sep. 29, 2020
Page 93 of 288
Rev 2.02
M031/M032
Pin M031KG8AE Pin Function
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / BPWM0_CH3
80 PG.12 / EBI_AD3 / BPWM0_CH2
81 PG.13 / EBI_AD4 / BPWM0_CH1
82 PG.14 / EBI_AD5 / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
95 PA.14 / UART0_TXD / BPWM1_CH4
96 PA.15 / UART0_RXD / BPWM1_CH5
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1
102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
Sep. 29, 2020
Page 94 of 288
Rev 2.02
M031/M032
Pin M031KG8AE Pin Function
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-21 M031KG8AE Multi-function Pin Table
Sep. 29, 2020
Page 95 of 288
Rev 2.02
M031/M032
M031KIAAE
BPWM0_CH5
PWM0_CH1
UART7_nRTS UART6_TXD
UART7_nCTS UART6_RXD
UART7_TXD UART6_nRTS
PWM0_CH5 UART7_RXD UART6_nCTS
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
PWM0_CH2
PWM0_CH3
PWM0_CH4
/
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD UART6_RXD
/
BPWM0_CH3
BPWM0_CH2
/
/
/
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
USCI0_CLK
/
EBI_nRD
EBI_nWR
99
UART2_TXD / UART6_TXD
/
/
/
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
BPWM0_CH1
/
/
/
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
BPWM0_CH0
/
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
UART3_nCTS
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
UART6_RXD
UART6_TXD
UART1_RXD
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
PWM1_CH1 / BPWM1_CH4
/
BPWM1_CH1
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
/ UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
BPWM1_CH2
/
I2C1_SDA
UART7_TXD
UART7_RXD
BPWM1_CH4
BPWM1_CH5
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
/
UART7_RXD
UART7_TXD
BPWM1_CH3
/
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
UART7_nCTS
UART7_nRTS
/
/
UART6_RXD
UART6_TXD
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-28 M031KIAAE Multi-function Pin Diagram
Pin M031KIAAE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 96 of 288
Rev 2.02
M031/M032
Pin M031KIAAE Pin Function
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / UART6_TXD / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / UART6_RXD / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART6_nRTS / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART6_nCTS / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD
34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD
35 PH.6 / EBI_ADR1 / UART7_TXD
36 PH.7 / EBI_ADR0 / UART7_RXD
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Sep. 29, 2020
Page 97 of 288
Rev 2.02
M031/M032
Pin M031KIAAE Pin Function
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD
63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD
68 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
Sep. 29, 2020
Page 98 of 288
Rev 2.02
M031/M032
Pin M031KIAAE Pin Function
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3
80 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2
81 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1
82 PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 PA.12 / UART4_TXD / I2C1_SCL / BPWM1_CH2
94 PA.13 / UART4_RXD / I2C1_SDA / BPWM1_CH3
95 PA.14 / UART0_TXD / BPWM1_CH4
96 PA.15 / UART0_RXD / BPWM1_CH5
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / UART6_TXD / UART7_nRTS / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / UART6_RXD / UART7_nCTS / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / UART6_nRTS / UART7_TXD / PWM0_CH4 / BPWM0_CH1
102 PE.2 / EBI_ALE / USCI0_CLK / UART6_nCTS / UART7_RXD / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
Sep. 29, 2020
Page 99 of 288
Rev 2.02
M031/M032
Pin M031KIAAE Pin Function
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-22 M031KIAAE Multi-function Pin Table
Sep. 29, 2020
Page 100 of 288
Rev 2.02
M031/M032
4.1.3
M032 Series Pin Diagram
4.1.3.1 M032 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M032FC1AE
1
20
19
18
17
USB_D-
USB_VBUS
2
3
USB_D+
PF.1
USB_VDD33_CAP
VSS
PF.0
4
nRESET
LDO_CAP
VDD
5
16 PA.0
15 PA.1
6
PB.14
PA.2
PA.3
PF.2
PF.3
7
14
13
12
11
PB.13
8
PB.12
9
AVDD
10
Figure 4.1-29 M032 Series TSSOP 20-pin Diagram
Sep. 29, 2020
Page 101 of 288
Rev 2.02
M031/M032
4.1.3.2 M032 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M032EC1AE
1
28
27
26
25
24
23
USB_VBUS
PC.0
2
USB_D-
PC.1
3
USB_D+
PF.1
4
5
USB_VDD33_CAP
VSS
PF.0
nRESET
PA.0
6
LDO_CAP
VDD
7
22 PA.1
21 PA.2
PB.14
8
PB.13
PA.3
PF.2
PF.3
PB.0
PB.1
PB.2
9
20
19
18
17
16
15
PB.12
10
11
12
13
14
AVDD
PB.5
PB.4
PB.3
Figure 4.1-30 M032 Series TSSOP 28-pin Diagram
Sep. 29, 2020
Page 102 of 288
Rev 2.02
M031/M032
4.1.3.3 M032 Series QFN 33-Pin Diagram
Corresponding Part Number: M032TC1AE, M032TD2AE
25
16
15
14
13
12
11
10
9
VSS
nRESET
PF.15
PA.0
Top transparent view
26
LDO_CAP
27
VDD
28
PB.15
PA.1
QFN33
29
PB.14
PA.2
30
PB.13
PA.3
31
PB.12
PF.2
33 VSS
32
AVDD
PF.3
Figure 4.1-31 M032 Series QFN 33-pin Diagram
Sep. 29, 2020
Page 103 of 288
Rev 2.02
M031/M032
4.1.3.4 M032 Series LQFP 48-Pin Diagram
Corresponding Part Number: M032LC2AE, M032LD2AE ,M032LE3AE, M032LG6AE,
M032LG8AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP48
AVSS
PB.7
PB.6
PF.3
Figure 4.1-32 M032 Series LQFP 48-pin Diagram
Sep. 29, 2020
Page 104 of 288
Rev 2.02
M031/M032
4.1.3.5 M032 Series LQFP 64-Pin Diagram
Corresponding Part Number: M032SE3AE, M032SG6AE, M032SG8AE, M032SIAAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP64
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PA.6
PA.7
PC.6
PC.7
PF.2
PB.8
PB.7
Figure 4.1-33 M032 Series LQFP 64-pin Diagram
Sep. 29, 2020
Page 105 of 288
Rev 2.02
M031/M032
4.1.3.6 M032 Series LQFP 128-Pin Diagram
Corresponding Part Number: M032KG6AE, M032KG8AE, M032KIAAE
97
64
PE.7
PE.6
nRESET
PE.15
PE.14
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
98
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
99
PE.5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PE.4
PE.3
PE.2
VSS
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
VSS
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
VDD
LQFP128
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
PB.8
PB.7
PB.6
Figure 4.1-34 M032 Series LQFP 128-pin Diagram
Sep. 29, 2020
Page 106 of 288
Rev 2.02
M031/M032
4.1.4
M032 Series Multi-function Pin Diagram
4.1.4.1 M032 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M032FC1AE
M032FC1AE
1
2
20
19
18
USB_D-
USB_VBUS
USB_D+
PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK
PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT
3
USB_VDD33_CAP
VSS
4
17 nRESET
LDO_CAP
5
16 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
VDD
CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
6
15 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
14 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
7
PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PF.2 / UART0_RXD / USCI1_CTL1
8
13
12
11
9
PF.3 / UART0_TXD / USCI1_CTL0
10
Figure 4.1-35 M032FC1AE Multi-function Pin Diagram
Pin M032FC1AE Pin Function
1
2
3
4
5
6
7
8
9
USB_D-
USB_D+
USB_VDD33_CAP
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1
PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
10 AVDD
11 PF.3 / UART0_TXD / USCI1_CTL0
12 PF.2 / UART0_RXD / USCI1_CTL1
13 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
14 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
15 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
16 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
17 nRESET
18 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT
19 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK
20 USB_VBUS
Table 4.1-23 M032FC1AE Multi-function Pin Table
Sep. 29, 2020
Page 107 of 288
Rev 2.02
M031/M032
4.1.4.2 M032 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M032EC1AE
M032EC1AE
1
2
28
27
26
25
24
USB_VBUS
PC.0 / BPWM0_CH4
USB_D-
PC.1 / BPWM0_CH5 / ADC0_ST
PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK
PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT
nRESET
3
USB_D+
4
USB_VDD33_CAP
5
VSS
LDO_CAP
6
23 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
VDD
7
22 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
21 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
8
9
20 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PF.2 / UART0_RXD / USCI1_CTL1
PF.3 / UART0_TXD / USCI1_CTL0
PB.0 / ADC0_CH0 / SPI0_I2SMCLK
PB.1 / ADC0_CH1 / USCI1_CLK
10
11
12
13
14
19
18
17
16
15
INT0 / TM0 / USCI1_CTL0 / ADC0_CH5 / PB.5
INT1 / TM1 / USCI1_CTL1 / ADC0_CH4 / PB.4
INT2 / USCI1_DAT1 / ADC0_CH3 / PB.3
PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3
Figure 4.1-36 M032EC1AE Multi-function Pin Diagram
Pin M032EC1AE Pin Function
1
2
3
4
5
6
7
8
9
USB_VBUS
USB_D-
USB_D+
USB_VDD33_CAP
VSS
LDO_CAP
VDD
PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1
10 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
11 AVDD
12 PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0
13 PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1
14 PB.3 / ADC0_CH3 / USCI1_DAT1 / INT2
15 PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3
16 PB.1 / ADC0_CH1 / USCI1_CLK
17 PB.0 / ADC0_CH0 / SPI0_I2SMCLK
18 PF.3 / UART0_TXD / USCI1_CTL0
19 PF.2 / UART0_RXD / USCI1_CTL1
Sep. 29, 2020
Page 108 of 288
Rev 2.02
M031/M032
Pin M032EC1AE Pin Function
20 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
21 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
22 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
23 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
24 nRESET
25 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT
26 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK
27 PC.1 / BPWM0_CH5 / ADC0_ST
28 PC.0 / BPWM0_CH4
Table 4.1-24 M032EC1AE Multi-function Pin Table
Sep. 29, 2020
Page 109 of 288
Rev 2.02
M031/M032
4.1.4.3 M032 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M032TC1AE, M032TD2AE
M032TC1AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
Top transparent view
LDO_CAP
VDD
PF.15 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PF.2 / UART0_RXD / USCI1_CTL1
TM0_EXT / BPWM0_CH3 / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / BPWM0_CH2 / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
BPWM0_CH1 / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
BPWM0_CH0 / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / USCI1_CTL0
Figure 4.1-37 M032TC1AE Multi-function Pin Diagram
Pin M032TC1AE Pin Function
1
2
3
PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0
PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1
PB.3 / ADC0_CH3 / USCI1_DAT1 / INT2
Sep. 29, 2020
Page 110 of 288
Rev 2.02
M031/M032
Pin M032TC1AE Pin Function
4
5
6
7
8
9
PB.2 / ADC0_CH2 / USCI1_DAT0 / INT3
PB.1 / ADC0_CH1 / USCI1_CLK
PB.0 / ADC0_CH0 / SPI0_I2SMCLK
PF.5 / BPWM0_CH4 / ADC0_ST
PF.4 / BPWM0_CH5
PF.3 / UART0_TXD / USCI1_CTL0
10 PF.2 / UART0_RXD / USCI1_CTL1
11 PA.3 / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
12 PA.2 / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
13 PA.1 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
14 PA.0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
15 PF.15 / CLKO / INT4
16 nRESET
17 PF.0 / UART0_TXD / BPWM0_CH5 / ICE_DAT
18 PF.1 / UART0_RXD / BPWM0_CH4 / ICE_CLK
19 PC.1 / BPWM0_CH5 / ADC0_ST
20 PC.0 / BPWM0_CH4
21 USB_VBUS
22 USB_D-
23 USB_D+
24 USB_VDD33_CAP
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / UART0_nCTS / BPWM0_CH3 / TM0_EXT
29 PB.14 / ADC0_CH14 / SPI0_CLK / UART0_nRTS / BPWM0_CH2 / TM1_EXT / CLKO
30 PB.13 / ADC0_CH13 / SPI0_MISO / UART0_TXD / BPWM0_CH1
31 PB.12 / ADC0_CH12 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
32 AVDD
Table 4.1-25 M032TC1AE Multi-function Pin Table
Sep. 29, 2020
Page 111 of 288
Rev 2.02
M031/M032
M032TD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
Top transparent view
PF.15 / TM2 / CLKO / INT4
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
QFN33
33 VSS
Figure 4.1-38 M032TD2AE Multi-function Pin Diagram
Pin M032TD2AE Pin Function
1
2
3
4
5
6
PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0
PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1
PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2
PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3
PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1
PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1
Sep. 29, 2020
Page 112 of 288
Rev 2.02
M031/M032
Pin M032TD2AE Pin Function
7
8
9
PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST
PF.4 / QSPI0_MOSI1 / BPWM0_CH5
PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
10 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
11 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
12 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
13 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
14 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
15 PF.15 / TM2 / CLKO / INT4
16 nRESET
17 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT
18 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK
19 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST
20 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4
21 USB_VBUS
22 USB_D-
23 USB_D+
24 USB_VDD33_CAP
25 VSS
26 LDO_CAP
27 VDD
28 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT
29 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO
30 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT
31 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT
32 AVDD
Table 4.1-26 M032TD2AE Multi-function Pin Table
Sep. 29, 2020
Page 113 of 288
Rev 2.02
M031/M032
4.1.4.4 M032 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M032LC2AE, M032LD2AE, M032LE3AE, M032LG6AE,
M032LG8AE
M032LC2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
PF.15 / TM2 / CLKO / INT4
VDD
TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4
PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5
PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0
TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
LQFP48
AVSS
PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1
INT5 / BPWM1_CH4 / USCI1_DAT0 / ADC0_CH7 / PB.7
PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
INT4 / BPWM1_CH5 / USCI1_DAT1 / ADC0_CH6 / PB.6
Figure 4.1-39 M032LC2AE Multi-function Pin Diagram
Pin M032LC2AE Pin Function
1
2
3
PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0
PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1
PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2
Sep. 29, 2020
Page 114 of 288
Rev 2.02
M031/M032
Pin M032LC2AE Pin Function
4
5
6
7
8
9
PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3
PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1
PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1
PA.11 / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / USCI0_DAT1 / BPWM0_CH2 / TM2_EXT
10 PA.8 / USCI0_CTL1 / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST
12 PF.4 / QSPI0_MOSI1 / BPWM0_CH5
13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1
16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5
18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4
19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
23 PF.15 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT
26 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK
27 PC.5 / QSPI0_MISO1
28 PC.4 / QSPI0_MOSI1
29 PC.3 / QSPI0_SS
30 PC.2 / QSPI0_CLK
31 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST
32 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
37 VSS
Sep. 29, 2020
Page 115 of 288
Rev 2.02
M031/M032
Pin M032LC2AE Pin Function
38 LDO_CAP
39 VDD
40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT
42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO
43 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT
44 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / USCI1_DAT0 / BPWM1_CH4 / INT5
48 PB.6 / ADC0_CH6 / USCI1_DAT1 / BPWM1_CH5 / INT4
Table 4.1-27 M032LC2AE Multi-function Pin Table
Sep. 29, 2020
Page 116 of 288
Rev 2.02
M031/M032
M032LD2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
VDD
PF.15 / TM2 / CLKO / INT4
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
TM1 / QSPI0_CLK / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4
PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5
PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0
TM0_EXT / BPWM0_CH3 / BPWM1_CH4 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / BPWM0_CH2 / BPWM1_CH5 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / BPWM0_CH1 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / BPWM0_CH0 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
LQFP48
AVSS
PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1
INT5 / BPWM1_CH4 / USCI1_DAT0 / ADC0_CH7 / PB.7
PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
INT4 / BPWM1_CH5 / USCI1_DAT1 / ADC0_CH6 / PB.6
Figure 4.1-40 M032LD2AE Multi-function Pin Diagram
Pin M032LD2AE Pin Function
1
2
3
4
5
6
PB.5 / ADC0_CH5 / USCI1_CTL0 / TM0 / INT0
PB.4 / ADC0_CH4 / USCI1_CTL1 / TM1 / INT1
PB.3 / ADC0_CH3 / USCI1_DAT1 / TM2 / INT2
PB.2 / ADC0_CH2 / USCI1_DAT0 / TM3 / INT3
PB.1 / ADC0_CH1 / USCI1_CLK / QSPI0_MISO1
PB.0 / ADC0_CH0 / SPI0_I2SMCLK / QSPI0_MOSI1
Sep. 29, 2020
Page 117 of 288
Rev 2.02
M031/M032
Pin M032LD2AE Pin Function
7
8
9
PA.11 / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / USCI0_DAT1 / BPWM0_CH2 / TM2_EXT
10 PA.8 / USCI0_CTL1 / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / QSPI0_MISO1 / BPWM0_CH4 / ADC0_ST
12 PF.4 / QSPI0_MOSI1 / BPWM0_CH5
13 PF.3 / UART0_TXD / BPWM1_CH0 / USCI1_CTL0
14 PF.2 / UART0_RXD / QSPI0_CLK / BPWM1_CH1 / USCI1_CTL1
15 PA.7 / UART0_TXD / BPWM1_CH2 / TM2 / INT1
16 PA.6 / UART0_RXD / BPWM1_CH3 / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / BPWM0_CH5
18 PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / BPWM0_CH4
19 PA.3 / QSPI0_SS / SPI0_SS / USCI1_DAT1 / BPWM0_CH3 / CLKO
20 PA.2 / QSPI0_CLK / SPI0_CLK / USCI1_DAT0 / BPWM0_CH2
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / USCI1_CLK / BPWM0_CH1
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / BPWM0_CH0
23 PF.15 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART0_TXD / BPWM1_CH0 / BPWM0_CH5 / ICE_DAT
26 PF.1 / UART0_RXD / BPWM1_CH1 / BPWM0_CH4 / ICE_CLK
27 PC.5 / QSPI0_MISO1
28 PC.4 / QSPI0_MOSI1
29 PC.3 / QSPI0_SS
30 PC.2 / QSPI0_CLK
31 PC.1 / QSPI0_MISO0 / BPWM1_CH2 / BPWM0_CH5 / ADC0_ST
32 PC.0 / QSPI0_MOSI0 / BPWM1_CH3 / BPWM0_CH4
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
Sep. 29, 2020
Page 118 of 288
Rev 2.02
M031/M032
Pin M032LD2AE Pin Function
41 PB.15 / ADC0_CH15 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / BPWM1_CH4 / BPWM0_CH3 / TM0_EXT
42 PB.14 / ADC0_CH14 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / BPWM1_CH5 / BPWM0_CH2 / TM1_EXT / CLKO
43 PB.13 / ADC0_CH13 / SPI0_MISO / USCI0_DAT0 / UART0_TXD / BPWM0_CH1 / TM2_EXT
44 PB.12 / ADC0_CH12 / SPI0_MOSI / USCI0_CLK / UART0_RXD / BPWM0_CH0 / TM3_EXT
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / USCI1_DAT0 / BPWM1_CH4 / INT5
48 PB.6 / ADC0_CH6 / USCI1_DAT1 / BPWM1_CH5 / INT4
Table 4.1-28 M032LD2AE Multi-function Pin Table
Sep. 29, 2020
Page 119 of 288
Rev 2.02
M031/M032
M032LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA XT1_OUT
/
/
/
/
/
/
/
/
I2C0_SCL / XT1_IN
Figure 4.1-41 M032LE3AE Multi-function Pin Diagram
Pin M032LE3AE Pin Function
1
2
3
4
5
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
Sep. 29, 2020
Page 120 of 288
Rev 2.02
M031/M032
Pin M032LE3AE Pin Function
6
7
8
9
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
18 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
19 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
20 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
21 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
22 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
27 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0
28 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1
29 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2
30 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3
31 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
32 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
37 VSS
38 LDO_CAP
39 VDD
Sep. 29, 2020
Page 121 of 288
Rev 2.02
M031/M032
Pin M032LE3AE Pin Function
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
PWM1_CH2 / TM2_EXT
43
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3
/ TM3_EXT
44
45 AVDD
46 AVSS
47 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
48 PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-29 M032LE3AE Multi-function Pin Table
Sep. 29, 2020
Page 122 of 288
Rev 2.02
M031/M032
M032LG6AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0
/
PWM0_CH5
PWM0_CH4
I2C1_SDA BPWM0_CH2
I2C1_SCL BPWM0_CH3 PWM0_CH2
I2C0_SDA UART5_RXD BPWM0_CH4 PWM0_CH1
UART5_TXD PWM0_CH0
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 /
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD USCI0_CLK
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
/
I2C0_SMBSUS
/
UART1_RXD
/
/
/
PWM0_CH3
CLKO / PWM1_BRAKE1
CLKO
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
/
/
/
LQFP48
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
/
/
/
/
BPWM0_CH5
/
TM3
TM2
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-42 M032LG6AE Multi-function Pin Diagram
Pin M032LG6AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 123 of 288
Rev 2.02
M031/M032
Pin M032LG6AE Pin Function
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
5
6
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
7
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
18
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
19
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
20
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
Sep. 29, 2020
Page 124 of 288
Rev 2.02
M031/M032
Pin M032LG6AE Pin Function
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42
43
44
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
47
48
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-30 M032LG6AE Multi-function Pin Table
Sep. 29, 2020
Page 125 of 288
Rev 2.02
M031/M032
M032LG8AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0
/
PWM0_CH5
PWM0_CH4
I2C1_SDA BPWM0_CH2
I2C1_SCL BPWM0_CH3 PWM0_CH2
I2C0_SDA UART5_RXD BPWM0_CH4 PWM0_CH1
UART5_TXD PWM0_CH0
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 /
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD USCI0_CLK
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
/
I2C0_SMBSUS
/
UART1_RXD
/
/
/
PWM0_CH3
CLKO / PWM1_BRAKE1
CLKO
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
/
/
/
LQFP48
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
/
/
/
/
BPWM0_CH5
/
TM3
TM2
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-43 M032LG8AE Multi-function Pin Diagram
Pin M032LG8AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 126 of 288
Rev 2.02
M031/M032
Pin M032LG8AE Pin Function
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
5
6
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
7
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
10 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
11 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
12 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
13 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
14 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
15 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
16 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
17 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
18
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
19
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
20
21 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
22 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
23 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
24 nRESET
25 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
26 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
27 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
28 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
29 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
30 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
31 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
32 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
Sep. 29, 2020
Page 127 of 288
Rev 2.02
M031/M032
Pin M032LG8AE Pin Function
37 VSS
38 LDO_CAP
39 VDD
40 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
41
42
43
44
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
45 AVDD
46 AVSS
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
47
48
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
Table 4.1-31 M032LG8AE Multi-function Pin Table
Sep. 29, 2020
Page 128 of 288
Rev 2.02
M031/M032
4.1.4.5 M032 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M032SE3AE, M032SG6AE, M032SG8AE, M032SIAAE
M032SE3AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
EBI_ADR16
EBI_ADR17
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
PWM1_CH3
PWM1_CH2
I2C0_SDA
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
EBI_nCS0
/
UART1_TXD
/
EBI_nWRL
EBI_nCS1
/
UART0_RXD
/
XT1_OUT
Figure 4.1-44 M032SE3AE Multi-function Pin Diagram
Pin M032SE3AE Pin Function
1
2
PB.6 / ADC0_CH6 / EBI_nWRH / UART1_RXD / EBI_nCS1 / PWM1_BRAKE1 / PWM1_CH5 / INT4 / ACMP1_O
PB.5 / ADC0_CH5 / ACMP1_N / I2C0_SCL / PWM0_CH0 / UART2_TXD / TM0 / INT0
Sep. 29, 2020
Page 129 of 288
Rev 2.02
M031/M032
Pin M032SE3AE Pin Function
3
4
5
6
7
8
9
PB.4 / ADC0_CH4 / ACMP1_P1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / XT1_OUT
18 PC.7 / EBI_AD9 / UART0_nCTS / PWM1_CH2 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART0_nRTS / PWM1_CH3 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
26 PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
27 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
28 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
29 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
30 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
35 PC.5 / EBI_AD5 / UART2_TXD / I2C1_SCL / PWM1_CH0
36 PC.4 / EBI_AD4 / UART2_RXD / I2C1_SDA / PWM1_CH1
Sep. 29, 2020
Page 130 of 288
Rev 2.02
M031/M032
Pin M032SE3AE Pin Function
37 PC.3 / EBI_AD3 / UART2_nRTS / PWM1_CH2
38 PC.2 / EBI_AD2 / UART2_nCTS / PWM1_CH3
39 PC.1 / EBI_AD1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O
40 PC.0 / EBI_AD0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
54 PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / PWM1_CH1 / TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD / PWM1_CH3
/ TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / I2C1_SCL / SPI0_I2SMCLK
61 PB.10 / ADC0_CH10 / EBI_ADR17 / UART0_nRTS / I2C1_SDA
62 PB.9 / ADC0_CH9 / EBI_ADR18 / UART0_TXD / UART1_nCTS
63 PB.8 / ADC0_CH8 / EBI_ADR19 / UART0_RXD / UART1_nRTS
64 PB.7 / ADC0_CH7 / EBI_nWRL / UART1_TXD / EBI_nCS0 / PWM1_BRAKE0 / PWM1_CH4 / INT5 / ACMP0_O
Table 4.1-32 M032SE2AE Multi-function Pin Table
Sep. 29, 2020
Page 131 of 288
Rev 2.02
M031/M032
M032SG6AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-45 M032SG6AE Multi-function Pin Diagram
Pin M032SG6AE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
3
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 132 of 288
Rev 2.02
M031/M032
Pin M032SG6AE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
4
5
6
7
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
Sep. 29, 2020
Page 133 of 288
Rev 2.02
M031/M032
Pin M032SG6AE Pin Function
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-33 M032SG6AE Multi-function Pin Table
Sep. 29, 2020
Page 134 of 288
Rev 2.02
M031/M032
M032SG8AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-46 M032SG8AE Multi-function Pin Diagram
Pin M032SG8AE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
3
4
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
Sep. 29, 2020
Page 135 of 288
Rev 2.02
M031/M032
Pin M032SG8AE Pin Function
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
5
6
7
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
Sep. 29, 2020
Page 136 of 288
Rev 2.02
M031/M032
Pin M032SG8AE Pin Function
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-34 M032SG8AE Multi-function Pin Table
Sep. 29, 2020
Page 137 of 288
Rev 2.02
M031/M032
M032SIAAE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
/
BPWM0_CH1 / PWM0_CH4
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
CLKO
/
/
/
/
/
/
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART7_TXD
UART7_RXD
PWM1_BRAKE0
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
/
/
/
BPWM1_CH2
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
/
UART0_nRTS
UART0_nCTS
/
UART6_RXD
UART6_TXD
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
BPWM1_CH3
/
/
/
/
UART0_RXD
UART1_TXD
/
/
/
/
/
/
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
/
/
/
USCI1_DAT0
/
EBI_nWRL
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-47 M032SIAAE Multi-function Pin Diagram
Pin M032SIAAE Pin Function
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
1
2
3
4
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
Sep. 29, 2020
Page 138 of 288
Rev 2.02
M031/M032
Pin M032SIAAE Pin Function
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
5
6
7
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
8
9
PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT
PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT
10 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT
11 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4
12 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
13 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
14 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
15 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
16 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
17 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
18 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
19 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
20 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
21 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
22 VSS
23 VDD
24 PD.15 / PWM0_CH5 / TM3 / INT1
25 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
26
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
27
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
28
29 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
30 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
31 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
32 nRESET
33 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
34 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
35 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
Sep. 29, 2020
Page 139 of 288
Rev 2.02
M031/M032
Pin M032SIAAE Pin Function
36 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
37 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
38 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
39 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
40 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
41 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
42 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
43 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
44 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
53
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
54
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
55
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
61 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
62 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2
63 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
64
Table 4.1-35 M032SIAAE Multi-function Pin Table
Sep. 29, 2020
Page 140 of 288
Rev 2.02
M031/M032
4.1.4.6 M032 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M032KG6AE, M032KG8AE, M032KIAAE
M032KG6AE
BPWM0_CH5
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
BPWM0_CH3
BPWM0_CH2
BPWM0_CH1
BPWM0_CH0
/
PWM0_CH1
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH2
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
PWM0_CH5 USCI0_CLK
/
EBI_nRD
EBI_nWR
99
/
PWM0_CH3
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PWM0_CH4
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
UART3_nCTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
UART1_RXD
/
PWM1_CH1
/
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
UART1_nRTS
/
UART1_TXD
/
PWM0_CH5
/
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-48 M032KG6AE Multi-function Pin Diagram
Pin M032KG6AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
Sep. 29, 2020
Page 141 of 288
Rev 2.02
M031/M032
Pin M032KG6AE Pin Function
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
3
4
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3
34 PH.5 / EBI_ADR2
Sep. 29, 2020
Page 142 of 288
Rev 2.02
M031/M032
Pin M032KG6AE Pin Function
35 PH.6 / EBI_ADR1
36 PH.7 / EBI_ADR0
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD
63 PE.15 / EBI_AD9 / UART2_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS
Sep. 29, 2020
Page 143 of 288
Rev 2.02
M031/M032
Pin M032KG6AE Pin Function
68 PD.8 / EBI_AD6 / UART2_nRTS
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / BPWM0_CH3
80 PG.12 / EBI_AD3 / BPWM0_CH2
81 PG.13 / EBI_AD4 / BPWM0_CH1
82 PG.14 / EBI_AD5 / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1
Sep. 29, 2020
Page 144 of 288
Rev 2.02
M031/M032
Pin M032KG6AE Pin Function
102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-36 M032KG6AE Multi-function Pin Table
Sep. 29, 2020
Page 145 of 288
Rev 2.02
M031/M032
M032KG8AE
BPWM0_CH5
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
BPWM0_CH3
BPWM0_CH2
BPWM0_CH1
BPWM0_CH0
/
PWM0_CH1
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH2
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
PWM0_CH5 USCI0_CLK
/
EBI_nRD
EBI_nWR
99
/
PWM0_CH3
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PWM0_CH4
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
UART3_nCTS
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
PWM1_CH3
PWM1_CH2
/
BPWM1_CH1
BPWM1_CH0
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
UART1_RXD
/
PWM1_CH1
/
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
/
UART1_TXD
/
PWM0_CH5
/
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
/
I2C1_SDA
BPWM1_CH2
BPWM1_CH3
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-49 M032KG8AE Multi-function Pin Diagram
Pin M032KG8AE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 146 of 288
Rev 2.02
M031/M032
Pin M032KG8AE Pin Function
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3
34 PH.5 / EBI_ADR2
35 PH.6 / EBI_ADR1
36 PH.7 / EBI_ADR0
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Sep. 29, 2020
Page 147 of 288
Rev 2.02
M031/M032
Pin M032KG8AE Pin Function
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD
63 PE.15 / EBI_AD9 / UART2_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS
68 PD.8 / EBI_AD6 / UART2_nRTS
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
Sep. 29, 2020
Page 148 of 288
Rev 2.02
M031/M032
Pin M032KG8AE Pin Function
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / BPWM0_CH3
80 PG.12 / EBI_AD3 / BPWM0_CH2
81 PG.13 / EBI_AD4 / BPWM0_CH1
82 PG.14 / EBI_AD5 / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / PWM0_CH4 / BPWM0_CH1
102 PE.2 / EBI_ALE / USCI0_CLK / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
Sep. 29, 2020
Page 149 of 288
Rev 2.02
M031/M032
Pin M032KG8AE Pin Function
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-37 M032KG8AE Multi-function Pin Table
Sep. 29, 2020
Page 150 of 288
Rev 2.02
M031/M032
M032KIAAE
BPWM0_CH5
PWM0_CH1
UART7_nRTS UART6_TXD
UART7_nCTS UART6_RXD
UART7_TXD UART6_nRTS
PWM0_CH5 UART7_RXD UART6_nCTS
/
PWM0_CH0
/
UART5_TXD
USCI0_CTL0
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
PWM0_CH2
PWM0_CH3
PWM0_CH4
/
/
UART5_RXD
/
98
PE.15
PE.14
PF.15
/
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD UART6_RXD
/
BPWM0_CH3
BPWM0_CH2
/
/
/
/
USCI0_CTL1
USCI0_DAT1
USCI0_DAT0
USCI0_CLK
/
EBI_nRD
EBI_nWR
99
UART2_TXD / UART6_TXD
/
/
/
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
BPWM0_CH1
/
/
/
/
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS
UART1_nCTS
/
BPWM0_CH0 PWM0_CH5
/
BPWM0_CH0
/
/
/
/
/
/
/
BPWM0_CH1 / PWM0_CH4
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS UART4_TXD
SPI0_I2SMCLK UART0_nRTS
UART0_nCTS UART0_TXD I2C0_SCL
INT1
/
UART4_RXD
I2C0_SMBAL
UART0_RXD
UART5_TXD
/
I2C0_SMBSUS
UART1_TXD
I2C0_SDA
BPWM0_CH5
/
UART1_RXD
I2C1_SCL
UART5_RXD
/
I2C1_SDA
BPWM0_CH3
BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
VDD
/
/
/
/
/
/
/
/
CLKO / PWM1_BRAKE1
UART4_nCTS
UART4_nRTS
/
I2C1_SCL
I2C1_SDA
/
UART3_TXD
UART3_RXD
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
/
/
/
/
PE.1
PE.0
PH.8
PH.9
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
UART1_TXD
/
UART3_nRTS
/
QSPI0_CLK
QSPI0_SS
/
/
PD.15
VDD
/
PWM0_CH5
/
TM3
/
UART1_RXD
/
UART3_nCTS
/
UART0_TXD
UART0_RXD
/
UART4_TXD
UART4_RXD
/
/
QSPI0_MISO1
QSPI0_MOSI1
/
/
/
EBI_AD14
/
/
/
PH.10
PH.11
PD.14
VSS
VSS
PWM0_CH5
/
/
EBI_AD15
EBI_nCS0
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
UART4_RXD
UART4_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
PWM0_CH4
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
/
/
/
/
/
/
UART0_nRTS
UART0_nCTS
UART4_nCTS
/
UART6_RXD
UART6_TXD
UART1_RXD
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
PWM1_CH1 / BPWM1_CH4
/
BPWM1_CH1
/
TM1
TM0
/
INT2
INT3
LQFP128
LDO_CAP
VDD
/
/
/
/
/
/
EBI_ADR16
/
I2C0_SDA
/
/
/
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART4_nRTS
/ UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
PWM0_BRAKE1
/
TM0_EXT
TM1_EXT
UART3_nRTS
UART3_nCTS
/
PWM1_CH0
PWM1_CH1 UART3_RXD
UART0_TXD USCI0_DAT0
UART0_RXD
/
UART3_TXD
/
/
USCI0_CTL1
/
SPI0_SS
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
CLKO
/
/
/
/
/
USCI0_DAT1
/
SPI0_CLK
USCI1_DAT1
USCI1_DAT0
/
/
UART3_RXD PWM0_CH3
/
UART1_nCTS
/
/ PWM1_BRAKE1
TM2_EXT
/
PWM1_CH2
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
TM3_EXT
/
PWM1_CH3
/
/
/
USCI0_CLK
PE.9
PE.8
VDD
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART4_TXD
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS
/
UART0_nCTS
USCI1_CTL0
USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
PH.7
PH.6
PH.5
PH.4
/
/
/
/
/
/
EBI_nCS1
EBI_nCS0
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
BPWM1_CH2
/
I2C1_SDA
UART7_TXD
UART7_RXD
BPWM1_CH4
BPWM1_CH5
/
UART4_RXD
/
/
/
EBI_ADR17
/
/
/
XT1_IN BPWM1_CH0
/
/
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
ADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
/
/
/
UART7_RXD
UART7_TXD
BPWM1_CH3
/
/
/
/
UART0_RXD
UART1_TXD
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0 EBI_nWRL
/
UART7_nCTS
UART7_nRTS
/
/
UART6_RXD
UART6_TXD
/
/
/
/
/
/
UART1_RXD
/
USCI1_DAT1 / EBI_nWRH
Figure 4.1-50 M032KIAAE Multi-function Pin Diagram
Pin M032KIAAE Pin Function
PB.5 / ADC0_CH5 / ACMP1_N / EBI_ADR0 / I2C0_SCL / UART5_TXD / USCI1_CTL0 / PWM0_CH0 / UART2_TXD /
TM0 / INT0
1
2
3
4
PB.4 / ADC0_CH4 / ACMP1_P1 / EBI_ADR1 / I2C0_SDA / UART5_RXD / USCI1_CTL1 / PWM0_CH1 / UART2_RXD
/ TM1 / INT1
PB.3 / ADC0_CH3 / ACMP0_N / EBI_ADR2 / I2C1_SCL / UART1_TXD / UART5_nRTS / USCI1_DAT1 / PWM0_CH2 /
PWM0_BRAKE0 / TM2 / INT2
PB.2 / ADC0_CH2 / ACMP0_P1 / EBI_ADR3 / I2C1_SDA / UART1_RXD / UART5_nCTS / USCI1_DAT0 /
PWM0_CH3 / TM3 / INT3
Sep. 29, 2020
Page 151 of 288
Rev 2.02
M031/M032
Pin M032KIAAE Pin Function
5
6
7
8
PC.12 / EBI_ADR4 / UART0_TXD / I2C0_SCL / UART6_TXD / PWM1_CH0 / ACMP0_O
PC.11 / EBI_ADR5 / UART0_RXD / I2C0_SDA / UART6_RXD / PWM1_CH1 / ACMP1_O
PC.10 / EBI_ADR6 / UART6_nRTS / UART3_TXD / PWM1_CH2
PC.9 / EBI_ADR7 / UART6_nCTS / UART3_RXD / PWM1_CH3
PB.1 / ADC0_CH1 / EBI_ADR8 / UART2_TXD / USCI1_CLK / I2C1_SCL / QSPI0_MISO1 / PWM0_CH4 / PWM1_CH4
/ PWM0_BRAKE0
9
PB.0 / ADC0_CH0 / EBI_ADR9 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / QSPI0_MOSI1 / PWM0_CH5 /
PWM1_CH5 / PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11 / ACMP0_P0 / EBI_nRD / USCI0_CLK / UART6_TXD / BPWM0_CH0 / TM0_EXT
14 PA.10 / ACMP1_P0 / EBI_nWR / USCI0_DAT0 / UART6_RXD / BPWM0_CH1 / TM1_EXT
15 PA.9 / EBI_MCLK / USCI0_DAT1 / UART1_TXD / UART7_TXD / BPWM0_CH2 / TM2_EXT
16 PA.8 / EBI_ALE / USCI0_CTL1 / UART1_RXD / UART7_RXD / BPWM0_CH3 / TM3_EXT / INT4
17 PC.13 / EBI_ADR10 / USCI0_CTL0 / UART2_TXD / BPWM0_CH4 / CLKO / ADC0_ST
18 PD.12 / EBI_nCS0 / UART2_RXD / BPWM0_CH5 / CLKO / ADC0_ST / INT5
19 PD.11 / EBI_nCS1 / UART1_TXD
20 PD.10 / UART1_RXD
21 PG.2 / EBI_ADR11 / I2C0_SMBAL / I2C1_SCL / TM0
22 PG.3 / EBI_ADR12 / I2C0_SMBSUS / I2C1_SDA / TM1
23 PG.4 / EBI_ADR13 / TM2
24 PF.11 / EBI_ADR14 / UART5_TXD / TM3
25 PF.10 / EBI_ADR15 / SPI0_I2SMCLK / UART5_RXD
26 PF.9 / EBI_ADR16 / SPI0_SS / UART5_nRTS
27 PF.8 / EBI_ADR17 / SPI0_CLK / UART5_nCTS
28 PF.7 / EBI_ADR18 / SPI0_MISO / UART4_TXD
29 PF.6 / EBI_ADR19 / SPI0_MOSI / UART4_RXD / EBI_nCS0
30 PF.14 / PWM1_BRAKE0 / PWM0_BRAKE0 / PWM0_CH4 / CLKO / TM3 / INT5
31 PF.5 / UART2_RXD / UART2_nCTS / PWM0_CH0 / BPWM0_CH4 / X32_IN / ADC0_ST
32 PF.4 / UART2_TXD / UART2_nRTS / PWM0_CH1 / BPWM0_CH5 / X32_OUT
33 PH.4 / EBI_ADR3 / UART7_nRTS / UART6_TXD
34 PH.5 / EBI_ADR2 / UART7_nCTS / UART6_RXD
35 PH.6 / EBI_ADR1 / UART7_TXD
36 PH.7 / EBI_ADR0 / UART7_RXD
37 PF.3 / EBI_nCS0 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Sep. 29, 2020
Page 152 of 288
Rev 2.02
M031/M032
Pin M032KIAAE Pin Function
38 PF.2 / EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
39 VSS
40 VDD
41 PE.8 / EBI_ADR10 / USCI1_CTL1 / UART2_TXD / PWM0_CH0 / PWM0_BRAKE0
42 PE.9 / EBI_ADR11 / USCI1_CTL0 / UART2_RXD / PWM0_CH1 / PWM0_BRAKE1
43 PE.10 / EBI_ADR12 / USCI1_DAT0 / UART3_TXD / PWM0_CH2 / PWM1_BRAKE0
44 PE.11 / EBI_ADR13 / USCI1_DAT1 / UART3_RXD / UART1_nCTS / PWM0_CH3 / PWM1_BRAKE1
45 PE.12 / EBI_ADR14 / USCI1_CLK / UART1_nRTS / PWM0_CH4
46 PE.13 / EBI_ADR15 / I2C0_SCL / UART4_nRTS / UART1_TXD / PWM0_CH5 / PWM1_CH0 / BPWM1_CH5
47 PC.8 / EBI_ADR16 / I2C0_SDA / UART4_nCTS / UART1_RXD / PWM1_CH1 / BPWM1_CH4
48 PC.7 / EBI_AD9 / UART4_TXD / UART0_nCTS / UART6_TXD / PWM1_CH2 / BPWM1_CH0 / TM0 / INT3
49 PC.6 / EBI_AD8 / UART4_RXD / UART0_nRTS / UART6_RXD / PWM1_CH3 / BPWM1_CH1 / TM1 / INT2
50 PA.7 / EBI_AD7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / BPWM1_CH2 / ACMP0_WLAT / TM2 / INT1
51 PA.6 / EBI_AD6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / BPWM1_CH3 / ACMP1_WLAT / TM3 / INT0
52 VSS
53 VDD
54 PD.15 / PWM0_CH5 / TM3 / INT1
55 PA.5 / QSPI0_MISO1 / UART0_nCTS / UART0_TXD / I2C0_SCL / UART5_TXD / BPWM0_CH5 / PWM0_CH0
PA.4 / QSPI0_MOSI1 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / UART5_RXD / BPWM0_CH4 /
PWM0_CH1
56
PA.3 / QSPI0_SS / SPI0_SS / UART4_TXD / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 /
CLKO / PWM1_BRAKE1
57
PA.2 / QSPI0_CLK / SPI0_CLK / UART4_RXD / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 /
PWM0_CH3
58
59 PA.1 / QSPI0_MISO0 / SPI0_MISO / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
60 PA.0 / QSPI0_MOSI0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
61 PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
62 PE.14 / EBI_AD8 / UART2_TXD / UART6_TXD
63 PE.15 / EBI_AD9 / UART2_RXD / UART6_RXD
64 nRESET
65 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / BPWM1_CH0 / ICE_DAT
66 PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / BPWM1_CH1 / ICE_CLK
67 PD.9 / EBI_AD7 / UART2_nCTS / UART7_TXD
68 PD.8 / EBI_AD6 / UART2_nRTS / UART7_RXD
69 PC.5 / EBI_AD5 / QSPI0_MISO1 / UART2_TXD / I2C1_SCL / UART4_TXD / PWM1_CH0
70 PC.4 / EBI_AD4 / QSPI0_MOSI1 / UART2_RXD / I2C1_SDA / UART4_RXD / PWM1_CH1
Sep. 29, 2020
Page 153 of 288
Rev 2.02
M031/M032
Pin M032KIAAE Pin Function
71 PC.3 / EBI_AD3 / QSPI0_SS / UART2_nRTS / I2C0_SMBAL / UART3_TXD / PWM1_CH2
72 PC.2 / EBI_AD2 / QSPI0_CLK / UART2_nCTS / I2C0_SMBSUS / UART3_RXD / PWM1_CH3
73 PC.1 / EBI_AD1 / QSPI0_MISO0 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_O / ADC0_ST
74 PC.0 / EBI_AD0 / QSPI0_MOSI0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_O
75 VSS
76 VDD
77 PG.9 / EBI_AD0 / BPWM0_CH5
78 PG.10 / EBI_AD1 / BPWM0_CH4
79 PG.11 / EBI_AD2 / UART7_TXD / BPWM0_CH3
80 PG.12 / EBI_AD3 / UART7_RXD / BPWM0_CH2
81 PG.13 / EBI_AD4 / UART6_TXD / BPWM0_CH1
82 PG.14 / EBI_AD5 / UART6_RXD / BPWM0_CH0
83 PG.15 / CLKO / ADC0_ST
84 PD.7 / UART1_TXD / I2C0_SCL / USCI1_CLK
85 PD.6 / UART1_RXD / I2C0_SDA / USCI1_DAT1
86 PD.5 / I2C1_SCL / USCI1_DAT0
87 PD.4 / USCI0_CTL0 / I2C1_SDA / USCI1_CTL1
88 PD.3 / EBI_AD10 / USCI0_CTL1 / SPI0_SS / UART3_nRTS / USCI1_CTL0 / UART0_TXD
89 PD.2 / EBI_AD11 / USCI0_DAT1 / SPI0_CLK / UART3_nCTS / UART0_RXD
90 PD.1 / EBI_AD12 / USCI0_DAT0 / SPI0_MISO / UART3_TXD
91 PD.0 / EBI_AD13 / USCI0_CLK / SPI0_MOSI / UART3_RXD / TM2
92 PD.13 / EBI_AD10 / SPI0_I2SMCLK
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7 / UART5_TXD / PWM0_CH0 / BPWM0_CH5
98 PE.6 / USCI0_CTL0 / UART5_RXD / PWM0_CH1 / BPWM0_CH4
99 PE.5 / EBI_nRD / USCI0_CTL1 / UART6_TXD / UART7_nRTS / PWM0_CH2 / BPWM0_CH3
100 PE.4 / EBI_nWR / USCI0_DAT1 / UART6_RXD / UART7_nCTS / PWM0_CH3 / BPWM0_CH2
101 PE.3 / EBI_MCLK / USCI0_DAT0 / UART6_nRTS / UART7_TXD / PWM0_CH4 / BPWM0_CH1
102 PE.2 / EBI_ALE / USCI0_CLK / UART6_nCTS / UART7_RXD / PWM0_CH5 / BPWM0_CH0
103 VSS
104 VDD
Sep. 29, 2020
Page 154 of 288
Rev 2.02
M031/M032
Pin M032KIAAE Pin Function
105 PE.1 / EBI_AD10 / QSPI0_MISO0 / UART3_TXD / I2C1_SCL / UART4_nCTS
106 PE.0 / EBI_AD11 / QSPI0_MOSI0 / UART3_RXD / I2C1_SDA / UART4_nRTS
107 PH.8 / EBI_AD12 / QSPI0_CLK / UART3_nRTS / UART1_TXD
108 PH.9 / EBI_AD13 / QSPI0_SS / UART3_nCTS / UART1_RXD
109 PH.10 / EBI_AD14 / QSPI0_MISO1 / UART4_TXD / UART0_TXD
110 PH.11 / EBI_AD15 / QSPI0_MOSI1 / UART4_RXD / UART0_RXD / PWM0_CH5
111 PD.14 / EBI_nCS0 / SPI0_I2SMCLK / USCI0_CTL0 / PWM0_CH4
112 VSS
113 LDO_CAP
114 VDD
115 PC.14 / EBI_AD11 / SPI0_I2SMCLK / USCI0_CTL0 / QSPI0_CLK / TM1
PB.15 / ADC0_CH15 / EBI_AD12 / SPI0_SS / USCI0_CTL1 / UART0_nCTS / UART3_TXD / PWM1_CH0 / TM0_EXT /
PWM0_BRAKE1
116
117
118
119
PB.14 / ADC0_CH14 / EBI_AD13 / SPI0_CLK / USCI0_DAT1 / UART0_nRTS / UART3_RXD / PWM1_CH1 /
TM1_EXT / CLKO
PB.13 / ADC0_CH13 / ACMP0_P3 / ACMP1_P3 / EBI_AD14 / SPI0_MISO / USCI0_DAT0 / UART0_TXD /
UART3_nRTS / PWM1_CH2 / TM2_EXT
PB.12 / ADC0_CH12 / ACMP0_P2 / ACMP1_P2 / EBI_AD15 / SPI0_MOSI / USCI0_CLK / UART0_RXD /
UART3_nCTS / PWM1_CH3 / TM3_EXT
120 AVDD
121 VREF
122 AVSS
123 PB.11 / ADC0_CH11 / EBI_ADR16 / UART0_nCTS / UART4_TXD / I2C1_SCL / SPI0_I2SMCLK / BPWM1_CH0
124 PB.10 / ADC0_CH10 / EBI_ADR17 / USCI1_CTL0 / UART0_nRTS / UART4_RXD / I2C1_SDA / BPWM1_CH1
125 PB.9 / ADC0_CH9 / EBI_ADR18 / USCI1_CTL1 / UART0_TXD / UART1_nCTS / UART7_TXD / BPWM1_CH2
126 PB.8 / ADC0_CH8 / EBI_ADR19 / USCI1_CLK / UART0_RXD / UART1_nRTS / UART7_RXD / BPWM1_CH3
PB.7 / ADC0_CH7 / EBI_nWRL / USCI1_DAT0 / UART1_TXD / EBI_nCS0 / BPWM1_CH4 / PWM1_BRAKE0 /
PWM1_CH4 / INT5 / ACMP0_O
127
PB.6 / ADC0_CH6 / EBI_nWRH / USCI1_DAT1 / UART1_RXD / EBI_nCS1 / BPWM1_CH5 / PWM1_BRAKE1 /
PWM1_CH5 / INT4 / ACMP1_O
128
Table 4.1-38 M032KIAAE Multi-function Pin Table
Sep. 29, 2020
Page 155 of 288
Rev 2.02
M031/M032
4.2 Pin Mapping
Different part number with the same package might have different function. Please refer to the
selection guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfig.
Corresponding Part Number: M031xB, M031xC, M031xD, M031xE, M031xG, M031xI, M032xC,
M032xD, M032xE, M032xG, M032xI series.
M031 Series
M032 Series
Pin Name
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
PB.5
PB.4
PB.3
PB.2
PC.12
PC.11
PC.10
PC.9
PB.1
PB.0
VSS
8
9
12
13
14
15
1
2
3
4
1
2
3
4
2
3
4
5
1
12
13
14
15
1
2
3
4
1
2
3
4
2
3
4
5
1
2
2
10
11
3
3
4
4
5
5
6
6
7
7
8
8
16
17
5
6
5
6
6
7
9
16
17
5
6
5
6
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VDD
PA.11
PA.10
PA.9
PA.8
PC.13
PD.12
PD.11
PD.10
PG.2
PG.3
PG.4
PF.11
PF.10
PF.9
7
8
8
9
7
8
8
9
9
10
11
9
10
11
10
10
PF.8
PF.7
PF.6
12
12
Sep. 29, 2020
Page 156 of 288
Rev 2.02
M031/M032
M031 Series
M032 Series
Pin Name
PF.14
PF.5
PF.4
PH.4
PH.5
PH.6
PH.7
PF.3
PF.2
VSS
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
13
14
15
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
13
14
15
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
7
8
11
12
7
8
11
12
12
13
18
19
9
13
14
16
17
11
12
18
19
9
13
14
16
17
10
10
VDD
PE.8
PE.9
PE.10
PE.11
PE.12
PE.13
PC.8
PC.7
PC.6
PA.7
PA.6
VSS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
18
19
20
21
22
23
24
25
26
27
28
29
30
31
15
16
15
16
VDD
PD.15
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
PF.15
PE.14
PE.15
17
18
19
20
21
22
23
17
18
19
20
21
22
23
14
15
16
17
20
21
22
23
11
12
13
14
15
13
14
15
16
20
21
22
23
11
12
13
14
15
Sep. 29, 2020
Page 157 of 288
Rev 2.02
M031/M032
M031 Series
M032 Series
Pin Name
nRESET
PF.0
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
18
19
24
25
16
17
24
25
32
33
64
65
17
18
24
25
16
17
24
25
32
33
64
65
ICE_DAT
PF.1
20
26
18
26
34
66
19
26
18
26
34
66
ICE_CLK
PD.9
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
PD.8
PC.5
27
28
29
30
31
32
35
36
37
38
39
40
27
28
29
30
31
32
35
36
37
38
39
40
PC.4
PC.3
PC.2
PC.1
27
28
19
20
27
28
19
20
PC.0
VSS
VDD
PG.9
PG.10
PG.11
PG.12
PG.13
PG.14
PG.15
PD.7
PD.6
PD.5
PD.4
PD.3
41
42
43
44
41
42
43
44
PD.2
PD.1
PD.0
PD.13
NC
NC
NC
Sep. 29, 2020
Page 158 of 288
Rev 2.02
M031/M032
M031 Series
M032 Series
Pin Name
NC
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
PA.12
1
2
3
4
21
22
23
24
33
34
35
36
45
46
47
48
93
94
95
96
PA.13
PA.14
PA.15
USB_VBUS
USB_D-
USB_D+
20
1
1
2
3
21
22
23
33
34
35
45
46
47
93
94
95
2
USB_VDD33_CAP
3
4
24
36
48
96
PE.7
PE.6
97
97
98
98
PE.5
99
99
PE.4
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
PE.3
PE.2
VSS
VDD
PE.1
PE.0
PH.8
PH.9
PH.10
PH.11
PD.14
VSS
1
2
3
5
6
7
25
26
27
37
38
39
40
41
42
43
44
45
49
50
51
52
53
54
55
56
57
58
4
5
6
5
6
7
25
26
27
37
38
39
40
41
42
43
44
45
49
50
51
52
53
54
55
56
57
58
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
28
29
30
31
32
28
29
30
31
32
4
5
6
7
8
9
7
8
8
9
10
11
9
10
11
10
Sep. 29, 2020
Page 159 of 288
Rev 2.02
M031/M032
M031 Series
M032 Series
Pin Name
AVSS
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
46
59
60
61
62
63
64
1
122
123
124
125
126
127
128
46
59
60
61
62
63
64
1
122
123
124
125
126
127
128
PB.11
PB.10
PB.9
PB.8
PB.7
47
48
47
48
PB.6
Sep. 29, 2020
Page 160 of 288
Rev 2.02
M031/M032
4.3
Pin Function Description
Group
Pin Name
Type Description
ACMP0_N
A
O
A
A
A
A
I
Analog comparator 0 negative input pin.
ACMP0_O
Analog comparator 0 output pin.
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
Analog comparator 1 output pin.
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
ADC0 channel 0 analog input.
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
ACMP0
A
O
A
A
A
A
I
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
ADC0_CH12
ADC0_CH13
ADC0_CH14
ADC0_CH15
ADC0_ST
ACMP1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I
ADC0 channel 1 analog input.
ADC0 channel 2 analog input.
ADC0 channel 3 analog input.
ADC0 channel 4 analog input.
ADC0 channel 5 analog input.
ADC0 channel 6 analog input.
ADC0 channel 7 analog input.
ADC0
ADC0 channel 8 analog input.
ADC0 channel 9 analog input.
ADC0 channel 10 analog input.
ADC0 channel 11 analog input.
ADC0 channel 12 analog input.
ADC0 channel 13 analog input.
ADC0 channel 14 analog input.
ADC0 channel 15 analog input.
ADC0 external trigger input pin.
BPWM0_CH0
I/O BPWM0 channel 0 output/capture input.
I/O BPWM0 channel 1 output/capture input.
I/O BPWM0 channel 2 output/capture input.
BPWM0 BPWM0_CH1
BPWM0_CH2
Sep. 29, 2020
Page 161 of 288
Rev 2.02
M031/M032
Group
Pin Name
BPWM0_CH3
BPWM0_CH4
BPWM0_CH5
BPWM1_CH0
BPWM1_CH1
BPWM1_CH2
BPWM1_CH3
BPWM1_CH4
BPWM1_CH5
CLKO
Type Description
I/O BPWM0 channel 3 output/capture input.
I/O BPWM0 channel 4 output/capture input.
I/O BPWM0 channel 5 output/capture input.
I/O BPWM1 channel 0 output/capture input.
I/O BPWM1 channel 1 output/capture input.
I/O BPWM1 channel 2 output/capture input.
I/O BPWM1 channel 3 output/capture input.
I/O BPWM1 channel 4 output/capture input.
I/O BPWM1 channel 5 output/capture input.
BPWM1
CLKO
O
Clock Out
EBI_AD0
I/O EBI address/data bus bit 0.
I/O EBI address/data bus bit 1.
I/O EBI address/data bus bit 2.
I/O EBI address/data bus bit 3.
I/O EBI address/data bus bit 4.
I/O EBI address/data bus bit 5.
I/O EBI address/data bus bit 6.
I/O EBI address/data bus bit 7.
I/O EBI address/data bus bit 8.
I/O EBI address/data bus bit 9.
I/O EBI address/data bus bit 10.
I/O EBI address/data bus bit 11.
I/O EBI address/data bus bit 12.
I/O EBI address/data bus bit 13.
I/O EBI address/data bus bit 14.
I/O EBI address/data bus bit 15.
EBI_AD1
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
EBI_AD14
EBI_AD15
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
EBI_ADR4
EBI_ADR5
EBI_ADR6
EBI_ADR7
EBI_ADR8
EBI_ADR9
EBI
O
O
O
O
O
O
O
O
O
O
EBI address bus bit 0.
EBI address bus bit 1.
EBI address bus bit 2.
EBI address bus bit 3.
EBI address bus bit 4.
EBI address bus bit 5.
EBI address bus bit 6.
EBI address bus bit 7.
EBI address bus bit 8.
EBI address bus bit 9.
Sep. 29, 2020
Page 162 of 288
Rev 2.02
M031/M032
Group
Pin Name
Type Description
EBI address bus bit 10.
EBI_ADR10
EBI_ADR11
EBI_ADR12
EBI_ADR13
EBI_ADR14
EBI_ADR15
EBI_ADR16
EBI_ADR17
EBI_ADR18
EBI_ADR19
EBI_ALE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
EBI address bus bit 11.
EBI address bus bit 12.
EBI address bus bit 13.
EBI address bus bit 14.
EBI address bus bit 15.
EBI address bus bit 16.
EBI address bus bit 17.
EBI address bus bit 18.
EBI address bus bit 19.
EBI address latch enable output pin.
EBI external clock output pin.
EBI chip select 0 output pin.
EBI chip select 1 output pin.
EBI read enable output pin.
EBI write enable output pin.
EBI high byte write enable output pin
EBI low byte write enable output pin.
EBI_MCLK
EBI_nCS0
EBI_nCS1
EBI_nRD
EBI_nWR
EBI_nWRH
EBI_nWRL
PA.x~PH.x
I2C0_SCL
I2C0_SDA
I2C0_SMBAL
I2C0_SMBSUS
I2C1_SCL
I2C1_SDA
ICE_CLK
GPIO
I2C0
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
I/O I2C0 data input/output pin.
O
O
I2C0 SMBus SMBALTER pin
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I/O I2C1 clock pin.
I2C1
ICE
I/O I2C1 data input/output pin.
Serial wired debugger clock pin
I
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin
Serial wired debugger data pin
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin
External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial
state.
ICE_DAT
nRESET
I/O
I
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET
pin.
INT0
INT1
INT3
INT4
INT5
PWM0
INT0
I
I
I
I
I
I
External interrupt 0 input pin.
External interrupt 1 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
PWM0 Brake 0 input pin.
INT1
INT3
INT4
INT5
PWM0_BRAKE0
Sep. 29, 2020
Page 163 of 288
Rev 2.02
M031/M032
Group
Pin Name
Type Description
PWM0_BRAKE1
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM1_BRAKE0
PWM1_BRAKE1
PWM1_CH0
PWM1_CH1
PWM1_CH2
PWM1_CH3
PWM1_CH4
PWM1_CH5
VDD
I
PWM0 Brake 1 input pin.
I/O PWM0 channel 0 output/capture input.
I/O PWM0 channel 1 output/capture input.
I/O PWM0 channel 2 output/capture input.
I/O PWM0 channel 3 output/capture input.
I/O PWM0 channel 4 output/capture input.
I/O PWM0 channel 5 output/capture input.
I
I
PWM1 Brake 0 input pin.
PWM1 Brake 1 input pin.
I/O PWM1 channel 0 output/capture input.
I/O PWM1 channel 1 output/capture input.
I/O PWM1 channel 2 output/capture input.
I/O PWM1 channel 3 output/capture input.
I/O PWM1 channel 4 output/capture input.
I/O PWM1 channel 5 output/capture input.
PWM1
P
P
P
P
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
VSS
Ground pin for digital circuit.
AVDD
Power supply for internal analog circuit.
Ground pin for analog circuit.
Power
AVSS
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
VREF
A
A
LDO output pin.
Note: This pin needs to be connected with a 1uF capacitor.
LDO_CAP
QSPI0_CLK
QSPI0_MISO0
QSPI0_MISO1
QSPI0_MOSI0
QSPI0_MOSI1
QSPI0_SS
SPI0_CLK
SPI0_I2SMCLK
SPI0_MISO
SPI0_MOSI
SPI0_SS
I/O Quad SPI0 serial clock pin.
I/O Quad SPI0 MISO0 (Master In, Slave Out) pin.
I/O Quad SPI0 MISO1 (Master In, Slave Out) pin.
I/O Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I/O Quad SPI0 MOSI1 (Master Out, Slave In) pin.
I/O Quad SPI0 slave select pin.
QSPI0
I/O SPI0 serial clock pin.
I/O SPI0 I2S master clock output pin
SPI0
I/O SPI0 MISO (Master In, Slave Out) pin.
I/O SPI0 MOSI (Master Out, Slave In) pin.
I/O SPI0 slave select pin.
TM0
I/O Timer0 event counter input/toggle output pin.
I/O Timer0 external capture input/toggle output pin.
I/O Timer1 event counter input/toggle output pin.
TM0
TM1
TM0_EXT
TM1
Sep. 29, 2020
Page 164 of 288
Rev 2.02
M031/M032
Group
Pin Name
Type Description
TM1_EXT
I/O Timer1 external capture input/toggle output pin.
I/O Timer2 event counter input/toggle output pin.
I/O Timer2 external capture input/toggle output pin.
I/O Timer3 event counter input/toggle output pin.
I/O Timer3 external capture input/toggle output pin.
TM2
TM2
TM3
TM2_EXT
TM3
TM3_EXT
UART0_RXD
UART0_TXD
UART0_nCTS
UART0_nRTS
UART1_RXD
UART1_TXD
UART1_nCTS
UART1_nRTS
UART2_RXD
UART2_TXD
UART2_nCTS
UART2_nRTS
UART3_RXD
UART3_TXD
UART3_nCTS
UART3_nRTS
UART4_RXD
UART4_TXD
UART4_nCTS
UART4_nRTS
UART5_RXD
UART5_TXD
UART5_nCTS
UART5_nRTS
UART6_RXD
UART6_TXD
UART6_nCTS
UART6_nRTS
UART7_RXD
UART7_TXD
UART7_nCTS
I
O
I
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART0 clear to Send input pin.
UART0 request to Send output pin.
UART1 data receiver input pin.
UART1 data transmitter output pin.
UART1 clear to Send input pin.
UART1 request to Send output pin.
UART2 data receiver input pin.
UART2 data transmitter output pin.
UART2 clear to Send input pin.
UART2 request to Send output pin.
UART3 data receiver input pin.
UART3 data transmitter output pin.
UART3 clear to Send input pin.
UART3 request to Send output pin.
UART4 data receiver input pin.
UART4 data transmitter output pin.
UART4 clear to Send input pin.
UART4 request to Send output pin.
UART5 data receiver input pin.
UART5 data transmitter output pin.
UART5 clear to Send input pin.
UART5 request to Send output pin.
UART6 data receiver input pin.
UART6 data transmitter output pin.
UART6 clear to Send input pin.
UART6 request to Send output pin.
UART7 data receiver input pin.
UART7 data transmitter output pin.
UART7 clear to Send input pin.
UART0
UART1
UART2
UART3
UART4
UART5
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
UART6
UART7
O
I
O
I
Sep. 29, 2020
Page 165 of 288
Rev 2.02
M031/M032
Group
Pin Name
Type Description
UART7_nRTS
USB_VBUS
USB_D-
O
P
A
A
A
UART7 request to Send output pin.
Power supply from USB host or HUB.
USB differential signal D-.
USB
USB_D+
USB differential signal D+.
USB_VDD33_CAP
USCI0_CLK
USCI0_CTL0
USCI0_CTL1
USCI0_DAT0
USCI0_DAT1
USCI1_CLK
USCI1_CTL0
USCI1_CTL1
USCI1_DAT0
USCI1_DAT1
X32_IN
Internal power regulator output 3.3V decoupling pin.
I/O USCI0 clock pin.
I/O USCI0 control 0 pin.
I/O USCI0 control 1 pin.
I/O USCI0 data 0 pin.
I/O USCI0 data 1 pin.
I/O USCI1 clock pin.
I/O USCI1 control 0 pin.
I/O USCI1 control 1 pin.
I/O USCI1 data 0 pin.
I/O USCI1 data 1 pin.
USCI0
USCI1
I
External 32.768 kHz crystal input pin.
X32
XT1
X32_OUT
O
I
External 32.768 kHz crystal output pin.
XT1_IN
External 4~24 MHz (high speed) crystal input pin.
External 4~24 MHz (high speed) crystal output pin.
XT1_OUT
O
Sep. 29, 2020
Page 166 of 288
Rev 2.02
M031/M032
5 BLOCK DIAGRAM
USB*: Only supported in the M032 series.
Figure 5-1 NuMicro® M031/M032 Block Diagram
Sep. 29, 2020
Page 167 of 288
Rev 2.02
M031/M032
6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M profile
processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is
entered as a result of an exception. An exception return can only be issued in Handler mode. Thread
mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows
the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
– Arm® 6-M Thumb® instruction set
– Thumb-2 technology
– Arm® 6-M compliant 24-bit SysTick timer
– A 32-bit hardware multiplier
– System interface supported with little-endian data accesses
– Ability to have deterministic, fixed-latency, interrupt handling
– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
– C Application Binary Interface compliant exception model. This is the Armv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use
of pure C functions as interrupt handlers
– Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
– 32 external interrupt inputs, each with four levels of priority
Sep. 29, 2020
Page 168 of 288
Rev 2.02
M031/M032
– Dedicated Non-maskable Interrupt (NMI) input
– Supports for both level-sensitive and pulse-sensitive interrupt lines
– Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Debug support:
– Four hardware breakpoints
– Two watchpoints
– Program Counter Sampling Register (PCSR) for non-intrusive code profiling
– Single step and vector catch capabilities
Bus interfaces:
– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
– Single 32-bit slave port that supports the DAP (Debug Access Port)
Sep. 29, 2020
Page 169 of 288
Rev 2.02
M031/M032
6.2 Clock Controller
6.2.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M0 core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~32
MHz external high speed crystal (HXT), 48 MHz internal high speed RC oscillator (HIRC) and
Programmable PLL output clock frequency (PLLFOUT) to reduce the overall system power
consumption.Figure 6.2-1 and Figure 6.2-2 shows the clock generator and the overview of the clock
source control.
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HIRC
48MHz
HXT
4~32MHz
LXT
32.768 kHz
LIRC
38.4 kHz
PCLK0
PCLK1
ACMP
/1,/2,/4,/8,/16
I2C0
PWM0
BPWM0
TMR0
ADC
I2C1
HIRC
1/4
1
0
PLLFOUT
PLL FOUT
HXT
PWM1
BPWM1
TMR2
TMR3
UART1
UART3
UART5
UART7
SPI0
TMR1
CLK_PLLCTL[19]
UART0
UART2
UART4
UART6
WDT
CPU
CRC
EBI
HIRC
111
011
010
001
000
LIRC
FMC
PDMA
SRAM
HDIV
PLLFOUT
HCLK
1/(HCLKDIV+1)
LXT
HXT
QSPI0
USCI0
USBD
USCI1
RTC
CLK_CLKSEL0[2:0]
/1,/2,/4,/8,/16
LIRC
11
10
01
LIRC
11
10
HCLK
1/2048
LXT
WDT
WWDT
HCLK
1/2048
CLK_CLKSEL1[3:2]
CLK_CLKSEL1[1:0]
LIRC
LIRC
101
101
100
011
010
001
000
PCLK0/PCLK1
HIRC
PCLK0/PCLK1
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(UART3DIV+1)
UART0
UART1
UART2
UART3
1/(UART4DIV+1)
UART4
UART5
UART6
UART7
100
011
010
001
000
HIRC
LXT
1/(UART5DIV+1)
1/(UART6DIV+1)
1/(UART7DIV+1)
LXT
PLLOUT
HXT
PLLOUT
HXT
CLK_CLKSEL1[26:24]
CLK_CLKSEL1[30:28]
CLK_CLKSEL3[26:24]
CLK_CLKSEL3[30:28]
CLK_CLKSEL3[18:16]
CLK_CLKSEL3[22:20]
CLK_CLKSEL3[10: 8]
CLK_CLKSEL3[14:12]
USBDSEL
(CLK_CLKSEL0[8])
HIRC
1/2
111
011
010
001
000
CPUCLK
1
HCLK
1/2
HIRC
48MHz
SysTick
0
1
HXT
1/2
USB1.1 Device
Controller
0
PLLFOUT
/(USBDIV + 1)
LXT
SYST_CTRL[2]
HXT
CLK_CLKSEL0[5:3]
DIV1EN
(CLK_CLKOCTL[5])
CLK1HZEN
(CLK_CLKOCTL[6])
PLLFOUT
HIRC
LIRC
110
HIRC
PCLK1
PLLFOUT
HXT
101
100
011
010
11
/2(CLK_CLKOCTL[3:0]+1)
0
1
HIRC
HCLK
LXT
10
01
00
0
CLKO
1/(ADCDIV + 1)
ADC
1
001
000
HXT
CLK_CLKSEL1[6:4]
LIRC
ADCSEL
(CLKSEL2[21:20])
0
1
1 Hz clock from RTC
/32768
LXT
RTCSEL(CLK_CLKSEL3[8])
Figure 6.2-1 Clock Generator Global View Diagram (1/2)
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HIRC
LIRC
HIRC
LIRC
111
101
011
010
001
000
111
101
011
010
001
000
TM0/TM1
TM2/TM3
TMR0
TMR1
TMR2
TMR3
PCLK0
LXT
PCLK1
LXT
HXT
HXT
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
HIRC
11
HIRC
11
PCLK1
10
PCLK1
10
1/(SPI0_CLKDIV[8:0]+1)
SPI0
1/(QSPI0_CLKDIV[8:0]+1)
QSPI0
PLLFOUT
01
PLLFOUT
01
HXT
00
HXT
00
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[3:2]
PCLK0
PCLK1
1
0
1
0
PWM 0
PWM 1
PLLFOUT
PLLFOUT
CLK_CLKSEL2[0]
CLK_CLKSEL2[1]
PCLK0
PCLK1
1
0
1
0
BPWM 0
BPWM 1
PLLFOUT
PLLFOUT
CLK_CLKSEL2[8]
CLK_CLKSEL2[9]
LIRC
LXT
1
0
RTC
CLK_CLKSEL3[8]
Figure 6.2-2 Clock Generator Global View Diagram (2/2)
6.2.2
Clock Generator
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~32 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~32 MHz external high speed crystal (HXT) or 48 MHz internal high speed
oscillator (HIRC/4)
48 MHz internal high speed RC oscillator (HIRC)
38.4 kHz internal low speed RC oscillator (LIRC)
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LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
(LXT)
LXT
X32_OUT
XT1_IN
HXTEN (CLK_PWRCTL[0])
HXT
External 4~32
MHz Crystal
(HXT)
PLLSRC (CLK_PLLCTL[19])
XT1_OUT
0
1
HIRCEN (CLK_PWRCTL[2])
PLL FOUT
PLL
/4
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 38.4
kHz Oscillator
(LIRC)
Figure 6.2-3 Clock Generator Block Diagram
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6.2.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.2-4
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Figure 6.2-4 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN (CLK_CLKDCTL[5]) is
set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.2-5.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.2-5 HXT Stop Protect Procedure
When LXT clock detector is enabled, the system clock will auto switch to LIRC if LXT clock stop being
detected when system clock source comes from LXT. If LXT clock stop condition is detected, the
LXTFIF (CLK_CLKDSTS[1]) is set to 1 and chip will enter interrupt if LXTFIEN (CLK_CLKDCTL[13]) is
set to 1. User can trying to recover LXT by disable LXT and enable LXT again to check if the clock
stable bit is set to 1 or not. If LXT clock stable bit is set to 1, it means LXT is recover to oscillate after
re-enable action and user can switch system clock to LXT again.
The LXT clock stop detect and system clock switch to LIRC procedure is shown in Figure 6.2-6.
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Set LXTFDEN To enable
LXT clock detector
NO
LXTFIF = 1?
YES
System clock source =
System clock keep
original clock
NO
“LXT ?
YES
Switch system clock to
LIRC
Figure 6.2-6 LXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.2-7.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Figure 6.2-7 SysTick Clock Control Block Diagram
Peripherals Clock
6.2.4
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSELx register description.
6.2.5
Power-down Mode Clock
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When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 38.4 kHz internal low speed RC oscillator (LIRC) clock
– 32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.2.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0
to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.
CLKOEN
Enable
(CLK_CLKOCTL[4])
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
PLL
CLK1HZEN
110
(CLK_CLKOCTL[6])
0000
0001
:
LIRC
HIRC
100
011
010
001
000
16 to 1
MUX
0
1
:
CLKO
0
1110
HCLK
LXT
1111
1
HXT
RTCSEL(CLK_CLKSEL3[8])
CLKOSEL (CLK_CLKSEL1[6:4])
LIRC
LXT
0
1
1 Hz clock from RTC
/32768
Figure 6.2-8 Clock Output Block Diagram
6.2.7
USB Clock Source
The clock source of USBD is generated from 48 MHz HIRC or programmable PLL output. The
generated clocks are shown in Figure 6.2-9.
USBDIV is the clock divider output frequency, the output formula is
(PLLFOUT frequency) / (USBDIV + 1).
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PLLFOUT
/(USBDIV + 1)
USB Device
Controller
HIRC48M
USBDSEL
Figure 6.2-9 USBD Clock Source
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6.3 System Manager
6.3.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.3.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
– nRESET glitch filter time 32us
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Glitch Filter
32 us
nRESET
~50k ohm
@3.3v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.3-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there are
small differences between each reset source and they are listed in Table 6.3-1.
Reset Sources
POR
0x001
nRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[16])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
LXTSELXT
(CLK_PWRCTL[24])
LXTGAIN
-
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(CLK_PWRCTL[25:26])
WDTCKEN
0x1
-
0x1
-
-
-
0x1
-
-
-
(CLK_APBCLK0[0])
HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
-
Reload
base
CONFIG0
-
-
-
on base on base on base on
on
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other Peripheral
Registers
Reset Value
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FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.3-1 Reset Value of Registers
6.3.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Table 6.3-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.3-2 nRESET Reset Waveform
6.3.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is
ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.3-3
shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.3-3 Power-on Reset (POR) Waveform
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6.3.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.3-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.3-4 Low Voltage Reset (LVR) Waveform
6.3.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.3-5 shows the Brown-out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.3-5 Brown-out Detector (BOD) Waveform
6.3.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.3.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.3.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
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6.3.3
System Power Distribution
In this chip, power distribution is divided into three segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be
located close to the corresponding pin. Figure 6.3-6 shows the NuMicro® M031 power distribution.
D+
D-
USB
Transceiver
Analog
Comparator
12-bit ADC
AVDD
AVSS
VDD33
1uF
3.3V
Brown-out
Detector
5V to 3.3V
LDO
Low Voltage Reset
VBUS
SRAM
Flash
Digital Logic
1.8V
LDO_CAP
1uF
X32_IN
(PF.5)
32.768 kHz
crystal
oscillator
48 MHz
HIRC48
Oscillator
38.4 kHz
LIRC
Oscillator
PLL
POR18
X32_OUT
(PF.4)
XT1_IN
(PF.3)
4~32 MHz
crystal oscillator
VDD to 1.8V
LDO
Power On
Control
POR33
IO Cell
XT1_OUT
(PF.2)
Figure 6.3-6 NuMicro® M031 Power Distribution Diagram
Power Modes and Wake-up Sources
6.3.4
The M031/M032 series has power manager unit to support several operating modes for saving power.
Table 6.3-2 lists all power mode in the M031/M032 series.
Mode
CPU Operating Maximum
Speed (MHz)
LDO_CAP(V) Clock Disable
Normal mode
72 MHz at 2.0V-3.6V
48 MHz at 1.8V-3.6V
1.8
All clocks are disabled by control register.
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Idle mode
CPU enter Sleep mode
1.8
1.8
Only CPU clock is disabled.
Power-down mode
CPU enters Power-down
mode
Most clocks are disabled except LIRC/LXT, and
only WDT/Timer/UART/RTC peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Table 6.3-2 Power Mode Table
There are different power mode entry settings and leaving condition for each power mode. Table 6.3-3
shows the entry setting for each power mode. When chip power-on, chip is running in normal mode.
User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT:[7]) and execute
WFI instruction.
Register/Instruction
Mode
SLEEPDEEP
(SCR[2])
PDEN
CPU Run WFI Instruction
(CLK_PWRCTL[7])
Normal mode
0
0
0
0
NO
Idle mode
YES
(CPU enter Sleep mode)
Power-down mode
1
1
YES
(CPU enters Deep Sleep
mode)
Table 6.3-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.3-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD,
GPIO, EINT, USCI, USBD,
ACMP, and RTC
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.3-4 Power Mode Difference Table
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System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC , HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP (SCS_SCR[2]) = 1
Wake-up events
occur
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[6]) = 1
3. CPU executes WFI
Idle Mode
CPU Clock OFF
HXT, HIRC, LXT , LIRC , HCLK, PCLK ON
Flash Halt
Power-down Mode
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.3-7 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode.
2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If UART clock source is selected as LXT and LXT is on.
6. If RTC clock source is selected as LIRC/LXT and LIRC/LXT is on.
Normal Mode
ON
Idle Mode
ON
Power-Down Mode
HXT (4~32 MHz XTL)
HIRC48 (48 MHz OSC)
LXT (32768 Hz XTL)
LIRC (38.4 kHz OSC)
PLL
Halt
Halt
ON
ON
ON
ON
ON/OFF1
ON/OFF2
Halt
ON
ON
ON/OFF
ON
ON/OFF
ON
LDO
ON
CPU
ON
Halt
ON
Halt
HCLK/PCLK
SRAM retention
FLASH
ON
Halt
ON
ON
ON
ON
ON
Halt
GPIO
ON
ON
Halt
PDMA
ON
ON
Halt
TIMER
ON
ON
ON/OFF3
Halt
PWM
ON
ON
BPWM
ON
ON
Halt
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WDT
WWDT
UART
USCI
I2C
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON/OFF4
Halt
ON/OFF5
Halt
Halt
SPI
Halt
QSPI
USBD
ADC
Halt
Halt
Halt
ACMP
RTC
Halt
ON/OFF6
Table 6.3-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, USCI, BOD, GPIO, USBD, ACMP, and RTC.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.3-5 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear (SYS_BODCTL[4]).
INT
External Interrupt
GPIO Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
TIMER
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
Timer Interrupt
WDT
RTC
WDT Interrupt
Alarm Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear ALMIF (RTC_INTSTS[0]).
After software writes 1 to clear TICKIF (RTC_INTSTS[1]).
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
Time Tick Interrupt
nCTS wake-up
Incoming Data wake-up
Received FIFO Threshold
Wake-up
After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]).
UART0/1/4/5
RS-485 AAD Mode Wake-up After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]).
Received FIFO Threshold
After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]).
Time-out Wake-up
nCTS wake-up
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
UART2/3/6/7
Incoming Data wake-up
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CTS Toggle
Data Toggle
Data toggle
After software writes 1 to clear WKF (UUART_WKSTS[0]).
After software writes 1 to clear WKF (UUART_WKSTS[0]).
After software writes 1 to clear WKF (UI2C_WKSTS[0]).
USCI UART
USCI I2C
After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], and then
writes 1 to clear WKF (UI2C_WKSTS[0]).
Address match
USCI SPI
I2C
SS Toggle
After software writes 1 to clear WKF (USPI_WKSTS[0]).
After software writes 1 to clear WKIF (I2C_WKSTS[0]).
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
Address match
Remote Wake-up
USBD
ACMP
Comparator Power-Down After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1
Wake-Up Interrupt (ACMP_STATUS[9]).
Table 6.3-6 Condition of Entering Power-down Mode Again
System Memory Map
6.3.5
The NuMicro® M031/M032 series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown inTable 6.3-7. The detailed register definition, memory
space, and programming will be described in the following sections for each on-chip peripheral. The
M031/M032 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0007_FFFF
0x2000_0000 – 0x2001_7FFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
SRAM0_BA
EXTMEM_BA
FLASH Memory Space (512 Kbytes)
SRAM Memory Space (96 Kbytes)
External Memory Space (256 Mbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4001_0000 – 0x4001_0FFF
0x4001_4000 – 0x4001_7FFF
0x4003_1000 – 0x4003_1FFF
SYS_BA
CLK_BA
NMI_BA
GPIO_BA
PDMA_BA
FMC_BA
EBI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
External Bus Interface Control Registers
Hardware Divider Register
CRC Generator Registers
HDIV_BA
CRC_BA
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4005_0000 – 0x4005_0FFF
WDT_BA
Watchdog Timer Control Registers
RTC Control Registers
RTC_BA
ADC_BA
Analog-Digital-Converter (ADC) Control Registers
Analog Comparator 0/ 1 Control Registers
Timer0/Timer1 Control Registers
ACMP01_BA
TMR01_BA
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0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4005_A000 – 0x4005_AFFF
0x4005_B000 – 0x4005_BFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4007_3000 – 0x4007_3FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4007_6000 – 0x4007_6FFF
0x4007_7000 – 0x4007_7FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x400C_0000 – 0x400C_0FFF
0x400D_0000 – 0x400D_0FFF
0x400D_1000 – 0x400D_1FFF
TMR23_BA
PWM0_BA
PWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
Timer2/Timer3 Control Registers
PWM0 Control Registers
PWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
QSPI0 Control Registers
SPI0 Control Registers
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
UART6_BA
UART7_BA
I2C0_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
UART6 Control Registers
UART7 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
USBD_BA
USCI0_BA
USCI1_BA
USB Device Control Register
USCI0 Control Registers
USCI1 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.3-7 Address Space Assignments for On-Chip Controllers
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6.3.6
SRAM Memory Organization
The M031 supports embedded SRAM with total 16 Kbytes size
Supports total 16 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
Table 6.3-9 shows the SRAM organization of M031. The address between 0x2000_4000 to
0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses.
0x3FFF_FFFF
Reserved
Reserved
Reserved
Reserved
0x2000_4000
0x2000_2000
0x2000_1000
16K byte
SRAM bank0
8K byte
SRAM bank0
4K byte
SRAM bank0
0x2000_0800
2K byte
SRAM bank0
0x2000_0000
16K byte device
4K byte device
8K byte device
2K byte device
Figure 6.3-8 SRAM Memory Organization
6.3.7
SRAM Memory Organization with parity function
The M031 supports embedded SRAM with total 96 Kbytes size
Supports total 96 Kbytes SRAM
Supports parity error check function for SRAM bank0 section 0(32 Kbytes)
Supports byte / half word / word write
Supports oversize response error
Table 6.3-9 shows the SRAM organization of M031. The address between 0x2001_8000 to
0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses. There are three section in SRAM bank0. The section 0 is addressed to 32 Kbytes
with parity function, the section 1 is addressed to 32 Kbytes and the section 2 is addressed to 32
Kbytes. SRAM section 0 has byte parity error check function. When CPU is accessing SRAM section
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0, the parity error checking mechanism is dynamic operating. As parity error occured, the PERRIF
(SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will recode
the address with parity error. Chip will enter interrupt when SRAM parity error occurred if PERRIEN
(SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occured, chip will stop detecting SRAM
parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.
0x3FFF_FFFF
Reserved
Reserved
0x2001_8000
32K byte
SRAM bank0
section 2
0x2001_0000
32K byte
SRAM bank0
section 1
32K byte
SRAM bank0
section 1
0x2000_8000
0x2000_8000
32K byte
SRAM bank0
section 0
32K byte
SRAM bank0
section 0
0x2000_0000
96K byte device
64K byte device
Figure 6.3-10 SRAM Memory Organization
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6.3.8
Chip Bus Matrix
The M031/M032 series supports Bus Matrix to manage the access arbitration between masters. The
access arbitration use round-robin algorithm as the bus priority.
M1
PDMA
M0
Cortex® -M0
S0
S1
S2
APB0
S3
APB1
S4
S5
EBI
AHB
(ctrl)
FLASH
SRAM
Figure 6.3-9 NuMicro® M031 Bus Matrix Diagram
6.3.9
IRC Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
external 32.768 kHz crystal oscillator or internal USB synchronous mode, automatically gets accurate
output frequency, 0.25 % deviation within all temperature ranges.
In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_HIRCTRIMCTL [10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTRIMCTL [1:0]
trim frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_HIRCTRIMSTS[0] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation.
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6.3.10 Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence. All proteced control registers are noted “(Write
Protect)” and add an note “Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in
register description field.
6.3.11 UART0_TXD/USCI0_DAT0 modulation with PWM
This chip supports UART0_TXD/USCI_DAT0 to modulate with PWM channel. User can set
MODPWMSEL(SYS_MODCTL[7:4]) to choose which PWM0 channel to modulate with
UART0_TXD/USCI0_DAT0 and set MODEN(SYS_MODCTL[0]) to enable modulation function. User
can set TXDINV(UART_LINE[8]) to inverse UART0_TXD or DATOINV(UUART_LINECTL[5]) to
inverse USCI0_DAT0 before modulating with PWM.
PWM0_CHx
UART0_TXD/USCI0_DAT0
TXDINV = 0 & MODH = 0
TXDINV = 0 & MODH = 1
TXDINV = 1 & MODH = 0
TXDINV = 1 & MODH = 1
Figure 6.3-11 UART0_TXD/USCI0_DAT0 Modulated with PWM Channel
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6.3.12 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
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6.3.13 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and
provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When
an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and branch
to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC
will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the
stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the
normal execution. Thus it will take less and deterministic time to process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to pending
ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of
concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to
execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the
higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
6.3.13.1 Exception Model and System Interrupt Map
Table 6.3-8 lists the exception model supported by the M031/M032 series. Software can set four
levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of
all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the
system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
3
-2
Hard Fault
Reserved
SVCall
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Reserved
PendSV
12 ~ 13
14
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SysTick
15
Configurable
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.3-8 Exception Model
Interrupt Number
Vector
Number
Interrupt Name
Interrupt
Interrupt Description
(Bit
In
Registers)
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
-
-
System exceptions
0
BODOUT
Brown-Out low voltage detected interrupt
Watchdog Timer interrupt
External interrupt fromEINT0,2,4.
External interrupt fromEINT1.3.5
External interrupt from PA, PB, PG, PH pin
External interrupt from PC, PD, PE, PF pin
PWM0 interrupt
1
WDT_INT
EINT024
2
3
EINT135
4
GPABGH_INT
GPCDEF_INT
PWM0_INT
PWM1_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART13_INT
SPI0_INT
5
6
7
PWM1 interrupt
8
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Timer 2 interrupt
Timer 3 interrupt
UART0,2 interrupt
UART1,3 interrupt
SPI0 interrupt
QSPI0_INT
Reserved
QSPI0 interrupt
Reserved
UART57_INT
I2C0_INT
UART5,7 interrupt
I2C0 interrupt
I2C1_INT
I2C1 interrupt
BPWM0_INT
BPWM1_INT
USCI01
BPWM0 interrupt
BPWM1 interrupt
USCI0,1 interrupt
USBD_INT
Reserved
USB device interrupt
Reserved
ACMP01_INT
PDMA_INT
UART46_INT
ACMP0 and ACMP1 interrupt
PDMA interrupt
UART4,6 interrupt
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44
45
28
29
PWRWU_INT
ADC_INT
Clock controller interrupt for chip wake-up from power-down state
ADC interrupt
Clock fail detected or IRC Auto Trim interrupt or SRAM parity check
error interrupt
46
47
30
31
CLKFAIL
RTC_INT
RTC interrupt
Table 6.3-9 Interrupt Number Table
6.3.13.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer
on reset, and the entry point addresses for all exception handlers. The vector number on previous
page defines the order of entries in the vector table associated with exception handler entry as
illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Vector Number
Table 7.2-10 Vector Figure Format
6.3.13.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state
until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
This chip is equipped with 16/32/64/128/256/512 Kbytes on-chip embedded Flash (the chip with 512
Kbytes consists of two 256 Kbytes BANK0 and BANK1). A User Configuration block is provided for
system initialization. A loader ROM (LDROM) is used for In-System-Programming (ISP) function. A
security protection ROM (SPROM) can conceal user program. For M031xG/I and M032xG/I, a 4
Kbytes cache with zero wait cycle is implemented to improve the performance of code/data fetching.
This chip also supports In-Application-Programming (IAP) function. User switches the code executing
without the chip reset after the embedded Flash is updated.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 111 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 111 pins are arranged in 5 ports named as PA, PB, PC, PD, PE, PF, PG
and PH. PA and PB has 16 pins on port. PC has 15 pins on port. PD and PE has 16 pins on port. PF
has 14 pins on port. PG has 10 pins on port. PH has 8 pins on port. Each of the 111 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).
6.5.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
I/O pin can be configured as interrupt source with edge/level setting
Input schmitt trigger function
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 9 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.6.2
Features
Supports 9 independently configurable channels
Selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and I2C, SPI/I2S, UART, USCI, ADC, PWM , QSPI and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
6.7.2
Features
6.7.2.1 Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
Supports event counting source from internal USB SOF signal
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports internal capture triggered while internal ACMP output signal and LIRC transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
PWM, ADC, PDMA, BPWM function
Supports Inter-Timer trigger mode
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.8.2
Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if
WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.9.2
Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.10 Real Time Clock (RTC)
6.10.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.10.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.
Supports Leap Year indication in RTC_LEAPYEAR register.
Supports Day of the Week counter in RTC_WEEKDAY register.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports 1 Hz clock output.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
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6.11 Basic PWM Generator and Capture Timer (BPWM)
6.11.1 Overview
The chip provides two BPWM generators － BPWM0 and BPWM1 as shown in BPWM Generator
Overview Block Diagram. Each BPWM supports 6 channels of BPWM output or input capture. There
is a 12-bit prescaler to support flexible clock to the 16-bit BPWM counter with 16-bit comparator. The
BPWM counter supports up, down and up-down counter types, all 6 channels share one counter.
BPWM uses the comparator compared with counter to generate events. These events are used to
generate BPWM pulse, interrupt and trigger signal for ADC to start conversion. For BPWM output
control unit, it supports polarity output, independent pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.11.2 Features
6.11.2.1 BPWM Function Features
Supports maximum clock frequency up to 144 MHz.
Supports up to two BPWM modules; each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
– BPWM counter matches 0, period value or compared value
Supports trigger ADC in the following events:
– BPWM counter matches 0, period value or compared value
6.11.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.12 PWM Generator and Capture Timer (PWM)
6.12.1 Overview
The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of
PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM
counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.
PWM uses comparator compared with counter to generate events. These events use to generate
PWM pulse, interrupt and trigger signal for ADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. In Complementary mode, there are two
comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control
unit, it supports polarity output, independent pin mask and brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.12.2 Features
6.12.2.1 PWM Function Features
Supports maximum clock frequency up to 144 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
– Dead-time insertion with 12-bit resolution
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution PWM counter
– Up, down and up-down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
– Brake source from pin and system safety events (clock failed, Brown-out detection,
SRAM parity error and CPU lockup)
– Noise filter for brake source from pin
– Edge detect brake source to control brake state until brake interrupt cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM counter matches 0, period value or compared value
– Brake condition happened
Supports trigger ADC on the following events:
– PWM counter matches 0, period value or compared value
6.12.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
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Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.13 UART Interface Controller (UART)
6.13.1 Overview
The chip provides eight channels of Universal Asynchronous Receiver/Transmitters (UART). The
UART controller performs Normal Speed UART and supports flow control function. The UART
controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-
to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten
types of interrupts. The UART controller also supports IrDA SIR, RS-485 and Single-wire function
modes and auto-baud rate measuring function.
6.13.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes or 1/1 byte entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function (Only UART0 /UART1 /UART4 /UART5
with Received Data FIFO reached threshold and RS-485 Address Match (AAD mode)
wake-up function)
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT. (Only UART0 /UART1 /UART4
/UART5 with this feature)
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
Support Single-wire function mode.
UART Feature
UART0/ UART1/ UART4/ UART2/ UART3/ UART6/ USCI-UART
UART5
UART7
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TX: 1byte
FIFO
16 Bytes
1 Bytes
RX: 2byte
Auto Flow Control (CTS/RTS)
IrDA
√
√
-
√
√
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Incoming Data Wake-up
√
√
√
√
√
√
√
√
√
-
Received
Data
FIFO
reached
√
√
-
-
threshold Wake-up
RS-485 Address Match (AAD mode)
Wake-up
-
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
√
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
Stick Bit
√
√
√
√
√
-
Note: √= Supported
Table 6.13-1 NuMicro® M031/M032 Series UART Features
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6.14 Serial Peripheral Interface (SPI)
6.14.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one set of SPI controller performing a serial-to-parallel conversion on data received from
a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Each SPI controller can be configured as a master or a slave device and supports the PDMA function
to access the data buffer. Each SPI controller also supports I2S mode to connect external audio
CODEC.
6.14.2 Features
SPI Mode
– Supports one set of SPI controller
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depends on SPI setting of data width
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD
=
1.8~3.6V)
– Supports one data channel half-duplex transfer
– Supports receive-only mode
– Supports PDMA transfer
I2S Mode
– Supports one set of I2S by SPI controller
– Interface with external audio CODEC
– Supports Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Supports two PDMA requests, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
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6.15 Quad Serial Peripheral Interface (QSPI)
6.15.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access
the data buffer.
6.15.2 Features
Supports one QSPI controller
Supports Master or Slave mode operation
Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD
1.8~3.6V)
=
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports receive-only mode
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6.16 I2C Serial Interface Controller (I2C)
6.16.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.16.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
Supports Bus Management (SM/PM compatible) function
M031xB/C/D/E M031xG/I
Section
Sub-Section
M032xB/C/D/E M032xG/I
6.16.5.2 Operation Modes
- Bus Management (SMBus/PMBus Compatiable)
- Device Identification – Slave Address
●
6.16.5 Functional Description - Bus Protocols
- Address Resolution Protocol (ARP)
- Received Command and Data acknowledge control
- Host Notify Protocol
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- Bus Management Alert
- Packet Error Checking
- Time-out
- Bus Management Time-out:
- Bus Clock Low Time-out:
- Bus Idle Detection
●
●
I2C Bus Manage Control Register (I2C_BUSCTL)
I2C
Bus
Management
Timer
Control
Register
(I2C_BUSTCTL)
●
●
●
●
●
I2C Bus Management Status Register (I2C_BUSSTS)
I2C Byte Number Register (I2C_PKTSIZE)
Register Description
I2C PEC Value Register (I2C_PKTCRC)
I2C Bus Management Timer Register (I2C_BUSTOUT)
I2C Clock Low Timer Register (I2C_CLKTOUT)
Table 6.16-1 I2C Feature Comparison Table at Different Chip
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6.17 USCI - Universal Serial Control Interface Controller (USCI)
6.17.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.17.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
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6.18 USCI – UART Mode
6.18.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the system.
6.18.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.19 USCI - SPI Mode
6.19.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as Master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in Master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0,1
Figure 6.19-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0,1
Figure 6.19-2 SPI Slave Mode Application Block Diagram
6.19.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
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Supports Word Suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.20 USCI - I2C Mode
6.20.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on
the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.20-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.20-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode .
6.20.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by received ‘START’ symbol or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.21 External Bus Interface (EBI)
6.21.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports two chip selects that can connect two external devices with different
timing setting requirements.
6.21.2 Features
Supports up to two memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports address bus and data bus separate mode
M031xB/C/D/
E
M031xG/I
M032xC/D
M032xE
M032xG/I
6.21.5.3 EBI Data Width Connection - Address Bus and Data Bus Separate
Mode
●
6.21.5.4 EBI Operating Control - Continuous Data Access Mode
●
Table 6.21-1 EBI Features Comparison Table
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6.22 USB 2.0 Full-Speed Device Controller (USBD)
6.22.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 512 Bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to
write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the
effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device plug-
in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register USBD_EPSTS0 to acknowledge what kind of
event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the
SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 2.0.
6.22.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 byte buffer size
Provides remote wake-up capability
-
M031xB/C/D/E
M032xE
M031xG/I
M032xG/I
Section
M032xC/D
6.22.7 Register Description
USB Configuration Register (USB_CFGx)
DSQSYNC OUT Token Transaction
●
-
-
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6.23 CRC Controller (CRC)
6.23.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.23.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.24 Hardware Divider (HDIV)
6.24.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a
signed, integer divider with both quotient and remainder outputs.
6.24.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)
Divided by zero warning flag
Write divisor to trigger calculation
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6.25 Analog-to-Digital Converter (ADC)
6.25.1 Overview
The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D
converter) with 16 input channels. The A/D converter supports four operation modes: Single, Burst,
Single-cycle Scan and Continuous Scan mode. The A/D converter can be started by software,
external pin (STADC), timer0~3 overflow pulse trigger, PWM trigger or BPWM trigger.
6.25.2 Features
Operating voltage: 1.8V~3.6V.
Analog input voltage: 0 ~ AVDD.
Supports external reference voltage from VREF pin.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels or 8 differential analog input channels.
Maximum ADC peripheral clock frequency is 34 MHz.
Up to 2 MSPS sampling rate.
Scan on enabled channels
Threshold voltage detection
Four operation modes:
– Single mode: A/D conversion is performed one time on a specified channel.
– Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
– Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
– Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
– Software Write 1 to ADST bit
– External pin (STADC)
– Timer 0~3 overflow pulse trigger
– BPWM trigger
– PWM trigger
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Supports extend sample time function (0~255 ADC clock).
One internal channel from band-gap voltage (VBG).
One internal channel from internal pull-up/down circuit.
Supports PDMA transfer mode.
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Supports Calibration mode.
Supports Floating Detect Function
Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note2: If the internal channel for band-gap voltage is active, the maximum sampling rate will be 300k
SPS.
Note3: The ADC Clock frequency must be slower than or equal to PCLK.
M031xG/I
M032xG/I
M031xB/C/D/E
M032x/E
M032xC/D
-
6.25.5.11 PWM trigger
●
-
●
●
●
6.25.5.12 BPWM trigger
●
●
-
6.25.5.17 Floating Detect Function
Table 6.25-1 ADC Features Comparison Table
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6.26 Analog Comparator Controller (ACMP)
6.26.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.26.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 3 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
ACMP1 supports
– 4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 3 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
Supports calibration function
M031xB/C/D/E
M032xB/C/D/E
M031xG/I
Section
Function Description
Sub-Section
M032xG/I
6.26.5.7 Calibration function
-/-/-/●
●
Table 6.26-1 Calibration Function Features Comparison Table at Different Chip
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6.27 Peripherals Interconnection
6.27.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interact without CPU
saves CPU resources, reduces power consumption, operates with no software latency and fast
responds.
6.27.2 Peripherals Interconnect Matrix table
Destination
Source
ADC
HIRC TRIM
BPWM
PWM
Timer
UART/USCI
ACMP
BOD
-
-
-
-
-
-
-
-
-
-
3
3
3
3
-
6
-
-
-
-
-
-
Clock Fail
CPU Lockup
LIRC
-
-
-
-
-
-
-
-
6
-
HXT
-
-
-
LXT
-
2
-
-
BPWM
PWM
1
1
1
-
4
4
5
-
-
-
-
8
-
-
-
4
5
-
-
Timer
7
-
USBD
2
-
Table 6.27-1 Peripherals Interconnect Matrix table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
as close to AVDD as possible
L=30Z
EXT_PWR
AVDD
AVSS
1uF+0.1uF+0.01uF
L=30Z
as close to the
EXT_PWR as possible
10uF+0.1uF
VREF
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
LDO_CAP
VSS
1uF
as close to LDO as possible
VDD
VSS
EXT_VSS
0.1uF*N
as close to VDD as possible
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7.2 Peripheral Application Scheme
DVCC
100K
100K
VDD
USB Full Speed Slot
ICE_DAT
SWD
Interface
ICE_CLK
nRESET
USB_VBUS
USB_D-
27R
27R
VSS
USB_D+
20pF
USB_VCC33_CAP
XT1_IN
1uF
4~32 MHz
20pF
crystal
DVCC
XT1_OUT
SPI Mode
CS
SPI_SS
VDD
SPI_CLK
CLK
SPI Device
Crystal
SPI_MISO
SPI_MOSI
MISO
MOSI
VSS
20pF
X32_IN
I2S Mode
Audio codec
32.768 kHz
crystal
SPI_I2SMCLK
Line In
20pF
SPI_CLK (I2S_BCLK)
SPI_SS (I2S_LRCLK)
SPI_MOSI (I2S_DO)
SPI_MISO (I2S_DI)
NUC8822
X32_OUT
Line Out
DVCC
M031/M032 Series
Reset
Circuit
10K
DVCC
nRESET
DVCC
10 uF
4.7K
4.7K
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
I2C Device
LDO_CAP
LDO
1 uF
64K x 16-bit
SRAM
LATCH
Q
D
Addr[15:0]
En
EBI_ALE
PC COM Port
RS 232 Transceiver
nCE
nOE
nWE
nLB
EBI_nCS
EBI_nRD
EBI
RIN
UART_RXD
UART_TXD
ROUT
TIN
EBI_nWR
EBI_nWRL
EBI_nWRH
UART
TOUT
nUB
Data[15:0]
EBI_AD[15:0]
Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
4.0
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
ΔVDD
|VDD –AVDD
ΔVSS
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance I/O
-
mV
mV
mV
mV
V
|
-
50
-
50
|VSS - AVSS
|
-
50
VSS-0.3
VSS-0.3
5.5
4.0
VIN
Input voltage on any other pin[*2]
V
Note:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance I/O includes PA.10 ~ 11; PB.0 ~ 15; PF.2, 3, 4, 5; all USB pin and nRESET pin. VIN maximum value
must be respected to avoid permanent damage. Refer to Table 8.1-2 for the values of the maximum allowed injected
current
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
150
100
20
Unit
[*1]
ΣIDD
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
IIO
mA
100
100
±5
[*3]
IINJ(PIN)
[*3]
ΣIINJ(PIN)
±25
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
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Table 8.1-2 Current Characteristics
Sep. 29, 2020
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8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (°C)
θJA = thermal resistance junction-ambient (°C/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
105
125
150
Unit
°C
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
T
J
-40
-65
-
T
ST
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
°C/Watt
38
30
-
-
-
-
-
-
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
-
-
-
-
-
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
28
[*1]
θJA
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
60
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
58
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)
38.5
Note:
1.
Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal Characteristics
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8.1.4
EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts
of narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-6000
-1000
-400
Typ
Max
+6000
+1000
+400
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
-4.4
Fast transient voltage burst
+4.4
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-4 EMC Characteristics for M03xB/M03xC/M03xD/M03xE
Sep. 29, 2020
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Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-5000
-750
-400
-4.4
Typ
Max
+5000
+750
+400
+4.4
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
Fast transient voltage burst
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-5 EMC Characteristics for M03xG/M03xI
8.1.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge
20-pin TSSOP(4.4x6.5 mm)[*1]
28-pin TSSOP(4.4x9.7 mm) [*1]
33-pin QFN(4x4 mm) [*1]
MSL
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
48-pin LQFP(7x7 mm) [*1]
64-pin LQFP(7x7 mm) [*1]
128-pin LQFP(14x14 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-6 Package Moisture Sensitivity (MSL)
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8.1.6
Soldering Profile
Figure 8.1-1 Soldering Profile from J-STD-020C
Porfile Feature
Pb Free Package
3°C/sec. max
Average ramp-up rate (217°C to peak)
Preheat temperature 150°C ~200°C
Temperature maintained above 217°C
Time with 5°C of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260°C
Ramp-down rate
6°C/sec ax.
8 min. max
Time 25°C to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.1-7 Soldering Profile
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8.2 General Operating Conditions
(VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 48/72 MHz unless otherwise specified.)
Symbol
Parameter
Temperature
Min
Typ
Max
Unit
Test Conditions
TA
-40
-
105
°C
-
-
-
-
-
48
72
MHz
MHz
VDD = 1.8 V~3.6V
VDD = 2.0 V~3.6V
fHCLK
Internal AHB clock frequency
Operation voltage
f
1.8
3.6
HCLK up to 48 MHz
VDD
f
2.0
-
3.6
HCLK up to 72 MHz
[*1]
AVDD
Analog operation voltage
Analog reference voltage
LDO output voltage
VDD
-
V
VREF
VLDO
1.8
-
AVDD
-
AVDD − VREF < 1.2 V
1.8
1.23
1
[*4]
VBG
Band-gap voltage
1.16
1.31
[*2]
CLDO
LDO output capacitor on each pin
ESR of CLDO output capacitor
μF
[*3]
RESR
0.1
-
-
10
-
Ω
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
[*3]
IRUSH
150
mA
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
VDD = 1.8 V, TA = 105 °C,
IRUSH = 150 mA for 15 us
[*3]
ERUSH
-
2.25
-
µC
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3.Guaranteed by design, not tested in production
4.Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 General Operating Conditions
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8.3 DC Electrical Characteristics
8.3.1 Supply Current Characteristics for M03xB/M03xC/M03xD/M03xE
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
8.5
5.6
5
9.78
6.44
5.75
4.14
2.76
10.18
6.90
6.13
4.49
3.08
10.80
7.41
6.63
4.93
3.47
Normal run mode, executed
from Flash, all peripherals
disable
3.6
2.4
38.4 kHz
32.768 kHz
48 MHz
0.099
0.098
19.5
0.114
0.113
22.43
0.385
0.383
23.19
0.711
0.710
24.21
IDD_RUN
mA
32 MHz
24 MHz
12.6
9.5
14.49
10.93
6.44
15.21
11.52
6.90
15.98
12.26
7.48
Normal run mode, executed
from Flash, all peripherals
enable
12 MHz
5.6
4 MHz
2.9
3.34
3.71
4.17
38.4 kHz
32.768 kHz
0.107
0.105
0.123
0.121
0.396
0.392
0.724
0.720
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-1 Current Consumption in Normal Run Mode
Sep. 29, 2020
Page 237 of 288
Rev 2.02
M031/M032
Typ
Max[*1] [*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
3.85
2.42
2.35
1.83
1.51
4.43
2.78
2.70
2.10
1.74
4.79
3.15
3.05
2.43
2.05
5.26
3.57
3.47
2.81
2.43
Idle mode, all peripherals
disable
38.4 kHz
32.768 kHz
48 MHz
0.095
0.095
14.94
0.109
0.109
17.18
0.380
0.380
17.87
0.706
0.707
18.79
IDD_IDLE
mA
32 MHz
24 MHz
9.47
7.2
10.89
8.28
11.52
8.81
12.21
9.47
Idle mode, all peripherals
enable
12 MHz
4.3
4.95
5.38
5.90
4 MHz
2.43
0.103
0.102
2.79
3.16
3.59
38.4 kHz
32.768 kHz
0.118
0.117
0.392
0.389
0.720
0.718
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-2 Current Consumption in Idle Mode
Sep. 29, 2020
Page 238 of 288
Rev 2.02
M031/M032
Typ[*2]
Max[*3][*4]
LXT[*1] LIRC
32.768 38.4
Symbol
Test Conditions
Unit
T
=
T
=
T
=
T =
A
A
A
A
kHz
kHz
25 °C 25 °C 85 °C 105 °C
Power-down mode, all peripherals disable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT use LIRC, UART/Timer use LXT
-
-
12
13.5
12.5
14
25 [*5]
27.5
26.5
28
350
360
365
375
700
710
715
725
V
-
-
IDD_PD
µA
V
V
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
5. Based on characterization, tested in production.
Table 8.3-3 Chip Current Consumption in Power-down Mode
Sep. 29, 2020
Page 239 of 288
Rev 2.02
M031/M032
8.3.2
Supply Current Characteristics for M03xG/M03xI
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
72 MHz[*3]
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
23.7
27.26
28.74
30.73
14.4
9.0
16.56
10.35
18.06
10.47
5.29
17.16
10.72
18.06
10.47
5.29
18.87
12.31
18.79
10.89
5.52
Normal run mode, executed
from Flash, all peripherals
disable
15.7
9.1
4.6
38.4 kHz
32.768 kHz
72 MHz[*3]
0.141
0.140
46.4
0.162
0.161
53.36
1.430
1.429
55.45
2.885
2.885
58.05
IDD_RUN
mA
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
28.6
18.9
15.4
8.9
32.89
21.74
17.71
10.24
5.29
35.09
23.76
19.43
11.76
6.68
36.95
25.53
21.22
13.44
8.24
Normal run mode, executed
from Flash, all peripherals
enable
4.6
38.4 kHz
32.768 kHz
0.153
0.150
0.176
0.173
1.449
1.445
2.908
2.903
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
3. When chip works at VDD = 2.0~3.6V.
Table 8.3-4 Current Consumption in Normal Run Mode
Sep. 29, 2020
Page 240 of 288
Rev 2.02
M031/M032
Typ
Max[*1] [*2]
= 85 °C
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
T = 105 °C
A
A
A
A
72 MHz[*3]
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
9.9
3.9
2.6
2.7
2.1
1.7
11.39
4.49
2.99
3.11
2.42
1.96
12.59
5.85
4.34
4.44
3.73
3.26
14.13
7.39
5.84
5.95
5.23
4.74
Idle mode, all peripherals
disable
38.4 kHz
32.768 kHz
72 MHz[*3]
0.133
0.133
32.6
0.153
0.153
37.49
1.421
1.422
39.69
2.877
2.878
41.60
IDD_IDLE
mA
48 MHz
32 MHz
19.1
12.5
10.5
6.2
21.97
14.38
12.08
7.13
23.87
16.14
13.65
8.58
25.72
17.86
15.38
10.19
6.68
24 MHz
Idle mode, all peripherals
enable
12 MHz
4 MHz
3.3
3.80
5.15
38.4 kHz
32.768 kHz
0.145
0.143
0.167
0.164
1.438
1.434
2.898
2.893
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
3. When chip works at VDD = 2.0~3.6V.
Table 8.3-5 Current Consumption in Idle Mode
Sep. 29, 2020
Page 241 of 288
Rev 2.02
M031/M032
Typ[*2]
Max[*3][*4]
T = 85 T = 105
A
LXT[*1] LIRC
32.768 38.4
Symbol
Test Conditions
Unit
T
=
T
=
A
A
A
kHz
kHz
25 °C 25 °C
°C
°C
51.5 59.2 [*5] 1298
2732 [*5]
Power-down mode, all peripherals disable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT use LIRC, UART/Timer use LXT
-
-
53.3
53.4
55.2
61.3
61.4
63.5
1294
1300
1306
2747
2751
2758
V
-
-
IDD_PD
µA
V
V
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
5. Based on characterization, tested in production.
Table 8.3-6 Chip Current Consumption in Power-down Mode
Sep. 29, 2020
Page 242 of 288
Rev 2.02
M031/M032
8.3.3
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[*1]
Peripheral
PDMA
IDD
Unit
0.721
0.0002
0.236
0.135
0.119
0.122
0.125
0.102
0.332
0.303
0.299
0.292
0.095
0.243
0.159
0.122
0.914
1.878
0.629
0.575
0.631
0.614
0.584
0.647
0.549
0.654
1.099
0.962
0.638
ISP
EBI
HDIV
CRC
SRAM0IDLE
WDT/WWDT
RTC
TMR0
TMR1
TMR2
TMR3
CLKO
ACMP01[*3]
I2C0
mA
I2C1
QSPI
SPI/I2S
UART0
UART1
UART2
UART3
UART4
UART5
UART6
UART7
USB FS Device
ADC[*2]
USCI0
Sep. 29, 2020
Page 243 of 288
Rev 2.02
M031/M032
USCI1
PWM0
0.445
1.257
1.26
PWM1
BPWM0
BPWM1
0.649
0.652
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
Table 8.3-7 Peripheral Current Consumption
Sep. 29, 2020
Page 244 of 288
Rev 2.02
M031/M032
8.3.4
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
Symbol
Parameter
Typ
5
Max
6
Unit
cycles
µs
tWU_IDLE
Wakeup from IDLE mode
Wakeup from normal power down mode
[*1][*2]
tWU_NPD
12
25
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-8 Low-power Mode Wakeup Timings
Sep. 29, 2020
Page 245 of 288
Rev 2.02
M031/M032
8.3.5
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece
I/O should be avoided during normal product operation. However, the analog compoenent of the MCU
is most likely to be affected by the injection current , but it is not easily clarified when abnormal
injection accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to
VDD) to pins that include analog function which may potentially injection currents.
Negative
injection
Positive
injection
Symbol
Parameter
Unit
Test Condition
-0
-0
0
0
Injected current on nReset pins
Injected current on PF2~PF5, PA10,
PA11 and PB0~PB15 for analog
input function
Injected current by a I/O Pin
mA
IINJ(PIN)
Injected current on any other 5V-
tolerance I/O
-5
NA
Table 8.3-9 I/O Current Injection Characteristics
8.3.6
I/O DC Characteristics
8.3.6.1 PIN Input Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
0.3*VDD
VDD
Unit
V
Test Conditions
Input low voltage
Input high voltage
0
-
VIH
0.7*VDD
-
-
V
[*1]
VHY
Hysteresis voltage of schmitt input
0.2*VDD
-
V
VSS < VIN < VDD
,
-1
-1
1
1
Open-drain or input only mode
[*2]
ILK
Input leakage current
A
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
-
-
45
-
-
VDD = 3.3 V, Quasi mode
VDD = 1.8 V, Quasi mode
[*1] [*3]
RPU
Pull up resistor
kΩ
120
Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher
than the maximum value, if positive current is injected on adjacent pins
Table 8.3-10 I/O Input Characteristics
Sep. 29, 2020
Page 246 of 288
Rev 2.02
M031/M032
8.3.6.2 I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 3.3 V
-25.5
-28
-31
µA
VIN=(VDD-0.4) V
Source current for quasi-
bidirectional mode and
high level
VDD = 2.5 V
-19
-10.5
-8
-22
-13
-10
-8
-24
-16
µA
µA
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
[*1] [*2]
ISR
VDD = 3.3 V
-15
mA
mA
mA
mA
mA
VIN=(VDD-0.4) V
VDD = 2.5 V
Source current for push-
pull mode and high level
-6
-13
VIN=(VDD-0.4) V
VDD = 1.8 V
-3.5
7.5
6
-5.5
9
-10.5
14.5
13
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
VDD = 2.5 V
VIN= 0.4 V
Sink current for push-
pull mode and low level
[*1] [*2]
ISK
7.5
VDD = 1.8 V
VIN= 0.4 V
3.5
-
5
5
10.5
-
mA
pF
[*1]
CIO
I/O pin capacitance
Note:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.3-11 I/O Output Characteristics
8.3.6.3 nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Min
Typ
-
Max Unit
Test Conditions
-
0.3*VDD
V
V
VIHR
0.7*VDD
-
-
-
-
45
120
32
-
-
VDD = 3.3 V
[*1]
RRST
Internal nRESET pull up resistor
nRESET input filtered pulse time
KΩ
-
-
VDD = 1.8 V
-
Normal run and Idle mode
Power down mode
[*1]
tFR
µs
75
155
Note:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.3-12 nRESET Input Characteristics
Sep. 29, 2020
Page 247 of 288
Rev 2.02
M031/M032
8.4 AC Electrical Characteristics
8.4.1
48 MHz Internal High Speed RC Oscillator (HIRC)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.8
-
3.6
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
47.52
-1
48
-
48.48
1
MHz
%
fHRC
TA = 25 °C,
VDD = 3.3V
Frequency drift over temperarure and
volatge
TA = -40C ~ +105 °C,
-2[*1]
-
2[*1]
-
%
µA
µs
VDD = 1.8 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
-
-
1655
11
TA = -40C ~ +105 °C,
[*2]
TS
15
VDD = 1.8 ~ 3.6V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-1 48 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
Sep. 29, 2020
Page 248 of 288
Rev 2.02
M031/M032
(a) Test condition: VDD=3.6 V, Temp = -40~125°C
(b) Test condition: VDD=2.7 V, Temp = -40~125°C
Sep. 29, 2020
Page 249 of 288
Rev 2.02
M031/M032
(c) Test condition: VDD=1.8 V, Temp = -40~125°C
Note:
1. The graph is a statistical result using a limited number of samples. For the actual characteristic range, please refer to
Table 8.4-1.
Figure 8.4-1 HIRC vs. Temperature
Sep. 29, 2020
Page 250 of 288
Rev 2.02
M031/M032
8.4.2
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.8
-
3.6
V
Oscillator frequnecy
38.016
38.4
38.784
kHz
TA = 25 °C,
VDD = 3.3V
-1
-
-
1
%
%
[*2]
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105 °C
VDD=1.8V~3.6V
-15
15
Without software calibration
ILRC
TS
Operating current
Stable time
-
-
1
-
-
µA
VDD = 3.3V
TA=-40~105 °C
VDD=1.8V~3.6V
500
μs
Note:
1. Guaranteed by characterization, not tested in production.
2. The 38.4 kHz low speed RC oscillator can be calibrated by user.
3. Guaranteed by design.
Table 8.4-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
Sep. 29, 2020
Page 251 of 288
Rev 2.02
M031/M032
(a) Test condition: VDD=3.6 V, Temp = -40~125°C
(b) Test condition: VDD=2.7 V, Temp = -40~125°C
Sep. 29, 2020
Page 252 of 288
Rev 2.02
M031/M032
(c) Test condition: VDD=1.8 V, Temp = -40~125°C
Note:
1. The graph is a statistical result using a limited number of samples. For the actual characteristic range, please refer to
Table 8.4-2
Figure 8.4-2 LIRC vs. Temperature
Sep. 29, 2020
Page 253 of 288
Rev 2.02
M031/M032
8.4.3
External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[*1]
Typ
-
Max[*1]
Unit
V
Test Conditions
1.8
-
3.6
-
Rf
Internal feedback resister
Oscillator frequency
200
kΩ
fHXT
4
-
-
32
MHz
120
200
4 MHz, Gain = L0
170
250
350
500
650
1700
900
600
450
400
350
300
450
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
4 MHz, Gain = L0
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
-
-
IHXT
Current consumption
A
600
850
-
-
1100
2200
1100
740
-
-
-
-
TS
Stable time
s
650
600
550
DuHXT
Vpp
Duty cycle
40
-
-
60
-
%
V
Peak-to-peak amplitude
1
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator
Sep. 29, 2020
Page 254 of 288
Rev 2.02
M031/M032
Symbol
Parameter
Min[*1]
Typ
Max[*1]
150
50
Unit
Test Conditions
-
-
-
-
-
-
-
-
-
-
Crystal @4 MHz
Crystal @12 MHz
Crystal @16 MHz
Crystal @24 MHz
Crystal @32 MHz
Rs
Equivalent series resisotr(ESR)
40
Ω
40
40
Note:
1. Guaranteed by characterization, not tested in production.
2. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life.
If Safety factor isn’t enough, the HXT gain should be increased.
ꢃꢄ
ꢐꢂꢄ
ꢑ
ꢁꢂꢄ
ꢎꢏꢏꢂ
ꢁꢂ
ꢀ
ꢅꢆꢇꢈꢉꢊꢋꢂꢌꢍꢄ
ꢄ
ꢑ
RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is
only used to measure Safety factor (Sf) and is not suitable for mass production.
XT1_OUT
XT1_IN
RADD
C2
C1
Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics
8.4.3.1 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 32 MHz
10 ~ 25 pF
10 ~ 25 pF
without
XT1_OUT
XT1_IN
R1
C1
C2
Figure 8.4-3 Typical Crystal Application Circuit
Sep. 29, 2020
Page 255 of 288
Rev 2.02
M031/M032
8.4.4
External 4~32 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
1
-
32
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
ns
ns
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
ns
ns
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal
Sep. 29, 2020
Page 256 of 288
Rev 2.02
M031/M032
8.4.5
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Min[*1]
1.8
-40
-
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
3.6
105
-
V
Temperature range
TLXT
C
Rf
Internal feedback resistor
Oscillator frequency
6.5
32.768
1.5
2
MΩ
kHz
FLXT
-
-
6
6
ESR=35 kΩ, Gain = L1
ESR=70 kΩ, Gain = L2
ILXT
Current consumption
A
TsLXT
DuLXT
Vpp
Stable time
-
500
-
900
70
-
ms
%
Duty cycle
30
TBD
Peak-to-peak amplitude
500
mV
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Min
Typ
Max
Unit
Test Conditions
Equivalnet Series Resisotr(ESR)
-
35
70
kΩ
Crystal @32.768 kHz
Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics
8.4.5.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20 pF
20 pF
without
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-4 Typical 32.768 kHz Crystal Application Circuit
Sep. 29, 2020
Page 257 of 288
Rev 2.02
M031/M032
8.4.6
External 32.768 kHz Low Speed Clock Input Signal Characteristics
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
fLSE_ext
tCHCX
Parameter
External clock source frequency
Clock high time
Min[*1]
-
Typ
Max[*1]
Unit
kHz
ns
Test Conditions
32.768
-
-
-
450
450
-
-
tCLCX
Clock low time
ns
tCLCH
Clock rise time
Low (10%) to high level (90%)
rise time
-
-
-
-
50
50
ns
ns
tCHCL
Clock fall time
High (90%) to low level (10%) fall
time
DuE_LXT
Xin_VIH
Xin_VIL
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
LXT input pin input high voltage
LXT input pin input low voltage
0.3*VDD
V
External
clock source
X32_IN
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by design, not tested in production
Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal
Sep. 29, 2020
Page 258 of 288
Rev 2.02
M031/M032
8.4.7
PLL Characteristics
Symbol
fPLL_in
Parameter
PLL input clock
Min[*1]
3.2
50
Typ
Max[*1]
32
Unit
MHz
MHz
MHz
MHz
µs
Test Conditions
-
-
-
-
-
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
PLL multiplier output clock
PLL reference clock
144
8
0.8
200
-
PLL voltage controlled oscillator
PLL locking time
500
500
Jitter[*2]
Cycle-to-cycle Jitter
Power consumption
-
-
200
5
350
9
ps
f
VDD =3.3V @ PLL_OUT = 144
IDD
mA
MHz
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
Table 8.4-9 PLL Characteristics
Sep. 29, 2020
Page 259 of 288
Rev 2.02
M031/M032
8.4.8
I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
Test Conditions[*2]
-
CL = 30 pF, V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
= 3.3 V,
5.5
3
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
-
-
-
-
-
-
-
-
-
-
-
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
tf(IO)out
Output high (90%) to low level (10%) fall time
Output low (10%) to high level (90%) rise time
I/O maximum frequency
ns
8.5
4.5
5.5
3
tr(IO)out
ns
8.5
4.5
60
110
40
75
[*3]
fmax(IO)out
MHz
2.77
-
f(IO)out = 24 MHz
CL = 10 pF, V
= 3.3 V,
= 3.3 V,
DD
f(IO)out = 24 MHz
CL = 30 pF, V
1.19
0.69
-
-
[*4]
IDIO
I/O dynamic current consumption
mA
DD
f(IO)out = 6 MHz
CL = 10 pF, V
= 3.3 V,
DD
f(IO)out = 6 MHz
0.3
-
Note:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢕ
3. The maximum frequency is defined by ꢒꢓꢊꢔ ꢁꢂꢖꢂꢗꢂꢘꢉ ꢐꢉ ꢛꢂ.
ꢙ
ꢚ
4. The I/O dynamic current consumption is defined by ꢜꢝꢞꢟ ꢁ ꢠꢝꢝ ꢂꢗꢂꢒꢞꢟ ꢂꢗ ꢘꢡꢞꢟ ꢢꢂꢡꢣꢛ
Table 8.4-10 I/O AC Characteristics
Sep. 29, 2020
Page 260 of 288
Rev 2.02
M031/M032
8.5 Analog Characteristics
8.5.1 LDO
Symbol
VDD
Parameter
Power supply
Min
1.8
-
Typ
Max
3.6
-
Unit
V
Test Condition
-
1.8
-
VLDO
TA
Output voltage
Temperature
V
-40
105
°C
Note
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
8.5.2
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
POR reset voltage
Min
-
Typ
20
2
Max
Unit
Test Conditions
AVDD = 3.6V
[*1]
IPOR
30
µA
[*1]
ILVR
-
3.6
AVDD = 3.6V
AVDD = 3.6V
-
[*1]
IBOD
-
3
5.5
VPOR
VLVR
VBOD
1.35
1.6
1.8
2.3
-
1.5
1.7
2.0
2.5
200
16
1000
120
-
1.65
V
LVR reset voltage
1.8
BOD brown-out detect voltage
2.2
BODVL = 0
2.7
BODVL = 1
[*1]
TLVR_SU
LVR startup time
LVR respond time
BOD startup time
BOD respond time
VDD rise time rate
VDD fall time rate
-
-
-
-
-
-
-
-
-
µs
-
[*1]
TLVR_RE
-
-
[*1]
TBOD_SU
-
-
[*1]
TBOD_RE
-
-
[*1]
RVDDR
10
10
80
250
150
µs/V
POR Enabled
POR Enabled
LVR Enabled
BOD 2.0V Enabled
BOD 2.5V Enabled
[*1]
RVDDF
-
-
-
-
Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.5-1 Reset and Power Control Unit
Sep. 29, 2020
Page 261 of 288
Rev 2.02
M031/M032
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
Sep. 29, 2020
Page 262 of 288
Rev 2.02
M031/M032
8.5.3
12-bit SAR ADC
Symbol
TA
Parameter
Min
Typ
Max
Unit
Test Conditions
Temperature
-40
105
-
-
°C
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.8
1.8
0
3.6
V
V
V
V
VDD
DD
AVDD
VREF
-
-
ADC channel input voltage
Common-Mode Input Range
VCM
VREF/2
Full differential input
AVDD = VDD =VREF = 3.3 V
FADC = 34 MHz
[*1]
IADC
Operating current (AVDD + VREF current)
-
-
355
34
µA
TCONV = 17 * TADC
NR
Resolution
12
-
Bit
[*1]
FADC
ADC Clock frequency
4
MHz
1/TADC
TSMP
=
TSMP
Sampling Time
Conversion time
1
-
-
256
272
1/FADC (EXTSMPT(ADC_ESMPCTL[7:0])
+ 1 ) * TADC
TCONV
17
1/FADC TCONV = TSMP + 16 * TADC
FSPS = FADC / TCONV
[*1]
FSPS
Sampling Rate
0.236
-
2
MSPS
EXTSMPT(ADC_ESMPCTL[7:0])
= 0
TEN
Enable to ready time
20
-2
-
-
-
μs
VREF = AVDD
,
+2
LSB
except TSSOP20 and TSSOP28
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
VREF = AVDD
-4
-1
+4
+2
+4
+4
+4
+4
+10
+4
+8
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TSSOP20 and TSSOP28
VREF = AVDD
,
-
-
-
-
except TSSOP20 and TSSOP28
DNL[*1]
VREF = AVDD
-1
TSSOP20 and TSSOP28
VREF = AVDD
,
-4
except TSSOP20 and TSSOP28
[*1]
EG
VREF = AVDD
-10
-4
TSSOP20 and TSSOP28
VREF = AVDD
,
except TSSOP20 and TSSOP28
[*1]
EO
Offset error
T
VREF = AVDD
-4
TSSOP20 and TSSOP28
[*1]
EA
Absolute Error
VREF = AVDD,
-4
except TSSOP20 and TSSOP28
VREF = AVDD
-8
TSSOP20 and TSSOP28
Sep. 29, 2020
Page 263 of 288
Rev 2.02
M031/M032
Symbol
ENOB[*1]
SINAD[*1]
SNR[*1]
Parameter
Effective number of bits
Min
Typ
Max
TBD
TBD
TBD
TBD
-
Unit
Test Conditions
-
-
-
-
-
-
-
-
bits FADC = 34 MHz
AVDD = VDD =VREF = 3.3 V
Signal-to-noise and distortion ratio
Signal-to-noise ratio
-
Input Frequency = 20 kHz
TA = 25 °C
-
dB
THD[*1]
Total harmonic distortion
Internal Capacitance
-
2.9
-
[*1]
CIN
pF
kΩ
kΩ
[*1]
RIN
Internal Switch Resistance
External input impedance
2
[*1]
REX
-
50
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
ꢦ
ꢤꢌꢥ ꢁꢂ
ꢬꢂꢤꢞꢨ
ꢒ
ꢧꢝꢅ ꢂꢗꢂꢡꢞꢨ ꢂꢗ ꢩꢪꢂꢘꢫꢨꢐꢕ
ꢛ
VDD
EADC_CHx
RIN
REX
12-bit
Converter
VEX
CIN
CEX
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
Sep. 29, 2020
Page 264 of 288
Rev 2.02
M031/M032
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Sep. 29, 2020
Page 265 of 288
Rev 2.02
M031/M032
8.5.4
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Temperature
Min Typ Max Unit
Test Conditions
VDD = AVDD
AVDD
1.8
-40
-
-
-
3.6
105
45
V
°C
A
TA
IDD
Operating current
30
1/2 AVDD
AVDD -0.3
[*2]
VCM
Input common mode voltage range
0.35
[*2]
VDI
Differential input voltage sensitivity
Input offset voltage
Hysteresis window
DC voltage Gain
10
-
20
10
90
65
-
-
mV Hysteresis disable
mV Hysteresis disable
[*2]
Voffset
20
[*2]
Vhys
40
45
-
140 mV
Av[*1]
75
400
4
dB
nS
uS
%
[*2]
Td
Propagation delay
Setup time
[*2]
TSetup
-
-
[*2]
ACRV
CRV output voltage
Unit resistor value
Setup time
-5
-
-
5
AVDD x (1/6+CRVCTL/24)
[*2]
RCRV
4.2
-
-
kΩ
[*2]
TSETUP_CRV
-
350
45
µS CRV output voltage settle to ±5%
[*2]
IDD_CRV
Operating current
-
30
A
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production
Table 8.5-2 ACMP Characteristics
Sep. 29, 2020
Page 266 of 288
Rev 2.02
M031/M032
8.6
Communications Characteristics
QSPI/SPI Dynamic Characteristics
8.6.1
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
24
Unit
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 25 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 25 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
24
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tDH
5
2.7 V ≤ VDD ≤ 3.6 V, CL = 25 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 25 pF
tV
Data output valid time
-
8.5
Note:
1. Guaranteed by design.
Table 8.6-1 QSPI/SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-1 QSPI/SPI Master Mode Timing Diagram
Sep. 29, 2020
Page 267 of 288
Rev 2.02
M031/M032
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
16
Unit
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
16
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
1
TSPICLK
+ 2ns
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSS
Slave select setup time
ns
1
TSPICLK
+ 3ns
-
-
-
-
1
tSH
tDS
tDH
Slave select hold time
ns
TSPICLK
Data input setup time
Data input hold time
1.5
3.5
-
-
-
-
-
-
-
ns
ns
17.5
25
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
ns
-
Note:
1. Guaranteed by design.
Table 8.6-2 QSPI/SPI Slave Mode Characteristics
Sep. 29, 2020
Page 268 of 288
Rev 2.02
M031/M032
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-2 QSPI/SPI Slave Mode Timing Diagram
Sep. 29, 2020
Page 269 of 288
Rev 2.02
M031/M032
8.6.2
SPI - I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min[*1]
Max[*1]
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
80
80
2
-
-
Master fPCLK = 48 MHz, data: 24 bits, audio
frequency = 128 kHz
6
-
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
2
WS setup time
24
0
-
WS hold time
-
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Note:
10
7
7
4
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
25
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
4
-
0
1. Guaranteed by design.
Table 8.6-3 I2S Characteristics
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-3 I2S Master Mode Timing Diagram
Sep. 29, 2020
Page 270 of 288
Rev 2.02
M031/M032
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-4 I2S Slave Mode Timing Diagram
Sep. 29, 2020
Page 271 of 288
Rev 2.02
M031/M032
8.6.3
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-4 I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-5 I2C Timing Diagram
Sep. 29, 2020
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8.6.4
USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
24
Unit
Test Conditions
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
24
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tDH
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
5
tV
Data output valid time
-
8.5
Note:
1. Guaranteed by design.
Table 8.6-5 USCI-SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram
Sep. 29, 2020
Page 273 of 288
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Symbol
FSPICLK
Parameter
Min[*1]
Typ
Max[*1] Unit
Test Conditions
-
-
-
7
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
SPI clock frequency
MHz
7
1/ TSPICLK
-
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
1
TSPICLK
+ 2ns
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSS
Slave select setup time
ns
1
TSPICLK
+ 3ns
-
-
-
1
tSH
tDS
tDH
Slave select hold time
-
ns
TSPICLK
Data input setup time
Data input hold time
2
4
-
-
-
-
-
-
ns
ns
-
65
70
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
ns
-
Note:
1. Guaranteed by design.
Table 8.6-6 USCI-SPI Slave Mode Characteristics
Sep. 29, 2020
Page 274 of 288
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M031/M032
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram
Sep. 29, 2020
Page 275 of 288
Rev 2.02
M031/M032
8.6.5
USCI - I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-7 USCI-I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-8 USCI-I2C Timing Diagram
Sep. 29, 2020
Page 276 of 288
Rev 2.02
M031/M032
8.6.6
USB Characteristics
8.6.6.1 USB Full-Speed Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
USB full speed transceiver
operating voltage
VBUS
4.4
5.25
V
USB Internal power regulator
output
[*2]
VDD33
3.0
3.3
3.6
V
VIH
VIL
VDI
Input high (driven)
Input low
2.0
-
-
-
-
-
0.8
-
V
V
V
-
-
Differential input sensitivity
0.2
|(USB_D+) - (USB_D-)|
Differential
VCM
0.8
-
2.5
V
Includes VDI range
common-mode range
Single-ended receiver threshold
Receiver hysteresis
0.8
-
-
2.0
-
V
mV
V
-
-
-
-
-
-
VSE
200
VOL
VOH
VCRS
RPU
Output low (driven)
0
-
-
-
-
0.3
3.6
2.0
1.9
Output high (driven)
2.8
1.3
1.19
V
Output signal cross voltage
Pull-up resistor
V
kΩ
Termination voltage for
upstream port pull-up (RPU)
VTRM
3.0
-
3.6
V
[*3]
ZDRV
Driver output resistance
Transceiver capacitance
-
-
10
-
-
Ω
Steady state drive
Pin to GND
CIN
26
pF
Note:
1. Guaranteed by characterization result, not tested in production.
2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the
USB_VDD33_CAP pin and the closest GND pin of the device.
3. USB_D+ and USB_D- must be connected with series resistors to fit USB Full-speed spec request (28 ~ 44Ω).
Table 8.6-8 USB Full-Speed Characteristics
8.6.6.2 USB Full-Speed PHY characteristics
Symbol
TFR
Parameter
Min[*1]
Typ
Max[*1]
20
Unit
ns
Test Conditions
CL=50 pF
rise time
fall time
4
4
-
-
-
TFF
20
ns
CL=50 pF
TFRFF
rise and fall time matching
90
111.11
%
TFRFF = TFR/TFF
Note:
1. Guaranteed by characterization result, not tested in production.
Table 8.6-9 USB Full-Speed PHY Characteristics
Sep. 29, 2020
Page 277 of 288
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M031/M032
8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.8
20
60
7
Max
Unit
V
Test Condition
[1]
VFLA
1.62
1.98
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
-
-
-
-
-
-
-
-
-
-
ms
µs
TA = 25°C
mA
mA
mA
IDD2
Program current
Erase current
8
IDD3
12
NENDUR
Endurance
20,000
-
-
-
-
cycles[2]
year
TJ = -40°C~125°C
20 kcycle[3] TJ = 55°C
20 kcycle[3] TJ = 85°C
20 kcycle[3] TJ = 125°C
65
10
4
-
-
-
TRET
Data retention
year
year
Note:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Sep. 29, 2020
Page 278 of 288
Rev 2.02
M031/M032
9 PACKAGE DIMENSIONS
9.1 TSSOP 20 (4.4x6.5x0.9 mm)
Sep. 29, 2020
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M031/M032
9.2 TSSOP 28 (4.4x9.7x1.0 mm)
Sep. 29, 2020
Page 280 of 288
Rev 2.02
M031/M032
9.3 QFN 33L (4X4x0.8 mm Pitch:0.40 mm)
Sep. 29, 2020
Page 281 of 288
Rev 2.02
M031/M032
9.4 LQFP 48L (7x7x1.4 mm Footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
0.024 0.030
0.45
0
L
L
Y
0.039
0.004
7
1
0.10
7
0
0
Sep. 29, 2020
Page 282 of 288
Rev 2.02
M031/M032
9.5 LQFP 64L (7x7x1.4 mm Footprint 2.0 mm)
Sep. 29, 2020
Page 283 of 288
Rev 2.02
M031/M032
9.6 LQFP 128L (14x14x1.4 mm Footprint 2.0 mm)
Sep. 29, 2020
Page 284 of 288
Rev 2.02
M031/M032
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EADC
EBI
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~32 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
Sep. 29, 2020
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M031/M032
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
Sep. 29, 2020
Page 286 of 288
Rev 2.02
M031/M032
11 REVISION HISTORY
Date
Revision
Description
Initial version.
1. Modified ISP ROM size in section 3.2.
2018.12.24
1.00
1.01
2019.02.25
2019.07.15
2. Modified HIRC trim reference clock in section 6.27.2.
1. Updated TBD values in Chapter 8.
2. Changed test condition of data retention from TA to TJ in section 8.7.
1.02
3. Updated Figure 6.3-6 to add a USB block and remove the
temperature sensor block.
4. Added multi-function pin tables in section 4.1.
1. Updated Figure 8.4-1 HIRC vs. Temperature in section 8.4.1.
2. Removed Figure 8.4-2 LIRC vs. Temperature in section 8.4.2.
2019.08.26
2019.11.04
1.03
2.00
Added new part numbers for M031xI / M032xI / M031xG / M032xG /
M032xC / M032xD and updated the description of the new part
numbers.
1. Modified Multi-function Pin Diagram name and Multi-function Pin
Table in section 4.1.4.1 and 4.1.4.2.
2. Changed the Pin Description tables to Pin Mapping tables and Pin
Function Description table in section 4.2 and 4.3.
3. Updated Supply Current Characteristics for M03xB/M03xC/M03xD/
M03xE in section 8.3.1.
4. Updated Band-gap voltage value in Table 8.2-1.
5. Modified the value of SYS_RSTSTS after Power-On-Reset(POR) in
Table 6.3-1
2020.04.29
2.01
6. Updated I/O Output Characteristics in Table 8.3-11
7. Added a note about the Safety factor for High Speed Crystal(HXT)
in Table 8.4-4
8. Added notes about the hardware reference design for ICE_DAT,
ICE_CLK and nRESET pins in section 4.3 and chapter 7.
9. Updated QFN 33L (4X4x0.8 mm Pitch:0.40 mm) Package
Dimensions in section 9.3
1. Added a new part number M031TE3AE and updated the description
of the new part number in chapter 3 and 4.
2020.09.29
2.02
2. Updated Figure 8.4-1 HIRC vs. Temperature in section 8.4.1.
3. Added Figure 8.4-2 LIRC vs. Temperature in section 8.4.2.
Sep. 29, 2020
Page 287 of 288
Rev 2.02
M031/M032
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Sep. 29, 2020
Page 288 of 288
Rev 2.02
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