M032EEAAE [NUVOTON]
Arm® Cortex®-M 32-bit Microcontroller;
| 型号： | M032EEAAE |
| 厂家： | 
NUVOTON |
| 描述： | Arm® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总274页 (文件大小：4826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M031/M032
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M031/M032 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Feb 25, 2019
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TABLE OF CONTENTS
1 GENERAL DESCRIPTION ............................................................................11
2 FEATURES....................................................................................................12
2.1 M031/M032 Features.................................................................................................. 12
3 PARTS INFORMATION.................................................................................22
3.1 Summary....................................................................................................................... 22
3.2 Package Type .............................................................................................................. 22
3.3 M031/M032 Series Selection Guide......................................................................... 23
3.3.1 M031 Control Series ......................................................................................................23
3.3.2 M032 USB Series...........................................................................................................23
3.3.3 M031/M032 Selection Code .........................................................................................24
4 PIN CONFIGURATION ..................................................................................25
4.1 Pin Configuration......................................................................................................... 25
4.1.1 M031 Series Pin Diagram .............................................................................................25
4.1.2 M031 Series Function Pin Diagram.............................................................................30
4.1.3 M032 Series Pin Diagram .............................................................................................41
4.1.4 M032 Series Function Pin Diagram.............................................................................43
4.2 Pin Description............................................................................................................. 45
4.2.1 M031/M032 Series Pin Description .............................................................................45
4.2.2 M031/M032 Series Multi-function Summary Table....................................................56
4.2.3 M031/M032 Series Multi-function Summary Table Sorted by GPIO.......................64
5 BLOCK DIAGRAM.........................................................................................74
5.1 M031/M032 Block Diagram........................................................................................ 74
6 FUNCTIONAL DESCRIPTION.......................................................................75
6.1 Arm® Cortex®-M0 Core............................................................................................... 75
6.2 System Manager ......................................................................................................... 77
6.2.1 Overview..........................................................................................................................77
6.2.2 System Reset..................................................................................................................77
6.2.3 System Power Distribution............................................................................................83
6.2.4 Power Modes and Wake-up Sources..........................................................................83
6.2.5 System Memory Map.....................................................................................................87
6.2.6 SRAM Memory Orginization .........................................................................................89
6.2.7 Chip Bus Matrix ..............................................................................................................90
6.2.8 IRC Auto Trim..................................................................................................................90
6.2.9 Register Lock Control ....................................................................................................91
6.2.10UART0_TXD/USCI0_DAT0 modulation with PWM...................................................96
6.2.11Register Map...................................................................................................................97
6.2.12Register Description.......................................................................................................98
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6.2.13System Timer (SysTick)...............................................................................................131
6.2.14Nested Vectored Interrupt Controller (NVIC)............................................................136
6.2.15System Control Register .............................................................................................152
6.3 Clock Controller ......................................................................................................... 162
6.3.1 Overview........................................................................................................................162
6.3.2 Clock Generator............................................................................................................164
6.3.3 System Clock and SysTick Clock...............................................................................165
6.3.4 Peripherals Clock .........................................................................................................166
6.3.5 Power-down Mode Clock ............................................................................................166
6.3.6 Clock Output .................................................................................................................167
6.3.7 USB Clock Source........................................................................................................167
6.3.8 Register Map.................................................................................................................169
6.3.9 Register Description.....................................................................................................170
6.4 Flash Memory Controller (FMC).............................................................................. 198
6.4.1 Overview........................................................................................................................198
6.4.2 Features.........................................................................................................................198
6.5 General Purpose I/O (GPIO) ................................................................................... 199
6.5.1 Overview........................................................................................................................199
6.5.2 Features.........................................................................................................................199
6.6 PDMA Controller (PDMA)......................................................................................... 200
6.6.1 Overview........................................................................................................................200
6.6.2 Features.........................................................................................................................200
6.7 Timer Controller (TMR)............................................................................................. 201
6.7.1 Overview........................................................................................................................201
6.7.2 Features.........................................................................................................................201
6.8 Watchdog Timer (WDT)............................................................................................ 202
6.8.1 Overview........................................................................................................................202
6.8.2 Features.........................................................................................................................202
6.9 Window Watchdog Timer (WWDT)......................................................................... 203
6.9.1 Overview........................................................................................................................203
6.9.2 Features.........................................................................................................................203
6.10 PWM Generator and Capture Timer (PWM) ................................................... 204
6.10.1Overview........................................................................................................................204
6.10.2Features.........................................................................................................................204
6.11 UART Interface Controller (UART) ................................................................... 206
6.11.1Overview........................................................................................................................206
6.11.2Features.........................................................................................................................206
6.12 Serial Peripheral Interface (SPI) ....................................................................... 208
6.12.1Overview........................................................................................................................208
6.12.2Features.........................................................................................................................208
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6.13 I2C Serial Interface Controller (I2C)................................................................... 209
6.13.1Overview........................................................................................................................209
6.13.2Features.........................................................................................................................209
6.14 USCI - Universal Serial Control Interface Controller (USCI)......................... 210
6.14.1Overview........................................................................................................................210
6.14.2Features.........................................................................................................................210
6.15 USCI – UART Mode............................................................................................ 211
6.15.1Overview........................................................................................................................211
6.15.2Features.........................................................................................................................211
6.16 USCI - SPI Mode................................................................................................. 212
6.16.1Overview........................................................................................................................212
6.16.2Features.........................................................................................................................212
6.17 USCI - I2C Mode .................................................................................................. 214
6.17.1Overview........................................................................................................................214
6.17.2Features.........................................................................................................................214
6.18 External Bus Interface (EBI) .............................................................................. 215
6.18.1Overview........................................................................................................................215
6.18.2Features.........................................................................................................................215
6.19 USB Device Controller (USBD)......................................................................... 216
6.19.1Overview........................................................................................................................216
6.19.2Features.........................................................................................................................216
6.20 CRC Controller (CRC) ........................................................................................ 217
6.20.1Overview........................................................................................................................217
6.20.2Features.........................................................................................................................217
6.21 Hardware Divider (HDIV).................................................................................... 218
6.21.1Overview........................................................................................................................218
6.21.2Features.........................................................................................................................218
6.22 Analog-to-Digital Converter (ADC) ................................................................... 219
6.22.1Overview........................................................................................................................219
6.22.2Features.........................................................................................................................219
6.23 Analog Comparator Controller (ACMP)............................................................ 221
6.23.1Overview........................................................................................................................221
6.23.2Features.........................................................................................................................221
6.24 Peripherals Interconnection ............................................................................... 222
6.24.1Overview........................................................................................................................222
6.24.2Peripherals Interconnect Matrix Table.......................................................................222
7 APPLICATION CIRCUIT..............................................................................223
7.1 Power Supply Scheme ............................................................................................. 223
7.2 Peripheral Application Scheme ............................................................................... 224
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8 ELECTRICAL CHARACTERISTICS............................................................225
8.1 Absolute Maximum Ratings..................................................................................... 225
8.1.1 Voltage Characteristics................................................................................................225
8.1.2 Current Characteristics................................................................................................225
8.1.3 Thermal Characteristics...............................................................................................227
8.1.4 EMC Characteristics ....................................................................................................228
8.1.5 Package Moisture Sensitivity(MSL)...........................................................................229
8.1.6 Soldering Profile ...........................................................................................................230
8.2 General Operating Conditions................................................................................. 231
8.3 DC Electrical Characteristics................................................................................... 232
8.3.1 Supply Current Characteristics...................................................................................232
8.3.2 On-Chip Peripheral Current Consumption................................................................235
8.3.3 Wakeup Time from Low-Power Modes .....................................................................236
8.3.4 I/O Current Injection Characteristics..........................................................................237
8.3.5 I/O DC Characteristics.................................................................................................237
8.4 AC Electrical Characteristics ................................................................................... 239
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC).................................................239
8.4.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................240
8.4.3 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
241
8.4.4 External 4~32 MHz High Speed Clock Input Signal Characteristics ....................243
8.4.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
244
8.4.6 External 32.768 kHz Low Speed Clock Input Signal Characteristics ...................245
8.4.7 PLL Characteristics ......................................................................................................246
8.4.8 I/O AC Characteristics .................................................................................................247
8.5 Analog Characteristics.............................................................................................. 248
8.5.1 LDO ................................................................................................................................248
8.5.2 Reset and Power Control Block Characteristics......................................................248
8.5.3 12-bit SAR ADC............................................................................................................250
8.5.4 Analog Comparator Controller (ACMP).....................................................................253
8.6 Communications Characteristics ............................................................................ 254
8.6.1 SPI Dynamic Characteristics ......................................................................................254
8.6.2 SPI - I2S Dynamic Characteristics .............................................................................257
8.6.3 I2C Dynamic Characteristics .......................................................................................259
8.6.4 USCI - SPI Dynamic Characteristics .........................................................................260
8.6.5 USCI-I2C Dynamic Characteristics ............................................................................263
8.6.6 USB Characteristics.....................................................................................................264
8.7 Flash DC Electrical Characteristics ........................................................................ 265
9 PACKAGE DIMENSIONS............................................................................266
9.1 TSSOP 20 (4.4x6.5x0.9 mm).................................................................................. 266
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9.2 TSSOP 28 (4.4x9.7x1.0 mm).................................................................................. 267
9.3 QFN 33L (4X4x0.8 mm Pitch:0.40 mm) .............................................................. 268
9.4 LQFP 48L (7x7x1.4 mm Footprint 2.0mm) ........................................................ 269
9.5 LQFP 64L (7x7x1.4 mm Footprint 2.0 mm) ....................................................... 270
10ABBREVIATIONS........................................................................................271
10.1 Abbreviations........................................................................................................ 271
11REVISION HISTORY ...................................................................................273
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LIST OF FIGURES
Figure 4.1-1 M031 Series TSSOP 20-pin Diagram........................................................................ 25
Figure 4.1-2 M031 Series TSSOP 28-pin Diagram........................................................................ 26
Figure 4.1-3 M031 Series QFN 33-pin Diagram ............................................................................ 27
Figure 4.1-4 M031 Series LQFP 48-pin Diagram .......................................................................... 28
Figure 4.1-5 M031 Series LQFP 64-pin Diagram .......................................................................... 29
Figure 4.1-6 M031FB0AE Function Pin Diagram........................................................................... 30
Figure 4.1-7 M031FC1AE Function Pin Diagram .......................................................................... 30
Figure 4.1-8 M031EB0AE Function Pin Diagram .......................................................................... 31
Figure 4.1-9 M031EC1AE Function Pin Diagram .......................................................................... 31
Figure 4.1-10 M031TB0AE Function Pin Diagram......................................................................... 32
Figure 4.1-11 M031TC1AE Function Pin Diagram ........................................................................ 33
Figure 4.1-12 M031TD2AE Function Pin Diagram ........................................................................ 34
Figure 4.1-13 M031LC2AE Function Pin Diagram......................................................................... 35
Figure 4.1-14 M031LD2AE Function Pin Diagram......................................................................... 36
Figure 4.1-15 M031LE3AE Function Pin Diagram......................................................................... 37
Figure 4.1-16 M031SC2AE Functon pin Diagram ......................................................................... 38
Figure 4.1-17 M031SD2AE Functon pin Diagram ......................................................................... 39
Figure 4.1-18 M031SE3AE Function Pin Diagram ........................................................................ 40
Figure 4.1-19 M032 Series LQFP 48-pin Diagram ........................................................................ 41
Figure 4.1-20 M032 Series LQFP 64-pin Diagram ........................................................................ 42
Figure 4.1-21 M032LE3AE Function Pin Diagram......................................................................... 43
Figure 4.1-22 M032SE3AE Functon Pin Diagram ......................................................................... 44
Figure 5.1-1 M031/M032 Block Diagram ....................................................................................... 74
Figure 6.1-1 Functional Block Diagram.......................................................................................... 75
Figure 6.2-1 System Reset Sources .............................................................................................. 78
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 80
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 80
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 81
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 82
Figure 6.2-6 NuMicro® M031 Power Distribution Diagram............................................................. 83
Figure 6.2-7 Power Mode State Machine ...................................................................................... 85
Figure 6.2-8 SRAM Memory Organization..................................................................................... 89
Figure 6.2-9 NuMicro® M031 Bus Matrix Diagram......................................................................... 90
Figure 6.3-1 Clock Generator Global View Diagram.................................................................... 163
Figure 6.3-2 Clock Generator Block Diagram.............................................................................. 164
Figure 6.3-3 System Clock Block Diagram .................................................................................. 165
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Figure 6.3-4 HXT Stop Protect Procedure................................................................................... 166
Figure 6.3-5 SysTick Clock Control Block Diagram..................................................................... 166
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 167
Figure 6.3-7 USB Clock Source................................................................................................... 168
Figure 6.16-1 SPI Master Mode Application Block Diagram........................................................ 212
Figure 6.16-2 SPI Slave Mode Application Block Diagram.......................................................... 212
Figure 6.17-1 I2C Bus Timing....................................................................................................... 214
Figure 8.1-1 Soldering Profile from J-STD-020C......................................................................... 230
Figure 8.4-1 HIRC vs. Temperature............................................................................................. 239
Figure 8.4-2 LIRC vs. Temperature ............................................................................................. 240
Figure 8.4-3 Typical Crystal Application Circuit ........................................................................... 242
Figure 8.4-4 Typical 32.768 kHz Crystal Application Circuit........................................................ 244
Figure 8.5-1 Power Ramp Up/Down Condition............................................................................ 249
Figure 8.6-1 SPI Master Mode Timing Diagram .......................................................................... 254
Figure 8.6-2 SPI Slave Mode Timing Diagram ............................................................................ 256
Figure 8.6-3 I2S Master Mode Timing Diagram........................................................................... 257
Figure 8.6-4 I2S Slave Mode Timing Diagram ............................................................................. 258
Figure 8.6-5 I2C Timing Diagram ................................................................................................. 259
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram................................................................. 260
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram................................................................... 262
Figure 8.6-8 USCI-I2C Timing Diagram........................................................................................ 263
Table 10.1-1 List of Abbreviations................................................................................................ 272
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List of Tables
Table 3.3-1 M031/M032 Series Selection Code ............................................................................ 24
Table 6.2-1 Reset Value of Registers............................................................................................ 79
Table 6.2-2 Power Mode Table...................................................................................................... 84
Table 6.2-3 Power Mode Difference Table .................................................................................... 84
Table 6.2-4 Power Mode Difference Table .................................................................................... 84
Table 6.2-5 Clocks in Power Modes .............................................................................................. 86
Table 6.2-6 Condition of Entering Power-down Mode Again......................................................... 86
Table 6.2-7 Address Space Assignments for On-Chip Controllers................................................ 88
Table 6.2-8 Protected Register List ............................................................................................... 95
Table 6.2-9 Exception Model ....................................................................................................... 137
Table 6.2-10 Interrupt Number Table........................................................................................... 138
Table 6.2-11 Vector Figure Format.............................................................................................. 138
Table 6.2-12 Priority Grouping..................................................................................................... 157
Table 6.3-1 Symbol Definition of PLL Output Frequency Formula .............................................. 189
Table 6.11-1 NuMicro® M031 Series UART Features ................................................................. 207
Table 6.24-1 Peripherals Interconnect Matrix Table.................................................................... 222
Table 8.1-1 Voltage Characteristics............................................................................................. 225
Table 8.1-2 Current Characteristics ............................................................................................. 226
Table 8.1-3 Thermal Characteristics............................................................................................ 227
Table 8.1-4 EMC Characteristics ................................................................................................. 228
Table 8.1-5 Package Moisture Sensitivity (MSL)......................................................................... 229
Table 8.1-6 Soldering Profile........................................................................................................ 230
Table 8.2-1 General Operating Conditions .................................................................................. 231
Table 8.3-1 Current Consumption in Normal Run Mode ............................................................. 232
Table 8.3-2 Current Consumption in Idle Mode........................................................................... 233
Table 8.3-3 Chip Current Consumption in Power-down Mode .................................................... 234
Table 8.3-4 Peripheral Current Consumption .............................................................................. 235
Table 8.3-5 Low-power Mode Wakeup Timings .......................................................................... 236
Table 8.3-6 I/O Current Injection Characteristics......................................................................... 237
Table 8.3-7 I/O Input Characteristics ........................................................................................... 237
Table 8.3-8 I/O Output Characteristics ........................................................................................ 238
Table 8.3-9 nRESET Input Characteristics.................................................................................. 238
Table 8.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics........................... 239
Table 8.4-238.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ........................... 240
Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator ........................................ 241
Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics .......................................... 242
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Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal ................................................. 243
Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator........................................ 244
Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics ......................................... 244
Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal ................................................ 245
Table 8.4-9 PLL Characteristics................................................................................................... 246
Table 8.4-10 I/O AC Characteristics ............................................................................................ 247
Table 8.5-1 Reset and Power Control Unit .................................................................................. 248
Table 8.5-2 ACMP Characteristics............................................................................................... 253
Table 8.6-1 SPI Master Mode Characteristics ............................................................................. 254
Table 8.6-2 SPI Slave Mode Characteristics ............................................................................... 255
Table 8.6-3 I2S Characteristics .................................................................................................... 257
Table 8.6-4 I2C Characteristics .................................................................................................... 259
Table 8.6-5 USCI-SPI Master Mode Characteristics ................................................................... 260
Table 8.6-6 USCI-SPI Slave Mode Characteristics ..................................................................... 261
Table 8.6-7 USCI-I2C Characteristics .......................................................................................... 263
Table 8.6-8 USB Full-Speed Characteristics ............................................................................... 264
Table 8.6-9 USB Full-Speed PHY Characteristics....................................................................... 264
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M031/M032
1
GENERAL DESCRIPTION
The new NuMicro® M031/M032 series 32-bit microcontroller based on Arm® Cortex® -M0 core features
1.8V ~ 3.6V operating voltage, 5V I/O tolerant and runs up to 48 MHz. It provides a solution for the
applications that need low-voltage interface connection operation, such as mobile devices, application
processor connected peripheral controllers, IoT sensor devices, motor control, industrial control, and
consumer devices.
The M031/M032 series supports up to 128 Kbytes of Flash memory, up to 16 Kbytes of SRAM, for the
program code and runtime storage. A special design 512 bytes SPROM (Security Protection ROM) is
to protect user’s code or library been read. It supports 4 Kbytes Flash memory of ISP (In-System
Programming) to easily upgrade new firmware and the IAP (In-Application Programming) feature that
can upgrade firmware while program is running.
The enhanced fast 2 MSPS conversion rate of 12-bit ADC, comparator and PWM control provide a
fast and precise data conversion of the voltage, current, and sensor data, and fast response control for
the external device, such as the current/voltage feedback from motor control or sensing devices.
The M031/M032 series provides plenty peripherals such as Universal Serial Control Interface (USCI)
that can be set as UART/SPI/I2C flexibly, up to 4-ch UART, 2-ch SPI/I2S, 3-ch I2C, USB, 16-ch 12-bit
ADC, 12-ch 16-bit PWM, Hardware Divider and Comparator, etc. Besides, it offers EBI, PDMA and
One-Wire UART special features for various application demands.
The M032 series is all based on the M031 and enhanced with the crystal-less USB 2.0 full-speed
device feature to provide more possibilities of USB related application.
The M031/M032 series supports different package sizes from TSSOP 20-pin, TSSOP 28-pin, QFN 33-
pin, to LQFP 48-pin and LQFP 64-pin. Different part numbers with same package are pin-to-pin
compatible. It is easy for users to find the suitable part number for the application.
The NuMicro® M031/M032 series is suitable for a wide range of applications such as:
Laser Distance Meter
Air Detector/Cleaner
Mobile LCD Panel Controller
IoT Sensing Device
HMI Controller
Micro Printer
Gaming Keyboard and Mouse
WPC Wireless Charger
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2
FEATURES
2.1
M031/M032 Features
Core and System
Arm® Cortex® -M0 processor, running up to 48 MHz
Built-in Nested Vectored Interrupt Controller (NVIC)
24-bit system tick timer
Arm® Cortex® -M0
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
Hardware Divider (HDIV)
32-bit quotient and 32-bit remainder outputs (16-bit remainder
with sign extends to 32-bit)
6 HCLK clocks taken for one cycle calculation
Two-level BOD with brown-out interrupt and reset option.
(2.5V/2.0V)
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
LVR with 1.7V threshold voltage level
96-bit Unique ID (UID)
Security
128-bit Unique Customer ID (UCID)
Memories
Up to 128 KB application ROM (APROM)
Up to 4 KB Flash for user program loader (LDROM)
512 bytes page erase for all embedded flash
Supports CRC-32 checksum calculation function
Flash
Hardware external read protection of whole flash memory by
Security Lock Bit
Supports In-System-Programming (ISP), In-Application-
Programming (IAP) update embedded flash memory
Supports 2-wired ICP update through SWD/ICE interface
Up to 16 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
SRAM
Cyclic Redundancy
Calculation (CRC)
Supports four common polynomials CRC-CCITT, CRC-8,
CRC-16, and CRC-32
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Programmable initial value
Supports programmable order reverse setting for input data
and CRC checksum
Supports programmable 1’s complement setting for input data
and CRC checksum.
Supports 8/16/32-bit of data width
Interrupt generated once checksum error occurs
Programmable seed value
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
Supports up to 5 independent configurable channels for
automatic data transfer between memories and peripherals
Channel 0, 1 supports time-out function
Basic and Scatter-Gather Transfer modes
Each channel supports circular buffer management using
Scatter-Gather Transfer mode
Two types of priorities modes: Fixed-priority and Round-robin
modes
Peripheral DMA (PDMA)
Transfer data width of 8, 16, and 32 bits
Single and burst transfer type
Source and destination address can be increment or fixed.
PDMA transfer count up to 65536
Request source can be from software, SPI/I2S, USPI, UART,
UUART, I2C, ADC, PWM and Timer
Clocks
4~24 MHz High-speed eXternal crystal oscillator (HXT) for
precise timing operation
32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC
function and low-power system operation
External Clock Source
Supports clock failure detection for external crystal oscillators
and exception generatation (NMI)
48 MHz High-speed Internal RC oscillator (HIRC) trimmed to
2% accuracy that can optionally be used as a system clock
38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wakeup operation
Internal Clock Source
Up to 96 MHz on-chip PLL, sourced from HIRC or HXT, allows
CPU operation up to the maximim CPU frequency without the
need for a high-frequency crystal
Timers
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TIMER
Four sets of 32-bit timers, each timer having one 24-bit up
counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous
counting operation modes
24-bit up counter value is readable through CNT
(TIMERx_CNT[23:0])
Supports event counting function from external pin.
Supports event counting source from internal USB SOF signal
24-bit capture value is readable through CAPDAT
(TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports internal capture triggered while internal ACMP output
signal and LIRC transition
Supports chip wake-up from Idle/Power-down mode if a timer
interrupt signal is generated
Supports Timer0 ~ Timer3 time-out interrupt signal or capture
interrupt signal to trigger PWM, ADC, PDMA function
Supports Inter-Timer trigger mode
PWM
32-bit Timer
Supports maximum clock source frequency up to 96 MHz
Supports up to two PWM modules, each module provides 6
output channels.
Supports independent mode for PWM output/Capture input
channel
Supports complementary mode for 3 complementary paired
PWM output channels
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin, ACMP and system safety events: clock
failed, Brown-out detection and CPU lockup.
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake
interrupt cleared
Level detect brake source to auto recover function after brake
condition removed
Supports interrupt on the following events:
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PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA request from input capture event
20-bit free running up counter for WDT time-out interval.
Selectable time-out interval (24 ~ 220) and the time-out interval
is 416us ~ 27.3 s if WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63.
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Watchdog
Supports selectable WDT reset delay period, including 1026,
130, 18 or 3 WDT_CLK reset delay period.
Supports to force WDT enabled after chip powered on or reset
by setting CWDTEN[2:0] in Config0 register.
Supports WDT time-out wake-up function only if WDT clock
source is selected as LIRC or LXT.
Clock sources from HCLK/2048 (default selection) or LIRC
Window set by 6-bit down counter with 11-bit prescale
WWDT counter suspends in Idle/Power-down mode
Supports Interrupt
Window Watchdog
Analog Interfaces
Analog input voltage range: 0 ~ AVDD.
Analog input voltage range: 0 ~ AVDD
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels or 8 differential
analog input channels
Maximum ADC peripheral clock frequency is 48 MHz.
Up to 2 MSPS sampling rate.
Analog-to-Digital
Converter (ADC)
Four operation modes:
Single mode: A/D conversion is performed one time on a
specified channel.
Burst mode: A/D converter samples and converts the specified
single channel and sequentially stores the result in FIFO.
Single-cycle Scan mode: A/D conversion is performed only one
cycle on all specified channels with the sequence from the
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M031/M032
smallest numbered channel to the largest numbered channel.
Continuous Scan mode: A/D converter continuously performs
Single-cycle Scan mode until software stops A/D conversion.
An A/D conversion can be started by:
Software Write 1 to ADST bit.
External pin (STADC).
Timer 0~3 overflow pulse trigger.
PWM trigger.
Each conversion result is held in data register of each channel
with valid and overrun indicators.
Conversion result can be compared with specified value and
user can select whether to generate an interrupt when
conversion result matches the compare register setting.
1 internal channels, they are band-gap voltage (VBG).
Supports PDMA transfer mode.
Supports Calibration mode.
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two rail-to-rail analog comparators
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports:
–
–
4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or
ACMP0_P3
3 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Analog Comparator
(ACMP)
Internal band-gap voltage (VBG)
ACMP1 supports
–
4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or
ACMP1_P3
–
3 negative sources:
ACMP1_N
–
–
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt
event condition is programmable)
Supports triggers for break events and cycle-by-cycle control
for PWM
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M031/M032
Supports window compare mode and window latch mode
Communication Interfaces
Supports up to 3 UARTs: UART0, UART1, UART2
UART baud rate clock from LXT(32.768 KHz) with 9600bps
can work normally in power down mode even system clock is
stopped (UART0/UART1 support)
Support Single-wire function mode
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for
data payloads (UART0/UART1 support)
Supports hardware auto-flow control (RX, TX, CTS and RTS)
and programmable receiver buffer trigger level (UART0/UART1
support)
Supports programmable baud rate generator for each channel
individually
Supports 8-bit receiver buffer time-out detection function
(UART0/UART1 support)
Programmable transmitting data delay time between the last
stop and the next start bit by setting DLY (UART_TOUT [15:8])
(UART0/UART1 support)
Supports Auto-Baud Rate measurement and baud rate
compensation function(UART0/UART1 support)
UART
Supports break error, frame error, parity error and
receive/transmit buffer overflow detection function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit
generation and detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode (UART0/UART1 support)
Supports for 3/16 bit duration for normal mode
Supports RS-485 mode (UART0/UART1 support)
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin
to control RS-485 transmission direction
Supports nCTS, incoming data, Received Data FIFO reached
threshold and RS-485
Address Match (AAD mode) wake-up function (UART0/UART1
support)
Supports PDMA mode
Up to 2 sets of I2C devices
I2C
Master/Slave mode
Bidirectional data transfer between masters and slaves
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M031/M032
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Arbitration between simultaneously transmitting masters
without corruption of serial data on the bus
Serial clock synchronization allows devices with different bit
rates to communicate via one serial bus
Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer
Supports 14-bit time-out counter requesting the I2C interrupt if
the I2C bus hangs up and timer-out counter overflows
Programmable clocks allow versatile rate control
Multiple address recognition (four slave addresses with mask
option)
Supports setup/hold time programmable
Multi-address Power-down wake-up function
Supports PDMA transfer
Supports one SPI/ I2S controller
Pin defined in SPI and I2S mode:
SPI
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-level of 32-bit (or 8-level of 16-bit) depth
transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Byte or Word Suspend mode
Master and slave mode up to 24 MHz (when chip works at VDD
= 1.8 ~3.6V)
SPI/I2S
Supports one data channel half-duplex transfer
Support receive-only mode
SPI Supports PDMA transfer
I2S
Supports Master or Slave mode operation
Capable of handling 8-, 16-, 24- and 32-bit word sizes in I2S
mode
Provides separate 4-level depth transmit and receive FIFO
buffers in I2S mode
Generates interrupt requests when buffer levels cross a
programmable boundary
Supports monaural and stereo audio data in I2S mode
Supports PCM mode A, PCM mode B, I2S and MSB justified
data format in I2S mode
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M031/M032
Supports PDMA transfer
Supports one set of USCI
USCI supports UART, SPI and I2C function
Single byte TX and RX buffer mode
UART
One transmit buffer and two receive buffer for data payload
Hardware auto flow control function and programmable flow
control trigger level
Programmable baud-rate generator
Support 9-bit Data Transfer
Baud rate detection possible by built-in capture event of baud
rate generator
Supports Wake-up function (Data and nCTS Wakeup Only)
Supports PDMA transfer
SPI
Master or Slave mode operation (maximum frequency: master
= fPCLK / 2, slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
One transmit buffer and two receive buffer for data payload
MSB first or LSB first transfer sequence
Universal Serial Control
Interface (USCI)
Word suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Wake-up function: input slave select transition
Supports one data channel half-duplex transfer
I2C
Full master and slave device capability
7-bit addressing mode (Not support 10-bit mode)
Communication in standard mode (100 kbps) or in fast mode
(up to 400 kbps)
Multi-master bus
One transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports Bus monitor mode
Power-down wake-up by data toggle or address match
Multiple address recognition
Device address flag
Setup/hold time programmable
External Bus Interface
(EBI)
Up to two memory banks
Dedicated external chip select pin with polarity control for each
Feb 25, 2019
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Rev. 1.01
M031/M032
bank
Two dedicated external chip select pins for each memory block
Accessible space up to 1 M bytes for each bank, actually
external addressable space is dependent on package pin out
8-/16-bit data width
Byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Timing parameters individual adjustment for each memory
block
Supports LCD interface i80 mode
Supports Continuous Data Access Mode
Supports PDMA mode
Four I/O modes:
–
–
–
–
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input
I/O pin configured as interrupt source with edge/level trigger
setting
GPIO
Supports high drive and high sink current I/O
I/O pin internal pull-up resistor enabled only in Quasi-
bidirectional I/O mode
Maximum I/O Speed is 24 MHz when VDD = 1.8 ~ 3.6V.
Supports input 5V tolerance, except analog pin (PA.10 ~ 11;
PB.0 ~ 15; PF.2 ~ 5; all USB pin and nRESET pin).
Supports up to 15/23/27/42/55 GPIOs for TSSOP20/28,
QFN33 and LQFP48/64 respectively
Enabling the pin interrupt function will also enable the wake-up
function
Advanced Connectivity
One set of USB 2.0 FS Device (12 Mbps)
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous
transfers
USB 2.0 Full Speed
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
Supports Crystal-less function
Feb 25, 2019
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M031/M032
Start of Frame (SOF) locked clock pulse generation
Feb 25, 2019
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Rev. 1.01
M031/M032
3 PARTS INFORMATION
3.1
Summary
Part No.
M031
USB FS
–
√
M032
3.2
Package Type
Part No.
TSSOP20
TSSOP28
QFN33
LQFP48
LQFP64
M031
M031FB0AE
M031FC1AE
M031EB0AE
M031EC1AE
M031TB0AE
M031TC1AE
M031TD2AE
M031LC2AE
M031LD2AE
M031LE3AE
M031SC2AE
M031SD2AE
M031SE3AE
Control Series
M032
-
-
-
M032LE3AE
M032SE3AE
USB Series
Feb 25, 2019
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Rev. 1.01
M031/M032
3.3
M031/M032 Series Selection Guide
3.3.1 M031 Control Series
Connectivity
Part Number
M031FB0AE
M031EB0AE
M031TB0AE
M031FC1AE
M031EC1AE
M031TC1AE
M031LC2AE
M031SC2AE
M031TD2AE
M031LD2AE
M031SD2AE
M031LE3AE
M031SE3AE
16
16
16
32
32
32
32
32
64
64
64
2
2
2
4
4
4
8
8
8
8
8
2
2
2
2
2
2
2
2
2
2
2
4
4
15
23
27
15
23
27
42
55
27
42
55
42
55
2
2
2
4
4
4
4
4
4
4
4
4
4
6
6
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
7-ch TSSOP20
9-ch TSSOP28
-
6
-
-
-
-
-
-
10-ch
QFN33
6
2
2
2
5
5
5
5
5
5
5
-
-
-
-
-
7-ch TSSOP20
9-ch TSSOP28
6
-
-
-
-
-
6
-
-
-
√
√
√
√
√
√
√
√
-
10-ch
12-ch
16-ch
10-ch
12-ch
16-ch
12-ch
16-ch
QFN33
LQFP48
LQFP64
QFN33
12
12
12
12
12
12
12
1
1
1
1
1
1
1
-
√
√
√
√
√
√
√
2
2
2
2
2
2
2
-
-
-
LQFP48
LQFP64
LQFP48
LQFP64
-
128 16
√
√
128 16
USCI*: supports UART, SPI or I2C
3.3.2 M032 USB Series
Connectivity
Part Number
M032LE3AE
M032SE3AE
128 16
128 16
4
4
42
55
4
12
12
5
5
1
1
1
3
3
1
1
2
2
√
√
√
√
2
2
12-ch
16-ch
LQFP48
LQFP64
4
1
USCI*: supports UART, SPI or I2C
Feb 25, 2019
Page 23 of 274
Rev. 1.01
M031/M032
3.3.3 M031/M032 Selection Code
M03
Core
1
S
E
3
A
E
Line
Package
Flash
SRAM
Reserved
Temperature
Cortex®-M0
1: Control Line
2: USB Line
F: TSSOP20
(4.4x6.5 mm)
B: 16 KB
0: 2 KB
E: -40°C~105°C
C: 32 KB
D: 64 KB
E: 128 KB
1: 4 KB
E: TSSOP28
(4.4x9.7 mm)
2: 8/12 KB
3: 16 KB
T: QFN33
(4x4 mm)
L: LQFP48
(7x7 mm)
S: LQFP64
(7x7 mm)
Table 3.3-1 M031/M032 Series Selection Code
Feb 25, 2019
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Rev. 1.01
M031/M032
4 PIN CONFIGURATION
Users can find pin configuration information in chapter 4 or by using NuTool - PinConfigure. The
NuTool - PinConfigure contains all NuMicro® Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
4.1
Pin Configuration
4.1.1 M031 Series Pin Diagram
4.1.1.1 TSSOP20 Package
Corresponding Part Number: M031FB0AE, M031FC1AE
1
20
19
18
17
VSS
PF.1
2
3
LDO_CAP
VDD
PF.0
nRESET
PA.0
4
PB.14
PB.13
PB.12
AVDD
5
16 PA.1
15 PA.2
6
PA.3
PF.2
PF.3
PB.2
7
14
13
12
11
PB.5
8
PB.4
9
PB.3
10
Figure 4.1-1 M031 Series TSSOP 20-pin Diagram
Feb 25, 2019
Page 25 of 274
Rev. 1.01
M031/M032
4.1.1.2 TSSOP28 Package
Corresponding Part Number: M031EB0AE, M031EC1AE
1
28
27
26
25
24
23
PA.12
PC.0
2
PA.13
PC.1
3
PA.14
PF.1
4
5
PA.15
VSS
PF.0
nRESET
PA.0
6
LDO_CAP
VDD
7
22 PA.1
21 PA.2
PB.14
PB.13
PB.12
AVDD
8
PA.3
PF.2
PF.3
PB.0
PB.1
PB.2
9
20
19
18
17
16
15
10
11
12
13
14
PB.5
PB.4
PB.3
Figure 4.1-2 M031 Series TSSOP 28-pin Diagram
Feb 25, 2019
Page 26 of 274
Rev. 1.01
M031/M032
4.1.1.3 QFN33 Package
Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
Top transparent view
PB.15
PA.1
QFN33
PB.14
PA.2
PB.13
PA.3
PB.12
PF.2
33 VSS
AVDD
PF.3
Figure 4.1-3 M031 Series QFN 33-pin Diagram
Feb 25, 2019
Page 27 of 274
Rev. 1.01
M031/M032
4.1.1.4 LQFP48 Package
Corresponding Part Number: M031LC2AE, M031LD2AE, M031LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP48
AVSS
PB.7
PB.6
Figure 4.1-4 M031 Series LQFP 48-pin Diagram
Feb 25, 2019
Page 28 of 274
Rev. 1.01
M031/M032
4.1.1.5 LQFP64 Package
Corresponding Part Number: M031SC2AE, M031SD2AE, M031SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
50
LDO_CAP
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
51
VDD
52
PC.14
53
PB.15
54
PB.14
55
PB.13
56
PB.12
LQFP64
57
AVDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
Figure 4.1-5 M031 Series LQFP 64-pin Diagram
Feb 25, 2019
Page 29 of 274
Rev. 1.01
M031/M032
4.1.2 M031 Series Function Pin Diagram
4.1.2.1 TSSOP20 Package
Corresponding Part Number: M031FB0AE, M031FC1AE
1
2
20
VSS
LDO_CAP
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
19
18
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
VDD
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
5
6
7
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
9
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
10
Figure 4.1-6 M031FB0AE Function Pin Diagram
1
2
20
19
18
VSS
LDO_CAP
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
nRESET
3
VDD
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
4
17 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
16 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
15 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
14 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
5
6
7
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
9
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
10
Figure 4.1-7 M031FC1AE Function Pin Diagram
Feb 25, 2019
Page 30 of 274
Rev. 1.01
M031/M032
4.1.2.2 TSSOP28 Package
Corresponding Part Number: M031EB0AE, M031EC1AE
1
2
28
27
26
25
I2C1_SCL / PA.12
PC.0 / UART2_RXD / I2C0_SDA
I2C1_SDA / PA.13
PC.1 / UART2_TXD / I2C0_SCL
3
UART0_TXD / PA.14
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / PA.15
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
VDD
7
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
8
9
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10
11
12
13
14
19
18
17
16
15
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / INT3
Figure 4.1-8 M031EB0AE Function Pin Diagram
1
2
28
27
26
25
I2C1_SCL / PA.12
PC.0 / UART2_RXD / I2C0_SDA
I2C1_SDA / PA.13
PC.1 / UART2_TXD / I2C0_SCL
3
UART0_TXD / PA.14
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / PA.15
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
21 PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
20 PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
VDD
7
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
8
9
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / TM0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC0_CH5 / PB.5
INT1 / TM1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC0_CH4 / PB.4
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC0_CH3 / PB.3
PB.0 / ADC0_CH0 / UART2_RXD / SPI0_I2SMCLK / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE1
PB.1 / ADC0_CH1 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE0
PB.2 / ADC0_CH2 / I2C1_SDA / UART1_RXD / PWM0_CH3 / TM3 / INT3
Figure 4.1-9 M031EC1AE Function Pin Diagram
Feb 25, 2019
Page 31 of 274
Rev. 1.01
M031/M032
4.1.2.3 QFN33 Package
Corresponding Part Number: M031TB0AE, M031TC1AE, M031TD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
Top transparent view
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-10 M031TB0AE Function Pin Diagram
Feb 25, 2019
Page 32 of 274
Rev. 1.01
M031/M032
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
Top transparent view
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
PWM0_BRAKE1 / TM0_EXT / UART0_nCTS / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / UART0_nRTS / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / UART0_TXD / SPI0_MISO / ADC0_CH13 / PB.13
TM3_EXT / UART0_RXD / SPI0_MOSI / ADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-11 M031TC1AE Function Pin Diagram
Feb 25, 2019
Page 33 of 274
Rev. 1.01
M031/M032
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
Top transparent view
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
QFN33
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-12 M031TD2AE Function Pin Diagram
Feb 25, 2019
Page 34 of 274
Rev. 1.01
M031/M032
4.1.2.4 LQFP48 Package
Corresponding Part Number: M031LC2AE, M031LD2AE, M031LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
LQFP48
AVSS
ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7
ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-13 M031LC2AE Function Pin Diagram
Feb 25, 2019
Page 35 of 274
Rev. 1.01
M031/M032
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
LDO_CAP
VDD
PF.15 / PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
PA.0 / SPI0_MOSI / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / SPI0_MISO / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / SPI0_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3
TM1 / USCI0_CTL0 / SPI0_I2SMCLK / PC.14
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / ADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / ADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / ADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / ADC0_CH12 / PB.12
AVDD
PA.3 / SPI0_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PA.4 / SPI0_I2SMCLK / UART0_nRTS / UART0_RXD / I2C0_SDA / PWM0_CH1
PA.5 / UART0_nCTS / UART0_TXD / I2C0_SCL / PWM0_CH0
PA.6 / UART0_RXD / I2C1_SDA / PWM1_CH5 / ACMP1_WLAT / TM3 / INT0
PA.7 / UART0_TXD / I2C1_SCL / PWM1_CH4 / ACMP0_WLAT / TM2 / INT1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
LQFP48
AVSS
ACMP0_O / INT5 / PWM1_CH4 / PWM1_BRAKE0 / UART1_TXD / ADC0_CH7 / PB.7
ACMP1_O / INT4 / PWM1_CH5 / PWM1_BRAKE1 / UART1_RXD / ADC0_CH6 / PB.6
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-14 M031LD2AE Function Pin Diagram
Feb 25, 2019
Page 36 of 274
Rev. 1.01
M031/M032
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL /
/
I2C1_SDA
I2C1_SCL
UART0_RXD
PWM0_CH0
/
PWM0_CH3
PWM0_CH2 PWM1_BRAKE1
I2C0_SDA / PWM0_CH1
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA XT1_OUT
/
/
INT4
/
/
/
/
/
/
I2C0_SCL / XT1_IN
Figure 4.1-15 M031LE3AE Function Pin Diagram
Feb 25, 2019
Page 37 of 274
Rev. 1.01
M031/M032
4.1.2.5 LQFP64 Package
Corresponding Part Number: M031SC2AE, M031SD2AE, M031SE3AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
PWM0_CH5
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
UART1_TXD
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
PWM1_CH3
PWM1_CH2
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-16 M031SC2AE Functon pin Diagram
Feb 25, 2019
Page 38 of 274
Rev. 1.01
M031/M032
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
PWM0_CH5
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
UART1_TXD
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
PWM1_CH3
PWM1_CH2
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
UART0_RXD / I2C0_SDA / XT1_OUT
Figure 4.1-17 M031SD2AE Functon pin Diagram
Feb 25, 2019
Page 39 of 274
Rev. 1.01
M031/M032
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
/
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
EBI_ADR16
EBI_ADR17
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
PWM1_CH3
PWM1_CH2
I2C0_SDA
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
EBI_nCS0
/
UART1_TXD
/
EBI_nWRL
EBI_nCS1
/
UART0_RXD
/
XT1_OUT
Figure 4.1-18 M031SE3AE Function Pin Diagram
Feb 25, 2019
Page 40 of 274
Rev. 1.01
M031/M032
4.1.3 M032 Series Pin Diagram
4.1.3.1 LQFP48 Package
Corresponding Part Number: M032LE3AE
37
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
38
LDO_CAP
39
VDD
40
PC.14
41
PB.15
42
PB.14
LQFP48
43
44
45
46
47
48
PB.13
PB.12
AVDD
AVSS
PB.7
PB.6
PF.3
Figure 4.1-19 M032 Series LQFP 48-pin Diagram
Feb 25, 2019
Page 41 of 274
Rev. 1.01
M031/M032
4.1.3.2 LQFP64 Package
Corresponding Part Number: M032SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
PF.15
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
50
LDO_CAP
51
VDD
52
PC.14
53
PB.15
54
PB.14
55
PB.13
56
PB.12
LQFP64
57
AVDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
Figure 4.1-20 M032 Series LQFP 64-pin Diagram
Feb 25, 2019
Page 42 of 274
Rev. 1.01
M031/M032
4.1.4 M032 Series Function Pin Diagram
4.1.4.1 LQFP48 Package
Corresponding Part Number: M032LE3AE
37
24
23
22
21
20
19
18
17
16
15
14
13
VSS
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
38
LDO_CAP
/
39
VDD
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
40
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
41
42
43
44
45
46
47
48
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL /
/
I2C1_SDA
I2C1_SCL
UART0_RXD
PWM0_CH0
/
PWM0_CH3
PWM0_CH2 PWM1_BRAKE1
I2C0_SDA / PWM0_CH1
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
EBI_nWRL
EBI_nWRH
/
/
ADC0_CH7
ADC0_CH6
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA XT1_OUT
/
/
INT4
/
/
/
/
/
/
I2C0_SCL / XT1_IN
Figure 4.1-21 M032LE3AE Function Pin Diagram
Feb 25, 2019
Page 43 of 274
Rev. 1.01
M031/M032
4.1.4.2 LQFP64 Package
Corresponding Part Number: M032SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
PF.15 PWM0_BRAKE0 / PWM0_CH1 / TM2 / CLKO / INT4
50
LDO_CAP
/
51
VDD
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
SPI0_MOSI
SPI0_MISO
/
/
UART0_RXD
UART0_TXD
/
UART1_nRTS PWM0_CH5
/
52
TM1
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
/
UART1_nCTS / PWM0_CH4
53
54
55
56
57
58
59
60
61
62
63
64
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
UART0_TXD
UART0_RXD
/
PWM1_CH0
PWM1_CH1
USCI0_DAT0
USCI0_CLK
/
UART0_nCTS
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
ADC0_CH15
ADC0_CH14
ADC0_CH13
ADC0_CH12
SPI0_CLK
SPI0_SS
SPI0_I2SMCLK
UART0_nCTS
/
UART1_RXD
UART1_TXD
UART0_nRTS
UART0_TXD I2C0_SCL
TM3 INT1
/
I2C1_SDA
I2C1_SCL PWM0_CH2
UART0_RXD I2C0_SDA
PWM0_CH0
/
PWM0_CH3
/
/
/
UART0_nRTS
/
/
/
/
/
/
CLKO
/
PWM1_BRAKE1
/ PWM0_CH1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
/
TM3_EXT
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
/
VREF
AVSS
VSS
SPI0_I2SMCLK
/
I2C1_SCL
I2C1_SDA
/
/
UART0_nCTS
UART0_nRTS
/
EBI_ADR16
EBI_ADR17
/
/
ADC0_CH11
ADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
/
/
/
/
/
/
UART1_nCTS
UART1_nRTS
/
UART0_TXD
UART0_RXD
/
/
EBI_ADR18
EBI_ADR19
/
/
/
ADC0_CH9
ADC0_CH8
ADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
PWM1_CH3
PWM1_CH2
I2C0_SDA
/
/
TM1
TM0
/
/
INT2
INT3
/
ACMP0_O
/
INT5
/
PWM1_CH4
/
PWM1_BRAKE0
/
EBI_nCS0
/
UART1_TXD
/
EBI_nWRL
EBI_nCS1
/
UART0_RXD
/
XT1_OUT
Figure 4.1-22 M032SE3AE Functon Pin Diagram
Feb 25, 2019
Page 44 of 274
Rev. 1.01
M031/M032
4.2
Pin Description
Different part number with the same package might have a different function. Please refer to the
selection guide in section 3.3.
4.2.1 M031/M032 Series Pin Description
20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
PB.6
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH6
EBI_nWRH
UART1_RXD
EBI_nCS1
A
O
I
MFP1
MFP2
MFP6
MFP8
ADC0 channel 6 analog input.
EBI high byte write enable output pin
UART1 data receiver input pin.
EBI chip select 1 output pin.
48 48
1
1
O
I
PWM1_BRAKE1
PWM1_CH5
INT4
MFP11 PWM1 Brake 1 input pin.
I/O
I
MFP12 PWM1 channel 5 output/capture input.
MFP13 External interrupt 4 input pin.
MFP15 Analog comparator 1 output pin.
ACMP1_O
PB.5
O
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH5
ACMP1_N
I2C0_SCL
PWM0_CH0
UART2_TXD
TM0
A
A
MFP1
MFP1
MFP6
ADC0 channel 5 analog input.
Analog comparator 1 negative input pin.
I2C0 clock pin.
I/O
I/O
O
8
12
1
1
1
2
2
MFP11 PWM0 channel 0 output/capture input.
MFP13 UART2 data transmitter output pin.
MFP14 Timer0 event counter input/toggle output pin.
MFP15 External interrupt 0 input pin.
I/O
INT0
PB.4
I
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH4
ACMP1_P1
I2C0_SDA
PWM0_CH1
UART2_RXD
TM1
A
A
MFP1
MFP1
MFP6
ADC0 channel 4 analog input.
Analog comparator 1 positive input 1 pin.
I2C0 data input/output pin.
I/O
I/O
I
9
13
2
2
2
3
3
MFP11 PWM0 channel 1 output/capture input.
MFP13 UART2 data receiver input pin.
I/O
MFP14 Timer1 event counter input/toggle output pin.
MFP15 External interrupt 1 input pin.
INT1
PB.3
I
I/O
MFP0
MFP1
General purpose digital I/O pin.
ADC0 channel 3 analog input.
10 14
3
3
3
4
4
ADC0_CH3
A
Feb 25, 2019
Page 45 of 274
Rev. 1.01
M031/M032
20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
ACMP0_N
I2C1_SCL
UART1_TXD
PWM0_CH2
PWM0_BRAKE0
TM2
A
I/O
O
MFP1
MFP4
MFP6
Analog comparator 0 negative input pin.
I2C1 clock pin.
UART1 data transmitter output pin.
I/O
I
MFP11 PWM0 channel 2 output/capture input.
MFP13 PWM0 Brake 0 input pin.
I/O
MFP14 Timer2 event counter input/toggle output pin.
MFP15 External interrupt 2 input pin.
INT2
PB.2
I
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH2
ACMP0_P1
I2C1_SDA
UART1_RXD
PWM0_CH3
TM3
A
A
MFP1
MFP1
MFP4
MFP6
ADC0 channel 2 analog input.
Analog comparator 0 positive input 1 pin.
I2C1 data input/output pin.
I/O
I
11 15
4
5
6
4
4
5
5
UART1 data receiver input pin.
I/O
I/O
MFP11 PWM0 channel 3 output/capture input.
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 3 input pin.
INT3
PB.1
I
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH1
UART2_TXD
I2C1_SCL
A
MFP1
MFP7
MFP9
ADC0 channel 1 analog input.
UART2 data transmitter output pin.
I2C1 clock pin.
O
16
5
5
6
6
I/O
I/O
I/O
PWM0_CH4
PWM1_CH4
MFP11 PWM0 channel 4 output/capture input.
MFP12 PWM1 channel 4 output/capture input.
MFP13 PWM0 Brake 0 input pin.
PWM0_BRAKE0
PB.0
I
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH0
UART2_RXD
SPI0_I2SMCLK
I2C1_SDA
A
MFP1
MFP7
MFP8
MFP9
ADC0 channel 0 analog input.
UART2 data receiver input pin.
SPI0 I2S master clock output pin
I2C1 data input/output pin.
I
I/O
I/O
I/O
I/O
17
6
6
7
7
PWM0_CH5
PWM1_CH5
MFP11 PWM0 channel 5 output/capture input.
MFP12 PWM1 channel 5 output/capture input.
MFP13 PWM0 Brake 1 input pin.
PWM0_BRAKE1
PA.11
I
I/O
MFP0
MFP1
General purpose digital I/O pin.
7
7
8
8
ACMP0_P0
A
Analog comparator 0 positive input 0 pin.
Feb 25, 2019
Page 46 of 274
Rev. 1.01
M031/M032
20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
EBI_nRD
O
MFP2
MFP6
EBI read enable output pin.
USCI0 clock pin.
USCI0_CLK
I/O
TM0_EXT
PA.10
I/O
I/O
MFP13 Timer0 external capture input/toggle output pin.
MFP0
General purpose digital I/O pin.
ACMP1_P0
EBI_nWR
A
O
MFP1
MFP2
MFP6
Analog comparator 1 positive input 0 pin.
EBI write enable output pin.
USCI0 data 0 pin.
8
8
9
9
USCI0_DAT0
I/O
TM1_EXT
PA.9
I/O
I/O
MFP13 Timer1 external capture input/toggle output pin.
MFP0
General purpose digital I/O pin.
EBI_MCLK
O
I/O
O
MFP2
MFP6
MFP7
EBI external clock output pin.
USCI0 data 1 pin.
9
9
10 10
USCI0_DAT1
UART1_TXD
UART1 data transmitter output pin.
TM2_EXT
PA.8
I/O
I/O
MFP13 Timer2 external capture input/toggle output pin.
MFP0
General purpose digital I/O pin.
EBI_ALE
O
I/O
I
MFP2
MFP6
MFP7
EBI address latch enable output pin.
USCI0 control 1 pin.
USCI0_CTL1
UART1_RXD
TM3_EXT
10 10 11 11
UART1 data receiver input pin.
I/O
MFP13 Timer3 external capture input/toggle output pin.
MFP15 External interrupt 4 input pin.
INT4
PF.6
I
I/O
MFP0
General purpose digital I/O pin.
EBI_ADR19
SPI0_MOSI
O
MFP2
MFP5
EBI address bus bit 19.
12 12
I/O
SPI0 MOSI (Master Out, Slave In) pin.
EBI_nCS0
PF.14
O
MFP7
MFP0
EBI chip select 0 output pin.
I/O
General purpose digital I/O pin.
PWM1_BRAKE0
PWM0_BRAKE0
PWM0_CH4
CLKO
I
MFP9
PWM1 Brake 0 input pin.
I
MFP10 PWM0 Brake 0 input pin.
13 13
I/O
O
MFP12 PWM0 channel 4 output/capture input.
MFP13 Clock Out
TM3
I/O
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 5 input pin.
INT5
PF.5
I
I/O
MFP0
MFP2
General purpose digital I/O pin.
UART2 data receiver input pin.
7
11 11 14 14
UART2_RXD
I
Feb 25, 2019
Page 47 of 274
Rev. 1.01
M031/M032
20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
UART2_nCTS
PWM0_CH0
X32_IN
I
I/O
I
MFP4
MFP7
UART2 clear to Send input pin.
PWM0 channel 0 output/capture input.
MFP10 External 32.768 kHz crystal input pin.
MFP11 ADC0 external trigger input.
ADC0_ST
PF.4
I
I/O
MFP0
General purpose digital I/O pin.
UART2_TXD
UART2_nRTS
PWM0_CH1
O
O
MFP2
MFP4
MFP7
UART2 data transmitter output pin.
UART2 request to Send output pin.
PWM0 channel 1 output/capture input.
8
12 12 15 15
I/O
X32_OUT
PF.3
O
MFP10 External 32.768 kHz crystal output pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_nCS0
UART0_TXD
I2C0_SCL
O
O
MFP2
MFP3
MFP4
EBI chip select 0 output pin.
UART0 data transmitter output pin.
I2C0 clock pin.
12 18
9
13 13 16 16
I/O
External 4~32 MHz (high speed) crystal input
pin.
XT1_IN
PF.2
I
MFP10
MFP0
I/O
General purpose digital I/O pin.
EBI_nCS1
UART0_RXD
I2C0_SDA
O
I
MFP2
MFP3
MFP4
EBI chip select 1 output pin.
UART0 data receiver input pin.
I2C0 data input/output pin.
13 19 10 14 14 17 17
I/O
External 4~32 MHz (high speed) crystal output
pin.
XT1_OUT
PC.7
O
MFP10
MFP0
I/O
General purpose digital I/O pin.
EBI_AD9
UART0_nCTS
PWM1_CH2
TM0
I/O
I
MFP2
MFP7
EBI address/data bus bit 9.
UART0 clear to Send input pin.
18 18
I/O
I/O
MFP11 PWM1 channel 2 output/capture input.
MFP14 Timer0 event counter input/toggle output pin.
MFP15 External interrupt 3 input pin.
INT3
PC.6
I
I/O
MFP0
General purpose digital I/O pin.
EBI_AD8
UART0_nRTS
PWM1_CH3
TM1
I/O
O
MFP2
MFP7
EBI address/data bus bit 8.
UART0 request to Send output pin.
19 19
I/O
I/O
I
MFP11 PWM1 channel 3 output/capture input.
MFP14 Timer1 event counter input/toggle output pin.
MFP15 External interrupt 2 input pin.
INT2
Feb 25, 2019
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Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
PA.7
I/O
MFP0
General purpose digital I/O pin.
EBI_AD7
I/O
O
MFP2
MFP7
MFP8
EBI address/data bus bit 7.
UART0 data transmitter output pin.
I2C1 clock pin.
UART0_TXD
I2C1_SCL
PWM1_CH4
ACMP0_WLAT
TM2
I/O
I/O
I
15 15 20 20
MFP11 PWM1 channel 4 output/capture input.
MFP13 Analog comparator 0 window latch input pin
MFP14 Timer2 event counter input/toggle output pin.
MFP15 External interrupt 1 input pin.
I/O
INT1
PA.6
I
I/O
MFP0
General purpose digital I/O pin.
EBI_AD6
UART0_RXD
I2C1_SDA
PWM1_CH5
ACMP1_WLAT
TM3
I/O
I
MFP2
MFP7
MFP8
EBI address/data bus bit 6.
UART0 data receiver input pin.
I2C1 data input/output pin.
I/O
I/O
I
16 16 21 21
MFP11 PWM1 channel 5 output/capture input.
MFP13 Analog comparator 1 window latch input pin
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 0 input pin.
I/O
INT0
I
22 22 VSS
23 23 VDD
PD.15
P
MFP0
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
P
I/O
General purpose digital I/O pin.
PWM0_CH5
TM3
I/O
I/O
MFP12 PWM0 channel 5 output/capture input.
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 1 input pin.
24 24
17 17 25 25
18 18 26 26
INT1
PA.5
I
I/O
MFP0
General purpose digital I/O pin.
UART0_nCTS
UART0_TXD
I2C0_SCL
I
MFP7
MFP8
MFP9
UART0 clear to Send input pin.
UART0 data transmitter output pin.
I2C0 clock pin.
O
I/O
PWM0_CH0
PA.4
I/O
I/O
MFP13 PWM0 channel 0 output/capture input.
MFP0
General purpose digital I/O pin.
SPI0_I2SMCLK
UART0_nRTS
UART0_RXD
I/O
O
I
MFP4
MFP7
MFP8
SPI0 I2S master clock output pin
UART0 request to Send output pin.
UART0 data receiver input pin.
Feb 25, 2019
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20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
I2C0_SDA
I/O
MFP9
I2C0 data input/output pin.
PWM0_CH1
PA.3
I/O
I/O
MFP13 PWM0 channel 1 output/capture input.
MFP0
General purpose digital I/O pin.
SPI0_SS
I/O
O
MFP4
MFP8
MFP9
SPI0 slave select pin.
UART1_TXD
I2C1_SCL
PWM0_CH2
CLKO
UART1 data transmitter output pin.
I2C1 clock pin.
14 20 11 19 19 27 27
I/O
I/O
O
MFP13 PWM0 channel 2 output/capture input.
MFP14 Clock Out
PWM1_BRAKE1
PA.2
I
MFP15 PWM1 Brake 1 input pin.
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
UART1_RXD
I2C1_SDA
I/O
I
MFP4
MFP8
MFP9
SPI0 serial clock pin.
15 21 12 20 20 28 28
16 22 13 21 21 29 29
17 23 14 22 22 30 30
UART1 data receiver input pin.
I2C1 data input/output pin.
I/O
PWM0_CH3
PA.1
I/O
I/O
MFP13 PWM0 channel 3 output/capture input.
MFP0
General purpose digital I/O pin.
SPI0_MISO
I/O
O
I
MFP4
MFP7
MFP8
SPI0 MISO (Master In, Slave Out) pin.
UART0 data transmitter output pin.
UART1 clear to Send input pin.
UART0_TXD
UART1_nCTS
PWM0_CH4
PA.0
I/O
I/O
MFP13 PWM0 channel 4 output/capture input.
MFP0
General purpose digital I/O pin.
SPI0_MOSI
I/O
I
MFP4
MFP7
MFP8
SPI0 MOSI (Master Out, Slave In) pin.
UART0 data receiver input pin.
UART0_RXD
UART1_nRTS
O
UART1 request to Send output pin.
PWM0_CH5
PF.15
I/O
I/O
MFP13 PWM0 channel 5 output/capture input.
MFP0 General purpose digital I/O pin.
PWM0_BRAKE0
PWM0_CH1
TM2
I
MFP11 PWM0 Brake 0 input pin.
I/O
I/O
O
MFP12 PWM0 channel 1 output/capture input.
MFP13 Timer2 event counter input/toggle output pin.
MFP14 Clock Out
15 23 23 31 31
CLKO
INT4
I
MFP15 External interrupt 4 input pin.
External reset input: active LOW, with an internal
MFP0
18 24 16 24 24 32 32 nRESET
I
pull-up. Set this pin low reset to initial state.
Feb 25, 2019
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M031/M032
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Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
PF.0
I/O
MFP0
General purpose digital I/O pin.
UART1_TXD
I2C1_SCL
O
I/O
O
MFP2
MFP3
MFP4
UART1 data transmitter output pin.
I2C1 clock pin.
19 25 17 25 25 33 33
20 26 18 26 26 34 34
27 27 35 35
UART0_TXD
UART0 data transmitter output pin.
ICE_DAT
PF.1
O
MFP14 Serial wired debugger data pin.
I/O
MFP0
General purpose digital I/O pin.
UART1_RXD
I2C1_SDA
I
I/O
I
MFP2
MFP3
MFP4
UART1 data receiver input pin.
I2C1 data input/output pin.
UART0_RXD
UART0 data receiver input pin.
ICE_CLK
PC.5
I
MFP14 Serial wired debugger clock pin.
I/O
MFP0
General purpose digital I/O pin.
EBI_AD5
I/O
O
MFP2
MFP8
MFP9
EBI address/data bus bit 5.
UART2 data transmitter output pin.
I2C1 clock pin.
UART2_TXD
I2C1_SCL
I/O
PWM1_CH0
PC.4
I/O
I/O
MFP12 PWM1 channel 0 output/capture input.
MFP0
General purpose digital I/O pin.
EBI_AD4
I/O
I
MFP2
MFP8
MFP9
EBI address/data bus bit 4.
UART2 data receiver input pin.
I2C1 data input/output pin.
28 28 36 36
UART2_RXD
I2C1_SDA
I/O
PWM1_CH1
PC.3
I/O
I/O
MFP12 PWM1 channel 1 output/capture input.
MFP0
General purpose digital I/O pin.
EBI_AD3
I/O
O
MFP2
MFP8
EBI address/data bus bit 3.
29 29 37 37
UART2_nRTS
UART2 request to Send output pin.
PWM1_CH2
PC.2
I/O
I/O
MFP12 PWM1 channel 2 output/capture input.
MFP0
General purpose digital I/O pin.
EBI_AD2
I/O
I
MFP2
MFP8
EBI address/data bus bit 2.
30 30 38 38
UART2_nCTS
UART2 clear to Send input pin.
PWM1_CH3
PC.1
I/O
I/O
MFP12 PWM1 channel 3 output/capture input.
MFP0
General purpose digital I/O pin.
EBI_AD1
I/O
O
MFP2
MFP8
MFP9
EBI address/data bus bit 1.
UART2 data transmitter output pin.
I2C0 clock pin.
27 19 31 31 39 39
UART2_TXD
I2C0_SCL
I/O
Feb 25, 2019
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Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
PWM1_CH4
I/O
MFP12 PWM1 channel 4 output/capture input.
MFP14 Analog comparator 0 output pin.
ACMP0_O
PC.0
O
I/O
MFP0
General purpose digital I/O pin.
EBI_AD0
I/O
I
MFP2
MFP8
MFP9
EBI address/data bus bit 0.
UART2 data receiver input pin.
I2C0 data input/output pin.
UART2_RXD
I2C0_SDA
PWM1_CH5
28 20 32 32 40 40
I/O
I/O
MFP12 PWM1 channel 5 output/capture input.
MFP14 Analog comparator 1 output pin.
ACMP1_O
PD.3
O
I/O
MFP0
General purpose digital I/O pin.
EBI_AD10
USCI0_CTL1
SPI0_SS
I/O
I/O
I/O
MFP2
MFP3
MFP4
EBI address/data bus bit 10.
USCI0 control 1 pin.
41 41
SPI0 slave select pin.
UART0_TXD
PD.2
O
MFP9
MFP0
UART0 data transmitter output pin.
General purpose digital I/O pin.
I/O
EBI_AD11
USCI0_DAT1
SPI0_CLK
I/O
I/O
I/O
MFP2
MFP3
MFP4
EBI address/data bus bit 11.
USCI0 data 1 pin.
42 42
43 43
44 44
SPI0 serial clock pin.
UART0_RXD
PD.1
I
MFP9
MFP0
UART0 data receiver input pin.
General purpose digital I/O pin.
I/O
EBI_AD12
I/O
I/O
MFP2
MFP3
EBI address/data bus bit 12.
USCI0 data 0 pin.
USCI0_DAT0
SPI0_MISO
PD.0
I/O
I/O
MFP4
MFP0
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
EBI_AD13
USCI0_CLK
SPI0_MOSI
I/O
I/O
I/O
MFP2
MFP3
MFP4
EBI address/data bus bit 13.
USCI0 clock pin.
SPI0 MOSI (Master Out, Slave In) pin.
TM2
I/O
I/O
MFP14 Timer2 event counter input/toggle output pin.
PA.12
MFP0
MFP4
MFP0
MFP4
MFP0
General purpose digital I/O pin.
I2C1 clock pin.
1
21 33
45
I2C1_SCL
PA.13
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
I2C1 data input/output pin.
General purpose digital I/O pin.
2
3
22 34
23 35
46
47
I2C1_SDA
PA.14
Feb 25, 2019
Page 52 of 274
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Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
UART0_TXD
PA.15
O
I/O
I
MFP3
MFP0
MFP3
MFP0
MFP0
MFP0
UART0 data transmitter output pin.
General purpose digital I/O pin.
UART0 data receiver input pin.
Power supply from USB host or HUB.
USB differential signal D-.
4
24 36
48
UART0_RXD
45 USB_VBUS
46 USB_D-
47 USB_D+
33
34
35
P
A
A
USB differential signal D+.
Internal power regulator output 3.3V decoupling
pin.
36
48 USB_VDD33_CAP
A
MFP0
1
2
5
6
25 37 37 49 49 VSS
P
A
MFP0
MFP0
Ground pin for digital circuit.
LDO output pin.
26 38 38 50 50 LDO_CAP
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
3
7
27 39 39 51 51 VDD
PC.14
P
MFP0
MFP0
I/O
General purpose digital I/O pin.
EBI_AD11
I/O
I/O
I/O
MFP2
MFP4
MFP5
EBI address/data bus bit 11.
SPI0 I2S master clock output pin
USCI0 control 0 pin.
40 40 52 52
SPI0_I2SMCLK
USCI0_CTL0
TM1
I/O
I/O
MFP13 Timer1 event counter input/toggle output pin.
PB.15
MFP0
General purpose digital I/O pin.
ADC0_CH15
EBI_AD12
A
MFP1
MFP2
MFP4
MFP5
MFP6
ADC0 channel 15 analog input.
EBI address/data bus bit 12.
SPI0 slave select pin.
I/O
I/O
I/O
I
SPI0_SS
28 41 41 53 53
USCI0_CTL1
UART0_nCTS
PWM1_CH0
TM0_EXT
USCI0 control 1 pin.
UART0 clear to Send input pin.
I/O
I/O
MFP11 PWM1 channel 0 output/capture input.
MFP13 Timer0 external capture input/toggle output pin.
MFP15 PWM0 Brake 1 input pin.
PWM0_BRAKE1
PB.14
I
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH14
EBI_AD13
A
MFP1
MFP2
MFP4
MFP5
MFP6
ADC0 channel 14 analog input.
EBI address/data bus bit 13.
SPI0 serial clock pin.
I/O
I/O
I/O
O
4
8
29 42 42 54 54
SPI0_CLK
USCI0_DAT1
UART0_nRTS
PWM1_CH1
USCI0 data 1 pin.
UART0 request to Send output pin.
I/O
MFP11 PWM1 channel 1 output/capture input.
Feb 25, 2019
Page 53 of 274
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Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
TM1_EXT
I/O
MFP13 Timer1 external capture input/toggle output pin.
MFP14 Clock Out
CLKO
PB.13
O
I/O
MFP0
General purpose digital I/O pin.
ADC0_CH13
ACMP0_P3
ACMP1_P3
EBI_AD14
A
A
MFP1
MFP1
MFP1
MFP2
MFP4
MFP5
MFP6
ADC0 channel 13 analog input.
Analog comparator 0 positive input 3 pin.
Analog comparator 1 positive input 3 pin.
EBI address/data bus bit 14.
A
I/O
I/O
I/O
O
5
9
30 43 43 55 55
SPI0_MISO
USCI0_DAT0
UART0_TXD
PWM1_CH2
SPI0 MISO (Master In, Slave Out) pin.
USCI0 data 0 pin.
UART0 data transmitter output pin.
I/O
MFP11 PWM1 channel 2 output/capture input.
TM2_EXT
PB.12
I/O
I/O
MFP13 Timer2 external capture input/toggle output pin.
MFP0
General purpose digital I/O pin.
ADC0_CH12
ACMP0_P2
ACMP1_P2
EBI_AD15
A
A
MFP1
MFP1
MFP1
MFP2
MFP4
MFP5
MFP6
ADC0 channel 12 analog input.
Analog comparator 0 positive input 2 pin.
Analog comparator 1 positive input 2 pin.
EBI address/data bus bit 15.
A
I/O
I/O
I/O
I
6
10 31 44 44 56 56
SPI0_MOSI
USCI0_CLK
UART0_RXD
PWM1_CH3
TM3_EXT
SPI0 MOSI (Master Out, Slave In) pin.
USCI0 clock pin.
UART0 data receiver input pin.
I/O
MFP11 PWM1 channel 3 output/capture input.
I/O
P
MFP13 Timer3 external capture input/toggle output pin.
7
11 32 45 45 57 57 AVDD
MFP0
MFP0
MFP0
Power supply for internal analog circuit.
ADC reference voltage input.
58 58 VREF
A
P
Note: This pin needs to be connected with a 1uF
capacitor.
46 46 59 59 AVSS
PB.11
Ground pin for analog circuit.
I/O
A
MFP0
MFP1
MFP2
MFP5
MFP7
General purpose digital I/O pin.
ADC0 channel 11 analog input.
EBI address bus bit 16.
ADC0_CH11
60 60
EBI_ADR16
UART0_nCTS
I2C1_SCL
O
I
UART0 clear to Send input pin.
I2C1 clock pin.
I/O
Feb 25, 2019
Page 54 of 274
Rev. 1.01
M031/M032
20 28 32 48
Pin Pin Pin Pin
64
Pin
Pin Name
Type
MFP
Description
SPI0_I2SMCLK
I/O
MFP9
SPI0 I2S master clock output pin
PB.10
I/O
A
MFP0
MFP1
MFP2
General purpose digital I/O pin.
ADC0 channel 10 analog input.
EBI address bus bit 17.
ADC0_CH10
EBI_ADR17
61 61
O
UART0_nRTS
I2C1_SDA
O
MFP5
MFP7
UART0 request to Send output pin.
I2C1 data input/output pin.
I/O
PB.9
I/O
A
MFP0
MFP1
MFP2
General purpose digital I/O pin.
ADC0 channel 9 analog input.
EBI address bus bit 18.
ADC0_CH9
EBI_ADR18
62 62
O
UART0_TXD
UART1_nCTS
O
I
MFP5
MFP6
UART0 data transmitter output pin.
UART1 clear to Send input pin.
PB.8
I/O
A
MFP0
MFP1
MFP2
General purpose digital I/O pin.
ADC0 channel 8 analog input.
EBI address bus bit 19.
ADC0_CH8
EBI_ADR19
63 63
O
UART0_RXD
UART1_nRTS
I
MFP5
MFP6
UART0 data receiver input pin.
O
UART1 request to Send output pin.
PB.7
I/O
A
MFP0
MFP1
MFP2
MFP6
MFP8
General purpose digital I/O pin.
ADC0 channel 7 analog input.
EBI low byte write enable output pin.
UART1 data transmitter output pin.
EBI chip select 0 output pin.
ADC0_CH7
EBI_nWRL
UART1_TXD
EBI_nCS0
PWM1_BRAKE0
PWM1_CH4
INT5
O
O
O
I
47 47 64 64
MFP11 PWM1 Brake 0 input pin.
I/O
I
MFP12 PWM1 channel 4 output/capture input.
MFP13 External interrupt 5 input pin.
Feb 25, 2019
Page 55 of 274
Rev. 1.01
M031/M032
4.2.2 M031/M032 Series Multi-function Summary Table
Group
Pin Name
GPIO
PB.3
PC.1
PB.7
PA.11
PB.2
PB.12
PB.13
PA.7
PB.5
PC.0
PB.6
PA.10
PB.4
PB.12
PB.13
PA.6
PF.14
PA.3
PF.15
PB.14
PB.0
PB.1
PB.2
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
PB.10
PB.11
PB.12
MFP
MFP1
MFP14
MFP15
MFP1
MFP1
MFP1
MFP1
MFP13
MFP1
MFP14
MFP15
MFP1
MFP1
MFP1
MFP1
MFP13
MFP13
MFP14
MFP14
MFP14
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
Type
A
O
O
A
A
A
A
I
Description
ACMP0_N
Analog comparator 0 negative input pin.
Analog comparator 0 output pin.
ACMP0_O
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
ACMP0
A
O
O
A
A
A
A
I
ACMP1_O
Analog comparator 1 output pin.
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
ACMP1
O
O
O
O
A
A
A
A
A
A
A
A
A
A
A
A
A
CLKO
CLKO
Clock Out
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
ADC0_CH12
ADC0 channel 0 analog input.
ADC0 channel 1 analog input.
ADC0 channel 2 analog input.
ADC0 channel 3 analog input.
ADC0 channel 4 analog input.
ADC0 channel 5 analog input.
ADC0 channel 6 analog input.
ADC0 channel 7 analog input.
ADC0 channel 8 analog input.
ADC0 channel 9 analog input.
ADC0 channel 10 analog input.
ADC0 channel 11 analog input.
ADC0 channel 12 analog input.
ADC0
Feb 25, 2019
Page 56 of 274
Rev. 1.01
M031/M032
Group
Pin Name
ADC0_CH13
ADC0_CH14
ADC0_CH15
ADC0_ST
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
EBI_AD10
GPIO
PB.13
PB.14
PB.15
PF.5
MFP
MFP1
MFP1
MFP1
MFP11
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP7
MFP2
MFP8
MFP2
Type
A
Description
ADC0 channel 13 analog input.
ADC0 channel 14 analog input.
ADC0 channel 15 analog input.
ADC0 external trigger input.
EBI address/data bus bit 0.
EBI address/data bus bit 1.
EBI address/data bus bit 2.
EBI address/data bus bit 3.
EBI address/data bus bit 4.
EBI address/data bus bit 5.
EBI address/data bus bit 6.
EBI address/data bus bit 7.
EBI address/data bus bit 8.
EBI address/data bus bit 9.
EBI address/data bus bit 10.
A
A
I
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PA.6
PA.7
PC.6
PC.7
PD.3
PD.2
PC.14
PD.1
PB.15
PD.0
PB.14
PB.13
PB.12
PB.11
PB.10
PB.9
PF.6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
EBI_AD11
EBI_AD12
EBI_AD13
EBI address/data bus bit 11.
EBI address/data bus bit 12.
EBI address/data bus bit 13.
EBI
EBI_AD14
EBI_AD15
EBI_ADR16
EBI_ADR17
EBI_ADR18
EBI address/data bus bit 14.
EBI address/data bus bit 15.
EBI address bus bit 16.
EBI address bus bit 17.
EBI address bus bit 18.
O
O
O
EBI_ADR19
EBI address bus bit 19.
PB.8
PA.8
PA.9
PF.6
O
EBI_ALE
O
EBI address latch enable output pin.
EBI external clock output pin.
EBI_MCLK
O
O
EBI_nCS0
EBI_nCS1
PF.3
O
EBI chip select 0 output pin.
EBI chip select 1 output pin.
PB.7
PF.2
O
O
Feb 25, 2019
Page 57 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PB.6
PA.11
PA.10
PB.6
PB.7
PB.5
PF.3
PA.5
PC.1
PB.4
PF.2
PA.4
PC.0
PB.3
PB.1
PA.7
PA.3
PF.0
PC.5
PA.12
PB.11
PB.2
PB.0
PA.6
PA.2
PF.1
PC.4
PA.13
PB.10
PF.1
PF.0
PB.5
PA.6
PB.4
MFP
MFP8
MFP2
MFP2
MFP2
MFP2
MFP6
MFP4
MFP9
MFP9
MFP6
MFP4
MFP9
MFP9
MFP4
MFP9
MFP8
MFP9
MFP3
MFP9
MFP4
MFP7
MFP4
MFP9
MFP8
MFP9
MFP3
MFP9
MFP4
MFP7
MFP14
MFP14
MFP15
MFP15
MFP15
Type
O
Description
EBI_nRD
O
EBI read enable output pin.
EBI write enable output pin.
EBI_nWR
EBI_nWRH
EBI_nWRL
O
O
EBI high byte write enable output pin
EBI low byte write enable output pin.
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I2C0_SCL
I2C0_SDA
I2C0 clock pin.
I2C0
I2C0 data input/output pin.
I2C1_SCL
I2C1 clock pin.
I2C1
I2C1_SDA
I2C1 data input/output pin.
ICE_CLK
ICE_DAT
Serial wired debugger clock pin.
Serial wired debugger data pin.
ICE
O
I
INT0
INT1
INT0
INT1
External interrupt 0 input pin.
External interrupt 1 input pin.
I
I
Feb 25, 2019
Page 58 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PA.7
PD.15
PB.3
PC.6
PB.2
PC.7
PA.8
PF.15
PB.6
PF.14
PB.7
PB.3
PB.1
PF.14
PF.15
PB.0
PB.15
PB.5
PF.5
PA.5
PB.4
PF.4
PA.4
PF.15
PB.3
PA.3
PB.2
PA.2
PB.1
PF.14
PA.1
PB.0
PD.15
PA.0
MFP
Type
Description
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP13
MFP15
MFP13
MFP13
MFP13
MFP10
MFP11
MFP13
MFP15
MFP11
MFP7
I
I
I
INT2
INT3
INT2
INT3
External interrupt 2 input pin.
External interrupt 3 input pin.
I
I
I
I
INT4
INT5
INT4
INT5
I
External interrupt 4 input pin.
External interrupt 5 input pin.
I
I
I
I
I
PWM0_BRAKE0
PWM0 Brake 0 input pin.
I
I
I
PWM0_BRAKE1
PWM0_CH0
PWM0 Brake 1 input pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM0 channel 0 output/capture input.
MFP13
MFP11
MFP7
PWM0_CH1
PWM0 channel 1 output/capture input.
PWM0
MFP13
MFP12
MFP11
MFP13
MFP11
MFP13
MFP11
MFP12
MFP13
MFP11
MFP12
MFP13
PWM0_CH2
PWM0_CH3
PWM0 channel 2 output/capture input.
PWM0 channel 3 output/capture input.
PWM0_CH4
PWM0_CH5
PWM0 channel 4 output/capture input.
PWM0 channel 5 output/capture input.
Feb 25, 2019
Page 59 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PF.14
PB.7
PA.3
PB.6
PC.5
PB.15
PC.4
PB.14
PC.7
PC.3
PB.13
PC.6
PC.2
PB.12
PB.1
PA.7
PC.1
PB.7
PB.0
PA.6
PC.0
PB.6
PA.2
PD.2
PB.14
PB.0
PA.4
PC.14
PB.11
PA.1
PD.1
PB.13
PF.6
MFP
Type
I
Description
MFP9
PWM1_BRAKE0
PWM1 Brake 0 input pin.
MFP11
MFP15
MFP11
MFP12
MFP11
MFP12
MFP11
MFP11
MFP12
MFP11
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP12
MFP12
MFP11
MFP12
MFP12
MFP4
I
I
PWM1_BRAKE1
PWM1_CH0
PWM1 Brake 1 input pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM1 channel 0 output/capture input.
PWM1 channel 1 output/capture input.
PWM1_CH1
PWM1_CH2
PWM1_CH3
PWM1 channel 2 output/capture input.
PWM1 channel 3 output/capture input.
PWM1
PWM1_CH4
PWM1 channel 4 output/capture input.
PWM1_CH5
SPI0_CLK
PWM1 channel 5 output/capture input.
MFP4
SPI0 serial clock pin.
MFP4
MFP8
MFP4
SPI0_I2SMCLK
SPI0 I2S master clock output pin
MFP4
SPI0
MFP9
MFP4
SPI0_MISO
SPI0_MOSI
MFP4
SPI0 MISO (Master In, Slave Out) pin.
SPI0 MOSI (Master Out, Slave In) pin.
MFP4
MFP5
PA.0
MFP4
Feb 25, 2019
Page 60 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PD.0
PB.12
PA.3
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
MFP4
MFP4
MFP4
SPI0_SS
PD.3
PB.15
PB.5
MFP4
SPI0 slave select pin.
MFP4
MFP14
MFP14
MFP13
MFP13
MFP14
MFP14
MFP13
MFP13
MFP13
MFP14
MFP14
MFP13
MFP14
MFP13
MFP13
MFP14
MFP14
MFP14
MFP14
MFP13
MFP13
MFP3
TM0
Timer0 event counter input/toggle output pin.
PC.7
PA.11
PB.15
PB.4
TM0
Timer0 external capture input/toggle output
pin.
TM0_EXT
TM1
PC.6
PC.14
PA.10
PB.14
PB.3
Timer1 event counter input/toggle output pin.
TM1
Timer1 external capture input/toggle output
pin.
TM1_EXT
PA.7
TM2
Timer2 event counter input/toggle output pin.
PF.15
PD.0
PA.9
TM2
Timer2 external capture input/toggle output
pin.
TM2_EXT
TM3
PB.13
PB.2
PF.14
PA.6
Timer3 event counter input/toggle output pin.
TM3
PD.15
PA.8
Timer3 external capture input/toggle output
pin.
TM3_EXT
PB.12
PF.2
PA.6
MFP7
I
PA.4
MFP8
I
PA.0
MFP7
I
UART0
UART0_RXD
UART0 data receiver input pin.
PF.1
MFP4
I
PD.2
PA.15
PB.12
MFP9
I
MFP3
I
MFP6
I
Feb 25, 2019
Page 61 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PB.8
PF.3
PA.7
PA.5
PA.1
PF.0
PD.3
PA.14
PB.13
PB.9
PC.7
PA.5
PB.15
PB.11
PC.6
PA.4
PB.14
PB.10
PB.2
PA.8
PA.2
PF.1
PB.6
PB.3
PA.9
PA.3
PF.0
PB.7
PA.1
PB.9
PA.0
PB.8
PB.4
PB.0
MFP
MFP5
MFP3
MFP7
MFP8
MFP7
MFP4
MFP9
MFP3
MFP6
MFP5
MFP7
MFP7
MFP6
MFP5
MFP7
MFP7
MFP6
MFP5
MFP6
MFP7
MFP8
MFP2
MFP6
MFP6
MFP7
MFP8
MFP2
MFP6
MFP8
MFP6
MFP8
MFP6
MFP13
MFP7
Type
I
Description
O
O
O
O
O
O
O
O
O
I
UART0_TXD
UART0 data transmitter output pin.
I
UART0_nCTS
UART0_nRTS
UART0 clear to Send input pin.
I
I
O
O
O
O
I
UART0 request to Send output pin.
I
UART1_RXD
I
UART1 data receiver input pin.
I
I
O
O
O
O
O
I
UART1
UART1_TXD
UART1 data transmitter output pin.
UART1_nCTS
UART1_nRTS
UART2_RXD
UART1 clear to Send input pin.
UART1 request to Send output pin.
UART2 data receiver input pin.
I
O
O
I
UART2
I
Feb 25, 2019
Page 62 of 274
Rev. 1.01
M031/M032
Group
Pin Name
GPIO
PF.5
PC.4
PC.0
PB.5
PB.1
PF.4
PC.5
PC.1
PF.5
PC.2
PF.4
PC.3
PA.11
PD.0
PB.12
PC.14
PA.8
PD.3
PB.15
PA.10
PD.1
PB.13
PA.9
PD.2
PB.14
PF.5
PF.4
MFP
MFP2
MFP8
MFP8
MFP13
MFP7
MFP2
MFP8
MFP8
MFP4
MFP8
MFP4
MFP8
MFP6
MFP3
MFP5
MFP5
MFP6
MFP3
MFP5
MFP6
MFP3
MFP5
MFP6
MFP3
MFP5
MFP10
MFP10
Type
I
Description
I
I
O
O
UART2_TXD
O
UART2 data transmitter output pin.
O
O
I
UART2_nCTS
UART2_nRTS
UART2 clear to Send input pin.
I
O
UART2 request to Send output pin.
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
USCI0_CLK
USCI0_CTL0
USCI0_CTL1
USCI0 clock pin.
USCI0 control 0 pin.
USCI0 control 1 pin.
USCI0
USCI0_DAT0
USCI0_DAT1
USCI0 data 0 pin.
USCI0 data 1 pin.
X32_IN
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
X32
XT1
X32_OUT
O
External 4~32 MHz (high speed) crystal input
pin.
XT1_IN
PF.3
PF.2
MFP10
MFP10
I
External 4~32 MHz (high speed) crystal output
pin.
XT1_OUT
O
Feb 25, 2019
Page 63 of 274
Rev. 1.01
M031/M032
4.2.3 M031/M032 Series Multi-function Summary Table Sorted by GPIO
Pin Name
PA.0
Type
I/O
I/O
I
MFP
MFP0
MFP4
MFP7
MFP8
MFP13
MFP0
MFP4
MFP7
MFP8
MFP13
MFP0
MFP4
MFP8
MFP9
MFP13
MFP0
MFP4
MFP8
MFP9
MFP13
MFP14
MFP15
MFP0
MFP4
MFP7
MFP8
MFP9
MFP13
MFP0
MFP7
MFP8
MFP9
MFP13
Description
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
UART0 data receiver input pin.
UART1 request to Send output pin.
PWM0 channel 5 output/capture input.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
UART0 data transmitter output pin.
UART1 clear to Send input pin.
PWM0 channel 4 output/capture input.
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_MOSI
PA.0 UART0_RXD
UART1_nRTS
PWM0_CH5
PA.1
O
I/O
I/O
I/O
O
SPI0_MISO
PA.1 UART0_TXD
UART1_nCTS
PWM0_CH4
PA.2
I
I/O
I/O
I/O
I
SPI0_CLK
PA.2 UART1_RXD
I2C1_SDA
UART1 data receiver input pin.
I2C1 data input/output pin.
I/O
I/O
I/O
I/O
O
PWM0_CH3
PA.3
PWM0 channel 3 output/capture input.
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
UART1_TXD
PA.3 I2C1_SCL
PWM0_CH2
CLKO
UART1 data transmitter output pin.
I2C1 clock pin.
I/O
I/O
O
PWM0 channel 2 output/capture input.
Clock Out
PWM1_BRAKE1
PA.4
I
PWM1 Brake 1 input pin.
I/O
I/O
O
General purpose digital I/O pin.
SPI0 I2S master clock output pin
UART0 request to Send output pin.
UART0 data receiver input pin.
I2C0 data input/output pin.
SPI0_I2SMCLK
UART0_nRTS
PA.4
UART0_RXD
I
I2C0_SDA
PWM0_CH1
PA.5
I/O
I/O
I/O
I
PWM0 channel 1 output/capture input.
General purpose digital I/O pin.
UART0 clear to Send input pin.
UART0 data transmitter output pin.
I2C0 clock pin.
UART0_nCTS
PA.5 UART0_TXD
I2C0_SCL
O
I/O
I/O
PWM0_CH0
PWM0 channel 0 output/capture input.
Feb 25, 2019
Page 64 of 274
Rev. 1.01
M031/M032
Pin Name
PA.6
Type
I/O
I/O
I
MFP
MFP0
MFP2
MFP7
MFP8
MFP11
MFP13
MFP14
MFP15
MFP0
MFP2
MFP7
MFP8
MFP11
MFP13
MFP14
MFP15
MFP0
MFP2
MFP6
MFP7
MFP13
MFP15
MFP0
MFP2
MFP6
MFP7
MFP13
MFP0
MFP1
MFP2
MFP6
MFP13
MFP0
MFP1
Description
General purpose digital I/O pin.
EBI address/data bus bit 6.
UART0 data receiver input pin.
I2C1 data input/output pin.
PWM1 channel 5 output/capture input.
EBI_AD6
UART0_RXD
I2C1_SDA
PWM1_CH5
ACMP1_WLAT
TM3
I/O
I/O
I
PA.6
Analog comparator 1 window latch input pin
Timer3 event counter input/toggle output pin.
External interrupt 0 input pin.
I/O
I
INT0
PA.7
I/O
I/O
O
General purpose digital I/O pin.
EBI address/data bus bit 7.
EBI_AD7
UART0_TXD
I2C1_SCL
PWM1_CH4
ACMP0_WLAT
TM2
UART0 data transmitter output pin.
I2C1 clock pin.
I/O
I/O
I
PA.7
PWM1 channel 4 output/capture input.
Analog comparator 0 window latch input pin
Timer2 event counter input/toggle output pin.
External interrupt 1 input pin.
I/O
I
INT1
PA.8
I/O
O
General purpose digital I/O pin.
EBI address latch enable output pin.
USCI0 control 1 pin.
EBI_ALE
USCI0_CTL1
UART1_RXD
TM3_EXT
INT4
I/O
I
PA.8
UART1 data receiver input pin.
Timer3 external capture input/toggle output pin.
External interrupt 4 input pin.
I/O
I
PA.9
I/O
O
General purpose digital I/O pin.
EBI external clock output pin.
EBI_MCLK
PA.9 USCI0_DAT1
UART1_TXD
TM2_EXT
I/O
O
USCI0 data 1 pin.
UART1 data transmitter output pin.
Timer2 external capture input/toggle output pin.
General purpose digital I/O pin.
Analog comparator 1 positive input 0 pin.
EBI write enable output pin.
I/O
I/O
A
PA.10
ACMP1_P0
PA.10 EBI_nWR
USCI0_DAT0
TM1_EXT
O
I/O
I/O
I/O
A
USCI0 data 0 pin.
Timer1 external capture input/toggle output pin.
General purpose digital I/O pin.
Analog comparator 0 positive input 0 pin.
PA.11
PA.11
ACMP0_P0
Feb 25, 2019
Page 65 of 274
Rev. 1.01
M031/M032
Pin Name
EBI_nRD
Type
O
MFP
MFP2
MFP6
MFP13
MFP0
MFP4
MFP0
MFP4
MFP0
MFP3
MFP0
MFP3
MFP0
MFP1
MFP7
MFP8
MFP9
MFP11
MFP12
MFP13
MFP0
MFP1
MFP7
MFP9
MFP11
MFP12
MFP13
MFP0
MFP1
MFP1
MFP4
MFP6
MFP11
MFP14
MFP15
Description
EBI read enable output pin.
USCI0 clock pin.
USCI0_CLK
TM0_EXT
PA.12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Timer0 external capture input/toggle output pin.
General purpose digital I/O pin.
I2C1 clock pin.
PA.12
PA.13
PA.14
PA.15
I2C1_SCL
PA.13
General purpose digital I/O pin.
I2C1 data input/output pin.
I2C1_SDA
PA.14
General purpose digital I/O pin.
UART0 data transmitter output pin.
General purpose digital I/O pin.
UART0 data receiver input pin.
General purpose digital I/O pin.
ADC0 channel 0 analog input.
UART2 data receiver input pin.
SPI0 I2S master clock output pin
I2C1 data input/output pin.
UART0_TXD
PA.15
I/O
I
UART0_RXD
PB.0
I/O
A
ADC0_CH0
UART2_RXD
SPI0_I2SMCLK
I2C1_SDA
PWM0_CH5
PWM1_CH5
PWM0_BRAKE1
PB.1
I
I/O
I/O
I/O
I/O
I
PB.0
PWM0 channel 5 output/capture input.
PWM1 channel 5 output/capture input.
PWM0 Brake 1 input pin.
I/O
A
General purpose digital I/O pin.
ADC0 channel 1 analog input.
UART2 data transmitter output pin.
I2C1 clock pin.
ADC0_CH1
UART2_TXD
O
PB.1 I2C1_SCL
PWM0_CH4
I/O
I/O
I/O
I
PWM0 channel 4 output/capture input.
PWM1 channel 4 output/capture input.
PWM0 Brake 0 input pin.
PWM1_CH4
PWM0_BRAKE0
PB.2
I/O
A
General purpose digital I/O pin.
ADC0 channel 2 analog input.
Analog comparator 0 positive input 1 pin.
I2C1 data input/output pin.
ADC0_CH2
ACMP0_P1
I2C1_SDA
UART1_RXD
PWM0_CH3
TM3
A
I/O
I
PB.2
UART1 data receiver input pin.
PWM0 channel 3 output/capture input.
Timer3 event counter input/toggle output pin.
External interrupt 3 input pin.
I/O
I/O
I
INT3
Feb 25, 2019
Page 66 of 274
Rev. 1.01
M031/M032
Pin Name
PB.3
Type
I/O
A
MFP
MFP0
MFP1
MFP1
MFP4
MFP6
MFP11
MFP13
MFP14
MFP15
MFP0
MFP1
MFP1
MFP6
MFP11
MFP13
MFP14
MFP15
MFP0
MFP1
MFP1
MFP6
MFP11
MFP13
MFP14
MFP15
MFP0
MFP1
MFP2
MFP6
MFP8
MFP11
MFP12
MFP13
MFP15
Description
General purpose digital I/O pin.
ADC0 channel 3 analog input.
Analog comparator 0 negative input pin.
I2C1 clock pin.
ADC0_CH3
ACMP0_N
I2C1_SCL
PB.3 UART1_TXD
PWM0_CH2
PWM0_BRAKE0
TM2
A
I/O
O
UART1 data transmitter output pin.
PWM0 channel 2 output/capture input.
PWM0 Brake 0 input pin.
I/O
I
I/O
I
Timer2 event counter input/toggle output pin.
External interrupt 2 input pin.
INT2
PB.4
I/O
A
General purpose digital I/O pin.
ADC0 channel 4 analog input.
Analog comparator 1 positive input 1 pin.
I2C0 data input/output pin.
ADC0_CH4
ACMP1_P1
A
I2C0_SDA
PB.4
I/O
I/O
I
PWM0_CH1
PWM0 channel 1 output/capture input.
UART2 data receiver input pin.
Timer1 event counter input/toggle output pin.
External interrupt 1 input pin.
UART2_RXD
TM1
I/O
I
INT1
PB.5
I/O
A
General purpose digital I/O pin.
ADC0 channel 5 analog input.
Analog comparator 1 negative input pin.
I2C0 clock pin.
ADC0_CH5
ACMP1_N
A
I2C0_SCL
PB.5
I/O
I/O
O
PWM0_CH0
PWM0 channel 0 output/capture input.
UART2 data transmitter output pin.
Timer0 event counter input/toggle output pin.
External interrupt 0 input pin.
UART2_TXD
TM0
I/O
I
INT0
PB.6
I/O
A
General purpose digital I/O pin.
ADC0 channel 6 analog input.
EBI high byte write enable output pin
UART1 data receiver input pin.
EBI chip select 1 output pin.
ADC0_CH6
EBI_nWRH
UART1_RXD
PB.6 EBI_nCS1
PWM1_BRAKE1
PWM1_CH5
INT4
O
I
O
I
PWM1 Brake 1 input pin.
I/O
I
PWM1 channel 5 output/capture input.
External interrupt 4 input pin.
ACMP1_O
O
Analog comparator 1 output pin.
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Pin Name
PB.7
Type
I/O
A
MFP
MFP0
MFP1
MFP2
MFP6
MFP8
MFP11
MFP12
MFP13
MFP15
MFP0
MFP1
MFP2
MFP5
MFP6
MFP0
MFP1
MFP2
MFP5
MFP6
MFP0
MFP1
MFP2
MFP5
MFP7
MFP0
MFP1
MFP2
MFP5
MFP7
MFP9
MFP0
MFP1
MFP1
MFP1
Description
General purpose digital I/O pin.
ADC0 channel 7 analog input.
EBI low byte write enable output pin.
UART1 data transmitter output pin.
EBI chip select 0 output pin.
PWM1 Brake 0 input pin.
ADC0_CH7
EBI_nWRL
O
UART1_TXD
PB.7 EBI_nCS0
PWM1_BRAKE0
PWM1_CH4
INT5
O
O
I
I/O
I
PWM1 channel 4 output/capture input.
External interrupt 5 input pin.
Analog comparator 0 output pin.
General purpose digital I/O pin.
ADC0 channel 8 analog input.
EBI address bus bit 19.
ACMP0_O
O
PB.8
I/O
A
ADC0_CH8
PB.8 EBI_ADR19
UART0_RXD
UART1_nRTS
PB.9
O
I
UART0 data receiver input pin.
UART1 request to Send output pin.
General purpose digital I/O pin.
ADC0 channel 9 analog input.
EBI address bus bit 18.
O
I/O
A
ADC0_CH9
PB.9 EBI_ADR18
UART0_TXD
UART1_nCTS
PB.10
O
O
UART0 data transmitter output pin.
UART1 clear to Send input pin.
General purpose digital I/O pin.
ADC0 channel 10 analog input.
EBI address bus bit 17.
I
I/O
A
ADC0_CH10
PB.10 EBI_ADR17
UART0_nRTS
I2C1_SDA
O
O
UART0 request to Send output pin.
I2C1 data input/output pin.
I/O
I/O
A
PB.11
General purpose digital I/O pin.
ADC0 channel 11 analog input.
EBI address bus bit 16.
ADC0_CH11
EBI_ADR16
PB.11
O
UART0_nCTS
I
UART0 clear to Send input pin.
I2C1 clock pin.
I2C1_SCL
SPI0_I2SMCLK
PB.12
I/O
I/O
I/O
A
SPI0 I2S master clock output pin
General purpose digital I/O pin.
ADC0 channel 12 analog input.
Analog comparator 0 positive input 2 pin.
Analog comparator 1 positive input 2 pin.
ADC0_CH12
PB.12
ACMP0_P2
A
ACMP1_P2
A
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Pin Name
EBI_AD15
SPI0_MOSI
USCI0_CLK
UART0_RXD
PWM1_CH3
TM3_EXT
Type
I/O
I/O
I/O
I
MFP
MFP2
MFP4
MFP5
MFP6
MFP11
MFP13
MFP0
MFP1
MFP1
MFP1
MFP2
MFP4
MFP5
MFP6
MFP11
MFP13
MFP0
MFP1
MFP2
MFP4
MFP5
MFP6
MFP11
MFP13
MFP14
MFP0
MFP1
MFP2
MFP4
MFP5
MFP6
MFP11
MFP13
MFP15
Description
EBI address/data bus bit 15.
SPI0 MOSI (Master Out, Slave In) pin.
USCI0 clock pin.
UART0 data receiver input pin.
PWM1 channel 3 output/capture input.
I/O
I/O
I/O
A
Timer3 external capture input/toggle output pin.
General purpose digital I/O pin.
ADC0 channel 13 analog input.
Analog comparator 0 positive input 3 pin.
Analog comparator 1 positive input 3 pin.
EBI address/data bus bit 14.
PB.13
ADC0_CH13
ACMP0_P3
ACMP1_P3
EBI_AD14
SPI0_MISO
USCI0_DAT0
UART0_TXD
PWM1_CH2
TM2_EXT
A
A
I/O
I/O
I/O
O
PB.13
SPI0 MISO (Master In, Slave Out) pin.
USCI0 data 0 pin.
UART0 data transmitter output pin.
PWM1 channel 2 output/capture input.
Timer2 external capture input/toggle output pin.
General purpose digital I/O pin.
ADC0 channel 14 analog input.
EBI address/data bus bit 13.
I/O
I/O
I/O
A
PB.14
ADC0_CH14
EBI_AD13
SPI0_CLK
I/O
I/O
I/O
O
SPI0 serial clock pin.
PB.14 USCI0_DAT1
UART0_nRTS
PWM1_CH1
TM1_EXT
USCI0 data 1 pin.
UART0 request to Send output pin.
PWM1 channel 1 output/capture input.
Timer1 external capture input/toggle output pin.
Clock Out
I/O
I/O
O
CLKO
PB.15
I/O
A
General purpose digital I/O pin.
ADC0 channel 15 analog input.
EBI address/data bus bit 12.
ADC0_CH15
EBI_AD12
I/O
I/O
I/O
I
SPI0_SS
SPI0 slave select pin.
PB.15 USCI0_CTL1
UART0_nCTS
PWM1_CH0
TM0_EXT
USCI0 control 1 pin.
UART0 clear to Send input pin.
PWM1 channel 0 output/capture input.
Timer0 external capture input/toggle output pin.
PWM0 Brake 1 input pin.
I/O
I/O
I
PWM0_BRAKE1
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Pin Name
PC.0
Type
I/O
I/O
I
MFP
MFP0
MFP2
MFP8
MFP9
MFP12
MFP14
MFP0
MFP2
MFP8
MFP9
MFP12
MFP14
MFP0
MFP2
MFP8
MFP12
MFP0
MFP2
MFP8
MFP12
MFP0
MFP2
MFP8
MFP9
MFP12
MFP0
MFP2
MFP8
MFP9
MFP12
MFP0
MFP2
MFP7
MFP11
Description
General purpose digital I/O pin.
EBI address/data bus bit 0.
EBI_AD0
UART2_RXD
I2C0_SDA
PWM1_CH5
ACMP1_O
PC.1
UART2 data receiver input pin.
I2C0 data input/output pin.
PC.0
I/O
I/O
O
PWM1 channel 5 output/capture input.
Analog comparator 1 output pin.
General purpose digital I/O pin.
EBI address/data bus bit 1.
I/O
I/O
O
EBI_AD1
UART2_TXD
I2C0_SCL
PWM1_CH4
ACMP0_O
PC.2
UART2 data transmitter output pin.
I2C0 clock pin.
PC.1
I/O
I/O
O
PWM1 channel 4 output/capture input.
Analog comparator 0 output pin.
General purpose digital I/O pin.
EBI address/data bus bit 2.
I/O
I/O
I
EBI_AD2
UART2_nCTS
PWM1_CH3
PC.3
PC.2
PC.3
UART2 clear to Send input pin.
PWM1 channel 3 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 3.
I/O
I/O
I/O
O
EBI_AD3
UART2_nRTS
PWM1_CH2
PC.4
UART2 request to Send output pin.
PWM1 channel 2 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 4.
I/O
I/O
I/O
I
EBI_AD4
PC.4 UART2_RXD
I2C1_SDA
UART2 data receiver input pin.
I2C1 data input/output pin.
I/O
I/O
I/O
I/O
O
PWM1_CH1
PC.5
PWM1 channel 1 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 5.
EBI_AD5
PC.5 UART2_TXD
I2C1_SCL
UART2 data transmitter output pin.
I2C1 clock pin.
I/O
I/O
I/O
I/O
O
PWM1_CH0
PC.6
PWM1 channel 0 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 8.
EBI_AD8
PC.6
UART0_nRTS
UART0 request to Send output pin.
PWM1 channel 3 output/capture input.
PWM1_CH3
I/O
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Pin Name
TM1
Type
I/O
I
MFP
MFP14
MFP15
MFP0
MFP2
MFP7
MFP11
MFP14
MFP15
MFP0
MFP2
MFP4
MFP5
MFP13
MFP0
MFP2
MFP3
MFP4
MFP14
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP9
MFP0
MFP2
MFP3
MFP4
MFP9
MFP0
MFP12
Description
Timer1 event counter input/toggle output pin.
External interrupt 2 input pin.
General purpose digital I/O pin.
EBI address/data bus bit 9.
INT2
PC.7
I/O
I/O
I
EBI_AD9
UART0_nCTS
PWM1_CH2
TM0
UART0 clear to Send input pin.
PWM1 channel 2 output/capture input.
Timer0 event counter input/toggle output pin.
External interrupt 3 input pin.
General purpose digital I/O pin.
EBI address/data bus bit 11.
SPI0 I2S master clock output pin
USCI0 control 0 pin.
PC.7
I/O
I/O
I
INT3
PC.14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
EBI_AD11
PC.14 SPI0_I2SMCLK
USCI0_CTL0
TM1
Timer1 event counter input/toggle output pin.
General purpose digital I/O pin.
EBI address/data bus bit 13.
USCI0 clock pin.
PD.0
EBI_AD13
PD.0 USCI0_CLK
SPI0_MOSI
TM2
SPI0 MOSI (Master Out, Slave In) pin.
Timer2 event counter input/toggle output pin.
General purpose digital I/O pin.
EBI address/data bus bit 12.
USCI0 data 0 pin.
PD.1
EBI_AD12
PD.1
USCI0_DAT0
SPI0_MISO
PD.2
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
EBI address/data bus bit 11.
USCI0 data 1 pin.
EBI_AD11
PD.2 USCI0_DAT1
SPI0_CLK
SPI0 serial clock pin.
UART0_RXD
PD.3
UART0 data receiver input pin.
General purpose digital I/O pin.
EBI address/data bus bit 10.
USCI0 control 1 pin.
I/O
I/O
I/O
I/O
O
EBI_AD10
PD.3 USCI0_CTL1
SPI0_SS
SPI0 slave select pin.
UART0_TXD
UART0 data transmitter output pin.
General purpose digital I/O pin.
PWM0 channel 5 output/capture input.
PD.15
PD.15
I/O
I/O
PWM0_CH5
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Pin Name
TM3
Type
I/O
I
MFP
MFP14
MFP15
MFP0
MFP2
MFP3
MFP4
MFP14
MFP0
MFP2
MFP3
MFP4
MFP14
MFP0
MFP2
MFP3
MFP4
MFP10
MFP0
MFP2
MFP3
MFP4
MFP10
MFP0
MFP2
MFP4
MFP7
MFP10
MFP0
MFP2
MFP4
MFP7
MFP10
MFP11
MFP0
Description
Timer3 event counter input/toggle output pin.
External interrupt 1 input pin.
INT1
PF.0
I/O
O
General purpose digital I/O pin.
UART1 data transmitter output pin.
I2C1 clock pin.
UART1_TXD
PF.0 I2C1_SCL
UART0_TXD
ICE_DAT
I/O
O
UART0 data transmitter output pin.
Serial wired debugger data pin.
General purpose digital I/O pin.
UART1 data receiver input pin.
I2C1 data input/output pin.
O
PF.1
I/O
I
UART1_RXD
PF.1 I2C1_SDA
UART0_RXD
ICE_CLK
I/O
I
UART0 data receiver input pin.
Serial wired debugger clock pin.
General purpose digital I/O pin.
EBI chip select 1 output pin.
I
PF.2
I/O
O
EBI_nCS1
PF.2 UART0_RXD
I2C0_SDA
XT1_OUT
I
UART0 data receiver input pin.
I2C0 data input/output pin.
I/O
O
External 4~32 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
EBI chip select 0 output pin.
PF.3
I/O
O
EBI_nCS0
PF.3 UART0_TXD
I2C0_SCL
XT1_IN
O
UART0 data transmitter output pin.
I2C0 clock pin.
I/O
I
External 4~32 MHz (high speed) crystal input pin.
General purpose digital I/O pin.
UART2 data transmitter output pin.
UART2 request to Send output pin.
PWM0 channel 1 output/capture input.
External 32.768 kHz crystal output pin.
General purpose digital I/O pin.
UART2 data receiver input pin.
UART2 clear to Send input pin.
PWM0 channel 0 output/capture input.
External 32.768 kHz crystal input pin.
ADC0 external trigger input.
PF.4
I/O
O
UART2_TXD
PF.4 UART2_nRTS
PWM0_CH1
X32_OUT
O
I/O
O
PF.5
I/O
I
UART2_RXD
UART2_nCTS
PF.5
I
PWM0_CH0
I/O
I
X32_IN
ADC0_ST
I
PF.6 PF.6
I/O
General purpose digital I/O pin.
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Pin Name
Type
O
MFP
MFP2
Description
EBI_ADR19
SPI0_MOSI
EBI_nCS0
EBI address bus bit 19.
I/O
O
MFP5
SPI0 MOSI (Master Out, Slave In) pin.
EBI chip select 0 output pin.
General purpose digital I/O pin.
PWM1 Brake 0 input pin.
PWM0 Brake 0 input pin.
PWM0 channel 4 output/capture input.
Clock Out
MFP7
PF.14
I/O
I
MFP0
PWM1_BRAKE0
PWM0_BRAKE0
MFP9
I
MFP10
MFP12
MFP13
MFP14
MFP15
MFP0
PF.14 PWM0_CH4
I/O
O
CLKO
TM3
I/O
I
Timer3 event counter input/toggle output pin.
External interrupt 5 input pin.
General purpose digital I/O pin.
PWM0 Brake 0 input pin.
INT5
PF.15
I/O
I
PWM0_BRAKE0
PWM0_CH1
TM2
MFP11
MFP12
MFP13
MFP14
MFP15
I/O
I/O
O
PWM0 channel 1 output/capture input.
Timer2 event counter input/toggle output pin.
Clock Out
PF.15
CLKO
INT4
I
External interrupt 4 input pin.
Feb 25, 2019
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M031/M032
5 BLOCK DIAGRAM
5.1 M031/M032 Block Diagram
USB*: Only supported in the M032 series.
Figure 5.1-1 M031/M032 Block Diagram
Feb 25, 2019
Page 74 of 274
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M031/M032
6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6.1-1 shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
– Arm® 6-M Thumb® instruction set
– Thumb-2 technology
– Arm® 6-M compliant 24-bit SysTick timer
– A 32-bit hardware multiplier
– System interface supported with little-endian data accesses
– Ability to have deterministic, fixed-latency, interrupt handling
– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
– C Application Binary Interface compliant exception model. This is the Armv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use
of pure C functions as interrupt handlers
– Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
Feb 25, 2019
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(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
– 32 external interrupt inputs, each with four levels of priority
– Dedicated Non-maskable Interrupt (NMI) input
– Supports for both level-sensitive and pulse-sensitive interrupt lines
– Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Debug support:
– Four hardware breakpoints
– Two watchpoints
– Program Counter Sampling Register (PCSR) for non-intrusive code profiling
– Single step and vector catch capabilities
Bus interfaces:
– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
– Single 32-bit slave port that supports the DAP (Debug Access Port)
Feb 25, 2019
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6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
– nRESET glitch filter time 32us
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M031/M032
Glitch Filter
32 us
nRESET
~50k ohm
@3.3v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there are
small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 0 = 1
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[16])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
-
0x1
-
-
-
0x1
-
(CLK_APBCLK0[0])
HCLKSEL
Reload
Reload
Reload
Reload
Reload
Reload
Reload
Reload
-
Feb 25, 2019
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M031/M032
(CLK_CLKSEL0[2:0])
from
from
from
from
from
from
from
from
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
-
Reload
base
CONFIG0
-
-
-
on base on base on base on
on
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
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6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Table 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is
ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3
shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
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AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used
to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same status
after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
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6.2.3
System Power Distribution
In this chip, power distribution is divided into three segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be
located close to the corresponding pin. Figure 6.2-6 shows the NuMicro® M031 power distribution.
Analog
Comparator
12-bit ADC
AVDD
AVSS
Brown-out
Detector
Low Voltage Reset
Temperature
Sensor
SRAM
Flash
Digital Logic
1.8V
LDO_CAP
1uF
X32_IN
(PF.5)
32.768 kHz
crystal
oscillator
48 MHz
HIRC48
Oscillator
38.4 kHz
LIRC
Oscillator
PLL
POR18
X32_OUT
(PF.4)
XT1_IN
(PF.3)
4~32 MHz
crystal oscillator
VDD to 1.8V
LDO
Power On
Control
POR50
IO Cell
XT1_OUT
(PF.2)
Figure 6.2-6 NuMicro® M031 Power Distribution Diagram
Power Modes and Wake-up Sources
6.2.4
The M031 series has power manager unit to support several operating modes for saving power. Table
6.2-2 lists all power mode in the M031 series.
Mode
CPU Operating Maximum
Speed(MHz)
LDO_CAP(V)
Clock Disable
Normal mode
48
1.8
All clocks are disabled by control register.
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Idle mode
CPU enter Sleep mode
1.8
1.8
Only CPU clock is disabled.
Power-down mode
CPU enters Power-down
mode
Most clocks are disabled except LIRC/LXT,
and only WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected
as LIRC/LXT.
Table 6.2-2 Power Mode Table
There are different power mode entry settings and leaving condition for each power mode. Table 6.2-3
shows the entry setting for each power mode. When chip power-on, chip is running in normal mode.
User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT:[7]) and execute
WFI instruction.
Register/Instruction
Mode
SLEEPDEEP
(SCR[2])
PDEN
CPU Run WFI Instruction
(CLK_PWRCTL[7])
Normal mode
0
0
0
0
NO
Idle mode
YES
(CPU enter Sleep mode)
Power-down mode
1
1
YES
(CPU enters Deep Sleep
mode)
Table 6.2-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD,
GPIO, EINT, USCI, USBD, and
ACMP
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-4 Power Mode Difference Table
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System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC , HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP (SCS_SCR[2]) = 1
Wake-up events
occur
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[6]) = 1
3. CPU executes WFI
Idle Mode
CPU Clock OFF
HXT, HIRC, LXT , LIRC , HCLK, PCLK ON
Flash Halt
Power-down Mode
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
Flash Halt
Figure 6.2-7 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode.
2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If UART clock source is selected as LXT and LXT is on.
Normal Mode
ON
Idle Mode
ON
Power-Down Mode
HXT (4~32 MHz XTL)
Halt
Halt
HIRC48 (48 MHz OSC)
ON
ON
LXT (32768 Hz XTL)
LIRC (38.4 kHz OSC)
PLL
ON
ON
ON/OFF1
ON/OFF2
Halt
ON
ON
ON/OFF
ON
ON/OFF
ON
LDO
ON
CPU
ON
Halt
ON
Halt
HCLK/PCLK
SRAM retention
FLASH
ON
Halt
ON
ON
ON
ON
ON
Halt
GPIO
ON
ON
Halt
PDMA
ON
ON
Halt
TIMER
ON
ON
ON/OFF3
Halt
PWM
ON
ON
WDT
ON
ON
ON/OFF4
Halt
WWDT
ON
ON
UART
ON
ON
ON/OFF6
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USCI
I2C
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
Halt
Halt
Halt
Halt
SPI
USBD
ADC
ACMP
Table 6.2-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, USCI, BOD, GPIO, USBD, and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-5 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear (SYS_BODCTL[4]).
INT
External Interrupt
GPIO Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
TIMER
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
Timer Interrupt
WDT
WDT Interrupt
nCTS wake-up
RX Data wake-up
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
Received FIFO Threshold
Wake-up
After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]).
UART0/1
RS-485 AAD Mode Wake-up After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]).
Received FIFO Threshold
After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]).
Time-out Wake-up
nCTS wake-up
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
UART2
I2C
RX Data wake-up
Address match or GC mode
match wake-up.
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
USBD
ACMP
Remote Wake-up
Comparator Power-Down After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1
Wake-Up Interrupt (ACMP_STATUS[9]).
Table 6.2-6 Condition of Entering Power-down Mode Again
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6.2.5
System Memory Map
The NuMicro® M031 series provides 4G-byte addressing space. The memory locations assigned to
each on-chip controllers are shown inTable 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The M031 series
only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
SRAM0_BA
EXTMEM_BA
FLASH Memory Space (192KB)
SRAM Memory Space (16KB)
External Memory Space (256MB)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4001_0000 – 0x4001_0FFF
0x4001_4000 – 0x4001_7FFF
0x4003_1000 – 0x4003_1FFF
SYS_BA
CLK_BA
NMI_BA
GPIO_BA
PDMA_BA
FMC_BA
EBI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
External Bus Interface Control Registers
Hardware Divider Register
CRC Generator Registers
HDIV_BA
CRC_BA
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4006_1000 – 0x4006_0FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x400C_0000 – 0x400C_0FFF
0x400D_0000 – 0x400D_0FFF
WDT_BA
Watchdog Timer Control Registers
Analog-Digital-Converter (ADC) Control Registers
Analog Comparator 0/ 1 Control Registers
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
PWM0 Control Registers
ADC_BA
ACMP01_BA
TMR01_BA
TMR23_BA
PWM0_BA
PWM1_BA
SPI0_BA
PWM1 Control Registers
SPI0 Control Registers
UART0_BA
UART1_BA
UART2_BA
I2C0_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
USBD_BA
USCI0_BA
USB Device Control Register
USCI0 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
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0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Controllers
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6.2.6
SRAM Memory Orginization
The M031 supports embedded SRAM with total 16 Kbytes size
Supports total 16 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
Table 6.2-10 shows the SRAM organization of M031. The address between 0x2000_4000 to
0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses.
0x3FFF_FFFF
Reserved
Reserved
Reserved
Reserved
0x2000_4000
0x2000_2000
0x2000_1000
16K byte
SRAM bank0
8K byte
SRAM bank0
4K byte
SRAM bank0
0x2000_0800
2K byte
SRAM bank0
0x2000_0000
4K byte device
16K byte device
8K byte device
2K byte device
Figure 6.2-8 SRAM Memory Organization
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6.2.7
Chip Bus Matrix
The M031 series supports Bus Matrix to manage the access arbitration between masters. The access
arbitration use round-robin algorithm as the bus priority.
M1
PDMA
M0
Cortex® -M0
S0
S1
S2
APB0
S3
APB1
S4
S5
EBI
AHB
(ctrl)
FLASH
SRAM
Figure 6.2-9 NuMicro® M031 Bus Matrix Diagram
6.2.8
IRC Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate
external 32.768 kHz crystal oscillator or internal USB synchronous mode, automatically gets accurate
output frequency, 0.25 % deviation within all temperature ranges.
In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal or in system, user has to set REFCKSEL
(SYS_HIRCTRIMCTL [10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTRIMCTL [1:0]
trim frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_HIRCTRIMSTS[0] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation.
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6.2.9
Register Lock Control
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence. All proteced control registers are noted “(Write
Protect)” and add an note “Note: This bit is write protected. Refer to the SYS_REGLCTL register “ in
register description field.
Register
Bit
Description
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_IPRST0
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_BODCTL
SYS_PORCTL
SYS_SRAM_BISTCTL
SYS_SRAM_BISTCTL
SYS_PORDISAN
NMIEN
[7] CRCRST
[4] HDIV_RST
[3] EBIRST
CRC Calculation Controller Reset (Write Protect)
HDIV Controller Reset (Write Protect)
EBI Controller Reset (Write Protect)
[2] PDMARST
[1] CPURST
[0] CHIPRST
[20] LVRVL
PDMA Controller Reset (Write Protect)
Processor Core One-shot Reset (Write Protect)
Chip One-shot Reset (Write Protect)
LVR Detector Threshold Voltage Selection (Write Protect)
Brown-out Detector Threshold Voltage Selection (Write Protect)
LVR Output De-glitch Time Select (Write Protect)
Brown-out Detector Output De-glitch Time Select (Write Protect)
Low Voltage Reset Enable Bit (Write Protect)
Brown-out Detector Low Power Mode (Write Protect)
Brown-out Reset Enable Bit (Write Protect)
Brown-out Detector Enable Bit (Write Protect)
Power-on Reset Enable Bit (Write Protect)
PDMA BIST Enable Bit (Write Protect)
[16] BODVL
[14:12] LVRDGSEL
[10:8] BODDGSEL
[7] LVREN
[5] BODLPM
[3] BODRSTEN
[0] BODEN
[15:0] POROFF
[7] PDMABIST
[4] USBBIST
[15:0] POROFFAN
[15] UART1_INT
[14] UART0_INT
[13] EINT5
USB BIST Enable Bit (Write Protect)
Power-on Reset Enable Bit (Write Protect)
UART1 NMI Source Enable (Write Protect)
UART0 NMI Source Enable (Write Protect)
NMIEN
NMIEN
External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write
Protect)
NMIEN
NMIEN
NMIEN
NMIEN
[12] EINT4
[11] EINT3
[10] EINT2
[9] EINT1
External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable
(Write Protect)
External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write
Protect)
External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write
Protect)
External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable
(Write Protect)
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NMIEN
NMIEN
[8] EINT0
External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write
Protect)
[4] CLKFAIL
Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable
(Write Protect)
NMIEN
[2] PWRWU_INT
[1] IRC_INT
[0] BODOUT
[26:25] LXTGAIN
[22:20] HXTGAIN
[7] PDEN
Power-down Mode Wake-up NMI Source Enable (Write Protect)
IRC TRIM NMI Source Enable (Write Protect)
BOD NMI Source Enable (Write Protect)
NMIEN
NMIEN
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_PWRCTL
CLK_APBCLK0
CLK_CLKSEL0
CLK_CLKSEL0
CLK_CLKSEL0
CLK_CLKSEL1
CLK_CLKSEL1
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_PLLCTL
CLK_CLKDSTS
CLK_CLKDSTS
CLK_CLKDSTS
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
LXT Gain Control Bit (Write Protect)
HXT Gain Control Bit (Write Protect)
System Power-down Enable (Write Protect)
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
Enable the Wake-up Delay Counter (Write Protect)
LIRC Enable Bit (Write Protect)
[5] PDWKIEN
[4] PDWKDLY
[3] LIRCEN
[2] HIRCEN
[1] LXTEN
HIRC Enable Bit (Write Protect)
LXT Enable Bit (Write Protect)
[0] HXTEN
HXT Enable Bit (Write Protect)
[0] WDTCKEN
[8] USBDSEL
[5:3] STCLKSEL
[2:0] HCLKSEL
[3:2] WWDTSEL
[1:0] WDTSEL
[23] STBSEL
[19] PLLSRC
[18] OE
Watchdog Timer Clock Enable Bit (Write Protect)
USB Device Clock Source Selection (Write Protect)
Cortex® -M0 SysTick Clock Source Selection (Write Protect)
HCLK Clock Source Selection (Write Protect)
Window Watchdog Timer Clock Source Selection (Write Protect)
Watchdog Timer Clock Source Selection (Write Protect)
PLL Stable Counter Selection (Write Protect)
PLL Source Clock Selection (Write Protect)
PLL OE (FOUT Enable) Pin Control (Write Protect)
PLL Bypass Control (Write Protect)
[17] BP
[16] PD
Power-down Mode (Write Protect)
[15:14] OUTDIV
[13:9] INDIV
[8:0] FBDIV
[8] HXTFQIF
[1] LXTFIF
PLL Output Divider Control (Write Protect)
PLL Input Divider Control (Write Protect)
PLL Feedback Divider Control (Write Protect)
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
LXT Clock Fail Interrupt Flag (Write Protect)
HXT Clock Fail Interrupt Flag (Write Protect)
ISP Fail Flag (Write Protect)
[0] HXTFIF
[6] ISPFF
[5] LDUEN
LDROM Update Enable Bit (Write Protect)
CONFIG Update Enable Bit (Write Protect)
[4] CFGUEN
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FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPCTL
FMC_ISPTRG
FMC_FTCTL
FMC_ISPSTS
TIMER0_CTL
TIMER1_CTL
TIMER2_CTL
TIMER3_CTL
WDT_CTL
[3] APUEN
APROM Update Enable Bit (Write Protect)
SPROM Update Enable Bit (Write Protect)
Boot Select (Write Protect)
[2] SPUEN
[1] BS
[0] ISPEN
ISP Enable Bit (Write Protect)
[0] ISPGO
ISP Start Trigger (Write Protect)
Frequency Optimization Mode (Write Protect)
ISP Fail Flag (Write Protect)
[6:4] FOM
[6] ISPFF
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[31] ICEDEBUG
[11:8] TOUTSEL
[7] WDTEN
[6] INTEN
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
WDT Time-out Interval Selection (Write Protect)
WDT Enable Bit (Write Protect)
WDT_CTL
WDT_CTL
WDT_CTL
WDT Time-out Interrupt Enable Bit (Write Protect)
WDT Time-out Wake-up Flag (Write Protect)
WDT_CTL
[5] WKF
WDT_CTL
[4] WKEN
WDT Time-out Wake-up Function Control (Write Protect)
WDT Time-out Reset Enable Bit (Write Protect)
WDT Reset Delay Selection (Write Protect)
WDT_CTL
[1] RSTEN
WDT_ALTCTL
PWM_CTL0
PWM_CTL0
PWM_DTCTL0_1
PWM_DTCTL0_1
[1:0] RSTDSEL
[31] DBGTRIOFF
[30] DBGHALT
[24] DTCKSEL
[16] DTEN
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Counter Halt (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL0_1
PWM_DTCTL2_3
PWM_DTCTL2_3
[11:0] DTCNT
[24] DTCKSEL
[16] DTEN
Dead-time Counter (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL2_3
PWM_DTCTL4_5
PWM_DTCTL4_5
[11:0] DTCNT
[24] DTCKSEL
[16] DTEN
Dead-time Counter (Write Protect)
Dead-time Clock Select (Write Protect)
Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1)
(PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
PWM_DTCTL4_5
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[11:0] DTCNT
Dead-time Counter (Write Protect)
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
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PWM_BRKCTL0_1
PWM_BRKCTL0_1
[12] BRKP0LEN
[9] CPO1LBEN
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL0_1
[8] CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[7] SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
[5] BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL0_1
PWM_BRKCTL0_1
PWM_BRKCTL0_1
[4] BRKP0EEN
[1] CPO1EBEN
[0] CPO0EBEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
[12] BRKP0LEN
[9] CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
[8] CPO0LBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[7] SYSEBEN
Enable System Fail As Edge-detect Brake Source (Write Protect)
[5] BRKP1EEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL2_3
PWM_BRKCTL2_3
PWM_BRKCTL2_3
[4] BRKP0EEN
[1] CPO1EBEN
[0] CPO0EBEN
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
[19:18] BRKAODD
[17:16] BRKAEVEN
[15] SYSLBEN
PWM Brake Action Select for Odd Channel (Write Protect)
PWM Brake Action Select for Even Channel (Write Protect)
Enable System Fail As Level-detect Brake Source (Write Protect)
Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
[13] BRKP1LEN
[12] BRKP0LEN
[9] CPO1LBEN
Enable ACMP1_O Digital Output As Level-detect Brake Source (Write
Protect)
PWM_BRKCTL4_5
PWM_BRKCTL4_5
[8] CPO0LBEN
[7] SYSEBEN
Enable ACMP0_O Digital Output As Level-detect Brake Source (Write
Protect)
Enable System Fail As Edge-detect Brake Source (Write Protect)
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PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_BRKCTL4_5
PWM_SWBRK
[5] BRKP1EEN
[4] BRKP0EEN
[1] CPO1EBEN
[0] CPO0EBEN
Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write
Protect)
Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write
Protect)
Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write
Protect)
Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write
Protect)
[8+n/2]
PWM Level Brake Software Trigger (Write Only) (Write Protect)
n=0,2,4 BRKLTRGn
PWM_SWBRK
[n/2]
PWM Edge Brake Software Trigger (Write Only) (Write Protect)
n=0,2,4 BRKETRGn
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTEN1
PWM_INTSTS1
[10] BRKLIEN4_5
[9] BRKLIEN2_3
[8] BRKLIEN0_1
[2] BRKEIEN4_5
[1] BRKEIEN2_3
[0] BRKEIEN0_1
PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write
Protect)
PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write
Protect)
PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write
Protect)
PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write
Protect)
[8+n]
PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)
PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)
ADC RESET (Write Protect)
n=0,1..5 BRKLIFn
PWM_INTSTS1
ADC_ADCR
[n]
n=0,1..5 BRKEIFn
[12] RESET
Table 6.2-8 Protected Register List
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6.2.10 UART0_TXD/USCI0_DAT0 modulation with PWM
This chip supports UART0_TXD/USCI_DAT0 to modulate with PWM channel. User can set
MODPWMSEL(SYS_MODCTL[7:4]) to choose which PWM0 channel to modulate with
UART0_TXD/USCI0_DAT0 and set MODEN(SYS_MODCTL[0]) to enable modulation function. User
can set TXDINV(UART_LINE[8]) to inverse UART0_TXD or DATOINV(UUART_LINECTL[5]) to
inverse USCI0_DAT0 before modulating with PWM.
PWM0_CHx
UART0_TXD/USCI0_DAT0
TXDINV = 0 & MODH = 0
TXDINV = 0 & MODH = 1
TXDINV = 1 & MODH = 0
TXDINV = 1 & MODH = 1
Figure 6.2-11 UART0_TXD/USCI0_DAT0 Modulated with PWM Channel
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6.2.11 Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
SYS Base Address:
SYS_BA = 0x4000_0000
SYS_PDID
SYS_BA+0x00
R
Part Device Identification Number Register
0xXXXX_XXXX
0x0000_0043
0x0000_0000
0x0000_0000
0x0000_0000
0x00XX_038X
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_00ee
SYS_RSTSTS
SYS_IPRST0
SYS_IPRST1
SYS_IPRST2
SYS_BODCTL
SYS_PORCTL
SYS_BA+0x04 R/W System Reset Status Register
SYS_BA+0x08 R/W Peripheral Reset Control Register 0
SYS_BA+0x0C R/W Peripheral Reset Control Register 1
SYS_BA+0x10 R/W Peripheral Reset Control Register 2
SYS_BA+0x18 R/W Brown-out Detector Control Register
SYS_BA+0x24 R/W Power-On-reset Controller Register
SYS_GPA_MFPL SYS_BA+0x30 R/W GPIOA Low Byte Multiple Function Control Register
SYS_GPA_MFPH SYS_BA+0x34 R/W GPIOA High Byte Multiple Function Control Register
SYS_GPB_MFPL SYS_BA+0x38 R/W GPIOB Low Byte Multiple Function Control Register
SYS_GPB_MFPH SYS_BA+0x3C R/W GPIOB High Byte Multiple Function Control Register
SYS_GPC_MFPL SYS_BA+0x40 R/W GPIOC Low Byte Multiple Function Control Register
SYS_GPC_MFPH SYS_BA+0x44 R/W GPIOC High Byte Multiple Function Control Register
SYS_GPD_MFPL SYS_BA+0x48 R/W GPIOD Low Byte Multiple Function Control Register
SYS_GPD_MFPH SYS_BA+0x4C R/W GPIOD High Byte Multiple Function Control Register
SYS_GPF_MFPL SYS_BA+0x58 R/W GPIOF Low Byte Multiple Function Control Register
SYS_GPF_MFPH SYS_BA+0x5C R/W GPIOF High Byte Multiple Function Control Register
0x0000_0000
0x0000_0000
SYS_MODCTL
SYS_BA+0xC0 R/W Modulation Control Register
SYS_SRAM_BIST
CTL
SYS_BA+0xD0 R/W System SRAM BIST Test Control Register
0x0000_0000
0x00xx_00xx
0x0008_0000
0x0000_0000
0x0000_0000
SYS_SRAM_BIST
STS
SYS_BA+0xD4
R
System SRAM BIST Test Status Register
SYS_HIRCTRIMC
TL
SYS_BA+0xF0 R/W HIRC Trim Control Register
SYS_HIRCTRIMIE
N
SYS_BA+0xF4 R/W HIRC Trim Interrupt Enable Register
SYS_BA+0xF8 R/W HIRC Trim Interrupt Status Register
SYS_HIRCTRIMS
TS
SYS_REGLCTL
SYS_BA+0x100 R/W Register Lock Control Register
0x0000_0000
0x0000_0000
SYS_PORDISAN SYS_BA+0x1EC R/W Analog POR Disable Control Register
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6.2.12 Register Description
Part Device Identification Number Register (SYS_PDID)
Register
Offset
R/W Description
Part Device Identification Number Register
Reset Value
SYS_PDID
SYS_BA+0x00
R
0xXXXX_XXXX
[1] Every part number has a unique default reset value.
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PDID
PDID
PDID
PDID
1
0
Bits
Description
Part Device Identification Number (Read Only)
[31:0]
PDID
This register reflects device part number code. Software can read this register to identify
which device is used.
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System Reset Status Register (SYS_RSTSTS)
This register provides specific information for software to identify this chip’s reset source from last
operation.
Register
Offset
R/W Description
Reset Value
SYS_RSTSTS SYS_BA+0x04
R/W System Reset Status Register
0x0000_0043
31
23
15
30
22
14
29
21
13
28
20
12
27
19
11
26
18
10
25
17
9
24
16
Reserved
Reserved
8
CPULKRF
0
Reserved
4
7
6
5
3
2
1
CPURF
Reserved
SYSRF
BODRF
LVRF
WDTRF
PINRF
PORF
Bits
Description
Reserved
[31:9]
Reserved.
CPU Lockup Reset Flag
0 = No reset from CPU lockup happened.
1 = The Cortex® -M0 lockup happened and chip is reset.
[8]
CPULKRF
Note: Write 1 to clear this bit to 0.
Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but
chip will not reset.
CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to
reset Cortex® - M0 Core and Flash Memory Controller (FMC).
[7]
[6]
CPURF
0 = No reset from CPU.
1 = The Cortex® -M0 Core and FMC are reset by software setting CPURST to 1.
Note: Write to clear this bit to 0.
Reserved
Reserved.
System Reset Flag
The system reset flag is set by the “Reset Signal” from the Cortex® -M0 Core to indicate the
previous reset source.
0 = No reset from Cortex® -M0.
[5]
SYSRF
1 = The Cortex® - M0 had issued the reset signal to reset the system by writing 1 to the bit
SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address =
0xE000ED0C) in system control registers of Cortex® -M0 core.
Note: Write 1 to clear this bit to 0.
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Bits
Description
BODRF
BOD Reset Flag
The BOD reset flag is set by the “Reset Signal” from the Brown-Out Detector to indicate
the previous reset source.
[4]
0 = No reset from BOD.
1 = The BOD had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
LVR Reset Flag
The LVR reset flag is set by the “Reset Signal” from the Low Voltage Reset Controller to
indicate the previous reset source.
[3]
LVRF
0 = No reset from LVR.
1 = LVR controller had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
WDT Reset Flag
The WDT reset flag is set by the “Reset Signal” from the Watchdog Timer or Window
Watchdog Timer to indicate the previous reset source.
0 = No reset from watchdog timer or window watchdog timer.
1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the
system.
[2]
WDTRF
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been
reset
by
WDT
time-out
reset.
Window
Watchdog
Timer
register
WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out
reset.
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the “Reset Signal” from the nRESET Pin to indicate
the previous reset source.
[1]
[0]
PINRF
0 = No reset from nRESET pin.
1 = Pin nRESET had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
POR Reset Flag
The POR reset flag is set by the “Reset Signal” from the Power-on Reset (POR) Controller
or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
PORF
0 = No reset from POR or CHIPRST.
1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
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Peripheral Reset Control Register 0 (SYS_IPRST0)
Register
Offset
R/W
Description
Reset Value
SYS_IPRST0
SYS_BA+0x08
R/W
Peripheral Reset Control Register 0
0x0000_0000
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
3
2
1
0
CRCRST
Reserved
HDIV_RST
EBIRST
PDMARST
CPURST
CHIPRST
Bits
Description
Reserved
[31:8]
Reserved.
CRC Calculation Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to
set this bit to 0 to release from the reset state.
[7]
CRCRST
Reserved
HDIV_RST
0 = CRC calculation controller normal operation.
1 = CRC calculation controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6:5]
[4]
Reserved.
HDIV Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the hardware divider. User need to set this
bit to 0 to release from the reset state.
0 = Hardware divider controller normal operation.
1 = Hardware divider controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
EBI Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to
release from the reset state.
[3]
EBIRST
0 = EBI controller normal operation.
1 = EBI controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0
to release from reset state.
[2]
[1]
PDMARST
CPURST
0 = PDMA controller normal operation.
1 = PDMA controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Processor Core One-shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and
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this bit will automatically return to 0 after the 2 clock cycles.
0 = Processor core normal operation.
1 = Processor core one-shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and
this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip
setting from flash are also reload.
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to
section 6.2.2
[0]
CHIPRST
0 = Chip normal operation.
1 = Chip one-shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note : reset by powr on reset
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Peripheral Reset Control Register 1 (SYS_IPRST1)
Setting these bits 1 will generate asynchronous reset signals to the corresponding module controller.
Users need to set these bits to 0 to release corresponding module controller from reset state.
Register
Offset
R/W
Description
Reset Value
SYS_IPRST1
SYS_BA+0x0C
R/W
Peripheral Reset Control Register 1
0x0000_0000
31
23
15
30
Reserved
22
29
28
ADCRST
20
27
USBDRST
19
26
25
Reserved
17
24
21
Reserved
13
18
UART2RST
10
16
UART0RST
8
UART1RST
9
14
12
11
Reserved
3
Reserved
SPI0RST
5
I2C1RST
1
I2C0RST
0
7
6
4
2
ACMP01RST
Reserved
TMR3RST
TMR2RST
TMR1RST
TMR0RST
GPIORST
Reserved
Bits
Description
Reserved
[31:29]
Reserved.
ADC Controller Reset
[28]
ADCRST
0 = ADC controller normal operation.
1 = ADC controller reset.
USBD Controller Reset
[27]
USBDRST
Reserved
UART2RST
0 = USBD controller normal operation.
1 = USBD controller reset.
[26:19]
[18]
Reserved.
UART2 Controller Reset
0 = UART2 controller normal operation.
1 = UART2 controller reset.
UART1 Controller Reset
[17]
UART1RST
0 = UART1 controller normal operation.
1 = UART1 controller reset.
UART0 Controller Reset
[16]
UART0RST
Reserved
SPI0RST
0 = UART0 controller normal operation.
1 = UART0 controller reset.
[15:14]
[13]
Reserved.
SPI0 Controller Reset
0 = SPI0 controller normal operation.
1 = SPI0 controller reset.
[12:10]
[9]
Reserved
I2C1RST
Reserved.
I2C1 Controller Reset
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0 = I2C1 controller normal operation.
1 = I2C1 controller reset.
I2C0 Controller Reset
[8]
I2C0RST
0 = I2C0 controller normal operation.
1 = I2C0 controller reset.
Analog Comparator 0/1 Controller Reset
0 = Analog Comparator 0/1 controller normal operation.
1 = Analog Comparator 0/1 controller reset.
[7]
[6]
[5]
ACMP01RST
Reserved
Reserved.
Timer3 Controller Reset
TMR3RST
0 = Timer3 controller normal operation.
1 = Timer3 controller reset.
Timer2 Controller Reset
[4]
[3]
[2]
TMR2RST
TMR1RST
TMR0RST
0 = Timer2 controller normal operation.
1 = Timer2 controller reset.
Timer1 Controller Reset
0 = Timer1 controller normal operation.
1 = Timer1 controller reset.
Timer0 Controller Reset
0 = Timer0 controller normal operation.
1 = Timer0 controller reset.
GPIO Controller Reset
[1]
[0]
GPIORST
Reserved
0 = GPIO controller normal operation.
1 = GPIO controller reset.
Reserved.
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Peripheral Reset Control Register 2 (SYS_IPRST2)
Setting these bits to 1 will generate asynchronous reset signals to the corresponding module
controller. Users need to set these bits to 0 to release corresponding module controller from reset
state.
Register
Offset
R/W
Description
Reset Value
SYS_IPRST2
SYS_BA+0x10
R/W
Peripheral Reset Control Register 2
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
24
Reserved
17
PWM1RST
9
16
Reserved
PWM0RST
8
Reserved
4
USCI0RST
0
1
Reserved
Bits
Description
Reserved
[31:18]
Reserved.
PWM1 Controller Reset
[17]
PWM1RST
0 = PWM1 controller normal operation.
1 = PWM1 controller reset.
PWM0 Controller Reset
[16]
[15:9]
[8]
PWM0RST
Reserved
USCI0RST
Reserved
0 = PWM0 controller normal operation.
1 = PWM0 controller reset.
Reserved.
USCI0 Controller Reset
0 = USCI0 controller normal operation.
1 = USCI0 controller reset.
[7:0]
Reserved.
Feb 25, 2019
Page 105 of 274
Rev. 1.01
M031/M032
Brown-out Detector Control Register (SYS_BODCTL)
Partial of the SYS_BODCTL control registers values are initiated by the flash configuration and partial
bits are write-protected bit.
Register
Offset
R/W Description
Reset Value
SYS_BODCTL SYS_BA+0x18
R/W Brown-out Detector Control Register
0x00XX_038X
31
23
30
29
21
28
20
27
19
26
25
17
24
Reserved
22
Reserved
14
18
Reserved
10
16
BODVL
8
LVRVL
12
15
Reserved
7
13
LVRDGSEL
5
11
Reserved
3
9
BODDGSEL
1
6
4
2
0
LVREN
BODOUT
BODLPM
BODIF
BODRSTEN
Reserved
BODEN
Bits
[31:21]
Description
Reserved
Reserved.
LVR Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register LVRLVSEL
(CONFIG0 [29]).
0 = LVR-Out Detector threshold voltage is 1.6V.
1 = LVR-Out Detector threshold voltage is 1.7V.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note: This bit is only for special case.
[20]
LVRVL
Note: reset by powr on reset
[19:17]
[16]
Reserved
BODVL
Reserved.
Brown-out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register CBOV (CONFIG0
[21]).
0 = Brown-Out Detector threshold voltage is 2.0V.
1 = Brown-Out Detector threshold voltage is 2.5V.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note : reset by powr on reset
[15]
Reserved
Reserved.
Feb 25, 2019
Page 106 of 274
Rev. 1.01
M031/M032
Bits
Description
LVRDGSEL
Reserved
LVR Output De-glitch Time Select (Write Protect)
000 = Without de-glitch function.
001 = 64 system clock (HCLK).
010 = 128 system clock (HCLK).
011 = 256 system clock (HCLK).
100 = 512 system clock (HCLK).
101 = 1024 system clock (HCLK).
110 = 2048 system clock (HCLK).
111 = 4096 system clock (HCLK).
[14:12]
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
[11]
Reserved.
Brown-out Detector Output De-glitch Time Select (Write Protect)
000 = BOD output is sampled by LIRC clock.
001 = 64 system clock (HCLK).
010 = 128 system clock (HCLK).
011 = 256 system clock (HCLK).
[10:8]
BODDGSEL
100 = 512 system clock (HCLK).
101 = 1024 system clock (HCLK).
110 = 2048 system clock (HCLK).
111 = 4096 system clock (HCLK).
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit
setting. LVR function is enabled by default.
0 = Low Voltage Reset function Disabled.
1 = Low Voltage Reset function Enabled.
[7]
LVREN
Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR
output stable (default).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
Brown-out Detector Output Status
0 = Brown-out Detector output status is 0.
It means the detected voltage is higher than BODVL setting or BODEN is 0.
1 = Brown-out Detector output status is 1.
[6]
[5]
BODOUT
BODLPM
It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD
function disabled , this bit always responds 0000.
Brown-out Detector Low Power Mode (Write Protect)
0 = BOD operate in normal mode (default).
1 = BOD Low Power mode Enabled.
Note1: The BOD consumes about 100uA in normal mode, the low power mode can
reduce the current to about 1/10 but slow the BOD response.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
Feb 25, 2019
Page 107 of 274
Rev. 1.01
M031/M032
Bits
Description
BODIF
Brown-out Detector Interrupt Flag
0 = Brown-out Detector does not detect any voltage draft at VDD down through or up
through the voltage of BODVL setting.
[4]
1 = When Brown-out Detector detects the VDD is dropped down through the voltage of
BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set
to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
Note: Write 1 to clear this bit to 0.
Brown-out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register
CBORST(CONFIG0[20]) bit .
0 = Brown-out “INTERRUPT” function Enabled.
1 = Brown-out “RESET” function Enabled.
Note1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is
enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected
voltage is lower than the threshold (BODOUT high).
[3]
BODRSTEN
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled
(BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep
till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD
interrupt or disabling BOD function (set BODEN low).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
Note : reset by powr on reset
[2:1]
[0]
Reserved
BODEN
Reserved.
Brown-out Detector Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBODEN (CONFIG0
[19]).
0 = Brown-out Detector function Disabled.
1 = Brown-out Detector function Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note : reset by powr on reset
Feb 25, 2019
Page 108 of 274
Rev. 1.01
M031/M032
Power-on Reset Controller Register (SYS_PORCTL)
Register
Offset
R/W Description
Reset Value
SYS_PORCTL SYS_BA+0x24
R/W Power-On-reset Controller Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
POROFF
POROFF
1
0
Bits
Description
Reserved
[31:16]
Reserved.
Power-on Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip
function, but noise on the power may cause the POR active again. User can disable internal
POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
[15:0]
POROFF
The POR function will be active again when this field is set to another value or chip is reset
by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip
reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Feb 25, 2019
Page 109 of 274
Rev. 1.01
M031/M032
GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPA_MFPL SYS_BA+0x30 R/W GPIOA Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PA7MFP
PA5MFP
PA3MFP
PA1MFP
PA6MFP
PA4MFP
PA2MFP
PA0MFP
1
0
Bits
Description
PA7MFP
PA6MFP
PA5MFP
PA4MFP
PA3MFP
PA2MFP
PA1MFP
PA0MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PA.7 Multi-function Pin Selection
PA.6 Multi-function Pin Selection
PA.5 Multi-function Pin Selection
PA.4 Multi-function Pin Selection
PA.3 Multi-function Pin Selection
PA.2 Multi-function Pin Selection
PA.1 Multi-function Pin Selection
PA.0 Multi-function Pin Selection
[3:0]
Feb 25, 2019
Page 110 of 274
Rev. 1.01
M031/M032
GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPA_MFPH SYS_BA+0x34 R/W GPIOA High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PA15MFP
PA13MFP
PA11MFP
PA9MFP
PA14MFP
PA12MFP
PA10MFP
PA8MFP
1
0
Bits
Description
PA15MFP
PA14MFP
PA13MFP
PA12MFP
PA11MFP
PA10MFP
PA9MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PA.15 Multi-function Pin Selection
PA.14 Multi-function Pin Selection
PA.13 Multi-function Pin Selection
PA.12 Multi-function Pin Selection
PA.11 Multi-function Pin Selection
PA.10 Multi-function Pin Selection
PA.9 Multi-function Pin Selection
PA.8 Multi-function Pin Selection
[3:0]
PA8MFP
Feb 25, 2019
Page 111 of 274
Rev. 1.01
M031/M032
GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPB_MFPL SYS_BA+0x38 R/W GPIOB Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PB7MFP
PB5MFP
PB3MFP
PB1MFP
PB6MFP
PB4MFP
PB2MFP
PB0MFP
1
0
Bits
Description
PB7MFP
PB6MFP
PB5MFP
PB4MFP
PB3MFP
PB2MFP
PB1MFP
PB0MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PB.7 Multi-function Pin Selection
PB.6 Multi-function Pin Selection
PB.5 Multi-function Pin Selection
PB.4 Multi-function Pin Selection
PB.3 Multi-function Pin Selection
PB.2 Multi-function Pin Selection
PB.1 Multi-function Pin Selection
PB.0 Multi-function Pin Selection
[3:0]
Feb 25, 2019
Page 112 of 274
Rev. 1.01
M031/M032
GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPB_MFPH SYS_BA+0x3C R/W GPIOB High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PB15MFP
PB13MFP
PB11MFP
PB9MFP
PB14MFP
PB12MFP
PB10MFP
PB8MFP
1
0
Bits
Description
PB15MFP
PB14MFP
PB13MFP
PB12MFP
PB11MFP
PB10MFP
PB9MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PB.15 Multi-function Pin Selection
PB.14 Multi-function Pin Selection
PB.13 Multi-function Pin Selection
PB.12 Multi-function Pin Selection
PB.11 Multi-function Pin Selection
PB.10 Multi-function Pin Selection
PB.9 Multi-function Pin Selection
PB.8 Multi-function Pin Selection
[3:0]
PB8MFP
Feb 25, 2019
Page 113 of 274
Rev. 1.01
M031/M032
GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPC_MFPL SYS_BA+0x40 R/W GPIOC Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PC7MFP
PC5MFP
PC3MFP
PC1MFP
PC6MFP
PC4MFP
PC2MFP
PC0MFP
1
0
Bits
Description
PC7MFP
PC6MFP
PC5MFP
PC4MFP
PC3MFP
PC2MFP
PC1MFP
PC0MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PC.7 Multi-function Pin Selection
PC.6 Multi-function Pin Selection
PC.5 Multi-function Pin Selection
PC.4 Multi-function Pin Selection
PC.3 Multi-function Pin Selection
PC.2 Multi-function Pin Selection
PC.1 Multi-function Pin Selection
PC.0 Multi-function Pin Selection
[3:0]
Feb 25, 2019
Page 114 of 274
Rev. 1.01
M031/M032
GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPC_MFPH SYS_BA+0x44 R/W GPIOC High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PC15MFP
PC13MFP
PC11MFP
PC9MFP
PC14MFP
PC12MFP
PC10MFP
PC8MFP
1
0
Bits
Description
PC15MFP
PC14MFP
PC13MFP
PC12MFP
PC11MFP
PC10MFP
PC9MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PC.15 Multi-function Pin Selection
PC.14 Multi-function Pin Selection
PC.13 Multi-function Pin Selection
PC.12 Multi-function Pin Selection
PC.11 Multi-function Pin Selection
PC.10 Multi-function Pin Selection
PC.9 Multi-function Pin Selection
PC.8 Multi-function Pin Selection
[3:0]
PC8MFP
Feb 25, 2019
Page 115 of 274
Rev. 1.01
M031/M032
GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPD_MFPL SYS_BA+0x48 R/W GPIOD Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PD7MFP
PD5MFP
PD3MFP
PD1MFP
PD6MFP
PD4MFP
PD2MFP
PD0MFP
1
0
Bits
Description
PD7MFP
PD6MFP
PD5MFP
PD4MFP
PD3MFP
PD2MFP
PD1MFP
PD0MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PD.7 Multi-function Pin Selection
PD.6 Multi-function Pin Selection
PD.5 Multi-function Pin Selection
PD.4 Multi-function Pin Selection
PD.3 Multi-function Pin Selection
PD.2 Multi-function Pin Selection
PD.1 Multi-function Pin Selection
PD.0 Multi-function Pin Selection
[3:0]
Feb 25, 2019
Page 116 of 274
Rev. 1.01
M031/M032
GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPD_MFPH SYS_BA+0x4C R/W GPIOD High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PD15MFP
PD13MFP
PD11MFP
PD9MFP
PD14MFP
PD12MFP
PD10MFP
PD8MFP
1
0
Bits
Description
PD15MFP
PD14MFP
PD13MFP
PD12MFP
PD11MFP
PD10MFP
PD9MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PD.15 Multi-function Pin Selection
PD.14 Multi-function Pin Selection
PD.13 Multi-function Pin Selection
PD.12 Multi-function Pin Selection
PD.11 Multi-function Pin Selection
PD.10 Multi-function Pin Selection
PD.9 Multi-function Pin Selection
PD.8 Multi-function Pin Selection
[3:0]
PD8MFP
Feb 25, 2019
Page 117 of 274
Rev. 1.01
M031/M032
GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPF_MFPL SYS_BA+0x58 R/W GPIOF Low Byte Multiple Function Control Register
0x0000_00ee
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PF7MFP
PF5MFP
PF3MFP
PF1MFP
PF6MFP
PF4MFP
PF2MFP
PF0MFP
1
0
Bits
Description
PF7MFP
PF6MFP
PF5MFP
PF4MFP
PF3MFP
PF2MFP
PF1MFP
PF0MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PF.7 Multi-function Pin Selection
PF.6 Multi-function Pin Selection
PF.5 Multi-function Pin Selection
PF.4 Multi-function Pin Selection
PF.3 Multi-function Pin Selection
PF.2 Multi-function Pin Selection
PF.1 Multi-function Pin Selection
PF.0 Multi-function Pin Selection
[3:0]
Feb 25, 2019
Page 118 of 274
Rev. 1.01
M031/M032
GPIOF High Byte Multiple Function Control Register (SYS_GPF_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPF_MFPH SYS_BA+0x5C R/W GPIOF High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PF15MFP
PF13MFP
PF11MFP
PF9MFP
PF14MFP
PF12MFP
PF10MFP
PF8MFP
1
0
Bits
Description
PF15MFP
PF14MFP
PF13MFP
PF12MFP
PF11MFP
PF10MFP
PF9MFP
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
PF.15 Multi-function Pin Selection
PF.14 Multi-function Pin Selection
PF.13 Multi-function Pin Selection
PF.12 Multi-function Pin Selection
PF.11 Multi-function Pin Selection
PF.10 Multi-function Pin Selection
PF.9 Multi-function Pin Selection
PF.8 Multi-function Pin Selection
[3:0]
PF8MFP
Feb 25, 2019
Page 119 of 274
Rev. 1.01
M031/M032
Modulation Control Register (SYS_MODCTL)
Register
Offset
R/W
Description
Reset Value
SYS_MODCTL
SYS_BA+0xC0
R/W
Modulation Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
MODPWMSEL
Reserved
MODH
MODEN
Bits
Description
[31:8]
Reserved
Reserved.
PWM0 Channel Select for Modulation
Select the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0.
0000: PWM0 Channel 0 modulate with UART0_TXD.
0001: PWM0 Channel 1 modulate with UART0_TXD.
0010: PWM0 Channel 2 modulate with UART0_TXD.
0011: PWM0 Channel 3 modulete with UART0_TXD.
0100: PWM0 Channel 4 modulete with UART0_TXD.
0101: PWM0 Channel 5 modulete with UART0_TXD.
0110: Reserved.
[7:4]
MODPWMSEL
0111: Reserved.
1000: PWM0 Channel 0 modulate with USCI0_DAT0.
1001: PWM0 Channel 1 modulate with USCI0_DAT0.
1010: PWM0 Channel 2 modulate with USCI0_DAT0.
1011: PWM0 Channel 3 modulete with USCI0_DAT0.
1100: PWM0 Channel 4 modulete with USCI0_DAT0.
1101: PWM0 Channel 5 modulete with USCI0_DAT0.
1110: Reserved.
1111: Reserved.
Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
[3:2]
[1]
Reserved
MODH
Reserved.
Modulation at Data High
Select modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0
0: Modulation pulse at UART0_TXD low or USCI0_DAT0 low.
1: Modulation pulse at UART0_TXD high or USCI0_DAT0 high.
Modulation Function Enable Bit
[0]
MODEN
This bit enables modulation funcion by modulating with PWM0 channel output and
Feb 25, 2019
Page 120 of 274
Rev. 1.01
M031/M032
USCI0(USCI0_DAT0) or UART0(UART0_TXD) output.
0 = Modulation Function Disabled.
1 = Modulation Function Enabled.
Feb 25, 2019
Page 121 of 274
Rev. 1.01
M031/M032
System SRAM BIST Test Control Register (SYS_SRAM_BISTCTL)
Register
Offset
R/W
Description
Reset Value
SYS_SRAM_BIS
TCTL
SYS_BA+0xD0
R/W
System SRAM BIST Test Control Register
0x0000_0000
31
23
15
30
22
14
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
6
2
1
0
PDMABIST
Reserved
USBBIST
Reserved
SRBIST
Bits
Description
Reserved
[31:8]
Reserved.
PDMA BIST Enable Bit (Write Protect)
This bit enables BIST test for PDMA RAM
0 = system PDMA BIST Disabled.
[7]
PDMABIST
Reserved
USBBIST
Reserved
1 = system PDMA BIST Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6:5]
[4]
Reserved.
USB BIST Enable Bit (Write Protect)
This bit enables BIST test for USB RAM
0 = system USB BIST Disabled.
1 = system USB BIST Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3:0]
Reserved.
Feb 25, 2019
Page 122 of 274
Rev. 1.01
M031/M032
System SRAM BIST Test Status Register (SYS_SRAM_BISTSTS)
Register
Offset
R/W
Description
Reset Value
SYS_SRAM_BIS
TSTS
SYS_BA+0xD4
R
System SRAM BIST Test Status Register
0x00xx_00xx
31
30
29
21
13
5
28
20
27
19
11
3
26
25
17
9
24
Reserved
23
PDMAEND
15
22
18
Reserved
10
16
SRBEND
8
Reserved
14
USBBEND
12
Reserved
7
6
4
2
1
0
PDMABISTF
Reserved
USBBEF
Reserved
SRBISTEF
Bits
Description
Reserved
[31:24]
Reserved.
PDMA SRAM BIST Test Finish
0 = PDMA SRAM BIST is active.
1 = PDMA SRAM BIST test finish.
[23]
PDMAEND
Reserved
USBBEND
Reserved
PDMABISTF
Reserved
USBBEF
[22:21]
[20]
Reserved.
USB SRAM BIST Test Finish
0 = USB SRAM BIST is active.
1 = USB SRAM BIST test finish.
[19:8]
[7]
Reserved.
PDMA SRAM BIST Failed Flag
0 = PDMA SRAM BIST pass.
1 = PDMA SRAM BIST failed.
[6:5]
[4]
Reserved.
USB SRAM BIST Fail Flag
0 = USB SRAM BIST test pass.
1 = USB SRAM BIST test fail.
[3:0]
Reserved
Reserved.
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HIRC Trim Control Register (SYS_HIRCTRIMCTL)
Register
Offset
R/W Description
Reset Value
SYS_HIRCTRI
MCTL
SYS_BA+0xF0
R/W HIRC Trim Control Register
0x0008_0000
31
23
15
7
30
29
21
28
20
12
4
27
19
11
3
26
25
17
9
24
16
8
Reserved
22
Reserved
14
18
BOUNDARY
13
Reserved
5
10
REFCKSEL
2
BOUNDEN
1
CESTOPEN
0
6
RETRYCNT
LOOPSEL
Reserved
FREQSEL
Bits
Description
Reserved
[31:21]
Reserved.
Boundary Selection
Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved.
[20:16]
[15:11]
BOUNDARY
Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
Reserved
Reserved.
Reference Clock Selection
0 = HIRC trim reference clock is from LXT (32.768 kHz).
1 = HIRC trim reference clock is from internal USB synchronous mode.
Note1: HIRC trim reference clock supports LXT or internal USB synchronous mode
depending on the chip spec. Please refer to section 4.3 NuMicro® M031/M032 Series
Selection Guide for detailed information.
[10]
REFCKSEL
Note2: If there is no reference clock (LXT or internal USB synchronous mode) when the
rc_trim is enabled, CLKERIF (SYS_HIRCTRIMCTL[2]) will be set to 1.
Boundary Enable Bit
[9]
[8]
BOUNDEN
CESTOPEN
0 = Boundary function Disabled.
1 = Boundary function Enabled.
Clock Error Stop Enable Bit
0 = The trim operation is keep going if clock is inaccuracy.
1 = The trim operation is stopped if clock is inaccuracy.
Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim
value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
[7:6]
RETRYCNT
If the trim value update counter reached this limitation value and frequency of HIRC still
doesn’t lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
00 = Trim retry count limitation is 64 loops.
01 = Trim retry count limitation is 128 loops.
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10 = Trim retry count limitation is 256 loops.
11 = Trim retry count limitation is 512 loops.
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks.
00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
[5:4]
[3:2]
LOOPSEL
Reserved
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value
based on the average frequency difference in 4 clocks of reference clock.
Reserved.
Trim Frequency Selection
This field indicates the target frequency of 48 MHz internal high speed RC oscillator
(HIRC) auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry
limitation count reached, this field will be cleared to 00 automatically.
[1:0]
FREQSEL
00 = Disable HIRC auto trim function.
01 = Enable HIRC auto trim function and trim HIRC to 48 MHz.
10 = Reserved..
11 = Reserved.
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HIRC Trim Interrupt Enable Register (SYS_HIRCTRIMIEN)
Register
Offset
R/W Description
Reset Value
SYS_HIRCTRI
MIEN
SYS_BA+0xF4
R/W HIRC Trim Interrupt Enable Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
2
1
0
Reserved
CLKEIEN
TFALIEN
Reserved
Bits
Description
Reserved
[31:3]
Reserved.
Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim
operation.
[2]
CLKEIEN
If this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim
operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
0 = Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU.
1 = Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU.
Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation
count reached and HIRC frequency still not locked on target frequency set by
FREQSEL(SYS_HIRCTRIMCTL[1:0]).
[1]
[0]
TFALIEN
If this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an
interrupt will be triggered to notify that HIRC trim value update limitation count was
reached.
0 = Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU.
1 = Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU.
Reserved
Reserved.
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HIRC Trim Interrupt Status Register (SYS_HIRCTRIMSTS)
Register
Offset
R/W Description
Reset Value
SYS_HIRCTRI
MSTS
SYS_BA+0xF8
R/W HIRC Trim Interrupt Status Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
2
1
0
Reserved
OVBDIF
CLKERIF
TFAILIF
FREQLOCK
Bits
Description
Reserved
[31:4]
Reserved.
Over Boundary Status
When the over boundary function is set, if there occurs the over boundary condition, this
flag will be set.
[3]
OVBDIF
0 = Over boundary coundition did not occur.
1 = Over boundary coundition occurred.
Note: Write 1 to clear this flag.
Clock Error Interrupt Status
When the frequency relation between reference clock (LXT or USB sync signals) and 48
MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit
will be set and to be an indicate that clock frequency is inaccuracy
Once this bit is set to 1, the auto trim operation stopped and
FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if
CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1.
[2]
CLKERIF
If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to
notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
0 = Clock frequency is accuracy.
1 = Clock frequency is inaccuracy.
Note : reset by powr on reset
Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock
frequency still doesn’t be locked. Once this bit is set, the auto trim operation stopped and
FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_HIRCIEN[1]) is high, an interrupt will be triggered to
notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
[1]
[0]
TFAILIF
0 = Trim value update limitation count does not reach.
1 = Trim value update limitation count reached and HIRC frequency still not locked.
Note : reset by powr on reset
FREQLOCK
HIRC Frequency Lock Status
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This bit indicates the HIRC frequency is locked.
This is a status bit and doesn’t trigger any interrupt
Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the
RC_TRIM is enabled.
0 = The internal high-speed oscillator frequency doesn’t lock at 48 MHz yet.
1 = The internal high-speed oscillator frequency locked at 48 MHz.
Note : Reset by powr on reset.
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Register Lock Control Register (SYS_REGLCTL)
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x4000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
After the protection is disabled, user can check the protection disable bit at address 0x4000_0100 bit0,
1 is protection disable, and 0 is protection enable. Then user can update the target protected register
value and then write any data to the address “0x4000_0100” to enable register protection.
This register is writen to disable/enable register protection and read for the REGLCTL status.
Register
Offset
R/W Description
Reset Value
SYS_REGLCTL SYS_BA+0x100 R/W Register Lock Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
REGLCTL
1
0
Bits
Description
Reserved
[31:8]
Reserved.
Register Lock Control Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the
protected function by writing the sequence value “59h”, “16h”, “88h” to this field. After this
sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can
be normal write.
[7:0]
REGLCTL
REGLCTL[0]
Register Lock Control Disable Index (Read Only)
0 = Write-protection Enabled for writing protected registers. Any write to the protected
register is ignored.
1 = Write-protection Disabled for writing protected registers.
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Analog POR Disable Control Register (SYS_PORDISAN)
Register
Offset
R/W Description
Reset Value
SYS_PORDISA
N
SYS_BA+0x1EC R/W Analog POR Disable Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
POROFFAN
POROFFAN
1
0
Bits
Description
Reserved
[31:16]
Reserved.
Power-on Reset Enable Bit (Write Protect)
After powered on, User can turn off internal analog POR circuit to save power by writing
0x5AA5 to this field.
The analog POR circuit will be active again when this field is set to another value or chip is
reset by other reset source, including:
[15:0]
POROFFAN
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip
reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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6.2.13 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
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6.2.13.1 System Timer Control Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
SYST Base Address:
SCS_BA = 0xE000_E000
SYST_CTRL SCS_BA+0x10
SYST_LOAD SCS_BA+0x14
R/W
R/W
R/W
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
0x0000_0000
0xXXXX_XXXX
0xXXXX_XXXX
SYST_VAL
SCS_BA+0x18
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6.2.13.2 System Timer Control Register Description
SysTick Control and Status Register (SYST_CTRL)
Register
Offset
R/W
Description
Reset Value
SYST_CTRL SCS_BA+0x10
R/W
SysTick Control and Status Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
28
20
27
19
11
3
26
18
10
25
17
9
24
Reserved
16
Reserved
12
COUNTFLAG
8
Reserved
5
4
2
1
0
Reserved
CLKSRC
TICKINT
ENABLE
Bits
Description
Reserved
[31:17]
Reserved.
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register was read.
COUNTFLAG is set by a count transition from 1 to 0.
[16]
COUNTFLAG
COUNTFLAG is cleared on read or by a write to the Current Value register.
[15:3]
[2]
Reserved
CLKSRC
Reserved.
System Tick Clock Source Selection
0 = Clock source is the (optional) external reference clock.
1 = Core clock used for SysTick.
System Tick Interrupt Enabled
0 = Counting down to 0 does not cause the SysTick exception to be pended. Software can
use COUNTFLAG to determine if a count to zero has occurred.
[1]
[0]
TICKINT
ENABLE
1 = Counting down to 0 will cause the SysTick exception to be pended. Clearing the
SysTick current value register by a register write in software will not cause SysTick to be
pended.
System Tick Counter Enabled
0 = Counter Disabled.
1 = Counter will operate in a multi-shot manner.
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SysTick Reload Value Register (SYST_LOAD)
Register
Offset
R/W
Description
Reset Value
SYST_LOAD SCS_BA+0x14
R/W
SysTick Reload Value Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
RELOAD
RELOAD
RELOAD
1
0
Bits
Description
Reserved
[31:24]
[23:0]
Reserved.
System Tick Reload Value
RELOAD
The value to load into the Current Value register when the counter reaches 0.
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SysTick Current Value Register (SYST_VAL)
Register
Offset
R/W Description
Reset Value
SYST_VAL
SCS_BA+0x18
R/W SysTick Current Value Register
0xXXXX_XXXX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
CURRENT
CURRENT
CURRENT
1
0
Bits
Description
Reserved
[31:24]
Reserved.
System Tick Current Value
Current counter value. This is the value of the counter at the time it is sampled. The
counter does not provide read-modify-write protection. The register is write-clear. A
software write of any value will clear the register to 0.
[23:0]
CURRENT
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6.2.14 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and
provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of
the interrupts and most of the system exceptions can be configured to different priority levels. When
an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s
priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will
override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and branch
to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC
will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the
stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the
normal execution. Thus it will take less and deterministic time to process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to pending
ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of
concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to
execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the
higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual”
and “Arm® v6-M Architecture Reference Manual”.
6.2.14.1 Exception Model and System Interrupt Map
Table 6.2-9 lists the exception model supported by the M031 series. Software can set four levels of
priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority
is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-
configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after
three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
3
-2
Hard Fault
Reserved
SVCall
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Reserved
PendSV
12 ~ 13
14
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SysTick
15
Configurable
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-9 Exception Model
Interrupt Number
Vector
Number
Interrupt Name
Interrupt Description
(Bit In Interrupt
Registers)
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-
-
System exceptions
0
BODOUT
WDT_INT
EINT024
Brown-Out low voltage detected interrupt
Watchdog Timer interrupt
External interrupt fromEINT0,2,4.
External interrupt fromEINT1.3.5
External interrupt from PA, PB pin
External interrupt from PC, PB pin
PWM0 interrupt
1
2
3
EINT135
4
GPAB_INT
GPCDEF_INT
PWM0_INT
PWM1_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
SPI0_INT
Reserved
Reserved
Reserved
I2C0_INT
I2C1_INT
Reserved
Reserved
USCI0
5
6
7
PWM1 interrupt
8
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Timer 2 interrupt
Timer 3 interrupt
UART0,2 interrupt
UART1 interrupt
SPI0 interrupt
Reserved
Reserved
Reserved
I2C0 interrupt
I2C1 interrupt
Reserved
Reserved
USCI0 interrupt
USBD_INT
Reserved
ACMP01_INT
PDMA_INT
USB device interrupt
Reserved
ACMP0 and ACMP1 interrupt
PDMA interrupt
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43
44
45
46
47
27
28
29
30
31
Reserved
PWRWU_INT
ADC_INT
CLKFAIL
Reserved
Clock controller interrupt for chip wake-up from power-down state
ADC interrupt
Clock fail detected or IRC Auto Trim interrupt
Reserved
Reserved
Table 6.2-10 Interrupt Number Table
6.2.14.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer
on reset, and the entry point addresses for all exception handlers. The vector number on previous
page defines the order of entries in the vector table associated with exception handler entry as
illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Vector Number
Table 6.2-11 Vector Figure Format
6.2.14.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state
until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.2.14.4 NVIC Control Registers
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
NVIC Base Address:
NVIC_BA = 0xE000_E100
NVIC_ISER0
NVIC_ICER0
NVIC_ISPR0
NVIC_ICPR0
NVIC_IABR0
NVIC_BA+0x000
R/W
R/W
R/W
R/W
R/W
IRQ0 ~ IRQ31 Set-enable Control Register
IRQ0 ~ IRQ31 Clear-enable Control Register
IRQ0 ~ IRQ31 Set-pending Control Register
IRQ0 ~ IRQ31 Clear-pending Control Register
IRQ0 ~ IRQ31 Active Bit Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
NVIC_BA+0x080
NVIC_BA+0x100
NVIC_BA+0x180
NVIC_BA+0x200
NVIC_IPRn
n=0,1..7
0xE000E400
+0x4*n
R/W
R/W
IRQ0 ~ IRQ31 Priority Control Register
Software Trigger Interrupt Registers
0x0000_0000
0x0000_0000
STIR
0xE000EF00
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IRQ0 ~ IRQ31 Set-enable Control Register (NVIC_ISER0)
Register
Offset
R/W Description
Reset Value
NVIC_ISER0 NVIC_BA+0x000 R/W IRQ0 ~ IRQ31 Set-enable Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SETENA
SETENA
SETENA
SETENA
1
0
Bits
Description
SETENA
Interrupt Set Enable Bit
The NVIC_ISER0 registers enable interrupts, and show which interrupts are enabled
Write Operation:
0 = No effect.
[31:0]
1 = Interrupt Enabled.
Read Operation:
0 = Interrupt Disabled.
1 = Interrupt Enabled.
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IRQ0 ~ IRQ31 Clear-enable Control Register (NVIC_ICER0)
Register
Offset
R/W Description
Reset Value
NVIC_ICER0 NVIC_BA+0x080 R/W IRQ0 ~ IRQ31 Clear-enable Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CALENA
CALENA
CALENA
CALENA
1
0
Bits
Description
CALENA
Interrupt Clear Enable Bit
The NVIC_ICER0 registers disable interrupts, and show which interrupts are enabled.
Write Operation:
0 = No effect.
[31:0]
1 = Interrupt Disabled.
Read Operation:
0 = Interrupt Disabled.
1 = Interrupt Enabled.
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IRQ0 ~ IRQ31 Set-pending Control Register (NVIC_ISPR0)
Register
Offset
R/W Description
Reset Value
NVIC_ISPR0 NVIC_BA+0x100 R/W IRQ0 ~ IRQ31 Set-pending Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SETPEND
SETPEND
SETPEND
SETPEND
1
0
Bits
Description
SETPEND
Interrupt Set-pending
The NVIC_ISPR0 registers force interrupts into the pending state, and show which
interrupts are pending
Write Operation:
0 = No effect.
[31:0]
1 = Changes interrupt state to pending.
Read Operation:
0 = Interrupt is not pending.
1 = Interrupt is pending.
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IRQ0 ~ IRQ31 Clear-pending Control Register (NVIC_ICPR0)
Register
Offset
R/W Description
Reset Value
NVIC_ICPR0 NVIC_BA+0x180 R/W IRQ0 ~ IRQ31 Clear-pending Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
CALPEND
CALPEND
CALPEND
CALPEND
1
0
Bits
Description
CALPEND
Interrupt Clear-pending
The NVIC_ICPR0 registers remove the pending state from interrupts, and show which
interrupts are pending
Write Operation:
0 = No effect.
[31:0]
1 = Removes pending state an interrupt.
Read Operation:
0 = Interrupt is not pending.
1 = Interrupt is pending.
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IRQ0 ~ IRQ31 Active Bit Register (NVIC_IABR0)
Register
Offset
R/W Description
Reset Value
NVIC_IABR0 NVIC_BA+0x200 R/W IRQ0 ~ IRQ31 Active Bit Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1
0
Bits
Description
ACTIVE
Interrupt Active Flags
The NVIC_IABR0 registers indicate which interrupts are active.
0 = interrupt not active.
[31:0]
1 = interrupt active.
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IRQ0 ~ IRQ31 Interrupt Priority Register (NVIC_IPRn)
Register
Offset
R/W Description
Reset Value
NVIC_IPRn
n=0,1..7
0xE000E400
+0x4*n
R/W IRQ0 ~ IRQ31 Priority Control Register
0x0000_0000
31
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_4n_3
Reserved
Reserved
Reserved
Reserved
23
15
7
PRI_4n_2
14
6
PRI_4n_1
PRI_4n_0
1
0
Bits
Description
PRI_4n_3
Reserved
PRI_4n_2
Reserved
PRI_4n_1
Reserved
PRI_4n_0
Reserved
Priority of IRQ_4n+3
[31:30]
[29:24]
[23:22]
[21:16]
[15:14]
[13:8]
[7:6]
“0” denotes the highest priority and “3” denotes the lowest priority
Reserved.
Priority of IRQ_4n+2
“0” denotes the highest priority and “3” denotes the lowest priority
Reserved.
Priority of IRQ_4n+1
“0” denotes the highest priority and “3” denotes the lowest priority
Reserved.
Priority of IRQ_4n+0
“0” denotes the highest priority and “3” denotes the lowest priority
[5:0]
Reserved.
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Software Trigger Interrupt Register (STIR)
Register
STIR
Offset
R/W Description
Reset Value
0xE000EF00
R/W Software Trigger Interrupt Registers
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
8
INTID
0
Reserved
4
1
INTID
Bits
Description
Reserved
[31:9]
Reserved.
Interrupt ID
Write to the STIR To Generate An Interrupt from Software
When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access
the STIR
[8:0]
INTID
Interrupt ID of the interrupt to trigger, in the range 0-31. For example, a value of 0x03
specifies interrupt IRQ3.
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6.2.14.5 NMI Control Registers
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
NMI Base Address:
NMI_BA = 0x4000_0300
NMIEN
NMI_BA+0x00
NMI_BA+0x04
R/W NMI Source Interrupt Enable Register
0x0000_0000
0x0000_0000
NMISTS
R
NMI Source Interrupt Status Register
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NMI Source Interrupt Enable Register (NMIEN)
Register
NMIEN
Offset
R/W Description
Reset Value
NMI_BA+0x00
R/W NMI Source Interrupt Enable Register
0x0000_0000
31
23
30
22
29
21
28
20
27
19
26
18
25
17
24
16
Reserved
Reserved
15
UART1_INT
7
14
UART0_INT
6
13
EINT5
5
12
EINT4
4
11
EINT3
3
10
EINT2
9
EINT1
1
8
EINT0
0
2
Reserved
CLKFAIL
Reserved
PWRWU_INT
IRC_INT
BODOUT
Bits
Description
Reserved
[31:16]
Reserved.
UART1 NMI Source Enable (Write Protect)
0 = UART1 NMI source Disabled.
[15]
[14]
[13]
[12]
[11]
UART1_INT
UART0_INT
EINT5
1 = UART1 NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
UART0 NMI Source Enable (Write Protect)
0 = UART0 NMI source Disabled.
1 = UART0 NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
External Interrupt From PB.7 or PF.14 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PB.7 or PF.14 pin NMI source Disabled.
1 = External interrupt from PB.7 or PF.14 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled.
1 = External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
EINT4
External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PB.2 or PC.7 pin NMI source Disabled.
1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
EINT3
External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled.
1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[10]
[9]
EINT2
EINT1
External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect)
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0 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled.
1 = External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PA.6 or PB.5 pin NMI source Disabled.
1 = External interrupt from PA.6 or PB.5 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8]
EINT0
[7:5]
[4]
Reserved
CLKFAIL
Reserved
PWRWU_INT
Reserved.
Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)
0 = Clock fail detected and IRC Auto Trim interrupt NMI source Disabled.
1 = Clock fail detected and IRC Auto Trim interrupt NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3]
Reserved.
Power-down Mode Wake-up NMI Source Enable (Write Protect)
0 = Power-down mode wake-up NMI source Disabled.
[2]
1 = Power-down mode wake-up NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
IRC TRIM NMI Source Enable (Write Protect)
0 = IRC TRIM NMI source Disabled.
[1]
[0]
IRC_INT
1 = IRC TRIM NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
BOD NMI Source Enable (Write Protect)
0 = BOD NMI source Disabled.
BODOUT
1 = BOD NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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NMI Source Interrupt Status Register (NMISTS)
Register
NMISTS
Offset
R/W Description
NMI Source Interrupt Status Register
Reset Value
NMI_BA+0x04
R
0x0000_0000
31
23
30
22
29
21
13
28
20
27
19
26
18
25
17
24
16
Reserved
Reserved
15
UART1_INT
7
14
UART0_INT
6
12
EINT4
4
11
EINT3
3
10
EINT2
9
EINT1
1
8
EINT0
0
EINT5
5
2
Reserved
CLKFAIL
Reserved
PWRWU_INT
IRC_INT
BODOUT
Bits
Description
Reserved
[31:16]
Reserved.
UART1 Interrupt Flag (Read Only)
0 = UART1 interrupt is deasserted.
1 = UART1 interrupt is asserted.
[15]
[14]
[13]
[12]
[11]
[10]
[9]
UART1_INT
UART0_INT
EINT5
UART0 Interrupt Flag (Read Only)
0 = UART1 interrupt is deasserted.
1 = UART1 interrupt is asserted.
External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PB.7 or PF.14 interrupt is deasserted.
1 = External Interrupt from PB.7 or PF.14 interrupt is asserted.
External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted.
1 = External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted.
EINT4
External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted.
1 = External Interrupt from PB.2 or PC.7 interrupt is asserted.
EINT3
External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted.
1 = External Interrupt from PB.3 or PC.6 interrupt is asserted.
EINT2
External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted.
1 = External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted.
EINT1
External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PA.6 or PB.5 interrupt is deasserted.
1 = External Interrupt from PA.6 or PB.5 interrupt is asserted.
[8]
EINT0
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[7:5]
[4]
Reserved
CLKFAIL
Reserved.
Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)
0 = Clock fail detected or IRC Auto Trim interrupt is deasserted.
1 = Clock fail detected or IRC Auto Trim interrupt is asserted.
[3]
Reserved
PWRWU_INT
Reserved.
Power-down Mode Wake-up Interrupt Flag (Read Only)
0 = Power-down mode wake-up interrupt is deasserted.
1 = Power-down mode wake-up interrupt is asserted.
[2]
IRC TRIM Interrupt Flag (Read Only)
0 = HIRC TRIM interrupt is deasserted.
1 = HIRC TRIM interrupt is asserted.
[1]
[0]
IRC_INT
BOD Interrupt Flag (Read Only)
0 = BOD interrupt is deasserted.
1 = BOD interrupt is asserted.
BODOUT
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6.2.15 System Control Register
The Cortex® -M0 status and operation mode control are managed by System Control Registers.
Including CPUID, Cortex® -M0 interrupt priority and Cortex® -M0 power management can be controlled
through these system control registers.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference Manual” and
“Arm® v6-M Architecture Reference Manual”.
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
SCR Base Address:
SCS_BA = 0xE000_E000
ICSR
SCS_BA+0xD04
SCS_BA+0xD08
R/W Interrupt Control and State Register
R/W Vector Table Offset Register
0x0000_0000
0x0000_0000
0xFA05_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
VTOR
AIRCR
SCR
SCS_BA+0xD0C R/W Application Interrupt and Reset Control Register
SCS_BA+0xD10
SCS_BA+0xD18
R/W System Control Register
SHPR1
SHPR2
SHPR3
R/W System Handler Priority Register 1
SCS_BA+0xD1C R/W System Handler Priority Register 2
SCS_BA+0xD20
R/W System Handler Priority Register 3
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Interrupt Control State Register (ICSR)
Register
ICSR
Offset
R/W Description
Reset Value
SCS_BA+0xD04
R/W Interrupt Control and State Register
0x0000_0000
31
NMIPENDSET
23
30
29
21
13
28
27
26
25
24
Reserved
PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR
Reserved
16
22
20
12
4
19
18
10
2
17
ISRPREEMPT ISRPENDING
Reserved
VECTPENDING
15
14
11
9
Reserved
1
8
VECTPENDING
RETTOBASE
3
7
6
5
0
Reserved
VECTACTIVE
Bits
Description
NMI Set-pending Bit
Write Operation:
0 = No effect.
1 = Changes NMI exception state to pending.
Read Operation:
[31]
NMIPENDSET
0 = NMI exception is not pending.
1 = NMI exception is pending.
Note: Because NMI is the highest-priority exception, normally the processor enters the
NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler
then clears this bit to 0. This means a read of this bit by the NMI exception handler returns
1 only if the NMI signal is reasserted while the processor is executing that handler.
[30:29]
Reserved
Reserved.
PendSV Set-pending Bit
Write Operation:
0 = No effect.
1 = Changes PendSV exception state to pending.
Read Operation:
[28]
PENDSVSET
0 = PendSV exception is not pending.
1 = PendSV exception is pending.
Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
PendSV Clear-pending Bit
Write Operation:
0 = No effect.
[27]
PENDSVCLR
1 = Removes the pending state from the PendSV exception.
Note: This is a write only bit. To clear the PENDSV bit, you must “write 0 to PENDSVSET
and write 1 to PENDSVRTC_CAL” at the same time.
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SysTick Exception Set-pending Bit
Write Operation:
0 = No effect.
[26]
PENDSTSET
1 = Changes SysTick exception state to pending.
Read Operation:
0 = SysTick exception is not pending.
1 = SysTick exception is pending.
SysTick Exception Clear-pending Bit
Write Operation:
0 = No effect.
[25]
PENDSTCLR
1 = Removes the pending state from the SysTick exception.
Note: This is a write only bit. To clear the PENDST bit, you must “write 0 to PENDSTSET
and write 1 to PENDSTRTC_CAL” at the same time.
[24]
[23]
Reserved
Reserved.
Interrupt Preempt Bit (Read Only)
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state.
Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
0 = Interrupt not pending.
[22]
ISRPENDING
Reserved
1 = Interrupt pending.
[21:18]
Reserved.
Number of the Highest Pended Exception
Indicate the Exception Number of the Highest Priority Pending Enabled Exception
0 = no pending exceptions.
[17:12]
VECTPENDING
RETTOBASE
Nonzero = the exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK
registers, but not any effect of the PRIMASK register.
Preempted Active Exceptions Indicator
Indicate whether There are Preempted Active Exceptions
0 = there are preempted active exceptions to execute.
[11]
1 = there are no active exceptions, or the currently-executing exception is the only active
exception.
[10:6]
[5:0]
Reserved
Reserved.
Number of the Current Active Exception
0 = Thread mode.
VECTACTIVE
Non-zero = The exception number of the currently active exception.
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Vector Table Offset Register (VTOR)
Register
VTOR
Offset
R/W Description
Reset Value
SCS_BA+0xD08
R/W Vector Table Offset Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
TBLOFF
TBLOFF
TBLOFF
1
0
TBLOFF
Reserved
Bits
Description
TBLOFF
Table Offset Bits
[31:7]
[6:0]
The vector table address for the selected Security state.
Reserved
Reserved.
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Application Interrupt and Reset Control Register (AIRCR)
Register
AIRCR
Offset
R/W Description
Reset Value
SCS_BA+0xD0C R/W Application Interrupt and Reset Control Register
0xFA05_0000
31
23
30
22
14
6
29
21
13
5
28
27
19
26
18
10
2
25
17
9
24
16
8
VECTORKEY
20
12
4
VECTORKEY
15
11
ENDIANNESS
7
Reserved
PRIGROUP
1
3
0
Reserved
SYSRESETRE VECTCLRAC VECTRESET
Bits
Description
Register Access Key
When writing this register, this field should be 0x05FA, otherwise the write action will be
unpredictable.
[31:16]
VECTORKEY
The VECTORKEY filed is used to prevent accidental write to this register from resetting
the system or clearing of the exception status.
Data Endianness
0 = Little-endian.
1 = Big-endian.
[15]
ENDIANNESS
[14:11]
[10:8]
[7:3]
Reserved
PRIGROUP
Reserved
Reserved.
Interrupt Priority Grouping
This field determines the Split Of Group priority from subpriority,
Reserved.
System Reset Request
Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate
A Reset Is Requested
[2]
SYSRESETREQ
This bit is write only and self-cleared as part of the reset sequence.
Exception Active Status Clear Bit
Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable
Exceptions
[1]
[0]
VECTCLRACTIVE
VECTRESET
This bit is write only and can only be written when the core is halted.
Note: It is the debugger’s responsibility to re-initialize the stack.
Reserved.
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Group
Number
Priorities
Of
Group
PRIGROUP
Binary Point
Subpriority Bits
Subpriorities
Priority Bits
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
bxxxxxxx.y
bxxxxxx.yy
bxxxxx.yyy
bxxxx.yyyy
bxxx.yyyyy
bxx.yyyyyy
bx.yyyyyyy
b.yyyyyyyy
[7:1]
[7:2]
[7:3]
[7:4]
[7:5]
[7:6]
[7]
[0]
128
64
32
16
8
2
[1:0]
[2:0]
[3;0]
[4:0]
[5:0]
[6:0]
[7:0]
4
8
16
32
64
128
256
4
2
None
1
Table 6.2-12 Priority Grouping
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System Control Register (SCR)
Register
SCR
Offset
R/W
Description
Reset Value
SCS_BA+0xD10
R/W
System Control Register
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
6
3
1
0
Reserved
SEVONPEND
Reserved
SLEEPDEEP SLEEPONEXI
Reserved
Bits
Description
Reserved
[31:5]
Reserved.
Send Event on Pending
0 = Only enabled interrupts or events can wake up the processor, while disabled interrupts
are excluded.
1 = Enabled events and all interrupts, including disabled interrupts, can wake up the
processor.
[4]
SEVONPEND
When an event or interrupt enters pending state, the event signal wakes up the processor
from WFE. If the processor is not waiting for an event, the event is registered and affects
the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
[3]
[2]
Reserved
Reserved.
Processor Deep Sleep and Sleep Mode Selection
Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
SLEEPDEEP
0 = Sleep.
1 = Deep sleep.
Sleep-on-exit Enable Control
This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.
0 = Do not sleep when returning to Thread mode.
[1]
[0]
SLEEPONEXIT
Reserved
1 = Enters sleep, or deep sleep, on return from an ISR to Thread mode.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty
main application.
Reserved.
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System Handler Priority Register 1 (SHPR1)
Register
SHPR1
Offset
R/W
Description
Reset Value
SCS_BA+0xD18 R/W
System Handler Priority Register 1
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
PRI_6
PRI_5
1
0
PRI_4
Bits
Description
[31:24]
[23:16]
[15:8]
[7:0]
Reserved
PRI_6
Reserved.
Priority of system handler 6, UsageFault
Priority of system handler 5, BusFault
Priority of system handler 4, MemManage
PRI_5
PRI_4
Feb 25, 2019
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System Handler Priority Register 2 (SHPR2)
Register
SHPR2
Offset
R/W Description
Reset Value
SCS_BA+0xD1C R/W System Handler Priority Register 2
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_11
Reserved
Reserved
Reserved
Reserved
1
0
Bits
Description
PRI_11
Priority of System Handler 11 – SVCall
[31:30]
[29:0]
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved
Reserved.
Feb 25, 2019
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System Handler Priority Register 3 (SHPR3)
Register
SHPR3
Offset
R/W Description
Reset Value
SCS_BA+0xD20
R/W System Handler Priority Register 3
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PRI_15
Reserved
Reserved
22
14
6
PRI_14
Reserved
Reserved
1
0
Bits
Description
PRI_15
Priority of System Handler 15 – SysTick
[31:30]
[29:24]
[23:22]
“0” denotes the highest priority and “3” denotes the lowest priority.
Reserved
PRI_14
Reserved.
Priority of System Handler 14 – PendSV
“0” denotes the highest priority and “3” denotes the lowest priority.
Feb 25, 2019
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M0 core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~32
MHz external high speed crystal (HXT) and 48 MHz internal high speed RC oscillator (HIRC) to
reduce the overall system power consumption
Feb 25, 2019
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HIRC
HXT
LXT
LIRC
48MHz
4~32MHz
32.768 kHz
38.4 kHz
HIRC
1/4
PCLK0
PCLK1
ACMP
1
0
PLLFOUT
/1,/2,/4,/8,/16
I2C0
PWM0
TMR0
TMR1
UART0
UART2
USBD
USCI0
WDT
PLL FOUT
HXT
ADC
I2C1
CPU
CRC
EBI
CLK_PLLCTL[19]
PWM1
SPI0
FMC
PDMA
SRAM
HDIV
HIRC
111
011
010
001
000
TMR2
TMR3
UART1
LIRC
PLLFOUT
HCLK
1/(HCLKDIV+1)
LXT
HXT
/1,/2,/4,/8,/16
LIRC
CLK_CLKSEL0[2:0]
101
100
011
010
001
000
LIRC
PCLK0/PCLK1
HIRC
11
10
01
UART0
1/(UART0DIV+1)
1/(UART1DIV+1)
1/(UART2DIV+1)
HCLK
1/2048
LXT
WDT
UART1
UART2
LXT
PLLOUT
HXT
CLK_CLKSEL1[1:0]
LIRC
CLK_CLKSEL1[26:24]
CLK_CLKSEL1[30:28]
CLK_CLKSEL3[26:24]
11
10
WWDT
HCLK
1/2048
USBDSEL
(CLK_CLKSEL0[8])
CLK_CLKSEL1[3:2]
HIRC
48MHz
0
1
USB1.1 Device
Controller
HIRC
1/2
111
011
010
001
000
PLLFOUT
/(USBDIV + 1)
CPUCLK
HCLK
1/2
1
0
SysTick
HXT
1/2
LXT
HIRC
PCLK1
PLLFOUT
HXT
11
10
01
00
SYST_CTRL[2]
HXT
1/(ADCDIV + 1)
ADC
CLK_CLKSEL0[5:3]
DIV1EN
(CLK_CLKOCTL[5])
ADCSEL
(CLKSEL2[21:20])
PLLFOUT
HIRC
110
101
100
LIRC
/2(CLK_CLKOCTL[3:0]+1)
HIRC
CLKO
0
1
HIRC
HCLK
LXT
11
011
010
001
PCLK1
10
01
00
1/(SPI0_CLKDIV[8:0]+1)
SPI0
PLLFOUT
HXT
HXT
000
CLK_CLKSEL1[6:4]
CLK_CLKSEL2[5:4]
PCLK0
1
0
PWM 0
PCLK1
PLLFOUT
1
0
PWM 1
PLLFOUT
CLK_CLKSEL2[0]
CLK_CLKSEL2[1]
HIRC
HIRC
LIRC
111
101
011
010
001
000
111
101
011
010
001
000
LIRC
TM0/TM1
TM2/TM3
TMR0
TMR1
TMR2
TMR3
PCLK0
LXT
PCLK1
LXT
HXT
HXT
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1[22:20]
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
Figure 6.3-1 Clock Generator Global View Diagram
Feb 25, 2019
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6.3.2
Clock Generator
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~32 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~32 MHz external high speed crystal (HXT) or 48 MHz internal high speed
oscillator (HIRC/4)
48 MHz internal high speed RC oscillator (HIRC)
38.4 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
LXT
(LXT)
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~32
PLLSRC (CLK_PLLCTL[19])
MHz Crystal
(HXT)
XT1_OUT
0
1
HIRCEN (CLK_PWRCTL[2])
PLL FOUT
PLL
/4
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRCEN (CLK_PWRCTL[3])
Internal 38.4
kHz Oscillator
(LIRC)
LIRC
Figure 6.3-2 Clock Generator Block Diagram
Feb 25, 2019
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.3-3
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIEN (CLK_CLKDCTL[5]) is
set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Figure 6.3-5 SysTick Clock Control Block Diagram
Peripherals Clock
6.3.4
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSELx register description in 6.3.9.
6.3.5
Power-down Mode Clock
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When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 38.4 kHz internal low speed RC oscillator (LIRC) clock
– 32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0
to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.
CLKOEN
Enable
(CLK_CLKOCTL[4])
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
PLL
110
0000
0001
:
LIRC
HIRC
100
011
010
001
000
16 to 1
MUX
CLKO
0
1
:
1110
HCLK
LXT
1111
HXT
CLKOSEL (CLK_CLKSEL1[6:4])
Figure 6.3-6 Clock Output Block Diagram
6.3.7
USB Clock Source
The clock source of USB 1.0 is generated from 48 Mhz HIRC or programmable PLL output. The
generated clocks are shown in Figure 6.3-7.
USBDIV is the clock divider output frequency, the output formula is
(PLLFOUT frequency) / (USBDIV + 1).
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PLLFOUT
/(USBDIV + 1)
1
0
USB1.1 Device
Controller
HIRC48M
USBDSEL
Figure 6.3-7 USB Clock Source
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6.3.8
Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
CLK Base Address:
CLK_BA = 0x4000_0200
CLK_PWRCTL
CLK_AHBCLK
CLK_APBCLK0
CLK_APBCLK1
CLK_CLKSEL0
CLK_CLKSEL1
CLK_CLKSEL2
CLK_CLKSEL3
CLK_CLKDIV0
CLK_CLKDIV4
CLK_PCLKDIV
CLK_PLLCTL
CLK_STATUS
CLK_CLKOCTL
CLK_CLKDCTL
CLK_CLKDSTS
CLK_CDUPB
CLK_BA+0x00 R/W System Power-down Control Register
CLK_BA+0x04 R/W AHB Devices Clock Enable Control Register
CLK_BA+0x08 R/W APB Devices Clock Enable Control Register 0
CLK_BA+0x0C R/W APB Devices Clock Enable Control Register 1
CLK_BA+0x10 R/W Clock Source Select Control Register 0
CLK_BA+0x14 R/W Clock Source Select Control Register 1
CLK_BA+0x18 R/W Clock Source Select Control Register 2
CLK_BA+0x1C R/W Clock Source Select Control Register 3
CLK_BA+0x20 R/W Clock Divider Number Register 0
CLK_BA+0x30 R/W Clock Divider Number Register 4
CLK_BA+0x34 R/W APB Clock Divider Register
0x0231_001X
0x0000_0004
0x0000_0001
0x0000_0000
0x0000_003F
0x4477_773B
0x0020_0023
0x0400_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0005_C25E
0x0000_00XX
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
CLK_BA+0x40 R/W PLL Control Register
CLK_BA+0x50 R
Clock Status Monitor Register
CLK_BA+0x60 R/W Clock Output Control Register
CLK_BA+0x70 R/W Clock Fail Detector Control Register
CLK_BA+0x74 R/W Clock Fail Detector Status Register
CLK_BA+0x78 R/W Clock Frequency Range Detector Upper Boundary Register
CLK_BA+0x7c R/W Clock Frequency Range Detector Lower Boundary Register
CLK_BA+0x80 R/W LDO Control Register
CLK_CDLOWB
CLK_LDOCTL
CLK_HXTFSEL
CLK_BA+0xB4 R/W HXT Filter Select Control Register
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6.3.9
Register Description
System Power-down Control Register (CLK_PWRCTL)
Register
Offset
R/W Description
Reset Value
CLK_PWRCTL CLK_BA+0x00
R/W System Power-down Control Register
0x0231_001X
31
30
22
14
29
Reserved
21
28
20
12
4
27
19
11
26
18
10
2
25
17
9
24
LXTSELXT
16
LXTGAIN
Reserved
23
Reserved
15
HXTGAIN
13
8
Reserved
7
6
5
3
1
0
PDEN
PDWKIF
PDWKIEN
PDWKDLY
LIRCEN
HIRCEN
LXTEN
HXTEN
Bits
Description
Reserved
[31:27]
Reserved.
LXT Gain Control Bit (Write Protect)
00 = LXT Crystal ESR = 35K, CL=12.5pF
10 = LXT Crystal ESR = 70K, CL=12.5pF
[26:25]
LXTGAIN
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
LXT Mode Selection
0 = LXT work as crystal mode. PF.4 and PF.5 are configured as external low speed crystal
(LXT) pins.
[24]
LXTSELXT
1 = LXT work as external clock mode. PF.5 is configured as external clock input pin.
Note1: When LXTSELXT = 1, PF.5 MFP should be setting as GPIO mode. The DC
characteristic of X32_IN is the same as GPIO.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
HXT Gain Control Bit (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If
gain control is enabled, crystal will consume more power than gain control off.
000 = HXT frequency is lower than from 4 MHz.
001 = HXT frequency is from 4 MHz to 8 MHz.
010 = HXT frequency is from 8 MHz to 12 MHz.
011 = HXT frequency is from 12 MHz to 16 MHz.
100 = HXT frequency is from 16 MHz to 24 MHz.
111 = HXT frequency is from 24 MHz to 32 MHz.
Others: Reserved
[22:20]
HXTGAIN
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[19:8]
[7]
Reserved
PDEN
Reserved.
System Power-down Enable (Write Protect)
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When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU
sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set
this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC
are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock
source selection. The clocks of peripheral are not controlled by Power-down mode, if the
peripheral clock source is from LXT or LIRC.
0 = Chip operating normally or chip in idle mode because of WFI command.
1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Power-down Mode Wake-up Interrupt Status
Set by “Power-down wake-up event”, it indicates that resume from Power-down mode”
The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up
Sources chapter.
[6]
[5]
PDWKIF
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
0 = Power-down mode wake-up interrupt Disabled.
PDWKIEN
1 = Power-down mode wake-up interrupt Enabled.
Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
Enable the Wake-up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock
cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip works at external high speed
crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC
oscillator (HIRC).
[4]
PDWKDLY
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
LIRC Enable Bit (Write Protect)
0 = Internal low speed RC oscillator (LIRC) Disabled.
1 = Internal low speed RC oscillator (LIRC) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3]
[2]
LIRCEN
HIRCEN
HIRC Enable Bit (Write Protect)
0 = Internal high speed RC oscillator (HIRC) Disabled.
1 = Internal high speed RC oscillator (HIRC) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
LXT Enable Bit (Write Protect)
0 = External low speed crystal (LXT) Disabled.
1 = External low speed crystal (LXT) Enabled.
Note1 : reset by power on reset
[1]
[0]
LXTEN
HXTEN
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
HXT Enable Bit (Write Protect)
0 = Eexternal high speed crystal (HXT) Disabled.
1 = External high speed crystal (HXT) Enabled.
Note1 : reset by power on reset
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Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
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AHB Devices Clock Enable Control Register (CLK_AHBCLK)
The bits in this register are used to enable/disable clock for system clock, AHB bus devices clock.
Register
Offset
R/W Description
Reset Value
CLK_AHBCLK CLK_BA+0x04
R/W AHB Devices Clock Enable Control Register
0x0000_0004
31
23
15
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
4
2
1
0
CRCCKEN
Reserved
EBICKEN
ISPCKEN
PDMACKEN
Reserved
HDIV_EN
Bits
Description
Reserved
Reserved
Reserved
[31:21]
[20]
Reserved.
Reserved.
[19:8]
CRC Generator Controller Clock Enable Bit
0 = CRC peripheral clock Disabled.
1 = CRC peripheral clock Enabled.
[7]
CRCCKEN
Reserved
HDIV_EN
[6:5]
[4]
Reserved.
Divider Controller Clock Enable Control
0 = Divider controller peripheral clock Disabled.
1 = Divider controller peripheral clock Enabled.
EBI Controller Clock Enable Bit
0 = EBI peripheral clock Disabled.
1 = EBI peripheral clock Enabled.
[3]
[2]
EBICKEN
ISPCKEN
Flash ISP Controller Clock Enable Bit
0 = Flash ISP peripheral clock Disabled.
1 = Flash ISP peripheral clock Enabled.
PDMA Controller Clock Enable Bit
0 = PDMA peripheral clock Disabled.
1 = PDMA peripheral clock Enabled.
[1]
[0]
PDMACKEN
Reserved
Reserved.
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APB Devices Clock Enable Control Register 0 (CLK_APBCLK0)
The bits in this register are used to enable/disable clock for peripheral controller clocks.
Register
Offset
R/W Description
Reset Value
CLK_APBCLK0 CLK_BA+0x08 R/W APB Devices Clock Enable Control Register 0
0x0000_0001
31
23
15
7
30
Reserved
22
29
28
ADCCKEN
20
27
USBDCKEN
19
26
18
25
Reserved
17
24
16
21
Reserved
13
UART2CKEN UART1CKEN UART0CKEN
14
12
11
Reserved
3
10
9
8
Reserved
SPI0CKEN
5
I2C1CKEN
1
I2C0CKEN
0
6
4
2
ACMP01CKE CLKOCKEN TMR3CKEN
TMR2CKEN
TMR1CKEN
TMR0CKEN
Reserved
WDTCKEN
Bits
Description
Reserved
[31:29]
Reserved.
Analog-digital-converter (ADC) Clock Enable Bit
0 = ADC clock Disabled.
[28]
ADCCKEN
1 = ADC clock Enabled.
USB Device Clock Enable Bit
0 = USB Device clock Disabled.
1 = USB Device clock Enabled.
[27]
USBDCKEN
Reserved
[26:19]
[18]
Reserved.
UART2 Clock Enable Bit
0 = UART2 clock Disabled.
1 = UART2 clock Enabled.
UART2CKEN
UART1 Clock Enable Bit
0 = UART1 clock Disabled.
1 = UART1 clock Enabled.
[17]
UART1CKEN
UART0 Clock Enable Bit
0 = UART0 clock Disabled.
1 = UART0 clock Enabled.
[16]
UART0CKEN
Reserved
[15:14]
[13]
Reserved.
SPI0 Clock Enable Bit
0 = SPI0 clock Disabled.
1 = SPI0 clock Enabled.
SPI0CKEN
[12:10]
[9]
Reserved
Reserved.
I2C1CKEN
I2C1 Clock Enable Bit
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0 = I2C1 clock Disabled.
1 = I2C1 clock Enabled.
I2C0 Clock Enable Bit
0 = I2C0 clock Disabled.
1 = I2C0 clock Enabled.
[8]
[7]
[6]
[5]
[4]
[3]
I2C0CKEN
Analog Comparator 0/1 Clock Enable Bit
0 = Analog comparator 0/1 clock Disabled.
1 = Analog comparator 0/1 clock Enabled.
ACMP01CKEN
CLKOCKEN
TMR3CKEN
TMR2CKEN
TMR1CKEN
CLKO Clock Enable Bit
0 = CLKO clock Disabled.
1 = CLKO clock Enabled.
Timer3 Clock Enable Bit
0 = Timer3 clock Disabled.
1 = Timer3 clock Enabled.
Timer2 Clock Enable Bit
0 = Timer2 clock Disabled.
1 = Timer2 clock Enabled.
Timer1 Clock Enable Bit
0 = Timer1 clock Disabled.
1 = Timer1 clock Enabled.
Timer0 Clock Enable Bit
0 = Timer0 clock Disabled.
1 = Timer0 clock Enabled.
[2]
[1]
TMR0CKEN
Reserved
Reserved.
Watchdog Timer Clock Enable Bit (Write Protect)
0 = Watchdog timer clock Disabled.
[0]
WDTCKEN
1 = Watchdog timer clock Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note: This bit is reset by power on reset, Watchdog reset or software chip reset.
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APB Devices Clock Enable Control Register 1 (CLK_APBCLK1)
The bits in this register are used to enable/disable clock for peripheral controller clocks.
Register
Offset
R/W Description
Reset Value
CLK_APBCLK1 CLK_BA+0x0C R/W APB Devices Clock Enable Control Register 1
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
24
16
Reserved
Reserved
PWM1CKEN PWM0CKEN
9
8
Reserved
4
USCI0CKEN
0
1
Reserved
Bits
Description
Reserved
[31:18]
Reserved.
PWM1 Clock Enable Bit
0 = PWM1 clock Disabled.
1 = PWM1 clock Enabled.
[17]
PWM1CKEN
PWM0 Clock Enable Bit
0 = PWM0 clock Disabled.
1 = PWM0 clock Enabled.
[16]
[15:9]
[8]
PWM0CKEN
Reserved
Reserved.
USCI0 Clock Enable Bit
0 = USCI0 clock Disabled.
1 = USCI0 clock Enabled.
USCI0CKEN
Reserved
[7:0]
Reserved.
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Clock Source Select Control Register 0 (CLK_CLKSEL0)
Register
Offset
R/W Description
Reset Value
CLK_CLKSEL0 CLK_BA+0x10 R/W Clock Source Select Control Register 0
0x0000_003F
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
8
USBDSEL
0
Reserved
4
1
Reserved
STCLKSEL
HCLKSEL
Bits
Description
Reserved
[31:9]
Reserved.
USB Device Clock Source Selection (Write Protect)
These bits are protected bit. It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x4000_0100 to disable register protection. Refer to the register
REGWRPROT at address GCR_BA+0x100.
[8]
USBDSEL
Reserved
0 = Clock source from HIRC.
1 = Clock source from PLL divided.
Note: If the PLL function is not supported, the clock source will be fixed at HIRC. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[7:6]
Reserved.
Cortex® -M0 SysTick Clock Source Selection (Write Protect)
If SYST_CTRL[2]=0, SysTick uses listed clock source below.
000 = Clock source from HXT.
001 = Clock source from LXT.
010 = Clock source from HXT/2.
011 = Clock source from HCLK/2.
[5:3]
STCLKSEL
111 = Clock source from HIRC/2.
Other = Reserved.
Note: if SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick clock
source must less than or equal to HCLK/2.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be
turned on.
[2:0]
HCLKSEL
000 = Clock source from HXT.
001 = Clock source from LXT.
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010 = Clock source from PLL.
011 = Clock source from LIRC.
111= Clock source from HIRC.
Other = Reserved.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note : reset by power on reset
Note: If the PLL function is not supported, the clock source will be fixed at HIRC. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Note: If the LXT function is not supported, the clock source will be kept previous clock
selection. Please refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for
detailed information.
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Clock Source Select Control Register 1 (CLK_CLKSEL1)
Before clock switching, the related clock sources (pre-selected and newly-selected) must be turned
on.
Register
Offset
R/W Description
Reset Value
CLK_CLKSEL1 CLK_BA+0x14 R/W Clock Source Select Control Register 1
0x4477_773B
31
Reserved
23
30
22
14
6
29
UART1SEL
21
28
20
12
4
27
Reserved
19
26
18
10
2
25
24
16
8
UART0SEL
17
Reserved
15
TMR3SEL
13
Reserved
11
TMR2SEL
9
TMR0SEL
1
Reserved
7
TMR1SEL
5
Reserved
3
0
Reserved
CLKOSEL
WWDTSEL
WDTSEL
Bits
Description
Reserved
[31]
Reserved.
UART1 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from PLL.
010 = Clock source from external low speed crystal oscillator (LXT).
011 = Clock source from internal high speed RC oscillator (HIRC).
100 = Clock source from PCLK1.
[30:28]
UART1SEL
101 = Clock source from internal low speed RC oscillator (LIRC).
Other = Reserved.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK1. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[27]
Reserved
Reserved.
UART0 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from PLL.
010 = Clock source from external low speed crystal oscillator (LXT).
011 = Clock source from internal high speed RC oscillator (HIRC).
100 = Clock source from PCLK0.
[26:24]
UART0SEL
101 = Clock source from internal low speed RC oscillator (LIRC).
Other = Reserved.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK0. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
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[23]
Reserved
TMR3SEL
Reserved
TMR2SEL
Reserved
TMR1SEL
Reserved
TMR0SEL
Reserved.
TIMER3 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from external low speed crystal oscillator (LXT).
010 = Clock source from PCLK1.
011 = Clock source from external clock T3 pin.
101 = Clock source from internal low speed RC oscillator (LIRC).
111 = Clock source from internal high speed RC oscillator (HIRC).
Others = Reserved.
[22:20]
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[19]
Reserved.
TIMER2 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from external low speed crystal oscillator (LXT).
010 = Clock source from PCLK1.
011 = Clock source from external clock T2 pin.
101 = Clock source from internal low speed RC oscillator (LIRC).
111 = Clock source from internal high speed RC oscillator (HIRC).
Others = Reserved.
[18:16]
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[15]
Reserved.
TIMER1 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from external low speed crystal oscillator (LXT).
010 = Clock source from PCLK0.
011 = Clock source from external clock T1 pin.
101 = Clock source from internal low speed RC oscillator (LIRC).
111 = Clock source from internal high speed RC oscillator (HIRC).
Others = Reserved.
[14:12]
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[11]
Reserved.
TIMER0 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from external low speed crystal oscillator (LXT).
010 = Clock source from PCLK0.
011 = Clock source from external clock T0 pin.
101 = Clock source from internal low speed RC oscillator (LIRC).
111 = Clock source from internal high speed RC oscillator (HIRC).
Others = Reserved.
[10:8]
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[7]
Reserved
CLKOSEL
Reserved.
[6:4]
Clock Divider Clock Source Selection
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000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from external low speed crystal oscillator (LXT).
010 = Clock source from HCLK.
011 = Clock source from internal high speed RC oscillator (HIRC).
100 = Clock source from internal low speed RC oscillator (LIRC).
101 = Clock source from internal high speed RC oscillator (HIRC).
110 = Clock source from PLL.
111 = Clock source from USB SOF.
Note: If the PLL function is not supported, the clock source will be fixed at HIRC. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Window Watchdog Timer Clock Source Selection (Write Protect)
10 = Clock source from HCLK/2048.
[3:2]
WWDTSEL
11 = Clock source from internal low speed RC oscillator (LIRC).
Others = Reserved.
Watchdog Timer Clock Source Selection (Write Protect)
00 = Reserved.
01 = Clock source from external low speed crystal oscillator (LXT).
10 = Clock source from HCLK/2048.
[1:0]
WDTSEL
11 = Clock source from internal low speed RC oscillator (LIRC).
Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2. Will be forced to
11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
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Clock Source Select Control Register 2 (CLK_CLKSEL2)
Before clock switching, the related clock sources (pre-select and new-select) must be turned on.
Register
Offset
R/W Description
Reset Value
CLK_CLKSEL2 CLK_BA+0x18 R/W Clock Source Select Control Register 2
0x0020_0023
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
Reserved
ADCSEL
Reserved
SPI0SEL
Reserved
Reserved
1
0
Reserved
PWM1SEL
PWM0SEL
Bits
Description
Reserved
[31]
Reserved.
ADC Clock Source Selection
00 = Clock source from external high speed crystal oscillator (HXT) clock.
01 = Clock source from PLL.
[21:20]
ADCSEL
10 = Clock source from PCLK1.
11 = Clock source from internal high speed RC oscillator (HIRC) clock.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK1. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
SPI0 Clock Source Selection
00 = Clock source from external high speed crystal oscillator (HXT).
01 = Clock source from PLL.
[5:4]
SPI0SEL
10 = Clock source from PCLK1.
11 = Clock source from internal high speed RC oscillator (HIRC).
Note: If the PLL function is not supported, the clock source will be fixed at PCLK1. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
[3:2]
[1]
Reserved
Reserved.
PWM1 Clock Source Selection
The peripheral clock source of PWM1 is defined by PWM1SEL.
0 = Clock source from PLL.
PWM1SEL
1 = Clock source from PCLK1.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK1. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
PWM0 Clock Source Selection
The peripheral clock source of PWM0 is defined by PWM0SEL.
0 = Clock source from PLL.
[0]
PWM0SEL
1 = Clock source from PCLK0.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK0. Please
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refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Feb 25, 2019
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Clock Source Select Control Register 3 (CLK_CLKSEL3)
Before clock switching, the related clock sources (pre-select and new-select) must be turned on.
Register
Offset
R/W Description
Reset Value
CLK_CLKSEL3 CLK_BA+0x1C R/W Clock Source Select Control Register 3
0x0400_0000
31
23
15
7
30
22
14
6
29
Reserved
21
28
20
12
4
27
19
11
3
26
18
10
2
25
UART2SEL
17
24
16
8
Reserved
Reserved
Reserved
13
5
9
1
0
Bits
Description
Reserved
[31:27]
[26:24]
[23:0]
Reserved.
UART2 Clock Source Selection
000 = Clock source from external high speed crystal oscillator (HXT).
001 = Clock source from PLL.
010 = Clock source from external low speed crystal oscillator (LXT).
011 = Clock source from internal high speed RC oscillator (HIRC).
100 = Clock source from PCLK0.
UART2SEL
101 = Clock source from internal low speed RC oscillator (LIRC).
Other = Reserved.
Note: If the PLL function is not supported, the clock source will be fixed at PCLK0. Please
refer to section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Note: If the LXT function is not supported, the clock source will be stopped. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
Reserved
Reserved.
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Clock Divider Number Register 0 (CLK_CLKDIV0)
Register
Offset
R/W Description
Reset Value
CLK_CLKDIV0 CLK_BA+0x20 R/W Clock Divider Number Register 0
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
ADCDIV
UART1DIV
USBDIV
UART0DIV
HCLKDIV
1
0
Bits
Description
Reserved
[31:24]
[23:16]
Reserved.
ADC Clock Divide Number From ADC Clock Source
ADCDIV
ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
UART1 Clock Divide Number From UART1 Clock Source
[15:12]
[11:8]
[7:4]
UART1DIV
UART0DIV
USBDIV
UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
UART0 Clock Divide Number From UART0 Clock Source
UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
USB Clock Divide Number From PLL Clock
USB clock frequency = (PLL frequency) / (USBDIV + 1).
HCLK Clock Divide Number From HCLK Clock Source
[3:0]
HCLKDIV
HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
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Clock Divider Number Register 4 (CLK_CLKDIV4)
Register
Offset
R/W Description
Reset Value
CLK_CLKDIV4 CLK_BA+0x30 R/W Clock Divider Number Register 4
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
UART2DIV
Bits
Description
Reserved
[31:4]
Reserved.
UART2 Clock Divide Number From UART2 Clock Source
[3:0]
UART2DIV
UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
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APB Clock Divider Register (CLK_PCLKDIV)
Register
Offset
R/W Description
Reset Value
CLK_PCLKDIV CLK_BA+0x34
R/W APB Clock Divider Register
0x0000_0000
31
23
15
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
5
1
0
Reserved
APB1DIV
Reserved
APB0DIV
Bits
Description
Reserved
[31:7]
[6:4]
[3]
Reserved.
APB1 Clock DIvider
APB1 clock can be divided from HCLK
000: PCLK1 = HCLK.
001: PCLK1 = 1/2 HCLK.
010: PCLK1 = 1/4 HCLK.
011: PCLK1 = 1/8 HCLK.
100: PCLK1 = 1/16 HCLK.
Others: Reserved.
APB1DIV
Reserved
APB0DIV
Reserved.
APB0 Clock DIvider
APB0 clock can be divided from HCLK
000: PCLK0 = HCLK.
001: PCLK0 = 1/2 HCLK.
010: PCLK0 = 1/4 HCLK.
011: PCLK0 = 1/8 HCLK.
100: PCLK0 = 1/16 HCLK.
Others: Reserved.
[2:0]
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PLL Control Register (CLK_PLLCTL)
The PLL reference clock input is from the 4~32 MHz external high speed crystal oscillator (HXT) clock
input or from the 48 MHz internal high speed oscillator (HIRC/4). This register is used to control the
PLL output frequency and PLL operation mode.
Programming these bits needs to write “59h”, “16h”, “88h” to address 0x4000_0100 to disable register
protection. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
Register
Offset
R/W
Description
Reset Value
CLK_PLLCTL CLK_BA+0x40 R/W
PLL Control Register
0x0005_C25E
31
30
22
14
6
29
28
27
26
25
24
Reserved
23
STBSEL
15
21
Reserved
13
20
12
4
19
PLLSRC
11
18
OE
10
17
BP
9
16
PD
8
OUTDIV
INDIV
3
FBDIV
0
7
5
2
1
FBDIV
Bits
Description
Reserved
[31:24]
Reserved.
PLL Stable Counter Selection (Write Protect)
0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less
than 12 MHz ).
[23]
STBSEL
1 = PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12
MHz).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[22:20]
[19]
Reserved
PLLSRC
Reserved.
PLL Source Clock Selection (Write Protect)
0 = PLL source clock from external high-speed crystal oscillator (HXT).
1 = PLL source clock from 48 MHz internal high-speed oscillator (HIRC/4).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PLL OE (FOUT Enable) Pin Control (Write Protect)
0 = PLL FOUT Enabled.
[18]
[17]
OE
BP
1 = PLL FOUT is fixed low.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PLL Bypass Control (Write Protect)
0 = PLL is in normal mode (default).
1 = PLL clock output is same as PLL input clock FIN.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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Power-down Mode (Write Protect)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
0 = PLL is in normal mode.
[16]
PD
1 = PLL is in Power-down mode (default).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PLL Output Divider Control (Write Protect)
[15:14]
[13:9]
[8:0]
OUTDIV
INDIV
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PLL Input Divider Control (Write Protect)
Refer to the formulas below the table.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
PLL Feedback Divider Control (Write Protect)
Refer to the formulas below the table.
FBDIV
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Output Clock Frequency Setting
NF 1
NR NO
FOUT FIN
Constraint:
1.
FIN
2*NR
2.
800kHz
8MHz
NF
200MHz FCO FIN *
500MHz,
3.
NR
FCO 250MHz is preferred
Symbol
FOUT
FIN
Description
Output Clock Frequency
Input (Reference) Clock Frequency
Input Divider (INDIV + 2)
NR
NF
Feedback Divider (FBDIV + 2)
NO
OUTDIV
OUTDIV
OUTDIV
=
=
=
“00”
“01”
“10”
:
:
:
NO
NO
NO
=
=
=
1
2
2
OUTDIV = “11” : NO = 4
Table 6.3-1 Symbol Definition of PLL Output Frequency Formula
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Clock Status Monitor Register (CLK_STATUS)
The bits in this register are used to monitor if the chip clock source is stable or not, and whether the
clock switch is failed.
Register
Offset
R/W Description
Clock Status Monitor Register
Reset Value
CLK_STATUS
CLK_BA+0x50
R
0x0000_00XX
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
3
2
1
0
CLKSFAIL
Reserved
HIRCSTB
LIRCSTB
PLLSTB
LXTSTB
HXTSTB
Bits
Description
[31:8]
Reserved
Reserved.
Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source. If switch target clock is
stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.
[7]
CLKSFAIL
0 = Clock switching success.
1 = Clock switching failure.
Note: Write 1 to clear the bit to 0.
[6:5]
[4]
Reserved
HIRCSTB
Reserved.
HIRC Clock Source Stable Flag (Read Only)
0 = Internal high speed RC oscillator (HIRC) clock is not stable or disabled.
1 = Internal high speed RC oscillator (HIRC) clock is stable and enabled.
LIRC Clock Source Stable Flag (Read Only)
[3]
[2]
LIRCSTB
PLLSTB
0 = Internal low speed RC oscillator (LIRC) clock is not stable or disabled.
1 = Internal low speed RC oscillator (LIRC) clock is stable and enabled.
Internal PLL Clock Source Stable Flag (Read Only)
0 = Internal PLL clock is not stable or disabled.
1 = Internal PLL clock is stable and enabled.
Note: If the PLL function is not supported, this bit field will become invalid. Please refer to
section 4.3 NuMicro® M031/M032 Series Selection Guide for detailed information.
LXT Clock Source Stable Flag (Read Only)
[1]
[0]
LXTSTB
HXTSTB
0 = External low speed crystal oscillator (LXT) clock is not stable or disabled.
1 = External low speed crystal oscillator (LXT) clock is stabled and enabled.
HXT Clock Source Stable Flag (Read Only)
0 = External high speed crystal oscillator (HXT) clock is not stable or disabled.
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1 = External high speed crystal oscillator (HXT) clock is stable and enabled.
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Clock Output Control Register (CLK_CLKOCTL)
Register
Offset
R/W Description
Reset Value
CLK_CLKOCTL CLK_BA+0x60 R/W Clock Output Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
1
0
Reserved
DIV1EN
CLKOEN
FREQSEL
Bits
Description
Reserved
[31:6]
Reserved.
Clock Output Divide One Enable Bit
[5]
[4]
DIV1EN
0 = Clock Output will output clock with source frequency divided by FREQSEL.
1 = Clock Output will output clock with source frequency.
Clock Output Enable Bit
CLKOEN
0 = Clock Output function Disabled.
1 = Clock Output function Enabled.
Clock Output Frequency Selection
The formula of output frequency is
Fout = Fin/2(N+1).
[3:0]
FREQSEL
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
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Clock Fail Detector Control Register (CLK_CLKDCTL)
Register
Offset
R/W
Description
Reset Value
CLK_CLKDCTL CLK_BA+0x70
R/W
Clock Fail Detector Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
28
20
12
27
19
11
3
26
18
10
2
25
17
24
16
Reserved
21
Reserved
HXTFQIEN
9
HXTFQDEN
8
13
LXTFIEN
5
Reserved
Reserved
LXTFDEN
4
Reserved
1
0
HXTFIEN
HXTFDEN
Reserved
Bits
Description
Reserved
[31:18]
Reserved.
HXT Clock Frequency Range Detector Interrupt Enable Bit
0 = External high speed crystal oscillator (HXT) clock frequency range detector fail
interrupt Disabled.
[17]
HXTFQIEN
1 = External high speed crystal oscillator (HXT) clock frequency range detector fail
interrupt Enabled.
HXT Clock Frequency Range Detector Enable Bit
[16]
HXTFQDEN
Reserved
LXTFIEN
0 = External high speed crystal oscillator (HXT) clock frequency range detector Disabled.
1 = External high speed crystal oscillator (HXT) clock frequency range detector Enabled.
[15:14]
[13]
Reserved.
LXT Clock Fail Interrupt Enable Bit
0 = External low speed crystal oscillator (LXT) clock fail interrupt Disabled.
1 = External low speed crystal oscillator (LXT) clock fail interrupt Enabled.
LXT Clock Fail Detector Enable Bit
[12]
[11:6]
[5]
LXTFDEN
Reserved
HXTFIEN
0 = External low speed crystal oscillator (LXT) clock fail detector Disabled.
1 = External low speed crystal oscillator (LXT) clock fail detector Enabled.
Reserved.
HXT Clock Fail Interrupt Enable Bit
0 = External high speed crystal oscillator (HXT) clock fail interrupt Disabled.
1 = External high speed crystal oscillator (HXT) clock fail interrupt Enabled.
HXT Clock Fail Detector Enable Bit
[4]
HXTFDEN
Reserved
0 = External high speed crystal oscillator (HXT) clock fail detector Disabled.
1 = External high speed crystal oscillator (HXT) clock fail detector Enabled.
[3:0]
Reserved.
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Clock Fail Detector Status Register (CLK_CLKDSTS)
Register
Offset
R/W
Description
Reset Value
CLK_CLKDSTS CLK_BA+0x74
R/W
Clock Fail Detector Status Register
0x0000_0000
31
23
15
7
30
22
14
6
29
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
21
13
5
8
Reserved
4
HXTFQIF
0
1
Reserved
LXTFIF
HXTFIF
Bits
Description
Reserved
[31:9]
Reserved.
HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)
0 = External high speed crystal oscillator (HXT) clock frequency is normal.
1 = External high speed crystal oscillator (HXT) clock frequency is abnormal.
Note: Write 1 to clear the bit to 0.
[8]
HXTFQIF
Reserved
LXTFIF
[7:2]
[1]
Reserved.
LXT Clock Fail Interrupt Flag (Write Protect)
0 = External low speed crystal oscillator (LXT) clock is normal.
1 = External low speed crystal oscillator (LXT) stops.
Note: Write 1 to clear the bit to 0.
HXT Clock Fail Interrupt Flag (Write Protect)
0 = External high speed crystal oscillator (HXT) clock is normal.
1 = External high speed crystal oscillator (HXT) clock stops.
Note: Write 1 to clear the bit to 0.
[0]
HXTFIF
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Clock Frequency Range Detector Upper Boundary Register (CLK_CDUPB)
Register
Offset
R/W
Description
Reset Value
Clock Frequency Range Detector Upper Boundary
Register
CLK_CDUPB CLK_BA+0x78
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
21
13
5
8
UPERBD
0
Reserved
1
UPERBD
Bits
Description
Reserved
[31:10]
Reserved.
HXT Clock Frequency Range Detector Upper Boundary Value
The bits define the maximum value of frequency range detector window.
[9:0]
UPERBD
When HXT frequency is higher than this maximum frequency value, the HXT Clock
Frequency Range Detector Interrupt Flag will be set to 1.
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Clock Frequency Range Detector Lower Boundary Register (CLK_CDLOWB)
Register
Offset
R/W
Description
Reset Value
Clock Frequency Range Detector Lower Boundary
Register
CLK_CDLOWB CLK_BA+0x7c
R/W
0x0000_0000
31
23
15
7
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
Reserved
Reserved
21
13
5
8
LOWERBD
0
Reserved
1
LOWERBD
Bits
Description
Reserved
[31:10]
Reserved.
HXT Clock Frequency Range Detector Lower Boundary Value
The bits define the minimum value of frequency range detector window.
[9:0]
LOWERBD
When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency
Range Detector Interrupt Flag will set to 1.
Frequency out of range will be asserted when HIRC_period*1024> HXT_period*CLK_DUPB or HIRC_period*1024 <
HXT_period*CLK_CDLOWB
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HXT Filter Select Control Register (CLK_HXTFSEL)
Register
Offset
R/W Description
Reset Value
CLK_HXTFSEL CLK_BA+0xB4 R/W HXT Filter Select Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
HXTFSEL
Bits
Description
Reserved
[31:1]
Reserved.
HXT Filter Select
0 = HXT frequency is greater than12 MHz.
[0]
HXTFSEL
1 = HXT frequency is less than or equal to 12 MHz.
Note: This bit should not be changed during HXT running.
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
This chip is equipped with 16/32/64/128 Kbytes on-chip embedded Flash for application and Data
Flash to store some application dependent data. A User Configuration block provides for system
initialization. A 2/4 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function
with 128 Kbytes Flash and 2 Kbytes LDROM for other size Flash. A 512 bytes security protection
ROM (SPROM) can conceal user program. This chip also supports In-Application-Programming (IAP)
function, user switches the code executing without the chip reset after the embedded Flash updated.
6.4.2
Features
Supports16/32/64/128 Kbytes application ROM (APROM).
Supports 2/4 Kbytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports 512 bytes security protection ROM (SPROM) to conceal user program.
Supports 12 bytes User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded Flash.
Supports CRC-32 checksum calculation function.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 55 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 55 pins are arranged in 5 ports named as PA, PB, PC, PD and PF. PA
and PB has 16 pins on port. PC has 9 pins on port. PD has 5 pins on port. PF has 9 pins on port. Each
of the 55 pins is independent and has the corresponding register bits to control the pin mode function
and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).
6.5.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
Schmitt trigger input
I/O pin can be configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
Supports input 5V tolerance, except analog pin (PA.10 ~ 11; PB.0 ~ 15; PF.2 ~ 5; all USB
pin and nRESET pin).
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 5 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.6.2
Features
Supports 5 independently configurable channels
Selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and I2C, SPI/I2S, UART, USCI, ADC, PWM and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
6.7.2
Features
6.7.2.1 Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
Supports event counting source from internal USB SOF signal
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports internal capture triggered while internal ACMP output signal and LIRC transition
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
PWM, ADC, PDMA function
Supports Inter-Timer trigger mode
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.8.2
Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if
WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.9.2
Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.10 PWM Generator and Capture Timer (PWM)
6.10.1 Overview
The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of
PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM
counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.
PWM uses comparator compared with counter to generate events. These events use to generate
PWM pulse, interrupt and trigger signal for ADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. In Complementary mode, there are two
comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control
unit, it supports polarity output, independent pin mask and brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.10.2 Features
6.10.2.1 PWM Function Features
Supports maximum clock frequency up to 96 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
– Dead-time insertion with 12-bit resolution
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution PWM counter
– Up, down and up-down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
– Brake source from pin and system safety events (clock failed, Brown-out detection
and CPU lockup)
– Noise filter for brake source from pin
– Edge detect brake source to control brake state until brake interrupt cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM counter matches 0, period value or compared value
– Brake condition happened
Supports trigger ADC on the following events:
– PWM counter matches 0, period value or compared value
6.10.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
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Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.11 UART Interface Controller (UART)
6.11.1 Overview
The chip provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The
UART controller performs Normal Speed UART and supports flow control function. The UART
controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-
to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten
types of interrupts. The UART controller also supports IrDA SIR, RS-485 and Single-wire function
modes and auto-baud rate measuring function.
6.11.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Support Single-wire function mode.
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function (Only UART0 /UART1 with Received Data
FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function)
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT. (Only UART0 /UART1 with this
feature)
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
UART Feature
UART0/ UART1
UART2
USCI-UART
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TX: 1byte
RX: 2byte
FIFO
16 Bytes
1 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
-
√
√
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Imcoming Data Wake-up
√
√
√
√
√
√
√
√
√
-
Received
Data
FIFO
reached
√
√
-
-
threshold Wake-up
RS-485 Address Match (AAD mode)
Wake-up
-
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
√
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
Stick Bit
√
√
√
√
√
-
Note: √= Supported
Table 6.11-1 NuMicro® M031 Series UART Features
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6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one set of SPI controller performing a serial-to-parallel conversion on data received from
a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
Each SPI controller can be configured as a master or a slave device and supports the PDMA function
to access the data buffer. Each SPI controller also supports I2S mode to connect external audio
CODEC.
6.12.2 Features
SPI Mode
– Supports one set of SPI controller
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depended on SPI setting of data width
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Master mode up to 24 MHz and Slave mode up to 16 MHz (when chip works at VDD
=
1.8~3.6V)
– Supports one data channel half-duplex transfer
– Supports receive-only mode
– Supports PDMA transfer
I2S Mode
– Supports one set of I2S by SPI controller
– Interface with external audio CODEC
– Supports Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Supports two PDMA requests, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
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6.13 I2C Serial Interface Controller (I2C)
6.13.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.13.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps) and Fast mode (400 kbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports two-level buffer function
Supports setup/hold time programmable
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6.14 USCI - Universal Serial Control Interface Controller (USCI)
6.14.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.14.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
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6.15 USCI – UART Mode
6.15.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the system.
6.15.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.16 USCI - SPI Mode
6.16.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as Master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in Master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0
Figure 6.16-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0
Figure 6.16-2 SPI Slave Mode Application Block Diagram
6.16.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
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Supports Word Suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.17 USCI - I2C Mode
6.17.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on
the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.17-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.17-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode .
6.17.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.18 External Bus Interface (EBI)
6.18.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.18.2 Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
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6.19 USB Device Controller (USBD)
6.19.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/ isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 512 Bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to
write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the
effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device plug-
in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register USBD_EPSTS0 to acknowledge what kind of
event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the
SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
6.19.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 byte buffer size
Provides remote wake-up capability
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6.20 CRC Controller (CRC)
6.20.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.20.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.21 Hardware Divider (HDIV)
6.21.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a
signed, integer divider with both quotient and remainder outputs.
6.21.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
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6.22 Analog-to-Digital Converter (ADC)
6.22.1 Overview
The ADC contains one 12-bit successive approximation analog-to-digital converter (SAR A/D
converter) with 16 input channels. The A/D converter supports four operation modes: Single, Burst,
Single-cycle Scan and Continuous Scan mode. The A/D converter can be started by software,
external pin (STADC/PF.5), timer0~3 overflow pulse trigger and PWM trigger.
6.22.2 Features
Operating voltage: 1.8V~3.6V.
Analog input voltage: 0 ~ AVDD.
Supports external reference voltage from VREF pin.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog input channels or 8 differential analog input channels.
Maximum ADC peripheral clock frequency is 48 MHz.
Up to 2 MSPS sampling rate.
Scan on enabled channels
Threshold voltage detection
Four operation modes:
– Single mode: A/D conversion is performed one time on a specified channel.
– Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
– Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
– Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
– Software Write 1 to ADST bit.
– External pin (STADC).
– Timer 0~3 overflow pulse trigger.
– PWM trigger.
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Supports extend sample time function (0~255 ADC clock).
One internal channel from band-gap voltage (VBG).
Supports PDMA transfer mode.
Supports Calibration mode.
Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
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Note2: If the internal channel for band-gap voltage is active, the maximum sampling rate will be 300 k
SPS.
Note3: The ADC Clock frequency must be slower than or equal to PCLK.
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6.23 Analog Comparator Controller (ACMP)
6.23.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.23.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two rail-to-rail analog comparators
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 3 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
ACMP1 supports
– 4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 3 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
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6.24 Peripherals Interconnection
6.24.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interaction without CPU
saves CPU resources, reduces power consumption, and allows for operation with no software latency
and fast responds.
6.24.2 Peripherals Interconnect Matrix Table
Destination
Source
ADC
HIRC TRIM
PWM
Timer
UART/USCI
ACMP
BOD
-
-
-
-
3
3
3
3
-
6
-
-
-
-
-
-
Clock Fail
CPU Lockup
LIRC
-
-
-
-
-
-
-
-
6
-
HXT
-
-
-
LXT
-
2
-
-
-
PWM
1
1
-
4
5
-
-
8
-
Timer
-
7
USB 1.1 Device
2
-
Table 6.24-1 Peripherals Interconnect Matrix Table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
as close to AVDD as possible
L=30Z
EXT_PWR
AVDD
AVSS
1uF+0.1uF+0.01uF
L=30Z
as close to the
EXT_PWR as possible
10uF+0.1uF
VREF
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
LDO_CAP
VSS
1uF
as close to LDO as possible
VDD
VSS
EXT_VSS
0.1uF*N
as close to VDD as possible
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7.2
Peripheral Application Scheme
DVCC
100K
100K
VDD
USB Full Speed Slot
ICE_DAT
SWD
Interface
ICE_CLK
nRESET
USB_VBUS
USB_D-
27R
27R
VSS
USB_D+
20pF
USB_VCC33_CAP
XT1_IN
1uF
4~32 MHz
20pF
crystal
DVCC
XT1_OUT
CS
SPI_SS
SPI_CLK
VDD
CLK
SPI Device
Crystal
SPI_MISO
SPI_MOSI
MISO
MOSI
VSS
20pF
X32_IN
32.768 kHz
crystal
20pF
DVCC
DVCC
X32_OUT
4.7K
4.7K
M031/M032 Series
DVCC
CLK
DIO
VDD
VSS
I2C_SCL
I2C Device
Reset
Circuit
I2C_SDA
10K
nRST
10 uF
PC COM Port
RS 232 Transceiver
LDO_CAP
LDO
1 uF
RIN
UART_RXD
UART_TXD
ROUT
UART
TIN
TOUT
64K x 16-bit
SRAM
LATCH
Q
D
Addr[15:0]
En
ALE
Audio codec
NUC8822
nCE
nOE
nWE
nLB
nCS
nRD
Line In
EBI
I2S
nWR
Line Out
nWRL
nWRH
nUB
Data[15:0]
AD[15:0]
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
4.0
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
ΔVDD
|VDD –AVDD
ΔVSS
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on 5V-tolerance I/O
-
mV
mV
mV
mV
V
|
-
50
-
50
|VSS - AVSS
|
-
50
VSS-0.3
VSS-0.3
5.5
4.0
VIN
Input voltage on any other pin[*2]
V
Note:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Non 5V-tolerance I/O includes PA.10 ~ 11; PB.0 ~ 15; PF.2, 3, 4, 5; all USB pin and nRESET pin. VIN maximum value
must be respected to avoid permanent damage. Refer to Table 8.1-2 for the values of the maximum allowed injected
current
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
150
100
20
Unit
[*1]
ΣIDD
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
IIO
mA
100
100
±5
[*3]
IINJ(PIN)
[*3]
ΣIINJ(PIN)
±25
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Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
Table 8.1-2 Current Characteristics
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8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (°C)
θJA = thermal resistance junction-ambient (°C/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
Unit
°C
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
105
125
150
T
J
-40
-65
-
T
ST
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
°C/Watt
38
30
-
-
-
-
-
-
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
-
-
-
-
-
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
28
[*1]
θJA
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
60
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
58
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)
38.5
Note:
1.
Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal Characteristics
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8.1.4
EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts
of narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-6000
-1000
-400
Typ
Max
+6000
+1000
+400
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
-4.4
Fast transient voltage burst
+4.4
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-4 EMC Characteristics
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8.1.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge
20-pin TSSOP(4.4x6.5 mm)[*1]
28-pin TSSOP(4.4x9.7 mm) [*1]
33-pin QFN(4x4 mm) [*1]
MSL
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
48-pin LQFP(7x7 mm) [*1]
64-pin LQFP(7x7 mm) [*1]
128-pin LQFP(14x14 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-5 Package Moisture Sensitivity (MSL)
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8.1.6
Soldering Profile
Figure 8.1-1 Soldering Profile from J-STD-020C
Porfile Feature
Pb Free Package
3°C/sec. max
Average ramp-up rate (217°C to peak)
Preheat temperature 150°C ~200°C
Temperature maintained above 217°C
Time with 5°C of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260°C
Ramp-down rate
6°C/sec ax.
8 min. max
Time 25°C to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.1-6 Soldering Profile
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8.2 General Operating Conditions
(VDD-VSS = 1.8 ~ 3.6V, TA = 25C, HCLK = 48 MHz unless otherwise specified.)
Test Conditions
Min
Typ
Max
Unit
°C
Symbol
TA
Parameter
Temperature
-40
-
105
fHCLK
VDD
Internal AHB clock frequency
-
-
-
48
MHz
Operation voltage
1.8
3.6
[*1]
AVDD
Analog operation voltage
Analog reference voltage
LDO output voltage
VDD
VREF
VLDO
1.8
-
-
1.8
1.2
1
AVDD
-
V
AVDD − VREF < 1.2 V
[*4]
VBG
Band-gap voltage
1.14
1.26
[*2]
CLDO
LDO output capacitor on each pin
ESR of CLDO output capacitor
[*3]
RESR
0.1
-
-
10
-
Ω
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
[*3]
IRUSH
150
mA
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
VDD = 1.8 V, TA = 105 °C,
IRUSH = 150 mA for 15 us
[*3]
ERUSH
-
2.25
-
µC
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3.Guaranteed by design, not tested in production
4.Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 General Operating Conditions
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8.3 DC Electrical Characteristics
8.3.1 Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1. 8V ~ 3.6 V unless otherwise
specified.
VDD = AVDD
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
9.78
6.44
5.75
4.14
TBD
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
8.5
5.6
5
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Normal run mode, executed
from Flash, all peripherals
disable
3.6
2.4
0.119
0.119
20.2
38.4 kHz
32.768 kHz
48 MHz
0.095
0.095
17.5
TBD
TBD
TBD
TBD
TBD
TBD
IDD_RUN
mA
13.1
10.9
6.4
32 MHz
24 MHz
11.5
9.5
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Normal run mode, executed
from Flash, all peripherals
enable
12 MHz
5.6
TBD
0.128
0.128
4 MHz
2.9
38.4 kHz
32.768 kHz
0.103
0.103
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-1 Current Consumption in Normal Run Mode
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Typ
Max[*1] [*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
3.8
2.5
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
3.3
2.2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2.7
2.35
1.83
1.51
Idle mode, all peripherals
disable
2.1
TBD
0.117
0.117
14.7
38.4 kHz
32.768 kHz
48 MHz
0.093
0.093
12.8
TBD
TBD
TBD
TBD
TBD
IDD_IDLE
mA
TBD
9.55
8.28
32 MHz
24 MHz
8.3
7.2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Idle mode, all peripherals
enable
4.95
12 MHz
4.3
TBD
0.124
0.124
4 MHz
2.43
0.099
0.099
38.4 kHz
32.768 kHz
Note:
1. When analog peripheral blocks such as ADC, ACMP, PLL, HIRC, LIRC, HXT and LXT are ON, an additional power
consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-2 Current Consumption in Idle Mode
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Typ[*2]
Max[*3][*4]
LXT[*1] LIRC
32.768 38.4
Symbol
Test Conditions
Unit
T
=
T
=
T
=
T =
A
A
A
A
kHz
kHz
25 °C 25 °C 85 °C 105 °C
Power-down mode, all peripherals disable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT/Timer/UART enable
Power-down mode, WDT use LIRC, UART/Timer use LXT
-
-
12
13.5
12.5
14
TBD[*5] TBD TBD[*5]
V
-
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IDD_PD
µA
V
V
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for typical values
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
5. Based on characterization, tested in production.
Table 8.3-3 Chip Current Consumption in Power-down Mode
Feb 25, 2019
Page 234 of 274
Rev. 1.01
M031/M032
8.3.2
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on
[*1]
Peripheral
ADC[*2]
ACMP01[*3]
PWM0
PWM1
WDT/WWDT
SPI/I2S
UART0
UART1
UART2
I2C0
IDD
Unit
TBD
TBD
1.23
1.23
0.12
TBD
0.56
0.56
0.56
TBD
TBD
0.60
TBD
0.28
0.27
0.28
0.27
TBD
TBD
TBD
TBD
TBD
I2C1
mA
USCI0
EBI
TMR0
TMR1
TMR2
TMR3
USB FS Device
CRC
EBI
PDMA
ADC[*2]
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
Table 8.3-4 Peripheral Current Consumption
Feb 25, 2019
Page 235 of 274
Rev. 1.01
M031/M032
8.3.3
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
Symbol
Parameter
Typ
5
Max
6
Unit
cycles
µs
tWU_IDLE
Wakeup from IDLE mode
Wakeup from normal power down mode
[*1][*2]
tWU_NPD
TBD
TBD
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-5 Low-power Mode Wakeup Timings
Feb 25, 2019
Page 236 of 274
Rev. 1.01
M031/M032
8.3.4
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD except 5V-tolenece
I/O should be avoided during normal product operation. However, the analog compoenent of the MCU
is most likely to be affected by the injection current , but it is not easily clarified when abnormal
injection accidentally happens. It is recommended to add a Schottky diode (pin to ground or pin to
VDD) to pins that include analog function which may potentially injection currents.
Negative
injection
Positive
injection
Symbol
Parameter
Unit
Test Condition
-0
-0
0
0
Injected current on nReset pins
Injected current on PF2~PF5, PA10,
PA11 and PB0~PB15 for analog
input function
Injected current by a I/O Pin
mA
IINJ(PIN)
Injected current on any other 5V-
tolerance I/O
-5
NA
Table 8.3-6 I/O Current Injection Characteristics
8.3.5
I/O DC Characteristics
8.3.5.1 PIN Input Characteristics
Symbol
VIL
Parameter
Min
Typ
Max
0.3*VDD
VDD
Unit
V
Test Conditions
Input low voltage
Input high voltage
0
-
VIH
0.7*VDD
-
-
V
[*1]
VHY
Hysteresis voltage of schmitt input
0.2*VDD
-
V
VSS < VIN < VDD
,
-1
-1
1
1
Open-drain or input only mode
[*2]
ILK
Input leakage current
A
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
-
-
45
-
-
VDD = 3.3 V, Quasi mode
VDD = 1.8 V, Quasi mode
[*1] [*3]
RPU
Pull up resistor
kΩ
120
Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher
than the maximum value, if positive current is injected on adjacent pins
Table 8.3-7 I/O Input Characteristics
Feb 25, 2019
Page 237 of 274
Rev. 1.01
M031/M032
8.3.5.2 I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 3.3 V
-25.5
-28
-31
µA
VIN=(VDD-0.4) V
Source current for quasi-
bidirectional mode and
high level
VDD = 2.5 V
-19
-10.5
-8.5
-7
-22
-13
-10
-8
-24
-16
-11
-9
µA
µA
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
[*1] [*2]
ISR
VDD = 3.3 V
mA
mA
mA
mA
mA
VIN=(VDD-0.4) V
VDD = 2.5 V
Source current for push-
pull mode and high level
VIN=(VDD-0.4) V
VDD = 1.8 V
-4.4
8
-5.5
9.5
7.5
-6.5
11
VIN=(VDD-0.4) V
VDD = 3.3 V
VIN= 0.4 V
VDD = 2.5 V
VIN= 0.4 V
Sink current for push-
pull mode and low level
[*1] [*2]
ISK
7
9
VDD = 1.8 V
VIN= 0.4 V
4.3
-
5
5
6.3
-
mA
pF
[*1]
CIO
I/O pin capacitance
Note:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.3-8 I/O Output Characteristics
8.3.5.3 nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Min
Typ
-
Max Unit
Test Conditions
-
0.3*VDD
V
V
VIHR
0.7*VDD
-
-
-
-
45
120
32
-
-
VDD = 3.3 V
[*1]
RRST
Internal nRESET pull up resistor
nRESET input filtered pulse time
KΩ
-
-
VDD = 1.8 V
-
Normal run and Idle mode
Power down mode
[*1]
tFR
µs
75
155
Note:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.3-9 nRESET Input Characteristics
Feb 25, 2019
Page 238 of 274
Rev. 1.01
M031/M032
8.4 AC Electrical Characteristics
8.4.1
48 MHz Internal High Speed RC Oscillator (HIRC)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.8
-
3.6
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
47.52
-1
48
-
48.48
1
MHz
%
TA = 25 °C,
VDD = 3.3V
fHRC
Frequency drift over temperarure and
volatge
TA = -40C ~ +105 °C,
-2[*1]
-
2[*1]
-
%
µA
µs
VDD = 1.8 ~ 3.6V
[*1]
IHRC
Operating current
Stable time
-
-
TBD
11
TA = -40C ~ +105 °C,
[*2]
TS
15
VDD = 1.8 ~ 3.6V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
Note: Test condition VDD=3.3V, Temp = -40~125°C
Figure 8.4-1 HIRC vs. Temperature
Feb 25, 2019
Page 239 of 274
Rev. 1.01
M031/M032
8.4.2
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.8
-
3.6
V
Oscillator frequnecy
38.016
38.4
38.784
kHz
TA = 25 °C,
VDD = 3.3V
-1
-
-
1
%
%
[*2]
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105 °C
VDD=1.8V~3.6V
-15
15
Without software calibration
ILRC
TS
Operating current
Stable time
-
-
0.85
500
1
-
µA
VDD = 3.3V
TA=-40~105 °C
VDD=1.8V~3.6V
μs
Note:
1. Guaranteed by characterization, not tested in production.
2. The 38.4 kHz low speed RC oscillator can be calibrated by user.
3. Guaranteed by design.
Table 8.4-238.4 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
Note: Test condition VDD=3.3V, Temp = -40~125°C
Figure 8.4-2 LIRC vs. Temperature
Feb 25, 2019
Page 240 of 274
Rev. 1.01
M031/M032
8.4.3
External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[*1]
Typ
-
Max[*1]
Unit
V
Test Conditions
1.8
-
3.6
-
Rf
Internal feedback resister
Oscillator frequency
200
kΩ
fHXT
4
-
-
32
MHz
120
200
4 MHz, Gain = L0
170
250
350
500
650
1700
900
600
450
400
350
300
450
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
4 MHz, Gain = L0
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
32 MHz, Gain = L7
-
-
IHXT
Current consumption
A
600
850
-
-
1100
2200
1100
740
-
-
-
-
TS
Stable time
s
650
600
550
DuHXT
Vpp
Duty cycle
40
-
-
60
-
%
V
Peak-to-peak amplitude
1
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-3 External 4~32 MHz High Speed Crystal (HXT) Oscillator
Feb 25, 2019
Page 241 of 274
Rev. 1.01
M031/M032
Symbol
Parameter
Min[*1]
Typ
TBD
TBD
TBD
TBD
TBD
Max[*1]
Unit
Test Conditions
-
-
-
-
-
-
-
-
-
-
Crystal @4 MHz
Crystal @12 MHz
Crystal @16 MHz
Crystal @24 MHz
Crystal @32 MHz
Rs
Equivalent series resisotr(ESR)
Ω
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-4 External 4~32 MHz High Speed Crystal Characteristics
8.4.3.1 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 32 MHz
10 ~ 25 pF
10 ~ 25 pF
without
XT1_OUT
XT1_IN
R1
C1
C2
Figure 8.4-3 Typical Crystal Application Circuit
Feb 25, 2019
Page 242 of 274
Rev. 1.01
M031/M032
8.4.4
External 4~32 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
1
-
32
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
ns
ns
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
ns
ns
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-5 External 4~32 MHz High Speed Clock Input Signal
Feb 25, 2019
Page 243 of 274
Rev. 1.01
M031/M032
8.4.5
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Min[*1]
1.8
-40
-
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
3.6
105
-
V
Temperature range
TLXT
C
Rf
Internal feedback resistor
Oscillator frequency
15
MΩ
kHz
FLXT
32.768
1.5
2
-
-
6
6
ESR=35 kΩ, Gain = L1
ESR=70 kΩ, Gain = L2
ILXT
Current consumption
A
TsLXT
DuLXT
Vpp
Stable time
-
500
-
900
70
-
ms
%
V
Duty cycle
30
-
Peak-to-peak amplitude
TBD
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Min
Typ
Max
Unit
Test Conditions
Equivalnet Series Resisotr(ESR)
-
35
70
kΩ
Crystal @32.768 kHz
Table 8.4-7 External 32.768 kHz Low Speed Crystal Characteristics
8.4.5.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
20 pF
20 pF
without
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-4 Typical 32.768 kHz Crystal Application Circuit
Feb 25, 2019
Page 244 of 274
Rev. 1.01
M031/M032
8.4.6
External 32.768 kHz Low Speed Clock Input Signal Characteristics
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
fLSE_ext
tCHCX
Parameter
External clock source frequency
Clock high time
Min[*1]
-
Typ
Max[*1]
Unit
kHz
ns
Test Conditions
32.768
-
-
-
450
450
-
-
tCLCX
Clock low time
ns
tCLCH
Clock rise time
Low (10%) to high level (90%)
rise time
-
-
-
-
50
50
ns
ns
tCHCL
Clock fall time
High (90%) to low level (10%) fall
time
DuE_LXT
Xin_VIH
Xin_VIL
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
LXT input pin input high voltage
LXT input pin input low voltage
0.3*VDD
V
External
clock source
X32_IN
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by design, not tested in production
Table 8.4-8 External 32.768 kHz Low Speed Clock Input Signal
Feb 25, 2019
Page 245 of 274
Rev. 1.01
M031/M032
8.4.7
PLL Characteristics
Symbol
fPLL_in
Parameter
PLL input clock
Min[*1]
3.2
50
Typ
Max[*1]
32
Unit
MHz
MHz
MHz
MHz
µs
Test Conditions
-
-
-
-
-
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
PLL multiplier output clock
PLL reference clock
96
0.8
200
-
8
PLL voltage controlled oscillator
PLL locking time
500
500
Jitter[*2]
Cycle-to-cycle Jitter
Power consumption
-
-
200
3.1
350
5
ps
IDD
f
mA
VDD =3.3V @ PLL_OUT = 96 MHz
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
Table 8.4-9 PLL Characteristics
Feb 25, 2019
Page 246 of 274
Rev. 1.01
M031/M032
8.4.8
I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
Test Conditions[*2]
-
CL = 30 pF, V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
= 3.3 V,
5.5
3
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
-
-
-
-
-
-
-
-
-
-
-
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
tf(IO)out
Output high (90%) to low level (10%) fall time
Output low (10%) to high level (90%) rise time
I/O maximum frequency
ns
8.5
4.5
5.5
3
tr(IO)out
ns
8.5
4.5
60
110
40
75
[*3]
fmax(IO)out
MHz
2.77
-
f(IO)out = 24 MHz
CL = 10 pF, V
= 3.3 V,
= 3.3 V,
DD
f(IO)out = 24 MHz
CL = 30 pF, V
1.19
0.69
-
-
[*4]
IDIO
I/O dynamic current consumption
mA
DD
f(IO)out = 6 MHz
CL = 10 pF, V
= 3.3 V,
DD
f(IO)out = 6 MHz
0.3
-
Note:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢅ
3. The maximum frequency is defined by
ꢃꢄ
ꢍꢄ.
ꢌ
ꢀꢁꢂ
ꢆꢄꢇꢄꢈꢉ ꢋꢉ
ꢊ
4. The I/O dynamic current consumption is defined by ꢎꢏꢐꢑ ꢃ ꢒꢏꢏ ꢄꢇꢄ ꢐꢑ ꢄꢇ ꢈꢓꢐꢑ ꢔꢄꢓꢕꢍ
Table 8.4-10 I/O AC Characteristics
Feb 25, 2019
Page 247 of 274
Rev. 1.01
M031/M032
8.5 Analog Characteristics
8.5.1 LDO
Symbol
VDD
Parameter
Power supply
Min
1.8
-
Typ
Max
3.6
-
Unit
V
Test Condition
-
1.8
-
VLDO
TA
Output voltage
Temperature
V
-40
105
°C
Note
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
8.5.2
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
POR reset voltage
Min
-
Typ
20
2
Max
Unit
Test Conditions
AVDD = 3.6V
[*1]
IPOR
30
µA
[*1]
ILVR
-
TBD
AVDD = 3.6V
AVDD = 3.6V
-
[*1]
IBOD
-
3
TBD
VPOR
VLVR
VBOD
1.35
1.6
1.8
2.3
-
1.5
1.7
2.0
2.5
TBD
TBD
TBD
TBD
-
1.65
V
LVR reset voltage
1.8
BOD brown-out detect voltage
2.2
BODVL = 0
2.7
BODVL = 1
[*1]
TLVR_SU
LVR startup time
LVR respond time
BOD startup time
BOD respond time
VDD rise time rate
VDD fall time rate
-
-
-
-
-
-
-
-
-
µs
-
[*1]
TLVR_RE
-
-
[*1]
TBOD_SU
-
-
[*1]
TBOD_RE
-
-
[*1]
RVDDR
10
10
TBD
TBD
TBD
µs/V
POR Enabled
POR Enabled
LVR Enabled
BOD 2.0V Enabled
BOD 2.5V Enabled
[*1]
RVDDF
-
-
-
-
Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.5-1 Reset and Power Control Unit
Feb 25, 2019
Page 248 of 274
Rev. 1.01
M031/M032
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
Feb 25, 2019
Page 249 of 274
Rev. 1.01
M031/M032
8.5.3
12-bit SAR ADC
Min
Typ
Max
Unit
Symbol
TA
Parameter
Test Conditions
Temperature
-40
105
-
-
°C
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.8
1.8
0
3.6
V
V
V
V
VDD
DD
AVDD
VREF
-
-
ADC channel input voltage
Common-Mode Input Range
VCM
VREF/2
Full differential input
AVDD = VDD =VREF = 3.3 V
FADC = 34 MHz
[*1]
IADC
Operating current (AVDD + VREF current)
-
-
355
34
µA
TCONV = 17 * TADC
NR
Resolution
12
-
Bit
[*1]
FADC
ADC Clock frequency
4
MHz
1/TADC
TSMP
=
TSMP
Sampling Time
Conversion time
1
-
-
256
272
1/FADC ( EXTSMPT(ADC_ESMPCTL[7:0])
+ 1 ) * TADC
TCONV
17
1/FADC TCONV = TSMP + 16 * TADC
FSPS = FADC / TCONV
[*1]
FSPS
Sampling Rate
0.236
-
2
MSPS
EXTSMPT(ADC_ESMPCTL[7:0])
= 0
TEN
Enable to ready time
20
-2
-
-
-
μs
VREF = AVDD
,
+2
LSB
except TSSOP20 and TSSOP28
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
VREF = AVDD
-4
-1
+4
+2
+4
+4
+4
+4
+10
+4
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TSSOP20 and TSSOP28
VREF = AVDD
,
-
-
-
-
except TSSOP20 and TSSOP28
DNL[*1]
VREF = AVDD
-1
TSSOP20 and TSSOP28
VREF = AVDD
,
-4
except TSSOP20 and TSSOP28
[*1]
EG
VREF = AVDD
-10
-4
TSSOP20 and TSSOP28
VREF = AVDD
,
except TSSOP20 and TSSOP28
[*1]
EO
Offset error
T
VREF = AVDD
-4
TSSOP20 and TSSOP28
[*1]
EA
Absolute Error
VREF = AVDD,
-4
except TSSOP20 and TSSOP28
Feb 25, 2019
Page 250 of 274
Rev. 1.01
M031/M032
Min
Typ
Max
Unit
Symbol
Parameter
Test Conditions
VREF = AVDD
TSSOP20 and TSSOP28
-8
+8
LSB
ENOB[*1]
SINAD[*1]
SNR[*1]
Effective number of bits
-
-
-
-
-
-
-
-
TBD
TBD
TBD
TBD
-
bits FADC = 34 MHz
AVDD = VDD =VREF = 3.3 V
Signal-to-noise and distortion ratio
Signal-to-noise ratio
-
Input Frequency = 20 kHz
TA = 25 °C
-
dB
THD[*1]
Total harmonic distortion
Internal Capacitance
-
2.9
-
[*1]
CIN
pF
kΩ
kΩ
[*1]
RIN
Internal Switch Resistance
External input impedance
2
[*1]
REX
-
50
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
ꢙ
ꢖꢗꢘ ꢃꢄ
ꢠꢄꢖꢐꢜ
ꢚꢏꢛ ꢄꢇꢄꢓꢐꢜ ꢄꢇ ꢝꢞꢄꢈꢟꢜꢋꢅ
ꢍ
VDD
EADC_CHx
RIN
REX
12-bit
Converter
VEX
CIN
CEX
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
Feb 25, 2019
Page 251 of 274
Rev. 1.01
M031/M032
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Feb 25, 2019
Page 252 of 274
Rev. 1.01
M031/M032
8.5.4
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical
values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Min
2.2
-40
-
Typ
-
Max Unit
Test Conditions
VDD = AVDD
Parameter
Analog supply voltage
Temperature
AVDD
3.6
105
45
V
°C
A
TA
-
IDD
Operating current
30
1/2 AVDD
AVDD -0.3
[*2]
VCM
Input common mode voltage range
0.35
[*2]
VDI
Differential input voltage sensitivity
Input offset voltage
Hysteresis window
DC voltage Gain
10
-
20
10
60
65
-
-
mV Hysteresis disable
mV Hysteresis disable,
[*2]
Voffset
20
[*2]
Vhys
-
140 mV
Av[*1]
45
-
75
400
350
5
dB
nS
uS
%
[*2]
Td
Propagation delay
Setup time
[*2]
TSetup
-
-
[*2]
ACRV
CRV output voltage
Unit resistor value
Setup time
-5
-
-
AVDD x (1/6+CRVCTL/24)
[*2]
RCRV
4.2
-
-
kΩ
[*2]
TSETUP_CRV
-
350
45
µS CRV output voltage settle to ±5%
[*2]
IDD_CRV
Operating current
-
30
A
Note:
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production
Table 8.5-2 ACMP Characteristics
Feb 25, 2019
Page 253 of 274
Rev. 1.01
M031/M032
8.6
Communications Characteristics
SPI Dynamic Characteristics
8.6.1
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
24
Unit
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
24
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tDH
5
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
-
8.5
Note:
1. Guaranteed by design.
Table 8.6-1 SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-1 SPI Master Mode Timing Diagram
Feb 25, 2019
Page 254 of 274
Rev. 1.01
M031/M032
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
16
Unit
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
16
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
1
TSPICLK
+ 2ns
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSS
Slave select setup time
ns
1
TSPICLK
+ 3ns
-
-
-
-
1
tSH
tDS
tDH
Slave select hold time
ns
TSPICLK
Data input setup time
Data input hold time
1.5
3.5
-
-
-
-
-
-
-
ns
ns
17.5
25
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
ns
-
Note:
1. Guaranteed by design.
Table 8.6-2 SPI Slave Mode Characteristics
Feb 25, 2019
Page 255 of 274
Rev. 1.01
M031/M032
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-2 SPI Slave Mode Timing Diagram
Feb 25, 2019
Page 256 of 274
Rev. 1.01
M031/M032
8.6.2
SPI - I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min[*1]
Max[*1]
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
80
80
2
-
-
Master fPCLK = 48 MHz, data: 24 bits, audio
frequency = 128 kHz
6
-
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
2
WS setup time
24
0
-
WS hold time
-
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Note:
10
7
7
4
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
25
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
4
-
0
1. Guaranteed by design.
Table 8.6-3 I2S Characteristics
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-3 I2S Master Mode Timing Diagram
Feb 25, 2019
Page 257 of 274
Rev. 1.01
M031/M032
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-4 I2S Slave Mode Timing Diagram
Feb 25, 2019
Page 258 of 274
Rev. 1.01
M031/M032
8.6.3
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-4 I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-5 I2C Timing Diagram
Feb 25, 2019
Page 259 of 274
Rev. 1.01
M031/M032
8.6.4
USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
24
Unit
Test Conditions
-
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
FSPICLK
SPI clock frequency
MHz
1/ TSPICLK
-
24
ns
ns
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tDH
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
5
tV
Data output valid time
-
8.5
Note:
1. Guaranteed by design.
Table 8.6-5 USCI-SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram
Feb 25, 2019
Page 260 of 274
Rev. 1.01
M031/M032
Symbol
FSPICLK
Parameter
Min[*1]
Typ
Max[*1] Unit
Test Conditions
-
-
-
7
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
SPI clock frequency
MHz
7
1/ TSPICLK
-
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
1
TSPICLK
+ 2ns
-
-
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSS
Slave select setup time
ns
1
TSPICLK
+ 3ns
-
-
-
1
tSH
tDS
tDH
Slave select hold time
-
ns
TSPICLK
Data input setup time
Data input hold time
2
4
-
-
-
-
-
-
ns
ns
-
65
70
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1.8 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tV
Data output valid time
ns
-
Note:
1. Guaranteed by design.
Table 8.6-6 USCI-SPI Slave Mode Characteristics
Feb 25, 2019
Page 261 of 274
Rev. 1.01
M031/M032
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram
Feb 25, 2019
Page 262 of 274
Rev. 1.01
M031/M032
8.6.5
USCI-I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-7 USCI-I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-8 USCI-I2C Timing Diagram
Feb 25, 2019
Page 263 of 274
Rev. 1.01
M031/M032
8.6.6
USB Characteristics
8.6.6.1 USB Full-Speed Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
USB full speed transceiver
operating voltage
VBUS
4.4
5.25
V
USB Internal power regulator
output
[*2]
VDD33
3.0
3.3
3.6
V
VIH
VIL
VDI
Input high (driven)
Input low
2.0
-
-
-
-
-
0.8
-
V
V
V
-
-
Differential input sensitivity
0.2
|(USB_D+) - (USB_D-)|
Differential
VCM
0.8
-
2.5
V
Includes VDI range
common-mode range
Single-ended receiver threshold
Receiver hysteresis
0.8
-
-
2.0
-
V
mV
V
-
-
-
-
-
-
VSE
200
VOL
VOH
VCRS
RPU
Output low (driven)
0
-
-
-
-
0.3
3.6
2.0
1.9
Output high (driven)
2.8
1.3
1.19
V
Output signal cross voltage
Pull-up resistor
V
kΩ
Termination voltage for
upstream port pull-up (RPU)
VTRM
3.0
-
3.6
V
[*3]
ZDRV
Driver output resistance
Transceiver capacitance
-
-
10
-
-
Ω
Steady state drive
Pin to GND
CIN
26
pF
Note:
1. Guaranteed by characterization result, not tested in production.
2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the
USB_VDD33_CAP pin and the closest GND pin of the device.
3. USB_D+ and USB_D- must be connected with series resistors to fit USB Full-speed spec request (28 ~ 44Ω).
Table 8.6-8 USB Full-Speed Characteristics
8.6.6.2 USB Full-Speed PHY characteristics
Symbol
TFR
Parameter
Min[*1]
Typ
Max[*1]
20
Unit
ns
Test Conditions
CL=50 pF
rise time
fall time
4
4
-
-
-
TFF
20
ns
CL=50 pF
TFRFF
rise and fall time matching
90
111.11
%
TFRFF = TFR/TFF
Note:
1. Guaranteed by characterization result, not tested in production.
Table 8.6-9 USB Full-Speed PHY Characteristics
Feb 25, 2019
Page 264 of 274
Rev. 1.01
M031/M032
8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.8
20
60
7
Max
Unit
V
Test Condition
[1]
VFLA
1.62
1.98
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
-
-
-
-
-
-
-
-
-
-
ms
µs
TA = 25°C
mA
mA
mA
IDD2
Program current
Erase current
8
IDD3
12
NENDUR
Endurance
20,000
-
-
-
-
cycles[2]
year
TJ = -40°C~125°C
20 kcycle[3] TA = 55°C
20 kcycle[3] TA = 85°C
20 kcycle[3] TA = 125°C
65
10
4
-
-
-
TRET
Data retention
year
year
Note:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Feb 25, 2019
Page 265 of 274
Rev. 1.01
M031/M032
9 PACKAGE DIMENSIONS
9.1 TSSOP 20 (4.4x6.5x0.9 mm)
Feb 25, 2019
Page 266 of 274
Rev. 1.01
M031/M032
9.2
TSSOP 28 (4.4x9.7x1.0 mm)
Feb 25, 2019
Page 267 of 274
Rev. 1.01
M031/M032
9.3
QFN 33L (4X4x0.8 mm Pitch:0.40 mm)
Feb 25, 2019
Page 268 of 274
Rev. 1.01
M031/M032
9.4
LQFP 48L (7x7x1.4 mm Footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
L
0.024 0.030
0.45
0
0.039
0.004
7
1
L
Y
0.10
7
0
0
Feb 25, 2019
Page 269 of 274
Rev. 1.01
M031/M032
9.5
LQFP 64L (7x7x1.4 mm Footprint 2.0 mm)
Feb 25, 2019
Page 270 of 274
Rev. 1.01
M031/M032
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
CAN
DAP
DES
ADC
EBI
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~32 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
38.4 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
Feb 25, 2019
Page 271 of 274
Rev. 1.01
M031/M032
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
Feb 25, 2019
Page 272 of 274
Rev. 1.01
M031/M032
11 REVISION HISTORY
Date
Revision
Description
2018.12.24
1.00
Initial version.
1. Modified ISP ROM size in section 3.3.1 and section 3.3.2
2019.02.25
1.01
2. Modified HIRC trim reference clock in section 6.2.8 and section 6.24.2.
Feb 25, 2019
Page 273 of 274
Rev. 1.01
M031/M032
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Feb 25, 2019
Page 274 of 274
Rev. 1.01
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