M0516LDE [NUVOTON]
ARM® Cortex®-M0 32-bit Microcontroller;
| 型号： | M0516LDE |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总86页 (文件大小：1680K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M051 DN/DE
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
M051 DN/DE Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Oct. 05, 2015
Page 1 of 86
Rev 1.03
M051 DN/DE
Table of Contents
1 GENERAL DESCRIPTION···················································································································· 7
2 FEATURES············································································································································· 8
3 ABBREVIATIONS································································································································ 12
3.1
List of Abbreviations ···················································································································12
4 PARTS INFORMATION AND PIN CONFIGURATION····································································· 14
4.1
4.2
4.3
NuMicro® M051 Series M05xxDN Selection Guide ·······························································14
NuMicro® M051 Series M05xxDE Selection Guide································································15
Pin Diagrams ·······························································································································17
4.3.1 QFN 33-pin···································································································································17
4.3.2 LQFP 48-pin·································································································································18
4.4
Pin Description ····························································································································19
5 BLOCK DIAGRAM······························································································································· 22
6 FUNCTIONAL DESCRIPTION············································································································ 23
6.1
ARM® Cortex® -M0 Core·············································································································23
6.2
System Manager·························································································································25
6.2.1 Overview·······································································································································25
6.2.2 System Reset·······························································································································25
6.2.3 System Power Architecture ·······································································································26
6.2.4 System Memory Map··················································································································27
6.2.5 Whole System Memory Mapping······························································································29
6.2.6 System Timer (SysTick)·············································································································30
6.2.7 Nested Vectored Interrupt Controller (NVIC) ··········································································31
6.3
Clock Controller···························································································································34
6.3.1 Overview·······································································································································34
6.3.2 System Clock and SysTick Clock ·····························································································37
6.3.3 Power-down Mode Clock ···········································································································38
6.3.4 Frequency Divider Output··········································································································38
6.4
Flash Memory Controller (FMC) ·······························································································40
6.4.1 Overview·······································································································································40
6.4.2 Features········································································································································40
6.5
External Bus Interface (EBI)······································································································41
6.5.1 Overview·······································································································································41
6.5.2 Features········································································································································41
6.6
General Purpose I/O (GPIO)·····································································································42
6.6.1 Overview·······································································································································42
6.6.2 Features········································································································································42
6.7
Timer Controller (TMR) ··············································································································43
6.7.1 Overview·······································································································································43
6.7.2 Features········································································································································43
6.8
PWM Generator and Capture Timer (PWM)···········································································44
6.8.1 Overview·······································································································································44
6.8.2 Features········································································································································45
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6.9
Watchdog Timer (WDT)·············································································································46
6.9.1 Overview·······································································································································46
6.9.2 Features········································································································································46
6.10 Window Watchdog Timer (WWDT) ··························································································47
6.10.1 Overview·····································································································································47
6.10.2 Features······································································································································47
6.11 UART Controller (UART) ···········································································································48
6.11.1 Overview·····································································································································48
6.11.2 Features······································································································································48
6.12 I2C Serial Interface Controller (I2C) ··························································································49
6.12.1 Overview·····································································································································49
6.12.2 Features······································································································································49
6.13 Serial Peripheral Interface (SPI)·······························································································50
6.13.1 Overview·····································································································································50
6.13.2 Features······································································································································50
6.14 Analog-to-Digital Converter (ADC)···························································································51
6.14.1 Overview·····································································································································51
6.14.2 Features······································································································································51
6.15 Analog Comparator (ACMP) ·····································································································52
6.15.1 Overview·····································································································································52
6.15.2 Features······································································································································52
6.16 Hardware Divider (HDIV) (M05xxDN/DE Only) ······································································53
6.16.1 Overview·····································································································································53
6.16.2 Features······································································································································53
7 APPLICATION CIRCUIT ····················································································································· 54
8 M05XXDN ELECTRICAL CHARACTERISTICS··············································································· 55
8.1
8.2
8.3
Absolute Maximum Ratings·······································································································55
DC Electrical Characteristics·····································································································56
AC Electrical Characteristics·····································································································60
8.3.1 External Input Clock····················································································································60
8.3.2 External 4~24 MHz High Speed Crystal (HXT) ······································································60
8.3.3 Typical Crystal Application Circuits ··························································································61
8.3.4 22.1184 MHz Internal High Speed RC Oscillator (HIRC) ·····················································61
8.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC) ··································································61
8.4
Analog Characteristics ···············································································································62
8.4.1 12-bit SAR ADC···························································································································62
8.4.2 LDO & Power Management·······································································································64
8.4.3 Low Voltage Reset······················································································································64
8.4.4 Brown-out Detector·····················································································································64
8.4.5 Power-on Reset···························································································································65
8.4.6 Temperature Sensor···················································································································66
8.4.7 Comparator ··································································································································66
8.5
Flash DC Electrical Characteristics··························································································67
8.6
SPI Dynamic Characteristics·····································································································67
8.6.1 Dynamic Characteristics of Data Input and Output Pin·························································67
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9 M05XXDE ELECTRICAL CHARACTERISTICS ··············································································· 68
9.1
9.2
9.3
Absolute Maximum Ratings·······································································································68
DC Electrical Characteristics·····································································································69
AC Electrical Characteristics·····································································································73
9.3.1 External Input Clock····················································································································73
9.3.2 External 4~24 MHz High Speed Crystal (HXT) ······································································73
9.3.3 Typical Crystal Application Circuits ··························································································73
9.3.4 22.1184 MHz Internal High Speed RC Oscillator (HIRC) ·····················································74
9.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC) ··································································75
9.4
Analog Characteristics ···············································································································76
9.4.1 12-bit SAR ADC···························································································································76
9.4.2 LDO & Power Management·······································································································77
9.4.3 Low Voltage Reset······················································································································77
9.4.4 Brown-out Detector·····················································································································78
9.4.5 Power-on Reset···························································································································78
9.4.6 Temperature Sensor···················································································································80
9.4.7 Comparator ··································································································································80
9.5
Flash DC Electrical Characteristics··························································································81
9.6
SPI Dynamic Characteristics·····································································································82
9.6.1 Dynamic Characteristics of Data Input and Output Pin·························································82
PACKAGE DIMENSIONS ··········································································································· 83
10.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm) ···············································································83
10.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) ··························································84
REVISION HISTORY ··················································································································· 85
10
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LIST OF FIGURES
Figure 4-1 NuMicro® M051 DN/DE Series Naming Rule ............................................................... 16
Figure 4-2 NuMicro® M051 DN/DE Series QFN-33 Pin Diagram .................................................. 17
Figure 4-3 NuMicro® M051 DN/DE Series LQFP-48 Pin Diagram................................................. 18
Figure 5-1 NuMicro® M051 DN/DE Series Block Diagram............................................................. 22
Figure 6-1 Functional Block Diagram............................................................................................. 23
Figure 6-2 NuMicro® M051 DN/DE Series Power Architecture Diagram....................................... 26
Figure 6-3 Clock Generator Block Diagram................................................................................... 34
Figure 6-4 Clock Source Controller Overview (1/2) ....................................................................... 35
Figure 6-5 Clock Source Controller Overview (2/2) ....................................................................... 36
Figure 6-6 System Clock Block Diagram ....................................................................................... 37
Figure 6-7 SysTick clock Control Block Diagram........................................................................... 37
Figure 6-8 Clock Source of Frequency Divider .............................................................................. 38
Figure 6-9 Block Diagram of Frequency Divider............................................................................ 39
Figure 8-1 M05xxDN Typical Crystal Application Circuit ............................................................... 61
Figure 8-2 Power-up Ramp Condition............................................................................................ 65
Figure 9-1 M05xDE Typical Crystal Application Circuit ................................................................. 74
Figure 9-2 HIRC Accuracy vs. Temperature.................................................................................. 75
Figure 9-3 Power-up Ramp Condition............................................................................................ 79
Oct. 05, 2015
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M051 DN/DE
LIST OF TABLES
Table 1-1 M05xxBN, M05xxDN and M05xxDE Difference List........................................................ 7
Table 3-1 List of Abbreviations....................................................................................................... 13
Table 6-1 Address Space Assignments for On-Chip Modules ...................................................... 28
Table 6-2 Exception Model ............................................................................................................ 32
Table 6-3 System Interrupt Map Vector Table............................................................................... 33
Table 6-4 Vector Figure Format..................................................................................................... 33
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M051 DN/DE
1
GENERAL DESCRIPTION
The NuMicro® M051 DN/DE series 32-bit microcontroller is embedded with ARM® Cortex® -M0
core for industrial control and applications which need rich communication interfaces. The
NuMicro® M051 DN/DE series includes the following part numbers: M052xDN/xDE,
M054xDN/xDE, M058xDN/xDE and M0516xDN/xDE.
The NuMicro® M051 DN/DE series can run up to 50 MHz and operate at 2.5V ~ 5.5V, -40℃ ~
85℃, while M05xxDE operates at -40℃ ~ 105℃, and thus can afford to support a variety of
industrial control and applications which need high CPU performance. The NuMicro® M051
DN/DE series offers 8/16/32/64 KB flash, 4 KB Data Flash, 4 KB flash for the ISP, and 4 KB
SRAM.
Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer,
UART, SPI, I2C, PWM, ADC, Watchdog Timer, Window Watchdog Timer, Analog Comparator and
Brown-out Detector, have been incorporated into The NuMicro® M051 DN/DE series in order to
reduce component count, board space and system cost. These useful functions make The
NuMicro® M051 DN/DE series powerful for a wide range of applications.
Additionally, the NuMicro® M051 DN/DE series is equipped with ISP (In-System Programming)
and ICP (In-Circuit Programming) functions, and IAP (In-Application Programming), which allow
the user to update the program memory without removing the chip from the actual end product.
Item
M05xxBN
M05xxDN
M05xxDE
-40℃ ~ 85℃
-40℃ ~ 85℃
-40℃ ~ 105℃
Operating Temperature
Hardware Divider
IAP Mode
●
●
●
4
●
●
●
4
-
-
Window WDT
-
Analog Comparators
2
Configurable I/O mode after
POR
●
●
-
2
2
I2C
1
(Supports Wake-up)
(Supports Wake-up)
-
Only Supports HCLK -
Supports HCLK and -
Supports HCLK and
PLL as SPI clock source
as SPI clock source
PLL as SPI clock source
SPI
-
No FIFO
-
4-level FIFO
-
4-level FIFO
-
PWM can trigger -
PWM can trigger
ADC conversion
PWM and ADC
PWM cannot trigger ADC
ADC conversion
Table 1-1 M05xxBN, M05xxDN and M05xxDE Difference List
Oct. 05, 2015
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M051 DN/DE
2
FEATURES
Core
ARM® Cortex® -M0 core running up to 50 MHz
One 24-bit system timer
Supports Low Power Sleep mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints
Provides hardware divider and supports signed 32-bit dividend, 16-bit divisor operation
Wide Operating Voltage Range: 2.5V to 5.5V
Memory
8KB/16KB/32KB/64KB Flash for program memory (APROM)
4KB Flash for data memory (Data Flash)
4KB Flash for loader (LDROM)
4KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
22.1184 MHz internal oscillator
4~24 MHz external crystal input
10 kHz low-power oscillator for Watchdog Timer and wake-up in Sleep mode
PLL allows CPU operation up to the maximum 50 MHz
I/O Port
Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink I/O mode
Configurable I/O mode after POR
Timer
Provides four channel 32-bit timers; one 8-bit pre-scale counter with 24-bit up-timer for
each timer
Independent clock source for each timer
24-bit timer value is readable through TDR (Timer Data Register)
Provides One-shot, Periodic and Toggle operation modes
Provides event counter function
Provides external capture/reset counter function
Two more timer clock sources from external trigger and internal 10 kHz
TIMER wake-up function
External capture input source selected from ACMP or TxEX
Toggle mode output pins selected from TxEX or TMx
Inter-Timer trigger mode
WDT (Watchdog Timer)
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M051 DN/DE
Multiple clock sources
Supports wake-up from Power-down or Sleep mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period time can be selected
WWDT (Window Watchdog Timer)
6-bit down counter with 11-bit pre-scale for wide range window selected
PWM
Up to four built-in 16-bit PWM generators, providing eight PWM outputs or four
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for
each PWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers with rising/falling capture inputs
Supports capture interrupt
Internal 10 kHz to PWM clock source
Polar inverse function
Center-aligned type function
Timer duty interrupt enable function
Two kinds of PWM interrupt period/duty type selection
Period/duty trigger ADC function
PWM Timer synchronous start function
UART
Up to two sets of UART devices
Programmable baud-rate generator
Buffered receiver and transmitter, each with 15 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
Supports LIN function
SPI
Up to two sets of SPI devices
Supports Master/Slave mode
Full-duplex synchronous serial data transfer
Provides 3 wire function
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte Suspend mode in 32-bit transmission
PLL clock source
4-level depth FIFO buffer for better performance and flexibility in SPI Burst Transfer
mode
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M051 DN/DE
I2C
Up to two sets of I2C modules
Supports Master/Slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allow versatile rate control
Supports multiple address recognition (four slave addresses with mask option)
ADC
12-bit SAR ADC
Up to 8-ch single-ended input or 4-ch differential input
Supports Single mode/Burst mode/Single-cycle Scan mode/Continuous Scan mode
Supports 2’ complement/un-signed format in differential mode conversion results
Each channel with an individual result register
Supports conversion value monitoring (or comparison) for threshold voltage detection
Conversion started either by software trigger or external pin trigger
A/D conversion started by PWM center-aligned trigger or edge-aligned trigger
PWM trigger delay function
Supports conversion result with signed format in Differential input and Burst mode
Analog Comparator
Up to four sets of Comparator analog modules
External input or internal band-gap voltage selectable at negative node
Interrupt when compared results change
Power-down wake-up
EBI (External Bus Interface) for external memory-mapped device access
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8-bit or 16-bit data width
Supports byte-write in 16-bit data width
ISP (In-System Programming) and ICP (In-Circuit Programming)
IAP (In-Application Programming)
One built-in temperature sensor with 1℃ resolution
BOD (Brown-out Detector)
With 4 levels: 4.4V/3.7V/2.7V/2.2V
Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Threshold voltage level: 2.0V
Operating Temperature:
Oct. 05, 2015
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M051 DN/DE
M05xxDN: -40℃~85℃
M05xxDE: -40℃~105℃
Packages:
Green package (RoHS)
48-pin LQFP, 33-pin QFN
Oct. 05, 2015
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M051 DN/DE
3
ABBREVIATIONS
3.1 List of Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
CAN
DAP
DES
EBI
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital Input/Output
SDIO
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M051 DN/DE
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TMR
UART
UCID
USB
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
Oct. 05, 2015
Page 13 of 86
Rev 1.03
M051 DN/DE
4
PARTS INFORMATION AND PIN CONFIGURATION
4.1 NuMicro® M051 Series M05xxDN Selection Guide
Connectivity
M052LDN
M052ZDN
M054LDN
M054ZDN
M058LDN
M058ZDN
M0516LDN
M0516ZDN
8
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
40
24
40
24
40
24
40
24
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
1
2
1
2
1
2
1
2
2
2
2
2
2
2
2
4
3
4
3
4
3
4
3
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP48
QFN33
LQFP48
QFN33
LQFP48
QFN33
LQFP48
QFN33
-40 to +85
8
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
16
16
32
32
64
64
Table 5-2 NuMicro® M051 Series M05xxDN Product Selection Guide
Oct. 05, 2015
Page 14 of 86
Rev 1.03
M051 DN/DE
4.2 NuMicro® M051 Series M05xxDE Selection Guide
Connectivity
M052LDE
M052ZDE
M054LDE
M054ZDE
M058LDE
M058ZDE
M0516LDE
M0516ZDE
8
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
40
24
40
24
40
24
40
24
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
1
2
1
2
1
2
1
2
2
2
2
2
2
2
2
4
3
4
3
4
3
4
3
8
5
8
5
8
5
8
5
8
5
8
5
8
5
8
5
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP48
QFN33
LQFP48
QFN33
LQFP48
QFN33
LQFP48
QFN33
-40 to +105
8
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
16
16
32
32
64
64
Table 5-2 NuMicro® M051 Series M05xxDE Product Selection Guide
Oct. 05, 2015
Page 15 of 86
Rev 1.03
M051 DN/DE
M0
5X - X X X
CPU core
ARM Cortex M0
Part Number
Temperature
52:ꢀ08 KB Flash ROM
54:ꢀ16 KB Flash ROM
58:ꢀ32 KB Flash ROM
516: 64 KB Flash ROM
℃
N: - 40 ~ +85
℃
℃
℃
E: - 40 ~ +105
Reserved
Package
Ｌ: LQFP48
Ｚ: QFN33
Figure 4-1 NuMicro® M051 DN/DE Series Naming Rule
Oct. 05, 2015
Page 16 of 86
Rev 1.03
M051 DN/DE
4.3 Pin Diagrams
4.3.1 QFN 33-pin
32 31 30 29 28 27 26 25
24
23
22
ACMP0_P, AIN5, P1.5
P0.4, SPISS1
P0.5, MOSI_1
P0.6, MISO_1
1
2
3
4
5
6
nRST
ACMP1_N, RXD, P3.0
AVSS
ACMP1_P, TXD, P3.1
T0EX, STADC, nINT0, P3.2
SDA, T0, P3.4
21 P0.7, SCLK1
QFN 33-Pin
P4.7, ICE_DAT
20
P4.6, ICE_CLK
19
18
17
P2.6, PWM6, ACMP1_O
P2.5, PWM5, SDA1
7
8
33 VSS
CKO, SCL, T1, P3.5
9
10 11 12 13 14 15 16
Top transparent view
Figure 4-2 NuMicro® M051 DN/DE Series QFN-33 Pin Diagram
Oct. 05, 2015
Page 17 of 86
Rev 1.03
M051 DN/DE
4.3.2 LQFP 48-pin
P4.1, PWM1, T3EX
P0.4, AD4, SPISS1
P0.5, AD5, MOSI_1
P0.6, AD6, MISO_1
ACMP0_P, MOSI_0, AIN5, P1.5
ACMP2_N, MISO_0, AIN6, P1.6
1
36
35
34
33
32
31
30
29
28
27
26
25
2
3
ACMP2_P, SPICLK0, AIN7, P1.7
nRST
4
P0.7, AD7, SPICLK1
P4.7, ICE_DAT
5
ACMP1_N, RXD, P3.0
AVSS
6
48-pin LQFP
P4.6, ICE_CLK
ACMP1_P, TXD, P3.1
T0EX, STADC, nINT0, P3.2
T1EX, MCLK, nINT1, P3.3
SDA0, T0, P3.4
7
P4.5, ALE, SDA1
8
P4.4, nCS, SCL1
9
P2.7, AD15, PWM7
P2.6, AD14, PWM6, ACMP1_O
P2.5, AD13, PWM5, SDA1
10
11
12
CKO, SCL0, T1, P3.5
PWM3, P4.3
Figure 4-3 NuMicro® M051 DN/DE Series LQFP-48 Pin Diagram
Oct. 05, 2015
Page 18 of 86
Rev 1.03
M051 DN/DE
4.4 Pin Description
Pin Number
Symbol
Alternate Function
Type[1]
Description
QFN33 LQFP48
1
2
3
I
External 4~24 MHz (high speed) crystal input pin.
External 4~24 MHz (high speed) crystal output pin.
11
16
XTAL1
(ST)
10
27
15
41
XTAL2
VDD
O
P
Power supply to I/O ports and LDO source for internal PLL
and digital circuit.
12
33
28
4
17
VSS
P
Ground pin for digital circuit.
42
6
AVDD
AVSS
P
P
Power supply to internal analog circuit.
Analog Ground pin for analog circuit.
LDO output pin.
13
18
LDO_CAP
nRST
P
Note: This pin needs to be connected with a 1uF
capacitor.
The nRST pin is a Schmitt trigger input pin for hardware
device reset. A “Low” on this pin for 768 clock counter of
I
Internal RC 22M while the system clock is running will
reset the device. The nRST pin has an internal pull-up
resistor allowing power-on reset by simply connecting an
external capacitor to GND.
2
4
(ST)
TXD1[2],
The P0.0 ~ P0.7 pins are called Port 0. Port 0 is a general
purpose I/O port, which can be configured as Input,
Output, Quasi Bi-direction and Open-drain mode.
26
25
40
39
P0.0
P0.1
CTS1
RTS1
AD0
AD1
I/O
/O
ACMP3_P
Port 0 supports multi-function pins, including CTS1, RTS1,
CTS0, RTS0, SPISS1, MOSI_1, MISO_1, SPICLK1, AD0
~ AD7, TXD1, RXD1, TXD, RXD, ACMP3_P, and
ACMP3_N.
RXD1[2],
ACMP3_N
TXD[2]
RXD[2]
I/O
I/O
I/O
I/O
I/O
AD0 ~ AD7 belong to EBI function for external memory
accessing.
NC
NC
24
38
37
35
34
33
P0.2
P0.3
P0.4
P0.5
P0.6
CTS0
RTS0
AD2
AD3
AD4
AD5
AD6
The SPISS1, MOSI_1, MISO_1, and SPICLK1 pins are for
SPI function.
The CTS0 and CTS1 pins are clear to send input pin for
UART0/1.
SPISS1
MOSI_1
MISO_1
The RTS0 and RTS1 pins are Request to Send output pin
for UART0/1.
23
The RXD and TXD pins are for UART0 function.
The RXD1 and TXD1 pins are for UART1 function.
22
The ACMP3_N and ACMP3_P pins are for ACMP3
negative/positive inputs.
21
32
P0.7
SPICLK1 AD7
I/O
29
43
44
P1.0
P1.1
T2
T3
AIN0
AIN1
nWRL
nWRH
I/O The P1.0 ~ P1.7 pins are called Port 1. Port 1 is a general
purpose I/O port, which can be configured as Input,
Output, Quasi-bidirectional and Open-drain mode.
NC
I/O
Oct. 05, 2015
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M051 DN/DE
Port 1 supports multi-function pins, including T2, T3,
30
31
32
1
45
46
47
1
P1.2
P1.3
P1.4
P1.5
P1.6
RXD1[2]
TXD1[2]
AIN2
AIN3
I/O
I/O
RXD1, TXD1, SPISS0, MOSI_0, MISO_0, SPICLK0, AIN0
~ AIN7, nWRL, nWRH, ACMP0_N, ACMP0_P,
ACMP2_N, and ACMP2_P.
The SPISS0, MOSI_0, MISO_0, and SPICLK0 pins are for
SPI function.
SPISS0 AIN4 ACMP0_N I/O
MOSI_0 AIN5 ACMP0_P I/O
MISO_0 AIN6 ACMP2_N I/O
The AIN0 ~ AIN7 pins are for 12 bits ADC function.
The RXD1 and TXD1 pins are for UART1 function.
The nWRL and nWRH pins are for low/high byte write
enable output in 16-bit data width of EBI.
NC
2
The ACMP0_N and ACMP0_P pins are for ACMP0
negative/positive inputs.
The ACMP2_N and ACMP2_P pins are for ACMP2
negative/positive inputs.
NC
3
P1.7
SPICLK0 AIN7 ACMP2_P I/O
The T2 and T3 pins are for Timer2/3 external even
counter input and toggle mode output.
NC
NC
14
15
16
17
18
NC
3
19
20
21
22
23
25
26
27
5
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
PWM0[2] AD8
PWM1[2] AD9
PWM2[2] AD10
PWM3[2] AD11
I/O The P2.0 ~ P2.7 pins are called Port 2. Port 2 is a general
purpose I/O port, which can be configured as Input,
Output, Quasi-bidirectional and Open-drain mode.
I/O
Port 2 supports multi-function pins, including PWM0 ~
PWM7, AD8 ~ AD15, SCL1, SDA1 and ACMP1_O.
I/O
The PWM0~PWM7 pins are for PWM function in the
LQFP48 package.
I/O
AD8 ~ AD15 belong to EBI function for external memory
accessing.
PWM4
PWM5
PWM6
PWM7
RXD[2]
TXD[2]
AD12
AD13
SCL1[2]
SDA1[2]
I/O
I/O
The SDA1 and SCL1 pins are for I2C1 function and both
of them are open-drain.
The ACMP1_O pin is the output of ACMP1.
AD14 ACMP1_O I/O
AD15 I/O
ACMP1_N I/O The P3.0 ~ P3.7 pins are called Port 3. Port 3 is a general
purpose I/O port, which can be configured as Input,
Output, Quasi-bidirectional and Open-drain mode.
5
7
ACMP1_P I/O
Port 3 supports multi-function pins, including RXD, TXD,
nINT0, nINT1, T0, T1, nWR, nRD, STADC, MCLK, SDA,
6
8
nINT0 STADC
T0EX
T1EX
I/O
I/O
I/O
I/O
SCL, CKO, ACMP1_N, ACMP1_P, T0EX, T1EX,
ACMP0_O.
NC
7
9
nINT1
T0
MCLK
SDA
SCL
The RXD and TXD pins are for UART0 function.
The nINT0 and nINT1 pins are for external interrupt input.
10
11
13
The T0 and T1 pins are for Timer0/1 external even
counter input and toggle mode output.
8
T1
CKO[2]
The nWR, nRD and MCLK are for EBI function.
The STADC pin is for ADC external trigger input.
9
nWR
CKO ACMP0_O I/O
The SDA and SCL pins are for I2C function and both of
them are open-drain.
The CKO is clock output pin for clock monitor.
The ACMP1_N and ACMP1_P pins are for ACMP1
negative/positive inputs.
NC
NC
14
24
P3.7
nRD
I/O
The T0EX and T1EX pins are for external capture/reset
trigger input of Timer0/1.
The ACMP0_O pin is the output of Analog ACMP0.
P4.0
PWM0[2]
T2EX
I/O The P4.0 ~ P4.7 pins are called Port 4. Port 4 is a general
Oct. 05, 2015
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Rev 1.03
M051 DN/DE
purpose I/O port, which can be configured as Input,
Output, Quasi-bidirectional and Open-drain mode.
NC
NC
NC
NC
NC
19
36
48
12
28
29
30
31
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
PWM1[2]
PWM2[2]
PWM3[2]
nCS
T3EX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 3 supports multi-function pins, including PWM0 ~
PWM3, nCS, ALE, ICE_CLK, ICE_DAT, SCL1, SDA1,
T2EX and T3EX.
The PWM0 ~ PWM3 pins are for PWM function.
The nCS and ALE pins are for EBI function.
SCL1
SDA1
The ICE_CLK and ICE_DAT pins are for Serial Wire
Debug Interface.
The SDA1 and SCL1 pins are for I2C1 function and both
of them are open-drain.
ALE
ICE_CLK
ICE_DAT
The T2EX and T3EX pins are for external capture/reset
trigger input of Timer2/3.
20
Note 1: I/O type description. I: Input, O: Output, I/O: Quasi-bidirectional, D: Open-drain, P: Power pins, ST: Schmitt trigger.
Note 2: The PWM0 ~ PWM3, RXD, TXD, RXD1, TXD1, SCL1, SDA1 and CKO can be assigned to different pins. However,
a pin function can only be assigned to a pin at the same time, i.e. software cannot assign RXD to P0.3 and P3.0 at the same
time.
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5
BLOCK DIAGRAM
Memory
PWM / Timer
Analog Interface
32-bit Timer x 4
LDROM
4 KB
APROM
64/32/16/8 KB
HDIV
EBI
Watchdog Timer
12-bit ADC x 8
ARM
Cortex-M0
50MHz
Window
Watchdog Timer
Analog
Comparator x 4
PWM/Capture
Timer x 8
SRAM
4 KB
DataFlash
4 KB
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 2
I/O Ports
General Purpose
I/O
LDO
Power On Reset
LVR
SPI x 2
I2C x 2
External Interrupt
Reset Pin
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
22.1184 MHz
Low Speed
Oscillator
10 kHz
Brownout
Detection
Figure 5-1 NuMicro® M051 DN/DE Series Block Diagram
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6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The following figure shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use of
pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
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NVIC:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and provides Ultra-low Power Sleep
mode
Debug support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Hardware Reset
Power-on Reset (POR)
Low level on the Reset Pin (nRST)
Watchdog Timer Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
MCU Reset - SYSRESETREQ(AIRCR[2])
Cortex® -M0 Core One-shot Reset - CPU_RST(IPRSTC1[1])
Chip One-shot Reset - CHIP_RST(IPRSTC1[0])
Note: ISPCON.BS keeps the original value after MCU Reset and CPU Reset.
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6.2.3 System Power Architecture
In this chip, the power distribution is divided into two segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies the power to the I/O pins and internal
regulator which provides a fixed 1.8 V power for digital operation.
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
as the digital power (VDD). The following figure shows the power distribution of the NuMicro® M051
DN/DE series.
Analog Comparator
AVDD
12-bit
SAR-ADC
Low
Voltage
Reset
Brown
Out
Detector
AVSS
Internal
22.1184 MHz and
10 kHz Oscillator
Temperature
Sensor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
POR18
POR50
5V to 1.8V
LDO
PLL
IO cell
GPIO Pins
PVSS
VDD VSS
M051 Series Power Distribution
Figure 6-2 NuMicro® M051 DN/DE Series Power Architecture Diagram
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6.2.4 System Memory Map
The NuMicro® M051 DN/DE series provides 4G-byte addressing space. The addressing space
assigned to each on-chip controllers are shown in the following table. The detailed register
definition, addressing space, and programming details will be described in the following sections
for each on-chip peripheral. The NuMicro® M051 DN/DE series only supports little-endian data
format.
Addressing Space
Token
Modules
Flash & SRAM Memory Space
0x0000_0000 – 0x0000_FFFF
0x2000_0000 – 0x2000_0FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (64 KB)
SRAM Memory Space (4 KB)
EBI Space (0x6000_0000 ~ 0x6001_FFFF)
0x6000_0000 – 0x6001_FFFF
EBI_BA
External Memory Space (128 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
0x5001_4000 – 0x5001_7FFF
GCR_BA
CLK_BA
System Global Control Registers
Clock Control Registers
INT_BA
Interrupt Multiplexer Control Registers
GPIO (P0~P4) Control Registers
Flash Memory Control Registers
EBI Control Registers
GPIO_BA
FMC_BA
EBI_CTL_BA
HDIV_BA
Hardware Divider Register
APB Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_00FF
0x4000_4100 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_FFFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x401D_0000 – 0x401D_3FFF
WDT_BA
Watchdog Timer Control Registers
Window Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
WWDT_BA
TMR01_BA
I2C0_BA
I2C0 Interface Control Registers
SPI0_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
SPI1_BA
PWMA_BA
UART0_BA
ACMP01_BA
ADC_BA
UART0 Control Registers
Analog Comparator 0/1 Control Registers
Analog-Digital-Converter (ADC) Control Registers
Timer2/Timer3 Control Registers
TMR23_BA
I2C1_BA
I2C1 Interface Control Registers
PWMB_BA
UART1_BA
ACMP23_BA
PWM4/5/6/7 Control Registers
UART1 Control Registers
Analog Comparator 2/3 Control Registers
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
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0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SYST_BA
NVIC_BA
SCB_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Block Registers
Table 6-1 Address Space Assignments for On-Chip Modules
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M051 DN/DE
6.2.5 Whole System Memory Mapping
M052/54/58/516
4 GB
0xFFFF_FFFF
|
Reserved
System Control
Reserved
EBI
System Control
System Control Block
External Interrupt Controller
System Timer Control
System Control Space
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_DFFF
|
0xE000_ED00
0xE000_E100
0xE000_E010
0xE000_E000
SCB_BA
NVIC_BA
SYST_BA
SCS_BA
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
Reserved
0x5020_0000
AHB peripherals
Hardw are Divider Control
EBI Control
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
0x5001_4000
0x5001_0000
0x5000_C000
0x5000_4000
0x5000_0300
0x5000_0200
0x5000_0000
HDIV_BA
EBI_CTL_BA
FLASH_BA
GPIO_BA
INT_BA
AHB
FMC
GPIO Control
Reserved
|
Interrupt Multiplexer Control
Clock Control
0x4020_0000
0x401F_FFFF
CLK_BA
System Global Control
GCR_BA
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
ACMPB Control
UART1 Control
PWM4/5/6/7 Control
I2C1 Control
Reserved
|
0x401D_0000
0x4015_0000
0x4014_0000
0x4012_0000
0x4011_0000
0x400E_0000
0x400D_0000
0x4005_0000
0x4004_0000
0x4003_4000
0x4003_0000
0x4002_0000
0x4001_0000
0x4000_4000
0x4000_4100
ACMP23_BA
UART1_BA
PWMB_BA
I2C1_BA
0x2000_1000
0x2000_0FFF
4 KB SRAM
(M052/M054/M058/M0516)
|
Timer2/Timer3 Control
ADC Control
TMR23_BA
ADC_BA
0.5 GB
0x2000_0000
0x1FFF_FFFF
ACMPA Control
UART0 Control
PWM0/1/2/3 Control
SPI1 Control
ACMP01_BA
UART0_BA
PWMA_BA
SPI1_BA
Reserved
|
0x0001_0000
0x0000_FFFF
0x0000_7FFF
0x0000_3FFF
0x0000_1FFF
0x0000_0000
SPI0 Control
SPI0_BA
64 KB on-chip Flash (M0516)
32 KB on-chip Flash (M058)
16 KB on-chip Flash (M054)
I2C Control
I2C0_BA
Timer0/Timer1 Control
WDT Control
TMR01_BA
WDT_BA
WWDT Control
WWDT_BA
8 KB on-chip Flash (M052)
0 GB
Oct. 05, 2015
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6.2.6 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.7 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.7.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro® M051 DN/DE series.
Software can set four levels of priority on some of these exceptions as well as on all interrupts.
The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”.
The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as
the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
3
-2
Hard Fault
Reserved
SVCall
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Reserved
12 ~ 13
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M051 DN/DE
PendSV
SysTick
14
15
Configurable
Configurable
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6-2 Exception Model
Interrupt
Number
(Bit In
Interrupt
Registers)
Power-
Down
Wakeup
Exception
Number
Vector
Address
Interrupt
Name
Source
Module
Interrupt Description
1-15
16
System exceptions
Brown-out low voltage detected
interrupt
0x40
0x44
0x48
0
1
2
BOD_INT
WDT_INT
EINT0
Brown-out
WDT
Yes
Yes
Yes
17
Watchdog Timer interrupt
External signal interrupt from P3.2
pin
18
GPIO
External signal interrupt from P3.3
pin
19
20
0x4C
0x50
3
4
EINT1
GPIO
GPIO
Yes
Yes
External signal interrupt from P0[7:0]
/ P1[7:0]
GP01_INT
External interrupt from
P2[7:0]/P3[7:0]/P4[7:0], except P32
and P33
21
0x54
5
GP234_INT
GPIO
Yes
PWM0, PWM1, PWM2 and PWM3
interrupt
22
23
0x58
0x5C
6
7
PWMA_INT
PWMB_INT
PWM0~3
PWM4~7
No
No
PWM4, PWM5, PWM6 and PWM7
interrupt
24
25
0x60
0x64
8
9
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
UART1_INT
SPI0_INT
SPI1_INT
Reserved
I2C0_INT
I2C1_INT
Reserved
TMR0
TMR1
TMR2
TMR3
UART0
UART1
SPI0
SPI1
-
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
UART1 interrupt
SPI0 interrupt
SPI1 interrupt
-
No
No
No
No
Yes
Yes
No
No
-
26
0x68
10
27
0x6C
11
28
0x70
12
29
0x74
13
30
0x78
14
31
0x7C
15
32-33
34
0x80-0x84
0x88
16-17
18
I2C0
I2C0 interrupt
I2C1 interrupt
-
Yes
Yes
-
35
0x8C
19
I2C1
36-40
0x90-0xA0
20-24
-
Analog Comparator 0 or Comparator
1 interrupt
41
0xA4
25
ACMP01_INT
ACMP0/1
Yes
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Analog Comparator 2 or Comparator
3 interrupt
42
43
44
0xA8
0xAC
0xB0
26
27
28
ACMP23_INT
Reserved
ACMP2/3
CLKC
Yes
Clock controller interrupt for chip
wake-up from Power-down state
PWRWU_INT
Yes
No
45
0xB4
29
ADC_INT
Reserved
ADC
-
ADC interrupt
-
46-47
0xB8-0xBC
30-31
Table 6-3 System Interrupt Map Vector Table
6.2.7.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Vector Number
Table 6-4 Vector Figure Format
6.2.7.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
Oct. 05, 2015
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit
Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC) to reduce
the overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
The clock generator consists of 4 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from external
4~24 MHz external high speed crystal (HXT) or 22.1184 MHz internal high speed
oscillator (HIRC)) (PLL FOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTL12M_EN (PWRCON[0])
HXT
XTAL1
XTAL2
PLL_SRC (PLLCON[19])
4~24 MHz HXT
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-3 Clock Generator Block Diagram
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HIRC
111
011
010
001
000
CPUCLK
HCLK
CPU
HDIV*
EBI
LIRC
PLL FOUT
Reserved
HXT
1/(HCLK_N+1)
ACMP0
ACMP1
PCLK
ACMP2*
ACMP3*
CLKSEL0[2:0]
I2C0
I2C1*
HIRC
FMC
HCLK
1
0
SPI0
SPI1
PLL FOUT
CLKSEL1[4:5]*
HIRC
11
10
01
00
HCLK
1/(ADC_N+1)
ADC
PLL FOUT
HXT
CLKSEL1[3:2]
HIRC
11
01
00
PLL FOUT
HXT
1/(UART_N+1)
UART 0-2
CLKSEL1[25:24]
LIRC
BOD
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-4 Clock Source Controller Overview (1/2)
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HIRC
111
101
011
Reserved
T0~T3**
TMR 0
TMR 1
TMR 2
TMR 3
HCLK
HXT
010
000
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
HIRC
HCLK
HXT
1/2
1/2
1/2
111
011
010
001
000
CPUCLK
1
0
SysTick
Reserved
HXT
SYST_CSR[2]
CLKSEL0[5:3]
HIRC
11
10
01
00
FDIV
HCLK
Reserved
HXT
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
CLKSEL2[7:2]
CLKSEL1[31:28]
LIRC
11
10
WWDT*
WDT
HCLK/2048
CLKSEL2[17:16]*
LIRC
11
10
01
HCLK
1/2048
Reserved
CLKSEL1[1:0]
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note1: T0 is for TMR0, T1 is for TMR1, T2 is for TMR2 and T3 is for TMR3.
Note2: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-5 Clock Source Controller Overview (2/2)
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6.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown below.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
PLL FOUT
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLK_N (CLKDIV[3:0])
PCLK
4~24 MHz HXT
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-6 System Clock Block Diagram
The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]. The block
diagram is shown below.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
HIRC
1/2
1/2
1/2
111
011
HCLK
STCLK
4~24 MHz HXT
Reserved
010
001
4~24 MHz HXT
000
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-7 SysTick clock Control Block Diagram
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6.3.3 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
10 kHz internal low speed oscillator clock
Peripherals Clock (when 10 kHz low speed oscillator is adopted as clock source)
6.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV [3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) set to 1, the frequency divider clock (FRQDIV_CLK) will bypass power-
of-2 frequency divider. The frequency divider clock will be output to CKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
22.1184 MHz
HIRC
11
HCLK
FRQDIV_CLK
10
01
00
10 kHz* LIRC
4~24 MHz HXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-8 Clock Source of Frequency Divider
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DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FSEL
(FRQDIV[3:0])
16 chained
divide-by-2 counter
FRQDIV_CLK
1/22
1/23
…...
1/215 1/216
DIVIDER1*
(FRQDIV[5])
1/2
000
000
0
1
:
16 to 1
MUX
0
1
:
CKO
111
111
0
1
Note1: DIVIDER1 = 1 is only available on M05xxDE.
Note2: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-9 Block Diagram of Frequency Divider
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The M05xxDN/DE are equipped with 64/32/16/8 Kbytes on chip embedded Flash memory for
application program (APROM) that can be updated through ISP registers. In-System-
Programming (ISP) and In-Application-Programming (IAP) enable user to update program
memory when chip is soldered on PCB. After chip power on Cortex® -M0 CPU fetches code from
APROM or LDROM decided by boot select (CBS) in CONFIG0. By the way, the M05xxDN/DE
also provide additional 4 Kbytes DATA Flash for user to store some application depended data
before chip power off in 64/32/16/8 Kbytes APROM model.
The M05xxDN/DE provides more settings in CONFIG0 to support more advanced functions,
including power-on with tri-state I/O, default to enable WDT after booting, enable WDT in Power-
down mode, and IAP functions.
6.4.2 Features
Runs up to 50 MHz with zero wait state for continuous address read access
64/32/16/8 Kbytes application program memory (APROM)
4 Kbytes in system programming (ISP) loader program memory (LDROM)
Fixed 4 Kbytes Data Flash
All embedded flash memory supports 512 bytes page erase
In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM
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6.5 External Bus Interface (EBI)
6.5.1 Overview
The NuMicro® M05xxDN/DE LQFP-48 package has an external bus interface (EBI) for access
external device.
To save the connections between external device and this chip, EBI supports address bus and
data bus multiplex mode which is differentiated by address latch enable signal.
6.5.2 Features
The External Bus Interface has the following functions:
Supports external devices with max. 64 KB size (8-bit data width) / 128 KB (16-bit data
width)
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and address
hold time (tAHD)
Supports address bus and data bus multiplex mode to save the address pins
Supports configurable idle cycle for different access condition: Write command finish (W2X),
Read-to-Read (R2R)
Supports zero address hold time with read/write operation and write buffer for write
operation to enhance read/write performance
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6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NuMicro® M05xxDN/DE has up to 40 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 40 pins are arranged in 5 ports named
as P0, P1, P2, P3 and P4. Each port has the maximum of 8 pins. Each of the 40 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each pin can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins is
stay in quasi-bidirectional mode and each port data register Px_DOUT[7:0] resets to 0x000_00FF.
Each I/O pin has a very weakly individual pull-up resistor which is about 110 k ~ 300 k for VDD
which is from 5.0 V to 2.5 V.
6.6.2 Features
Four I/O modes:
Input only with high impedance
Push-pull output
Open-drain output
Quasi-bidirectional TTL/Schmitt trigger input mode selected by Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function
Configurable default I/O mode of all pins after reset by CIOINI(CONFIG[10]) setting
CIOINI = 0, all GPIO pins in Input tri-state mode after chip reset
CIOINI = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
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6.7 Timer Controller (TMR)
6.7.1 Overview
The Timer Controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.7.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous counting
Time-out period = (Period time of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period time of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the input event from external counter pin (T0~T3)
24-bit capture value is readable through TCAP (Timer Capture Data Register)
Supports external capture pin (T0EX~T3EX) for interval measurement
Supports external capture pin (T0EX~T3EX) to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Supports internal capture triggered while internal ACMP output signal transition
Supports Inter-Timer trigger mode
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6.8 PWM Generator and Capture Timer (PWM)
6.8.1 Overview
The NuMicro® M051 DN/DE series has two sets of PWM groups supporting a total of four sets of
PWM generators, which can be configured as eight independent PWM outputs, PWM0~PWM7, or
as four complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) with 4 programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide eight independent PWM period interrupt flags set by hardware
when the corresponding PWM period down counter reaches 0. Each PWM period interrupt source
with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators
can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode
to output PWM waveform continuously.
When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;
the paired PWM period, duty and Dead-zone are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to figures below for the architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be loaded into the 16-bit down
counter/ comparator at the time down counter reaching 0. The double buffering feature avoids
glitch at PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-Timer
is set as Auto-reload mode when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically and then starts decreasing repeatedly. If the PWM-Timer is set as
one-shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-Timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must set the PWM-Timer before enabling the Capture feature. After capture
feature is enabled, the capture always latched PWM-counter to Capture Rising Latch Register
(CRLR) when input channel has a rising transition and latched PWM-counter to Capture Falling
Latch Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0
(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture
channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). The
capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source, read CRLRx/CFLRx (x = 0~3) to get capture value and finally write 1
to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0.
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6.8.2 Features
PWM function:
PWM group has two PWM generators. Each PWM generator supports one 8-bit prescaler, one
clock divider, two PWM-Timers (down counter), one dead-zone generator and two PWM outputs.
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4 complementary
PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting one 8-bit
prescaler, two clock dividers, two PWM-Timers, one Dead-zone generator and two PWM
outputs.
Up to 16-bit resolution
One-shot or Auto-reload mode
Edge-aligned type or Center-aligned type option
PWM trigger ADC start-to-conversion
Capture function:
Timing control logic shared with PWM generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLRx), one falling latch register (CFLRx)
and Capture interrupt flag (CAPIFx)
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6.9 Watchdog Timer (WDT)
6.9.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.9.2 Features
18-bit free running up counter for Watchdog Timer time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period is
104 ms ~ 26.3168 s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period 3/18/130/1026 * WDT_CLK
Supports to force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(CONFIG[31] Watchdog Enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function only if WDT clock source is selected
as 10 kHz
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6.10 Window Watchdog Timer (WWDT)
6.10.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period
to prevent software run to uncontrollable status by any unpredictable condition.
6.10.2 Features
6-bit down counter value (WWDTCVAL) and 6-bit compare window value (WINCMP) to
make the WWDT time-out window period flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of WWDT
counter
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6.11 UART Controller (UART)
6.11.1 Overview
The NuMicro® M05xxDN/DE provides two channels of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART, and support flow
control function. The UART Controller performs a serial-to-parallel conversion on data received
from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The
UART controller also supports IrDA SIR Function, LIN master/slave function and RS-485 function
mode. Each UART Controller channel supports seven types of interrupts.
6.11.2 Features
Full-duplex, asynchronous communications
Separate receive / transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control and flow control function (CTS, RTS) and
programmable RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UA_TOR [15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enable to program RTS pin to control RS-485
transmission direction directly
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6.12 I2C Serial Interface Controller (I2C)
6.12.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. There are two sets of I2C which supports Power-down wake-up function.
6.12.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down Wake-up function
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6.13 Serial Peripheral Interface (SPI)
6.13.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full-duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction
interface. The NuMicro® M051 DN/DE series contains up to two sets of SPI controllers performing
a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial
conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a
master or a slave device.
6.13.2 Features
Up to two sets of SPI controllers
Supports Master or Slave mode operation
Configurable transfer bit length
Provides FIFO buffers
Supports MSB or LSB first transfer
Supports byte reorder function
Supports byte or word suspend mode
Supports Slave 3-wire mode
SPI bus clock rate can be configured to equal the system clock rate
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6.14 Analog-to-Digital Converter (ADC)
6.14.1 Overview
The NuMicro® M05xxDN/DE contains one 12-bit successive approximation analog-to-digital
converter (SAR A/D converter) with eight input channels. The A/D converter supports four
operation modes: Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D
converter can be started by software, external pin (STADC/P3.2) or PWM trigger.
6.14.2 Features
Analog input voltage range: 0 ~ AVDD
12-bit resolution and 10-bit accuracy is guaranteed
Up to eight single-end analog input channels or 4 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Up to 760 kSPS sample rate
Four operation modes:
Single mode: A/D conversion is performed one time on a specified channel.
Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
Software Write 1 to ADST bit
External pin (STADC)
PWM trigger with optional start delay period
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Channel 7 supports 3 input sources: external analog voltage, internal band-gap voltage and
Internal temperature sensor output.
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6.15 Analog Comparator (ACMP)
6.15.1 Overview
The NuMicro® M05xxDN/DE contains up to four comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input greater than
negative input, otherwise the output is 0. Each comparator can be configured to generate interrupt
request when the comparator output value changes.
6.15.2 Features
Up to four sets of ACMP
Analog input voltage range: 0 ~ AVDD
Supports Hysteresis function
Supports ACMP output inverse Function (M05xxDE only)
Optional internal reference voltage source for each comparator negative input
Two interrupt vectors for the four analog comparators
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6.16 Hardware Divider (HDIV) (M05xxDN/DE Only)
6.16.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider
is a signed, integer divider with both quotient and remainder outputs.
6.16.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
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7
APPLICATION CIRCUIT
DVCC
[1]
CS
CLK
MISO
MOSI
AVCC
SPISS0
SPICLK0
MISO_0
AVDD
VDD
VDD
VSS
SPI Device
FB
DVCC
Power
MOSI_0
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
FB
AVSS
4.7K
CLK
DIO
SCL0
SDA0
VDD
I2C Device
VDD
VSS
ICE_CLK
ICE_DAT
SWD
Interface
nRST
VSS
20p
20p
64K x 16-bit
SRAM
LATCH
XTAL1
XTAL2
M05xxDN/DE
LQFP48
D
Q
Addr[15:0]
En
ALE
Crystal
4~24 MHz
crystal
nCE
nOE
nWE
nLB
nCS
nRD
nWR
nWRL
nWRH
EBI
AD[15:0]
nUB
DVCC
AD[15:0]
Data[15:0]
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
TXD
nRST
RXD
TXD
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
Note: For the SPI device, the M05xx chip supply
voltage must be equal to SPI device working
voltage. For example, when the SPI Flash
working voltage is 3.3 V, the M05xx chip supply
voltage must also be 3.3V.
LDO
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8 M05XXDN ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
Max
+7.0
VDD + 0.3
24
Unit
V
DC Power Supply
-0.3
Input Voltage
VSS - 0.3
V
1/tCLCL
TA
Oscillator Frequency
4
MHz
℃
Operating Temperature
-40
+85
℃
TST
Storage Temperature
-55
+150
120
IDD
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the
life and reliability of the device.
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8.2 DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25C)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
Operation voltage
2.5
-
5.5
V
VDD = 2.5 V ~ 5.5 V up to 50 MHz
VSS
AVSS
/
Power Ground
-0.3
-
-
V
VLDO
LDO Output Voltage
1.62
1.16
1.8
1.98
1.24
V
V
VDD ≥ 2.5 V
1.20
VDD = 2.5 V ~ 5.5 V, TA = 25C
VBG
Band-gap Voltage
VDD = 2.5 V ~ 5.5 V,
1.14
-0.3
1.20
0
1.26
0.3
V
V
TA = -40C~85C
Allowed Voltage
Difference for VDD and
AVDD
VDD
AVDD
-
-
All digital
modules
VDD
HXT
HIRC
PLL
IDD1
-
21
-
mA
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
IDD2
IDD3
IDD4
-
-
-
15
20
13
-
-
-
mA
mA
mA
Executed from Flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD5
-
6.6
-
mA
Operating Current
Normal Run Mode
HCLK =22.1184 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
IDD6
IDD7
IDD8
-
-
-
3.7
6.4
3.6
-
-
-
mA
mA
mA
Executed from Flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD9
-
5.4
-
mA
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
5.5V
5.5V
12 MHz
12 MHz
X
X
X
X
V
X
IDD10
IDD11
IDD12
-
-
-
3.6
4.0
2.3
-
-
-
mA
mA
3.3V
12 MHz
X
X
V
X
Executed from Flash
mA
mA
3.3V
VDD
12 MHz
HXT
X
X
All digital
modules
HIRC
PLL
IDD13
-
3.3
-
Operating Current
Normal Run Mode
HCLK =4 MHz
5.5V
5.5V
3.3V
3.3V
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
X
V
X
IDD14
IDD15
IDD16
-
-
-
2.5
2.0
1.3
-
-
-
mA
mA
mA
while(1){}
Executed from Flash
Oct. 05, 2015
Page 56 of 86
Rev 1.03
M051 DN/DE
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
IDD17
-
110
-
μA
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
X
IDD18
IDD19
IDD20
-
-
-
105
92
-
-
-
μA
μA
μA
V[4]
X
Executed from Flash
90
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE1
-
17
-
mA
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
-
-
-
10
15
8
-
-
-
mA
mA
mA
HCLK = 50 MHz
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE5
-
4.5
-
mA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
-
-
-
1.6
4.4
1.6
-
-
-
mA
mA
mA
HCLK =22.1184 MHz
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE9
-
4.1
-
mA
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
-
2.4
2.8
1.2
-
-
-
mA
mA
mA
HCLK =12 MHz
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE13
-
2.9
-
mA
5.5V
5.5V
3.3V
3.3V
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
-
2.1
1.6
0.9
-
-
-
mA
mA
mA
HCLK =4 MHz
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
IIDLE17
-
106
-
μA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
X
Operating Current
Idle Mode
IIDLE18
IIDLE19
IIDLE20
IPWD1
-
-
-
-
104
90
-
-
-
-
μA
μA
μA
A
at 10 kHz
V[4]
X
89
Standby Current
10
VDD = 5.5 V, All oscillators and analog blocks turned off.
Oct. 05, 2015
Page 57 of 86
Rev 1.03
M051 DN/DE
Power-down Mode
(Deep Sleep Mode)
IPWD2
-
-
8
-
VDD = 3.3 V, All oscillators and analog blocks turned off.
A
A
Logic 0 Input Current
P0/1/2/3/4 (Quasi-
bidirectional Mode)
IIL
-65
-75
VDD = 5.5 V, VIN = 0V
VDD = 5.5 V, VIN = 2.0V
Logic 1 to 0 Transition
Current P0/1/2/3/4
(Quasi-bidirectional
Mode) [*3]
ITL
-
-690
-
-750
+1
A
VDD = 5.5 V, 0 < VIN < VDD
Input Leakage Current
P0/1/2/3/4
ILK
-1
A
Open-drain or input only mode
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
Input Low Voltage
P0/1/2/3/4 (TTL Input)
VIL1
V
VDD + 0.3
VDD + 0.3
0.8
Input High Voltage
P0/1/2/3/4 (TTL Input)
VIH1
VIL3
VIH3
V
V
Input Low Voltage
XTAL1[*2]
0
0.4
3.5
2.4
VDD + 0.3
VDD + 0.3
V
V
Input High Voltage
XTAL1[*2]
Negative-going
Threshold
VILS
-0.3
-
-
0.2 VDD
-
(Schmitt Input), nRST
Positive-going
Threshold
VIHS
0.7 VDD
40
VDD + 0.3
150
V
-
-
(Schmitt Input), nRST
Internal nRST Pin
Pull-up Resistor
RRST
kΩ
Negative-going
Threshold
VILS
-0.3
-
-
0.3 VDD
V
V
-
-
(Schmitt input),
P0/1/2/3/4
Positive-going
Threshold
VIHS
0.7 VDD
VDD + 0.3
(Schmitt input),
P0/1/2/3/4
ISR11
ISR12
ISR13
ISR21
ISR22
ISR23
ISK11
ISK12
-300
-50
-40
-20
-3
-420
-75
-67
-26
-5
-
-
-
-
-
-
-
-
VDD = 4.5 V, VS = 2.4 V
VDD = 2.7 V, VS = 2.2 V
VDD = 2.5 V, VS = 2.0 V
A
A
A
Source Current
P0/1/2/3/4 (Quasi-
bidirectional Mode)
mA VDD = 4.5 V, VS = 2.4 V
mA VDD = 2.7 V, VS = 2.2 V
mA VDD = 2.5 V, VS = 2.0 V
mA VDD = 4.5 V, VS = 0.45 V
mA VDD = 2.7 V, VS = 0.45 V
Source Current
P0/1/2/3/4 (Push-pull
Mode)
-2.5
10
-4.2
16
Sink Current
P0/1/2/3/4 (Quasi-
bidirectional, Open-
6
9
Oct. 05, 2015
Page 58 of 86
Rev 1.03
M051 DN/DE
Drain and Push-pull
Mode)
ISK13
5
8
-
mA VDD = 2.5 V, VS = 0.45 V
Notes:
1. nRST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from
1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN
approximates to 2V.
4. Only enable modules which support 10 kHz LIRC clock source.
Oct. 05, 2015
Page 59 of 86
Rev 1.03
M051 DN/DE
8.3 AC Electrical Characteristics
8.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
0.7 VDD
10%
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Min
10
10
2
Typ
Max
-
Unit
ns
Test Condition
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
8.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
85
-
Unit
V
Test Condition
-
-
-
TA
℃
-
12 MHz, VDD = 5.5V
12 MHz, VDD = 3.3V
-
2
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
-
0.8
-
-
fHXT
4
24
Oct. 05, 2015
Page 60 of 86
Rev 1.03
M051 DN/DE
8.3.3 Typical Crystal Application Circuits
Crystal
C1
10~20 pF
C2
4 MHz ~ 24 MHz
10~20 pF
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 8-1 M05xxDN Typical Crystal Application Circuit
8.3.4 22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Supply Voltage
Center Frequency
Min
1.62
-
Typ
1.8
Max
1.98
-
Unit
V
Test Condition
VHRC
-
-
22.1184
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40 ℃ ~ 85 ℃
-3
-
-
+3
-
%
VDD = 2.5 V ~ 5.5 V
TA = 25 ℃,VDD = 5 V
IHRC
Operating Current
800
μA
8.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Supply Voltage
Center Frequency
Min
2.5
-
Typ
-
Max
5.5
-
Unit
V
Test Condition
VLRC
-
-
10
kHz
VDD = 2.5 V ~ 5.5 V
-10
-40
-
-
+10
+40
%
%
TA = 25℃
fLRC
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40℃ ~ +85℃
Oct. 05, 2015
Page 61 of 86
Rev 1.03
M051 DN/DE
8.4 Analog Characteristics
8.4.1 12-bit SAR ADC
Symbol
Parameter
Min
Typ
Max
12
Unit
Bit
Test Condition
-
DNL
INL
EO
EG
EA
Resolution
-
-
-
-
-
-
-
-
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
±1
-1~+4
±4
LSB
LSB
LSB
LSB
LSB
-
-
±2
-
2
4
-
Gain Error (Transfer Gain)
Absolute Error
-2
-4
-
3
4
-
-
Monotonic
Guaranteed
-
-
-
-
-
-
-
16
8
AVDD = 4.5~5.5 V
FADC
ADC Clock Frequency
MHz
AVDD = 2.5~5.5 V
-
800
400
kSPS
kSPS
1/FADC
1/FADC
V
AVDD = 4.5~5.5 V
FS
Sample Rate (FADC/TCONV)
-
AVDD = 2.5~5.5 V
TACQ
TCONV
AVDD
IDDA
Acquisition Time (Sample Stage)
Total Conversion Time
Supply Voltage
7
-
20
-
-
2.5
5.5
-
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
-
0
-
2.9
-
-
mA
AVDD = 5 V
VIN
AVDD
V
-
-
-
CIN
3.2
6
-
-
pF
RIN
Input Load
-
kΩ
Oct. 05, 2015
Page 62 of 86
Rev 1.03
M051 DN/DE
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated
transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the
offset and gain error from the actual transfer curve.
Oct. 05, 2015
Page 63 of 86
Rev 1.03
M051 DN/DE
8.4.2 LDO & Power Management
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Min
2.5
Typ
-
Max
5.5
Unit
V
Test Condition
-
VLDO
TA
1.62
-40
1.8
25
1.98
85
V
-
℃
-
RESR = 1Ω
CLDO
Capacitor
-
1
-
μF
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
2.
For ensuring power stability, a 1μF or higher capacitor must be connected between LDO_CAP pin and
the closest VSS pin of the device.
8.4.3 Low Voltage Reset
Symbol
AVDD
TA
Parameter
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
Supply Voltage
Temperature
℃
μA
V
-40
-
25
85
-
ILVR
Quiescent Current
1
5
AVDD = 5.5 V
TA = 25 ℃
TA = -40 ℃
TA = 85 ℃
1.90
2.00
1.70
2.00
2.10
1.90
2.20
2.40
2.10
VLVR
Threshold Voltage
V
V
8.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-40
-
25
85
-
IBOD
Quiescent Current
-
140
4.55
3.85
2.85
2.35
4.75
4.05
3.05
2.55
AVDD = 5.5 V
4.2
3.5
2.5
2.0
4.3
3.5
2.5
2.0
4.38
3.68
2.68
2.18
4.52
3.8
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
V
Brown-out Voltage
(Falling edge)
VBOD
V
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
2.77
2.25
V
V
Oct. 05, 2015
Page 64 of 86
Rev 1.03
M051 DN/DE
8.4.5 Power-on Reset
Symbol
TA
Parameter
Min
-40
-
Typ
25
2
Max
85
-
Unit
℃
Test Condition
Temperature
-
VPOR
Reset Voltage
V
V+
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
-
-
-
-
100
mV
V/ms
ms
-
-
-
VDD Raising Rate to Ensure
Power-on Reset
0.025
0.5
-
-
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
VDD
tPOR
RRVDD
VPOR
Time
Figure 8-2 Power-up Ramp Condition
Oct. 05, 2015
Page 65 of 86
Rev 1.03
M051 DN/DE
8.4.6 Temperature Sensor
Symbol
VTEMP
TA
Parameter
Supply Voltage
Temperature
Current Consumption
Gain
Min
1.62
-40
Typ
1.8
-
Max
1.98
85
Unit
V
Test Condition
℃
ITEMP
-
16
-
μA
-
mV/℃
-1.65
714
-1.75
724
-1.85
734
-
Offset
mV
TA = 0 ℃
Note:
The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃) x Temperature (℃) + Offset (mV)
8.4.7 Comparator
Symbol
VCMP
TA
Parameter
Supply Voltage
Min
2.5
-40
-
Typ
Max
Unit
V
Test Condition
5.5
℃
Temperature
25
50
10
-
85
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
100
20
μA
mV
V
AVDD = 5 V
-
-
-
-
0.1
0.1
40
AVDD - 0.1
AVDD – 0.1
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
200
-
ns
VHYS
TSTB
Hysteresis
Stable time
-
-
±20
-
±30
1
mV
μs
Oct. 05, 2015
Page 66 of 86
Rev 1.03
M051 DN/DE
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Data Retention
Page Erase Time
Program Time
Read Current
Min
Typ
1.8
-
Max
Unit
V
Test Condition
[1]
VFLA
1.62
1.98
TA = 85℃
TRET
TERASE
TPROG
IDD1
10
-
-
-
-
-
-
-
year
ms
us
3
-
40
0.25
7
-
mA
mA
mA
IDD2
Program Current
Erase Current
-
IDD3
-
20
Notes:
1. VFLA is source from chip LDO output voltage.
2. Guaranteed by design, and not tested in production.
8.6 SPI Dynamic Characteristics
8.6.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V ~ 5.5 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
9
11
SPI MASTER MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
19.5
20.5
SPI SLAVE MODE (VDD = 4.5 V ~ 5.5 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
26
34
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
44
48
Oct. 05, 2015
Page 67 of 86
Rev 1.03
M051 DN/DE
9
M05XXDE ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
Max
+7.0
VDD + 0.3
24
Unit
V
DC Power Supply
-0.3
Input Voltage
VSS - 0.3
V
1/tCLCL
TA
Oscillator Frequency
4
MHz
℃
Operating Temperature
-40
+105
+150
120
℃
TST
Storage Temperature
-55
IDD
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the
life and reliability of the device.
Oct. 05, 2015
Page 68 of 86
Rev 1.03
M051 DN/DE
9.2 DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25C)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
Operation voltage
2.5
-
5.5
V
VDD = 2.5 V ~ 5.5 V up to 50 MHz
VSS
AVSS
/
Power Ground
-0.3
0
0.3
V
VLDO
LDO Output Voltage
1.62
1.22
1.8
1.98
1.28
V
V
VDD ≥ 2.5 V
1.25
VDD = 2.5 V ~ 5.5 V, TA = 25C
VBG
Band-gap Voltage
VDD = 2.5 V ~ 5.5 V,
1.18
-0.3
1.25
0
1.32
0.3
V
V
TA = -40C~105C
Allowed voltage
difference for VDD and
AVDD
VDD
AVDD
-
All digital
modules
VDD
HXT
HIRC
PLL
IDD1
-
21
-
mA
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
IDD2
IDD3
IDD4
-
-
-
15
20
13
-
-
-
mA
mA
mA
executed from flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD5
-
6.6
-
mA
Operating Current
Normal Run Mode
HCLK =22.1184 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
IDD6
IDD7
IDD8
-
-
-
3.7
6.4
3.6
-
-
-
mA
mA
mA
executed from flash
All digital
modules
VDD
HXT
HIRC
PLL
IDD9
-
5.4
-
mA
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
V
X
V
X
IDD10
IDD11
IDD12
-
-
-
3.6
4
-
-
-
mA
mA
mA
executed from flash
2.3
All digital
modules
VDD
HXT
HIRC
PLL
IDD13
-
3.3
-
mA
Operating Current
Normal Run Mode
HCLK =4 MHz
5.5V
5.5V
3.3V
3.3V
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
X
V
X
IDD14
IDD15
IDD16
-
-
-
2.5
2.0
1.3
-
-
-
mA
mA
mA
while(1){}
executed from flash
Oct. 05, 2015
Page 69 of 86
Rev 1.03
M051 DN/DE
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
IDD17
-
110
-
μA
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
X
IDD18
IDD19
IDD20
-
-
-
105
92
-
-
-
μA
μA
μA
V[4]
X
Executed from Flash
90
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE1
-
17
-
mA
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
-
-
-
10
14
6
-
-
-
mA
mA
mA
HCLK = 50 MHz
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE5
-
5.2
-
mA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
-
-
-
2
5
-
-
-
mA
mA
mA
HCLK =22.1184 MHz
1.8
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE9
-
4.3
-
mA
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
2.4
3.2
1.3
mA
mA
mA
HCLK =12 MHz
-
-
-
-
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE13
-
2.9
-
mA
5.5V
5.5V
3.3V
3.3V
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
-
2.1
1.8
1
-
-
-
mA
mA
mA
HCLK =4 MHz
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
IIDLE17
-
106
-
μA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
X
Operating Current
Idle Mode
IIDLE18
IIDLE19
IIDLE20
IPWD1
-
-
-
-
104
90
-
-
-
-
μA
μA
μA
A
at 10 kHz
V[4]
X
89
Standby Current
10
VDD = 5.5 V, All oscillators and analog blocks turned off.
Oct. 05, 2015
Page 70 of 86
Rev 1.03
M051 DN/DE
Power-down Mode
(Deep Sleep Mode)
IPWD2
-
-
8
-
VDD = 3.3 V, All oscillators and analog blocks turned off.
A
A
Logic 0 Input Current
P0/1/2/3/4 (Quasi-
bidirectional mode)
IIL
-65
-75
VDD = 5.5 V, VIN = 0V
VDD = 5.5 V, VIN = 2.0V
Logic 1 to 0 Transition
Current P0/1/2/3/4
(Quasi-bidirectional
mode) [*3]
ITL
-
-510
-
-650
+1
A
VDD = 5.5 V, 0 < VIN < VDD
Input Leakage Current
P0/1/2/3/4
ILK
-1
A
Open-drain or input only mode
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
Input Low Voltage
P0/1/2/3/4 (TTL input)
VIL1
V
VDD + 0.3
VDD + 0.3
0.8
Input High Voltage
P0/1/2/3/4 (TTL input)
VIH1
VIL3
VIH3
V
V
Input Low Voltage
XT1[*2]
0
0.4
3.5
2.4
VDD + 0.3
VDD + 0.3
V
V
Input High Voltage
XT1[*2]
Negative going
threshold
VILS
-0.3
-
-
0.2 VDD
(Schmitt input), nRST
Positive going
threshold
VIHS
0.7 VDD
40
VDD + 0.3
150
V
(Schmitt input), nRST
Internal nRST pin pull
up resistor
RRST
kΩ
Negative going
threshold
VILS
-0.3
-
-
0.3 VDD
V
V
(Schmitt input),
P0/1/2/3/4
Positive going
threshold
VIHS
0.7 VDD
VDD + 0.3
(Schmitt input),
P0/1/2/3/4
ISR11
ISR12
ISR13
ISR21
ISR22
ISR23
ISK11
ISK12
-300
-50
-40
-20
-3
-370
-70
-60
-25
-5
-
-
-
-
-
-
-
-
VDD = 4.5 V, VS = 2.4 V
VDD = 2.7 V, VS = 2.2 V
VDD = 2.5 V, VS = 2.0 V
A
A
A
Source Current
P0/1/2/3/4 (Quasi-
bidirectional Mode)
mA VDD = 4.5 V, VS = 2.4 V
mA VDD = 2.7 V, VS = 2.2 V
mA VDD = 2.5 V, VS = 2.0 V
mA VDD = 4.5 V, VS = 0.45 V
mA VDD = 2.7 V, VS = 0.45 V
Source Current
P0/1/2/3/4 (Push-pull
Mode)
-2.5
10
-4.5
15
Sink Current
P0/1/2/3/4 (Quasi-
bidirectional, Open-
6
9
Oct. 05, 2015
Page 71 of 86
Rev 1.03
M051 DN/DE
Drain and Push-pull
Mode)
ISK13
5
8
-
mA VDD = 2.5 V, VS = 0.45 V
Notes:
1. nRST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1
to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN
approximates to 2V.
4. Only enable modules which support 10 kHz LIRC clock source.
Oct. 05, 2015
Page 72 of 86
Rev 1.03
M051 DN/DE
9.3 AC Electrical Characteristics
9.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
0.7 VDD
10%
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Min
10
10
2
Typ
Max
-
Unit
ns
Test Conditions
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
9.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
-
-
-
TA
℃
-
12 MHz, VDD = 5.5V
12 MHz, VDD = 3.3V
-
2
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
-
0.8
-
-
fHXT
4
24
9.3.3 Typical Crystal Application Circuits
Crystal
C1
10~20 pF
C2
4 MHz ~ 24 MHz
10~20 pF
Oct. 05, 2015
Page 73 of 86
Rev 1.03
M051 DN/DE
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 9-1 M05xDE Typical Crystal Application Circuit
9.3.4 22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Supply Voltage
Center Frequency
Min
1.62
-
Typ
1.8
Max
Unit
V
Test Conditions
VHRC
1.98
-
-
22.1184
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40 ℃ ~ 105 ℃
-2
-
-
+2
-
%
VDD = 2.5 V ~ 5.5 V
TA = 25 ℃,VDD = 5 V
IHRC
Operating Current
800
μA
Oct. 05, 2015
Page 74 of 86
Rev 1.03
M051 DN/DE
HIRC oscillator accuracy vs. temperature
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
Max
Min
-40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100110
TA ℃
Figure 9-2 HIRC Accuracy vs. Temperature
9.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Supply Voltage
Center Frequency
Min
2.5
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
VLRC
-
-
10
kHz
VDD = 2.5 V ~ 5.5 V
-10
-40
-
-
+10
+40
%
%
TA = 25℃
fLRC
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40℃ ~ +105℃
Oct. 05, 2015
Page 75 of 86
Rev 1.03
M051 DN/DE
9.4 Analog Characteristics
9.4.1 12-bit SAR ADC
Symbol
Parameter
Min
Typ
Max
12
Unit
Bit
Test Condition
-
DNL
INL
EO
EG
EA
Resolution
-
-
-
-
-
-
-
-
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
±1
-1~+4
±4
LSB
LSB
LSB
LSB
LSB
-
-
±2
-
2
4
-
Gain Error (Transfer Gain)
Absolute Error
-2
-4
-
3
4
-
-
Monotonic
Guaranteed
-
-
-
-
-
-
-
20
8
AVDD = 4.5~5.5 V
FADC
ADC Clock Frequency
MHz
AVDD = 2.5~5.5 V
-
1000
400
kSPS
kSPS
1/FADC
1/FADC
V
AVDD = 4.5~5.5 V
FS
Sample Rate (FADC/TCONV)
-
AVDD = 2.5~5.5 V
TACQ
TCONV
AVDD
IDDA
Acquisition Time (Sample Stage)
Total Conversion Time
Supply Voltage
7
-
20
-
-
2.5
5.5
-
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
-
0
-
2.5
-
-
mA
AVDD = 5 V
VIN
AVDD
V
-
-
-
CIN
3.2
6
-
-
pF
RIN
Input Load
-
kΩ
Oct. 05, 2015
Page 76 of 86
Rev 1.03
M051 DN/DE
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
9.4.2 LDO & Power Management
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Capacitor
Min
2.5
1.62
-40
-
Typ
-
Max
5.5
1.98
105
-
Unit
Test Condition
V
V
-
-
VLDO
1.8
25
1
℃
TA
RESR = 1Ω
CLDO
μF
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
2.
For ensuring power stability, a 1μF or higher capacitor must be connected between LDO_CAP pin and
the closest VSS pin of the device.
9.4.3 Low Voltage Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
Oct. 05, 2015
Page 77 of 86
Rev 1.03
M051 DN/DE
AVDD
TA
Supply Voltage
Temperature
0
-
5.5
105
5
V
℃
μA
V
-
-
-40
-
25
ILVR
Quiescent Current
1
AVDD = 5.5 V
TA = 25 ℃
1.90
1.70
2.00
2.00
1.90
2.20
2.10
2.05
2.45
VLVR
Threshold Voltage
V
TA = -40 ℃
TA = 105 ℃
V
9.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-40
-
25
105
-
IBOD
Quiescent Current
-
140
AVDD = 5.5 V
4.2
3.5
2.5
2.0
4.3
3.5
2.5
2.0
4.38
3.68
2.68
2.18
4.52
3.8
4.55
3.85
2.85
2.35
4.75
4.05
3.05
2.55
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
V
Brown-out Voltage
(Falling edge)
VBOD
V
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
2.77
2.25
V
V
9.4.5 Power-on Reset
Symbol
TA
Parameter
Min
-40
1.6
Typ
25
2
Max
105
2.4
Unit
℃
Test Condition
Temperature
-
-
VPOR
Reset Voltage
V
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
-
-
-
-
100
mV
V/ms
ms
VDD Raising Rate to Ensure
Power-on Reset
0.025
0.5
-
-
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
Oct. 05, 2015
Page 78 of 86
Rev 1.03
M051 DN/DE
VDD
tPOR
RRVDD
VPOR
Time
Figure 9-3 Power-up Ramp Condition
Oct. 05, 2015
Page 79 of 86
Rev 1.03
M051 DN/DE
9.4.6 Temperature Sensor
Symbol
Parameter
Temperature
Current Consumption
Gain
Min
-40
-
Typ
-
Max
105
-
Unit
℃
Test Condition
TA
ITEMP
16
μA
-
mV/℃
-1.55
735
-1.65
745
-1.75
755
-
Offset
mV
TA = 0 ℃
Note:
The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃) x Temperature (℃) + Offset (mV)
9.4.7 Comparator
Symbol
VCMP
TA
Parameter
Supply Voltage
Min
2.5
-40
-
Typ
-
Max
Unit
V
Test Condition
5.5
℃
Temperature
25
35
10
-
105
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
70
20
μA
mV
V
AVDD = 5 V
-
-
-
-
0.1
0.1
40
AVDD - 0.1
AVDD – 0.1
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
200
-
ns
VHYS
TSTB
Hysteresis
Stable time
-
-
±40
-
±60
1
mV
μs
Oct. 05, 2015
Page 80 of 86
Rev 1.03
M051 DN/DE
9.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
Typ
1.8
-
Max
Unit
V
Test Condition
[2]
VFLA
1.62
1.98
NENDUR
TRET
20,000
-
-
-
-
-
-
-
cycles[1]
year
ms
TA = 85℃
Data Retention
Page Erase Time
Program Time
Read Current
Program Current
Erase Current
10
-
-
TERASE
TPROG
IDD1
20
40
6
-
us
-
mA
IDD2
-
8
mA
IDD3
-
12
mA
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
3. Guaranteed by design, not test in production.
Oct. 05, 2015
Page 81 of 86
Rev 1.03
M051 DN/DE
9.6 SPI Dynamic Characteristics
9.6.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
0
5
-
-
-
-
-
ns
ns
ns
ns
tH(MI)
tV
1
-
2
-
tH(MO)
1
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
0
4
-
-
-
-
ns
ns
ns
ns
tH(MI)
tV
0
-
1
-
tH(MO)
1
Oct. 05, 2015
Page 82 of 86
Rev 1.03
M051 DN/DE
10 PACKAGE DIMENSIONS
10.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
0.024 0.030
0.45
0
L
L
Y
0.039
0.004
7
1
0.10
7
0
0
Oct. 05, 2015
Page 83 of 86
Rev 1.03
M051 DN/DE
10.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm)
Oct. 05, 2015
Page 84 of 86
Rev 1.03
M051 DN/DE
11 REVISION HISTORY
Date
Revision
Description
2013.09.15
1.00
1.01
1.
1.
1.
Initially issued.
Modified M05xDN LVR specification
2014.06.03
Changed the order of Chapter 5 BLOCK DIAGRAM and
Chapter 6 FUNCTIONAL DESCRIPTION.
2.
3.
Fixed typos and obscure description.
Fixed the number of COMP. sets in 4.1 NuMicro® M051
Series M05xxDN Selection Guide and 4.2 NuMicro® M051
Series M05xxDE Selection Guide
2015.05.12
1.02
4.
5.
Added clock switching note in Chapter 6.3 Clock
Controller.
Removed description about ACMP output inverse function
available on M05xxDN.
1.
2.
Changed NuMicro™ to NuMicro® .
Updated Figure 5-1 NuMicro® M051 DN/DE Series Block
Diagram.
2015.10.05
1.03
Oct. 05, 2015
Page 85 of 86
Rev 1.03
M051 DN/DE
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Oct. 05, 2015
Page 86 of 86
Rev 1.03
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