M058SSN [NUVOTON]
ARM Cortex®-M0 32-bit Microcontroller;
| 型号： | M058SSN |
| 厂家： | 
NUVOTON |
| 描述： | ARM Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总72页 (文件大小：2091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NuMicro M058S Series Datasheet
ARM Cortex® -M0
32-bit Microcontroller
NuMicro™ M058S Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Nov. 27, 2014
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TABLE OF CONTENTS
1 GENERAL DESCRIPTION ··················································································································· 7
2 FEATURES ············································································································································ 8
3 ABBREVIATIONS ······························································································································· 11
3.1 List of Abbreviations ·························································································································11
4 PARTS INFORMATION LIST AND PIN CONFIGURATION ··························································· 12
4.1 NuMicro™ M058S Series Selection Guide·····················································································12
4.2 Pin Configuration·······························································································································13
4.2.1 TSSOP20 pin·······························································································································13
4.2.2 QFN 33-pin···································································································································14
4.2.3 LQFP 48-pin·································································································································15
4.2.4 LQFP 64-pin·································································································································16
4.3 Pin Description ··································································································································17
5 BLOCK DIAGRAM ······························································································································ 21
5.1 NuMicro M058S Block Diagram···································································································21
6 FUNCTIONAL DESCRIPTION ··········································································································· 22
6.1 ARM® Cortex® -M0 Core ···················································································································22
6.2 System Manager ·······························································································································24
6.2.1 Overview·······································································································································24
6.2.2 System Reset ······························································································································24
6.2.3 System Power Architecture ·······································································································25
6.2.4 System Memory Map··················································································································26
6.2.5 Whole System Memory Mapping······························································································28
6.2.6 System Timer (SysTick)·············································································································29
6.2.7 Nested Vectored Interrupt Controller (NVIC) ··········································································30
6.3 Clock Controller·································································································································34
6.3.1 Overview·······································································································································34
6.3.2 Clock Generator Block Diagram ·······························································································34
6.3.3 System Clock & SysTick Clock ·································································································37
6.3.4 Power-down Mode Clock···········································································································38
6.3.5 Frequency Divider Output··········································································································38
6.4 Flash Memory Controller (FMC) ·····································································································40
6.4.1 Overview·······································································································································40
6.4.2 Features········································································································································40
6.5 General Purpose I/O (GPIO)···········································································································41
6.5.1 Overview·······································································································································41
6.5.2 Features········································································································································41
6.6 Timer Controller (TMR) ····················································································································42
6.6.1 Overview·······································································································································42
6.6.2 Features: ······································································································································42
6.7 PWM Generator and Capture Timer (PWM)·················································································43
6.7.1 Overview·······································································································································43
6.7.2 Features········································································································································44
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6.8 Watchdog Timer (WDT) ···················································································································45
6.8.1 Overview·······································································································································45
6.8.2 Features········································································································································45
6.9 Window Watchdog Timer (WWDT) ································································································46
6.9.1 Overview·······································································································································46
6.9.2 Features········································································································································46
6.10 UART Interface Controller (UART)·······························································································47
6.10.1
6.10.2
Overview·······························································································································47
Features································································································································47
6.11 I2C Serial Interface Controller (I2C) ······························································································48
6.11.1
6.11.2
Overview·······························································································································48
Features································································································································48
6.12 Serial Peripheral Interface (SPI)···································································································49
6.12.1
Overview·······························································································································49
6.12.2
Features································································································································49
6.13 Analog-to-Digital Converter (ADC)·······························································································50
6.13.1
6.13.2
Overview·······························································································································50
Features································································································································50
7 ELECTRICAL CHARACTERISTICS·································································································· 51
7.1 Absolute Maximum Ratings·············································································································51
7.2 DC Electrical Characteristics···········································································································52
7.3 AC Electrical Characteristics···········································································································56
7.3.1 External Crystal ···························································································································56
7.3.2 External Oscillator·······················································································································56
7.3.3 Typical Crystal Application Circuits ··························································································57
7.3.4 Internal 22.1184 MHz RC Oscillator·························································································58
7.3.5 Internal 10 kHz RC Oscillator····································································································58
7.4 Analog Characteristics ·····················································································································59
7.4.1 12-bit SARADC Specification····································································································59
7.4.2 LDO Specification ·······················································································································61
7.4.3 Low Voltage Reset Specification ······························································································62
7.4.4 Brown-Out Detector Specification·····························································································62
7.4.5 Power-On Reset Specification (5V)··························································································62
7.4.6 Temperature Sensor Specification ···························································································62
7.4.7 Comparator Specification···········································································································63
7.5 Flash DC Electrical Characteristics································································································64
7.6 SPI Dynamic Characteristics···········································································································65
7.6.1 Dynamic Characteristics of Data Input and Output Pin·························································65
8 PACKAGE DIMENSIONS··················································································································· 67
8.1 TSSOP-20 (4.4x6.5 mm) ·················································································································67
8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) ································································68
8.3 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm) ·····················································································69
8.4 LQFP-64 (7x7x1.4mm2 Footprint 2.0mm) ·····················································································70
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9 REVISION HISTORY··························································································································· 71
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LIST OF FIGURES
Figure 4.1-1 NuMicro M058S Series Selection Code ................................................................. 12
Figure 4.2-1 NuMicro M058S TSSOP20 Pin Diagram................................................................ 13
Figure 4.2-2 NuMicro M058S Series QFN-33 Pin Diagram........................................................ 14
Figure 4.2-3 NuMicro M058S Series LQFP-48 Pin Diagram ...................................................... 15
Figure 4.2-4 NuMicro M058S Series LQFP-64 Pin Diagram ...................................................... 16
Figure 5.1-1 NuMicro M058S Block Diagram.............................................................................. 21
Figure 6.1-1 Functional Block Diagram.......................................................................................... 22
Figure 6.2-1 NuMicro™ M058S Power Architecture Diagram ........................................................ 25
Figure 6.3-1 Clock Generator Block Diagram................................................................................ 34
Figure 6.3-2 Clock Source Controller Overview (1/2) .................................................................... 35
Figure 6.3-3 Clock Source Controller Overview (2/2) .................................................................... 36
Figure 6.3-4 System Clock Block Diagram .................................................................................... 37
Figure 6.3-5 SysTick clock Control Block Diagram........................................................................ 37
Figure 6.3-6 Clock Source of Frequency Divider........................................................................... 38
Figure 6.3-7 Block Diagram of Frequency Divider......................................................................... 39
Figure 7.3-1 Typical Crystal Application Circuit ............................................................................. 57
Figure 7.6-1 SPI Master Mode Timing........................................................................................... 65
Figure 7.6-2 SPI Slave Mode Timing............................................................................................. 66
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LIST OF TABLES
Table 3.1-1 List of Abbreviations.................................................................................................... 11
Table 4.1-1 NuMicro M058S Series Selection Guide ................................................................. 12
Table 6.2-1 Address Space Assignments for On-Chip Modules ................................................... 27
Table 6.2-2 Exception Model ......................................................................................................... 31
Table 6.2-3 System Interrupt Map Vector Table............................................................................ 32
Table 6.2-4 Vector Figure Format.................................................................................................. 33
Table 6.4-1 M058S Series Function Difference List (FMC) ........................................................... 40
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1
GENERAL DESCRIPTION
The NuMicro™ M058S is a 32-bit microcontroller with embedded ARM® Cortex® -M0 core for
industrial control and applications which need rich communication interfaces. The Cortex® -M0 is
ARM embedded processor with 32-bit performance and cost-effective microcontroller.
The NuMicro™ M058S can run up to 50 MHz. Thus it can afford to support a variety of industrial
control and applications which need high CPU performance. The NuMicro™ M058S has 32 KB
flash, 4 KB data flash, 4 KB flash for the ISP, and 4 KB SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, and Brown-Out Detector, have been incorporated into the NuMicro™ M058S in
order to reduce component count, board space and system cost. These useful functions make the
NuMicro™ M058S powerful for a wide range of applications.
Additionally, the NuMicro™ M058S is equipped with IAP (In-Application Programming), ISP (In-
System Programming) and ICP (In-Circuit Programming) functions, which allow the user to
update the program memory without removing the chip from the actual end product.
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2
FEATURES
Core
ARM® Cortex® -M0 core runs up to 50 MHz.
One 24-bit system timer.
Supports low power sleep-mode.
A single-cycle 32-bit hardware multiplier.
NVIC for the 32 interrupt inputs, each with 4-levels of priority.
Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints.
Wide Operating Voltage Range: 2.5V to 5.5V
Memory
32 KB Flash for program memory (APROM)
4 KB Flash for data memory (DataFlash)
4 KB Flash for loader (LDROM)
4 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
22.1184 MHz internal oscillator
4~24 MHz external crystal input
10 kHz low-power oscillator for Watchdog Timer and wake-up in Sleep mode
PLL allows CPU operation up to the maximum 50 MHz
I/O Port
Up to 55 general-purpose I/O (GPIO) pins for LQFP-64 package
Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Configurable I/O mode after POR
Timer
Provides four channel 32-bit timers, one 8-bit pre-scale counter with 24-bit up-timer for
each timer.
Independent clock source for each timer.
24-bit timer value is readable through TDR (Timer Data Register)
Provides one-shot, periodic and toggle operation modes.
Provide event counter function.
Provide external capture/reset counter function.
Additional functions:
Two more timer clock sources from external trigger and internal 10 kHz
TIMER wake-up function
External capture input source selected from TxEX
Toggle mode output pins selected from TxEX or TMx
Inter-Timer trigger mode
WDT (Watchdog Timer)
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Multiple clock sources
Supports wake-up from Power-down or Sleep mode
Interrupt or reset selectable on watchdog time-out
Time-out reset delay period time can be selected
WWDT (Window Watchdog Timer)
6-bit down counter with 11-bit prescale for wide range window selected
PWM
Up to two built-in 16-bit PWM generators, providing four PWM outputs or two
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for
each PWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs
Supports capture interrupt
Additional functions
Internal 10 kHz to PWM clock source
Polar inverse function
Center-aligned type function
Timer duty interrupt enable function
Two kinds of PWM interrupt period/duty type selection
Period/duty trigger ADC function
UART
Programmable baud-rate generator
Buffered receiver and transmitter, each with 16 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
Supports LIN function
SPI
Supports Master/Slave mode
Full-duplex synchronous serial data transfer
Provides 3 wire function
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Supports Byte Suspend mode in 32-bit transmission
Additional functions
PLL clock source
4-level depth FIFO buffer for better performance and flexibility in SPI Burst
Transfer mode
I2C
Up to two sets of I2C device
Supports master/slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
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one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
Programmable clocks allow versatile rate control.
Supports multiple address recognition (four slave address with mask option)
ADC
12-bit SAR ADC
Up to 8-ch single-ended input or 4-ch differential input
Supports Single mode/Burst mode/Single-cycle Scan mode/Continuous Scan mode
Supports 2’ complement/un-signed format in differential mode conversion results
Each channel with an individual result register
Supports conversion value monitoring (or comparison) for threshold voltage detection
Conversion started either by software trigger or external pin trigger
Additional functions
A/D conversion started by PWM center-aligned trigger or edge-aligned trigger
PWM trigger delay function
ISP (In-System Programming) and ICP (In-Circuit Programming)
IAP (In-Application Programming)
One built-in temperature sensor with 1℃ resolution
BOD (Brown-out Detector)
With 4 levels: 4.4V/3.7V/2.7V/2.2V
Supports Brown-Out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Threshold voltage levels: 2.0V
Operating Temperature: -40℃~85℃
Packages:
Green package (RoHS)
64-pin LQFP, 48-pin LQFP, 33-pin QFN, 20-pin TSSOP
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3
ABBREVIATIONS
3.1 List of Abbreviations
Acronym
ADC
APB
Description
Analog-to-Digital Converter
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
FIFO
FMC
GPIO
HCLK
HIRC
HXT
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIRC
NVIC
PCLK
PLL
10 kHz internal low speed RC oscillator (LIRC)
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Phase-Locked Loop
PWM
SPI
Pulse Width Modulation
Serial Peripheral Interface
SPS
Samples per Second
TMR
UART
UCID
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
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NuMicro M058S Series Datasheet
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro™ M058S Series Selection Guide
Connectivity
M058SFAN
M058SZAN
M058SLAN
M058SSAN
32
32
32
32
4
4
4
4
4
4
4
4
4
4
4
4
14
26
42
55
4
4
4
4
1
1
1
1
1
1
1
1
1
1
2
2
1
2
4
4
2
5
8
8
√
√
√
√
√
√
√
√
√
√
√
√
TSSOP20
QFN33
-40 to +85
-40 to +85
-40 to +85
-40 to +85
LQFP48
LQFP64
Table 4.1-1 NuMicro M058S Series Selection Guide
M0
58S - X X X
CPU core
ARM Cortex M0
Temperature
Part Number
58S: 32 KB Flash ROM
℃
℃
N: - 40 ~ +85
Reserved
Package
Ｓ: LQFP64
Ｌ: LQFP48
Ｚ: QFN33
Ｆ: TSSOP20
Figure 4.1-1 NuMicro M058S Series Selection Code
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NuMicro M058S Series Datasheet
4.2 Pin Configuration
4.2.1 TSSOP20 pin
1
2
3
20
T2, AIN0,P1.0
AVDD
VDD
19
SPISS, AIN4, P1.4
/RST
18
P0.5, MOSI
17
RXD, P3.0
4
5
P0.6, MISO
M058S
TSSOP
20-pin
16
AVSS
P0.7, SPICLK
6
15
TXD, P3.1
P4.7, ICE_DAT
7
14
SDA0, T0, P3.4
CKO, SCL0, T1, P3.5
P4.6, ICE_CLK
8
13
P2.3, PWM3
9
12
LDO_CAP
XTAL2, P7.0
XTAL1, P7.1
10
11
VSS
Figure 4.2-1 NuMicro M058S TSSOP20 Pin Diagram
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4.2.2 QFN 33-pin
32 31 30 29 28 27 26 25
AIN5, P1.5
/RST
P0.4, SPISS
P0.5, MOSI
P0.6, MISO
P0.7, SPICLK
P4.7, ICE_DAT
P4.6, ICE_CLK
P2.6
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RXD, P3.0
AVSS
QFN 33-Pin
TXD, P3.1
T0EX, STADC, INT0, P3.2
SDA0, T0, P3.4
33 VSS
10 11 12 13 14 15 16
CKO, SCL0, T1, P3.5
P2.5
9
Figure 4.2-2 NuMicro M058S Series QFN-33 Pin Diagram
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4.2.3 LQFP 48-pin
P4.1, PWM1, T3EX
36
MOSI, AIN5, P1.5
MISO, AIN6, P1.6
SPICLK, AIN7, P1.7
/RST
1
P0.4, SPISS
35
2
P0.5, MOSI
P0.6, MISO
P0.7, SPICLK
P4.7, ICE_DAT
P4.6, ICE_CLK
P4.5, SDA1
P4.4, SCL1
P2.7
3
34
33
32
31
30
29
28
27
26
25
4
5
RXD, P3.0
6
AVSS
48-pin LQFP
TXD, P3.1
7
T0EX, STADC, INT0, P3.2
T1EX, INT1, P3.3
SDA0, T0, P3.4
CKO, SCL0, T1, P3.5
PWM3, P4.3
8
9
10
11
12
P2.6
P2.5
Figure 4.2-3 NuMicro M058S Series LQFP-48 Pin Diagram
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4.2.4 LQFP 64-pin
MOSI, AIN5, P1.5
MISO, AIN6, P1.6
SPICLK, AIN7, P1.7
/RST
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P4.1, PWM1, T3EX
P0.4, SPISS
P0.5, MOSI
P0.6, MISO
P0.7, SPICLK
P6.3
2
3
4
RXD, P3.0
5
AVSS
6
T1EX,P5.1
7
P6.2
SDA0,P5.2
8
P6.1
LQFP 64-Pin
SCL0,P5.3
9
P6.0
TXD, P3.1
10
11
12
13
14
15
16
P4.7, ICE_DAT
P4.6, ICE_CLK
P4.5, SDA1
P4.4, SCL1
P2.7
T0EX, STADC, INT0, P3.2
T1EX, INT1, P3.3
SDA0, T0, P3.4
CKO, SCL0, T1, P3.5
PWM3, P4.3
P2.6
CKO, P3.6
P2.5
Figure 4.2-4 NuMicro M058S Series LQFP-64 Pin Diagram
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4.3 Pin Description
Pin Number
Alternate Function
Symbol
Type[1]
Description
TSSOP
20
QFN
33
LQFP
48
LQFP
64
1
2
3
21
54
20
53
Power supply to I/O ports and
LDO source for internal PLL and
digital circuit.
19
11
27
41
17
VDD
P
P
12
33
Ground pin for digital circuit.
VSS
Power supply to internal analog
circuit.
20
5
28
4
42
6
55
6
AVDD
AVSS
Vref
P
P
P
Analog Ground pin for analog
circuit.
Voltage reference input for
ADC
NC
NC
56
LDO output pin
LDO
Note: This pin needs to be
12
13
18
22
P
_CAP
connected
capacitor.
with
a
1uF
/RST pin is a Schmitt trigger
input pin for hardware device
reset. A “Low” on this pin for
768 clock counter of Internal
RC 22M while the system
clock is running will reset the
device. /RST pin has an
I
3
2
4
4
/RST
(ST)
internal pull-up resistor
allowing power-on reset by
simply connecting an external
capacitor to GND.
26
25
40
39
38
37
35
34
52
51
50
49
47
46
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
I/O
I/O
I/O
I/O
I/O
I/O
PORT0: General purpose I/O
port, which can be configured
by software in four modes. Its
multifunction pins are for
CTS1, RTS1, CTS0, RTS0,
SPISS, MOSI, MISO, and
SPICLK.
NC
NC
24
CTS
RTS
TXD[2]
RXD[2]
The pins SPISS, MOSI,
MISO, and SPICLK are for
the SPI function use.
SPISS[2]
MOSI[2]
CTS: Clear to Send input pin
18
23
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NuMicro M058S Series Datasheet
Pin Number
Alternate Function
Symbol
Type[1]
Description
TSSOP
20
QFN
33
LQFP
LQFP
64
1
2
3
48
for UART
I/O
I/O
17
16
1
22
21
33
45
44
P0.6
P0.7
MISO[2]
RTS: Request to Send output
pin for UART
32
SPICLK[2]
The RXD/TXD pins are for
UART function use.
29
NC
30
31
32
1
43
44
45
46
47
1
59
60
61
62
63
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
T2
T3
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT1: General purpose I/O
port, which can be configured
by software in four modes. Its
multifunction pins are for T2,
T3, SPISS0, MOSI, MISO,
and SPICLK.
The pins SPISS0, MOSI,
MISO, and SCLK are for the
SPI function use.
2
SPISS[2]
MOSI[2]
The pins AIN0~AIN7 are for
the 12 bits ADC function use.
The T2/T3 pins are for
Timer2/3 external event
counter input.
NC
NC
NC
NC
14
15
16
17
18
NC
3
2
2
MISO[2]
3
3
SPICLK[2]
PWM0[2]
PWM1[2]
PWM2[2]
PWM3[2]
19
20
21
22
23
25
26
27
5
27
28
29
30
31
33
34
35
5
PORT2: General purpose I/O
port, which can be configured
by software in four modes. It
has an alternative function.
The pins PWM0~PWM3 are
for the PWM function use.
13
4
6
RXD[2]
TXD[2]
/INT0
/INT1
PORT3: General purpose I/O
port, which can be configured
by software in four modes. Its
multifunction pins are for
RXD, TXD, /INT0, /INT1, T0
and T1.
5
7
10
11
12
6
8
STADC T0EX
T1EX
The RXD/TXD pins are for
NC
9
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NuMicro M058S Series Datasheet
Pin Number
Alternate Function
Symbol
Type[1]
Description
TSSOP
20
QFN
33
LQFP
LQFP
64
1
2
3
48
10
11
13
UART function use.
7
8
7
8
9
13
14
16
P3.4
P3.5
P3.6
T0
T1
SDA0
I/O
I/O
I/O
The SDA0/SCL0 pins are for
I2C0 function use.
SCL0 CKO[2]
CKO
CKO: HCLK clock output
The STADC pin is for ADC
external trigger input.
The T0/T1 pins are for
Timer0/1 external event
counter input.
NC
14
17
P3.7
I/O
The T0EX/T1EX pins are for
external capture/reset trigger
input of Timer0/1.
NC
NC
NC
NC
NC
NC
19
24
36
32
48
64
15
36
37
38
39
7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
PWM0[2]
PWM1[2]
PWM2[2]
PWM3[2]
T2EX
T3EX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT4: General purpose I/O
port, which can be configured
by software in four modes. Its
multifunction pins are for
PWM0-3, SCL1, SDA1,
48
ICE_CLK and ICE_DAT.
The ICE_CLK/ICE_DAT pins
are for JTAG-ICE function
use.
12
28
SCL1
SDA1
PWM0-3 can be used from
P2.0-P2.3 or P4.0-P4.3.
29
The T2EX/T3EX pins are for
external capture/reset trigger
input of Timer2/3.
14
15
30
ICE_CLK
ICE_DAT
T1EX
20
31
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PORT5: General purpose I/O
port, which can be configured
by software in four modes. Its
multifunction pins are for
T0EX, T1EX, SDA0 and
SCL0.
8
SDA0
9
SCL0
The T0EX/T1EX pins are for
external capture/reset trigger
input of Timer0/1.
23
24
25
26
40
The SDA0/SCL0 pins are for
I2C0 function use.
PORT6: General purpose I/O
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NuMicro M058S Series Datasheet
Pin Number
Alternate Function
Symbol
Type[1]
Description
TSSOP
20
QFN
33
LQFP
LQFP
64
1
2
3
48
port, which can be configured
by software in four modes.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
41
42
43
57
58
P6.1
P6.2
P6.3
P6.6
P6.7
I/O
I/O
I/O
I/O
I/O
I/O,
O
PORT7: General purpose I/O port,
which can be configured by
software in four modes. Its
9
10
11
15
16
18
19
P7.0
P7.1
XTAL2
XTAL1
multifunction pins are for XTAL
I/O,
XTAL: External 4~24 MHz (high
speed) crystal pin.
10
I(ST)
Note 1: I/O type description. I: Input, O: Output, I/O: Quasi-bidirectional, D: Open-drain, P: Power pins, ST: Schmitt trigger.
Note 2: The PWM0 ~ PWM3, RXD, TXD, RXD1, TXD1, SCL1, SDA1 and CKO can be assigned to different pins. However, a
pin function can only be assigned to a pin at the same time, i.e. software cannot assign RXD to P0.3 and P3.0 at the same time.
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NuMicro M058S Series Datasheet
5
BLOCK DIAGRAM
5.1 NuMicro M058S Block Diagram
Memory
PWM / Timer
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
Watchdog Timer
LDROM
4 KB
APROM
32 KB
ARM
Cortex-M0
50 MHz
Window Watchdog
Timer
SRAM
4 KB
DataFlash
4 KB
PWM/Capture
Timer x 4
Bridge
AHB Bus
APB Bus
Power Control
LDO
Clock Control
PLL
Connectivity
UART x 1
I/O Ports
General Purpose
I/O
Power On Reset
LVR
SPI x 1
I2C x 2
External Interrupt
Reset Pin
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
22.1184 MHz
Low Speed
Oscillator
10 kHz
Brown-out
Detection
Figure 5.1-1 NuMicro M058S Block Diagram
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NuMicro M058S Series Datasheet
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-
Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The
processor can execute Thumb code and is compatible with other Cortex-M profile processor. The
profile supports two modes -Thread and Handler modes. Handler mode is entered as a result of an
exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset,
and can be entered as a result of an exception return. Figure 6.1-1 shows the functional controller of
processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor the features:
The ARMv6-M Thumb® instruction set.
Thumb-2 technology.
ARMv6-M compliant 24-bit SysTick timer.
A 32-bit hardware multiplier.
The system interface supports little-endian data accesses.
The ability to have deterministic, fixed-latency, interrupt handling.
Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling.
C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface(C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers.
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Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event(WFE)
instructions, or the return from interrupt sleep-on-exit feature.
NVIC features:
32 external interrupt inputs, each with four levels of priority.
Dedicated non-Maskable Interrupt (NMI) input.
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and provides Ultra-low Power Sleep mode
Debug support:
Four hardware breakpoints.
Two watchpoints.
Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
Single step and vector catch capabilities.
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory.
Single 32-bit slave port that supports the DAP (Debug Access Port).
Nov. 27, 2014
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NuMicro M058S Series Datasheet
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Hardware Reset
Power-on Reset (POR)
Low level on the Reset Pin (nRST)
Watchdog Timer Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
MCU Reset - SYSRESETREQ(AIRCR[2])
Cortex-M0 Core One-shot Reset - CPU_RST(IPRSTC1[1])
Chip One-shot Reset - CHIP_RST(IPRSTC1[0])
Note: ISPCON.BS keeps the original value after MCU Reset and CPU Reset.
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NuMicro M058S Series Datasheet
6.2.3 System Power Architecture
In this device, the power architecture is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies the power to the I/O pins and internal
regulator which provides a fixed 1.8 V power for digital operation.
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
as the digital power (VDD). The following figure shows the power distribution of the M058S series.
Analog Comparator
AVDD
12-bit
SAR-ADC
Low
Voltage
Reset
Brown
Out
Detector
AVSS
Internal
22.1184 MHz and
10 kHz Oscillator
Temperature
Sensor
Flash
Digital Logic
LDO_CAP
1uF
1.8V
POR18
POR50
5V to 1.8V
LDO
PLL
I/O cell
GPIO Pins
PVSS
VDD VSS
M058 Series Power Distribution
Figure 6.2-1 NuMicro™ M058S Power Architecture Diagram
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NuMicro M058S Series Datasheet
6.2.4 System Memory Map
The NuMicro M058S series provides 4 GB addressing space. The addressing space assigned
to each on-chip controllers are shown in the following table. The detailed register definition,
addressing space, and programming details will be described in the following sections for each
on-chip peripheral. The NuMicro M058S series only supports little-endian data format.
Addressing Space
Token
Modules
Flash & SRAM Memory Space
0x0000_0000 – 0x0000_7FFF
0x2000_0000 – 0x2000_0FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (32 KB)
SRAM Memory Space (4 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO (P0~P7) Control Registers
Flash Memory Control Registers
GPIO_BA
FMC_BA
APB Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_00FF
0x4000_4100 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
WDT_BA
Watchdog Timer Control Registers
WWDT_BA
TMR01_BA
I2C0_BA
Window Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400E_0000 – 0x400E_FFFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
SPI0_BA
SPI0 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
PWMA_BA
UART0_BA
ADC_BA
UART0 Control Registers
Analog-Digital-Converter (ADC) Control Registers
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
TMR23_BA
I2C1_BA
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
SYST_BA
NVIC_BA
System Timer Control Registers
External Interrupt Controller Control Registers
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0xE000_ED00 – 0xE000_ED8F
SCB_BA
System Control Block Registers
Table 6.2-1 Address Space Assignments for On-Chip Modules
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6.2.5 Whole System Memory Mapping
M058S
4 GB
0xFFFF_FFFF
|
Reserved
System Control
Reserved
EBI
System Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_DFFF
|
System Control Block
External Interrupt Controller
System Timer Control
System Control Space
0xE000_ED00
0xE000_E100
0xE000_E010
0xE000_E000
SCB_BA
NVIC_BA
SYST_BA
SCS_BA
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
Reserved
AHB peripherals
FMC
0x5020_0000
0x5000_C000
0x5000_4000
0x5000_0300
0x5000_0200
0x5000_0000
FLASH_BA
GPIO_BA
INT_BA
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
GPIO Control
AHB
Interrupt Multiplexer Control
Clock Control
CLK_BA
GCR_BA
System Global Control
Reserved
|
0x4020_0000
0x401F_FFFF
APB peripherals
I2C1 Control
0x4012_0000
0x4011_0000
0x400E_0000
I2C1_BA*
TMR23_BA
ADC_BA
Timer2/Timer3 Control
ADC Control
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
UART0 Control
PWM0/1/2/3 Control
SPI0 Control
0x4005_0000
0x4004_0000
0x4003_0000
0x4002_0000
0x4001_0000
0x4000_4000
0x4000_4100
UART0_BA
PWMA_BA
SPI0_BA
Reserved
|
I2C Control
I2C0_BA
0x2000_1000
0x2000_0FFF
Timer0/Timer1 Control
WDT Control
TMR01_BA
WDT_BA
WWDT Control
WWDT_BA*
4 KB SRAM
(M052/M054/M058/M0516)
|
0.5 GB
0x2000_0000
0x1FFF_FFFF
Reserved
|
0x0001_0000
0x0000_7FFF
32 KB on-chip Flash
|
0 GB
0x0000_0000
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6.2.6 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock edge, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_RVR value
rather than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the documents “ARM® Cortex® -M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.7 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.7.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro™ M058S series. Software can
set four levels of priority on some of these exceptions as well as on all interrupts. The highest
user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default
priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
1
-3
-2
NMI
2
Hard Fault
Reserved
3
-1
Reserved
4 ~ 10
SVCall
11
Configurable
Reserved
Reserved
12 ~ 13
PendSV
SysTick
14
Configurable
Configurable
Configurable
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 6.2-2 Exception Model
Interrupt
Number
(Bit
Power-
down
Wakeup
Exception
Number
Vector
Address
Interrupt
Name
Source
Module
in
Interrupt description
Interrupt
Registers)
1-15
System exceptions
Brown-out low voltage detected
interrupt
16
17
18
0x40
0x44
0x48
0
1
2
BOD_INT
WDT_INT
EINT0
Brown-out
WDT
Yes
Yes
Yes
Watchdog Timer interrupt
External signal interrupt from P3.2
pin
GPIO
External signal interrupt from P3.3
pin
19
20
0x4C
0x50
3
4
EINT1
GPIO
GPIO
Yes
Yes
External signal interrupt from
P0[7:0] / P1[7:0]
GP01_INT
External
P2[7:0]/P3[7:0]/P4[7:0],
P32 and P33
interrupt
from
except Yes
21
0x54
5
GP234_INT
GPIO
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PWM0, PWM1, PWM2 and PWM3
interrupt
22
0x58
6
PWMA_INT
PWM0~3
No
23
24
25
26
27
28
29
30
31
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
7
Reserved
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
Reserved
SPI0_INT
Reserved
-
-
-
8
TMR0
TMR1
TMR2
TMR3
UART0
-
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
-
No
No
No
No
Yes
-
9
10
11
12
13
14
15
SPI0
-
SPI0 interrupt
-
No
-
External signal interrupt from
P5[7:0]
32
0x80
16
GP5_INT
GPIO
Yes
External signal interrupt from
P6[7:0] / P7[1:0]
33
34
0x84
0x88
17
18
GP67_INT
I2C0_INT
GPIO
I2C0
Yes
Yes
I2C0 interrupt
35
36
0x8C
0x90
19
20
I2C1_INT
I2C1
Yes
No
I2C1 interrupt
CAP0_INT
PWM
PWM0 capture in interrupt
37
38
0x94
0x98
21
22
CAP1_INT
CAP2_INT
CAP3_INT
Reserved
PWM
PWM
PWM
-
PWM1 capture in interrupt
PWM2 capture in interrupt
PWM3 capture in interrupt
-
No
No
No
-
39
0x9C
23
40-43
0x90-0xAC
20-27
Clock controller interrupt for chip
wake-up from Power-down state
44
0xB0
28
PWRWU_INT CLKC
Yes
No
45
0xB4
29
ADC_INT
Reserved
ADC
-
ADC interrupt
-
46-47
0xB8-0xBC
30-31
Table 6.2-3 System Interrupt Map Vector Table
6.2.7.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
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entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Vector Number
Exception Entry Pointer using that Vector Number
Table 6.2-4 Vector Figure Format
6.2.7.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit
Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC) to reduce
the overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
6.3.2 Clock Generator Block Diagram
The clock generator consists of 4 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from external
4~24 MHz external high speed crystal (HXT) or 22.1184 MHz internal high speed
oscillator (HIRC)) (PLL FOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTL12M_EN (PWRCON[0])
HXT
XTAL1
XTAL2
PLL_SRC (PLLCON[19])
4~24 MHz HXT
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-1 Clock Generator Block Diagram
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HIRC
111
011
010
001
000
CPUCLK
HCLK
CPU
LIRC
PLL FOUT
Reserved
HXT
1/(HCLK_N+1)
I2C0
I2C1
PCLK
CLKSEL0[2:0]
HIRC
FMC
HCLK
1
0
SPI0
SPI1
PLL FOUT
CLKSEL1[4:5]*
HIRC
11
10
01
00
HCLK
1/(ADC_N+1)
ADC
PLL FOUT
HXT
CLKSEL1[3:2]
HIRC
11
01
00
PLL FOUT
HXT
1/(UART_N+1)
UART 0
BOD
CLKSEL1[25:24]
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-2 Clock Source Controller Overview (1/2)
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HIRC
111
101
011
Reserved
T0~T3**
TMR 0
TMR 1
TMR 2
TMR 3
HCLK
HXT
010
000
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
HIRC
HCLK
HXT
1/2
1/2
1/2
111
011
010
001
000
CPUCLK
1
SysTick
0
Reserved
HXT
SYST_CSR[2]
CLKSEL0[5:3]
HIRC
11
10
01
00
FDIV
HCLK
Reserved
HXT
PWM 2-3
PWM 0-1
CLKSEL2[7:2]
CLKSEL1[31:28]
LIRC
11
10
WWDT
HCLK/2048
CLKSEL2[17:16]*
LIRC
11
10
01
HCLK
1/2048
WDT
Reserved
CLKSEL1[1:0]
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note1: T0 is for TMR0, T1 is for TMR1, T2 is for TMR2 and T3 is for TMR3.
Figure 6.3-3 Clock Source Controller Overview (2/2)
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6.3.3 System Clock & SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown below.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
PLL FOUT
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLK_N (CLKDIV[3:0])
PCLK
4~24 MHz HXT
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-4 System Clock Block Diagram
The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]. The block
diagram is shown below.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
HIRC
1/2
1/2
1/2
111
011
HCLK
STCLK
4~24 MHz HXT
Reserved
010
001
4~24 MHz HXT
000
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-5 SysTick clock Control Block Diagram
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6.3.4 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
10 kHz internal low speed oscillator clock
Peripherals Clock (when 10 kHz low speed oscillator is adopted as clock source)
6.3.5 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to
DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) set to 1, the frequency divider clock (FRQDIV_CLK) will bypass power-
of-2 frequency divider. The frequency divider clock will be output to CKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
22.1184 MHz
HIRC
11
HCLK
FRQDIV_CLK
10
01
00
10 kHz LIRC
4~24 MHz HXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-6 Clock Source of Frequency Divider
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DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FSEL
16 chained
divide-by-2 counter
(FRQDIV[3:0])
FRQDIV_CLK
1/22
1/23
…...
1/215 1/216
DIVIDER1
(FRQDIV[5])
1/2
000
000
0
1
:
16 to 1
MUX
0
1
:
CKO
111
111
0
1
Figure 6.3-7 Block Diagram of Frequency Divider
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The M058S Series are equipped with 64/32/16/8 KB on chip embedded Flash memory for
application program (APROM) that can be updated through ISP registers. In-System-
Programming (ISP) and In-Application-Programming (IAP) enable user to update program
memory when chip is soldered on PCB. After chip power on Cortex-M0 CPU fetches code from
APROM or LDROM decided by boot select (CBS) in CONFIG0. By the way, it also provides
additional 4 KB DATA Flash for user to store some application depended data before chip power
off in 64/32/16/8 KB APROM model.
It provides more settings in CONFIG0 to support more advanced functions, including power-on
with tri-state I/O, default to enable WDT after booting, enable WDT in Power-down mode, and IAP
functions. The following table shows the added functions of M058S Series.
M058S Series
CONFIG[6]
CONFIG[10]
CONFIG[30]
CONFIG[31]
To support IAP function and Multi-Boot function
Select I/O state after booting
To support WDT in Power-Down mode when WDT is default on after booting
To support WDT default on after booting
Table 6.4-1 M058S Series Function Difference List (FMC)
6.4.2 Features
Runs up to 50 MHz with zero wait state for continuous address read access
32 KB application program memory (APROM)
4 KB in system programming (ISP) loader program memory (LDROM)
Fixed 4 KB Data Flash
All embedded flash memory supports 512 bytes page erase
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
There are 58 General Purpose I/O pins shared with special feature functions in this MCU. The 58
pins are arranged in 9 ports named with P0, P1… to P7. Each port equips maximum 8 pins
except P7[1:0]. Each one of the 58 pins is independent and has the corresponding register bits to
control the pin mode function and data
The I/O type of each of I/O pins can be software configured individually as input, output, open-
drain or quasi-bidirectional mode. The all pins of I/O type stay in quasi-bidirectional mode and port
data register Px_DOUT[7:0] resets to 0x000_00FF. Each I/O pin equips a very weakly individual
pull-up resistor which is about 110K~300K for VDD which is from 5.0V to 2.5V.
6.5.2 Features
Four I/O modes:
Input only with high impedance
Push-pull output
Open-drain output
Quasi-bidirectional TTL/Schmitt trigger input mode selected by Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function
Configurable default I/O mode of all pins after reset by CIOINI(CONFIG[10]) setting
CIOINI = 0, all GPIO pins in Input tri-state mode after chip reset
CIOINI = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
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6.6 Timer Controller (TMR)
6.6.1 Overview
The Timer Controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.6.2 Features:
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous counting
Time-out period = (Period time of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period time of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the input event from external counter pin (T0~T3)
24-bit capture value is readable through TCAP (Timer Capture Data Register)
Supports external capture pin (T0EX~T3EX) for interval measurement
Supports external capture pin (T0EX~T3EX) to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Supports Inter-Timer trigger mode
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6.7 PWM Generator and Capture Timer (PWM)
6.7.1 Overview
The NuMicroTM M058S has one sets of PWM groups supporting a total of two sets of PWM
generators, which can be configured as four independent PWM outputs, PWM0~PWM3, or as two
complementary PWM pairs, (PWM0, PWM1) and (PWM2, PWM3) with 2 programmable Dead-
zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 2
sets of PWM generators provide four independent PWM period interrupt flags set by hardware
when the corresponding PWM period down counter reaches 0. Each PWM period interrupt source
with its corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators
can be configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode
to output PWM waveform continuously.
When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;
the paired PWM period, duty and Dead-zone are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3) are controlled by PWM2
timers and Dead-zone generator 2. Refer to figures below for the architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be loaded into the 16-bit down
counter/ comparator at the time down counter reaching 0. The double buffering feature avoids
glitch at PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-Timer
is set as Auto-reload mode when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically and then starts decreasing repeatedly. If the PWM-Timer is set as
one-shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-Timer is digital input Capture function. If Capture function is
enabled, the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must set the PWM-Timer before enabling the Capture feature. After capture
feature is enabled, the capture always latched PWM-counter to Capture Rising Latch Register
(CRLR) when input channel has a rising transition and latched PWM-counter to Capture Falling
Latch Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0
(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture
channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). The
capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
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PIIR to get interrupt source, read CRLRx/CFLRx (x = 0~3) to get capture value and finally write 1
to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0.
6.7.2 Features
PWM function:
PWM group has two PWM generators. Each PWM generator supports one 8-bit prescaler, one
clock divider, two PWM-Timers (down counter), one dead-zone generator and two PWM outputs.
PWMA (PWM group A) is a group of PWM which support 4 PWM channels or 2
complementary PWM paired channels
PWM group has two PWM generators with each PWM generator supporting one 8-bit
prescaler, two clock dividers, two PWM-Timers, one Dead-zone generator and two PWM
outputs.
Up to 16-bit resolution
One-shot or Auto-reload mode
Edge-aligned type or Center-aligned type option
PWM trigger ADC start-to-conversion
Capture function:
Timing control logic shared with PWM generators
Supports 4 Capture input channels shared with 4 PWM output channels
Each channel supports one rising latch register (CRLRx), one falling latch register (CFLRx)
and Capture interrupt flag (CAPIFx)
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake-up system from Idle/Power-down mode.
6.8.2 Features
18-bit free running up counter for Watchdog Timer time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period is
104 ms ~ 26.3168 s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer reset delay period
Selectable reset delay period 3/18/130/1026 * WDT_CLK
Supports to force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(CONFIG[31] Watchdog Enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function only if WDT clock source is selected
as 10 kHz
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.9.2 Features
6-bit down counter value (WWDTCVAL) and 6-bit compare window value (WINCMP) to
make the WWDT time-out window period flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of WWDT
counter
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6.10 UART Interface Controller (UART)
6.10.1 Overview
The NuMicroTM M058S provides two channels of Universal Asynchronous Receiver/Transmitters
(UART). UART Controller performs Normal Speed UART, and support flow control function. The
UART Controller performs a serial-to-parallel conversion on data received from the peripheral,
and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also
supports IrDA SIR Function, LIN master/slave function and RS-485 function mode. Each UART
Controller channel supports seven types of interrupts.
6.10.2 Features
Full duplex, asynchronous communications
Separate receive / transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake up function
Supports 8 bit receiver buffer time out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5, 6, 7, 8 bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
Supports RS-485 function mode.
Supports RS-485 9bit mode
Supports hardware or software enable to program RTS pin to control RS-485
transmission direction directly
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6.11 I2C Serial Interface Controller (I2C)
6.11.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. There are two sets of I2C which supports Power-down wake up function.
6.11.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between master and slave
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down Wake-up function
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6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full-duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction
interface. The NuMicroTM M058S contains one set of SPI controllers performing a serial-to-parallel
conversion on data received from a peripheral device, and a parallel-to-serial conversion on data
transmitted to a peripheral device. SPI controller can be configured as a master or a slave device.
6.12.2 Features
One set of SPI controllers
Supports Master or Slave mode operation
Configurable transfer bit length
Provides transmit/receive can be transferred up to two times word transaction in one transfer
Provides FIFO buffers
Supports MSB or LSB first transfer
Supports byte reorder function
Supports byte or word suspend mode
Supports Slave 3-wire mode
SPI bus clock rate can be configured to equal the system clock rate
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6.13 Analog-to-Digital Converter (ADC)
6.13.1 Overview
The NuMicro™ M058S series contains one 12-bit successive approximation analog-to-digital
converter (SAR A/D converter) with eight input channels. The A/D converter supports four
operation modes: Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D
converter can be started by software, external pin (STADC/P3.2) or PWM trigger.
6.13.2 Features
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed
Up to eight single-end analog input channels or 4 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Up to 760 kSPS sample rate
Four operation modes:
Single mode: A/D conversion is performed one time on a specified channel.
Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
Software Write 1 to ADST bit
External pin (STADC)
PWM trigger with optional start delay period
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Channel 7 supports 3 input sources: external analog voltage, internal band-gap voltage and
Internal temperature sensor output.
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
VDD VSS
VIN
MIN
MAX
UNIT
V
DC Power Supply
-0.3
+7.0
Input Voltage
V
VSS-0.3
VDD +0.3
Oscillator Frequency
1/tCLCL
TA
4
24
MHz
Operating Temperature
-40
+85
C
Storage Temperature
TST
-55
-
+150
120
120
35
C
mA
mA
mA
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O
pin
35
mA
mA
mA
Maximum Current sunk by total I/O
pins
100
100
Maximum Current sourced by total
I/O pins
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
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7.2 DC Electrical Characteristics
(VDD -VSS=2.5~5.5V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operation voltage
VDD
2.5
1.7
5.5
1.9
V
VDD =2.5V ~ 5.5V up to 50 MHz
1.8
LDO Output Voltage
VLDO
VBG
V
V
V
VDD ≥ 2.5V
-5%
1.20
+5%
Band Gap Analog Input
VDD =2.5V ~ 5.5V
Analog Operating
Voltage
AVDD
VDD
VDD
VDD = 5.5V@ 50 MHz,
IDD1
IDD2
20.6
14.4
mA
mA
enable all peripherals and PLL, XTAL=12
MHz
VDD =5.5V@ 50 MHz,
disable all peripherals and enable PLL,
XTAL=12 MHz
Operating Current
Normal Run Mode
@ 50 MHz
VDD = 3.3V@ 50 MHz,
IDD3
IDD4
IDD5
IDD6
IDD7
18.9
12.8
6.2
mA
mA
mA
mA
mA
enable all peripherals and PLL, XTAL=12
MHz
VDD = 3.3V@ 50 MHz,
disable all peripherals and enable PLL,
XTAL=12 MHz
VDD = 5.5V@ 22 MHz,
enable all peripherals and IRC 22 MHz,
disable PLL
VDD =5.5V@ 22 MHz,
disable all peripherals and enable IRC 22
MHz, disable PLL
3.4
Operating Current
Normal Run Mode
@ 22 MHz
VDD = 3.3V@ 22 MHz,
enable all peripherals and IRC 22 MHz,
disable PLL
6.1
VDD = 3.3V@ 22 MHz,
disable all peripherals and enable IRC 22
MHz, disable PLL
IDD8
3.4
mA
VDD = 5.5V@ 12 MHz,
IDD9
IDD10
IDD11
IDD12
5.3
3.7
4.0
2.3
mA
mA
mA
mA
enable all peripherals and disable PLL,
XTAL=12 MHz
VDD = 5.5V@ 12 MHz,
disable all peripherals and disable PLL,
XTAL=12 MHz
Operating Current
Normal Run Mode
@ 12 MHz
VDD = 3.3V@ 12 MHz,
enable all peripherals and disable PLL,
XTAL=12 MHz
VDD = 3.3V@ 12 MHz,
disable all peripherals and disable PLL,
XTAL=12 MHz
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VDD = 5.5V@ 4 MHz,
IDD13
IDD14
IDD15
IDD16
IDD17
3.4
2.6
mA
mA
mA
mA
uA
enable all peripherals and disable PLL,
XTAL=4 MHz
VDD = 5.5V@ 4 MHz,
disable all peripherals and disable PLL,
XTAL=4 MHz
Operating Current
Normal Run Mode
@ 4 MHz
VDD = 3.3V@ 4 MHz,
enable all peripherals and disable PLL,
XTAL=4 MHz
2.0
VDD = 3.3V@ 4 MHz,
disable all peripherals and disable PLL,
XTAL=4 MHz
1.3
VDD = 5.5V@ 10 KHz,
enable all peripherals and IRC10 KHz,
disable PLL
98.7
VDD = 5.5V@ 10 KHz,
disable all peripherals and enable IRC
10KHz, disable PLL
IDD18
IDD19
IDD20
97.4
86.4
85.2
uA
uA
uA
Operating Current
Normal Run Mode
@10 KHz
VDD = 3.3V@ 10 KHz,
enable all peripherals and IRC 10 KHz,
disable PLL
VDD = 3.3V@ 10 KHz,
disable all peripherals and enable IRC 10
KHz, disable PLL
VDD = 5.5V@ 50 MHz, enable all
peripherals and PLL, XTAL=12 MHz
IIDLE1
IIDLE2
16.2
10.0
mA
mA
VDD =5.5V@ 50 MHz, disable all
peripherals and enable PLL, XTAL=12
MHz
Operating Current
Idle Mode
@ 50 MHz
VDD = 3V@ 50 MHz, enable all peripherals
and PLL, XTAL=12 MHz
IIDLE3
IIDLE4
IIDLE5
14.6
8.5
mA
mA
mA
VDD = 3V@50 MHz, disable all peripherals
and enable PLL, XTAL=12 MHz
VDD = 5.5V@ 22MHz,
enable all peripherals and IRC 22MHz,
disable PLL
4.3
VDD =5.5V@ 22MHz,
disable all peripherals and enable IRC 22
MHz, disable PLL
IIDLE6
IIDLE7
IIDLE8
1.5
4.2
1.4
mA
mA
mA
Operating Current
Idle Mode
@ 22 MHz
VDD = 3.3V@ 22 MHz,
enable all peripherals and IRC 22 MHz,
disable PLL
VDD = 3.3V@ 22 MHz,
disable all peripherals and enable IRC
22MHz, disable PLL
VDD = 5.5V@ 12 MHz,
IIDLE9
4.3
2.6
mA
mA
enable all peripherals and disable PLL,
XTAL=12MHz
Operating Current
Idle Mode
@ 12 MHz
VDD = 5.5V@ 12 MHz,
disable all peripherals and disable PLL,
XTAL=12MHz
IIDLE10
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VDD = 3.3V@ 12 MHz,
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
IIDLE16
IIDLE17
2.9
1.3
3.0
2.3
1.7
1.0
97.8
mA
mA
mA
mA
mA
mA
uA
enable all peripherals and disable PLL,
XTAL=12MHz
VDD = 3.3V@ 12 MHz,
disable all peripherals and disable PLL,
XTAL=12MHz
VDD = 5.5V@ 4 MHz,
enable all peripherals and disable PLL,
XTAL=4MHz
VDD = 5.5V@ 4 MHz,
disable all peripherals and disable PLL,
XTAL=4MHz
Operating Current
Idle Mode
@ 4 MHz
VDD = 3.3V@ 4 MHz,
enable all peripherals and disable PLL,
XTAL=4MHz
VDD = 3.3V@ 4 MHz,
disable all peripherals and disable PLL,
XTAL=4MHz
VDD = 5.5V@ 10 KHz,
enable all peripherals and IRC 10 KHz,
disable PLL
VDD = 5.5V@ 10 KHz,
disable all peripherals and enable IRC 10
KHz, disable PLL
IIDLE18
IIDLE19
IIDLE20
96.5
85.5
84.4
uA
uA
uA
Operating Current
Idle Mode
@10 KHz
VDD = 3.3V@ 10 KHz,
enable all peripherals and IRC 10 KHz,
disable PLL
VDD = 3.3V@ 10 KHz,
disable all peripherals and enable IRC 10
KHz, disable PLL
VDD = 5.5V, No load @ Disable BOV
function
IPWD1
IPWD2
10
10
A
A
Standby Current
Power-down Mode
(Deep Sleep Mode)
VDD = 3.0V, No load @ Disable BOV
function
Input Current P0/1/2/3/4
(Quasi-bidirectional
mode)
IIN1
-75
-1
-
+15
+1
VDD = 5.5V, VIN = 0V or VIN= VDD
A
Input Leakage Current
P0/1/2/3/4
ILK
-
VDD = 5.5V, 0<VIN< VDD
A
-0.3
-0.3
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
Input Low Voltage
P0/1/2/3/4 (TTL input)
VIL1
V
VDD
+0.2
2.0
1.5
-
-
VDD = 5.5V
VDD =3.0V
Input High Voltage
P0/1/2/3/4 (TTL input)
VIH1
VIL3
V
V
VDD
+0.2
0
0
-
-
0.8
0.4
VDD = 4.5V
VDD = 2.5V
Input Low Voltage
XT1[*2]
VDD
+0.2
3.5
2.4
-
-
-
V
V
VDD = 5.5V
VDD = 3.0V
Input High Voltage
XT1[*2]
VIH3
VILS
VDD
+0.2
Negative going threshold
(Schmitt input), /RST
-0.5
0.2 VDD
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Positive going threshold
(Schmitt input), /RST
VDD
+0.5
VIHS
0.7 VDD
40
-
-
V
Internal /RST pin pull up
resistor
RRST
150
KΩ
Negative going threshold
(Schmitt input),
P0/1/2/3/4
VILS
-0.5
0.3 VDD
V
Positive going threshold
(Schmitt input),
P0/1/2/3/4
VDD
+0.5
VIHS
0.7 VDD
-300
-
V
ISR11
-370
-450
VDD = 4.5V, VS = 2.4V
A
Source Current
P0/1/2/3/4 (Quasi-
bidirectional Mode)
ISR12
ISR13
ISR21
-50
-40
-20
-70
-60
-24
-90
-80
-28
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
VDD = 4.5V, VS = 2.4V
A
A
mA
Source Current
P0/1/2/3/4 (Push-pull
Mode)
ISR22
ISR23
-4
-3
-6
-5
-8
-7
mA
mA
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
ISK11
ISK12
ISK13
10
7
16
10
9
20
13
12
mA
mA
mA
VDD = 4.5V, VS = 0.45V
VDD = 2.7V, VS = 0.45V
VDD = 2.5V, VS = 0.45V
Sink Current P0/1/2/3/4
(Quasi-bidirectional and
Push-pull Mode)
6
Brown-Out voltage with
BOV_VL [1:0] =00b
VBO2.2
VBO2.7
VBO3.7
VBO4.4
VBH
2.0
2.5
3.5
4.2
30
2.2
2.7
3.7
4.4
-
2.4
2.9
3.9
4.6
150
V
V
VDD =5.5V
VDD =5.5V
Brown-Out voltage with
BOV_VL [1:0] =01b
Brown-Out voltage with
BOV_VL [1:0] =10b
V
VDD =5.5V
Brown-Out voltage with
BOV_VL [1:0] =11b
V
VDD =5.5V
Hysteresis range of BOD
voltage
mV
VDD = 2.5V~5.5V
Notes:
1. /RST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0 - P7 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, 5he
transition current reaches its maximum value when Vin approximates to 2V.
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7.3 AC Electrical Characteristics
7.3.1 External Crystal
t
CLCL
t
CLCH
t
CLCX
t
t
CHCL
CHCX
Note: Duty cycle is 50%.
PARAMETER
Clock High Time
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITION
tCHCX
tCLCX
tCLCH
tCHCL
20
20
-
-
-
-
-
-
nS
nS
nS
nS
Clock Low Time
Clock Rise Time
Clock Fall Time
-
10
10
-
7.3.2 External Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
24
UNIT
MHz
oC
Input clock frequency
Temperature
VDD
External crystal
4
-40
2.5
-
12
-
-
85
-
5
5.5
-
V
Operating current
12 MHz@ VDD = 5V
1
mA
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7.3.3 Typical Crystal Application Circuits
CRYSTAL
C1
C2
Optional
4 MHz ~ 24 MHz
(Depend on crystal specification)
C1
C2
XTAL1
XTAL2
Figure 7.3-1 Typical Crystal Application Circuit
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7.3.4 Internal 22.1184 MHz RC Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Center Frequency
-
-
22.1184
-
MHz
%
+25oC; VDD =5V
-40oC~+85oC;
-3
+3
+5
-
Calibrated Internal Oscillator
Frequency
-5
-
-
%
VDD=2.5V~5.5V
Operating current
VDD =5V
500
uA
7.3.5 Internal 10 kHz RC Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Supply voltage[1]
-
2.5
-
-
10
-
5.5
-
V
kHz
%
Center Frequency
-
+25oC; VDD =5V
-30
+30
Calibrated Internal Oscillator
Frequency
-40oC~+85oC;
-50
-
-
+50
-
%
VDD=2.5V~5.5V
Operating current
VDD =5V
5
uA
Notes:
1. Internal operation voltage comes from LDO.
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7.4 Analog Characteristics
7.4.1 12-bit SARADC Specification
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
12
UNIT
Bit
-
Resolution
-
-
-
-
-
-
-1~2.0
-1~4.0
±4
DNL
INL
EO
Differential nonlinearity error
Integral nonlinearity error
Offset error
LSB
LSB
LSB
-
±2
3
-
EG
Gain error (Transfer gain)
Full scale error
1
1.005
EF
±2
LSB
AVDD =5V
AVDD =3V
5
EA
-
Absolute error
Monotonic
LSB
4
Guaranteed
AVDD =5V
AVDD =3V
16
8
FADC
ADC clock frequency
-
-
-
MHz
FS
TS
Sample rate
-
760
K SPS
ADC
clock
Sampling time
7
VDDA
IDD
IDDA
VIN
Supply voltage
3
-
-
5.5
V
mA
mA
V
Supply current (Avg.)
0.5
2.5
-
-
-
Supply current (Avg.) @ AVDD =3.0V
Analog Input voltage
-
[1]
Vref
0
Note[1]: Vref is connected to AVDD for LQFP48/QFN33 package.
Nov. 27, 2014
Page 59 of 72
Rev.1.03
NuMicro M058S Series Datasheet
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated
transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the
offset and gain error from the actual transfer curve.
Nov. 27, 2014
Page 60 of 72
Rev.1.03
NuMicro M058S Series Datasheet
7.4.2 LDO Specification
RAMETER
MIN
2.5
TYP
MAX
5.5
UNIT
V
NOTE
Input Voltage
VDD input voltage
LDO output voltage
Output Voltage
-10%
1.8
+10%
V
℃
Temperature
-40
-
25
1
85
-
C
uF
Resr=1ohm
Note:
1. It is recommended a 100nF bypass capacitor is connected between VDD and the closest VSS
pin of the device.
2. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin
and the closest VSS pin of the device.
Nov. 27, 2014
Page 61 of 72
Rev.1.03
NuMicro M058S Series Datasheet
7.4.3 Low Voltage Reset Specification
PARAMETER
CONDITION
MIN.
2.5
-40
-
TYP.
MAX.
5.5
85
UNIT
V
Operation voltage
-
5
25
℃
Temperature
-
Quiescent current
VDD =5.5V
-
5
uA
Temperature=25°
Temperature=-40°
1.7
-
2.0
2.3
-
V
V
Threshold voltage
Hysteresis
2.3
Temperature=85°
-
-
1.8
0
-
V
V
0
0
7.4.4 Brown-Out Detector Specification
Parameter
Condition
Min.
Typ.
Max.
5.5
Unit
V
Operation voltage
Quiescent current
-
2.5
-
-
-
AVDD =5.5V
-
140
μA
℃
V
Temperature
-40
4.2
25
85
BOV_VL[1:0]=11
BOV_VL [1:0]=10
BOV_VL [1:0]=01
BOV_VL [1:0]=00
4.4
4.6
3.5
2.6
3.7
2.7
2.2
3.9
2.8
V
Brown-Out voltage
V
2.1
2.3
V
Hysteresis
30m
150m
V
-
-
7.4.5 Power-On Reset Specification (5V)
Parameter
Condition
Min.
Typ.
25
2
Max.
Unit
℃
Temperature
-
V+
-40
85
-
Reset voltage
Quiescent current
-
-
V
Vin>reset voltage
1
-
nA
7.4.6 Temperature Sensor Specification
PARAMETER
CONDITIONS
MIN.
TYP.
1.8
MAX. UNIT
Supply voltage[1]
Temperature
Gain
1.62
-40
1.98
85
V
℃
-
mV/℃
-1.72
-1.76
-1.80
Nov. 27, 2014
Page 62 of 72
Rev.1.03
NuMicro M058S Series Datasheet
Temp=0 ℃
Offset
717
725
733
mV
Note[1]: Internal operation voltage comes from LDO.
7.4.7
Comparator Specification
PARAMETER
Temperature
CONDITION
MIN.
-40
2.4
-
TYP.
MAX. UNIT
℃
V
-
-
-
-
-
-
-
25
3
85
5.5
VDD
VDD current
40
10
-
80
uA
mV
V
Input offset voltage
Output swing
20
0.1
0.1
-
VDD -0.1
VDD -0.1
-
Input common mode range
DC gain
-
V
70
dB
@VCM=1.2 V and
VDIFF=0.1 V
Propagation delay
Hysteresis
-
-
200
±10
-
-
ns
@VCM=0.2 V ~ VDD -0.2V
mV
@CINP=1.3 V
CINN=1.2 V
Stable time
-
-
2
us
Nov. 27, 2014
Page 63 of 72
Rev.1.03
NuMicro M058S Series Datasheet
7.5 Flash DC Electrical Characteristics
SYMBOL
PARAMETER
CONDITIONS
MIN.
10
TYP.
MAX.
UNIT
year
ms
Temp=85 ℃
TRET
Retention time
TERASE
TMESS
TPROG
VDD
Page erase time
Mess erase time
Program time
19
20
40
40
1.8
21
50
30
ms
38
42
us
Supply voltage
1.62
1.98
0.25
7
V[2]
IDD1
Read current
mA
mA
uA
IDD2
Program/Erase current
Power down current
IPD
1
20
1. Number of program/erase cycles.
2. VDD is source from chip LDO output voltage.
3. Guaranteed by design, not test in production.
Nov. 27, 2014
Page 64 of 72
Rev.1.03
NuMicro M058S Series Datasheet
7.6 SPI Dynamic Characteristics
7.6.1 Dynamic Characteristics of Data Input and Output Pin
Symbol Parameter Min. Typ. Max.
SPI Master Mode (VDD = 4.5 V ~ 5.5 V, 30 pF loading Capacitor)
Unit
tDS
tDH
tV
Data setup time
0
3
-
-
-
ns
ns
ns
Data hold time
-
-
Data output valid time
3.5
4.5
SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 30 pF loading Capacitor)
tDS
tDH
tV
Data setup time
ns
ns
ns
Data hold time
Data output valid time
SPI Slave Mode (VDD = 4.5 V ~ 5.5 V, 30 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
3
-
-
-
ns
ns
ns
Data hold time
-
-
Data output valid time
20
27.5
SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 30 pF loading Capacitor)
tDS
tDH
tV
Data setup time
ns
ns
ns
Data hold time
Data output valid time
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 7.6-1 SPI Master Mode Timing
Nov. 27, 2014
Page 65 of 72
Rev.1.03
NuMicro M058S Series Datasheet
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 7.6-2 SPI Slave Mode Timing
Nov. 27, 2014
Page 66 of 72
Rev.1.03
NuMicro M058S Series Datasheet
8
PACKAGE DIMENSIONS
8.1 TSSOP-20 (4.4x6.5 mm)
Nov. 27, 2014
Page 67 of 72
Rev.1.03
NuMicro M058S Series Datasheet
8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm)
Nov. 27, 2014
Page 68 of 72
Rev.1.03
NuMicro M058S Series Datasheet
8.3 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Symbol
Dimension in mm
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
L
0.024 0.030
0.45
0
0.039
0.004
7
1
L
Y
0.10
7
0
0
Nov. 27, 2014
Page 69 of 72
Rev.1.03
NuMicro M058S Series Datasheet
8.4 LQFP-64 (7x7x1.4mm2 Footprint 2.0mm)
Nov. 27, 2014
Page 70 of 72
Rev.1.03
NuMicro M058S Series Datasheet
9
REVISION HISTORY
Revision
Date
Description
1.00
Jun. 12, 2014
Jul. 24, 2014
First version
1.01
Corrected 7.5 Flash DC Electrical Characteristics.
1.
2.
3.
4.
5.
Adjusted the format of Table 4.1-1 NuMicro M058S Series Selection Guide.
Updated Figure 4.1-1 NuMicro M058S Series Selection Code.
Added Chapter 3 ABBREVIATIONS.
Added 7.6 SPI Dynamic Characteristics.
Changed the order of Chapter 5 BLOCK DIAGRAM and Chapter 6
FUNCTIONAL DESCRIPTION.
1.02
1.03
Sep. 12, 2014
Nov. 27, 2014
6.
1.
Fixed typos and obscure descriptions.
Fixed typos of Table 4.1-1 NuMicro M058S Series Selection Guide
Nov. 27, 2014
Page 71 of 72
Rev.1.03
NuMicro M058S Series Datasheet
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Nov. 27, 2014
Page 72 of 72
Rev.1.03
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