M2351ZIAE [NUVOTON]
NuMicro® Family;
| 型号： | M2351ZIAE |
| 厂家： | 
NUVOTON |
| 描述： | NuMicro® Family |
| 文件： | 总245页 (文件大小：5936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M2351
NuMicro® Family
M2351 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of Micro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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TABLE OF CONTENTS
1 GENERAL DESCRIPTION.............................................................................11
2 FEATURE DESCRIPTION .............................................................................13
3 PARTS INFORMATION .................................................................................24
3.1 Summary.......................................................................................................................24
3.2 Package Type...............................................................................................................24
3.3 NuMicro® M2351 Series Selection Guide ................................................................25
3.4 NuMicro® M2351 Naming Rule..................................................................................26
4 PIN CONFIGURATION...................................................................................27
4.1 NuMicro® M2351 Series QFN33 Pin Diagram.........................................................27
4.2 NuMicro® M2351 Series WLCSP49 Pin Diagram...................................................28
4.3 NuMicro® M2351 Series LQFP64 Pin Diagram.......................................................29
4.4 NuMicro® M2351 Series LQFP128 Pin Diagram.....................................................30
4.5 M2351 Performance Series Pin Description............................................................31
4.6 M2351 Multi-function Summary Table Sorted by GPIO .........................................81
5 BLOCK DIAGRAM.......................................................................................107
5.1 NuMicro® M2351 Series Block Diagram....................................................................107
5.2 NuMicro® M2351 Series TrustZone® Architecture.................................................108
6 FUNCTIONAL DESCRIPTION .....................................................................109
6.1 Arm® Cortex®-M23 Core ...........................................................................................109
6.2 Arm® TrustZone® ........................................................................................................111
6.2.1 Address Space Partition ............................................................................................. 112
6.2.2 Security Attribute Configuration ................................................................................. 114
6.2.3 System Address Map and Access Scheme ............................................................. 115
6.3 System Manager........................................................................................................118
6.3.1 Overview ....................................................................................................................... 118
6.3.2 Reset.............................................................................................................................. 118
6.3.3 Power Modes and Wake-up Sources........................................................................ 124
6.3.4 System Power Distribution ......................................................................................... 128
6.3.5 Bus Matrix ..................................................................................................................... 130
6.3.6 System Memory Map................................................................................................... 130
6.3.7 Implementation Defined Attribution Unit (IDAU)...................................................... 134
6.3.8 SRAM Memory Orginization....................................................................................... 136
6.3.9 Auto Trim....................................................................................................................... 138
6.3.10System Timer (SysTick) .............................................................................................. 139
6.3.11Nested Vectored Interrupt Controller (NVIC) ........................................................... 139
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6.4 Clock Controller..........................................................................................................140
6.4.1 Overview ....................................................................................................................... 140
6.4.2 Clock Generator........................................................................................................... 143
6.4.3 System Clock and SysTick Clock .............................................................................. 145
6.4.4 Peripherals Clock......................................................................................................... 146
6.4.5 Power-down Mode Clock............................................................................................ 147
6.4.6 Clock Output................................................................................................................. 147
6.5 Security Configuration Unit (SCU)...........................................................................148
6.5.1 Overview ....................................................................................................................... 148
6.5.2 Features ........................................................................................................................ 148
6.6 True Random Number Generator (TRNG).............................................................149
6.6.1 Overview ....................................................................................................................... 149
6.6.2 Features ........................................................................................................................ 149
6.7 Flash Memeory Controller (FMC)............................................................................150
6.7.1 Overview ....................................................................................................................... 150
6.7.2 Features ........................................................................................................................ 150
6.8 General Purpose I/O (GPIO)....................................................................................151
6.8.1 Overview ....................................................................................................................... 151
6.8.2 Features ........................................................................................................................ 151
6.9 PDMA Controller (PDMA).........................................................................................152
6.9.1 Overview ....................................................................................................................... 152
6.9.2 Features ........................................................................................................................ 152
6.10 Timer Controller (TMR) .......................................................................................153
6.10.1Overview ....................................................................................................................... 153
6.10.2Features ........................................................................................................................ 153
6.11 Watchdog Timer (WDT).......................................................................................155
6.11.1Overview ....................................................................................................................... 155
6.11.2Features ........................................................................................................................ 155
6.12 Window Watchdog Timer (WWDT) ...................................................................156
6.12.1Overview ....................................................................................................................... 156
6.12.2Features ........................................................................................................................ 156
6.13 Real Time Clock (RTC) .......................................................................................157
6.13.1Overview ....................................................................................................................... 157
6.13.2Features ........................................................................................................................ 157
6.14 EPWM Generator and Capture Timer (EPWM)...............................................158
6.14.1Overview ....................................................................................................................... 158
6.14.2Features ........................................................................................................................ 158
6.15 Basic PWM Generator and Capture Timer (BPWM) ......................................160
6.15.1Overview ....................................................................................................................... 160
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6.15.2Features ........................................................................................................................ 160
6.16 Quadrature Encoder Interface (QEI).................................................................161
6.16.1Overview ....................................................................................................................... 161
6.16.2Features ........................................................................................................................ 161
6.17 Enhanced Input Capture Timer (ECAP) ...........................................................162
6.17.1Overview ....................................................................................................................... 162
6.17.2Features ........................................................................................................................ 162
6.18 UART Interface Controller (UART)....................................................................163
6.18.1Overview ....................................................................................................................... 163
6.18.2Features ........................................................................................................................ 163
6.19 Smart Card Host Interface (SC).........................................................................165
6.19.1Overview ....................................................................................................................... 165
6.19.2Features ........................................................................................................................ 165
6.20 I2S Controller (I2S)................................................................................................166
6.20.1Overview ....................................................................................................................... 166
6.20.2Features ........................................................................................................................ 166
6.21 Serial Peripheral Interface (SPI)........................................................................167
6.21.1Overview ....................................................................................................................... 167
6.21.2Features ........................................................................................................................ 167
6.22 Quad Serial Peripheral Interface (QSPI)..........................................................168
6.22.1Overview ....................................................................................................................... 168
6.22.2Features ........................................................................................................................ 168
6.23 I2C Serial Interface Controller (I2C) ...................................................................169
6.23.1Overview ....................................................................................................................... 169
6.23.2Features ........................................................................................................................ 169
6.24 USCI - Universal Serial Control Interface Controller (USCI).........................170
6.24.1Overview ....................................................................................................................... 170
6.24.2Features ........................................................................................................................ 170
6.25 USCI – UART Mode.............................................................................................171
6.25.1Overview ....................................................................................................................... 171
6.25.2Features ........................................................................................................................ 171
6.26 USCI - SPI Mode..................................................................................................172
6.26.1Overview ....................................................................................................................... 172
6.26.2Features ........................................................................................................................ 172
6.27 USCI - I2C Mode...................................................................................................174
6.27.1Overview ....................................................................................................................... 174
6.27.2Features ........................................................................................................................ 174
6.28 Controller Area Network (CAN)..........................................................................175
6.28.1Overview ....................................................................................................................... 175
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6.28.2Features ........................................................................................................................ 175
6.29 Secure Digital Host Controller (SDH)................................................................176
6.29.1Overview ....................................................................................................................... 176
6.29.2Features ........................................................................................................................ 176
6.30 External Bus Interface (EBI)...............................................................................177
6.30.1Overview ....................................................................................................................... 177
6.30.2Features ........................................................................................................................ 177
6.31 USB 1.1 Device Controller (USBD)...................................................................178
6.31.1Overview ....................................................................................................................... 178
6.31.2Features ........................................................................................................................ 178
6.32 USB 1.1 Host Controller (USBH).......................................................................179
6.32.1Overview ....................................................................................................................... 179
6.32.2Features ........................................................................................................................ 179
6.33 USB On-The-Go (OTG) ......................................................................................180
6.33.1Overview ....................................................................................................................... 180
6.33.2Features ........................................................................................................................ 180
6.34 CRC Controller (CRC).........................................................................................181
6.34.1Overview ....................................................................................................................... 181
6.34.2Features ........................................................................................................................ 181
6.35 Cryptographic Accelerator (CRYPTO)..............................................................182
6.35.1Overview ....................................................................................................................... 182
6.35.2Features ........................................................................................................................ 182
6.36 Enhanced 12-bit Analog-to-Digital Converter (EADC) ...................................184
6.36.1Overview ....................................................................................................................... 184
6.36.2Features ........................................................................................................................ 184
6.37 Digital to Analog Converter (DAC).....................................................................186
6.37.1Overview ....................................................................................................................... 186
6.37.2Features ........................................................................................................................ 186
6.38 Analog Comparator Controller (ACMP)............................................................187
6.38.1Overview ....................................................................................................................... 187
6.38.2Features ........................................................................................................................ 187
7 APPLICATION CIRCUIT ..............................................................................188
7.1 Power Supply Scheme with External VREF .............................................................188
7.2 Power Supply Scheme with Internal VREF ..............................................................189
7.3 Peripheral Application Scheme................................................................................190
8 ELECTRICAL CHARACTERISTICS............................................................191
8.1 Absolute Maximum Ratings......................................................................................191
8.1.1 Voltage Characteristics ............................................................................................... 191
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8.1.2 Current Characteristics ............................................................................................... 191
8.1.3 Thermal Characteristics.............................................................................................. 192
8.1.4 EMC Characteristics .................................................................................................... 192
8.2 General Operating Conditions .................................................................................194
8.3 DC Electrical Characteristics....................................................................................195
8.3.1 Typical Current Consumption..................................................................................... 195
8.3.2 On-chip Peripheral Current Consumption ................................................................ 206
8.3.3 Wakeup Time................................................................................................................ 208
8.3.4 I/O DC Characteristics................................................................................................. 209
8.4 AC Electrical Characteristics....................................................................................211
8.4.1 External 4~24 MHz High Speed Crystal (HXT) Characteristics............................ 211
8.4.2 External 4~24 MHz High Speed Crystal (OSC) Input Clock.................................. 212
8.4.3 External 32.768 kHz Low Speed Crystal (LXT) Characteristics............................ 214
8.4.4 External 32.768 kHz Low Speed Crystal (OSC) Input Clock................................. 214
8.4.5 12 MHz Internal High Speed RC Oscillator (HIRC) ................................................ 215
8.4.6 48 MHz Internal High Speed RC Oscillator (HIRC48)............................................ 215
8.4.7 10 kHz Internal Low Speed RC Oscillator (LIRC)................................................... 216
8.4.8 PLL Characteristics...................................................................................................... 216
8.4.9 I/O AC Characteristics................................................................................................. 217
8.5 Analog Electrical Characteristics.............................................................................218
8.5.1 LDO................................................................................................................................ 218
8.5.2 DC-DC ........................................................................................................................... 218
8.5.3 Low-Voltage Reset....................................................................................................... 219
8.5.4 Internal Voltage Reference......................................................................................... 221
8.5.5 12-bit ADC..................................................................................................................... 222
8.5.6 Temperature Sensor.................................................................................................... 225
8.5.7 Digital to Analog Converter (DAC)............................................................................. 225
8.5.8 Analog Comparator Controller (ACMP).................................................................... 227
8.6 Flash DC Electrical Characteristics.........................................................................228
8.7 I2C Dynamic Characteristics.....................................................................................229
8.8 SPI Dynamic Characteristics....................................................................................230
8.9 I2S Dynamic Characteristics.....................................................................................232
8.10 USCI - I2C Dynamic Characteristics..................................................................234
8.11 USCI - SPI Dynamic Characteristics.................................................................235
8.12 USB Characteristics.............................................................................................237
8.12.1USB Full-Speed PHY Characteristics....................................................................... 237
8.13 SDIO Characteristics...........................................................................................238
8.13.1Default Mode Timing.................................................................................................... 238
8.13.2SDIO Dynamic Characteristics .................................................................................. 239
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9 PACKAGE DIMENSIONS ............................................................................240
9.1 QFN 33 (5x5x0.8 mm Pitch 0.5 mm) ......................................................................240
9.2 LQFP 64 (7x7x1.4 mm Footprint 2.0 mm)..............................................................241
9.3 LQFP 128 (14x14x1.4 mm Footprint 2.0 mm).......................................................242
10ABBREVIATIONS ........................................................................................243
11REVISION HISTORY....................................................................................245
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LIST OF FIGURES
Figure 4.1-1 NuMicro® M2351 Series QFN 33-pin Diagram ..........................................................27
Figure 4.2-1 NuMicro® M2351 Series WLCSP 49-pin Diagram .....................................................28
Figure 4.3-1 NuMicro® M2351 Series LQFP 64-pin Diagram.........................................................29
Figure 4.4-1 NuMicro® M2351 Series LQFP 128-pin Diagram.......................................................30
Figure 5.1-1 NuMicro® M2351 Block Diagram..............................................................................107
Figure 5.2-1 NuMicro® M2351 Series Cortex®-M23 Architecture .......................................................108
Figure 6.1-1 Cortex® -M23 Block Diagram ....................................................................................109
Figure 6.2-1 Secure World View and Non-secure World View on a Chip....................................111
Figure 6.2-2 The 4 GB Memory Map Divided Into Secure and Non-secure Regions by IDAU....113
Figure 6.2-3 Typical Setting of SAU .............................................................................................114
Figure 6.2-4 Example of SRAM Divided Into Secure Block and Non-secure Block.....................116
Figure 6.2-5 Checking Point of Accesses.....................................................................................117
Figure 6.3-1 System Reset Sources.............................................................................................119
Figure 6.3-2 nRESET Reset Waveform .......................................................................................121
Figure 6.3-3 Power-on Reset (POR) Waveform...........................................................................121
Figure 6.3-4 Low Voltage Reset (LVR) Waveform .......................................................................122
Figure 6.3-5 Brown-out Detector (BOD) Waveform .....................................................................123
Figure 6.3-6 Power Mode State Machine.....................................................................................125
Figure 6.3-7 Power Distribution Diagram .....................................................................................129
Figure 6.3-8 IDAU Memory Map...................................................................................................135
Figure 6.3-9 IDAU Block Diagram ................................................................................................136
Figure 6.3-10 SRAM Block Diagram ............................................................................................136
Figure 6.3-11 SRAM Memory Organization .................................................................................137
Figure 6.3-12 SRAM Marco Organization ....................................................................................138
Figure 6.4-1 Clock Generator Global View Diagram (1/3)............................................................141
Figure 6.4-2 Clock Generator Global View Diagram (2/3)............................................................142
Figure 6.4-3 Clock Generator Global View Diagram (3/3)............................................................143
Figure 6.4-4 Clock Generator Block Diagram...............................................................................144
Figure 6.4-5 System Clock Block Diagram...................................................................................145
Figure 6.4-6 HXT Stop Protect Procedure....................................................................................146
Figure 6.4-7 SysTick Clock Control Block Diagram .....................................................................146
Figure 6.4-8 Clock Output Block Diagram....................................................................................147
Figure 6.26-1 SPI Master Mode Application Block Diagram ........................................................172
Figure 6.26-2 SPI Slave Mode Application Block Diagram ..........................................................172
Figure 6.27-1 I2C Bus Timing .......................................................................................................174
Figure 8.4-1 Typical Crystal Application Circuit............................................................................212
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Figure 8.4-2 Typical Crystal Application Circuit............................................................................214
Figure 8.5-1 Power-up Ramp Condition.......................................................................................220
Figure 8.5-2 Typical Connection with Internal Voltage Reference ...............................................221
Figure 8.5-3 Typical Connection Using the ADC..........................................................................224
Figure 8.7-1 I2C Timing Diagram..................................................................................................229
Figure 8.8-1 SPI Master Mode Timing Diagram...........................................................................230
Figure 8.8-2 SPI Slave Mode Timing Diagram.............................................................................231
Figure 8.9-1 I2S Master Mode Timing Diagram............................................................................232
Figure 8.9-2 I2S Slave Mode Timing Diagram..............................................................................233
Figure 8.10-1 I2C Timing Diagram................................................................................................234
Figure 8.11-1 SPI Master Mode Timing Diagram.........................................................................235
Figure 8.11-2 SPI Slave Mode Timing Diagram...........................................................................236
Figure 8.13-1 SDIO Default Mode................................................................................................238
Figure 8.13-2 SDIO High-speed Mode.........................................................................................239
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List of Tables
Table 6.2-1 Peripherals and Regions that are Always Secure.....................................................115
Table 6.3-1 Reset Value of Registers...........................................................................................121
Table 6.3-2 Power Mode Table ....................................................................................................124
Table 6.3-3 Power Mode Entry Setting Table...............................................................................125
Table 6.3-4 Power Mode Difference Table...................................................................................125
Table 6.3-5 Clocks in Power Modes.............................................................................................126
Table 6.3-6 Condition of Entering Power-down Mode Again .......................................................128
Table 6.3-7 Address Space Assignments for On-Chip Controllers ..............................................132
Table 6.18-1 NuMicro® M2351 Series UART Features................................................................164
Table 8.1-1 Voltage Characteristics .............................................................................................191
Table 8.1-2 Current Characteristics..............................................................................................192
Table 8.1-3 Thermal Characteristics ............................................................................................192
Table 8.1-4 EMC Characteristics..................................................................................................193
Table 8.3-1 Current Consumption in LDO Normal Run Mode......................................................196
Table 8.3-2 Current Consumption in DC-DC Normal Run Mode .................................................197
Table 8.3-3 Current consumption in LDO Idle mode....................................................................198
Table 8.3-4 Current Consumption in DC-DC Idle Mode...............................................................199
Table 8.3-5 Chip Current Consumption in Power-down Mode.....................................................205
Table 8.3-6 Current Consumption for VBAT ...................................................................................206
Table 8.3-7 Low-power Mode Wakeup Timings...........................................................................208
Table 8.3-8 PIN input Characteristics...........................................................................................209
Table 8.3-9 PIN Output Characteristics........................................................................................210
Table 8.3-10 nRESET Pin Characteristics ...................................................................................210
Table 8.4-1 External 4~24 MHz High Speed Crystal (HXT) Oscillator.........................................211
Table 8.4-2 External 32.768 kHz Crystal......................................................................................214
Table 8.4-3 I/O AC Characteristics...............................................................................................217
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1 GENERAL DESCRIPTION
NuMicro® M2351 Series – a TrustZone® empowered microcontroller series focusing on IoT security.
The rise of the internet of things (IoT) era has increased awareness for the integration of the physical
world into digital systems. While the efficiency improvements and economic benefits coming behind
the digitization of our everyday lives, it has also placed pressure on system designers to deliver the
innovative products capable of connecting and exchanging data incessantly. Since security and power
consumption are the key requirements of IoT applications, Nuvoton NuMicro® M2351 series is
excellence in supporting the proliferation of intelligent connected devices.
The NuMicro® M2351 microcontroller series is powered by Arm® Cortex® -M23 core with TrustZone®
for Armv8-M architecture, which elevates the traditional firmware security to the new level of robust
software security.
The low-power M2351 microcontrollers run up to 64 MHz with up to 512 Kbytes embedded Flash
memory in dual bank mode, supporting secure OTA (Over-The-Air) firmware update and up to 96
Kbytes embedded SRAM. Furthermore, the M2351 series provides high-performance connectivity
peripheral interfaces such as UART, SPI, I2C, GPIOs, USB and ISO 7816-3 for smart card reader. Its
secure and low-power features strengthen the innovation of IoT security.
TrustZone® for Armv8-M Empowered
The NuMicro® M2351 series is empowered by Arm® TrustZone® for Armv8-M architecture. The
TrustZone® technology is a System on Chip (SoC) and CPU system-wide approach to security. In
addition to the firmware-level security, the M2351 series offers a more enhanced software-level
security for more robust security and greater power efficiency.
Nuvoton Security Functions Strengthened
In addition to the TrustZone® technology, the NuMicro® M2351 series is also equipped with rich
functions to improve system security. The Secure Bootloader supports trusted boot feature. The
hardware crypto accelerators, including ECC, support encryption and decryption operations to offload
the main processor’s computing power. The KPROM is a password protection mechanism to allow
Flash memory write and erase. The XOM defines execute-only memory regions to protect critical
program codes. The Flash lock bits are designed to disable external Flash-read/ -write and debug
interface. Tamper detection pins can detect the state transition on the tamper pins.
Low-power Technology for IoT Innovation
Other than security, low power is also vital for IoT applications. Regarding the power consumption of
the M2351 series, the normal run mode consumes 97 μA/MHz in LDO mode and 45 μA/MHz in DC-DC
mode. The current consumption of Standby Power-down mode is 2.8 μA and the Deep Power-down
mode without VBAT is less than 2μA.
Arm® PSA with Nuvoton Secure Microcontroller Platform (NuSMP) Supported
The Platform Security Architecture (PSA) is a holistic set of threat models, security analysis, hardware
and firmware architecture specifications, and an open source firmware reference implementation. The
PSA is a contribution from Arm® to the entire IoT ecosystem, offering common ground rules and a
more economical approach to building more secure devices.
Nuvoton has developed the Nuvoton Secure Microcontroller Platform (NuSMP) to support Arm® PSA.
The NuSMP is a range of hardware and software mixture technologies for security requirements of
general purpose and secure IoT microcontrollers. With NuSMP, developers can easily achieve the
secure services with the M2351 series in coverage of: Trusted Boot (Root of Trust), Secure OTA
(Over-The-Air) firmware update (including secure software download), Power Management APIs for
non-secure world and PC side crypto related development software tool.
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Security Features
Applications
- Arm® Cortex® -M23 TrustZone® Technology
- IoT Devices with Secure Connection
- 8 regions MPU_NS (for non-secure world);
- Collaborative Secure Software
8 regions MPU_S (for secure world)
Development Business Model
- 8 regions Security Attribution Units (SAU)
- Implementation Defined Attribution Unit (IDAU)
- 2 KB OTP ROM with additional 1KB lock bits
- Hardware Crypto Accelerators
- Fingerprint Card, Fingerprint Lock
- Smart Home Appliance
- Smart City Facilities
- Wireless Sensor Node Device (WSND)
- Auto Meter Reading (AMR)
- Portable Wireless Data Collector
- Digital Currency Authentication
- CRC calculation unit
- Up to 6 tamper detection pins
- 96-bit Unique ID (UID), 128-bit Unique Customer ID
(UCID)
- Trusted Execution Environment (TEE) with
- Arm® Platform Security Architecture (PSA) and
Trusted Base System Architecture-M (TBSA-M)
supported
Trusted Applications (TAs)
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2 FEATURE DESCRIPTION
Core and System
Arm® Cortex® -M23 processor, running up to 64 MHz
64MHz at 1.8V-3.6V; 48MHz at 1.7V-3.6V
Supports Arm® TrustZone® technology
Built-in PMSAv8 Memory Protection Unit (MPU)
Built-in Security Attribution Unit (SAU)
Built-in Nested Vectored Interrupt Controller (NVIC)
Built-in Embedded Trace Macrocell (ETM)
Arm® Cortex® -M23
32-bit Single-cycle hardware multiplier and 32-bit 17-cycle hardware
divider
24-bit system tick timer
Supports Programmble and maskable interrupt
Supports Low Power Sleep mode by WFI and WFE instructions
Supports single cycle I/O access
Configures SRAM’s secure attribution block by block
Configures GPIO’s secure attribution port by port
Monitor secure violation incident on the chip
Secure Configuration Unit
(SCU)
24-bit non-secure state monitor timer
Eight-level BOD with brown-out interrupt and reset option
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
(3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V)
LVR with 1.5V threshold voltage level
Dual voltage regulator is available for DC-DC converter or LDO
Supports 1.26v and 1.2v core voltage
Supports Power-down mode
Supports Standby Power-down mode
Supports low leakage Power-down mode
Supports ultra low leakage Power-down mode
Supports fast wake-up Power-down mode
Supports deep Power-down mode
Power Manager
96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Security
Memories
Factory pre-loaded 32 KB mask ROM for secure boot procedure
Boot Loader
Flash
Root of Trust for Nuvoton Secure Microcontroller Platform
Dual bank 512 KB on-chip Application ROM (APROM) for Over-
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The-Air (OTA) upgrade
64 MHz maximum frequency, with performance at zero wait cycle in
continuous address read access
4 KB on-chip Flash memory for user-defined loader (LDROM)
4 KB non-readbale Key Protection ROM (KPROM) for firmware
programming protection
2 KB OTP for general-purpose control use, (2 KB data + 1 KB lock
bit) easy for PLM (Product Lifecycle Management) implementation
Execute Only Memory (XOM) for software intelectual property
protection
32 KB Secure Boot ROM
All on-chip Flash support 2 KB page erase
Fast Flash programming verification with CRC
On-chip Flash programming with In-Chip Programming (ICP), In-
System Programming (ISP) and In-Application Programming (IAP)
capabilities
Configurable boot up sources including boot loader, user-defined
loader (LDROM) or Application ROM (APROM)
2-wired ICP Flash updating through SWD interface
32-bit/64-bit and multi-word Flash programming function
Up to 96 KB on-chip SRAM includes:
–
32 KB SRAM located in bank 0 that supports hardware
parity check; Exception (NMI) generated upon a parity check
error
SRAM
–
64 KB SRAM located in bank 1
Byte-, half-word- and word-access
PDMA operation
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials
Programmable initial value and seed value
Programmable order reverse setting and one’s complement setting
for input data and CRC checksum
Cyclic Redundancy
Calculation (CRC)
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
16 independent and configurable channels for automatic data
transfer between memories and peripherals
8 channels of PDMA1 can be configured as secure or non-secure
channels
Peripheral DMA (PDMA)
Supports time-out function when transfer time-out
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using Scatter-
Gather Transfer mode
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Stride function for rectangle image data movement
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
4~24 MHz High-speed external crystal oscillator (HXT) for precise
timing operation
32.768 kHz Low-speed external crystal oscillator (LXT) for RTC
External Clock Source
function and low-power system operation
Supports clock failure detection for external crystal oscillators and
exception generation (NMI)
12 MHz High-speed Internal RC oscillator (HIRC) trimmed to 0.25%
accuracy that can optionally be used as a system clock
48 MHz High-speed Internal RC oscillator (HIRC48) trimmed to
0.25% accuracy that can optionally be used as a system clock
10 kHz Low-speed Internal RC oscillator (LIRC) for watchdog timer
Internal Clock Source
and wakeup operation
32 kHz Low-speed Internal RC oscillator (LIRC32) for RTC function
Up to 144 MHz on-chip PLL, sourced from HIRC or HXT, allowing
for CPU operation up to the maximum CPU frequency without the
need for a high-frequency crystal
Real-Time Clock with a separate power domain
The RTC clock source includes Low-speed external crystal
oscillator (LXT) and 32kHz Low-speed Internal RC oscillator
(LIRC32) and 10kHz Low-speed Internal RC oscillator (LIRC)
The RTC block includes 80 bytes of battery-powered backup
registers, which can be cleared by tamper pins
Supports 6 static and dynamic tamper pins
Real-Time Clock (RTC)
Able to wake up CPU from any reduced power mode
Supports Alarm registers (second, minute, hour, day, month, year)
Supports RTC Time Tick and Alarm Match interrupt
Automatic leap year recognition
Supports 1 Hz clock output for calibration
Frequency of RTC clock source compensate by RTC_FREQADJ
register
Timers
TIMER
Four sets of 32-bit timers with 24-bit up counter and one 8-bit pre-
scale counter from independent clock source
32-bit Timer
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Supports event counting function to count the event from external
Feb 15, 2019
Page 15 of 245
Rev 1.01
M2351
pins
Supports external capture pin for interval measurement and
resetting 24-bit up counter
Supports chip wake-up function, if a timer interrupt signal is
generated
PWM
Eight 16-bit PWM counters with 12-bit clock prescale with up to 64
MHz
Supports 12-bit deadband (dead time)
Up, down or up-down PWM counter type
Supports brake function
Supports mask function and tri-state output for each PWM channel
Twelve 16-bit counters with 12-bit clock prescale for twelve 64 MHz
PWM output channels
Up to 12 independent input capture channels with 16-bit resolution
counter
Supports dead time with maximum divided 12-bit prescale
Up, down or up-down PWM counter type
Supports complementary mode for 3 complementary paired PWM
Enhanced PWM (EPWM)
output channels
Synchronous function for phase control
Counter synchronous start function
Brake function with auto recovery mechanism
Mask function and tri-state output for each PWM channel
Able to trigger EADC or DAC to start conversion
Two 16-bit counters with 12-bit clock prescale for twelve 64 MHz
PWM output channels
Up to 6 independent input capture channels with 16-bit resolution
counter
Basic PWM (BPWM)
Up, down or up-down PWM counter type
Counter synchronous start function
Mask function and tri-state output for each PWM channel
Able to trigger EADC to start conversion
18-bit free running up counter for WDT time-out interval
Supports multiple clock sources from LIRC (default selection),
HCLK/2048 and LXT with 8 selectable time-out period
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Watchdog
Supports four WDT reset delay periods, including 1026, 130, 18 or 3
WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset
Clock sourced from HCLK/2048 or LIRC; the window set by 6-bit
Window Watchdog
down counter with 11-bit prescale
Feb 15, 2019
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Rev 1.01
M2351
Suspended in Idle/Power-down mode
Analog Interfaces
One 12-bit, 16-ch 3.76 MSPS SAR EADC with up to 16 single-
ended input channels or 8 differential input pairs; 10-bit accuracy is
guaranteed.
Three internal channels for VBAT, band-gap VBG input and
Temperature sensor input.
Supports external VREF pin or internal reference voltage VREF:
1.6V, 2.0V, 2.5V, and 3.0V.
Two power saving modes: Power-down mode and Standby mode.
Supports calibration capability.
Enhanced Analog-to-Digital
Converter (EADC)
Analog-to-Digital conversion can be triggered by software enable,
external pin, Timer 0~3 overflow pulse trigger or EPWM trigger.
Configurable EADC sampling time.
Up to 19 sample modules.
Double data buffers for sample module 0~3.
PDMA operation.
Two 12-bit, 1 MSPS voltage type DAC with 8-bit mode and 8μs rail-
to-rail settle time
Maximum output voltage AVDD -0.2V in buffer mode.
Digital-to-Analog Converter
(DAC)
Digital-to-Analog conversion triggered by Timer0~3, EPWM0,
EPWM1, external trigger pin to start DAC conversion or software.
Supports group mode for synchronized data update of two DACs.
PDMA operation.
Two rail-to-rail Analog Comparators.
Supports four multiplexed I/O pins at positive input.
Supports I/O pins, band-gap, DAC output, and 16-level Voltage
divider from AVDD or VREF at negative input.
Supports four programmable propagation speeds for power saving.
Supports wake up from Power-down by interrput.
Analog Comparator
(ACMP)
Supports triggers for brake events and cycle-by-cycle control for
PWM.
Supports window compare mode and window latch mode.
Supports programmable hysteresis window: 0mV, 10mV, 20mV and
30mV.
Communication Interfaces
Six sets of UARTs with up to 10.66 MHz baud rate
Auto-Baud Rate measurement and baud rate compensation
function
Low-power UART
Supports low power UART (LPUART): baud rate clock from
LXT(32.768 KHz) with 9600bps in Power-down mode even system
clock is stopped
16-byte FIFOs with programmable level trigger
Feb 15, 2019
Page 17 of 245
Rev 1.01
M2351
Auto flow control ( nCTS and nRTS)
Supports IrDA (SIR) function
Supports LIN function on UART0 and UART1
Supports RS-485 9-bit mode and direction control
Supports nCTS, incoming data, Received Data FIFO reached
threshold and RS-485 Address Match (AAD mode) wake-up
function in idle mode
Supports hardware or software enables to program nRTS pin to
control RS-485 transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and receive/transmit
FIFO overflow detection function
PDMA operation
Three sets of ISO-7816-3 which are compliant with ISO-7816-3 T=0,
T=1
Supports full duplex UART function
4-byte FIFOs with programmable level trigger
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8 bit time-out counters for Answer to Request
(ATR) and waiting times processing
Smart Card Interface
Auto inverse convention function
Stop clock level and clock stop (clock keep) function
Transmitter and receiver error retry function
Supports hardware activation, deactivation and warm reset
sequence process
Supports hardware auto deactivation sequence after card removal
Three sets of I2C devices with Master/Slave mode
Supports Standard mode (100 kbps), Fast mode (400 kbps) and
Fast mode plus (1 Mbps)
Supports 10 bits mode
Programmable clocks allowing for versatile rate control
I2C
Supports multiple address recognition (four slave address with
mask option)
Supports SM (Sytem Management) Bus and PM (Power
Management) Bus
Supports multi-address power-down wake-up function
PDMA operation
One set of SPI Quad controller with Master/Slave mode, up to 64
MHz at 2.7V~3.6V stsyem voltage.
Supports Dual and Quad I/O Transfer mode
Supports one/two data channel half-duplex transfer
Supports receive-only mode
Quad SPI
Feb 15, 2019
Page 18 of 245
Rev 1.01
M2351
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
MSB first or LSB first transfer sequence
The byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wired, no slave select signal, bi-direction interface
PDMA operation.
Up to four sets of SPI/I2S controllers with Master/Slave mode
SPI can communicate at up to 64 Mbit/s
SPI/I2S provides separate 4-level of 32-bit (or 8-level of 16-bit)
transmit and receive FIFO buffers
SPI
Configurable bit length of a transfer word from 8 to 32-bit
MSB first or LSB first transfer sequence
Byte reorder function
SPI/I2S
Supports Byte or Word Suspend mode
Supports one data channel half-duplex transfer
Supports receive-only mode
I2S
Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit
audio data sizes
Supports PCM mode A, PCM mode B, I2S and MSB justified data
format
PDMA operation
One set of I2S interface with Master/Slave mode
I2S audio sampling frequencies up to 192 kHz are supported
Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit
word sizes
Two 16-level FIFO data buffers, one for transmitting and the other
for receiving
I2S
Supports I2S protocols: Philips standard, MSB-justified, and LSB-
justified data format
Supports PCM protocols: PCM standard, MSB-justified, and LSB-
justified data format
PCM protocol supports TDM multi-channel transmission in one
audio sample; the number of data channel can be set as 2, 4, 6 or 8
PDMA operation
Two sets of USCI,configured as UART, SPI or I2C function
Supports single byte TX and RX buffer mode
UART
Universal Serial Control
Interface (USCI)
Supports one transmit buffer and two receive buffers for data
payload
Supports hardware auto flow control function and programmable
Feb 15, 2019
Page 19 of 245
Rev 1.01
M2351
flow control trigger level
9-bit Data Transfer
Baud rate detection by built-in capture event of baud rate generator
Supports wake-up function
PDMA operation
SPI
Supports Master or Slave mode operation
Supports one transmit buffer and two receive buffer for data payload
Configurable bit length of a transfer word from 4 to 16-bit
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in slave mode
Supports one data channel half-duplex transfer
PDMA operation
I2C
Supports master and slave device capability
Supports one transmit buffer and two receive buffer for data payload
Communication in standard mode (100 kbps), fast mode (up to 400
kbps), and Fast mode plus (1 Mbps)
Supports 10-bit mode
Supports 10-bit bus time out capability
Supports bus monitor mode
Supports power-down wake-up by data toggle or address match
Supports multiple address recognition
Supports device address flag
Programmable setup/hold time
Two sets of CAN 2.0B controllers
Each supports 32 Message Objects; each Message Object has its
own identifier mask
Controller Area Network
(CAN)
Programmable FIFO mode (concatenation of Message Object)
Disabled Automatic Re-transmission mode for Time Triggered CAN
applications
Supports power-down wake-up function
One set of Secure Digital Host Controller, compliant with SD
Memory Card Specification Version 2.0
Secure Digital Host
Controller (SDHC)
Supports 50 MHz to achieve 200 Mbps at 3.3V operation
Supports dedicated DMA master with Scatter-Gather function to
accelerate the data transfer between system memory and
SD/SDHC/SDIO card
External Bus Interface
(EBI)
Supports up to three memory banks with individual adjustment of
timing parameter
Feb 15, 2019
Page 20 of 245
Rev 1.01
M2351
Each bank supports dedicated external chip select pin with polarity
control and up to 1 MB addressing space
8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports variable external bus base clock (MCLK) which based on
HCLK
Configurable idle cycle for different access condition: Idle of Write
command finish (W2X) and Idle of Read-to-Read (R2R)
Supports Address/Data multiplexed mode
Supports address bus and data bus separate mode
Supports LCD interface i80 mode
PDMA operation
Supports four I/O modes: Quasi bi-direction, Push-Pull output,
Open-Drain output and Input only with high impendence mode
Selectable TTL/Schmitt trigger input
Configured as interrupt source with edge/level trigger setting
Supports independent pull-up/pull-down control
Supports high driver and high sink current I/O
Supports software selectable slew rate control
GPIO
Supports 5V-tolerance function except analog I/O. (Except PA.8 ~
15; PB.0 ~ 15; PD.10 ~ 12; PF.2 ~ 5; nReset.)
Improve access efficiency by using single cycle IO bus
Control Interfaces
Two QEI phase inputs (QEI_A, QEI_B) and one Index input
(QEI_INDEX)
Quadrature Encoder
Interface (QEI)
Supports 2/4 times free-counting mode and 2/4 compare-counting
mode
Supports encoder pulse width measurement mode with ECAP
Input Capture Timer/Counter
Supports three input channels with independent capture counter
hold register
24-bit Input Capture up-counting timer/counter supports captured
Enhanced Capture (ECAP)
events reset and/or reload capture counter
Supports rising edge, falling edge and both edge detector options
with noise filter in front of input ports
Supports compare-match function
Advanced Connectivity
USB 2.0 Full Speed OTG (On-The-Go)
On-chip USB 2.0 full speed OTG transceiver
Compliant with USB OTG Supplement 2.0
Configurable as host-only, device-only or ID-dependent
USB 2.0 Full Speed with
on-chip transceiver
Feb 15, 2019
Page 21 of 245
Rev 1.01
M2351
USB 1.1 Host Controller
Compliant with USB Revision 1.1 Specification
Compatible with OHCI (Open Host Controller Interface) Revision 1.0
Supports full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices
Supports Control, Bulk, Interrupt, Isochronous and Split transfers
Integrated a port routing logic to route full/low speed device to OHCI
controller
Supports an integrated Root Hub
Supports port power control and port over current detection
Built-in DMA
USB 2.0 Full Speed Device Controller
Compliant with USB Revision 2.0 Specification
Supports crystal-less
Supports suspend function when no bus activity existing for 3 ms
12 configurable endpoints for configurable Isochronous, Bulk,
Interrupt and Control transfer types
1024 bytes configurable RAM for endpoint buffer
Remote wake-up capability
Cryptography Accelerator
Hardware ECC accelerator
Supports both prime field GF(p) and binary field GF(2m)
Supports NIST P-192, P-224, P-256, P-384 and P-521 curve sizes
Supports NIST B-163, B-233, B-283, B-409 and B-571 curve sizes
Supports NIST K-163, K-233, K-283, K-409 and K-571 curve sizes
Elliptic Curve
Cryptography (ECC)
Supports point multiplication, addition and doubling operations in
GF(p) and GF(2m)
Supports modulus division, multiplication, addition and subtraction
operations in GF(p)
Hardware AES accelerator
Supports 128-bit, 192-bit and 256-bit key length and key expander,
and is compliant with FIPS 197
Advanced Encryption
Standard (AES)
Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2 and
CBC-CS3 block cipher modes
Compliant with NIST SP800-38A and addendum
Hardware DES accelerator
Data Encryption Standard
(DES)
Supports ECB, CBC, CFB, OFB, and CTR block cipher mode
Compliant with FIPS 46-3
Hardware Triple DES accelerator
Triple Data Encryption
Standard (3DES)
Supports two or three different keys in each round
Supports ECB, CBC, CFB, OFB, and CTR block cipher mode
Feb 15, 2019
Page 22 of 245
Rev 1.01
M2351
Implemented based on X9.52 standard and compliant with FIPS SP
800-67
Hardware SHA accelerator
Secure Hash Algorithm
(SHA)
Supports SHA-160, SHA-224, SHA-256 and SHA-384
Compliant with FIPS 180/180-2
Pseudo Random Number
Generator (PRNG)
Supports 64-bit, 128-bit, 192-bit and 256-bit random number
generation
True Randon Number
Generator (TRNG)
Up to 800 random bits per second
Feb 15, 2019
Page 23 of 245
Rev 1.01
M2351
3 PARTS INFORMATION
3.1 Summary
Part No.
USB FS
CAN
Crypto
M2351
√
√
√
3.2 Package Type
Part No.
QFN33
WLCSP49
LQFP64
M2351SIAAE
LQFP128
M2351
M2351ZIAAE
M2351CIAAE
M2351KIAAE
Feb 15, 2019
Page 24 of 245
Rev 1.01
M2351
3.3 NuMicro® M2351 Series Selection Guide
M2351
PART NUMBER
ZIAAE
CIAAE
SIAAE
KIAAE
Flash (KB)
SRAM (KB)
ISP Loader ROM (KB)
I/O
512
96
512
96
512
96
512
96
4
4
25
-
41
-
51
1
107
6
32-bit Timer
Tamper
RTC
√
6
3
LPUART
ISO-7816
Quad SPI
1
SPI/I2S
3
3
4
4
I2S
I2C
1
3
2
1
2
USCI (UART/I2C/ SPI)
CAN
LIN
SDHC
1
1
1
1
TRNG
√
√
DES / 3-DES / AES
ECC
√
SHA
√
16-bit Enhanced PWM
16-bit Basic PWM
QEI
12
12
1
-
2
1
2
1
2
2
ECAP
USB 2.0 FS OTG
12-bit ADC
12-bit DAC
Analog Comparator
Cryptography
External Bus Interface
Package
√
2
10
2
12
2
16
2
16
2
√
-
√
√
√
QFN 33
WLCSP 49
LQFP 64
LQFP 128
Feb 15, 2019
Page 25 of 245
Rev 1.01
M2351
3.4 NuMicro® M2351 Naming Rule
ARM–Based
32-bit Microcontroller
X X X X
51 X
M23
CPU Core
M23: Cortex® -M23
Product Line Function
51: Performance line
Temperature
E: -40°C ~ +105°C
Reserve
Package Type
SRAM size
A: 96KB
Z: QFN33 (5x5 mm)
C: WLCSP49 (3x3 mm)
S: LQFP64 (7x7 mm)
K: LQFP128 (14x14 mm)
Flash ROM
I: 512KB
Feb 15, 2019
Page 26 of 245
Rev 1.01
M2351
4 PIN CONFIGURATION
4.1
NuMicro® M2351 Series QFN33 Pin Diagram
Corresponding Part Number: M2351ZIAAE
25
16
15
14
13
12
11
10
9
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PF.2
Top transparent view
26
Vsw
27
VDD
28
LDO_CAP
QFN33
29
PB.14
30
PB.13
31
PB.12
33 VSS
32
AVDD
PF.3
VDDIO power domain
Figure 4.1-1 NuMicro® M2351 Series QFN 33-pin Diagram
Feb 15, 2019
Page 27 of 245
Rev 1.01
M2351
4.2
NuMicro® M2351 Series WLCSP49 Pin Diagram
Corresponding Part Number: M2351CIAAE
A
B
C
D
E
F
G
Figure 4.2-1 NuMicro® M2351 Series WLCSP 49-pin Diagram
Feb 15, 2019
Page 28 of 245
Rev 1.01
M2351
4.3
NuMicro® M2351 Series LQFP64 Pin Diagram
Corresponding Part Number: M2351SIAAE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
PA.0
50
VSW
51
VDD
52
LDO_CAP
PA.1
53
PB.15
PA.2
54
PB.14
PA.3
55
PB.13
PA.4
56
PB.12
PA.5
LQFP64
57
AVDD
LDO_CAP
VDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
VDDIO power domain
VBAT power domain
Figure 4.3-1 NuMicro® M2351 Series LQFP 64-pin Diagram
Feb 15, 2019
Page 29 of 245
Rev 1.01
M2351
4.4
NuMicro® M2351 Series LQFP128 Pin Diagram
Corresponding Part Number: M2351KIAAE
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PE.7
nRESET
PE.15
PE.14
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
LDO_CAP
VDD
98
PE.6
99
PE.5
100
PE.4
101
PE.3
102
PE.2
103
VSS
104
VDD
105
PE.1
106
PE.0
107
PH.8
108
PH.9
109
PH.10
VSS
110
PH.11
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
VDD
111
PD.14
112
VSS
LQFP128
113
VSW
114
VDD
115
LDO_CAP
116
PB.15
117
PB.14
118
PB.13
119
PB.12
120
AVDD
121
VREF
122
AVSS
VSS
123
PB.11
PF.2
124
PB.10
PF.3
125
PB.9
PH.7
PH.6
PH.5
PH.4
126
PB.8
127
PB.7
128
PB.6
VDDIO power domain
VBAT power domain
Figure 4.4-1 NuMicro® M2351 Series LQFP 128-pin Diagram
Feb 15, 2019
Page 30 of 245
Rev 1.01
M2351
4.5
M2351 Performance Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
1
2
3
D3
C2
B1
2
3
4
1
2
3
PB.5
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 5 analog input.
MFP1 Analog comparator 1 negative input pin.
MFP2 EBI address bus bit 0.
EADC0_CH5
ACMP1_N
EBI_ADR0
SD0_DAT3
SPI1_MISO
I2C0_SCL
UART5_TXD
USCI1_CTL0
SC0_CLK
I2S0_BCLK
EPWM0_CH0
TM0
A
O
I/O
I/O
I/O
O
MFP3 SD/SDIO0 data line bit 3.
MFP5 SPI1 MISO (Master In, Slave Out) pin.
MFP6 I2C0 clock pin.
MFP7 UART5 data transmitter output pin.
MFP8 USCI1 control 0 pin.
I/O
O
MFP9 Smart Card 0 clock pin.
O
MFP10 I2S0 bit clock output pin.
I/O
I/O
I
MFP11 EPWM0 channel 0 output/capture input.
MFP14 Timer0 event counter input/toggle output pin.
MFP15 External interrupt 0 input pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 4 analog input.
MFP1 Analog comparator 1 positive input 1 pin.
MFP2 EBI address bus bit 1.
INT0
PB.4
I/O
A
EADC0_CH4
ACMP1_P1
EBI_ADR1
SD0_DAT2
SPI1_MOSI
I2C0_SDA
UART5_RXD
USCI1_CTL1
SC0_DAT
I2S0_MCLK
EPWM0_CH1
TM1
A
O
I/O
I/O
I/O
I
MFP3 SD/SDIO0 data line bit 2.
MFP5 SPI1 MOSI (Master Out, Slave In) pin.
MFP6 I2C0 data input/output pin.
MFP7 UART5 data receiver input pin.
MFP8 USCI1 control 1 pin.
I/O
I/O
O
MFP9 Smart Card 0 data pin.
MFP10 I2S0 master clock output pin.
MFP11 EPWM0 channel 1 output/capture input.
MFP14 Timer1 event counter input/toggle output pin.
MFP15 External interrupt 1 input pin.
MFP0 General purpose digital I/O pin.
I/O
I/O
I
INT1
PB.3
I/O
Feb 15, 2019
Page 31 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
EADC0_CH3
ACMP0_N
EBI_ADR2
SD0_DAT1
SPI1_CLK
UART1_TXD
UART5_nRTS
USCI1_DAT1
SC0_RST
I2S0_DI
A
A
MFP1 EADC0 channel 3 analog input.
MFP1 Analog comparator 0 negative input pin.
MFP2 EBI address bus bit 2.
O
I/O
I/O
O
MFP3 SD/SDIO0 data line bit 1.
MFP5 SPI1 serial clock pin.
MFP6 UART1 data transmitter output pin.
MFP7 UART5 request to Send output pin.
MFP8 USCI1 data 1 pin.
O
I/O
O
MFP9 Smart Card 0 reset pin.
I
MFP10 I2S0 data input pin.
EPWM0_CH2
TM2
I/O
I/O
I
MFP11 EPWM0 channel 2 output/capture input.
MFP14 Timer2 event counter input/toggle output pin.
MFP15 External interrupt 2 input pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 2 analog input.
MFP1 Analog comparator 0 positive input 1 pin.
MFP2 EBI address bus bit 3.
INT2
4
E3
5
4
PB.2
I/O
A
EADC0_CH2
ACMP0_P1
EBI_ADR3
SD0_DAT0
SPI1_SS
A
O
I/O
I/O
I
MFP3 SD/SDIO0 data line bit 0.
MFP5 SPI1 slave select pin.
UART1_RXD
UART5_nCTS
USCI1_DAT0
SC0_PWR
I2S0_DO
MFP6 UART1 data receiver input pin.
MFP7 UART5 clear to Send input pin.
MFP8 USCI1 data 0 pin.
I
I/O
O
MFP9 Smart Card 0 power pin.
O
MFP10 I2S0 data output pin.
EPWM0_CH3
TM3
I/O
I/O
I
MFP11 EPWM0 channel 3 output/capture input.
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 3 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 4.
INT3
5
PC.12
I/O
O
EBI_ADR4
UART0_TXD
I2C0_SCL
SPI3_MISO
SC0_nCD
ECAP1_IC2
O
MFP3 UART0 data transmitter output pin.
MFP4 I2C0 clock pin.
I/O
I/O
I
MFP6 SPI3 MISO (Master In, Slave Out) pin.
MFP9 Smart Card 0 card detect pin.
MFP11 Enhanced capture unit 1 input 2 pin.
I
Feb 15, 2019
Page 32 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
EPWM1_CH0
I/O
O
MFP12 EPWM1 channel 0 output/capture input.
MFP14 Analog comparator 0 output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 5.
ACMP0_O
PC.11
6
I/O
O
EBI_ADR5
UART0_RXD
I2C0_SDA
SPI3_MOSI
ECAP1_IC1
EPWM1_CH1
ACMP1_O
PC.10
I
MFP3 UART0 data receiver input pin.
MFP4 I2C0 data input/output pin.
I/O
I/O
I
MFP6 SPI3 MOSI (Master Out, Slave In) pin.
MFP11 Enhanced capture unit 1 input 1 pin.
MFP12 EPWM1 channel 1 output/capture input.
MFP14 Analog comparator 1 output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 6.
I/O
O
7
I/O
O
EBI_ADR6
SPI3_CLK
I/O
O
MFP6 SPI3 serial clock pin.
UART3_TXD
ECAP1_IC0
EPWM1_CH2
PC.9
MFP7 UART3 data transmitter output pin.
MFP11 Enhanced capture unit 1 input 0 pin.
MFP12 EPWM1 channel 2 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 7.
I
I/O
I/O
O
8
EBI_ADR7
SPI3_SS
I/O
I
MFP6 SPI3 slave select pin.
UART3_RXD
EPWM1_CH3
PB.1
MFP7 UART3 data receiver input pin.
MFP12 EPWM1 channel 3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 1 analog input.
MFP2 EBI address bus bit 8.
I/O
I/O
A
5
D2
6
9
EADC0_CH1
EBI_ADR8
SD0_CLK
O
O
MFP3 SD/SDIO0 clock output pin
SPI1_I2SMCLK
SPI3_I2SMCLK
UART2_TXD
USCI1_CLK
I2C1_SCL
I/O
I/O
O
MFP5 SPI1 I2S master clock output pin
MFP6 SPI3 I2S master clock output pin
MFP7 UART2 data transmitter output pin.
MFP8 USCI1 clock pin.
I/O
I/O
O
MFP9 I2C1 clock pin.
I2S0_LRCK
EPWM0_CH4
EPWM1_CH4
EPWM0_BRAKE0
MFP10 I2S0 left right channel clock output pin.
MFP11 EPWM0 channel 4 output/capture input.
MFP12 EPWM1 channel 4 output/capture input.
MFP13 EPWM0 Brake 0 input pin.
I/O
I/O
I
Feb 15, 2019
Page 33 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
6
C1
7
10 PB.0
EADC0_CH0
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 0 analog input.
MFP2 EBI address bus bit 9.
EBI_ADR9
O
SD0_CMD
I/O
I
MFP3 SD/SDIO0 command/response pin
MFP7 UART2 data receiver input pin.
MFP8 SPI0 I2S master clock output pin
MFP9 I2C1 data input/output pin.
UART2_RXD
SPI0_I2SMCLK
I2C1_SDA
I/O
I/O
I/O
I/O
I
EPWM0_CH5
EPWM1_CH5
EPWM0_BRAKE1
MFP11 EPWM0 channel 5 output/capture input.
MFP12 EPWM1 channel 5 output/capture input.
MFP13 EPWM0 Brake 1 input pin.
11 VSS
P
MFP0 Ground pin for digital circuit.
12 VDD
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
D1
8
13 PA.11
I/O
A
MFP0 General purpose digital I/O pin.
MFP1 Analog comparator 0 positive input 0 pin.
MFP2 EBI read enable output pin.
MFP3 Smart Card 2 power pin.
ACMP0_P0
EBI_nRD
O
SC2_PWR
O
SPI2_SS
I/O
I/O
I/O
I/O
O
MFP4 SPI2 slave select pin.
USCI0_CLK
I2C2_SCL
MFP6 USCI0 clock pin.
MFP7 I2C2 clock pin.
BPWM0_CH0
EPWM0_SYNC_OUT
TM0_EXT
MFP9 BPWM0 channel 0 output/capture input.
MFP10 EPWM0 counter synchronous trigger output pin.
MFP13 Timer0 external capture input/toggle output pin.
MFP14 DAC1 external trigger input.
MFP0 General purpose digital I/O pin.
MFP1 Analog comparator 1 positive input 0 pin.
MFP2 EBI write enable output pin.
MFP3 Smart Card 2 reset pin.
I/O
I
DAC1_ST
E2
9
14 PA.10
I/O
A
ACMP1_P0
EBI_nWR
O
SC2_RST
O
SPI2_CLK
I/O
I/O
I/O
I/O
I
MFP4 SPI2 serial clock pin.
USCI0_DAT0
I2C2_SDA
MFP6 USCI0 data 0 pin.
MFP7 I2C2 data input/output pin.
BPWM0_CH1
QEI1_INDEX
ECAP0_IC0
MFP9 BPWM0 channel 1 output/capture input.
MFP10 Quadrature encoder 1 index input
MFP11 Enhanced capture unit 0 input 0 pin.
I
Feb 15, 2019
Page 34 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
TM1_EXT
DAC0_ST
I/O
I
MFP13 Timer1 external capture input/toggle output pin.
MFP14 DAC0 external trigger input.
MFP0 General purpose digital I/O pin.
MFP2 EBI external clock output pin.
MFP3 Smart Card 2 data pin.
E1 10 15 PA.9
EBI_MCLK
SC2_DAT
I/O
O
I/O
I/O
I/O
O
SPI2_MISO
USCI0_DAT1
UART1_TXD
BPWM0_CH2
QEI1_A
MFP4 SPI2 MISO (Master In, Slave Out) pin.
MFP6 USCI0 data 1 pin.
MFP7 UART1 data transmitter output pin.
MFP9 BPWM0 channel 2 output/capture input.
MFP10 Quadrature encoder 1 phase A input
MFP11 Enhanced capture unit 0 input 1 pin.
MFP13 Timer2 external capture input/toggle output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address latch enable output pin.
MFP3 Smart Card 2 clock pin.
I/O
I
ECAP0_IC1
TM2_EXT
I
I/O
I/O
O
F2 11 16 PA.8
EBI_ALE
SC2_CLK
O
SPI2_MOSI
USCI0_CTL1
UART1_RXD
BPWM0_CH3
QEI1_B
I/O
I/O
I
MFP4 SPI2 MOSI (Master Out, Slave In) pin.
MFP6 USCI0 control 1 pin.
MFP7 UART1 data receiver input pin.
MFP9 BPWM0 channel 3 output/capture input.
MFP10 Quadrature encoder 1 phase B input
MFP11 Enhanced capture unit 0 input 2 pin.
MFP13 Timer3 external capture input/toggle output pin.
MFP15 External interrupt 4 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 10.
I/O
I
ECAP0_IC2
TM3_EXT
I
I/O
I
INT4
17 PC.13
I/O
O
EBI_ADR10
SC2_nCD
I
MFP3 Smart Card 2 card detect pin.
MFP4 SPI2 I2S master clock output pin
MFP6 USCI0 control 0 pin.
SPI2_I2SMCLK
USCI0_CTL0
UART2_TXD
BPWM0_CH4
CLKO
I/O
I/O
O
MFP7 UART2 data transmitter output pin.
MFP9 BPWM0 channel 4 output/capture input.
MFP13 Clock Out
I/O
O
EADC0_ST
18 PD.12
I
MFP14 EADC0 external trigger input.
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 0 output pin.
I/O
O
EBI_nCS0
Feb 15, 2019
Page 35 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
UART2_RXD
BPWM0_CH5
QEI0_INDEX
CLKO
I
I/O
I
MFP7 UART2 data receiver input pin.
MFP9 BPWM0 channel 5 output/capture input.
MFP10 Quadrature encoder 0 index input
MFP13 Clock Out
O
EADC0_ST
INT5
I
MFP14 EADC0 external trigger input.
MFP15 External interrupt 5 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 1 output pin.
MFP3 UART1 data transmitter output pin.
MFP4 CAN0 bus transmitter output.
MFP10 Quadrature encoder 0 phase A input
MFP15 External interrupt 6 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 2 output pin.
MFP3 UART1 data receiver input pin.
MFP4 CAN0 bus receiver input.
I
19 PD.11
EBI_nCS1
UART1_TXD
CAN0_TXD
QEI0_A
I/O
O
O
O
I
INT6
I
20 PD.10
EBI_nCS2
UART1_RXD
CAN0_RXD
QEI0_B
I/O
O
I
I
I
MFP10 Quadrature encoder 0 phase B input
MFP15 External interrupt 7 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 11.
INT7
I
21 PG.2
EBI_ADR11
SPI2_SS
I/O
O
I/O
O
MFP3 SPI2 slave select pin.
I2C0_SMBAL
I2C1_SCL
TM0
MFP4 I2C0 SMBus SMBALTER pin
MFP5 I2C1 clock pin.
I/O
I/O
I/O
O
MFP13 Timer0 event counter input/toggle output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 12.
22 PG.3
EBI_ADR12
SPI2_CLK
I2C0_SMBSUS
I2C1_SDA
TM1
I/O
O
MFP3 SPI2 serial clock pin.
MFP4 I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP5 I2C1 data input/output pin.
I/O
I/O
I/O
O
MFP13 Timer1 event counter input/toggle output pin.
MFP0 General purpose digital I/O pin.
23 PG.4
EBI_ADR13
SPI2_MISO
TM2
MFP2 EBI address bus bit 13.
I/O
I/O
MFP3 SPI2 MISO (Master In, Slave Out) pin.
MFP13 Timer2 event counter input/toggle output pin.
Feb 15, 2019
Page 36 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
24 PF.11
EBI_ADR14
SPI2_MOSI
TAMPER5
TM3
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 14.
I/O
I/O
I/O
I/O
O
MFP3 SPI2 MOSI (Master Out, Slave In) pin.
MFP10 TAMPER detector loop pin 5.
MFP13 Timer3 event counter input/toggle output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 15.
25 PF.10
EBI_ADR15
SC0_nCD
I2S0_BCLK
SPI0_I2SMCLK
TAMPER4
26 PF.9
I
MFP3 Smart Card 0 card detect pin.
MFP4 I2S0 bit clock output pin.
O
I/O
I/O
I/O
O
MFP5 SPI0 I2S master clock output pin
MFP10 TAMPER detector loop pin 4.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 16.
EBI_ADR16
SC0_PWR
I2S0_MCLK
SPI0_SS
O
MFP3 Smart Card 0 power pin.
O
MFP4 I2S0 master clock output pin.
MFP5 SPI0 slave select pin.
I/O
I/O
I/O
O
TAMPER3
27 PF.8
MFP10 TAMPER detector loop pin 3.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 17.
EBI_ADR17
SC0_RST
I2S0_DI
O
MFP3 Smart Card 0 reset pin.
I
MFP4 I2S0 data input pin.
SPI0_CLK
TAMPER2
28 PF.7
I/O
I/O
I/O
O
MFP5 SPI0 serial clock pin.
MFP10 TAMPER detector loop pin 2.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 18.
EBI_ADR18
SC0_DAT
I2S0_DO
I/O
O
MFP3 Smart Card 0 data pin.
MFP4 I2S0 data output pin.
SPI0_MISO
UART4_TXD
TAMPER1
12 29 PF.6
EBI_ADR19
SC0_CLK
I2S0_LRCK
I/O
O
MFP5 SPI0 MISO (Master In, Slave Out) pin.
MFP6 UART4 data transmitter output pin.
MFP10 TAMPER detector loop pin 1.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 19.
I/O
I/O
O
O
MFP3 Smart Card 0 clock pin.
O
MFP4 I2S0 left right channel clock output pin.
Feb 15, 2019
Page 37 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
SPI0_MOSI
UART4_RXD
EBI_nCS0
I/O
I
MFP5 SPI0 MOSI (Master Out, Slave In) pin.
MFP6 UART4 data receiver input pin.
MFP7 EBI chip select 0 output pin.
O
TAMPER0
I/O
P
MFP10 TAMPER detector loop pin 0.
MFP0 Power supply by batteries for RTC.
MFP0 General purpose digital I/O pin.
MFP2 UART2 data receiver input pin.
MFP4 UART2 clear to Send input pin.
MFP8 BPWM0 channel 4 output/capture input.
13 30 VBAT
7
F1 14 31 PF.5
UART2_RXD
I/O
I
UART2_nCTS
BPWM0_CH4
EPWM0_SYNC_OUT
X32_IN
I
I/O
O
MFP9 EPWM0 counter synchronous trigger output pin.
MFP10 External 32.768 kHz crystal input pin.
MFP11 EADC0 external trigger input.
MFP0 General purpose digital I/O pin.
MFP2 UART2 data transmitter output pin.
MFP4 UART2 request to Send output pin.
MFP8 BPWM0 channel 5 output/capture input.
MFP10 External 32.768 kHz crystal output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 3.
I
EADC0_ST
I
8
G1 15 32 PF.4
I/O
O
UART2_TXD
UART2_nRTS
BPWM0_CH5
X32_OUT
O
I/O
O
33 PH.4
I/O
O
EBI_ADR3
SPI1_MISO
I/O
I/O
O
MFP3 SPI1 MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 2.
34 PH.5
EBI_ADR2
SPI1_MOSI
I/O
I/O
O
MFP3 SPI1 MOSI (Master Out, Slave In) pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 1.
35 PH.6
EBI_ADR1
SPI1_CLK
I/O
I/O
O
MFP3 SPI1 serial clock pin.
36 PH.7
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 0.
EBI_ADR0
SPI1_SS
I/O
I/O
O
MFP3 SPI1 slave select pin.
9
G2 16 37 PF.3
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 0 output pin.
MFP3 UART0 data transmitter output pin.
MFP4 I2C0 clock pin.
EBI_nCS0
UART0_TXD
I2C0_SCL
XT1_IN
O
I/O
I
MFP10 External 4~24 MHz (high speed) crystal input pin.
Feb 15, 2019
Page 38 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
BPWM1_CH0
10 G3 17 38 PF.2
EBI_nCS1
I/O
I/O
O
MFP11 BPWM1 channel 0 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 1 output pin.
MFP3 UART0 data receiver input pin.
MFP4 I2C0 data input/output pin.
UART0_RXD
I2C0_SDA
I
I/O
I/O
O
QSPI0_CLK
XT1_OUT
MFP5 Quad SPI0 serial clock pin.
MFP10 External 4~24 MHz (high speed) crystal output pin.
MFP11 BPWM1 channel 1 output/capture input.
MFP0 Ground pin for digital circuit.
BPWM1_CH1
I/O
P
39 VSS
40 VDD
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
41 PE.8
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 10.
EBI_ADR10
I2S0_BCLK
O
MFP4 I2S0 bit clock output pin.
SPI2_CLK
I/O
I/O
O
MFP5 SPI2 serial clock pin.
USCI1_CTL1
UART2_TXD
EPWM0_CH0
EPWM0_BRAKE0
ECAP0_IC0
MFP6 USCI1 control 1 pin.
MFP7 UART2 data transmitter output pin.
MFP10 EPWM0 channel 0 output/capture input.
MFP11 EPWM0 Brake 0 input pin.
MFP12 Enhanced capture unit 0 input 0 pin.
MFP14 ETM Trace Data 3 output pin
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 11.
I/O
I
I
TRACE_DATA3
O
42 PE.9
I/O
O
EBI_ADR11
I2S0_MCLK
O
MFP4 I2S0 master clock output pin.
MFP5 SPI2 MISO (Master In, Slave Out) pin.
MFP6 USCI1 control 0 pin.
SPI2_MISO
I/O
I/O
I
USCI1_CTL0
UART2_RXD
EPWM0_CH1
EPWM0_BRAKE1
ECAP0_IC1
MFP7 UART2 data receiver input pin.
MFP10 EPWM0 channel 1 output/capture input.
MFP11 EPWM0 Brake 1 input pin.
MFP12 Enhanced capture unit 0 input 1 pin.
MFP14 ETM Trace Data 2 output pin
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 12.
I/O
I
I
TRACE_DATA2
O
43 PE.10
I/O
O
EBI_ADR12
I2S0_DI
I
MFP4 I2S0 data input pin.
Feb 15, 2019
Page 39 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
SPI2_MOSI
USCI1_DAT0
UART3_TXD
EPWM0_CH2
EPWM1_BRAKE0
ECAP0_IC2
TRACE_DATA1
44 PE.11
I/O
I/O
O
MFP5 SPI2 MOSI (Master Out, Slave In) pin.
MFP6 USCI1 data 0 pin.
MFP7 UART3 data transmitter output pin.
MFP10 EPWM0 channel 2 output/capture input.
MFP11 EPWM1 Brake 0 input pin.
MFP12 Enhanced capture unit 0 input 2 pin.
MFP14 ETM Trace Data 1 output pin
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 13.
I/O
I
I
O
I/O
O
EBI_ADR13
I2S0_DO
O
MFP4 I2S0 data output pin.
SPI2_SS
I/O
I/O
I
MFP5 SPI2 slave select pin.
USCI1_DAT1
UART3_RXD
UART1_nCTS
EPWM0_CH3
EPWM1_BRAKE1
ECAP1_IC2
TRACE_DATA0
45 PE.12
MFP6 USCI1 data 1 pin.
MFP7 UART3 data receiver input pin.
MFP8 UART1 clear to Send input pin.
MFP10 EPWM0 channel 3 output/capture input.
MFP11 EPWM1 Brake 1 input pin.
MFP13 Enhanced capture unit 1 input 2 pin.
MFP14 ETM Trace Data 0 output pin
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 14.
I
I/O
I
I
O
I/O
O
EBI_ADR14
I2S0_LRCK
O
MFP4 I2S0 left right channel clock output pin.
MFP5 SPI2 I2S master clock output pin
MFP6 USCI1 clock pin.
SPI2_I2SMCLK
USCI1_CLK
UART1_nRTS
EPWM0_CH4
ECAP1_IC1
TRACE_CLK
46 PE.13
I/O
I/O
O
MFP8 UART1 request to Send output pin.
MFP10 EPWM0 channel 4 output/capture input.
MFP13 Enhanced capture unit 1 input 1 pin.
MFP14 ETM Trace Clock output pin
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 15.
I/O
I
O
I/O
O
EBI_ADR15
I2C0_SCL
I/O
O
MFP4 I2C0 clock pin.
UART4_nRTS
UART1_TXD
EPWM0_CH5
EPWM1_CH0
MFP5 UART4 request to Send output pin.
MFP8 UART1 data transmitter output pin.
MFP10 EPWM0 channel 5 output/capture input.
MFP11 EPWM1 channel 0 output/capture input.
O
I/O
I/O
Feb 15, 2019
Page 40 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
BPWM1_CH5
ECAP1_IC0
47 PC.8
I/O
I
MFP12 BPWM1 channel 5 output/capture input.
MFP13 Enhanced capture unit 1 input 0 pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address bus bit 16.
I/O
O
EBI_ADR16
I2C0_SDA
I/O
I
MFP4 I2C0 data input/output pin.
UART4_nCTS
UART1_RXD
EPWM1_CH1
BPWM1_CH4
MFP5 UART4 clear to Send input pin.
MFP8 UART1 data receiver input pin.
MFP11 EPWM1 channel 1 output/capture input.
MFP12 BPWM1 channel 4 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 9.
I
I/O
I/O
I/O
I/O
I/O
O
18 48 PC.7
EBI_AD9
SPI1_MISO
UART4_TXD
SC2_PWR
UART0_nCTS
I2C1_SMBAL
EPWM1_CH2
BPWM1_CH0
TM0
MFP4 SPI1 MISO (Master In, Slave Out) pin.
MFP5 UART4 data transmitter output pin.
MFP6 Smart Card 2 power pin.
O
I
MFP7 UART0 clear to Send input pin.
MFP8 I2C1 SMBus SMBALTER pin
O
I/O
I/O
I/O
I
MFP11 EPWM1 channel 2 output/capture input.
MFP12 BPWM1 channel 0 output/capture input.
MFP14 Timer0 event counter input/toggle output pin.
MFP15 External interrupt 3 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 8.
INT3
19 49 PC.6
I/O
I/O
I/O
I
EBI_AD8
SPI1_MOSI
UART4_RXD
SC2_RST
MFP4 SPI1 MOSI (Master Out, Slave In) pin.
MFP5 UART4 data receiver input pin.
MFP6 Smart Card 2 reset pin.
O
UART0_nRTS
I2C1_SMBSUS
EPWM1_CH3
BPWM1_CH1
TM1
O
MFP7 UART0 request to Send output pin.
O
MFP8 I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP11 EPWM1 channel 3 output/capture input.
MFP12 BPWM1 channel 1 output/capture input.
MFP14 Timer1 event counter input/toggle output pin.
MFP15 External interrupt 2 input pin.
I/O
I/O
I/O
I
INT2
F3 20 50 PA.7
I/O
I/O
I/O
MFP0 General purpose digital I/O pin.
EBI_AD7
MFP2 EBI address/data bus bit 7.
SPI1_CLK
MFP4 SPI1 serial clock pin.
Feb 15, 2019
Page 41 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
SC2_DAT
UART0_TXD
I2C1_SCL
I/O
O
MFP6 Smart Card 2 data pin.
MFP7 UART0 data transmitter output pin.
MFP8 I2C1 clock pin.
I/O
I/O
I/O
I
EPWM1_CH4
BPWM1_CH2
ACMP0_WLAT
TM2
MFP11 EPWM1 channel 4 output/capture input.
MFP12 BPWM1 channel 2 output/capture input.
MFP13 Analog comparator 0 window latch input pin
MFP14 Timer2 event counter input/toggle output pin.
MFP15 External interrupt 1 input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 6.
I/O
I
INT1
G4 21 51 PA.6
EBI_AD6
I/O
I/O
I/O
O
SPI1_SS
MFP4 SPI1 slave select pin.
SC2_CLK
MFP6 Smart Card 2 clock pin.
UART0_RXD
I2C1_SDA
I
MFP7 UART0 data receiver input pin.
MFP8 I2C1 data input/output pin.
I/O
I/O
I/O
I
EPWM1_CH5
BPWM1_CH3
ACMP1_WLAT
TM3
MFP11 EPWM1 channel 5 output/capture input.
MFP12 BPWM1 channel 3 output/capture input.
MFP13 Analog comparator 1 window latch input pin
MFP14 Timer3 event counter input/toggle output pin.
MFP15 External interrupt 0 input pin.
MFP0 Ground pin for digital circuit.
I/O
I
INT0
22 52 VSS
23 53 VDD
P
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
24 54 LDO_CAP
G5 25 55 PA.5
QSPI0_MISO1
SPI1_I2SMCLK
SC2_nCD
P
I/O
I/O
I/O
I
MFP0 LDO output pin.
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 MISO1 (Master In, Slave Out) pin.
MFP4 SPI1 I2S master clock output pin
MFP6 Smart Card 2 card detect pin.
MFP7 UART0 clear to Send input pin.
MFP8 UART5 data transmitter output pin.
MFP9 I2C0 clock pin.
UART0_nCTS
UART5_TXD
I
O
I2C0_SCL
I/O
O
CAN0_TXD
MFP10 CAN0 bus transmitter output.
MFP12 BPWM0 channel 5 output/capture input.
MFP13 EPWM0 channel 0 output/capture input.
MFP14 Quadrature encoder 0 index input
BPWM0_CH5
EPWM0_CH0
QEI0_INDEX
I/O
I/O
I
Feb 15, 2019
Page 42 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
F4 26 56 PA.4
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 MOSI1 (Master Out, Slave In) pin.
MFP4 SPI0 I2S master clock output pin
MFP6 Smart Card 0 card detect pin.
MFP7 UART0 request to Send output pin.
MFP8 UART5 data receiver input pin.
MFP9 I2C0 data input/output pin.
QSPI0_MOSI1
SPI0_I2SMCLK
SC0_nCD
UART0_nRTS
UART5_RXD
I2C0_SDA
O
I
I/O
I
CAN0_RXD
BPWM0_CH4
EPWM0_CH1
QEI0_A
MFP10 CAN0 bus receiver input.
I/O
I/O
I
MFP12 BPWM0 channel 4 output/capture input.
MFP13 EPWM0 channel 1 output/capture input.
MFP14 Quadrature encoder 0 phase A input
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 slave select pin.
11 E4 27 57 PA.3
I/O
I/O
I/O
O
QSPI0_SS
SPI0_SS
MFP4 SPI0 slave select pin.
SC0_PWR
UART4_TXD
UART1_TXD
I2C1_SCL
MFP6 Smart Card 0 power pin.
O
MFP7 UART4 data transmitter output pin.
MFP8 UART1 data transmitter output pin.
MFP9 I2C1 clock pin.
O
I/O
I/O
I/O
I
BPWM0_CH3
EPWM0_CH2
QEI0_B
MFP12 BPWM0 channel 3 output/capture input.
MFP13 EPWM0 channel 2 output/capture input.
MFP14 Quadrature encoder 0 phase B input
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 serial clock pin.
12 G6 28 58 PA.2
I/O
I/O
I/O
O
QSPI0_CLK
SPI0_CLK
MFP4 SPI0 serial clock pin.
SC0_RST
MFP6 Smart Card 0 reset pin.
UART4_RXD
UART1_RXD
I2C1_SDA
I
MFP7 UART4 data receiver input pin.
MFP8 UART1 data receiver input pin.
MFP9 I2C1 data input/output pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BPWM0_CH2
EPWM0_CH3
MFP12 BPWM0 channel 2 output/capture input.
MFP13 EPWM0 channel 3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 MISO0 (Master In, Slave Out) pin.
MFP4 SPI0 MISO (Master In, Slave Out) pin.
MFP6 Smart Card 0 data pin.
13 F5 29 59 PA.1
QSPI0_MISO0
SPI0_MISO
SC0_DAT
Feb 15, 2019
Page 43 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
UART0_TXD
UART1_nCTS
I2C2_SCL
O
I
MFP7 UART0 data transmitter output pin.
MFP8 UART1 clear to Send input pin.
MFP9 I2C2 clock pin.
I/O
I/O
I/O
I
BPWM0_CH1
EPWM0_CH4
DAC1_ST
MFP12 BPWM0 channel 1 output/capture input.
MFP13 EPWM0 channel 4 output/capture input.
MFP15 DAC1 external trigger input.
MFP0 General purpose digital I/O pin.
MFP3 Quad SPI0 MOSI0 (Master Out, Slave In) pin.
MFP4 SPI0 MOSI (Master Out, Slave In) pin.
MFP6 Smart Card 0 clock pin.
14 E5 30 60 PA.0
QSPI0_MOSI0
SPI0_MOSI
I/O
I/O
I/O
O
SC0_CLK
UART0_RXD
UART1_nRTS
I2C2_SDA
I
MFP7 UART0 data receiver input pin.
MFP8 UART1 request to Send output pin.
MFP9 I2C2 data input/output pin.
O
I/O
I/O
I/O
I
BPWM0_CH0
EPWM0_CH5
DAC0_ST
MFP12 BPWM0 channel 0 output/capture input.
MFP13 EPWM0 channel 5 output/capture input.
MFP15 DAC0 external trigger input.
MFP0 Power supply for PA.0~PA.5.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 8.
15 F6 31 61 VDDIO
62 PE.14
P
I/O
I/O
O
EBI_AD8
UART2_TXD
CAN0_TXD
MFP3 UART2 data transmitter output pin.
MFP4 CAN0 bus transmitter output.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 9.
O
63 PE.15
I/O
I/O
I
EBI_AD9
UART2_RXD
CAN0_RXD
MFP3 UART2 data receiver input pin.
MFP4 CAN0 bus receiver input.
I
16 G7 32 64 nRESET
I
MFP0 External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
17 D5 33 65 PF.0
UART1_TXD
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 UART1 data transmitter output pin.
MFP3 I2C1 clock pin.
I2C1_SCL
I/O
I/O
O
BPWM1_CH0
MFP12 BPWM1 channel 0 output/capture input.
MFP14 Serial wired debugger data pin.
MFP0 General purpose digital I/O pin.
MFP2 UART1 data receiver input pin.
ICE_DAT
18 E6 34 66 PF.1
UART1_RXD
I/O
I
Feb 15, 2019
Page 44 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I2C1_SDA
BPWM1_CH1
ICE_CLK
I/O
I/O
I
MFP3 I2C1 data input/output pin.
MFP12 BPWM1 channel 1 output/capture input.
MFP14 Serial wired debugger clock pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 7.
MFP3 I2C2 clock pin.
67 PD.9
I/O
I/O
I/O
I
EBI_AD7
I2C2_SCL
UART2_nCTS
68 PD.8
MFP4 UART2 clear to Send input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 6.
MFP3 I2C2 data input/output pin.
I/O
I/O
I/O
O
EBI_AD6
I2C2_SDA
UART2_nRTS
D6 35 69 PC.5
EBI_AD5
MFP4 UART2 request to Send output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 5.
MFP4 Quad SPI0 MISO1 (Master In, Slave Out) pin.
MFP8 UART2 data transmitter output pin.
MFP9 I2C1 clock pin.
I/O
I/O
I/O
O
QSPI0_MISO1
UART2_TXD
I2C1_SCL
I/O
O
CAN0_TXD
UART4_TXD
EPWM1_CH0
C6 36 70 PC.4
EBI_AD4
MFP10 CAN0 bus transmitter output.
MFP11 UART4 data transmitter output pin.
MFP12 EPWM1 channel 0 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 4.
MFP4 Quad SPI0 MOSI1 (Master Out, Slave In) pin.
MFP5 Smart Card 1 card detect pin.
MFP6 I2S0 bit clock output pin.
O
I/O
I/O
I/O
I/O
I
QSPI0_MOSI1
SC1_nCD
I2S0_BCLK
SPI1_I2SMCLK
UART2_RXD
I2C1_SDA
O
I/O
I
MFP7 SPI1 I2S master clock output pin
MFP8 UART2 data receiver input pin.
MFP9 I2C1 data input/output pin.
I/O
I
CAN0_RXD
UART4_RXD
EPWM1_CH1
F7 37 71 PC.3
EBI_AD3
MFP10 CAN0 bus receiver input.
I
MFP11 UART4 data receiver input pin.
MFP12 EPWM1 channel 1 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 3.
MFP4 Quad SPI0 slave select pin.
MFP5 Smart Card 1 power pin.
I/O
I/O
I/O
I/O
O
QSPI0_SS
SC1_PWR
Feb 15, 2019
Page 45 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I2S0_MCLK
SPI1_MISO
O
I/O
O
MFP6 I2S0 master clock output pin.
MFP7 SPI1 MISO (Master In, Slave Out) pin.
MFP8 UART2 request to Send output pin.
MFP9 I2C0 SMBus SMBALTER pin
MFP11 UART3 data transmitter output pin.
MFP12 EPWM1 channel 2 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 2.
UART2_nRTS
I2C0_SMBAL
UART3_TXD
EPWM1_CH2
E7 38 72 PC.2
EBI_AD2
O
O
I/O
I/O
I/O
I/O
O
QSPI0_CLK
SC1_RST
MFP4 Quad SPI0 serial clock pin.
MFP5 Smart Card 1 reset pin.
I2S0_DI
I
MFP6 I2S0 data input pin.
SPI1_MOSI
I/O
I
MFP7 SPI1 MOSI (Master Out, Slave In) pin.
MFP8 UART2 clear to Send input pin.
UART2_nCTS
I2C0_SMBSUS
UART3_RXD
EPWM1_CH3
19 D7 39 73 PC.1
EBI_AD1
O
MFP9 I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP11 UART3 data receiver input pin.
MFP12 EPWM1 channel 3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 1.
I
I/O
I/O
I/O
I/O
I/O
O
QSPI0_MISO0
SC1_DAT
MFP4 Quad SPI0 MISO0 (Master In, Slave Out) pin.
MFP5 Smart Card 1 data pin.
I2S0_DO
MFP6 I2S0 data output pin.
SPI1_CLK
I/O
O
MFP7 SPI1 serial clock pin.
UART2_TXD
I2C0_SCL
MFP8 UART2 data transmitter output pin.
MFP9 I2C0 clock pin.
I/O
I/O
O
EPWM1_CH4
ACMP0_O
MFP12 EPWM1 channel 4 output/capture input.
MFP14 Analog comparator 0 output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 0.
20 C7 40 74 PC.0
EBI_AD0
I/O
I/O
I/O
O
QSPI0_MOSI0
SC1_CLK
MFP4 Quad SPI0 MOSI0 (Master Out, Slave In) pin.
MFP5 Smart Card 1 clock pin.
I2S0_LRCK
O
MFP6 I2S0 left right channel clock output pin.
MFP7 SPI1 slave select pin.
SPI1_SS
I/O
I
UART2_RXD
I2C0_SDA
MFP8 UART2 data receiver input pin.
MFP9 I2C0 data input/output pin.
I/O
Feb 15, 2019
Page 46 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
EPWM1_CH5
ACMP1_O
75 VSS
I/O
O
MFP12 EPWM1 channel 5 output/capture input.
MFP14 Analog comparator 1 output pin.
MFP0 Ground pin for digital circuit.
P
76 VDD
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
77 PG.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 0.
MFP12 BPWM0 channel 5 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 1.
MFP12 BPWM0 channel 4 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 2.
MFP12 BPWM0 channel 3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 3.
MFP12 BPWM0 channel 2 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 4.
MFP12 BPWM0 channel 1 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 5.
MFP12 BPWM0 channel 0 output/capture input.
MFP0 General purpose digital I/O pin.
MFP14 Clock Out
EBI_AD0
BPWM0_CH5
78 PG.10
EBI_AD1
BPWM0_CH4
79 PG.11
EBI_AD2
BPWM0_CH3
80 PG.12
EBI_AD3
BPWM0_CH2
81 PG.13
EBI_AD4
BPWM0_CH1
82 PG.14
EBI_AD5
BPWM0_CH0
83 PG.15
CLKO
EADC0_ST
I
MFP15 EADC0 external trigger input.
MFP0 General purpose digital I/O pin.
MFP3 UART1 data transmitter output pin.
MFP4 I2C0 clock pin.
84 PD.7
I/O
O
UART1_TXD
I2C0_SCL
I/O
I/O
I/O
O
SPI1_MISO
USCI1_CLK
SC1_PWR
MFP5 SPI1 MISO (Master In, Slave Out) pin.
MFP6 USCI1 clock pin.
MFP8 Smart Card 1 power pin.
85 PD.6
UART1_RXD
I/O
I
MFP0 General purpose digital I/O pin.
MFP3 UART1 data receiver input pin.
Feb 15, 2019
Page 47 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I2C0_SDA
SPI1_MOSI
USCI1_DAT1
SC1_RST
I/O
I/O
I/O
O
MFP4 I2C0 data input/output pin.
MFP5 SPI1 MOSI (Master Out, Slave In) pin.
MFP6 USCI1 data 1 pin.
MFP8 Smart Card 1 reset pin.
MFP0 General purpose digital I/O pin.
MFP4 I2C1 clock pin.
86 PD.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I2C1_SCL
SPI1_CLK
MFP5 SPI1 serial clock pin.
USCI1_DAT0
SC1_DAT
MFP6 USCI1 data 0 pin.
MFP8 Smart Card 1 data pin.
87 PD.4
MFP0 General purpose digital I/O pin.
MFP3 USCI0 control 0 pin.
USCI0_CTL0
I2C1_SDA
MFP4 I2C1 data input/output pin.
MFP5 SPI1 slave select pin.
SPI1_SS
USCI1_CTL1
SC1_CLK
MFP6 USCI1 control 1 pin.
MFP8 Smart Card 1 clock pin.
MFP14 USB external VBUS regulator status pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 10.
MFP3 USCI0 control 1 pin.
USB_VBUS_ST
41 88 PD.3
EBI_AD10
I
I/O
I/O
I/O
I/O
O
USCI0_CTL1
SPI0_SS
MFP4 SPI0 slave select pin.
UART3_nRTS
USCI1_CTL0
SC2_PWR
MFP5 UART3 request to Send output pin.
MFP6 USCI1 control 0 pin.
I/O
O
MFP7 Smart Card 2 power pin.
MFP8 Smart Card 1 card detect pin.
MFP9 UART0 data transmitter output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 11.
MFP3 USCI0 data 1 pin.
SC1_nCD
I
UART0_TXD
42 89 PD.2
EBI_AD11
O
I/O
I/O
I/O
I/O
I
USCI0_DAT1
SPI0_CLK
MFP4 SPI0 serial clock pin.
UART3_nCTS
SC2_RST
MFP5 UART3 clear to Send input pin.
MFP7 Smart Card 2 reset pin.
MFP9 UART0 data receiver input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 12.
O
UART0_RXD
43 90 PD.1
EBI_AD12
I
I/O
I/O
Feb 15, 2019
Page 48 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
USCI0_DAT0
SPI0_MISO
UART3_TXD
I2C2_SCL
I/O
I/O
O
MFP3 USCI0 data 0 pin.
MFP4 SPI0 MISO (Master In, Slave Out) pin.
MFP5 UART3 data transmitter output pin.
MFP6 I2C2 clock pin.
I/O
I/O
I/O
I/O
I/O
I/O
I
SC2_DAT
MFP7 Smart Card 2 data pin.
44 91 PD.0
EBI_AD13
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 13.
MFP3 USCI0 clock pin.
USCI0_CLK
SPI0_MOSI
UART3_RXD
I2C2_SDA
MFP4 SPI0 MOSI (Master Out, Slave In) pin.
MFP5 UART3 data receiver input pin.
MFP6 I2C2 data input/output pin.
MFP7 Smart Card 2 clock pin.
I/O
O
SC2_CLK
TM2
I/O
I/O
I/O
I
MFP14 Timer2 event counter input/toggle output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 10.
MFP3 SD/SDIO0 card detect input pin
MFP4 SPI0 I2S master clock output pin
MFP5 SPI1 I2S master clock output pin
MFP7 Smart Card 2 card detect pin.
MFP0 General purpose digital I/O pin.
MFP2 I2S0 bit clock output pin.
92 PD.13
EBI_AD10
SD0_nCD
SPI0_I2SMCLK
SPI1_I2SMCLK
SC2_nCD
I/O
I/O
I
21 B6 45 93 PA.12
I2S0_BCLK
I/O
O
UART4_TXD
I2C1_SCL
O
MFP3 UART4 data transmitter output pin.
MFP4 I2C1 clock pin.
I/O
I/O
O
SPI2_SS
MFP5 SPI2 slave select pin.
CAN0_TXD
MFP6 CAN0 bus transmitter output.
MFP7 Smart Card 2 power pin.
SC2_PWR
O
BPWM1_CH2
QEI1_INDEX
USB_VBUS
22 B7 46 94 PA.13
I2S0_MCLK
UART4_RXD
I2C1_SDA
I/O
I
MFP11 BPWM1 channel 2 output/capture input.
MFP12 Quadrature encoder 1 index input
MFP14 Power supply from USB host or HUB.
MFP0 General purpose digital I/O pin.
MFP2 I2S0 master clock output pin.
MFP3 UART4 data receiver input pin.
MFP4 I2C1 data input/output pin.
MFP5 SPI2 serial clock pin.
P
I/O
O
I
I/O
I/O
SPI2_CLK
Feb 15, 2019
Page 49 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
CAN0_RXD
SC2_RST
I
MFP6 CAN0 bus receiver input.
O
MFP7 Smart Card 2 reset pin.
BPWM1_CH3
QEI1_A
I/O
I
MFP11 BPWM1 channel 3 output/capture input.
MFP12 Quadrature encoder 1 phase A input
MFP14 USB differential signal D-.
USB_D-
A
23 A6 47 95 PA.14
I2S0_DI
I/O
I
MFP0 General purpose digital I/O pin.
MFP2 I2S0 data input pin.
UART0_TXD
SPI2_MISO
O
MFP3 UART0 data transmitter output pin.
MFP5 SPI2 MISO (Master In, Slave Out) pin.
MFP6 I2C2 clock pin.
I/O
I/O
I/O
I/O
I
I2C2_SCL
SC2_DAT
MFP7 Smart Card 2 data pin.
BPWM1_CH4
QEI1_B
MFP11 BPWM1 channel 4 output/capture input.
MFP12 Quadrature encoder 1 phase B input
MFP14 USB differential signal D+.
USB_D+
A
24 A7 48 96 PA.15
I2S0_DO
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 I2S0 data output pin.
UART0_RXD
SPI2_MOSI
I
MFP3 UART0 data receiver input pin.
MFP5 SPI2 MOSI (Master Out, Slave In) pin.
MFP6 I2C2 data input/output pin.
I/O
I/O
O
I2C2_SDA
SC2_CLK
MFP7 Smart Card 2 clock pin.
BPWM1_CH5
I/O
I
MFP11 BPWM1 channel 5 output/capture input.
MFP12 EPWM0 counter synchronous trigger input pin.
MFP14 USB_ identification.
EPWM0_SYNC_IN
USB_OTG_ID
97 PE.7
I
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP3 SD/SDIO0 command/response pin
MFP8 UART5 data transmitter output pin.
MFP11 Quadrature encoder 1 index input
MFP12 EPWM0 channel 0 output/capture input.
MFP13 BPWM0 channel 5 output/capture input.
MFP0 General purpose digital I/O pin.
MFP3 SD/SDIO0 clock output pin
SD0_CMD
UART5_TXD
QEI1_INDEX
EPWM0_CH0
BPWM0_CH5
I
I/O
I/O
I/O
O
98 PE.6
SD0_CLK
SPI3_I2SMCLK
SC0_nCD
I/O
I
MFP5 SPI3 I2S master clock output pin
MFP6 Smart Card 0 card detect pin.
MFP7 USCI0 control 0 pin.
USCI0_CTL0
I/O
Feb 15, 2019
Page 50 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
UART5_RXD
QEI1_A
I
MFP8 UART5 data receiver input pin.
MFP11 Quadrature encoder 1 phase A input
MFP12 EPWM0 channel 1 output/capture input.
MFP13 BPWM0 channel 4 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI read enable output pin.
MFP3 SD/SDIO0 data line bit 3.
I
EPWM0_CH1
BPWM0_CH4
99 PE.5
I/O
I/O
I/O
O
EBI_nRD
SD0_DAT3
SPI3_SS
I/O
I/O
O
MFP5 SPI3 slave select pin.
SC0_PWR
USCI0_CTL1
QEI1_B
MFP6 Smart Card 0 power pin.
I/O
I
MFP7 USCI0 control 1 pin.
MFP11 Quadrature encoder 1 phase B input
MFP12 EPWM0 channel 2 output/capture input.
MFP13 BPWM0 channel 3 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI write enable output pin.
MFP3 SD/SDIO0 data line bit 2.
EPWM0_CH2
BPWM0_CH3
100 PE.4
I/O
I/O
I/O
O
EBI_nWR
SD0_DAT2
SPI3_CLK
I/O
I/O
O
MFP5 SPI3 serial clock pin.
SC0_RST
MFP6 Smart Card 0 reset pin.
USCI0_DAT1
QEI0_INDEX
EPWM0_CH3
BPWM0_CH2
101 PE.3
I/O
I
MFP7 USCI0 data 1 pin.
MFP11 Quadrature encoder 0 index input
MFP12 EPWM0 channel 3 output/capture input.
MFP13 BPWM0 channel 2 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI external clock output pin.
MFP3 SD/SDIO0 data line bit 1.
I/O
I/O
I/O
O
EBI_MCLK
SD0_DAT1
SPI3_MISO
SC0_DAT
I/O
I/O
I/O
I/O
I
MFP5 SPI3 MISO (Master In, Slave Out) pin.
MFP6 Smart Card 0 data pin.
USCI0_DAT0
QEI0_A
MFP7 USCI0 data 0 pin.
MFP11 Quadrature encoder 0 phase A input
MFP12 EPWM0 channel 4 output/capture input.
MFP13 BPWM0 channel 1 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI address latch enable output pin.
MFP3 SD/SDIO0 data line bit 0.
EPWM0_CH4
BPWM0_CH1
102 PE.2
I/O
I/O
I/O
O
EBI_ALE
SD0_DAT0
I/O
Feb 15, 2019
Page 51 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
SPI3_MOSI
SC0_CLK
I/O
O
MFP5 SPI3 MOSI (Master Out, Slave In) pin.
MFP6 Smart Card 0 clock pin.
USCI0_CLK
QEI0_B
I/O
I
MFP7 USCI0 clock pin.
MFP11 Quadrature encoder 0 phase B input
MFP12 EPWM0 channel 5 output/capture input.
MFP13 BPWM0 channel 0 output/capture input.
MFP0 Ground pin for digital circuit.
EPWM0_CH5
BPWM0_CH0
103 VSS
I/O
I/O
P
104 VDD
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
105 PE.1
I/O
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 10.
MFP3 Quad SPI0 MISO0 (Master In, Slave Out) pin.
MFP4 Smart Card 2 data pin.
EBI_AD10
QSPI0_MISO0
SC2_DAT
I2S0_BCLK
SPI1_MISO
UART3_TXD
I2C1_SCL
MFP5 I2S0 bit clock output pin.
I/O
O
MFP6 SPI1 MISO (Master In, Slave Out) pin.
MFP7 UART3 data transmitter output pin.
MFP8 I2C1 clock pin.
I/O
I
UART4_nCTS
106 PE.0
MFP9 UART4 clear to Send input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 11.
MFP3 Quad SPI0 MOSI0 (Master Out, Slave In) pin.
MFP4 Smart Card 2 clock pin.
I/O
I/O
I/O
O
EBI_AD11
QSPI0_MOSI0
SC2_CLK
I2S0_MCLK
SPI1_MOSI
UART3_RXD
I2C1_SDA
UART4_nRTS
107 PH.8
O
MFP5 I2S0 master clock output pin.
MFP6 SPI1 MOSI (Master Out, Slave In) pin.
MFP7 UART3 data receiver input pin.
MFP8 I2C1 data input/output pin.
MFP9 UART4 request to Send output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 12.
MFP3 Quad SPI0 serial clock pin.
MFP4 Smart Card 2 power pin.
I/O
I
I/O
O
I/O
I/O
I/O
O
EBI_AD12
QSPI0_CLK
SC2_PWR
I2S0_DI
I
MFP5 I2S0 data input pin.
SPI1_CLK
I/O
O
MFP6 SPI1 serial clock pin.
UART3_nRTS
MFP7 UART3 request to Send output pin.
Feb 15, 2019
Page 52 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I2C1_SMBAL
I2C2_SCL
O
I/O
O
MFP8 I2C1 SMBus SMBALTER pin
MFP9 I2C2 clock pin.
UART1_TXD
108 PH.9
MFP10 UART1 data transmitter output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 13.
MFP3 Quad SPI0 slave select pin.
MFP4 Smart Card 2 reset pin.
MFP5 I2S0 data output pin.
I/O
I/O
I/O
O
EBI_AD13
QSPI0_SS
SC2_RST
I2S0_DO
O
SPI1_SS
I/O
I
MFP6 SPI1 slave select pin.
UART3_nCTS
I2C1_SMBSUS
I2C2_SDA
MFP7 UART3 clear to Send input pin.
O
MFP8 I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP9 I2C2 data input/output pin.
I/O
I
UART1_RXD
109 PH.10
MFP10 UART1 data receiver input pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 14.
I/O
I/O
I/O
I
EBI_AD14
QSPI0_MISO1
SC2_nCD
MFP3 Quad SPI0 MISO1 (Master In, Slave Out) pin.
MFP4 Smart Card 2 card detect pin.
I2S0_LRCK
SPI1_I2SMCLK
UART4_TXD
UART0_TXD
110 PH.11
O
MFP5 I2S0 left right channel clock output pin.
MFP6 SPI1 I2S master clock output pin
MFP7 UART4 data transmitter output pin.
MFP8 UART0 data transmitter output pin.
MFP0 General purpose digital I/O pin.
MFP2 EBI address/data bus bit 15.
I/O
O
O
I/O
I/O
I/O
I
EBI_AD15
QSPI0_MOSI1
UART4_RXD
UART0_RXD
EPWM0_CH5
111 PD.14
MFP3 Quad SPI0 MOSI1 (Master Out, Slave In) pin.
MFP7 UART4 data receiver input pin.
MFP8 UART0 data receiver input pin.
MFP11 EPWM0 channel 5 output/capture input.
MFP0 General purpose digital I/O pin.
MFP2 EBI chip select 0 output pin.
I
I/O
I/O
O
EBI_nCS0
SPI3_I2SMCLK
SC1_nCD
I/O
I
MFP3 SPI3 I2S master clock output pin
MFP4 Smart Card 1 card detect pin.
USCI0_CTL0
SPI0_I2SMCLK
EPWM0_CH4
I/O
I/O
I/O
MFP5 USCI0 control 0 pin.
MFP6 SPI0 I2S master clock output pin
MFP11 EPWM0 channel 4 output/capture input.
Feb 15, 2019
Page 53 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
25 D4 49 112 VSS
26 A5 50 113 Vsw
27 A4 51 114 VDD
P
MFP0 Ground pin for digital circuit.
MFP0
P
MFP0 Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
28 B5 52 115 LDO_CAP
A3 53 116 PB.15
A
I/O
A
MFP0 LDO output pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 15 analog input.
MFP2 EBI address/data bus bit 12.
MFP3 Smart Card 1 power pin.
EADC0_CH15
EBI_AD12
I/O
O
SC1_PWR
SPI0_SS
I/O
I/O
I
MFP4 SPI0 slave select pin.
USCI0_CTL1
UART0_nCTS
UART3_TXD
I2C2_SMBAL
EPWM1_CH0
TM0_EXT
MFP5 USCI0 control 1 pin.
MFP6 UART0 clear to Send input pin.
MFP7 UART3 data transmitter output pin.
MFP8 I2C2 SMBus SMBALTER pin
MFP11 EPWM1 channel 0 output/capture input.
MFP13 Timer0 external capture input/toggle output pin.
MFP14 USB external VBUS regulator enable pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 14 analog input.
MFP2 EBI address/data bus bit 13.
MFP3 Smart Card 1 reset pin.
O
O
I/O
I/O
O
USB_VBUS_EN
29 C5 54 117 PB.14
I/O
A
EADC0_CH14
EBI_AD13
I/O
O
SC1_RST
SPI0_CLK
I/O
I/O
O
MFP4 SPI0 serial clock pin.
USCI0_DAT1
UART0_nRTS
UART3_RXD
I2C2_SMBSUS
EPWM1_CH1
TM1_EXT
MFP5 USCI0 data 1 pin.
MFP6 UART0 request to Send output pin.
MFP7 UART3 data receiver input pin.
MFP8 I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP11 EPWM1 channel 1 output/capture input.
MFP13 Timer1 external capture input/toggle output pin.
MFP14 Clock Out
I
O
I/O
I/O
O
CLKO
USB_VBUS_ST
I
MFP15 USB external VBUS regulator status pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 13 analog input.
MFP1 DAC1 channel analog output.
MFP1 Analog comparator 0 positive input 3 pin.
30 B4 55 118 PB.13
I/O
A
EADC0_CH13
DAC1_OUT
ACMP0_P3
A
A
Feb 15, 2019
Page 54 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
ACMP1_P3
EBI_AD14
A
I/O
I/O
I/O
I/O
O
MFP1 Analog comparator 1 positive input 3 pin.
MFP2 EBI address/data bus bit 14.
SC1_DAT
MFP3 Smart Card 1 data pin.
SPI0_MISO
MFP4 SPI0 MISO (Master In, Slave Out) pin.
MFP5 USCI0 data 0 pin.
USCI0_DAT0
UART0_TXD
UART3_nRTS
I2C2_SCL
MFP6 UART0 data transmitter output pin.
MFP7 UART3 request to Send output pin.
MFP8 I2C2 clock pin.
O
I/O
I/O
I/O
I/O
A
EPWM1_CH2
TM2_EXT
MFP11 EPWM1 channel 2 output/capture input.
MFP13 Timer2 external capture input/toggle output pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 12 analog input.
MFP1 DAC0 channel analog output.
MFP1 Analog comparator 0 positive input 2 pin.
MFP1 Analog comparator 1 positive input 2 pin.
MFP2 EBI address/data bus bit 15.
31 C4 56 119 PB.12
EADC0_CH12
DAC0_OUT
A
ACMP0_P2
A
ACMP1_P2
A
EBI_AD15
I/O
O
SC1_CLK
MFP3 Smart Card 1 clock pin.
SPI0_MOSI
I/O
I/O
I
MFP4 SPI0 MOSI (Master Out, Slave In) pin.
MFP5 USCI0 clock pin.
USCI0_CLK
UART0_RXD
UART3_nCTS
I2C2_SDA
MFP6 UART0 data receiver input pin.
MFP7 UART3 clear to Send input pin.
MFP8 I2C2 data input/output pin.
I
I/O
I
SD0_nCD
MFP9 SD/SDIO0 card detect input pin
MFP11 EPWM1 channel 3 output/capture input.
MFP13 Timer3 external capture input/toggle output pin.
MFP0 Power supply for internal analog circuit.
MFP0 ADC reference voltage input.
EPWM1_CH3
TM3_EXT
I/O
I/O
P
32 A2 57 120 AVDD
58 121 VREF
A
Note: This pin needs to be connected with a 1uF
capacitor.
B3 59 122 AVSS
60 123 PB.11
EADC0_CH11
EBI_ADR16
P
I/O
A
MFP0 Ground pin for analog circuit.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 11 analog input.
MFP2 EBI address bus bit 16.
O
I
UART0_nCTS
UART4_TXD
MFP5 UART0 clear to Send input pin.
MFP6 UART4 data transmitter output pin.
O
Feb 15, 2019
Page 55 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
I2C1_SCL
I/O
O
MFP7 I2C1 clock pin.
CAN0_TXD
MFP8 CAN0 bus transmitter output.
MFP9 SPI0 I2S master clock output pin
MFP10 BPWM1 channel 0 output/capture input.
MFP11 SPI3 serial clock pin.
SPI0_I2SMCLK
I/O
I/O
I/O
I/O
A
BPWM1_CH0
SPI3_CLK
61 124 PB.10
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 10 analog input.
MFP2 EBI address bus bit 17.
EADC0_CH10
EBI_ADR17
USCI1_CTL0
UART0_nRTS
UART4_RXD
I2C1_SDA
O
I/O
O
MFP4 USCI1 control 0 pin.
MFP5 UART0 request to Send output pin.
MFP6 UART4 data receiver input pin.
MFP7 I2C1 data input/output pin.
MFP8 CAN0 bus receiver input.
I
I/O
I
CAN0_RXD
BPWM1_CH1
SPI3_SS
I/O
I/O
I/O
A
MFP10 BPWM1 channel 1 output/capture input.
MFP11 SPI3 slave select pin.
62 125 PB.9
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 9 analog input.
MFP2 EBI address bus bit 18.
EADC0_CH9
EBI_ADR18
USCI1_CTL1
UART0_TXD
UART1_nCTS
I2C1_SMBAL
BPWM1_CH2
SPI3_MISO
INT7
O
I/O
O
MFP4 USCI1 control 1 pin.
MFP5 UART0 data transmitter output pin.
MFP6 UART1 clear to Send input pin.
MFP7 I2C1 SMBus SMBALTER pin
MFP10 BPWM1 channel 2 output/capture input.
MFP11 SPI3 MISO (Master In, Slave Out) pin.
MFP13 External interrupt 7 input pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 8 analog input.
MFP2 EBI address bus bit 19.
I
O
I/O
I/O
I
C3 63 126 PB.8
I/O
A
EADC0_CH8
EBI_ADR19
USCI1_CLK
UART0_RXD
UART1_nRTS
I2C1_SMBSUS
BPWM1_CH3
SPI3_MOSI
O
I/O
I
MFP4 USCI1 clock pin.
MFP5 UART0 data receiver input pin.
MFP6 UART1 request to Send output pin.
O
O
MFP7 I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
MFP10 BPWM1 channel 3 output/capture input.
MFP11 SPI3 MOSI (Master Out, Slave In) pin.
I/O
I/O
Feb 15, 2019
Page 56 of 245
Rev 1.01
M2351
33 49 64 128 Pin Name
Pin Pin Pin Pin
Type
MFP
Description
INT6
A1 64 127 PB.7
EADC0_CH7
EBI_nWRL
I
I/O
A
MFP13 External interrupt 6 input pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 7 analog input.
MFP2 EBI low byte write enable output pin.
MFP4 USCI1 data 0 pin.
O
I/O
O
O
I/O
I
USCI1_DAT0
UART1_TXD
EBI_nCS0
MFP6 UART1 data transmitter output pin.
MFP8 EBI chip select 0 output pin.
BPWM1_CH4
EPWM1_BRAKE0
EPWM1_CH4
INT5
MFP10 BPWM1 channel 4 output/capture input.
MFP11 EPWM1 Brake 0 input pin.
I/O
I
MFP12 EPWM1 channel 4 output/capture input.
MFP13 External interrupt 5 input pin.
MFP14 USB external VBUS regulator status pin.
MFP15 Analog comparator 0 output pin.
MFP0 General purpose digital I/O pin.
MFP1 EADC0 channel 6 analog input.
MFP2 EBI high byte write enable output pin
MFP4 USCI1 data 1 pin.
USB_VBUS_ST
ACMP0_O
I
O
I/O
A
B2
1
128 PB.6
EADC0_CH6
EBI_nWRH
O
I/O
I
USCI1_DAT1
UART1_RXD
EBI_nCS1
MFP6 UART1 data receiver input pin.
MFP8 EBI chip select 1 output pin.
O
I/O
I
BPWM1_CH5
EPWM1_BRAKE1
EPWM1_CH5
INT4
MFP10 BPWM1 channel 5 output/capture input.
MFP11 EPWM1 Brake 1 input pin.
I/O
I
MFP12 EPWM1 channel 5 output/capture input.
MFP13 External interrupt 4 input pin.
MFP14 USB external VBUS regulator enable pin.
MFP15 Analog comparator 1 output pin.
USB_VBUS_EN
ACMP1_O
O
O
M2351 Multi-function Summary Table
Group
Pin Name
GPIO
PB.3
MFP
MFP1
MFP14
MFP14
MFP15
MFP1
MFP1
Type
A
Description
ACMP0_N
Analog comparator 0 negative input pin.
PC.12
PC.1
PB.7
O
ACMP0_O
O
Analog comparator 0 output pin.
ACMP0
O
ACMP0_P0
ACMP0_P1
PA.11
PB.2
A
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
A
Feb 15, 2019
Page 57 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PB.12
PB.13
PA.7
MFP
Type
A
Description
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
MFP1
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
MFP1
A
MFP13
MFP1
I
PB.5
A
PB.6
MFP15
MFP14
MFP14
MFP1
O
ACMP1_O
PC.11
PC.0
PA.10
PB.4
O
Analog comparator 1 output pin.
O
ACMP1
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
A
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
MFP1
A
PB.12
PB.13
PA.6
MFP1
A
MFP1
A
MFP13
MFP9
I
PA.11
PA.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MFP12
MFP12
MFP13
MFP9
BPWM0_CH0
BPWM0_CH1
BPWM0_CH2
BPWM0_CH3
BPWM0 channel 0 output/capture input.
BPWM0 channel 1 output/capture input.
BPWM0 channel 2 output/capture input.
BPWM0 channel 3 output/capture input.
PG.14
PE.2
PA.10
PA.1
MFP12
MFP12
MFP13
MFP9
PG.13
PE.3
PA.9
PA.2
MFP12
MFP12
MFP13
MFP9
PG.12
PE.4
BPWM0
PA.8
PA.3
MFP12
MFP12
MFP13
MFP9
PG.11
PE.5
PC.13
PF.5
MFP8
BPWM0_CH4
BPWM0_CH5
PA.4
MFP12
MFP12
MFP13
MFP9
BPWM0 channel 4 output/capture input.
BPWM0 channel 5 output/capture input.
PG.10
PE.6
PD.12
Feb 15, 2019
Page 58 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PF.4
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
MFP8
PA.5
MFP12
MFP12
MFP13
MFP11
MFP12
MFP12
MFP10
MFP11
MFP12
MFP12
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP10
MFP12
MFP11
MFP4
PG.9
PE.7
PF.3
PC.7
PF.0
BPWM1_CH0
BPWM1_CH1
BPWM1 channel 0 output/capture input.
BPWM1 channel 1 output/capture input.
PB.11
PF.2
PC.6
PF.1
PB.10
PA.7
BPWM1_CH2
BPWM1_CH3
BPWM1_CH4
BPWM1_CH5
PA.12
PB.9
BPWM1 channel 2 output/capture input.
BPWM1 channel 3 output/capture input.
BPWM1 channel 4 output/capture input.
BPWM1 channel 5 output/capture input.
BPWM1
PA.6
PA.13
PB.8
PC.8
PA.14
PB.7
PB.6
PE.13
PA.15
PD.10
PA.4
MFP10
MFP4
I
PE.15
PC.4
PA.13
PB.10
PD.11
PA.5
I
CAN0_RXD
CAN0 bus receiver input.
MFP10
MFP6
I
I
CAN0
MFP8
I
MFP4
O
MFP10
MFP4
O
CAN0_TXD
CAN0 bus transmitter output.
PE.14
PC.5
O
MFP10
O
Feb 15, 2019
Page 59 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PA.12
PB.11
PC.13
PD.12
PG.15
PB.14
PB.12
PA.10
PA.0
MFP
Type
Description
MFP6
O
O
O
O
O
O
A
I
MFP8
MFP13
MFP13
MFP14
MFP14
MFP1
CLKO
CLKO
Clock Out
DAC0_OUT
DAC0_ST
DAC0 channel analog output.
DAC0 external trigger input.
DAC1 channel analog output.
DAC0
DAC1
MFP14
MFP15
MFP1
I
DAC1_OUT
PB.13
PA.11
PA.1
A
I
MFP14
MFP15
DAC1_ST
DAC1 external trigger input.
I
EADC0_CH0
EADC0_CH1
EADC0_CH2
EADC0_CH3
EADC0_CH4
EADC0_CH5
EADC0_CH6
EADC0_CH7
EADC0_CH8
EADC0_CH9
EADC0_CH10
EADC0_CH11
EADC0_CH12
EADC0_CH13
EADC0_CH14
EADC0_CH15
PB.0
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP14
MFP14
MFP11
MFP15
MFP2
MFP2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I
EADC0 channel 0 analog input.
EADC0 channel 1 analog input.
EADC0 channel 2 analog input.
EADC0 channel 3 analog input.
EADC0 channel 4 analog input.
EADC0 channel 5 analog input.
EADC0 channel 6 analog input.
EADC0 channel 7 analog input.
EADC0 channel 8 analog input.
EADC0 channel 9 analog input.
EADC0 channel 10 analog input.
EADC0 channel 11 analog input.
EADC0 channel 12 analog input.
EADC0 channel 13 analog input.
EADC0 channel 14 analog input.
EADC0 channel 15 analog input.
PB.1
PB.2
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
EADC0
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
PC.13
PD.12
PF.5
I
EADC0_ST
EBI_AD0
EADC0 external trigger input.
EBI address/data bus bit 0.
I
PG.15
PC.0
PG.9
I
I/O
I/O
EBI
Feb 15, 2019
Page 60 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PC.1
PG.10
PC.2
PG.11
PC.3
PG.12
PC.4
PG.13
PC.5
PG.14
PA.6
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
EBI_AD1
EBI address/data bus bit 1.
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
EBI address/data bus bit 2.
EBI address/data bus bit 3.
EBI address/data bus bit 4.
EBI address/data bus bit 5.
EBI address/data bus bit 6.
EBI address/data bus bit 7.
EBI address/data bus bit 8.
EBI address/data bus bit 9.
PD.8
PA.7
PD.9
PC.6
PE.14
PC.7
PE.15
PD.3
PD.13
PE.1
EBI_AD10
EBI_AD11
EBI_AD12
EBI address/data bus bit 10.
EBI address/data bus bit 11.
EBI address/data bus bit 12.
PD.2
PE.0
PD.1
PH.8
PB.15
PD.0
PH.9
PB.14
PH.10
PB.13
PH.11
PB.12
PB.5
EBI_AD13
EBI_AD14
EBI address/data bus bit 13.
EBI address/data bus bit 14.
EBI_AD15
EBI_ADR0
EBI address/data bus bit 15.
EBI address bus bit 0.
Feb 15, 2019
Page 61 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PH.7
PB.4
MFP
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
EBI_ADR1
EBI_ADR2
EBI_ADR3
EBI address bus bit 1.
EBI address bus bit 2.
EBI address bus bit 3.
PH.6
PB.3
PH.5
PB.2
PH.4
PC.12
PC.11
PC.10
PC.9
PB.1
EBI_ADR4
EBI_ADR5
EBI_ADR6
EBI_ADR7
EBI_ADR8
EBI_ADR9
EBI address bus bit 4.
EBI address bus bit 5.
EBI address bus bit 6.
EBI address bus bit 7.
EBI address bus bit 8.
EBI address bus bit 9.
PB.0
PC.13
PE.8
EBI_ADR10
EBI_ADR11
EBI_ADR12
EBI_ADR13
EBI_ADR14
EBI_ADR15
EBI address bus bit 10.
EBI address bus bit 11.
EBI address bus bit 12.
EBI address bus bit 13.
EBI address bus bit 14.
EBI address bus bit 15.
PG.2
PE.9
PG.3
PE.10
PG.4
PE.11
PF.11
PE.12
PF.10
PE.13
PF.9
EBI_ADR16
PC.8
PB.11
PF.8
EBI address bus bit 16.
EBI_ADR17
EBI_ADR18
EBI_ADR19
EBI address bus bit 17.
EBI address bus bit 18.
EBI address bus bit 19.
PB.10
PF.7
PB.9
PF.6
PB.8
Feb 15, 2019
Page 62 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PA.8
MFP
MFP2
MFP2
MFP2
MFP2
MFP2
MFP7
MFP2
MFP2
MFP8
MFP8
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP13
MFP11
MFP13
MFP11
MFP13
MFP6
MFP4
MFP4
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Description
EBI_ALE
EBI address latch enable output pin.
PE.2
PA.9
EBI_MCLK
EBI_nCS0
EBI external clock output pin.
EBI chip select 0 output pin.
PE.3
PD.12
PF.6
PF.3
PD.14
PB.7
PB.6
EBI_nCS1
PD.11
PF.2
EBI chip select 1 output pin.
EBI_nCS2
EBI_nRD
PD.10
PA.11
PE.5
EBI chip select 2 output pin.
EBI read enable output pin.
PA.10
PE.4
EBI_nWR
EBI write enable output pin.
EBI_nWRH
EBI_nWRL
PB.6
EBI high byte write enable output pin
EBI low byte write enable output pin.
PB.7
PA.10
PE.8
ECAP0_IC0
ECAP0_IC1
ECAP0_IC2
ECAP1_IC0
ECAP1_IC1
ECAP1_IC2
Enhanced capture unit 0 input 0 pin.
Enhanced capture unit 0 input 1 pin.
Enhanced capture unit 0 input 2 pin.
Enhanced capture unit 1 input 0 pin.
Enhanced capture unit 1 input 1 pin.
Enhanced capture unit 1 input 2 pin.
I
PA.9
I
ECAP0
PE.9
I
PA.8
I
PE.10
PC.10
PE.13
PC.11
PE.12
PC.12
PE.11
PB.5
I
I
I
I
ECAP1
I
I
I
I/O
I/O
I/O
I2C0
I2C0_SCL
PC.12
PF.3
I2C0 clock pin.
Feb 15, 2019
Page 63 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PE.13
PA.5
PC.1
PD.7
PB.4
PC.11
PF.2
PC.8
PA.4
PC.0
PD.6
PG.2
PC.3
PG.3
PC.2
PB.1
PG.2
PA.7
PA.3
PF.0
PC.5
PD.5
PA.12
PE.1
PB.11
PB.0
PG.3
PA.6
PA.2
PF.1
PC.4
PD.4
PA.13
PE.0
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
MFP4
MFP9
MFP9
MFP4
MFP6
MFP4
MFP4
MFP4
MFP9
MFP9
MFP4
MFP4
MFP9
MFP4
MFP9
MFP9
MFP5
MFP8
MFP9
MFP3
MFP9
MFP4
MFP4
MFP8
MFP7
MFP9
MFP5
MFP8
MFP9
MFP3
MFP9
MFP4
MFP4
MFP8
I2C0_SDA
I2C0 data input/output pin.
I2C0_SMBAL
I2C0 SMBus SMBALTER pin
O
O
I2C0 SMBus SMBSUS pin (PMBus CONTROL
pin)
I2C0_SMBSUS
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I2C1_SCL
I2C1 clock pin.
I2C1
I2C1_SDA
I2C1 data input/output pin.
Feb 15, 2019
Page 64 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PB.10
PC.7
PH.8
PB.9
MFP
Type
I/O
O
Description
MFP7
MFP8
MFP8
MFP7
MFP8
MFP8
MFP7
MFP7
MFP9
MFP3
MFP6
MFP6
MFP9
MFP8
MFP7
MFP9
MFP3
MFP6
MFP6
MFP9
MFP8
MFP8
I2C1_SMBAL
I2C1_SMBSUS
O
I2C1 SMBus SMBALTER pin
O
PC.6
PH.9
PB.8
O
I2C1 SMBus SMBSUS pin (PMBus CONTROL
pin)
O
O
PA.11
PA.1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PD.9
PD.1
PA.14
PH.8
PB.13
PA.10
PA.0
I2C2_SCL
I2C2 clock pin.
I2C2
PD.8
PD.0
PA.15
PH.9
PB.12
PB.15
I2C2_SDA
I2C2 data input/output pin.
I2C2_SMBAL
I2C2 SMBus SMBALTER pin
I2C2 SMBus SMBSUS pin (PMBus CONTROL
pin)
I2C2_SMBSUS
PB.14
MFP8
O
PB.5
PF.10
PE.8
PC.4
PA.12
PE.1
PB.3
PF.8
MFP10
MFP4
MFP4
MFP6
MFP2
MFP5
MFP10
MFP4
MFP4
MFP6
MFP2
O
O
O
O
O
O
I
I2S0_BCLK
I2S0 bit clock output pin.
I2S0
I
I2S0_DI
PE.10
PC.2
PA.14
I
I2S0 data input pin.
I
I
Feb 15, 2019
Page 65 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PH.8
PB.2
PF.7
PE.11
PC.1
PA.15
PH.9
PB.1
PF.6
PE.12
PC.0
PH.10
PB.4
PF.9
PE.9
PC.3
PA.13
PE.0
PF.1
PF.0
PB.5
PA.6
PB.4
PA.7
PB.3
PC.6
PB.2
PC.7
PB.6
PA.8
PD.12
PB.7
PD.11
PB.8
MFP
Type
I
Description
MFP5
MFP10
MFP4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
MFP4
I2S0_DO
I2S0 data output pin.
MFP6
MFP2
MFP5
MFP10
MFP4
I2S0_LRCK
MFP4
I2S0 left right channel clock output pin.
MFP6
MFP5
MFP10
MFP4
MFP4
I2S0_MCLK
I2S0 master clock output pin.
MFP6
MFP2
MFP5
ICE_CLK
ICE_DAT
MFP14
MFP14
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP15
MFP13
MFP15
MFP15
MFP13
MFP15
MFP13
Serial wired debugger clock pin.
Serial wired debugger data pin.
ICE
O
I
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT0
INT1
INT2
INT3
INT4
INT5
INT6
External interrupt 0 input pin.
External interrupt 1 input pin.
External interrupt 2 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
External interrupt 6 input pin.
I
I
I
I
I
I
I
I
I
I
I
I
I
Feb 15, 2019
Page 66 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.10
PB.9
PB.1
PE.8
PB.0
PE.9
PB.5
PE.8
PA.5
PE.7
PB.4
PE.9
PA.4
PE.6
PB.3
PE.10
PA.3
PE.5
PB.2
PE.11
PA.2
PE.4
PB.1
PE.12
PA.1
PE.3
PD.14
PB.0
PE.13
PA.0
PE.2
PH.11
PA.15
MFP
Type
I
Description
MFP15
MFP13
MFP13
MFP11
MFP13
MFP11
MFP11
MFP10
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP10
MFP13
MFP12
MFP11
MFP11
MFP10
MFP13
MFP12
MFP11
MFP12
MFP10
INT7
INT7
External interrupt 7 input pin.
I
I
EPWM0_BRAKE0
EPWM0_BRAKE1
EPWM0 Brake 0 input pin.
EPWM0 Brake 1 input pin.
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
EPWM0_CH0
EPWM0_CH1
EPWM0_CH2
EPWM0_CH3
EPWM0 channel 0 output/capture input.
EPWM0 channel 1 output/capture input.
EPWM0 channel 2 output/capture input.
EPWM0 channel 3 output/capture input.
EPWM0
EPWM0_CH4
PWM0 channel 4 output/capture input.
EPWM0_CH5
EPWM0 channel 5 output/capture input.
EPWM0_SYNC_IN
EPWM0 counter synchronous trigger input pin.
EPWM0 counter synchronous trigger output
EPWM0_SYNC_OUT PA.11
O
Feb 15, 2019
Page 67 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PF.5
MFP
Type
O
Description
pin.
MFP9
PE.10
PB.7
MFP11
MFP11
MFP11
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP11
MFP12
MFP12
MFP12
MFP12
MFP11
MFP12
MFP10
MFP14
MFP11
MFP10
MFP14
I
EPWM1_BRAKE0
EPWM1_BRAKE1
EPWM1 Brake 0 input pin.
EPWM1 Brake 1 input pin.
I
PB.6
I
PE.11
PC.12
PE.13
PC.5
PB.15
PC.11
PC.8
PC.4
PB.14
PC.10
PC.7
PC.3
PB.13
PC.9
PC.6
PC.2
PB.12
PB.1
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PWM1_CH0
EPWM1_CH1
EPWM1_CH2
EPWM1_CH3
EPWM1_CH4
EPWM1_CH5
EPWM1 channel 0 output/capture input.
PWM1 channel 1 output/capture input.
EPWM1 channel 2 output/capture input.
EPWM1 channel 3 output/capture input.
EPWM1 channel 4 output/capture input.
EPWM1 channel 5 output/capture input.
PWM1
PA.7
PC.1
PB.7
PB.6
PB.0
PA.6
PC.0
PD.11
PA.4
QEI0_A
QEI0_B
I
Quadrature encoder 0 phase A input
Quadrature encoder 0 phase B input
QEI0
PE.3
I
PD.10
PA.3
I
I
Feb 15, 2019
Page 68 of 245
Rev 1.01
M2351
Group
Pin Name
QEI0_INDEX
QEI1_A
GPIO
PE.2
PD.12
PA.5
PE.4
PA.9
PA.13
PE.6
PA.8
PA.14
PE.5
PA.10
PA.12
PE.7
PB.5
PF.6
PA.0
PE.2
PB.4
PF.7
PA.1
PE.3
PB.2
PF.9
PA.3
PE.5
PB.3
PF.8
PA.2
PE.4
PC.12
PF.10
PA.4
PE.6
PC.0
MFP
MFP11
MFP10
MFP14
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP10
MFP12
MFP11
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP9
MFP3
MFP6
MFP6
MFP5
Type
Description
I
I
I
Quadrature encoder 0 index input
Quadrature encoder 1 phase A input
Quadrature encoder 1 phase B input
Quadrature encoder 1 index input
I
I
I
I
I
QEI1
QEI1_B
I
I
I
QEI1_INDEX
I
I
O
O
O
O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
SC0_CLK
SC0_DAT
SC0_PWR
SC0_RST
Smart Card 0 clock pin.
Smart Card 0 data pin.
Smart Card 0 power pin.
Smart Card 0 reset pin.
SC0
I
SC0_nCD
SC1_CLK
Smart Card 0 card detect pin.
Smart Card 1 clock pin.
I
I
SC1
O
Feb 15, 2019
Page 69 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.4
PB.12
PC.1
PD.5
PB.13
PC.3
PD.7
PB.15
PC.2
PD.6
PB.14
PC.4
PD.3
PD.14
PA.8
PA.6
PD.0
PA.15
PE.0
PA.9
PA.7
PD.1
PA.14
PE.1
PA.11
PC.7
PD.3
PA.12
PH.8
PA.10
PC.6
PD.2
PA.13
PH.9
MFP
Type
O
Description
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP3
MFP5
MFP8
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
MFP3
MFP6
MFP7
MFP7
MFP4
O
I/O
I/O
I/O
O
SC1_DAT
SC1_PWR
SC1_RST
SC1_nCD
Smart Card 1 data pin.
O
Smart Card 1 power pin.
Smart Card 1 reset pin.
Smart Card 1 card detect pin.
O
O
O
O
I
I
I
O
O
SC2_CLK
SC2_DAT
SC2_PWR
SC2_RST
O
Smart Card 2 clock pin.
Smart Card 2 data pin.
Smart Card 2 power pin.
Smart Card 2 reset pin.
O
O
I/O
I/O
I/O
I/O
I/O
O
SC2
O
O
O
O
O
O
O
O
O
Feb 15, 2019
Page 70 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PC.13
PA.5
PD.13
PH.10
PB.1
PE.6
PB.0
PE.7
PB.2
PE.2
PB.3
PE.3
PB.4
PE.4
PB.5
PE.5
PD.13
PB.12
PF.2
PA.2
PC.2
PH.8
PA.1
PC.1
PE.1
PA.5
PC.5
PH.10
PA.0
PC.0
PE.0
PA.4
PC.4
PH.11
MFP
Type
I
Description
MFP3
MFP6
MFP7
MFP4
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP9
MFP5
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
MFP3
MFP4
MFP3
I
SC2_nCD
Smart Card 2 card detect pin.
I
I
O
SD0_CLK
SD0_CMD
SD0_DAT0
SD0_DAT1
SD0_DAT2
SD0_DAT3
SD0_nCD
SD/SDIO0 clock output pin
SD/SDIO0 command/response pin
SD/SDIO0 data line bit 0.
SD/SDIO0 data line bit 1.
SD/SDIO0 data line bit 2.
SD/SDIO0 data line bit 3.
SD/SDIO0 card detect input pin
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SD0
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
QSPI0_CLK
Quad SPI0 serial clock pin.
QSPI0_MISO0
QSPI0_MISO1
QSPI0_MOSI0
QSPI0_MOSI1
Quad SPI0 MISO0 (Master In, Slave Out) pin.
Quad SPI0 MISO1 (Master In, Slave Out) pin.
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
QSPI0
Feb 15, 2019
Page 71 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PA.3
PC.3
PH.9
PF.8
PA.2
PD.2
PB.14
PB.0
PF.10
PA.4
PD.13
PD.14
PB.11
PF.7
PA.1
PD.1
PB.13
PF.6
PA.0
PD.0
PB.12
PF.9
PA.3
PD.3
PB.15
PB.3
PH.6
PA.7
PC.1
PD.5
PH.8
PB.1
PA.5
PC.4
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP3
MFP4
MFP3
MFP5
MFP4
MFP4
MFP4
MFP8
MFP5
MFP4
MFP4
MFP6
MFP9
MFP5
MFP4
MFP4
MFP4
MFP5
MFP4
MFP4
MFP4
MFP5
MFP4
MFP4
MFP4
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP4
MFP7
QSPI0_SS
Quad SPI0 slave select pin.
SPI0_CLK
SPI0 serial clock pin.
SPI0_I2SMCLK
SPI0 I2S master clock output pin
SPI0
SPI0_MISO
SPI0 _MOSI
SPI0_SS
SPI0 MISO (Master In, Slave Out) pin.
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 slave select pin.
SPI1_CLK
SPI1 serial clock pin.
SPI1
SPI1_I2SMCLK
SPI1 I2S master clock output pin
Feb 15, 2019
Page 72 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.13
PH.10
PB.5
PH.4
PC.7
PC.3
PD.7
PE.1
PB.4
PH.5
PC.6
PC.2
PD.6
PE.0
PB.2
PH.7
PA.6
PC.0
PD.4
PH.9
PA.10
PG.3
PE.8
PA.13
PC.13
PE.12
PA.9
PG.4
PE.9
PA.14
PA.8
PF.11
PE.10
PA.15
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP5
MFP6
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP5
MFP3
MFP4
MFP7
MFP5
MFP6
MFP4
MFP3
MFP5
MFP5
MFP4
MFP5
MFP4
MFP3
MFP5
MFP5
MFP4
MFP3
MFP5
MFP5
SPI1_MISO
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 slave select pin.
SPI1_MOSI
SPI1_SS
SPI2_CLK
SPI2 serial clock pin.
SPI2_I2SMCLK
SPI2_MISO
SPI2 I2S master clock output pin
SPI2 MISO (Master In, Slave Out) pin.
SPI2
SPI2_MOSI
SPI2 MOSI (Master Out, Slave In) pin.
Feb 15, 2019
Page 73 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PA.11
PG.2
PE.11
PA.12
PC.10
PE.4
MFP
MFP4
MFP3
MFP5
MFP5
MFP6
MFP5
MFP11
MFP6
MFP5
MFP3
MFP6
MFP5
MFP11
MFP6
MFP5
MFP11
MFP6
MFP5
MFP11
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
SPI2_SS
SPI2 slave select pin.
SPI3_CLK
SPI3 serial clock pin.
PB.11
PB.1
SPI3_I2SMCLK
SPI3_MISO
SPI3_MOSI
PE.6
SPI3 I2S master clock output pin
PD.14
PC.12
PE.3
SPI3 MISO (Master In, Slave Out) pin.
SPI3 MOSI (Master Out, Slave In) pin.
SPI3
PB.9
PC.11
PE.2
PB.8
PC.9
PE.5
SPI3_SS
SPI3 slave select pin.
PB.10
TAMPER0
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
TAMPER0
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
PF.6
MFP10
MFP10
MFP10
MFP10
MFP10
MFP10
MFP14
MFP13
MFP14
MFP13
MFP13
MFP14
MFP13
MFP14
MFP13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TAMPER detector loop pin 0.
TAMPER detector loop pin 1.
TAMPER detector loop pin 2.
TAMPER detector loop pin 3.
TAMPER detector loop pin 4.
TAMPER detector loop pin 5.
PF.7
PF.8
PF.9
PF.10
PF.11
PB.5
PG.2
PC.7
PA.11
PB.15
PB.4
PG.3
PC.6
PA.10
TM0
Timer0 event counter input/toggle output pin.
TM0
Timer0 external capture input/toggle output
pin.
TM0_EXT
TM1
Timer1 event counter input/toggle output pin.
TM1
TM1_EXT
Timer1 external capture input/toggle output
Feb 15, 2019
Page 74 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PB.14
PB.3
MFP
MFP13
MFP14
MFP13
MFP14
MFP14
MFP13
MFP13
MFP14
MFP13
MFP14
MFP13
MFP13
MFP14
MFP14
MFP14
MFP14
MFP14
MFP3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
pin.
PG.4
PA.7
TM2
Timer2 event counter input/toggle output pin.
TM2
PD.0
PA.9
Timer2 external capture input/toggle output
pin.
TM2_EXT
TM3
PB.13
PB.2
PF.11
PA.6
Timer3 event counter input/toggle output pin.
TM3
PA.8
Timer3 external capture input/toggle output
pin.
TM3_EXT
PB.12
PE.12
PE.11
PE.10
PE.9
TRACE_CLK
ETM Trace Clock output pin
ETM Trace Data 0 output pin
ETM Trace Data 1 output pin
ETM Trace Data 2 output pin
ETM Trace Data 3 output pin
TRACE_DATA0
TRACE_DATA1
TRACE_DATA2
TRACE_DATA3
O
TRACE
O
O
PE.8
O
PC.11
PF.2
I
MFP3
I
PA.6
MFP7
I
PA.0
MFP7
I
UART0_RXD
PD.2
PA.15
PH.11
PB.12
PB.8
MFP9
I
UART0 data receiver input pin.
MFP3
I
MFP8
I
MFP6
I
UART0
MFP5
I
PC.12
PF.3
MFP3
O
MFP3
O
PA.7
MFP7
O
PA.1
MFP7
O
UART0_TXD
UART0 data transmitter output pin.
PD.3
PA.14
PH.10
PB.13
MFP9
O
MFP3
O
MFP8
O
MFP6
O
Feb 15, 2019
Page 75 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PB.9
PC.7
PA.5
PB.15
PB.11
PC.6
PA.4
PB.14
PB.10
PB.6
PB.2
PA.8
PD.10
PC.8
PA.2
PF.1
PD.6
PH.9
PB.3
PA.9
PD.11
PE.13
PA.3
PF.0
PD.7
PH.8
PB.7
PE.11
PA.1
PB.9
PE.12
PA.0
PB.8
PB.0
MFP
MFP5
MFP7
MFP7
MFP6
MFP5
MFP7
MFP7
MFP6
MFP5
MFP6
MFP6
MFP7
MFP3
MFP8
MFP8
MFP2
MFP3
MFP10
MFP6
MFP7
MFP3
MFP8
MFP8
MFP2
MFP3
MFP10
MFP6
MFP8
MFP8
MFP6
MFP8
MFP8
MFP6
MFP7
Type
Description
O
I
I
UART0_nCTS
UART0 clear to Send input pin.
I
I
O
O
O
O
I
UART0_nRTS
UART0 request to Send output pin.
I
I
I
UART1_RXD
I
UART1 data receiver input pin.
I
I
I
I
O
O
O
O
O
O
O
O
O
I
UART1
UART1_TXD
UART1 data transmitter output pin.
UART1_nCTS
I
UART1 clear to Send input pin.
I
O
O
O
I
UART1_nRTS
UART2_RXD
UART1 request to Send output pin.
UART2 data receiver input pin.
UART2
Feb 15, 2019
Page 76 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.12
PF.5
MFP
MFP7
MFP2
MFP7
MFP3
MFP8
MFP8
MFP7
MFP7
MFP2
MFP7
MFP3
MFP8
MFP8
MFP4
MFP4
MFP8
MFP4
MFP4
MFP8
MFP7
MFP7
MFP11
MFP5
MFP7
MFP7
MFP7
MFP7
MFP11
MFP5
MFP7
MFP7
MFP5
MFP7
MFP7
Type
Description
I
I
PE.9
PE.15
PC.4
PC.0
PB.1
PC.13
PF.4
I
I
I
I
O
O
O
O
O
O
O
I
UART2_TXD
PE.8
PE.14
PC.5
PC.1
PF.5
UART2 data transmitter output pin.
UART2_nCTS
UART2_nRTS
PD.9
PC.2
PF.4
I
UART2 clear to Send input pin.
I
O
O
O
I
PD.8
PC.3
PC.9
PE.11
PC.2
PD.0
PE.0
PB.14
PC.10
PE.10
PC.3
PD.1
PE.1
PB.15
PD.2
PH.9
PB.12
UART2 request to Send output pin.
I
I
UART3_RXD
UART3 data receiver input pin.
I
I
I
O
O
O
O
O
O
I
UART3
UART3_TXD
UART3 data transmitter output pin.
UART3_nCTS
I
UART3 clear to Send input pin.
I
Feb 15, 2019
Page 77 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.3
PH.8
PB.13
PF.6
MFP
MFP5
MFP7
MFP7
MFP6
MFP5
MFP7
MFP11
MFP3
MFP7
MFP6
MFP6
MFP5
MFP7
MFP11
MFP3
MFP7
MFP6
MFP5
MFP9
MFP5
MFP9
MFP7
MFP8
MFP8
MFP7
MFP8
MFP8
MFP7
MFP7
MFP14
MFP14
MFP14
MFP14
MFP14
Type
O
O
O
I
Description
UART3_nRTS
UART3 request to Send output pin.
PC.6
PA.2
PC.4
PA.13
PH.11
PB.10
PF.7
I
I
UART4_RXD
I
UART4 data receiver input pin.
I
I
I
O
O
O
O
O
O
O
I
PC.7
PA.3
PC.5
PA.12
PH.10
PB.11
PC.8
PE.1
PE.13
PE.0
PB.4
PA.4
PE.6
PB.5
PA.5
PE.7
PB.2
PB.3
PA.14
PA.13
PA.15
PA.12
PB.6
UART4
UART4_TXD
UART4 data transmitter output pin.
UART4_nCTS
UART4_nRTS
UART4 clear to Send input pin.
I
O
O
I
UART4 request to Send output pin.
UART5_RXD
UART5_TXD
I
UART5 data receiver input pin.
I
O
O
O
I
UART5
UART5 data transmitter output pin.
UART5_nCTS
UART5_nRTS
USB_D+
UART5 clear to Send input pin.
UART5 request to Send output pin.
USB differential signal D+.
USB differential signal D-.
USB_ identification.
O
A
A
I
USB_D-
USB
USB_OTG_ID
USB_VBUS
USB_VBUS_EN
P
O
Power supply from USB host or HUB.
USB external VBUS regulator enable pin.
Feb 15, 2019
Page 78 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PB.15
PD.4
PB.14
PB.7
PA.11
PD.0
PE.2
PB.12
PC.13
PD.4
PE.6
PD.14
PA.8
PD.3
PE.5
PB.15
PA.10
PD.1
PE.3
PB.13
PA.9
PD.2
PE.4
PB.14
PB.1
PE.12
PD.7
PB.8
PB.5
PE.9
PD.3
PB.10
PB.4
PE.8
MFP
MFP14
MFP14
MFP15
MFP14
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP6
MFP3
MFP7
MFP5
MFP8
MFP6
MFP6
MFP4
MFP8
MFP6
MFP6
MFP4
MFP8
MFP6
Type
O
Description
I
USB_VBUS_ST
I
USB external VBUS regulator status pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USCI0_CLK
USCI0_CTL0
USCI0_CTL1
USCI0_DAT0
USCI0_DAT1
USCI1_CLK
USCI0 clock pin.
USCI0 control 0 pin.
USCI0 control 1 pin.
USCI0 data 0 pin.
USCI0 data 1 pin.
USCI1 clock pin.
USCI0
USCI1
USCI1_CTL0
USCI1_CTL1
USCI1 control 0 pin.
USCI1 control 1 pin.
Feb 15, 2019
Page 79 of 245
Rev 1.01
M2351
Group
Pin Name
GPIO
PD.4
PB.9
PB.2
PE.10
PD.5
PB.7
PB.6
PB.3
PE.11
PD.6
PF.5
PF.4
MFP
MFP6
MFP4
MFP8
MFP6
MFP6
MFP4
MFP4
MFP8
MFP6
MFP6
MFP10
MFP10
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
USCI1_DAT0
USCI1_DAT1
USCI1 data 0 pin.
USCI1 data 1 pin.
X32_IN
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
X32
XT1
X32_OUT
O
External 4~24 MHz (high speed) crystal input
pin.
XT1_IN
PF.3
PF.2
MFP10
MFP10
I
External 4~24 MHz (high speed) crystal output
pin.
XT1_OUT
O
Feb 15, 2019
Page 80 of 245
Rev 1.01
M2351
4.6
M2351 Multi-function Summary Table Sorted by GPIO
Pin Name
Type
I/O
I/O
I/O
O
MFP
MFP0
MFP3
MFP4
MFP6
MFP7
MFP8
MFP9
MFP12
MFP13
MFP15
MFP0
MFP3
MFP4
MFP6
MFP7
MFP8
MFP9
MFP12
MFP13
MFP15
MFP0
MFP3
MFP4
MFP6
MFP7
MFP8
MFP9
MFP12
MFP13
MFP0
MFP3
MFP4
MFP6
Description
PA.0
General purpose digital I/O pin.
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
SPI0 MOSI (Master Out, Slave In) pin.
Smart Card 0 clock pin.
QSPI0_MOSI0
SPI0_MOSI
SC0_CLK
UART0_RXD
UART1_nRTS
I2C2_SDA
BPWM0_CH0
EPWM0_CH5
DAC0_ST
I
UART0 data receiver input pin.
UART1 request to Send output pin.
I2C2 data input/output pin.
PA.0
O
I/O
I/O
I/O
I
BPWM0 channel 0 output/capture input.
EPWM0 channel 5 output/capture input.
DAC0 external trigger input.
PA.1
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
Quad SPI0 MISO0 (Master In, Slave Out) pin.
SPI0 MISO (Master In, Slave Out) pin.
Smart Card 0 data pin.
QSPI0_MISO0
SPI0_MISO
SC0_DAT
UART0_TXD
UART1_nCTS
I2C2_SCL
BPWM0_CH1
EPWM0_CH4
DAC1_ST
UART0 data transmitter output pin.
UART1 clear to Send input pin.
I2C2 clock pin.
PA.1
I
I/O
I/O
I/O
I
BPWM0 channel 1 output/capture input.
EPWM0 channel 4 output/capture input.
DAC1 external trigger input.
PA.2
I/O
I/O
I/O
O
General purpose digital I/O pin.
Quad SPI0 serial clock pin.
QSPI0_CLK
SPI0_CLK
SC0_RST
SPI serial clock pin.
Smart Card 0 reset pin.
PA.2 UART4_RXD
UART1_RXD
I2C1_SDA
I
UART4 data receiver input pin.
UART1 data receiver input pin.
I2C1 data input/output pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
O
BPWM0_CH2
EPWM0_CH3
PA.3
BPWM0 channel 2 output/capture input.
EPWM0 channel 3 output/capture input.
General purpose digital I/O pin.
Quad SPI0 slave select pin.
QSPI0_SS
PA.3
SPI0_SS
SPI0 slave select pin.
SC0_PWR
Smart Card 0 power pin.
Feb 15, 2019
Page 81 of 245
Rev 1.01
M2351
Pin Name
UART4_TXD
UART1_TXD
I2C1_SCL
Type
O
MFP
MFP7
MFP8
MFP9
MFP12
MFP13
MFP14
MFP0
MFP3
MFP4
MFP6
MFP7
MFP8
MFP9
MFP10
MFP12
MFP13
MFP14
MFP0
MFP3
MFP4
MFP6
MFP7
MFP8
MFP9
MFP10
MFP12
MFP13
MFP14
MFP0
MFP2
MFP4
MFP6
MFP7
MFP8
Description
UART4 data transmitter output pin.
UART1 data transmitter output pin.
I2C1 clock pin.
O
I/O
I/O
I/O
I
BPWM0_CH3
EPWM0_CH2
QEI0_B
BPWM0 channel 3 output/capture input.
EPWM0 channel 2 output/capture input.
Quadrature encoder 0 phase B input
General purpose digital I/O pin.
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
SPI0 I2S master clock output pin
Smart Card 0 card detect pin.
UART0 request to Send output pin.
UART5 data receiver input pin.
I2C0 data input/output pin.
PA.4
I/O
I/O
I/O
I
QSPI0_MOSI1
SPI0_I2SMCLK
SC0_nCD
UART0_nRTS
PA.4 UART5_RXD
I2C0_SDA
O
I
I/O
I
CAN0_RXD
BPWM0_CH4
EPWM0_CH1
QEI0_A
CAN0 bus receiver input.
I/O
I/O
I
BPWM0 channel 4 output/capture input.
EPWM0 channel 1 output/capture input.
Quadrature encoder 0 phase A input
General purpose digital I/O pin.
Quad SPI0 MISO1 (Master In, Slave Out) pin.
SPI1 I2S master clock output pin
Smart Card 2 card detect pin.
UART0 clear to Send input pin.
UART5 data transmitter output pin.
I2C0 clock pin.
PA.5
I/O
I/O
I/O
I
QSPI0_MISO1
SPI1_I2SMCLK
SC2_nCD
UART0_nCTS
PA.5 UART5_TXD
I2C0_SCL
I
O
I/O
O
CAN0_TXD
BPWM0_CH5
EPWM0_CH0
QEI0_INDEX
PA.6
CAN0 bus transmitter output.
BPWM0 channel 5 output/capture input.
EPWM0 channel 0 output/capture input.
Quadrature encoder 0 index input
General purpose digital I/O pin.
EBI address/data bus bit 6.
I/O
I/O
I
I/O
I/O
I/O
O
EBI_AD6
SPI1_SS
PA.6
SPI1 slave select pin.
SC2_CLK
Smart Card 2 clock pin.
UART0_RXD
I2C1_SDA
I
UART0 data receiver input pin.
I2C1 data input/output pin.
I/O
Feb 15, 2019
Page 82 of 245
Rev 1.01
M2351
Pin Name
EPWM1_CH5
BPWM1_CH3
ACMP1_WLAT
TM3
Type
I/O
I/O
I
MFP
MFP11
MFP12
MFP13
MFP14
MFP15
MFP0
MFP2
MFP4
MFP6
MFP7
MFP8
MFP11
MFP12
MFP13
MFP14
MFP15
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP9
MFP10
MFP11
MFP13
MFP15
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP9
Description
EPWM1 channel 5 output/capture input.
BPWM1 channel 3 output/capture input.
Analog comparator 1 window latch input pin
Timer3 event counter input/toggle output pin.
External interrupt 0 input pin.
I/O
I
INT0
PA.7
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
EBI address/data bus bit 7.
EBI_AD7
SPI1_CLK
SC2_DAT
UART0_TXD
SPI1 serial clock pin.
Smart Card 2 data pin.
UART0 data transmitter output pin.
I2C1 clock pin.
PA.7 I2C1_SCL
I/O
I/O
I/O
I
EPWM1_CH4
BPWM1_CH2
ACMP0_WLAT
TM2
EPWM1 channel 4 output/capture input.
BPWM1 channel 2 output/capture input.
Analog comparator 0 window latch input pin
Timer2 event counter input/toggle output pin.
External interrupt 1 input pin.
I/O
I
INT1
PA.8
I/O
O
General purpose digital I/O pin.
EBI address latch enable output pin.
Smart Card 2 clock pin.
EBI_ALE
SC2_CLK
O
SPI2_MOSI
USCI0_CTL1
PA.8 UART1_RXD
BPWM0_CH3
QEI1_B
I/O
I/O
I
SPI2 MOSI (Master Out, Slave In) pin.
USCI0 control 1 pin.
UART1 data receiver input pin.
BPWM0 channel 3 output/capture input.
Quadrature encoder 1 phase B input
Enhanced capture unit 0 input 2 pin.
Timer3 external capture input/toggle output pin.
External interrupt 4 input pin.
I/O
I
ECAP0_IC2
TM3_EXT
I
I/O
I
INT4
PA.9
I/O
O
General purpose digital I/O pin.
EBI external clock output pin.
EBI_MCLK
SC2_DAT
I/O
I/O
I/O
O
Smart Card 2 data pin.
PA.9 SPI2_MISO
USCI0_DAT1
UART1_TXD
BPWM0_CH2
SPI2 MISO (Master In, Slave Out) pin.
USCI0 data 1 pin.
UART1 data transmitter output pin.
BPWM0 channel 2 output/capture input.
I/O
Feb 15, 2019
Page 83 of 245
Rev 1.01
M2351
Pin Name
QEI1_A
Type
I
MFP
MFP10
MFP11
MFP13
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP9
MFP10
MFP11
MFP13
MFP14
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP9
MFP10
MFP13
MFP14
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP11
Description
Quadrature encoder 1 phase A input
Enhanced capture unit 0 input 1 pin.
Timer2 external capture input/toggle output pin.
General purpose digital I/O pin.
Analog comparator 1 positive input 0 pin.
EBI write enable output pin.
ECAP0_IC1
TM2_EXT
PA.10
I
I/O
I/O
A
ACMP1_P0
EBI_nWR
SC2_RST
SPI2_CLK
USCI0_DAT0
I2C2_SDA
BPWM0_CH1
QEI1_INDEX
ECAP0_IC0
TM1_EXT
DAC0_ST
PA.11
O
O
Smart Card 2 reset pin.
I/O
I/O
I/O
I/O
I
SPI2 serial clock pin.
USCI0 data 0 pin.
PA.10
I2C2 data input/output pin.
BPWM0 channel 1 output/capture input.
Quadrature encoder 1 index input
Enhanced capture unit 0 input 0 pin.
Timer1 external capture input/toggle output pin.
DAC0 external trigger input.
General purpose digital I/O pin.
Analog comparator 0 positive input 0 pin.
EBI read enable output pin.
I
I/O
I
I/O
A
ACMP0_P0
EBI_nRD
O
SC2_PWR
SPI2_SS
O
Smart Card 2 power pin.
I/O
I/O
I/O
I/O
O
SPI2 slave select pin.
PA.11 USCI0_CLK
I2C2_SCL
USCI0 clock pin.
I2C2 clock pin.
BPWM0_CH0
BPWM0 channel 0 output/capture input.
EPWM0 counter synchronous trigger output pin.
Timer0 external capture input/toggle output pin.
DAC1 external trigger input.
General purpose digital I/O pin.
I2S0 bit clock output pin.
EPWM0_SYNC_OUT
TM0_EXT
DAC1_ST
PA.12
I/O
I
I/O
O
I2S0_BCLK
UART4_TXD
I2C1_SCL
SPI2_SS
O
UART4 data transmitter output pin.
I2C1 clock pin.
I/O
I/O
O
PA.12
SPI2 slave select pin.
CAN0_TXD
SC2_PWR
BPWM1_CH2
CAN0 bus transmitter output.
Smart Card 2 power pin.
O
I/O
BPWM1 channel 2 output/capture input.
Feb 15, 2019
Page 84 of 245
Rev 1.01
M2351
Pin Name
QEI1_INDEX
USB_VBUS
PA.13
Type
I
MFP
MFP12
MFP14
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP11
MFP12
MFP14
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP14
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP14
MFP0
MFP1
MFP2
MFP3
Description
Quadrature encoder 1 index input
Power supply from USB host or HUB.
General purpose digital I/O pin.
I2S0 master clock output pin.
UART4 data receiver input pin.
I2C1 data input/output pin.
P
I/O
O
I2S0_MCLK
UART4_RXD
I2C1_SDA
SPI2_CLK
CAN0_RXD
SC2_RST
BPWM1_CH3
QEI1_A
I
I/O
I/O
I
SPI2 serial clock pin.
PA.13
CAN0 bus receiver input.
O
Smart Card 2 reset pin.
I/O
I
BPWM1 channel 3 output/capture input.
Quadrature encoder 1 phase A input
USB differential signal D-.
USB_D-
A
PA.14
I/O
I
General purpose digital I/O pin.
I2S0 data input pin.
I2S0_DI
UART0_TXD
SPI2_MISO
O
UART0 data transmitter output pin.
SPI2 MISO (Master In, Slave Out) pin.
I2C2 clock pin.
I/O
I/O
I/O
I/O
I
PA.14 I2C2_SCL
SC2_DAT
Smart Card 2 data pin.
BPWM1_CH4
BPWM1 channel 4 output/capture input.
Quadrature encoder 1 phase B input
USB differential signal D+.
QEI1_B
USB_D+
A
PA.15
I/O
O
General purpose digital I/O pin.
I2S0 data output pin.
I2S0_DO
UART0_RXD
SPI2_MOSI
PA.15 I2C2_SDA
SC2_CLK
I
UART0 data receiver input pin.
SPI2 MOSI (Master Out, Slave In) pin.
I2C2 data input/output pin.
I/O
I/O
O
Smart Card 2 clock pin.
BPWM1_CH5
I/O
I
BPWM1 channel 5 output/capture input.
EPWM0 counter synchronous trigger input pin.
USB_ identification.
EPWM0_SYNC_IN
USB_OTG_ID
PB.0
I
I/O
A
General purpose digital I/O pin.
EADC0 channel 0 analog input.
EBI address bus bit 9.
EADC0_CH0
EBI_ADR9
SD0_CMD
PB.0
O
I/O
SD/SDIO0 command/response pin
Feb 15, 2019
Page 85 of 245
Rev 1.01
M2351
Pin Name
Type
I
MFP
MFP7
MFP8
MFP9
MFP11
MFP12
MFP13
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP9
MFP10
MFP11
MFP12
MFP13
MFP0
MFP1
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP9
MFP10
MFP11
MFP14
MFP15
MFP0
Description
UART2_RXD
SPI0_I2SMCLK
I2C1_SDA
UART2 data receiver input pin.
SPI0 I2S master clock output pin
I2C1 data input/output pin.
I/O
I/O
I/O
I/O
I
EPWM0_CH5
EPWM1_CH5
EPWM0_BRAKE1
PB.1
EPWM0 channel 5 output/capture input.
EPWM1 channel 5 output/capture input.
EPWM0 Brake 1 input pin.
I/O
A
General purpose digital I/O pin.
EADC0 channel 1 analog input.
EBI address bus bit 8.
EADC0_CH1
EBI_ADR8
O
SD0_CLK
O
SD/SDIO0 clock output pin
SPI1_I2SMCLK
SPI3_I2SMCLK
I/O
I/O
O
SPI1 I2S master clock output pin
SPI3 I2S master clock output pin
UART2 data transmitter output pin.
USCI1 clock pin.
PB.1 UART2_TXD
USCI1_CLK
I2C1_SCL
I2S0_LRCK
EPWM0_CH4
EPWM1_CH4
EPWM0_BRAKE0
PB.2
I/O
I/O
O
I2C1 clock pin.
I2S0 left right channel clock output pin.
EPWM0 channel 4 output/capture input.
EPWM1 channel 4 output/capture input.
EPWM0 Brake 0 input pin.
I/O
I/O
I
I/O
A
General purpose digital I/O pin.
EADC0 channel 2 analog input.
Analog comparator 0 positive input 1 pin.
EBI address bus bit 3.
EADC0_CH2
ACMP0_P1
EBI_ADR3
SD0_DAT0
SPI1_SS
A
O
I/O
I/O
I
SD/SDIO0 data line bit 0.
SPI1 slave select pin.
UART1_RXD
UART5_nCTS
USCI1_DAT0
SC0_PWR
I2S0_DO
UART1 data receiver input pin.
UART5 clear to Send input pin.
USCI1 data 0 pin.
PB.2
I
I/O
O
Smart Card 0 power pin.
O
I2S0 data output pin.
EPWM0_CH3
TM3
I/O
I/O
I
EPWM0 channel 3 output/capture input.
Timer3 event counter input/toggle output pin.
External interrupt 3 input pin.
General purpose digital I/O pin.
INT3
PB.3 PB.3
I/O
Feb 15, 2019
Page 86 of 245
Rev 1.01
M2351
Pin Name
EADC0_CH3
ACMP0_N
EBI_ADR2
SD0_DAT1
SPI1_CLK
UART1_TXD
UART5_nRTS
USCI1_DAT1
SC0_RST
I2S0_DI
Type
A
MFP
MFP1
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP9
MFP10
MFP11
MFP14
MFP15
MFP0
MFP1
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP9
MFP10
MFP11
MFP14
MFP15
MFP0
MFP1
MFP1
MFP2
MFP3
MFP5
MFP6
Description
EADC0 channel 3 analog input.
Analog comparator 0 negative input pin.
EBI address bus bit 2.
A
O
I/O
I/O
O
SD/SDIO0 data line bit 1.
SPI1 serial clock pin.
UART1 data transmitter output pin.
UART5 request to Send output pin.
USCI1 data 1 pin.
O
I/O
O
Smart Card 0 reset pin.
I
I2S0 data input pin.
EPWM0_CH2
TM2
I/O
I/O
I
EPWM0 channel 2 output/capture input.
Timer2 event counter input/toggle output pin.
External interrupt 2 input pin.
General purpose digital I/O pin.
EADC0 channel 4 analog input.
Analog comparator 1 positive input 1 pin.
EBI address bus bit 1.
INT2
PB.4
I/O
A
EADC0_CH4
ACMP1_P1
EBI_ADR1
SD0_DAT2
SPI1_MOSI
I2C0_SDA
UART5_RXD
USCI1_CTL1
SC0_DAT
I2S0_MCLK
EPWM0_CH1
TM1
A
O
I/O
I/O
I/O
I
SD/SDIO0 data line bit 2.
SPI1 MOSI (Master Out, Slave In) pin.
I2C0 data input/output pin.
PB.4
UART5 data receiver input pin.
USCI1 control 1 pin.
I/O
I/O
O
Smart Card 0 data pin.
I2S0 master clock output pin.
EPWM0 channel 1 output/capture input.
Timer1 event counter input/toggle output pin.
External interrupt 1 input pin.
General purpose digital I/O pin.
EADC0 channel 5 analog input.
Analog comparator 1 negative input pin.
EBI address bus bit 0.
I/O
I/O
I
INT1
PB.5
I/O
A
EADC0_CH5
ACMP1_N
A
PB.5 EBI_ADR0
SD0_DAT3
O
I/O
I/O
I/O
SD/SDIO0 data line bit 3.
SPI1_MISO
SPI1 MISO (Master In, Slave Out) pin.
I2C0 clock pin.
I2C0_SCL
Feb 15, 2019
Page 87 of 245
Rev 1.01
M2351
Pin Name
Type
O
MFP
MFP7
MFP8
MFP9
MFP10
MFP11
MFP14
MFP15
MFP0
MFP1
MFP2
MFP4
MFP6
MFP8
MFP10
MFP11
MFP12
MFP13
MFP14
MFP15
MFP0
MFP1
MFP2
MFP4
MFP6
MFP8
MFP10
MFP11
MFP12
MFP13
MFP14
MFP15
MFP0
MFP1
MFP2
Description
UART5_TXD
USCI1_CTL0
SC0_CLK
UART5 data transmitter output pin.
USCI1 control 0 pin.
I/O
O
Smart Card 0 clock pin.
I2S0_BCLK
EPWM0_CH0
TM0
O
I2S0 bit clock output pin.
I/O
I/O
I
EPWM0 channel 0 output/capture input.
Timer0 event counter input/toggle output pin.
External interrupt 0 input pin.
General purpose digital I/O pin.
EADC0 channel 6 analog input.
EBI high byte write enable output pin
USCI1 data 1 pin.
INT0
PB.6
I/O
A
EADC0_CH6
EBI_nWRH
USCI1_DAT1
UART1_RXD
EBI_nCS1
BPWM1_CH5
EPWM1_BRAKE1
EPWM1_CH5
INT4
O
I/O
I
UART1 data receiver input pin.
EBI chip select 1 output pin.
O
PB.6
I/O
I
BPWM1 channel 5 output/capture input.
EPWM1 Brake 1 input pin.
I/O
I
EPWM1 channel 5 output/capture input.
External interrupt 4 input pin.
USB external VBUS regulator enable pin.
Analog comparator 1 output pin.
General purpose digital I/O pin.
EADC0 channel 7 analog input.
EBI low byte write enable output pin.
USCI1 data 0 pin.
USB_VBUS_EN
ACMP1_O
PB.7
O
O
I/O
A
EADC0_CH7
EBI_nWRL
USCI1_DAT0
UART1_TXD
EBI_nCS0
BPWM1_CH4
EPWM1_BRAKE0
EPWM1_CH4
INT5
O
I/O
O
UART1 data transmitter output pin.
EBI chip select 0 output pin.
O
PB.7
I/O
I
BPWM1 channel 4 output/capture input.
EPWM1 Brake 0 input pin.
I/O
I
EPWM1 channel 4 output/capture input.
External interrupt 5 input pin.
USB external VBUS regulator status pin.
Analog comparator 0 output pin.
General purpose digital I/O pin.
EADC0 channel 8 analog input.
EBI address bus bit 19.
USB_VBUS_ST
ACMP0_O
PB.8
I
O
I/O
A
PB.8 EADC0_CH8
EBI_ADR19
O
Feb 15, 2019
Page 88 of 245
Rev 1.01
M2351
Pin Name
Type
I/O
I
MFP
MFP4
MFP5
MFP6
MFP7
MFP10
MFP11
MFP13
MFP0
MFP1
MFP2
MFP4
MFP5
MFP6
MFP7
MFP10
MFP11
MFP13
MFP0
MFP1
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP10
MFP11
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP8
Description
USCI1_CLK
UART0_RXD
UART1_nRTS
I2C1_SMBSUS
BPWM1_CH3
SPI3_MOSI
INT6
USCI1 clock pin.
UART0 data receiver input pin.
UART1 request to Send output pin.
O
O
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
BPWM1 channel 3 output/capture input.
SPI3 MOSI (Master Out, Slave In) pin.
External interrupt 6 input pin.
General purpose digital I/O pin.
EADC0 channel 9 analog input.
EBI address bus bit 18.
I/O
I/O
I
PB.9
I/O
A
EADC0_CH9
EBI_ADR18
USCI1_CTL1
UART0_TXD
UART1_nCTS
I2C1_SMBAL
BPWM1_CH2
SPI3_MISO
INT7
O
I/O
O
USCI1 control 1 pin.
UART0 data transmitter output pin.
UART1 clear to Send input pin.
I2C1 SMBus SMBALTER pin
BPWM1 channel 2 output/capture input.
SPI3 MISO (Master In, Slave Out) pin.
External interrupt 7 input pin.
General purpose digital I/O pin.
EADC0 channel 10 analog input.
EBI address bus bit 17.
PB.9
I
O
I/O
I/O
I
PB.10
I/O
A
EADC0_CH10
EBI_ADR17
USCI1_CTL0
UART0_nRTS
UART4_RXD
I2C1_SDA
O
I/O
O
USCI1 control 0 pin.
UART0 request to Send output pin.
UART4 data receiver input pin.
I2C1 data input/output pin.
PB.10
I
I/O
I
CAN0_RXD
BPWM1_CH1
SPI3_SS
CAN0 bus receiver input.
I/O
I/O
I/O
A
BPWM1 channel 1 output/capture input.
SPI3 slave select pin.
PB.11
General purpose digital I/O pin.
EADC0 channel 11 analog input.
EBI address bus bit 16.
EADC0_CH11
EBI_ADR16
O
PB.11 UART0_nCTS
UART4_TXD
I
UART0 clear to Send input pin.
UART4 data transmitter output pin.
I2C1 clock pin.
O
I2C1_SCL
I/O
O
CAN0_TXD
CAN0 bus transmitter output.
Feb 15, 2019
Page 89 of 245
Rev 1.01
M2351
Pin Name
SPI0_I2SMCLK
BPWM1_CH0
SPI3_CLK
Type
I/O
I/O
I/O
I/O
A
MFP
MFP9
MFP10
MFP11
MFP0
MFP1
MFP1
MFP1
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP11
MFP13
MFP0
MFP1
MFP1
MFP1
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP11
MFP13
MFP0
MFP1
Description
SPI0 I2S master clock output pin
BPWM1 channel 0 output/capture input.
SPI3 serial clock pin.
PB.12
General purpose digital I/O pin.
EADC0 channel 12 analog input.
DAC0 channel analog output.
Analog comparator 0 positive input 2 pin.
Analog comparator 1 positive input 2 pin.
EBI address/data bus bit 15.
EADC0_CH12
DAC0_OUT
ACMP0_P2
ACMP1_P2
EBI_AD15
A
A
A
I/O
O
SC1_CLK
Smart Card 1 clock pin.
PB.12 SPI0_MOSI
USCI0_CLK
UART0_RXD
UART3_nCTS
I2C2_SDA
I/O
I/O
I
SPI0 MOSI (Master Out, Slave In) pin.
USCI0 clock pin.
UART0 data receiver input pin.
UART3 clear to Send input pin.
I2C2 data input/output pin.
I
I/O
I
SD0_nCD
SD/SDIO0 card detect input pin
EPWM1 channel 3 output/capture input.
Timer3 external capture input/toggle output pin.
General purpose digital I/O pin.
EADC0 channel 13 analog input.
DAC1 channel analog output.
Analog comparator 0 positive input 3 pin.
Analog comparator 1 positive input 3 pin.
EBI address/data bus bit 14.
EPWM1_CH3
TM3_EXT
I/O
I/O
I/O
A
PB.13
EADC0_CH13
DAC1_OUT
ACMP0_P3
ACMP1_P3
EBI_AD14
A
A
A
I/O
I/O
I/O
I/O
O
SC1_DAT
PB.13
Smart Card 1 data pin.
SPI0_MISO
SPI0 MISO (Master In, Slave Out) pin.
USCI0 data 0 pin.
USCI0_DAT0
UART0_TXD
UART3_nRTS
I2C2_SCL
UART0 data transmitter output pin.
UART3 request to Send output pin.
I2C2 clock pin.
O
I/O
I/O
I/O
I/O
A
EPWM1_CH2
TM2_EXT
EPWM1 channel 2 output/capture input.
Timer2 external capture input/toggle output pin.
General purpose digital I/O pin.
EADC0 channel 14 analog input.
PB.14
PB.14
EADC0_CH14
Feb 15, 2019
Page 90 of 245
Rev 1.01
M2351
Pin Name
Type
I/O
O
MFP
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP11
MFP13
MFP14
MFP15
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP11
MFP13
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP12
MFP14
MFP0
Description
EBI_AD13
EBI address/data bus bit 13.
Smart Card 1 reset pin.
SPI0 serial clock pin.
SC1_RST
SPI0_CLK
I/O
I/O
O
USCI0_DAT1
UART0_nRTS
UART3_RXD
I2C2_SMBSUS
EPWM1_CH1
TM1_EXT
USCI0 data 1 pin.
UART0 request to Send output pin.
UART3 data receiver input pin.
I
O
I2C2 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1 channel 1 output/capture input.
Timer1 external capture input/toggle output pin.
Clock Out
I/O
I/O
O
CLKO
USB_VBUS_ST
PB.15
I
USB external VBUS regulator status pin.
General purpose digital I/O pin.
EADC0 channel 15 analog input.
EBI address/data bus bit 12.
I/O
A
EADC0_CH15
EBI_AD12
I/O
O
SC1_PWR
SPI0_SS
Smart Card 1 power pin.
I/O
I/O
I
SPI0 slave select pin.
USCI0_CTL1
UART0_nCTS
UART3_TXD
I2C2_SMBAL
EPWM1_CH0
TM0_EXT
USCI0 control 1 pin.
PB.15
UART0 clear to Send input pin.
UART3 data transmitter output pin.
I2C2 SMBus SMBALTER pin
O
O
I/O
I/O
O
EPWM1 channel 0 output/capture input.
Timer0 external capture input/toggle output pin.
USB external VBUS regulator enable pin.
General purpose digital I/O pin.
EBI address/data bus bit 0.
USB_VBUS_EN
PC.0
I/O
I/O
I/O
O
EBI_AD0
QSPI0_MOSI0
SC1_CLK
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
Smart Card 1 clock pin.
I2S0_LRCK
SPI1_SS
O
I2S0 left right channel clock output pin.
SPI1 slave select pin.
PC.0
I/O
I
UART2_RXD
I2C0_SDA
UART2 data receiver input pin.
I2C0 data input/output pin.
I/O
I/O
O
EPWM1_CH5
ACMP1_O
EPWM1 channel 5 output/capture input.
Analog comparator 1 output pin.
General purpose digital I/O pin.
PC.1 PC.1
I/O
Feb 15, 2019
Page 91 of 245
Rev 1.01
M2351
Pin Name
EBI_AD1
Type
I/O
I/O
I/O
O
MFP
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP12
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP11
MFP12
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP11
MFP12
MFP0
MFP2
MFP4
MFP5
MFP6
Description
EBI address/data bus bit 1.
Quad SPI0 MISO0 (Master In, Slave Out) pin.
Smart Card 1 data pin.
QSPI0_MISO0
SC1_DAT
I2S0_DO
I2S0 data output pin.
SPI1_CLK
UART2_TXD
I2C0_SCL
EPWM1_CH4
ACMP0_O
PC.2
I/O
O
SPI1 serial clock pin.
UART2 data transmitter output pin.
I2C0 clock pin.
I/O
I/O
O
EPWM1 channel 4 output/capture input.
Analog comparator 0 output pin.
General purpose digital I/O pin.
EBI address/data bus bit 2.
Quad SPI0 serial clock pin.
Smart Card 1 reset pin.
I/O
I/O
I/O
O
EBI_AD2
QSPI0_CLK
SC1_RST
I2S0_DI
I
I2S0 data input pin.
PC.2
SPI1_MOSI
UART2_nCTS
I2C0_SMBSUS
UART3_RXD
EPWM1_CH3
PC.3
I/O
I
SPI1 MOSI (Master Out, Slave In) pin.
UART2 clear to Send input pin.
O
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
UART3 data receiver input pin.
EPWM1 channel 3 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 3.
I
I/O
I/O
I/O
I/O
O
EBI_AD3
QSPI0_SS
SC1_PWR
I2S0_MCLK
SPI1_MISO
UART2_nRTS
I2C0_SMBAL
UART3_TXD
EPWM1_CH2
PC.4
Quad SPI0 slave select pin.
Smart Card 1 power pin.
O
I2S0 master clock output pin.
PC.3
I/O
O
SPI1 MISO (Master In, Slave Out) pin.
UART2 request to Send output pin.
I2C0 SMBus SMBALTER pin
O
O
UART3 data transmitter output pin.
EPWM1 channel 2 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 4.
I/O
I/O
I/O
I/O
I
EBI_AD4
PC.4 QSPI0_MOSI1
SC1_nCD
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
Smart Card 1 card detect pin.
I2S0_BCLK
O
I2S0 bit clock output pin.
Feb 15, 2019
Page 92 of 245
Rev 1.01
M2351
Pin Name
Type
I/O
I
MFP
MFP7
MFP8
MFP9
MFP10
MFP11
MFP12
MFP0
MFP2
MFP4
MFP8
MFP9
MFP10
MFP11
MFP12
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP11
MFP12
MFP14
MFP15
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP11
MFP12
Description
SPI1_I2SMCLK
UART2_RXD
I2C1_SDA
CAN0_RXD
UART4_RXD
EPWM1_CH1
PC.5
SPI1 I2S master clock output pin
UART2 data receiver input pin.
I2C1 data input/output pin.
I/O
I
CAN0 bus receiver input.
I
UART4 data receiver input pin.
EPWM1 channel 1 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 5.
I/O
I/O
I/O
I/O
O
EBI_AD5
QSPI0_MISO1
UART2_TXD
I2C1_SCL
Quad SPI0 MISO1 (Master In, Slave Out) pin.
UART2 data transmitter output pin.
I2C1 clock pin.
PC.5
I/O
O
CAN0_TXD
UART4_TXD
EPWM1_CH0
PC.6
CAN0 bus transmitter output.
UART4 data transmitter output pin.
EPWM1 channel 0 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 8.
O
I/O
I/O
I/O
I/O
I
EBI_AD8
SPI1_MOSI
UART4_RXD
SC2_RST
SPI1 MOSI (Master Out, Slave In) pin.
UART4 data receiver input pin.
Smart Card 2 reset pin.
O
PC.6 UART0_nRTS
I2C1_SMBSUS
EPWM1_CH3
BPWM1_CH1
TM1
O
UART0 request to Send output pin.
O
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
EPWM1 channel 3 output/capture input.
BPWM1 channel 1 output/capture input.
Timer1 event counter input/toggle output pin.
External interrupt 2 input pin.
I/O
I/O
I/O
I
INT2
PC.7
I/O
I/O
I/O
O
General purpose digital I/O pin.
EBI_AD9
EBI address/data bus bit 9.
SPI1_MISO
UART4_TXD
PC.7 SC2_PWR
UART0_nCTS
I2C1_SMBAL
EPWM1_CH2
BPWM1_CH0
SPI1 MISO (Master In, Slave Out) pin.
UART4 data transmitter output pin.
Smart Card 2 power pin.
O
I
UART0 clear to Send input pin.
O
I2C1 SMBus SMBALTER pin
I/O
I/O
EPWM1 channel 2 output/capture input.
BPWM1 channel 0 output/capture input.
Feb 15, 2019
Page 93 of 245
Rev 1.01
M2351
Pin Name
TM0
Type
I/O
I
MFP
MFP14
MFP15
MFP0
MFP2
MFP4
MFP5
MFP8
MFP11
MFP12
MFP0
MFP2
MFP6
MFP7
MFP12
MFP0
MFP2
MFP6
MFP7
MFP11
MFP12
MFP0
MFP2
MFP3
MFP4
MFP6
MFP11
MFP12
MFP14
MFP0
MFP2
MFP3
MFP4
MFP6
MFP9
Description
Timer0 event counter input/toggle output pin.
External interrupt 3 input pin.
General purpose digital I/O pin.
EBI address bus bit 16.
INT3
PC.8
I/O
O
EBI_ADR16
I2C0_SDA
PC.8 UART4_nCTS
UART1_RXD
EPWM1_CH1
BPWM1_CH4
PC.9
I/O
I
I2C0 data input/output pin.
UART4 clear to Send input pin.
UART1 data receiver input pin.
EPWM1 channel 1 output/capture input.
BPWM1 channel 4 output/capture input.
General purpose digital I/O pin.
EBI address bus bit 7.
I
I/O
I/O
I/O
O
EBI_ADR7
PC.9 SPI3_SS
UART3_RXD
EPWM1_CH3
PC.10
I/O
I
SPI3 slave select pin.
UART3 data receiver input pin.
EPWM1 channel 3 output/capture input.
General purpose digital I/O pin.
EBI address bus bit 6.
I/O
I/O
O
EBI_ADR6
SPI3_CLK
PC.10
I/O
O
SPI3 serial clock pin.
UART3_TXD
UART3 data transmitter output pin.
Enhanced capture unit 1 input 0 pin.
EPWM1 channel 2 output/capture input.
General purpose digital I/O pin.
EBI address bus bit 5.
ECAP1_IC0
EPWM1_CH2
PC.11
I
I/O
I/O
O
EBI_ADR5
UART0_RXD
I
UART0 data receiver input pin.
I2C0 data input/output pin.
I2C0_SDA
PC.11
I/O
I/O
I
SPI3_MOSI
SPI3 MOSI (Master Out, Slave In) pin.
Enhanced capture unit 1 input 1 pin.
EPWM1 channel 1 output/capture input.
Analog comparator 1 output pin.
General purpose digital I/O pin.
EBI address bus bit 4.
ECAP1_IC1
EPWM1_CH1
ACMP1_O
PC.12
I/O
O
I/O
O
EBI_ADR4
UART0_TXD
PC.12
O
UART0 data transmitter output pin.
I2C0 clock pin.
I2C0_SCL
I/O
I/O
I
SPI3_MISO
SC0_nCD
SPI3 MISO (Master In, Slave Out) pin.
Smart Card 0 card detect pin.
Feb 15, 2019
Page 94 of 245
Rev 1.01
M2351
Pin Name
ECAP1_IC2
EPWM1_CH0
ACMP0_O
Type
I
MFP
MFP11
MFP12
MFP14
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP9
MFP13
MFP14
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP14
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP9
Description
Enhanced capture unit 1 input 2 pin.
EPWM1 channel 0 output/capture input.
Analog comparator 0 output pin.
General purpose digital I/O pin.
EBI address bus bit 10.
I/O
O
PC.13
I/O
O
EBI_ADR10
SC2_nCD
I
Smart Card 2 card detect pin.
SPI2 I2S master clock output pin
USCI0 control 0 pin.
SPI2_I2SMCLK
PC.13 USCI0_CTL0
UART2_TXD
BPWM0_CH4
CLKO
I/O
I/O
O
UART2 data transmitter output pin.
BPWM0 channel 4 output/capture input.
Clock Out
I/O
O
EADC0_ST
PD.0
I
EADC0 external trigger input.
General purpose digital I/O pin.
EBI address/data bus bit 13.
USCI0 clock pin.
I/O
I/O
I/O
I/O
I
EBI_AD13
USCI0_CLK
SPI0_MOSI
PD.0
SPI0 MOSI (Master Out, Slave In) pin.
UART3 data receiver input pin.
I2C2 data input/output pin.
Smart Card 2 clock pin.
UART3_RXD
I2C2_SDA
SC2_CLK
I/O
O
TM2
I/O
I/O
I/O
I/O
I/O
O
Timer2 event counter input/toggle output pin.
General purpose digital I/O pin.
EBI address/data bus bit 12.
USCI0 data 0 pin.
PD.1
EBI_AD12
USCI0_DAT0
PD.1 SPI0_MISO
UART3_TXD
I2C2_SCL
SPI0 MISO (Master In, Slave Out) pin.
UART3 data transmitter output pin.
I2C2 clock pin.
I/O
I/O
I/O
I/O
I/O
I/O
I
SC2_DAT
Smart Card 2 data pin.
PD.2
General purpose digital I/O pin.
EBI address/data bus bit 11.
USCI0 data 1 pin.
EBI_AD11
USCI0_DAT1
PD.2 SPI0_CLK
UART3_nCTS
SC2_RST
SPI0 serial clock pin.
UART3 clear to Send input pin.
Smart Card 2 reset pin.
O
UART0_RXD
I
UART0 data receiver input pin.
Feb 15, 2019
Page 95 of 245
Rev 1.01
M2351
Pin Name
PD.3
Type
I/O
I/O
I/O
I/O
O
MFP
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP0
MFP3
MFP4
MFP5
MFP6
MFP8
MFP14
MFP0
MFP4
MFP5
MFP6
MFP8
MFP0
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
Description
General purpose digital I/O pin.
EBI address/data bus bit 10.
USCI0 control 1 pin.
EBI_AD10
USCI0_CTL1
SPI0_SS
SPI0 slave select pin.
PD.3 UART3_nRTS
USCI1_CTL0
SC2_PWR
UART3 request to Send output pin.
USCI1 control 0 pin.
I/O
O
Smart Card 2 power pin.
Smart Card 1 card detect pin.
UART0 data transmitter output pin.
General purpose digital I/O pin.
USCI0 control 0 pin.
SC1_nCD
I
UART0_TXD
PD.4
O
I/O
I/O
I/O
I/O
I/O
O
USCI0_CTL0
I2C1_SDA
I2C1 data input/output pin.
SPI1 slave select pin.
PD.4 SPI1_SS
USCI1_CTL1
SC1_CLK
USCI1 control 1 pin.
Smart Card 1 clock pin.
USB_VBUS_ST
PD.5
I
USB external VBUS regulator status pin.
General purpose digital I/O pin.
I2C1 clock pin.
I/O
I/O
I/O
I/O
I/O
I/O
I
I2C1_SCL
PD.5 SPI1_CLK
USCI1_DAT0
SC1_DAT
SPI1 serial clock pin.
USCI1 data 0 pin.
Smart Card 1 data pin.
PD.6
General purpose digital I/O pin.
UART1 data receiver input pin.
I2C0 data input/output pin.
SPI1 MOSI (Master Out, Slave In) pin.
USCI1 data 1 pin.
UART1_RXD
I2C0_SDA
PD.6
I/O
I/O
I/O
O
SPI1_MOSI
USCI1_DAT1
SC1_RST
PD.7
Smart Card 1 reset pin.
I/O
O
General purpose digital I/O pin.
UART1 data transmitter output pin.
I2C0 clock pin.
UART1_TXD
I2C0_SCL
PD.7
I/O
I/O
I/O
O
SPI1_MISO
SPI1 MISO (Master In, Slave Out) pin.
USCI1 clock pin.
USCI1_CLK
SC1_PWR
Smart Card 1 power pin.
General purpose digital I/O pin.
PD.8 PD.8
I/O
Feb 15, 2019
Page 96 of 245
Rev 1.01
M2351
Pin Name
EBI_AD6
I2C2_SDA
UART2_nRTS
PD.9
Type
I/O
I/O
O
MFP
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP10
MFP15
MFP0
MFP2
MFP3
MFP4
MFP10
MFP15
MFP0
MFP2
MFP7
MFP9
MFP10
MFP13
MFP14
MFP15
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
Description
EBI address/data bus bit 6.
I2C2 data input/output pin.
UART2 request to Send output pin.
General purpose digital I/O pin.
EBI address/data bus bit 7.
I2C2 clock pin.
I/O
I/O
I/O
I
EBI_AD7
I2C2_SCL
UART2_nCTS
PD.10
PD.9
UART2 clear to Send input pin.
General purpose digital I/O pin.
EBI chip select 2 output pin.
UART1 data receiver input pin.
CAN0 bus receiver input.
I/O
O
EBI_nCS2
UART1_RXD
CAN0_RXD
QEI0_B
I
PD.10
I
I
Quadrature encoder 0 phase B input
External interrupt 7 input pin.
General purpose digital I/O pin.
EBI chip select 1 output pin.
UART1 data transmitter output pin.
CAN0 bus transmitter output.
Quadrature encoder 0 phase A input
External interrupt 6 input pin.
General purpose digital I/O pin.
EBI chip select 0 output pin.
UART2 data receiver input pin.
BPWM0 channel 5 output/capture input.
Quadrature encoder 0 index input
Clock Out
INT7
I
PD.11
I/O
O
EBI_nCS1
UART1_TXD
CAN0_TXD
QEI0_A
O
PD.11
PD.12
PD.13
O
I
INT6
I
PD.12
I/O
O
EBI_nCS0
UART2_RXD
BPWM0_CH5
QEI0_INDEX
CLKO
I
I/O
I
O
EADC0_ST
INT5
I
EADC0 external trigger input.
External interrupt 5 input pin.
General purpose digital I/O pin.
EBI address/data bus bit 10.
SD/SDIO0 card detect input pin
SPI0 I2S master clock output pin
SPI1 I2S master clock output pin
Smart Card 2 card detect pin.
General purpose digital I/O pin.
I
PD.13
I/O
I/O
I
EBI_AD10
SD0_nCD
SPI0_I2SMCLK
SPI1_I2SMCLK
SC2_nCD
I/O
I/O
I
PD.14 PD.14
I/O
Feb 15, 2019
Page 97 of 245
Rev 1.01
M2351
Pin Name
EBI_nCS0
Type
O
MFP
MFP2
MFP3
MFP4
MFP5
MFP6
MFP11
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP13
MFP0
Description
EBI chip select 0 output pin.
SPI3 I2S master clock output pin
Smart Card 1 card detect pin.
USCI0 control 0 pin.
SPI3_I2SMCLK
SC1_nCD
I/O
I
USCI0_CTL0
SPI0_I2SMCLK
EPWM0_CH4
PE.0
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI0 I2S master clock output pin
EPWM0 channel 4 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 11.
Quad SPI0 MOSI0 (Master Out, Slave In) pin.
Smart Card 2 clock pin.
EBI_AD11
QSPI0_MOSI0
SC2_CLK
PE.0 I2S0_MCLK
SPI1_MOSI
UART3_RXD
I2C1_SDA
O
I2S0 master clock output pin.
SPI1 MOSI (Master Out, Slave In) pin.
UART3 data receiver input pin.
I2C1 data input/output pin.
I/O
I
I/O
O
UART4_nRTS
PE.1
UART4 request to Send output pin.
General purpose digital I/O pin.
EBI address/data bus bit 10.
Quad SPI0 MISO0 (Master In, Slave Out) pin.
Smart Card 2 data pin.
I/O
I/O
I/O
I/O
O
EBI_AD10
QSPI0_MISO0
SC2_DAT
PE.1 I2S0_BCLK
SPI1_MISO
UART3_TXD
I2C1_SCL
I2S0 bit clock output pin.
I/O
O
SPI1 MISO (Master In, Slave Out) pin.
UART3 data transmitter output pin.
I2C1 clock pin.
I/O
I
UART4_nCTS
PE.2
UART4 clear to Send input pin.
General purpose digital I/O pin.
EBI address latch enable output pin.
SD/SDIO0 data line bit 0.
I/O
O
EBI_ALE
SD0_DAT0
SPI3_MOSI
PE.2 SC0_CLK
USCI0_CLK
QEI0_B
I/O
I/O
O
SPI3 MOSI (Master Out, Slave In) pin.
Smart Card 0 clock pin.
I/O
I
USCI0 clock pin.
Quadrature encoder 0 phase B input
EPWM0 channel 5 output/capture input.
BPWM0 channel 0 output/capture input.
General purpose digital I/O pin.
EPWM0_CH5
BPWM0_CH0
PE.3 PE.3
I/O
I/O
I/O
Feb 15, 2019
Page 98 of 245
Rev 1.01
M2351
Pin Name
EBI_MCLK
SD0_DAT1
SPI3_MISO
SC0_DAT
USCI0_DAT0
QEI0_A
Type
O
MFP
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP13
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP13
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP11
MFP12
MFP13
MFP0
MFP3
MFP5
MFP6
MFP7
MFP8
MFP11
MFP12
Description
EBI external clock output pin.
SD/SDIO0 data line bit 1.
I/O
I/O
I/O
I/O
I
SPI3 MISO (Master In, Slave Out) pin.
Smart Card 0 data pin.
USCI0 data 0 pin.
Quadrature encoder 0 phase A input
EPWM0 channel 4 output/capture input.
BPWM0 channel 1 output/capture input.
General purpose digital I/O pin.
EBI write enable output pin.
SD/SDIO0 data line bit 2.
EPWM0_CH4
BPWM0_CH1
PE.4
I/O
I/O
I/O
O
EBI_nWR
SD0_DAT2
SPI3_CLK
I/O
I/O
O
SPI3 serial clock pin.
PE.4 SC0_RST
Smart Card 0 reset pin.
USCI0_DAT1
QEI0_INDEX
EPWM0_CH3
BPWM0_CH2
PE.5
I/O
I
USCI0 data 1 pin.
Quadrature encoder 0 index input
EPWM0 channel 3 output/capture input.
BPWM0 channel 2 output/capture input.
General purpose digital I/O pin.
EBI read enable output pin.
SD/SDIO0 data line bit 3.
I/O
I/O
I/O
O
EBI_nRD
SD0_DAT3
SPI3_SS
I/O
I/O
O
SPI3 slave select pin.
PE.5 SC0_PWR
USCI0_CTL1
QEI1_B
Smart Card 0 power pin.
I/O
I
USCI0 control 1 pin.
Quadrature encoder 1 phase B input
EPWM0 channel 2 output/capture input.
BPWM0 channel 3 output/capture input.
General purpose digital I/O pin.
SD/SDIO0 clock output pin
EPWM0_CH2
BPWM0_CH3
PE.6
I/O
I/O
I/O
O
SD0_CLK
SPI3_I2SMCLK
I/O
I
SPI3 I2S master clock output pin
Smart Card 0 card detect pin.
USCI0 control 0 pin.
SC0_nCD
PE.6
USCI0_CTL0
I/O
I
UART5_RXD
QEI1_A
UART5 data receiver input pin.
Quadrature encoder 1 phase A input
EPWM0 channel 1 output/capture input.
I
EPWM0_CH1
I/O
Feb 15, 2019
Page 99 of 245
Rev 1.01
M2351
Pin Name
Type
I/O
I/O
I/O
O
MFP
MFP13
MFP0
MFP3
MFP8
MFP11
MFP12
MFP13
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP10
MFP11
MFP12
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP10
MFP11
MFP12
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP10
Description
BPWM0_CH4
PE.7
BPWM0 channel 4 output/capture input.
General purpose digital I/O pin.
SD/SDIO0 command/response pin
UART5 data transmitter output pin.
Quadrature encoder 1 index input
EPWM0 channel 0 output/capture input.
BPWM0 channel 5 output/capture input.
General purpose digital I/O pin.
EBI address bus bit 10.
SD0_CMD
UART5_TXD
QEI1_INDEX
EPWM0_CH0
BPWM0_CH5
PE.8
PE.7
I
I/O
I/O
I/O
O
EBI_ADR10
I2S0_BCLK
SPI2_CLK
O
I2S0 bit clock output pin.
I/O
I/O
O
SPI2 serial clock pin.
USCI1_CTL1
UART2_TXD
EPWM0_CH0
EPWM0_BRAKE0
ECAP0_IC0
TRACE_DATA3
PE.9
USCI1 control 1 pin.
PE.8
UART2 data transmitter output pin.
EPWM0 channel 0 output/capture input.
EPWM0 Brake 0 input pin.
I/O
I
I
Enhanced capture unit 0 input 0 pin.
ETM Trace Data 3 output pin
General purpose digital I/O pin.
EBI address bus bit 11.
O
I/O
O
EBI_ADR11
I2S0_MCLK
SPI2_MISO
USCI1_CTL0
UART2_RXD
EPWM0_CH1
EPWM0_BRAKE1
ECAP0_IC1
TRACE_DATA2
PE.10
O
I2S0 master clock output pin.
SPI2 MISO (Master In, Slave Out) pin.
USCI1 control 0 pin.
I/O
I/O
I
PE.9
UART2 data receiver input pin.
EPWM0 channel 1 output/capture input.
EPWM0 Brake 1 input pin.
I/O
I
I
Enhanced capture unit 0 input 1 pin.
ETM Trace Data 2 output pin
General purpose digital I/O pin.
EBI address bus bit 12.
O
I/O
O
EBI_ADR12
I2S0_DI
I
I2S0 data input pin.
PE.10 SPI2_MOSI
USCI1_DAT0
I/O
I/O
O
SPI2 MOSI (Master Out, Slave In) pin.
USCI1 data 0 pin.
UART3_TXD
UART3 data transmitter output pin.
EPWM0 channel 2 output/capture input.
EPWM0_CH2
I/O
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Pin Name
Type
I
MFP
MFP11
MFP12
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP8
MFP10
MFP11
MFP13
MFP14
MFP0
MFP2
MFP4
MFP5
MFP6
MFP8
MFP10
MFP13
MFP14
MFP0
MFP2
MFP4
MFP5
MFP8
MFP10
MFP11
MFP12
MFP13
MFP0
MFP2
Description
EPWM1_BRAKE0
ECAP0_IC2
TRACE_DATA1
PE.11
EPWM1 Brake 0 input pin.
I
Enhanced capture unit 0 input 2 pin.
ETM Trace Data 1 output pin
General purpose digital I/O pin.
EBI address bus bit 13.
O
I/O
O
EBI_ADR13
I2S0_DO
O
I2S0 data output pin.
SPI2_SS
I/O
I/O
I
SPI2 slave select pin.
USCI1_DAT1
USCI1 data 1 pin.
PE.11 UART3_RXD
UART3 data receiver input pin.
UART1 clear to Send input pin.
EPWM0 channel 3 output/capture input.
EPWM1 Brake 1 input pin.
UART1_nCTS
EPWM0_CH3
EPWM1_BRAKE1
ECAP1_IC2
I
I/O
I
I
Enhanced capture unit 1 input 2 pin.
ETM Trace Data 0 output pin
General purpose digital I/O pin.
EBI address bus bit 14.
TRACE_DATA0
PE.12
O
I/O
O
EBI_ADR14
I2S0_LRCK
O
I2S0 left right channel clock output pin.
SPI2 I2S master clock output pin
USCI1 clock pin.
SPI2_I2SMCLK
I/O
I/O
O
PE.12 USCI1_CLK
UART1_nRTS
EPWM0_CH4
ECAP1_IC1
UART1 request to Send output pin.
EPWM0 channel 4 output/capture input.
Enhanced capture unit 1 input 1 pin.
ETM Trace Clock output pin
General purpose digital I/O pin.
EBI address bus bit 15.
I/O
I
TRACE_CLK
PE.13
O
I/O
O
EBI_ADR15
I2C0_SCL
I/O
O
I2C0 clock pin.
UART4_nRTS
PE.13 UART1_TXD
EPWM0_CH5
EPWM1_CH0
BPWM1_CH5
ECAP1_IC0
UART4 request to Send output pin.
UART1 data transmitter output pin.
EPWM0 channel 5 output/capture input.
EPWM1 channel 0 output/capture input.
BPWM1 channel 5 output/capture input.
Enhanced capture unit 1 input 0 pin.
General purpose digital I/O pin.
EBI address/data bus bit 8.
O
I/O
I/O
I/O
I
PE.14
PE.14
I/O
I/O
EBI_AD8
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Pin Name
UART2_TXD
CAN0_TXD
PE.15
Type
O
MFP
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP12
MFP14
MFP0
MFP2
MFP3
MFP12
MFP14
MFP0
MFP2
MFP3
MFP4
MFP5
MFP10
MFP11
MFP0
MFP2
MFP3
MFP4
MFP10
MFP11
MFP0
MFP2
MFP4
MFP8
MFP10
Description
UART2 data transmitter output pin.
CAN0 bus transmitter output.
General purpose digital I/O pin.
EBI address/data bus bit 9.
UART2 data receiver input pin.
CAN0 bus receiver input.
O
I/O
I/O
I
EBI_AD9
PE.15
UART2_RXD
CAN0_RXD
PF.0
I
I/O
O
General purpose digital I/O pin.
UART1 data transmitter output pin.
I2C1 clock pin.
UART1_TXD
PF.0 I2C1_SCL
BPWM1_CH0
I/O
I/O
O
BPWM1 channel 0 output/capture input.
Serial wired debugger data pin.
General purpose digital I/O pin.
UART1 data receiver input pin.
I2C1 data input/output pin.
ICE_DAT
PF.1
I/O
I
UART1_RXD
PF.1 I2C1_SDA
BPWM1_CH1
ICE_CLK
I/O
I/O
I
BPWM1 channel 1 output/capture input.
Serial wired debugger clock pin.
General purpose digital I/O pin.
EBI chip select 1 output pin.
UART0 data receiver input pin.
I2C0 data input/output pin.
PF.2
I/O
O
EBI_nCS1
UART0_RXD
PF.2 I2C0_SDA
QSPI0_CLK
XT1_OUT
I
I/O
I/O
O
Quad SPI0 serial clock pin.
External 4~24 MHz (high speed) crystal output pin.
BPWM1 channel 1 output/capture input.
General purpose digital I/O pin.
BPWM1_CH1
PF.3
I/O
I/O
O
EBI_nCS0
EBI chip select 0 output pin.
UART0_TXD
PF.3
O
UART0 data transmitter output pin.
I2C0 clock pin.
I2C0_SCL
I/O
I
XT1_IN
BPWM1_CH0
PF.4
External 4~24 MHz (high speed) crystal input pin.
BPWM1 channel 0 output/capture input.
General purpose digital I/O pin.
I/O
I/O
O
UART2_TXD
PF.4 UART2_nRTS
BPWM0_CH5
X32_OUT
UART2 data transmitter output pin.
UART2 request to Send output pin.
BPWM0 channel 5 output/capture input.
External 32.768 kHz crystal output pin.
O
I/O
O
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Pin Name
PF.5
Type
I/O
I
MFP
MFP0
MFP2
MFP4
MFP8
MFP9
MFP10
MFP11
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP10
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP10
MFP0
MFP2
MFP3
MFP4
MFP5
MFP10
MFP0
MFP2
MFP3
MFP4
MFP5
MFP10
Description
General purpose digital I/O pin.
UART2 data receiver input pin.
UART2 clear to Send input pin.
BPWM0 channel 4 output/capture input.
EPWM0 counter synchronous trigger output pin.
External 32.768 kHz crystal input pin.
EADC0 external trigger input.
General purpose digital I/O pin.
EBI address bus bit 19.
UART2_RXD
UART2_nCTS
PF.5 BPWM0_CH4
I
I/O
O
EPWM0_SYNC_OUT
X32_IN
I
EADC0_ST
PF.6
I
I/O
O
EBI_ADR19
SC0_CLK
I2S0_LRCK
SPI0_MOSI
UART4_RXD
EBI_nCS0
TAMPER0
PF.7
O
Smart Card 0 clock pin.
O
I2S0 left right channel clock output pin.
SPI0 MOSI (Master Out, Slave In) pin.
UART4 data receiver input pin.
EBI chip select 0 output pin.
TAMPER detector loop pin 0.
General purpose digital I/O pin.
EBI address bus bit 18.
PF.6
I/O
I
O
I/O
I/O
O
EBI_ADR18
SC0_DAT
I/O
O
Smart Card 0 data pin.
PF.7 I2S0_DO
SPI0_MISO
UART4_TXD
TAMPER1
PF.8
I2S0 data output pin.
I/O
O
SPI0 MISO (Master In, Slave Out) pin.
UART4 data transmitter output pin.
TAMPER detector loop pin 1.
General purpose digital I/O pin.
EBI address bus bit 17.
I/O
I/O
O
EBI_ADR17
SC0_RST
PF.8
O
Smart Card 0 reset pin.
I2S0_DI
I
I2S0 data input pin.
SPI0_CLK
TAMPER2
PF.9
I/O
I/O
I/O
O
SPI0 serial clock pin.
TAMPER detector loop pin 2.
General purpose digital I/O pin.
EBI address bus bit 16.
EBI_ADR16
SC0_PWR
PF.9
O
Smart Card 0 power pin.
I2S0_MCLK
O
I2S0 master clock output pin.
SPI0 slave select pin.
SPI0_SS
I/O
I/O
TAMPER3
TAMPER detector loop pin 3.
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Pin Name
PF.10
Type
I/O
O
MFP
MFP0
MFP2
MFP3
MFP4
MFP5
MFP10
MFP0
MFP2
MFP3
MFP10
MFP13
MFP0
MFP2
MFP3
MFP4
MFP5
MFP13
MFP0
MFP2
MFP3
MFP4
MFP5
MFP13
MFP0
MFP2
MFP3
MFP13
MFP0
MFP2
MFP12
MFP0
MFP2
MFP12
MFP0
Description
General purpose digital I/O pin.
EBI address bus bit 15.
EBI_ADR15
SC0_nCD
I2S0_BCLK
SPI0_I2SMCLK
TAMPER4
PF.11
I
Smart Card 0 card detect pin.
I2S0 bit clock output pin.
PF.10
O
I/O
I/O
I/O
O
SPI0 I2S master clock output pin
TAMPER detector loop pin 4.
General purpose digital I/O pin.
EBI address bus bit 14.
EBI_ADR14
PF.11 SPI2_MOSI
TAMPER5
TM3
I/O
I/O
I/O
I/O
O
SPI2 MOSI (Master Out, Slave In) pin.
TAMPER detector loop pin 5.
Timer3 event counter input/toggle output pin.
General purpose digital I/O pin.
EBI address bus bit 11.
PG.2
EBI_ADR11
SPI2_SS
PG.2
I/O
O
SPI2 slave select pin.
I2C0_SMBAL
I2C0 SMBus SMBALTER pin
I2C1 clock pin.
I2C1_SCL
TM0
I/O
I/O
I/O
O
Timer0 event counter input/toggle output pin.
General purpose digital I/O pin.
EBI address bus bit 12.
PG.3
EBI_ADR12
SPI2_CLK
PG.3
I/O
O
SPI2 serial clock pin.
I2C0_SMBSUS
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C1 data input/output pin.
I2C1_SDA
TM1
I/O
I/O
I/O
O
Timer1 event counter input/toggle output pin.
General purpose digital I/O pin.
PG.4
EBI_ADR13
PG.4
EBI address bus bit 13.
SPI2_MISO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI2 MISO (Master In, Slave Out) pin.
Timer2 event counter input/toggle output pin.
General purpose digital I/O pin.
TM2
PG.9
PG.9 EBI_AD0
BPWM0_CH5
PG.10
EBI address/data bus bit 0.
BPWM0 channel 5 output/capture input.
General purpose digital I/O pin.
PG.10 EBI_AD1
BPWM0_CH4
PG.11 PG.11
EBI address/data bus bit 1.
BPWM0 channel 4 output/capture input.
General purpose digital I/O pin.
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Pin Name
EBI_AD2
BPWM0_CH3
PG.12
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
MFP
MFP2
MFP12
MFP0
MFP2
MFP12
MFP0
MFP2
MFP12
MFP0
MFP2
MFP12
MFP0
MFP14
MFP15
MFP0
MFP2
MFP3
MFP0
MFP2
MFP3
MFP0
MFP2
MFP3
MFP0
MFP2
MFP3
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
Description
EBI address/data bus bit 2.
BPWM0 channel 3 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 3.
BPWM0 channel 2 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 4.
BPWM0 channel 1 output/capture input.
General purpose digital I/O pin.
EBI address/data bus bit 5.
BPWM0 channel 0 output/capture input.
General purpose digital I/O pin.
Clock Out
PG.12 EBI_AD3
BPWM0_CH2
PG.13
PG.13 EBI_AD4
BPWM0_CH1
PG.14
PG.14 EBI_AD5
BPWM0_CH0
PG.15
PG.15 CLKO
EADC0_ST
PH.4
I
EADC0 external trigger input.
General purpose digital I/O pin.
EBI address bus bit 3.
I/O
O
PH.4 EBI_ADR3
SPI1_MISO
PH.5
I/O
I/O
O
SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
EBI address bus bit 2.
PH.5 EBI_ADR2
SPI1_MOSI
PH.6
I/O
I/O
O
SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
EBI address bus bit 1.
PH.6 EBI_ADR1
SPI1_CLK
I/O
I/O
O
SPI1 serial clock pin.
PH.7
General purpose digital I/O pin.
EBI address bus bit 0.
PH.7 EBI_ADR0
SPI1_SS
I/O
I/O
I/O
I/O
O
SPI1 slave select pin.
PH.8
General purpose digital I/O pin.
EBI address/data bus bit 12.
Quad SPI0 serial clock pin.
Smart Card 2 power pin.
EBI_AD12
QSPI0_CLK
SC2_PWR
PH.8
I2S0_DI
I
I2S0 data input pin.
SPI1_CLK
I/O
O
SPI1 serial clock pin.
UART3_nRTS
I2C1_SMBAL
UART3 request to Send output pin.
I2C1 SMBus SMBALTER pin
O
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Pin Name
Type
I/O
O
MFP
MFP9
MFP10
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP9
MFP10
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP7
MFP8
MFP11
Description
I2C2_SCL
I2C2 clock pin.
UART1_TXD
PH.9
UART1 data transmitter output pin.
General purpose digital I/O pin.
EBI address/data bus bit 13.
Quad SPI0 slave select pin.
Smart Card 2 reset pin.
I2S0 data output pin.
I/O
I/O
I/O
O
EBI_AD13
QSPI0_SS
SC2_RST
I2S0_DO
O
PH.9
SPI1_SS
I/O
I
SPI1 slave select pin.
UART3_nCTS
I2C1_SMBSUS
I2C2_SDA
UART1_RXD
PH.10
UART3 clear to Send input pin.
O
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
I2C2 data input/output pin.
I/O
I
UART1 data receiver input pin.
I/O
I/O
I/O
I
General purpose digital I/O pin.
EBI_AD14
QSPI0_MISO1
SC2_nCD
EBI address/data bus bit 14.
Quad SPI0 MISO1 (Master In, Slave Out) pin.
Smart Card 2 card detect pin.
PH.10
I2S0_LRCK
SPI1_I2SMCLK
UART4_TXD
UART0_TXD
PH.11
O
I2S0 left right channel clock output pin.
SPI1 I2S master clock output pin
UART4 data transmitter output pin.
UART0 data transmitter output pin.
General purpose digital I/O pin.
I/O
O
O
I/O
I/O
I/O
I
EBI_AD15
QSPI0_MOSI1
UART4_RXD
UART0_RXD
EPWM0_CH5
EBI address/data bus bit 15.
Quad SPI0 MOSI1 (Master Out, Slave In) pin.
UART4 data receiver input pin.
PH.11
I
UART0 data receiver input pin.
I/O
EPWM0 channel 5 output/capture input.
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5 BLOCK DIAGRAM
5.1 NuMicro® M2351 Series Block Diagram
Figure 5.1-1 NuMicro® M2351 Block Diagram
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5.2 NuMicro® M2351 Series TrustZone® Architecture
Figure 5.2-1 NuMicro® M2351 Series Cortex®-M23 Architecture
Feb 15, 2019
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6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M23 Core
The NuMicro® M2351 series is embedded with the Cortex® -M23 processor. The Cortex® -M23
processor is a low gate count, two-stage, and highly energy efficient 32-bit RISC processor, which has
an AMBA AHB5 interface supporting Arm® TrustZone® technology, a debug access port supporting
serial wire debug and single-cycle I/O ports. It has an NVIC component and MPU for memory-
protection functionality. The processor also supports Security Extension. Figure 6.1-1 shows the
functional controller of the processor.
MTB AHB
Cortex-M23 processor
Micro Trace
Buffer
(MTB)
MTB
SRAM
interface
Cross
Trigger
Interface
(CTI)
Wakeup
Interrupt
Controller
(WIC)
Nested
Vectored
Interrupt
(NVIC)
Cortex-M23
processor
core
APB
IRQ and power
control interface
Embedded
Trace
Macrocell
(ETM)
ETM
ATB
interface
Memory Protection
Implementation
Defined Attribution
Unit (IDAU)
Security
Attribution
Unit (SAU)
Data
Watchpoint
and Trace
(DWT)
Flash Patch
and
Breakpoint Unit
(FPB)*
Secure
Memory
Protection Unit
(MPU_S)
Non-secure
Memory
Protection Unit
(MPU_NS)
Slave
AHB
interface
Bus matrix
Processor
ROM
table
Single-cycle
I/O port
AHB Master
Configurable
Optional
* Flash Patching is not supported in the Cortex-M23 processor.
Figure 6.1-1 Cortex® -M23 Block Diagram
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Cortex® -M23 processor features:
Arm® v8-M Baseline architecture.
Arm® v8-M Baseline Thumb® -2 instruction set that combines high code density with 32-bit
performance.
Support for single-cycle I/O access.
Power control optimization of system components.
Integrated sleep modes for low power consumption.
Optimized code fetching for reduced Flash and ROM power consumption.
32-bit Single cycle Hardware multiplier.
32-bit Hardware divider.
Deterministic, high-performance interrupt handling for time-critical applications.
Deterministic instruction cycle timing.
Support for system level debug authentication.
Support for Arm® Debug Interface Architecture ADIv5.1 Serial Wire Debug (SWD).
ETM for instruction trace.
Separated privileged and unprivileged modes.
Security Extension supporting a Secure and a Non-secure state.
Protected Memory System Architecture (PMSAv8) Memory Protection Units (MPUs) for both
Secure and Non-secure states.
Security Attribution Unit (SAU).
SysTick timers for both Secure and Non-secure states.
A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor with up
to 240 interrupts.
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6.2
Arm® TrustZone®
The Arm® TrustZone® can be considered as a physical partition that divides the microcontroller into
Secure (Trusted) and Non-secure (Non-trusted) worlds according to memory address. The secure
world is an isolated execution environment, code and data loaded inside are protected and cannot be
accessed from Non-secure world. Code running at secure world is called secure code that can access
both secure and non-secure memories and peripherals; while code running at non-secure world is
called non-secure code that can only access non-secure memories and peripherals.
Figure 6.2-1 shows an example of a system divided into the secure world and non-secure world.
Green blocks indicate secure components, Red blocks indicate non-secure components and white
ones are both/either secure and/or non-secure accessible. When the core processor is in secure state
(left side of the figure), it belongs to secure world, which has its own MSP, PSP and VTOR registers
and can access the green, red, white blocks. Contrarily, when the core processor is in non-secure
state (right side of the figure), it belongs to non-secure world, which also has its own MSP, PSP and
VTOR registers, but, it can only access red and white blocks so that non-secure world components are
not able to impact secure world.
Secure World
Non-Secure World
SRAM
SRAM
CRYPTO
UART
I2C
CRYPTO
UART
I2C
Core
Processor
Core
Processor
SRAM
SRAM
MSP / PSP
VTOR
MSP / PSP
VTOR
DMA
Timer
RTC
DMA
Timer
RTC
Flash
Flash
Flash
Flash
SPI
SPI
NVIC
SCU
NVIC
SCU
By function calls
GPIO
GPIO
AHB5 / APB Bus
AHB5 / APB Bus
Figure 6.2-1 Secure World View and Non-secure World View on a Chip
In order to support TrustZone® to set up both secure world and non-secure world, Cortex® -M23
provides three security attributes. Each memory address is assigned with one of the security
attributes. These security attributes are listed below.
Non-secure (NS)
Addresses used for non-secure memory or non-secure peripheral's registers.
Secure (S)
Addresses used for secure memory or secure peripheral's registers.
Non-secure Callable (NSC)
A special type of secure memory region which can contain SG instructions. The SG
instruction allows a non-secure function calls to a secure function.
The address space partitioning is completed by Implementation Define Attribution Unit (IDAU) and
Security Attribution Unit (SAU) together. The IDAU is non-programmable, which defines static partition
of address space. The static partition specifies the default security attribute of a memory region. In
contrast with IDAU, the SAU is programmable which provides dynamic partition of address space. The
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dynamic partition is given by software programmer to specify the security attribute of a memory region.
The core processor is in secure state when executing instructions from secure memory. Otherwise, the
core processor is in non-secure state when executing instructions from non-secure memory. For
setting IDAU and SAU, refer to sections “Implementation Defined Attribution Unit (IDAU)” and “Security
Attribution Unit (SAU)” in “System Manager” chapter for more details.
The security attribute of Flash, SRAM and peripherals are assigned by TrustZone® related control
units. The NSCBA register in FMC is used to divide the APROM into two parts, one is secure and the
other is non-secure. The security attribute of SRAM and peripherals are assigned by programming
Secure Configuration Unit (SCU).
Whenever being reset, the M2351 is in secure state, that is, the core processor, Flash, SRAM and
peripherals are all in secure state. Therefore, the system boots in secure state. The boot code is
responsible to set up TrustZone® related control units in M2351 to partition address space and assign
non-secure resources that can be directly accessed from non-secure world.
6.2.1
Address Space Partition
The SAU and IDAU are the control units used to define security attribute of memory addresses. The
IDAU defines default partition of secure and non-secure addresses, while the SAU is programmable to
change the security attribute defined by IDAU.
6.2.1.1 Implementation Define Attribution Unit (IDAU)
The IDAU uses address bit 28 to distinguish between secure and non-secure world, i.e. the bit 28 of a
secure address is always 0, and the bit 28 of a non-secure address is always 1, except regions above
0xE000_0000.
The partition of 4GB address space is shown as Figure 6.2-2. Each region consists of a secure (bit 28
is 0) and a non-secure (bit 28 is 1) sub-regions, the size of a sub-region is 256MB. In order to store
entry functions for non-secure code, the security attribute of secure SRAM region is assigned as non-
secure callable (NSC). Similarly, the secure “Code” region is assigned as NSC but has an exception at
first 2 KB area. This first 2 KB area is defined as secure only to avoid accidental SG instruction after
power on.
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Region
Range
Memory Attribute
0xFFFFFFFF
0xF0000000
Exempted
Exempted
Non-secure
Secure
Device
System
0xE0000000
0xD0000000
0xC0000000
0xB0000000
0xA0000000
0x90000000
External Device
External RAM
Non-secure
Secure
Non-secure
Secure
0x80000000
0x70000000
Non-secure
Secure
0x60000000
0x50000000
Non-secure
Secure
Device
SRAM
Code
0x40000000
0x30000000
Non-secure
Secure+ NSC
Non-secure
Secure + NSC
0x20000000
0x10000000
0x00000800
0x00000000
Secure
0x00000000
Memory Partition
Figure 6.2-2 The 4 GB Memory Map Divided Into Secure and Non-secure Regions by IDAU
6.2.1.2 Security Attribution Unit (SAU)
The SAU is a MPU-like function unit inside Cortex® -M23. Up to 8 memory regions can be defined by
programming control registers of SAU.
Memory regions are enabled individually by programming SAU_RNR, SAU_RBAR and SAU_RLAR.
The memory region is enabled once RENABLE (SAU_RLAR[0]) is set to 1, and the security attribute is
defined by NSC (SAU_RLAR[1]):
NSC = 0, the memory region is Non-secure (NS).
NSC = 1, the memory region is Secure and Non-secure callable (NSC).
The security attribute of each memory region defined by SAU is either NS or NSC. Those memory
addresses not defined by SAU regions are treated as Secure. After all memory regions are set,
SAU_CTRL[0] should be set to 1 to enable SAU.
Both IDAU and SAU define the security attribute of a memory address. If the definitions are different,
the more secure attribute will be used for the memory address. The priority of the security attribute
from high to low is Secure > NSC > NS.
When the core processor attempts to access a target, e.g. a memory or peripheral register, the
security attribute of the target is decided by checking IDAU and SAU. If the core processor is non-
secure but the target is secure, a HardFault exception will be generated. Because non-specified
memory addresses are treated as secure, non-secure memory regions need to be defined for the core
processor to access non-secure memory and non-secure peripheral registers. Besides, whole secure
code and SRAM regions are defined as NSC by IDAU. The size of NSC regions can be changed
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according to the NSC entry functions included in application code. The example usage of SAU regions
is shown as Figure 6.2-3.
Not used
Not used
Not used
Not used
7
6
5
4
Allow core processor to successfully access
Non-secure peripherals
Define Non-secure peripheral region
(0x50000000~0x5FFFFFFF)
3
2
1
Define Non-secure SRAM region
(0x30000000~0x3FFFFFFF)
Allow core processor to successfully access
Non-secure SRAM
Define Non-secure code region
(0x10000000~0x1FFFFFFF)
Allow core processor to successfully access
Non-secure Flash
Define Non-secure callable area in
Secure code region
0
Figure 6.2-3 Typical Setting of SAU
Security Attribute Configuration
6.2.2
The previous section describes how to divide the address space of core processor view into secure
world and non-secure world. For M2351, the memory and peripherals can be assigned to either secure
or non-secure world during system initialization. The M2351 is designed to start execution in secure
state after reset. In other words, core processor and all system resources including Flash, SRAM and
peripherals are secure after reset. Then, the system initialization code may change some parts of the
system resources to be non-secure.
6.2.2.1 Security Attribute Configuration of Flash
The M2351 Flash memory is split into a number of different regions such as LDROM, APROM and
others. Most of the Flash regions are always secure and cannot be changed. The only one can be
changed is the APROM region. Non-secure APROM region is set by programming a special control
register, NSCBA (Non-secure base address). The NSCBA[23:0] indicates the starting address of non-
secure APROM and its value should be aligned with a Flash page size. The secure APROM region
starts from address 0x0 and ends at NSCBA[23:0] – 1, while the non-secure APROM region ranges
from NSCBA[23:0] to the end of APROM. For setting NSCBA, refer to FMC section for more details.
6.2.2.2 Security Attribute Configuration of SRAM and Peripherals
The secure state of SRAM blocks and all peripherals can be configured by Security Configuration Unit
(SCU), which contains a set of control registers used to assign the security attribute. Besides, the SCU
monitors bus transfers to detect unsecure access. The unsecure access is one of the following
conditions.
Non-secure master peripheral tries to access a secure address (address bit 28 = 0).
Secure code or secure master peripheral uses non-secure address (address bit 28 = 1) to
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access secure SRAM or peripheral.
When an unsecure access is detected, SCU blocks the access operation and generates a secure
alarm interrupt.
For more details, refer to the Security Configuration Unit (SCU) chapter.
6.2.3
System Address Map and Access Scheme
In the M2351 series, the Flash, SRAM and most peripherals can be assigned to be Secure or Non-
secure, but each of them can be accessed through either Secure address or Non-secure address
depending on its security attribute configuration. Core processor and master peripherals should use
correct address to access resources, i.e. the secure resource should be accessed by using secure
address. Similarly, the non-secure resource should be accessed by using non-secure address.
6.2.3.1 Permanent Secure Peripherals
The security attribute of some peripherals are always secure and cannot be changed for safety and
security. If necessary, the secure code should manage and provide functions for non-secure code to
access these peripherals. Table 6.2-1 lists these secure peripherals.
Peripheral
SYS
Function
Address
System Control Registers
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4002_F000 – 0x4002_FFFF
0x4004_0000 – 0x4004_0FFF
0x4005_0000 – 0x4005_0FFF
CLK
Clock Control Registers
NMI
NMI Control Registers
PDMA0
FMC
Peripheral DMA 0 Control Registers
Flash Memory Control Registers
Security Configuration Unit Registers
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
SCU
WDT
TMR01
Table 6.2-1 Peripherals and Regions that are Always Secure
6.2.3.2 Secure Address vs. Non-secure Address
A memory or a peripheral register may have secure and non-secure address in system address map,
but the memory or register only responds to the address that is consistent with its security attribute.
The different access modes of secure and non-secure target are illustrated in Figure 6.2-4.
Suppose that SRAM block 0, 2, and 4 are in secure state, they will respond to an access when
address bit 28 is 0 (secure address), but will not respond to an access with address bit 28 is 1 (non-
secure address). In this example, SRAM block 1 and 3 are in non-secure state. Hence, these blocks
will only respond to an access when the address bit 28 is 1.
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SRAM Block 4
0x200XXXXX
inaccessible
Secure address
range
SRAM Block 2
inaccessible
SRAM Block 0
The same SRAM Memory which
contains secure and non-secure
blocks
inaccessible
SRAM Block 3
0x300XXXXX
Non-secure address
range
inaccessible
SRAM Block 1
Secure Region
inaccessible
Non-secure Region
Figure 6.2-4 Example of SRAM Divided Into Secure Block and Non-secure Block
6.2.3.3 Valid Access vs. Invalid Access
When core processor or a master peripheral is trying to access (read or write) a memory or register,
the result depends on the following conditions.
Non-secure code or master peripheral is not allowed to access a secure memory or
register.
A memory or register only responds to the related address which is consistent with its
security attribute.
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Secure
FMC
(NSCB
A)
SAU
(a)
(b-1)
(c-1)
Cortex-M23
Flash
IDAU
(
b
Non-secure
-
2
)
)
1
-
CPU bus
e
(
(c-2)
Secure
SRAM
Master
peripheral
(d)
(e-2)
SCU
Non-secure
(
c
-
2
)
(
e
-
Secure
3
)
Non-secure
Peripherals
Non-secure
Secure
Non-secure
AHB/APB Bus
Figure 6.2-5 Checking Point of Accesses
Figure 6.2-5 illustrates how the above conditions are checked by TrustZone® related control units.
When the core processsor tries to fetch instructions or access data, the security attribute of the core
processor and target address are verified by SAU and IDAU (refer to (a)). If the core processor is in
non-secure state and target address is secure, a hard fault exception will be generated. The other
cases will go to next checkpoints (refer to (b-1) and (b-2)). If the non-secure code tries to read/write a
secure memory or register, the access will be blocked and a secure violation interrupt (SCU interrupt)
can be generated. If a secure code uses non-secure address to access a secure memory or register,
the operation has no effect. (refer to (c-1) and (c-2))
When a master peripheral tries to read/write a memory or register, the SCU will verify the access (refer
to (d)). When a non-secure master peripheral wants to access a secure memory or register, the
access will be blocked and a secure violation interrupt (SCU interrupt) can be generated. If a secure
master peripheral uses non-secure address to read/write a secure memory or register, the operation
has no effect.
The responses of the accesses from the core processor and master peripherals follow the rule called
memory access policy, which is described in the “Memory Access Policy (MAP)” section of “Security
Configuration Unit (SCU)” chapter.
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6.3
System Manager
Overview
6.3.1
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.3.2
Reset
The system reset can be issued by one of the events listed below. These reset event flags can be read
from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset (POR)
– Low level on the nRESET pin
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– System Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M23 core only by writing 1 to CPURST (SYS_IPRST0[1])
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Glitch Filter
32 us
nRESET
VDD
~50k ohm
@3.3v
PORMASK(SYS_PORCTL0[15:0])
Power-on
Reset
POROFF(SYS_PORCTL1[15:0])
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
System Reset
SYSRESETREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.3-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M23 only; the other reset sources will reset Cortex® -M23 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.3-1.
Reset Sources
POR
NRESET
WDT
LVR
BOD
Lockup
CHIP
SYSTEM CPU
Register
SYS_RSTSTS
Bit 0 = 1
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[18:16])
BODRSTEN
(SYS_BODCTL[3])
SYS_SRAMPCTL
SYS_SRAMPPCT
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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LXTEN
0x0
0x1
0x3
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
-
0x1
0x1
(CLK_APBCLK0[0])
WDTSEL
0x3
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
CLK_PLLCTL
0x000D_44 -
0A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PDMSEL
0x0
-
(CLK_PMUCTL [2:0])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
Reload
from
CONFIG0
-
-
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
BL
(FMC_ISPCTL[16])
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG0
-
-
-
-
(FMC_ISPSTS[2])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
Reload
base
CONFIG0
on base on base on base on
on
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
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Other Peripheral
Registers
Reset Value
Reset Value
-
FMC Registers
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.3-1 Reset Value of Registers
6.3.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Figure 6.3-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
32 us
0.2 VDD
32 us
nRESET Reset
Figure 6.3-2 nRESET Reset Waveform
6.3.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is ready
for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a
POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.3-3
shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.3-3 Power-on Reset (POR) Waveform
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6.3.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.3-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.3-4 Low Voltage Reset (LVR) Waveform
6.3.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[18:16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.3-5 shows the Brown-out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.3-5 Brown-out Detector (BOD) Waveform
6.3.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to
check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.3.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.3.2.7 CPU Reset, CHIP Reset and System Reset
The CPU Reset means only Cortex® -M23 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The System Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
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LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the System Reset.
6.3.3 Power Modes and Wake-up Sources
The NuMicro® M2351 series has power manager unit to support several operating modes for saving
power. Table 6.3-2 lists all power modes in the NuMicro® M2351 series.
Mode
CPU Operating Maximum
Speed
LDO_CAP Clock Disable
(V)
(MHz)
Normal mode
Turbo mode
48MHz
1.20
1.26
All clocks are disabled by control register.
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
and
and
64MHz
All clocks are disabled by control register.
CLK_AHBCLK,
CLK_APBCLK1.
CLK_APBCLK0
Idle mode
CPU enter Sleep mode
keep
keep
Only CPU clock is disabled.
Power-down mode (PD)
CPU enters Deep Sleep mode
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Fast Wake-up Power-down CPU enters Deep Sleep mode
mode (FWPD)
keep
0.96
0.9
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Low
leakage
Power-down CPU enters Deep Sleep mode
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
mode
(LLPD)
Ultra Low leakage Power-down CPU enters Deep Sleep mode
mode
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
(ULLPD)
Standby Power-down mode
(SPD)
Power off
Power off
Floating Only LIRC/LXT still enable for RTC function and
wake-up timer usage.
Deep Power-down mode
(DPD)
Floating Only LIRC/LXT still enable for RTC function and
wake-up timer usage.
Table 6.3-2 Power Mode Table
Each power mode has different entry setting and leaving condition. Table 6.3-3 shows the entry setting
for each power mode. When chip power-on, chip is running in normal mode. User can enter each
mode by setting SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT[7]) and PDMSEL (CLK_PMUCTL[2:0])
and execute WFI instruction.
Register/Instruction
Mode
SLEEPDEEP PDEN
PDMSEL
CPU Run WFI Instruction
(SCR[2])
(CLK_PWRCTL[7]) (CLK_PMUCTL[2:0])
Normal mode
Idle mode
0
0
1
0
0
1
0
0
0
NO
YES
YES
Power-down mode
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Low leakage Power-down mode
1
1
1
1
1
3
YES
YES
Ultra Low leakage Power-down
mode
Fast Wake-up Power-down mode
Standby Power-down mode
Deep Power-down mode
1
1
1
1
1
1
2
4
6
YES
YES
YES
Table 6.3-3 Power Mode Entry Setting Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.3-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all clocks
stop except LXT and LIRC. SRAM
content be retained by setting
SYS_SRAMPCTL and
SYS_SRAMPPCT.
Entry Condition
Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable and
system reset released
power down enable and executes
WFI instruction.
Wake-up Sources
N/A
All interrupts
EINT, GPIO, UART, USBD, USBH,
OTG, CAN, BOD, WDT, SDH,
Timer, I²C, USCI, RTC and ACMP.
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.3-4 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, HIRC48, LXT, LIRC, HCLK,
PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFI
Wake-up events
occur
Power-down Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
Idle Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK ON
LXT, LIRC ON
Flash Halt
Flash Halt
Figure 6.3-6 Power Mode State Machine
1. LXT ON or OFF depends on software setting in normal mode.
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2. LIRC ON or OFF depends on software setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
6. If UART clock source is selected as LXT and LXT is on.
Power-Down Mode
Power-Down Mode
Normal Mode
Idle Mode
(PD/FWPD/LLPD/ULLPD)
(SPD/DPD)
HXT
HIRC
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
Halt
Halt
HIRC48
LXT
Halt
Halt
ON/OFF1
ON/OFF2
Halt
ON/OFF1
ON/OFF2
Halt
LIRC
PLL
CPU
Halt
Halt
HCLK/PCLK
FLASH
TIMER
WDT
Halt
Halt
Halt
Halt
ON/OFF3
ON/OFF4
ON/OFF5
ON/OFF6
Halt
Halt
Halt
RTC
ON/OFF5
Halt
UART
Others
Halt
Table 6.3-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
EINT, GPIO, UART, USBD, USBH, OTG, CAN, BOD, ACMP, WDT, SDH, Timer, I²C, USCI, , , RTC.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.3-6 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Power-down mode
PD
Wake-Up
Source
System Can Enter Power-Down Mode Again
Condition*
Wake-Up Condition
LLPD
ULLPD
FWPD
SPD DPD
After software writes
(SYS_BODCTL[4]).
1
to clear BODIF
Brown-out Detector Reset / Interrupt
Brown-out Detector Reset
√
-
-
-
BOD
After software writes
(CLK_PMUSTS[13]) when SPD mode is
1 to clear BODWK
-
√
entered.
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After software writes
(SYS_RSTSTS[3])
1
to clear LVRF
√
-
-
-
LVR
LVR Reset
After software writes
(CLK_PMUSTS[12]) when SPD mode is
entered.
1 to clear LVRWK
-
√
√
After software writes
(SYS_RSTSTS[0]).
1
to clear PORF
√
POR
EINT
GPIO
POR Reset
External Interrupt
GPIO Interrupt
-
-
-
After software write 1 to clear the Px_INTSRC[n]
bit.
√
√
-
-
After software write 1 to clear the Px_INTSRC[n]
bit.
GPIO(PA~P
D) Wake-up
pin
GPxWK(CLK_PMUSTS[11:8]) is cleared when
SPD mode is entered.
rising or falling edge event, 61-pin
rising or falling edge event , 1-pin
Timer Interrupt
-
-
√
-
-
√
-
GPIO(PC.0)
Wake-up pin
PINWK(CLK_PMUSTS[1]) is cleared when DPD
mode is entered.
After software writes
(TIMERx_INTSTS[1])
(TIMERx_INTSTS[0]).
1
to clear TWKF
and TIF
TIMER
√
-
After software writes
(CLK_PMUSTS[1]) when SPD or DPD mode is
entered.
1 to clear TMRWK
Wakeup
timer
Wakeup by wake-up timer time-out
-
√
√
After software writes
(WDT_CTL[5]) (Write Protect).
1
to clear WKF
to clear ALMIF
to clear TICKIF
WDT
WDT Interrupt
Alarm Interrupt
√
√
√
-
-
-
-
-
After software writes
(RTC_INTSTS[0]).
1
1
After software writes
(RTC_INTSTS[1]).
Time Tick Interrupt
Wakeup by RTC alarm
-
-
RTCWK (CLK_PMUSTS[5]) is cleared when
DPD or SPD mode is entered.
√
√
RTC
RTCWK (CLK_PMUSTS[5]) is cleared when
DPD or SPD mode is entered.
Wakeup by RTC tick time
-
√
√
RTCWK (CLK_PMUSTS[5]) is cleared when
DPD or SPD mode is entered.
Wakeup by tamper event
nCTS wake-up
-
√
-
-
-
-
-
-
-
√
-
-
-
-
-
-
-
After software writes
(UARTx_WKSTS[0]).
1
1
to clear CTSWKF
to clear DATWKF
√
√
√
√
√
√
√
After software writes
(UARTx_WKSTS[1]).
RX Data wake-up
After software writes 1 to clear RFRTWKF
(UARTx_WKSTS[2]).
UART
Received FIFO Threshold Wake-up
RS-485 AAD Mode Wake-up
After software writes 1 to clear RS485WKF
(UARTx_WKSTS[3]).
Received FIFO Threshold Time-out
Wake-up
After software writes 1 to clear TOUTWKF
(UARTx_WKSTS[4]).
After software writes
(UUART_WKSTS[0]).
1
to clear WKF
CTS Toggle
Data Toggle
USCI UART
After software writes
(UUART_WKSTS[0]).
1
to clear WKF
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After software writes
(UI2C_WKSTS[0]).
1
to clear WKF
Data toggle
Address match
√
√
√
√
-
-
-
-
-
-
-
-
USCI I2C
After software writes 1 to clear WKAKDONE
(UI2C_PROTSTS[16], then writes 1 to clear
WKF (UI2C_WKSTS[0]).
After software writes
(USPI_WKSTS[0]).
1
to clear WKF
USCI SPI
I2C
SS Toggle
After software writes 1 to clear WKAKDONE
(I2C_WKSTS[1]). Then software writes 1 to
clear WKIF(I2C_WKSTS[0]).
Address match wake-up
1.Remote wake-up
2.Pulg in wake-up
After software writes
(USBD_INTSTS[0]).
1
to clear BUSIF
USBD
√
√
-
-
-
-
1.After
write
1
to
to
to
clear
clear
clear
RHSC
RHSC
RHSC
(HcInterruptStatus[7]).
1.Connection detected
2.Disconnect detected
3.Remote-wakeup
2.After write
(HcInterruptStatus[7]).
3.After write
1
USBH
OTG
1
(HcInterruptStatus[7]). and port suspended.
After
software
writes
1
to
set
ID pin state be change
√
√
-
-
-
-
WKEN(OTG_CTL[5]).
After software writes
(ACMP_STATUS[8])
(ACMP_STATUS[9]).
1
to clear WKIF0
and WKIF1
Comparator Power-Down Wake-Up
Interrupt
ACMP
ACMPWK (CLK_PMUSTS[3]) is cleared when
SPD mode is entered.
ACMPO status change
-
√
-
After software writes 0 to clear WAKUP_STS
(CAN_WU_STATUS[0])
CAN
SDH
Incoming Data Toggle
Card detection
√
√
-
-
-
-
Clear CDIF0 (SDH_INTSTS[8]) after SDH wake-
up.
Table 6.3-6 Condition of Entering Power-down Mode Again
6.3.4
System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which provides
a fixed 1.2V or 1.26V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
RTC power from VBAT provides the power for RTC and 80 bytes backup registers.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which should be
located close to the corresponding pin. Analog power (AVDD) should be the same voltage level of the
digital power (VDD). If system enters SPD mode SW_SPD switch needs to be turned off, and internal
voltage regulator can be set to LDO mode or DC-DC converter mode. Figure 6.3-7 shows the power
distribution.
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Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
VDDIO
12-bit ADC
12-bit DAC
IO Cell
IO Cell
AVDD
AVSS
0.9V
Temp. Sensor
Analog Comparator
RTC &
80 bytes
backup register
32 KHz
LIRC
Oscillator
RTCLDO
3.3V à0.9V
LVDR
(Low Voltage Reset, Brown-out
Detector)
SRAM
Digital Logic
SRAM
(32K)
Flash
POR12
(64K)
SW_SPD
1.2V/1.26V
LDO_CAP
2uF
Power Management
and Holder Logic
12 MHz HIRC
Oscillator
48 MHz HIRC
Oscillator
PLL
TRNG
GPIO except
PF.4~PF.11 and
PA.0~PA.5
4~24 MHz
crystal
oscillator
Power
On
Control
10 kHz
LIRC
Oscillator
3.3V à
1.2V/1.26V
Regulator
USB 1.1
OTG
PHY
PF.2
PF.3
POR33
IO Cell
M2351 Power Distribution
Figure 6.3-7 Power Distribution Diagram
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6.3.5
Bus Matrix
M4
PDMA1
M3
M2
M1
M0
USBH
Crypto
SDH0
PDMA0
Cortex-M23
S0
S1
S2
S3
S4
S5
S6
SRAM0
(32 KB)
SRAM1
(64 KB)
APB0
Peripheral
APB1
Peripheral
AHB
Peripheral
FLASH
EBI
Figure 6.3-2 M2351 Bus Martix Architecture Diagram
Refer to Figure 6.3-2. This chip uses Advanced Microcontroller Bus Architecture (AMBA) protocol to
implement system bus. The system has five masters and seven slaves, in which a different master can
communicate with a different slave at the same time through Bus Matrix. The Cortex® -M23 core
processor acts as the master in Bus Matrix, located on M0 to communicate with any slaves through
Bus Matrix. PDMA0 and PDMA1 are Peripheral Direct Memory Access and act as the master in Bus
Matrix, respectively located on M1 and M4, which can communicate with any slaves through Bus
Matrix. SDH0 and Crypto share the same master bandwidth located on M2. USBH acts as the master
role in Bus Matrix and is located on M3. The slave AHB Peripheral is the Advanced High-performance
Bus (AHB) controller, and any master can communicate with any AHB peripheral through Bus Matrix.
6.3.6
System Memory Map
This chip provides 4G-byte addressing space. The memory locations assigned to each on-chip
controllers are shown in Table 6.3-7. The detailed register definition, memory space, and programming
will be described in the following sections for each on-chip peripheral. This chip implement Arm® Trust
Zone Architecture as well as memory alias technique, secure code and non-secure code can run
together on the chip well, while both have different memory view. Secure code view is shown in Table
6.2-1 and non-secure code view is shown in Table 6.2-2.
The NuMicro® M2351 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0003_FFFF
0x0000_0000 – 0x0007_FFFF
FLASH_BA
FLASH_BA
FLASH Memory Space (256 KB)
FLASH Memory Space (512 KB)
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0x2000_0000 – 0x2000_7FFF
0x2000_8000 – 0x2001_7FFF
0x6000_0000 – 0x6FFF_FFFF
SRAM0_BA
SRAM1_BA
EXTMEM_BA
SRAM Memory Space (32 KB)
SRAM Memory Space (64 KB)
External Memory Space (256 MB)
Secure Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_9000 – 0x4000_9FFF
0x4000_C000 – 0x4000_CFFF
0x4000_D000 – 0x4000_DFFF
0x4001_0000 – 0x4001_0FFF
0x4001_8000 – 0x4000_8FFF
0x4003_1000 – 0x4003_1FFF
0x4003_2000 – 0x4003_4FFF
0x4002_F000 – 0x4002_FFFF
SYS_BA
System Control Registers (always secure)
Clock Control Registers (always secure)
NMI Control Registers (always secure)
GPIO Control Registers
CLK_BA
NMI_BA
GPIO_BA
PDMA0_BA
USBH_BA
FMC_BA
SDH0_BA
EBI_BA
Peripheral DMA 0 Control Registers (always secure)
USB Host Control Registers
Flash Memory Control Registers (always secure )
SDHOST0 Control Registers
External Bus Interface Control Registers
Peripheral DMA 1Control Registers (secure or non-secure)
CRC Generator Registers
PDMA1_BA
CRC_BA
CRPT_BA
SCU_BA
Cryptographic Accelerator Registers
Secure Configuration Unit Registers (always secure)
Secure APB Controllers Space (0x4004_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4004_7000 – 0x4004_7FFF
0x4004_8000 – 0x4004_8FFF
0x4004_D000 – 0x4004_DFFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4005_A000 – 0x4005_AFFF
0x4005_B000 – 0x4005_BFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4006_2000 – 0x4006_2FFF
0x4006_3000 – 0x4006_3FFF
WDT_BA
Watchdog Timer Control Registers (always secure)
Real Time Clock (RTC) Control Register
RTC_BA
EADC_BA
ACMP01_BA
DAC_BA
Enhanced Analog-Digital-Converter (EADC) Control Registers
Analog Comparator 0/ 1 Control Registers
DAC Control Registers
I2S0_BA
I2S0 Interface Control Registers
OTG Control Registers
OTG_BA
TMR01_BA
TMR23_BA
EPWM0_BA
EPWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
Timer0/Timer1 Control Registers (always secure)
Timer2/Timer3 Control Registers
EPWM0 Control Registers
EPWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
Quad SPI0 Control Registers
SPI0 Control Registers
SPI1_BA
SPI1 Control Registers
SPI2_BA
SPI2 Control Registers
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0x4006_4000 – 0x4006_4FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4007_3000 – 0x4007_3FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x4008_2000 – 0x4008_2FFF
0x4009_0000 – 0x4009_0FFF
0x4009_1000 – 0x4009_1FFF
0x4009_2000 – 0x4009_2FFF
0x400A_0000 – 0x400A_0FFF
0x400B_0000 – 0x400B_0FFF
0x400B_1000 – 0x400B_1FFF
0x400B_4000 – 0x400B_4FFF
0x400B_5000 – 0x400B_5FFF
0x400B_9000 – 0x400B_9FFF
0x400C_0000 – 0x400C_0FFF
0x400D_0000 – 0x400D_0FFF
0x400D_1000 – 0x400D_1FFF
SPI3_BA
SPI3 Control Registers
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
Reserved
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
Reserved
Reserved
I2C0_BA
Reserved
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
I2C2_BA
I2C2 Control Registers
SC0_BA
Smartcard Host 0 Control Registers
Smartcard Host 1 Control Registers
Smartcard Host 2 Control Registers
CAN0 Bus Control Registers
QEI0 Control Registers
QEI1 Control Registers
ECAP0 Control Registers
ECAP1 Control Registers
TRNG Control Registers
USB Device Control Register
USCI0 Control Registers
USCI1 Control Registers
SC1_BA
SC2_BA
CAN0_BA
QEI0_BA
QEI1_BA
ECAP0_BA
ECAP1_BA
TRNG_BA
USBD_BA
USCI0_BA
USCI1_BA
Table 6.3-7 Address Space Assignments for On-Chip Controllers
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Address Space
Token
Controllers
Non-secure Peripheral Controllers Space (0x5000_0000 – 0x500F_FFFF)
0x5000_4000 – 0x5000_4FFF
0x5000_9000 – 0x5000_9FFF
0x5000_D000 – 0x5000_DFFF
0x5001_0000 – 0x5001_0FFF
0x5001_8000 – 0x5000_8FFF
0x5003_1000 – 0x5003_1FFF
0x5003_2000 – 0x5003_4FFF
GPIO_BA
USBH_BA
SDH0_BA
EBI_BA
GPIO Control Registers
USB Host Control Registers
SDHOST0 Control Registers
External Bus Interface Control Registers
Peripheral DMA 1Control Registers (secure or non-secure)
CRC Generator Registers
PDMA1_BA
CRC_BA
CRPT_BA
Cryptographic Accelerator Registers
Non-secure APB Controllers Space (0x5004_0000 ~ 0x500F_FFFF)
0x5004_1000 – 0x5004_1FFF
0x5004_3000 – 0x5004_3FFF
0x5004_5000 – 0x5004_5FFF
0x5004_7000 – 0x5004_7FFF
0x5004_8000 – 0x5004_8FFF
0x5004_D000 – 0x5004_DFFF
0x5005_1000 – 0x5005_1FFF
0x5005_8000 – 0x5005_8FFF
0x5005_9000 – 0x5005_9FFF
0x5005_A000 – 0x5005_AFFF
0x5005_B000 – 0x5005_BFFF
0x5006_0000 – 0x5006_0FFF
0x5006_1000 – 0x5006_1FFF
0x5006_2000 – 0x5006_2FFF
0x5006_3000 – 0x5006_3FFF
0x5006_4000 – 0x5006_4FFF
0x5007_0000 – 0x5007_0FFF
0x5007_1000 – 0x5007_1FFF
0x5007_2000 – 0x5007_2FFF
0x5007_3000 – 0x5007_3FFF
0x5007_4000 – 0x5007_4FFF
0x5007_5000 – 0x5007_5FFF
0x5007_4000 – 0x5007_4FFF
0x5007_5000 – 0x5007_5FFF
0x5008_0000 – 0x5008_0FFF
RTC_BA
Real Time Clock (RTC) Control Register
EADC_BA
ACMP01_BA
DAC_BA
Enhanced Analog-Digital-Converter (EADC) Control Registers
Analog Comparator 0/ 1 Control Registers
DAC Control Registers
I2S0_BA
I2S0 Interface Control Registers
OTG Control Registers
OTG_BA
TMR23_BA
EPWM0_BA
EPWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
Timer2/Timer3 Control Registers
EPWM0 Control Registers
EPWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
Quad SPI0 Control Registers
SPI0 Control Registers
SPI1_BA
SPI1 Control Registers
SPI2_BA
SPI2 Control Registers
SPI3_BA
SPI3 Control Registers
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
Reserved
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
Reserved
Reserved
Reserved
I2C0_BA
I2C0 Control Registers
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0x5008_1000 – 0x5008_1FFF
0x5008_2000 – 0x5008_2FFF
0x5009_0000 – 0x5009_0FFF
0x5009_1000 – 0x5009_1FFF
0x5009_2000 – 0x5009_2FFF
0x500A_0000 – 0x500A_0FFF
0x500B_0000 – 0x500B_0FFF
0x500B_1000 – 0x500B_1FFF
0x500B_4000 – 0x500B_4FFF
0x500B_5000 – 0x500B_5FFF
0x500B_9000 – 0x500B_9FFF
0x500C_0000 – 0x500C_0FFF
0x500D_0000 – 0x500D_0FFF
0x500D_1000 – 0x500D_1FFF
I2C1_BA
I2C1 Control Registers
I2C2_BA
I2C2 Control Registers
SC0_BA
Smartcard Host 0 Control Registers
Smartcard Host 1 Control Registers
Smartcard Host 2 Control Registers
CAN0 Bus Control Registers
QEI0 Control Registers
SC1_BA
SC2_BA
CAN0_BA
QEI0_BA
QEI1_BA
ECAP0_BA
ECAP1_BA
TRNG_BA
USBD_BA
USCI0_BA
USCI1_BA
QEI1 Control Registers
ECAP0 Control Registers
ECAP1 Control Registers
TRNG Control Registers
USB Device Control Register
USCI0 Control Registers
USCI1 Control Registers
Table 6.3-2 Non-secure Address Space Assignments for On-Chip Controllers
6.3.7
Implementation Defined Attribution Unit (IDAU)
6.3.7.1 Overview
The Arm® v8-M has the new feature called TrustZone® , which adds an additional security state to allow
full isolation of two security levels. The processor security state is decided by the memory definition.
For example, processor is in Secure state when the code is excuted in the Secure region. The memory
map security state will be defined by the combination of:
Internal Security Attribution Unit (SAU)
Implementation Defined Attribution Unit (IDAU)
These attribution units define the memory space into four type regions:
Secure Region: contains Secure program code or data
Non-secure Callable Region (NSC): contains entry functions for Non-secure programs to
access Secure functions
Non-secure Region: contains Non-secure program code or data
Exempt Region: exempt region will be exempted from security check
For each memory region defined by the SAU and IDAU has a region number generated by the SAU or
by the IDAU. Region number is used for determine a group of memory share the same security
attribute. Overlapping region numbers are not allow. For testing security attributes and region
numbers, a new instruction “TT” (Test Target) is introduced. By using a TT instruction on the start and
end addresses of the memory range, and identifying that both reside in the same region number, user
can determine that the memory range is located entirely in same space. To be more specific, please
refer to the Arm® v8-M Architecture Reference Manual. The M2351 IDAU memory map attributions and
corresponding region numbers are shown in Figure 6.3-8. The address from 0xE000_0000 to
0xFFFF_FFFF is marked as exempt regions because the behavior of the address is fixed, so their
security attributes don’t control by the SAU or IDAU.
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Region num
15
0xFFFF_FFFF
0xF000_0000
0xE000_0000
0xD000_0000
0xC000_0000
0xB000_0000
0xA000_0000
0x9000_0000
0x8000_0000
0x7000_0000
0x6000_0000
0x5000_0000
0x4000_0000
0x3000_0000
0x2000_0000
Device
System
Exempt
Exempt
14
13
12
11
10
9
NON-SECURE
SECURE
External Device
External RAM
NON-SECURE
SECURE
NON-SECURE
SECURE
8
NON-SECURE
SECURE
7
6
NON-SECURE
SECURE
5
Device
SRAM
4
NON-SECURE
NSC
3
2
NON-SECURE
1
16
0
0x1000_0000
0x0000_0800
0x0000_0000
Code
NSC
SECURE
Figure 6.3-8 IDAU Memory Map
6.3.7.2 IDAU Block Diagram
The IDAU block diagram is shown in Figure 6.3-9. IDAU is security attribute unit connected outside of
the processor. Both SAU and IDAU are responsible to response the security property of the address
from processor, the only difference is that the memory security attribute of the SAU is configurable and
the IDAU is fixed. After the processor compare the security property of the IDAU and SAU, it will take
the highest security attribute applied. The hierarchy of security levels from high to low is: Secure >
NSC > Non-secure.
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processor
CPU
address
SAU
IDAU
Other
Master
Other
Master
MPU MPU
Bus Matrix
Slave
Slave
Slave
Slave
Slave
Slave
Figure 6.3-9 IDAU Block Diagram
SRAM Memory Orginization
6.3.8
This chip supports embedded SRAM with a total of 96 Kbytes size and the SRAM organization is
separated into two banks: SRAM bank0 and SRAM bank1. The first bank has 32 Kbytes address
space and the second bank has 64Kbyte address space. These two banks address space can be
accessed simultaneously. The SRAM bank0 supports parity error check to make sure the chip is
operating more stable.
Supports total 96 Kbytes SRAM
Supports byte / half word / word write
Supports fixed 32 Kbytes SRAM bank0 for independent access
Supports parity error check function for SRAM bank0
Supports oversize response error
AHB interface
SRAM decoder
controller
SRAM bank0
SRAM bank1
AHB interface
SRAM decoder
controller
Figure 6.3-10 SRAM Block Diagram
Figure 6.3-11 shows the SRAM organization. There are two SRAM banks. The bank0 is addressed to
32 Kbytes and the bank1 is addressed to 64 Kbytes. The bank0 address space is from 0x2000_0000
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to 0x2000_7FFF(Secure) or 0x3000_0000 to 0x3000_7FFF(Non-secure). The bank1 address space is
from 0x2000_8000 to 0x2001_7FFF(Secure) or 0x3000_8000 to 0x3001_7FFF(Non-secure). The
address between 0x2001_8000 to 0x2FFF_FFFF(Secure) and 0x3001_8000 to 0x3FFF_FFFF(Non-
secure) is illegal memory space and chip will enter hardfault if CPU accesses these illegal memory
addresses.
0x3FFF_FFFF
0x2FFF_FFFF
Reserved
Reserved
0x3001_8000
0x3001_7FFF
0x2001_8000
0x2001_7FFF
64 Kbytes
64 Kbytes
SRAM bank1
SRAM bank1
0x3000_8000
0x3000_7FFF
0x2000_8000
0x2000_7FFF
32 Kbytes
32 Kbytes
SRAM bank0
SRAM bank0
0x3000_0000
0x2000_0000
96 Kbytes device
(secure)
96 Kbytes device
(non-secure)
Figure 6.3-11 SRAM Memory Organization
SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the parity
error checking mechanism is dynamic operating. As parity error occurs, the PERRIF
(SYS_SRAMSTS[0]) will be asserted to 1 and the SYS_SRAMEADR register will recode the address
with the parity error. Chip will enter interrupt when SRAM parity error occurs if PERRIEN
(SYS_SRAMICTL[0]) is set to 1. When SRAM parity error occurs, chip will stop detecting SRAM parity
error until user writes 1 to clear the PERRIF(SYS_SRAMSTS[0]) bit.
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SRAM Power Control
SRAM bank0 and bank1 have marco retention and power shut down function. Each SRAM marco can
be configured to retention or power shut down mode independently by SRAMxPMn
(SYS_SRAMPCTL[23:8], x=0-1 n=0-3). When chip entering power-down, each SRAM marco will enter
retention
or
power
shut
down
or
keep
operation
mode
depended
on
SRAMxPMn(SYS_SRAMPCTL[23:8], x=0-1 n=0-3).When chip power down wake up, SRAM marco will
wake up from retention or power shut down mode. User must identify which SRAM marco that CPU
first accessed for saving power down wake up time by STACK(SYS_SRAMPCTL[1:0]).
Figure 6.3-12 shows the SRAM marco number in bank0 and bank1. When chip power down wake up,
the first wake up SRAM marco is depened on STACK (SYS_SRAMPCTL[1:0]), the rest SRAM marcos
wake up in the order of marco number, from SRAM marco0 to SRAM marco7.
0x3001_7FFF
0x3001_4000
0x2001_7FFF
0x2001_4000
16 Kbytes
SRAM Marco 7
16 Kbytes
SRAM Marco 7
16 Kbytes
16 Kbytes
SRAM Marco 6
SRAM Marco 6
0x3001_0000
0x3000_C000
0x2001_0000
0x2000_C000
16 Kbytes
SRAM Marco 5
16 Kbytes
SRAM Marco 5
16 Kbytes
16 Kbytes
SRAM Marco 4
SRAM Marco 4
0x3000_8000
0x3000_6000
0x2000_8000
0x2000_6000
8 Kbytes
SRAM Marco 3
8 Kbytes
SRAM Marco 3
8 Kbytes
8 Kbytes
SRAM Marco 2
SRAM Marco 2
0x3000_4000
0x2000_4000
8 Kbytes
8 Kbytes
SRAM Marco 1
SRAM Marco 1
0x3000_2000
0x3000_0000
0x2000_2000
0x2000_0000
8 Kbytes
SRAM Marco 0
8K byte
SRAM Marco 0
96 Kbytes device
(secure)
96 Kbytes device
(non-secure)
Figure 6.3-12 SRAM Marco Organization
6.3.9
Auto Trim
This chip supports auto-trim function: the HIRC trim (12 MHz RC oscillator, 48 MHz RC oscillator),
according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode, to
automatically get accurate HIRC output frequency, 0.25 % deviation within all temperature ranges.
For instance, the system needs an accurate 12 MHz clock. In such case, if neither using PLL as the
system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_TCTL12M[10] reference clock selection) to “1”, set FREQSEL (SYS_TCTL12M[1:0] trim
frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK
(SYS_TISTS12M[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate
within 0.25% deviation.
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In another case, the system needs an accurate 48 MHz clock. In such case, if neither using PLL as the
system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_TCTL48M[10] reference clock selection) to “1”, set FREQSEL (SYS_TCTL48M[1:0] trim
frequency selection) to “01”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK
(SYS_TISTS48M[8] HIRC48 frequency lock status) “1” indicates the HIRC output frequency is
accurate within 0.25% deviation.
6.3.10 System Timer (SysTick)
The Cortex® -M23 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M23 Technical Reference Manual”
and “Arm® v8-M Architecture Reference Manual”.
6.3.11 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the
stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC
from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable
the Configuration and Control Register. Any other user mode access causes a bus fault. You can
access all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC
registers are located within the SCS (System Control Space). All NVIC registers and system debug
registers are little-endian regardless of the endianness state of the processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-3 for each interrupt; a higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
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6.4 Clock Controller
6.4.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN (CLK_PWRCTL[7]) and core executes the WFI
instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to
leave Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal (HXT), 48MHz internal high speed RC oscillator (HIRC48) and 12 MHz internal high
speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure 6.4-1 to Figure
6.4-3 show the clock generator and the overview of the clock source control.
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CPU
CRC
1/32
1/16
1/8
101
100
011
010
001
000
CAN0
ECAP0
I2C0
CRYPTO
EBI
12 MHz
HIRC
HXT
1
0
PCLK0
PLL FOUT
4~24 MHz
FMC
1/4
I2C2
CLK_PLLCTL[19]
GPIO
ISP
1/2
I2S0
EPWM0
BPWM0
QEI0
PDMA0
PDMA1
SDH0
SRAM
USBH
12 MHz
48 MHz
CLK_PCLKDIV[2:0]
HIRC
111
SC0
HIRC48
LIRC
PLL
101
HCLK
SC2
10 kHz
1/(HCLKDIV+1)
011
010
001
QSPI0
SPI1
PLLFOUT
32.768 kHz
4~24 MHz
LXT
SPI3
HXT
000
TMR0
TMR1
UART0
UART2
UART4
USBD
USCI0
WDT
CLK_CLKSEL0[2:0]
12 MHz
HIRC
1/2
1/2
1/2
111
011
010
001
000
HCLK
HCLK
HXT
LXT
CPUCLK
1
0
4~24 MHz
SysTick
32.768 kHz
1/32
1/16
1/8
101
100
011
010
001
000
4~24 MHz
HXT
ACMP
DAC
SYST_CTRL[2]
PCLK1
EADC
DSRC
ECAP1
I2C1
CLK_CLKSEL0[5:3]
PLLFOUT
1/4
1/2
USBH
USBD
OTG
1/(USBDIV+1)
OTG
CLK_PCLKDIV[6:4]
EPWM1
BPWM1
QEI1
RTC
HIRC
11
10
01
00
SC1
HCLK
PLL
SPI0
1/(SDH0DIV+1)
SDH0
SPI2
HXT
SPI4
TMR2
TMR3
TRNG
UART1
UART3
UART5
USCI1
CLK_CLKSEL0[21:20]
1/(DSRCDIV+1)
DSRC
HIRC
10 kHz
1/2048
10 kHz
1/2048
LIRC
11
10
01
LIRC
11
10
WWDT
WDT
HCLK
HCLK
32.768 kHz
LXT
CLK_CLKSEL1[31:30]
CLK_CLKSEL1[1:0]
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.4-1 Clock Generator Global View Diagram (1/3)
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12 MHz
10 kHz
HIRC
LIRC
111
101
EPWM 0
EPWM 1
PCLK0
TMR 0
TMR 1
TM0~TM1
PCLK0
TM0/TM1
PCLK0
LXT
011
010
PCLK1
PCLK0
PCLK1
32.768 kHz
4~24 MHz
001
000
BPWM 0
BPWM 1
HXT
CLK_CLKSEL1 [10: 8]
CLK_CLKSEL1 [14:12]
12 MHz
HIRC
12 MHz
PCLK0
111
101
HIRC
11
10
10 kHz
LIRC
PCLK0
QSPI0
TMR 2
TMR 3
TM2~TM3
TM2/TM3
PLLFOUT
4~24 MHz
011
010
SPI1
SPI3
01
00
PLLFOUT
HXT
PCLK1
PCLK1
32.768 kHz
LXT
001
000
4~24 MHz
HXT
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
CLK_CLKSEL2[13:12]
CLK_CLKSEL1 [18:16]
CLK_CLKSEL1 [22:20]
12 MHz
HIRC
11
10
PCLK1
SPI0
SPI2
SPI4
12 MHz
HIRC
PCLK1
11
10
01
00
PLLFOUT
PLLFOUT
01
00
32.768 kHz
LXT
1/(UART0DIV+1)
UART 0
UART 1
4~24 MHz
HXT
PLLFOUT
PLL
1/(UART1DIV+1)
4~24 MHz
HXT
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[11:10]
CLK_CLKSEL2[15:14]
CLK_CLKSEL1[25:24]
CLK_CLKSEL1[27:26]
12 MHz
HIRC
12 MHz
HIRC
11
1/(UART2DIV+1)
1/(UART3DIV+1)
1/(UART4DIV+1)
1/(UART5DIV+1)
UART 2
UART 3
UART 4
UART 5
11
10
32.768 kHz
LXT
10
01
00
PCLK0
PCLK0
PLLFOUT
PLL
1/(SC0DIV+1)
1/(SC2DIV+1)
SC0
SC2
PLLFOUT
4~24 MHz
PLL
01
00
HXT
4~24 MHz
HXT
CLK_CLKSEL3[25:24]
CLK_CLKSEL3[27:26]
CLK_CLKSEL3[29:28]
CLK_CLKSEL3[31:30]
CLK_CLKSEL3[1:0]
CLK_CLKSEL3[5:4]
12 MHz
HIRC
HCLK
HCLK
32.768 kHz
LXT
12 MHz
11
HIRC
11
10
PCLK1
10
01
00
PCLK1
Clock Output
1/(SC1DIV+1)
SC1
PLLFOUT
4~24 MHz
PLL
01
00
4~24 MHz
HXT
HXT
CLK_CLKSEL1[29:28]
CLK_CLKSEL3[3:2]
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and
stable.
Figure 6.4-2 Clock Generator Global View Diagram (2/3)
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LIRC
LXT
1
0
12 MHz
HIRC
PCLK0
PLL
11
10
RTC
1
0
LIRC32k
extLXT
PCLK0
I2S0
PLLFOUT
4~24 MHz
01
00
HXT
CLK_CLKSEL3[8]
RTC_LXTCTL[7]
CLK_CLKSEL3[17:16]
PCLK1
1/(EADCDIV+1)
EADC
12MHz
HIRC
FMC
BOD
10kHz
LIRC
1
0
LIRC32k
extLXT
32.768kHz
TRNG
Note:
RTC_LXTCTL[7]
Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6.4-3 Clock Generator Global View Diagram (3/3)
6.4.2
Clock Generator
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected from
external 4~24 MHz external high speed crystal (HXT) or 12 MHz internal high speed
oscillator (HIRC)
12 MHz internal high speed RC oscillator (HIRC)
48 MHz internal high speed RC oscillator (HIRC48)
10 kHz internal low speed RC oscillator (LIRC)
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LIRC32KEN (RTC_LXTCTL[0])
Internal 32 kHz
Oscillator
(LIRC32k)
C32KS(RTC_LXTCTL[7])
LXTEN (CLK_PWRCTL[1])
X32_IN
LXT
1
0
External 32.768
kHz Crystal
(extLXT)
X32_OUT
XT1_IN
HXTEN (CLK_PWRCTL[0])
HXT
External 4~24
MHz Crystal
(HXT)
PLLSRC (CLK_PLLCTL[19])
XT1_OUT
0
1
PLL FOUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal 12 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
HIRC48EN (CLK_PWRCTL[18])
Internal 48 MHz
Oscillator
HIRC48
(HIRC48)
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6.4-4 Clock Generator Block Diagram
Each of these clock sources has certain stable time to wait for clock operating at stable frequency.
When clock source is enabled, a stable counter start counting and correlated clock stable index.
That is, HXTSTB (CLK_STATUS[0]), LXTSTB (CLK_STATUS[1]), PLLSTB (CLK_STATUS[2]),
LIRCSTB (CLK_STATUS[3]), HIRCSTB (CLK_STATUS[4]), HIRC48STB (CLK_STATUS[6]),
EXTLXTSTB (CLK_STATUS[8]) and LIRC32STB(CLK_STATUS[9]) these bits are set to 1 after the
stable counter value reaches a defined value.
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System and peripheral can use the clock as its operating clock only when correlate clock stable index
is set to 1. The clock stable index will be auto cleared when the clock source (HXTEN
(CLK_PWRCTL[0]), LXTEN (CLK_PWRCTL[1]), LIRC32KEN (RTC_LXTCTL[0]), HIRCEN
(CLK_PWRCTL[2]), LIRCEN (CLK_PWRCTL[3]), HIRC48EN (CLK_PWRCTL[18]) and PD
(CLK_PLLCTL[16])) are disabled.
Besides, the clock stable index of HXT, HIRC, HIRC48 and PLL will be auto cleared when chip enters
power-down and clock stable counter will re-count after chip wake-up if correlate clock is enabled.
6.4.3
System Clock and SysTick Clock
The system clock has 6 clock sources which are generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.4-5.
HCLKSEL
(CLK_CLKSEL0[2:0])
111
100
HIRC
CPUCLK
HCLK
HIRC48
CPU
AHB
011
010
001
000
LIRC
1/(HCLKDIV+1)
PLLFOUT
PCLK0
PCLK1
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
LXT
HXT
CPU in Power Down Mode
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.4-5 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop being
detected on the following condition: system clock source comes from HXT or system clock source
comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the HXTFIF
(CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is set to 1.
HXT clock source stable flag, HXTSTB (CLK_STATUS[0]), will be cleared if HXT stops when using
HXT fail detector function. User can try to recover HXT by disable HXT and enable HXT again to
check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover
to oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.4-6.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.4-6 HXT Stop Protect Procedure
HIRC
HCLK
1/2
1/2
1/2
other
011
010
001
000
CPUCLK
1
0
HXT
LXT
HXT
SysTick
SYST_CTRL[2]
CLK_CLKSEL0[5:3]
Note:
Before clock switching, both the pre-selected and newly selected clock sources must
be turned on and stable.
Figure 6.4-7 SysTick Clock Control Block Diagram
The clock source of SysTick in processor can use CPU clock or external clock (SYST_CTRL[2]). If
using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock source switch
depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown
in Figure 6.4-7.
6.4.4
Peripherals Clock
Each peripheral clock has its own clock source selection. Refer to the CLK_CLKSEL1, CLK_CLKSEL2
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and CLK_CLKSEL3 register.
6.4.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 10 kHz internal low speed RC oscillator (LIRC) clock
– 32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.4.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by 16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore, there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN
(CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and
stays in low state.
If DIV1EN(CLK_CLKOCTL[5]) set to 1, the clock output clock (CLKO_CLK) will bypass power-of-2
frequency divider. The output divider clock will be output to CLKO pin directly.
When entering Power-down mode, clock output does not out put clock even if the CKO clock source is
LXT.
Enable
divide-by-2 counter
FREQSEL
(CLK_CLKOCTL[3:0])
CLKOEN
(CLK_CLKOCTL[4])
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
1/2
1/22
1/23
…...
1/215 1/216
CLK1HZEN
(CLK_CLKOCTL[6])
0000
0001
:
CLKOCKEN
(CLK_APBCLK0[6])
16 to 1
MUX
HIRC
11
0
1
:
0
1
1110
CLKO
HCLK
10
1111
LXT
01
HXT
00
RTCSEL(CLK_CLKSEL3[8])
CLKOSEL (CLK_CLKSEL1[29:28])
LIRC
LXT
0
1
1 Hz clock from RTC
/32768
Note:
Before clock switching, both the pre-selected and newly selected clock sources must be turned on and
stable.
Figure 6.4-8 Clock Output Block Diagram
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6.5 Security Configuration Unit (SCU)
6.5.1 Overview
Security configuration unit is designed for Arm® TrustZone® , and used to configure the security
attribution of SRAM, GPIO and all other peripherals. SCU also collects AHB slaves’ security violation
response and generates SCU interrupt. When non-secure master tries to access SCU, SCU will
response AHB bus error and generate SCU interrupt. The AHB bus error will cause system hardfault, if
the master is the core processor. SCU is also equipped with a timer to monitor the duration of the core
processor in non-secure state.
Note: SCU accepts secure access only.
Note: For details on Arm® TrustZone® , refer to the section “Arm® TrustZone® ”
6.5.2
Features
Configure SRAM’s security attribution block by block
Configure GPIOs’ security attribution port by port
Configure peripherals’ security attribution
Generate secure violation interrupt
Equipped with a 24-bit timer as a non-secure state monitor
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6.6 True Random Number Generator (TRNG)
6.6.1 Overview
The True Random Number Generator (TRNG) is used to generate the randomness by extracting
from physical phenomena.
6.6.2
Features
Generates 800 random bits per second
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6.7 Flash Memeory Controller (FMC)
6.7.1 Overview
The FMC is equipped with dual-bank on-chip embedded Flash (BANK0 and BANK1) for application.
Both BANK0 and BANK1 have 64/128/256 Kbytes space. Thus, the total size of Application ROM
(APROM) is 128/256/512 Kbytes. A User Configuration block provides for system initiation in BANK0.
A 4 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function in BANK0. A 2
Kbytes one-time-program ROM (OTP) is used for recording one-time-program data in BANK1. A 32K
Secure Bootloader is used to check boot code integrity and authenticity, and consists of native ISP
functions. A 4KB cache with zero wait cycle is used to improve Flash access performance. This chip
also supports In-Application-Programming (IAP) function. User switches the code executing without
chip reset after the embedded Flash is updated.
6.7.2
Features
Supports dual-bank Flash macro for safe firmware upgrade
Supports 128/256/512 Kbytes application ROM (APROM)
Supports 4 Kbytes loader ROM (LDROM)
Supports 4 XOM (Execution Only Memory) regions to conceal user program in APROM.
Supports 16 bytes User Configuration block to control system initiation
Supports 3 Kbytes one-time-program ROM (OTP)
Supports 2 Kbytes page erase for all embedded Flash
Supports block erase and bank erase for APROM, except XOM regions.
Supports two level locks for protecting secure region and non-sec region.
Supports Secure Bootloader with native In-System-Programming (ISP) functions
Supports Secure Boot function for check boot code integrity and authenticity
Supports Security Key protection function for APROM, LDROM, User Configuration block
and KPROM protection
Supports 32-bit/64-bit and multi-word Flash programming function
Supports fast Flash programming verification function
Supports CRC32 checksum calculation function
Supports Flash all one verification function
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory
Supports cache memory to improve Flash access performance and reduce power
consumption
Supports auto-tuning Flash access cycle function to optimize the Flash access
performance
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6.8 General Purpose I/O (GPIO)
6.8.1 Overview
This chip has up to 107 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 107 pins are arranged in 8 ports named as PA, PB, PC, PD, PE, PF, PG
and PH. PA, PB and PE has 16 pins on port. PC has 14 pins on port. PD has 15 pins on port. PF has
12 pins on port. PG has 10 pins on port. PH has 8 pins on port. Each of the 107 pins is independent
and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]).
6.8.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
Improve access efficiency by using single cycle IO bus.
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6.9
PDMA Controller (PDMA)
Overview
6.9.1
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
There are two PDMA controller PDMA0 and PDMA1. PDMA0 is secure PDMA, PDMA1 can be
configured as secure or non-secure PDMA. Each PDMA controller has a total of 8 channels and each
channel can perform transfer between memory and peripherals or between memory and memory.
6.9.2
Features
Supports 2 PDMA controller PDMA0 and PDMA1, PDMA0 is secure PDMA, PDMA1 can
be configured as secure or non-secure PDMA.
Supports 8 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and USB, UART, USCI, SPI, EPWM, I2C, I2S, Timer, ADC, and DAC
request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
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6.10 Timer Controller (TMR)
6.10.1 Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
The timer controller also provides four PWM generators. Each PWM generator supports two PWM
output channels in independent mode and complementary mode. The output state of PWM output pin
can be control by pin mask, polarity and break control, and dead-time generator.
6.10.2 Features
6.10.2.1 Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
PWM, EADC, DAC and PDMA function
Supports internal capture triggered while internal ACMP output signal transition
Supports Inter-Timer trigger mode
Supports event counting source from internal USB SOF signal
6.10.2.2 PWM Function Features
Supports maximum clock frequency up to maximum PCLK
Supports independent mode for PWM generator with two output channels
Supports complementary mode for PWM generator with paired PWM output channel
– 12-bit dead-time insertion with 12-bit prescale
Supports 12-bit prescale from 1 to 4096
Supports 16-bit PWM counter
– Up, down and up-down count operation type
– One-shot or auto-reload counter operation mode
Supports mask function and tri-state enable for each PWM output pin
Supports brake function
– Brake source from pin, analog comparator and system safety events (clock failed,
Brown-out detection, SRAM parity error and CPU lockup)
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– Brake pin noise filter control for brake source
– Edge detect brake source to control brake state until brake status cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM zero point, period point, up-count compared or down-count compared point
events
– Brake condition happened
Supports trigger EADC on the following events:
– PWM zero point, period, zero or period point, up-count compared or down-count
compared point events
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6.11 Watchdog Timer (WDT)
6.11.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.11.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz
or LXT.
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6.12 Window Watchdog Timer (WWDT)
6.12.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.12.2 Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.13 Real Time Clock (RTC)
6.13.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.13.2 Features
Supports external power pin V BAT.
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.
Optional support 1/128 second HZCNT in RTC_TIME and RTC_TALM.
Supports Leap Year indication in RTC_LEAPYEAR register.
Supports Day of the Week counter in RTC_WEEKDAY register.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
Supports Daylight Saving Time software control in RTC_DSTCTL.
Supports up 3 pairs dynamic loop tamper pin or 6 individual tamper pin.
Built-in LXT frequency monitor .
Supports 80 bytes spare registers and tamper pins detection to clear the content of these
spare registers.
Supports Flash mass erase operate will also clear the 80 bytes spare registers content.
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6.14 EPWM Generator and Capture Timer (EPWM)
6.14.1 Overview
The chip provides two EPWM generators － EPWM0 and EPWM1. Each EPWM supports 6 channels
of EPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
EPWM counter with 16-bit comparator. The EPWM counter supports up, down and up-down counter
types. EPWM uses comparator compared with counter to generate events. These events use to
generate EPWM pulse, interrupt and trigger signal for EADC/DAC to start conversion.
The EPWM generator supports two standard EPWM output modes: Independent mode and
Complementary mode, which have difference architecture. There are two output functions based on
standard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled under
complementary mode. Complementary mode has two comparators to generate various EPWM pulse
with 12-bit dead-time generator and another free trigger comparator to generate trigger signal for
EADC. For EPWM output control unit, it supports polarity output, independent pin mask and brake
functions.
The EPWM generator also supports input capture function. It supports latch EPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.14.2 Features
6.14.2.1 EPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency
Supports up to two EPWM modules, each module provides 6 output channels
Supports independent mode for EPWM output/Capture input channel
Supports complementary mode for 3 complementary paired EPWM output channel
– Dead-time insertion with 12-bit resolution
– Synchronous function for phase control
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution EPWM counter
– Up, down and up/down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each EPWM pin
Supports brake function
– Brake source from pin, analog comparator and system safety events (clock failed,
SRAM parity error, Brown-out detection and CPU lockup).
– Noise filter for brake source from pin
– Leading edge blanking (LEB) function for brake source from analog comparator
– Edge detect brake source to control brake state until brake interrupt cleared
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– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– EPWM counter matches 0, period value or compared value
– Brake condition happened
Supports trigger EADC/DAC on the following events:
– EPWM counter matches 0, period value or compared value
– EPWM counter match free trigger comparator compared value (only for EADC)
6.14.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for EPWM all channels
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6.15 Basic PWM Generator and Capture Timer (BPWM)
6.15.1 Overview
The chip provides two BPWM generators － BPWM0 and BPWM1. Each BPWM supports 6 channels
of BPWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
BPWM counter with 16-bit comparator. The BPWM counter supports up, down and up-down counter
types, all 6 channels share one counter. BPWM uses the comparator compared with counter to
generate events. These events are used to generate BPWM pulse, interrupt and trigger signal for
EADC to start conversion. For BPWM output control unit, it supports polarity output, independent pin
mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.15.2 Features
6.15.2.1 BPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency.
Supports up to two BPWM modules; each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
– BPWM counter matches 0, period value or compared value
Supports trigger EADC in the following events:
– BPWM counter matches 0, period value or compared value
6.15.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.16 Quadrature Encoder Interface (QEI)
6.16.1 Overview
There are two Quadrature Encoder Interfaces (QEI) QEI controllers in this device. The QEI decodes
speed of rotation and motion sensor information and can be used in any application that uses a
quadrature encoder for feedback.
6.16.2 Features
6.16.2.1 Quadrature Encoder Interface (QEI) Features
Up to two QEI controllers, QEI0 and QEI1.
Two QEI phase inputs, QEA and QEB; One Index input.
A 32-bit up/down Quadrature Encoder Pulse Counter (QEI_CNT)
A 32-bit software-latch Quadrature Encoder Pulse Counter Hold Register
(QEI_CNTHOLD)
A 32-bit Quadrature Encoder Pulse Counter Index Latch Register (QEI_CNTLATCH)
A 32-bit Quadrature Encoder Pulse Counter Compare Register (QEI_CNTCMP) with a
Pre-set Maximum Count Register (QEI_CNTMAX)
One QEI control register (QEI_CTL) and one QEI Status Register (QEI_STATUS)
Four Quadrature encoder pulse counter operation modes
– Support x4 free-counting mode
– Support x2 free-counting mode
– Support x4 compare-counting mode
– Support x2 compare-counting mode
Encoder Pulse Width measurement mode
Input frequency of QEA/QEB/IDX without noise filter must lower than PCLK/4
Input frequency of QEA/QEB/IDX with noise filter must lower than Noise Filter Clk/8
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6.17 Enhanced Input Capture Timer (ECAP)
6.17.1 Overview
This device provides up to two units of Input Capture Timer/Counter whose capture function can detect
the digital edge-changed signal at channel inputs. Each unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.17.2 Features
Up to two Input Capture Timer/Counter units, CAP0 and CAP1.
Each unit has 3 input channels.
Each unit has its own interrupt vector.
Each input channel has its own capture counter hold register.
24-bit Input Capture up-counting timer/counter.
With noise filter in front end of input ports.
Edge detector with three options:
– Rising edge detection
– Falling edge detection
– Both edge detection
Captured events reset and/or reload capture counter.
Supports compare-match function.
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6.18 UART Interface Controller (UART)
6.18.1 Overview
The chip provides six channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs Normal Speed UART and supports flow control function. The UART controller
performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial
conversion on data transmitted from the CPU. Each UART controller channel supports ten types of
interrupts. The UART controller also supports IrDA SIR, LIN and RS-485 function modes and auto-
baud rate measuring function.
6.18.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT.
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART0 /UART1 with LIN function)
– Supports LIN master/slave mode
– Supports programmable break generation function for transmitter
– Supports break detection function for receiver
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
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UART Feature
UART0/ UART1
UART2/UART3/
UART4/ UART5
SC_UART
USCI-UART
TX: 1byte
RX: 2byte
FIFO
16 Bytes
16 Bytes
4 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Imcoming Data Wake-up
√
√
√
√
√
√
-
Received
Data
FIFO
reached
√
√
√
√
-
-
threshold Wake-up
RS-485 Address Match (AAD mode)
Wake-up
-
Auto-Baud Rate Measurement
STOP Bit Length
Word Length
√
√
-
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
1, 2 bit
5, 6, 7, 8 bits
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
Stick Bit
√
√
√
√
√
√
-
-
Note: √= Supported
Table 6.18-1 NuMicro® M2351 Series UART Features
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6.19 Smart Card Host Interface (SC)
6.19.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.19.2 Features
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Three ISO 7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
– Full duplex, asynchronous communications
– Separates receiving / transmitting 4 bytes entry FIFO for data payloads
– Supports programmable baud rate generator
– Supports programmable receiver buffer trigger level
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting EGT (SCn_EGT[7:0])
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1- or 2- stop bit generation
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6.20 I2S Controller (I2S)
6.20.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 16-level depth
FIFO for reading path and writing path respectively are capable of handling 8/16/24/32 bits audio data
sizes. A PDMA controller handles the data movement between FIFO and memory.
6.20.2 Features
Supports Master mode and Slave mode
Capable of handling 8, 16, 24 and 32 bits data sizes in each audio channel
Supports monaural and stereo audio data
Supports I2S protocols: Philips standard, MSB-justified, and LSB-justified data format
Supports PCM protocols: PCM standard, MSB-justified, and LSB-justified data format
PCM protocol supports TDM multi-channel transmission in one audio sample, and the
number of data channel can be set as 2, 4, 6, or 8
Provides two 16-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two PDMA requests, one for transmitting and the other for receiving
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6.21 Serial Peripheral Interface (SPI)
6.21.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
M2351 series contains up to four sets of SPI controllers performing a serial-to-parallel conversion on
data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device. Each SPI controller can be configured as a master or a slave device and supports
the PDMA function to access the data buffer. Each SPI controller also supports I2S mode to connect
external audio CODEC.
6.21.2 Features
SPI Mode
– Up to four sets of SPI controllers
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Supports PDMA transfer
– Supports one data channel half-duplex transfer
– Supports receive-only mode
I2S Mode
– Supports Master or Slave
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Supports two PDMA requests, one for transmitting and the other for receiving
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6.22 Quad Serial Peripheral Interface (QSPI)
6.22.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The M2351 series contains one QSPI controller performing a serial-to-parallel conversion on
data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access
the data buffer.
6.22.2 Features
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports receive-only mode
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6.23 I2C Serial Interface Controller (I2C)
6.23.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are three sets of I2C controllers which support Power-down wake-up function.
6.23.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to three I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports High speed mode 3.4Mbps
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing and 10-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
Supports Bus Management (SM/PM compatible) function
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6.24 USCI - Universal Serial Control Interface Controller (USCI)
6.24.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.24.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
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6.25 USCI – UART Mode
6.25.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the system.
6.25.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.26 USCI - SPI Mode
6.26.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USCI_CTL[2:0]) = 0x1
This SPI protocol can operate as master or Slave mode by setting the SLAVE (USCI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0, 1
Figure 6.26-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0, 1
Figure 6.26-2 SPI Slave Mode Application Block Diagram
6.26.2 Features
Supports Master or Slave mode operation (the maximum frequency -- Master = fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
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Supports Word Suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.27 USCI - I2C Mode
6.27.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on the
SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.27-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.27-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (USCI_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode .
6.27.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.28 Controller Area Network (CAN)
6.28.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.28.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
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6.29 Secure Digital Host Controller (SDH)
6.29.1 Overview
The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a
DMA (Direct Memory Access) function for SD to exchange data between system memory and shared
buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SDHOST controller can
support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory
and cards.
6.29.2 Features
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Supports single DMA channel.
Supports hardware Scatter-Gather function.
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC card.
Completely asynchronous design for Secure Digital with two clock domains, HCLK and
Engine clock, note that frequency of HCLK should be higher than the frequency of
peripheral clock.
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6.30 External Bus Interface (EBI)
6.30.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.30.2 Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports address bus and data bus separate mode
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6.31 USB 1.1 Device Controller (USBD)
6.31.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 1 Kbytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to
write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the
effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device plug-
in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register (USBD_EPSTS0 and USBD_EPSTS1) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the
SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
6.31.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBDET, USB and
BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 1 Kbytes buffer size
Provides remote wake-up capability
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6.32 USB 1.1 Host Controller (USBH)
6.32.1 Overview
This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller
Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to manage
the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data
transfer, collecting status and activity of USB bus, providing power control and detecting over current
of attached USB devices.
6.32.2 Features
Compliant with Universal Serial Bus (USB) Specification Revision 1.1.
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports an integrated Root Hub.
Supports a USB host port shared with USB device (OTG function).
Supports port power control and port over current detection.
Supports DMA for real-time data transfer.
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6.33 USB On-The-Go (OTG)
6.33.1 Overview
The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host
controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 2.0
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID-dependent or OTG Device mode defined in USBROLE (SYS_USBPHY[1:0]). In Host-
only mode, USB frame acts as USB host. USB frame can support both full-speed and low-speed
transfer. In Device-only mode, USB frame acts as USB device. USB frame only supports full-speed
transfer. In ID-dependent mode, USB frame can be USB Host or USB device depending on USB_ID
pin state. In OTG device mode, the role of USB frame depends on the definition of OTG specification.
USB frame only supports full-speed transfer when OTG device acts as a peripheral.
6.33.2 Features
Built in USB PHY
Configurable to operate as:
– Host-only
– Device-only
– ID-dependent: The role of USB frame is only dependent on USB_ID pin value--as USB
Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not support HNP or SRP
protocol.
– OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is low) or B-
device (USB_ID pin is high). Support HNP and SRP protocols.
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6.34 CRC Controller (CRC)
6.34.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.34.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.35 Cryptographic Accelerator (CRYPTO)
6.35.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG)
core and supports AES, DES/TDES, SHA and ECC algorithms.
The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation.
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB, OFB,
CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode.
The DES/TDES accelerator is an implementation fully compliant with the DES and Triple DES
encryption/decryption algorithm. The DES/TDES accelerator supports ECB, CBC, CFB, OFB, and
CTR mode.
The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224, SHA-256, and
SHA-384.
The ECC accelerator is an implementation fully compliant with elliptic curve cryptography by using
polynomial basis in binary field and prime filed.
6.35.2 Features
PRNG
– Supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation
AES
– Supports FIPS NIST 197
– Supports SP800-38A and addendum
– Supports 128, 192, and 256 bits key
– Supports both encryption and decryption
– Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode
– Supports key expander
DES
– Supports FIPS 46-3
– Supports both encryption and decryption
– Supports ECB, CBC, CFB, OFB, and CTR mode
TDES
– Supports FIPS NIST 800-67
– Implemented according to the X9.52 standard
– Supports two keys or three keys mode
– Supports both encryption and decryption
– Supports ECB, CBC, CFB, OFB, and CTR mode
SHA
– Supports FIPS NIST 180, 180-2
– Supports SHA-160, SHA-224, SHA-256, and SHA-384
ECC
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– Supports both prime field GF(p) and binary filed GF(2m)
– Supports NIST P-192, P-224, P-256, P-384, and P-521
– Supports NIST B-163, B-233, B-283, B-409, and B-571
– Supports NIST K-163, K-233, K-283, K-409, and K-571
– Supports point multiplication, addition and doubling operations in GF(p) and GF(2m)
– Supports modulus division, multiplication, addition and subtraction operations in GF(p)
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6.36 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.36.1 Overview
The chip contains one 12-bit successive approximation analog-to-digital converter (SAR ADC
converter) with 16 external input channels and 3 internal channels. The ADC converter can be started
by software trigger, EPWM0/1 triggers, BPWM0/1 triggers, timer0~3 overflow pulse triggers, ADINT0,
ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0_ST) input signal.
6.36.2 Features
Analog input voltage range: 0~ VREF (Max to 3.6V)
Reference voltage from VREF pin
12-bit resolution and 10-bit accuracy is guaranteed
Up to 16 single-end analog external input channels or 8 pair differential analog input
channels
Up to 3 internal channels: band-gap voltage (VBG), temperature sensor (VTEMP), and
Battery power (VBAT
)
Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses
Maximum ADC clock frequency is 64 MHz
Up to 3.76 MSPS conversion rate
Configurable ADC internal sampling time.
12-bit, 10-bit, 8-bit, 6-bit configurable resolution.
Supports calibration and load calibration words capability.
Supports internal reference voltage VREF: 1.6V, 2.0V, 2.5V, and 3.0V.
Supports three power saving modes:
– Deep Power-down mode
– Power-down mode
– Standby mode
Up to 19 sample modules
– Each of sample modules which is configurable for ADC converter channel
EADC_CH0~15 and trigger source
– Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap
voltage, temperature sensor, and battery power (VBAT
– Double buffer for sample control logic module 0~3
– Configurable sampling time for each sample module
)
– Conversion results are held in 19 data registers with valid and overrun indicators
An ADC conversion can be started by:
– Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18)
– External pin EADC0_ST
– Timer0~3 overflow pulse triggers
– ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
– EPWM/BPWM triggers
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Supports PDMA transfer
Conversion Result Monitor by Compare Mode
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6.37 Digital to Analog Converter (DAC)
6.37.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12- or
8-bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a
voltage output buffer that can be used to reduce output impendence and drive external loads directly
without having to add an external operational amplifier.
6.37.2 Features
Analog output voltage range: 0~AVDD.
Supports 12- or 8-bit output mode.
Rail to rail settle time 8us.
Supports up to two 12-bit 1 MSPS voltage type DAC.
Reference voltage from internal reference voltage (INT_VREF), VREF pin.
DAC maximum conversion updating rate 1 MSPS.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger, including Timer0~3, EPWM0, EPWM1, and
external trigger pin to start DAC conversion.
Supports PDMA mode.
Supports group mode of synchronized update capability for two DACs.
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6.38 Analog Comparator Controller (ACMP)
6.38.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.38.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Up to two rail-to-rail analog comparators
Supports hysteresis function
– Supports programmable hysteresis window: 0mV, 10mV, 20mV and 30mV
Supports wake-up function
Supports programmable propagaion speed and low power consumption
Selectable input sources of positive input and negative input
ACMP0 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 4 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
ACMP1 supports
– 4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 4 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme with External VREF
as close to AVDD as possible
L=30Z
1uF+0.1uF+0.01uF
EXT_PWR
AVDD
AVSS
as close to LDO as possible
EXT_PWR
VDD
VSW
10uF
4.7uH
2.2uF
LDO_CAP
VSS
as close to VREF as possible
as close to the EXT_PWR as possible
L=30Z
2.2uF+1uF+470pF
VREF
as close to VBAT as possible
0.1uF
VBAT
10uF+0.1uF
AVSS
VSS
L=30Z
as close to VDD as possible
0.1uF*N
as close to VDDIO as possible
0.1uF
VDD
VDDIO
VSS
VSS
EXT_VSS
EXT_VSS
Note:VDD which is near LDO need to be connected to 10 uF.(ex. QFN33 pin 27; LQFP64 pin 51; LQFP128 pin 114)
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7.2 Power Supply Scheme with Internal VREF
as close to AVDD as possible
L=30Z
1uF+0.1uF+0.01uF
EXT_PWR
AVDD
AVSS
as close to LDO as possible
EXT_PWR
VDD
VSW
10uF
4.7uH
2.2uF
L=30Z
LDO_CAP
VSS
as close to VREF as possible
as close to the EXT_PWR as possible
VREF
as close to VBAT as possible
0.1uF
VBAT
10uF+0.1uF
0.1uF
AVSS
VSS
as close to VDD as possible
0.1uF*N
as close to VDDIO as possible
0.1uF
VDDIO
VDD
VSS
VSS
EXT_VSS
EXT_VSS
Note:VDD which is near LDO need to be connected to 10 uF.(ex. QFN33 pin 27; LQFP64 pin 51; LQFP128 pin 114)
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7.3 Peripheral Application Scheme
5V
USB Full Speed
OTG Slot Power Switch
(OTG Host)
64K x 16-bit
SRAM
LATCH
USB_VBUS
D
Q
Addr[15:0]
33R
USB_D-
33R
En
ALE
USB_D+
USB_ID
nCE
nOE
nWE
nLB
nUB
nCS
nRD
EBI
nWR
nWRL
nWRH
VDD
ICE_DAT
SWD
Interface
ICE_CLK
nRESET
AD[15:0]
Data[15:0]
VSS
DVCC
20pF
M2351 Series
XT1_IN
CS
SPI_SS
VDD
VSS
SPI_CLK
CLK
SPI Device
SPI_MISO
SPI_MOSI
MISO
MOSI
4~24 MHz
crystal
20pF
20pF
DVCC
XT1_OUT
DVCC
Crystal
4.7K
4.7K
X32_IN
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
32.768 kHz
crystal
I2C Device
20pF
X32_OUT
DVCC
DVCC
SC_PWR
Reset
Circuit
10K
nRST
SC_RST
SC_CLK
Smart Card Slot
10uF/10V
SC_DAT
SC_nCD
ODB Port
CAN Transceiver
LDO_CAP
CAN_TX
CAN_RX
D
R
CAN_H
CAN_L
LDO
2.2uF
CAN
PC COM Port
RS 232 Transceiver
Audio codec
NUC8822
RIN
UART_RXD
UART_TXD
ROUT
TIN
Line In
Line Out
I2S
UART
TOUT
*Note: USB_ID could be floating using USB or USB HS without OTG.
Feb 15, 2019
Page 190 of 245
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8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stesses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1 Voltage Characteristics
Symbol
VDD-VSS
VDDIO-VSS
VBat
Parameter
DC Power Supply
Min
-0.3
-0.3
-0.3
-
Max
4.0
4.0
4.0
50
Unit
V
VDDIO Power Supply
V
RTC domain Power Supply
Variations between different power pins
V
|VDDX – VDD
|
mV
-
|VDD –AVDD
|
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
50
50
50
mV
mV
mV
-
-
|VSSX - VSS
|
|VSS - AVSS
|
Input Voltage on 5V-tolerance GPIO
Input Voltage on RTC domain (PF.6 ~ PF.11)
Input Voltage on any other pin[*2]
VSS-0.3
VSS-0.3
VSS-0.3
5.5
4.0
4.0
V
V
V
VIN
Note:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must always be connected to the external power supply, in the
permitted range.
2. Non 5V-tolerance PIN: PA.8 ~ 15; PB.0 ~ 15; PD.10, 11, 12; PF.2, 3, 4, 5; All USB High Speed pin and nRESET pin.
Table 8.1-1 Voltage Characteristics
8.1.2 Current Characteristics
Symbol
IDD
Parameter
Max
200
100
100
100
20
Unit
Maximum Current into VDD
IDDIO
IBAT
Maximum Current into VDDIO
Maximum Current into VBAT
ISS
Maximum Current out of VSS
mA
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
Maximum Current Sunk by Total I/O Pins
Maximum Current Sourced by Total I/O Pins
20
IIO
100
100
Feb 15, 2019
Page 191 of 245
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Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
Table 8.1-2 Current Characteristics
8.1.3 Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (℃)
θJA = thermal resistance junction-ambient (℃/Watt)
P
D
= sum of internal and I/O power dissipation
Parameter
Symbol
TA
Min
-40
-40
-65
Max
105
125
150
Unit
Operating Temperature
TJ
Junction temperature
C
TST
Storage Temperature
Table 8.1-3 Thermal Characteristics
8.1.4 EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of
narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Feb 15, 2019
Page 192 of 245
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M2351
Symbol
Ratings
Conditions
Max
Unit
kV
Fast transient voltage burst limits to be applied through
100 pF on VDD and VSS pins to induce a functional
disturbance
[*3] [*4]
VEFTB
VDD = 3.3 V, LQFP128, TA
+25 °C, fHCLK = 64 MHz,
=
4.4
[*5]
Electrostatic discharge voltage (human body model)
Electrostatic discharge voltage (charge device model)
Static latch-up class
TA = +25 °C
TA = +25 °C
TA +25 °C
2
VESD(HBM)
[*6]
0.5
400
VESD(CDM)
LU [*7]
mA
Note:
1. Guaranteed by characterization results, not tested in production.
2. On VBAT pin, VESD(HBM) is limited to 1000V.
3. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
4. The performace cretia class is 4A.
5. Determined according to JEDEC EIA/JESD78 standard.
6. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
7. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
Table 8.1-4 EMC Characteristics
Feb 15, 2019
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M2351
8.2 General Operating Conditions
(VDD-VSS = 1.7 ~ 3.6V, TA = 25C, HCLK = 64 MHz unless otherwise specified.)
Conditions
Unit
Min.
-
Typ.
Max.
64
Symbol
Parameter
fHCLK
Internal AHB clock frequency
MHz
-
VDD
Operation Voltage
1.7
3.6
-
[*1]
AVDD
Analog Operation Voltage
Power supply for PA.0 ~ 5
VDD
VDDIO
VBAT
1.7
1.7
3.6
3.6
-
-
V
RTC Operation voltage for PF.6
PF.11
~
VLDO
VBG
LDO Output Voltage
1.08
1.18
1.2
-
1.32
1.21
Band-gap Voltage
[*2]
CLDO
LDO Output capacitance on each pin
2.2
uF
-
-
Note:
1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2. To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
Feb 15, 2019
Page 194 of 245
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M2351
8.3 DC Electrical Characteristics
8.3.1 Typical Current Consumption
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
ALL GPIO pins are in push pull mode, output high.
LDO = 1.26V
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
VDD = VBAT = AVDD = VDDIO
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK/2.
Program run while(1){} from Flash.
8.3.1.1 LDO Normal Mode
T
A
HIRC /
HIRC48 / LIRC
f
Symbol
Conditions
HXT/LXT
PLL
unit
HCLK
25 °C
6.2
105 °C[*1]
7.1
64 MHz[*2]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
-
V
V
-
5.2
6.0
-
1.7
2.4
-
1.4
2.2
-
-
1.2
1.9
-
-
1.1
1.8
-
-
Normal Run, executed from
Flash, VDD = 3.3V, Vsw without
Inductance, all peripherals
disable
6.9
7.6
12MHz
V
V
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
32.768 KHz
10KHz
-
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
4.2
3.8
1.3
0.8
0.7
0.5
0.1
0.1
14.1
4.9
4.5
1.9
1.4
1.4
1.2
0.8
0.8
15.1
-
-
-
-
-
I
-
-
mA
DD
-
32.768 kHz
-
-
-
10KHz
-
-
64 MHz[*2]
12MHz
V
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
48 MHz[*3]
12MHz
12MHz
12MHz
12MHz
12MHz
-
-
V
-
11.0
3.7
11.8
4.4
-
Normal run, executed from
Flash, VDD = 3.3V, Vsw
without Inductance, all
peripherals enabled
2.8
3.5
-
-
2.3
3.1
-
-
2.0
2.8
-
-
13.7
9.6
14.4
10.2
12MHz
12MHz
V
V
-
Feb 15, 2019
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M2351
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
32.768 KHz
10KHz
-
48MHz
12MHz
12MHz
12MHz
12MHz
-
9.1
3.1
1.9
1.6
1.3
0.8
0.9
9.8
3.8
2.5
2.2
1.9
1.5
1.6
-
-
-
-
-
-
-
-
-
-
32.768 kHz
-
10KHz
Note:
1. Guaranteed by characterization results, not tested in production.
2. In this case HCLK = system clock, system clock = 64MHz, LDO = 1.26V
3. In this case HCLK = system clock, system clock = 48MHz, LDO = 1.2V
4. In this case HCLK = system clock, system clock = 12MHz, LDO = 1.2V
5. In this case HCLK = system clock/2, system clock = 12MHz, LDO = 1.2V
6. In this case HCLK = system clock/3, system clock = 12MHz, LDO = 1.2V
7. In this case HCLK = system clock/6, system clock = 12MHz, LDO = 1.2V
8. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-1 Current Consumption in LDO Normal Run Mode
8.3.1.2 DC-DC Normal Mode
T
A
HIRC /
HIRC48 / LIRC
f
Symbol
Conditions
HXT/LXT
PLL
unit
HCLK
25 °C
3.1
105 °C
3.6
64 MHz[*2]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
-
-
V
V
-
2.7
3.1
-
1.1
1.5
-
1.0
1.3
-
-
0.9
1.2
-
-
0.8
1.2
-
-
Normal Run, executed from
Flash, VDD = 3.3V, Vsw with
Inductance, all peripherals
disable
2.9
3.3
12MHz
V
V
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
32.768 KHz
10KHz
-
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
1.9
1.7
0.7
0.5
0.4
0.3
0.1
0.1
6.7
2.2
2.0
1.0
0.7
0.7
0.6
0.4
0.4
7.2
-
-
-
-
I
mA
DD
-
-
-
-
32.768 kHz
-
-
-
10KHz
-
-
64 MHz[*2]
12MHz
V
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
12MHz
12MHz
12MHz
12MHz
-
-
-
-
V
-
5.3
2.0
1.6
1.5
5.7
2.4
2.0
1.8
Normal run, executed from
Flash, VDD = 3.3V, Vsw with
Inductance, all peripherals
enabled
-
-
Feb 15, 2019
Page 196 of 245
Rev 1.01
M2351
2 MHz[*7]
64 MHz[*2]
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
32.768 KHz
10KHz
12MHz
-
-
1.3
6.5
4.2
4.0
1.4
0.9
0.8
0.7
0.5
0.5
1.7
6.8
4.5
4.3
1.7
1.2
1.1
1.0
0.8
0.8
12MHz
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
V
V
-
-
-
-
-
-
-
-
-
-
-
-
32.768 kHz
-
10KHz
Note:
1. Guaranteed by characterization results, not tested in production.
2. In this case HCLK = system clock, system clock = 64MHz, LDO = 1.26V
3. In this case HCLK = system clock, system clock = 48MHz, LDO = 1.2V
4. In this case HCLK = system clock, system clock = 12MHz, LDO = 1.2V
5. In this case HCLK = system clock/2, system clock = 12MHz, LDO = 1.2V
6. In this case HCLK = system clock/3, system clock = 12MHz, LDO = 1.2V
7. In this case HCLK = system clock/6, system clock = 12MHz, LDO = 1.2V
8. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-2 Current Consumption in DC-DC Normal Run Mode
8.3.1.3 LDO Idle Mode
TA
Symbol
Conditions
fHCLK
HXT/LXT
HIRC/LIRC
PLL
Unit
25 °C
2.9
105 °C[*1]
3.7
64 MHz[*2]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
12MHz
12MHz
12MHz
12MHz
12MHz
-
-
V
V
-
2.4
3.1
1.1
1.8
-
1.0
1.7
-
-
1.0
1.7
-
-
2 MHz[*7]
12MHz
-
-
1.0
2.3
1.7
3.1
Idle mode, executed from
Flash, VDD = 3.3V, Vsw without
Inductance, all peripherals
disabled
64 MHz[*2]
12MHz
V
V
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
-
-
-
-
-
-
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
1.8
1.4
0.6
0.5
0.5
0.4
0.1
0.1
10.9
2.5
2.1
1.2
1.1
1.1
1.0
0.8
0.8
11.9
IDD
mA
-
-
-
-
32.768 KHz 32.768 kHz
-
10KHz
64 MHz[*2]
-
10KHz
-
-
12MHz
V
Idle mode, executed from
Flash, VDD = 3.3V, Vsw without
Inductance, all peripherals
48 MHz[*3]
12MHz
-
V
8.2
9.0
Feb 15, 2019
Page 197 of 245
Rev 1.01
M2351
enabled
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
12MHz
12MHz
12MHz
12MHz
-
-
-
3.0
2.3
2.0
1.8
10.0
7.4
6.9
2.2
1.5
1.2
1.0
0.7
0.8
3.7
3.0
2.8
2.5
10.7
8.0
7.5
2.8
2.1
1.9
1.6
1.3
1.4
-
-
-
-
-
12MHz
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
V
V
-
-
-
-
-
-
-
-
-
-
-
-
32.768 KHz 32.768 kHz
10KHz
-
10KHz
Note:
1. Guaranteed by characterization results, not tested in production.
2. In this case HCLK = system clock, system clock = 64MHz, LDO = 1.26V
3. In this case HCLK = system clock, system clock = 48MHz, LDO = 1.2V
4. In this case HCLK = system clock, system clock = 12MHz, LDO = 1.2V
5. In this case HCLK = system clock/2, system clock = 12MHz, LDO = 1.2V
6. In this case HCLK = system clock/3, system clock = 12MHz, LDO = 1.2V
7. In this case HCLK = system clock/6, system clock = 12MHz, LDO = 1.2V
8. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-3 Current consumption in LDO Idle mode
8.3.1.4 DC-DC Idle Mode
T
A
Symbol
Conditions
fHCLK
HXT/LXT HIRC/LIRC PLL
unit
25 °C
105 °C[*1]
64 MHz[*2]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
-
V
1.6
1.4
0.9
0.8
0.8
0.8
1.1
2.1
1.8
1.2
1.2
1.2
1.1
1.5
-
-
-
-
-
V
-
-
-
-
Idle mode, executed from
Flash, VDD = 3.3V, Vsw with
Inductance, all peripherals
disabled
IDD
mA
12MHz
V
V
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
-
-
-
-
-
-
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
0.9
0.7
0.4
0.3
0.3
0.3
0.1
1.2
1.0
0.7
0.6
0.6
0.6
0.6
-
-
-
-
-
32.768 KHz 32.768 kHz
Feb 15, 2019
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M2351
0.1
5.3
0.4
10KHz
64 MHz[*2]
-
10KHz
-
-
5.8
4.4
2.1
1.8
1.7
1.6
4.9
3.5
3.4
1.3
1.0
0.9
0.8
0.7
0.7
12MHz
V
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
64 MHz[*2]
48 MHz[*3]
48 MHz[*3]
12MHz[*4]
6 MHz[*5]
4 MHz[*6]
2 MHz[*7]
12MHz
12MHz
12MHz
12MHz
12MHz
-
V
-
4.0
1.7
1.4
1.3
1.2
4.6
3.3
3.1
1.0
0.7
0.6
0.5
0.4
0.4
-
-
-
-
-
-
-
12MHz
12MHz
48MHz
12MHz
12MHz
12MHz
12MHz
-
V
V
Idle mode, executed from
Flash, VDD = 3.3V, Vsw with
Inductance, all peripherals
enabled
-
-
-
-
-
-
-
-
-
-
-
-
32.768 KHz 32.768 kHz
10KHz
-
10KHz
Note:
1. Guaranteed by characterization results, not tested in production.
2. In this case HCLK = system clock, system clock = 64MHz, LDO = 1.26V
3. In this case HCLK = system clock, system clock = 48MHz, LDO = 1.2V
4. In this case HCLK = system clock, system clock = 12MHz, LDO = 1.2V
5. In this case HCLK = system clock/2, system clock = 12MHz, LDO = 1.2V
6. In this case HCLK = system clock/3, system clock = 12MHz, LDO = 1.2V
7. In this case HCLK = system clock/6, system clock = 12MHz, LDO = 1.2V
8. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-4 Current Consumption in DC-DC Idle Mode
8.3.1.5 LDO Power-down Mode
Symbol
Conditions
LXT
LIRC
PLL
TA
LDO
Unit
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
96.5
128.3
225.0
462.1
698.0
91.0
Power-down mode, VDD = 3.3V, all peripherals
disabled, SRAM retention
IDD_FWPD
-
-
-
uA
Power-down mode, VDD = 3.3V, all peripherals
disabled, no SRAM retention
107.7
131.6
Feb 15, 2019
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M2351
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
189.2
271.8
96.9
129.0
225.9
468.8
715.0
91.8
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, SRAM retention
V
-
-
109.1
132.8
190.5
273.4
95.9
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, no SRAM
retention
128.1
224.6
455.8
737.5
91.4
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, SRAM retention
-
V
-
107.9
131.7
189.6
272.0
96.6
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, no SRAM retention
129.2
225.7
446.8
737.5
92.4
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, SRAM retention
V
V
-
109.2
133.0
191.3
273.5
18.2
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, no SRAM retention
40.3
Power-down mode, VDD = 3.3V, all peripherals
disabled, SRAM retention
IDD_PD
-
-
-
115.9
282.9
Feb 15, 2019
Page 200 of 245
Rev 1.01
M2351
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
737.5
12.5
20.2
Power-down mode, VDD = 3.3V, all peripherals
disabled, no SRAM retention
35.7
79.0
140.1
19.2
41.5
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, SRAM retention
117.1
289.9
498.8
13.5
V
-
-
-
-
21.6
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, no SRAM
retention
37.1
80.3
141.8
18.6
40.7
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, SRAM retention
116.3
292.9
500.0
12.9
-
V
20.4
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, no SRAM retention
36.0
78.7
140.5
19.3
41.7
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, SRAM retention
117.6
288.6
503.2
13.9
V
V
21.7
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, no SRAM retention
37.4
80.0
142.2
Feb 15, 2019
Page 201 of 245
Rev 1.01
M2351
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
6.2
15.8
55.5
154.5
299.3
4.6
Power-down mode, VDD = 3.3V, all peripherals
disabled, SRAM retention
-
-
-
8.2
Power-down mode, VDD = 3.3V, all peripherals
disabled, no SRAM retention
17.0
44.4
88.0
7.0
16.9
56.8
156.2
301.1
5.4
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, SRAM retention
V
-
-
9.6
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, no SRAM
retention
18.3
45.8
89.7
6.3
IDD_LLPD
uA
16.1
55.8
157.3
299.6
4.7
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, SRAM retention
-
V
-
8.4
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, no SRAM retention
17.2
44.4
88.5
7.2
17.2
57.0
161.2
301.0
5.7
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, SRAM retention
V
V
-
Power-down mode, VDD = 3.3V, WDT/Timer use
Feb 15, 2019
Page 202 of 245
Rev 1.01
M2351
LIRC, RTC/UART use LXT, no SRAM retention
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
9.6
18.6
45.8
90.1
4.4
11.7
43.6
132.6
251.4
3.3
Power-down mode, VDD = 3.3V, all peripherals
disabled, SRAM retention
-
-
-
6.2
Power-down mode, VDD = 3.3V, all peripherals
disabled, no SRAM retention
13.6
37.1
76.4
5.4
12.8
44.9
134.6
252.7
4.3
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, SRAM retention
V
-
-
IDD_ULLPD
uA
7.6
Power-down mode, VDD = 3.3V,
RTC/WDT/Timer/UART enabled, no SRAM
retention
14.8
38.4
78.0
4.6
11.9
43.9
133.3
251.2
3.5
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, SRAM retention
-
V
-
6.5
Power-down mode, VDD = 3.3V, RTC/WDT/Timer
use LIRC, no SRAM retention
13.9
37.4
76.7
5.5
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, SRAM retention
V
V
-
13.0
Feb 15, 2019
Page 203 of 245
Rev 1.01
M2351
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
45.2
134.0
252.6
4.4
7.7
Power-down mode, VDD = 3.3V, WDT/Timer use
LIRC, RTC/UART use LXT, no SRAM retention
15.3
38.8
78.3
2.1
2.8
Standby Power-down mode(SPD), VDD = 3.3V, all
peripherals disabled
-
V
-
-
-
-
-
-
3.9
8.1
15.5
3.0
3.9
Standby Power-down mode (SPD), VDD = 3.3V,
RTC enabled
IDD_SPD
-
5.0
9.5
17.2
2.1
2.8
Standby Power-down mode (SPD), VDD = 3.3V,
RTC enabled
V
3.9
8.3
15.6
1.0
1.5
Deep Power-down mode (DPD), VDD = 3.3V, all
peripherals disabled
-
-
1.9
4.2
8.2
1.9
IDD_DPD
2.4
Deep Power-down mode(DPD), RTC enable[*1]
V
-
-
-
3.3
5.6
9.8
0.9
Deep Power-down mode(DPD), RTC enable[*1]
-
V
1.6
2.0
Feb 15, 2019
Page 204 of 245
Rev 1.01
M2351
85 °C
4.2
8.3
105 °C
Note:
1. VDD = AVDD = VBAT = VDDIO = 3.3V
2. Guaranteed by characterization results, not tested in production.
3. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-5 Chip Current Consumption in Power-down Mode
8.3.1.6 Current Consumption for RTC Domain
T
Symbol
Conditions
LXT
LDO
DCDC
Unit
A
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
-40 °C
25 °C
55 °C
85 °C
105 °C
2.3
2.5
3.1
4.9
7.8
2.0
2.3
2.8
4.7
7.5
1.9
2.3
2.8
4.5
7.3
1.0
1.4
1.8
3.6
6.2
0.9
1.3
1.7
3.4
6.0
2.0
2.4
3.0
4.7
7.1
1.9
2.5
2.9
4.8
7.5
1.9
2.2
2.8
4.1
7.3
1.2
1.3
1.6
3.5
5.7
1.1
1.2
1.6
3.2
5.9
RTC enabled, operating current, VBAT = 3.6V
V
RTC enabled, operating current, VBAT = 3.3V
RTC enabled, operating current, VBAT = 1.7V
RTC disabled, operating current, VBAT = 3.6V
RTC disabled, operating current, VBAT = 3.3V
V
V
V
IBAT
uA
V
Feb 15, 2019
Page 205 of 245
Rev 1.01
M2351
-40 °C
25 °C
55 °C
85 °C
105 °C
0.9
1.1
1.5
3.0
5.7
0.9
1.2
1.6
2.9
5.7
RTC disabled, operating current, VBAT = 1.7V
V
Note: Guaranteed by characterization results, not tested in production.
Table 8.3-6 Current Consumption for VBAT
On-chip Peripheral Current Consumption
8.3.2
All GPIO pins are in push pull mode, output high.
LDO = 1.26V
The typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
When the peripherals are enabled HCLK is the system clock, fHCLK = 64 MHz, fPCLK0, 1
fHCLK/2.
=
Peripheral
PDMA0
PDMA1
ISP
IDD
24.8
24
Unit
0.1
6.1
36.5
2.5
6
EBI
SDH0
CRC
CRPT
FMC
30
USBH
SRAM0IDLE
SRAM1IDLE
WDT
50
6.2
4.8
1.3
3.8
5.1
4.9
4.6
4.9
0.2
4
uA
RTC
TMR0
TMR1
TMR2
TMR3
CLKO
ACMP01
I2C0
1.1
1
I2C1
Feb 15, 2019
Page 206 of 245
Rev 1.01
M2351
I2C2
QSPI0
SPI0
0.8
10.5
13.9
11.5
16.5
6
SPI1
SPI2
UART0
UART1
UART2
UART3
UART4
UART5
CAN0
OTG
8.4
4.9
7.3
4.9
7.7
8.2
15.2
38.7
12.7
2.9
USBDC
EADC
I2S0
SC0
2.8
SC1
5.3
SC2
2.6
SPI3
12.8
5.9
USCI0
USCI1
DAC
7.2
1.4
EPWM0
EPWM1
BPWM0
BPWM1
QEI0
8.3
10.4
3.1
5.2
2.1
QEI1
3.4
TRNG
ECAP0
28.8
1.8
ECAP1
3.4
Note: Guaranteed by characterization results, not tested in production.
Feb 15, 2019
Page 207 of 245
Rev 1.01
M2351
8.3.3
Wakeup Time
The wakeup times given in Table 8.3-7 is measured on a wakeup phase with a 12 MHz HIRC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
–
Fast-wakeup, power down, low leakage Power-down mode: the clock source is the RC
oscillator
–
Standby and Deep Power-down mode: the clock source is the clock that was set before
entering Sleep mode.
The wakeup times are measured from the wakeup event to the point in which the application
code reads the first instruction.
The clock source is the RC oscillator from HIRC.
Symbol
Parameter
Typ[*1]
Unit
1.63[*2]
tWU_IDLE
tWU_FWPD
tWU_NPD
tWU_LLPD
tWU_ULLPD
tWU_SPD
tWU_DPD
Wakeup from IDLE mode
9.0[*2]
11.5[*2]
60[*2]
Wakeup from Fast-wakeup Power-down mode
Wakeup from normal Power-down mode
Wakeup from low leakage Power-down mode
Wakeup from ultra low leakage power down
Wakeup from Standby Power-down mode (SPD)
Deep Power-down mode (DPD)
µs
61[*2]
525[*2]
183[*3]
Note:
1. Guaranteed by characterization results, not tested in production.
2. The wake up source is GPIO(PA.0) wake up.
3. The wake up source is GPIO(PC.0) wake up.
4. Based on test during characterization, not tested in production.
5. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-7 Low-power Mode Wakeup Timings
Feb 15, 2019
Page 208 of 245
Rev 1.01
M2351
8.3.4
I/O DC Characteristics
Symbol
Parameter
Min
0.8
Typ
Max Unit
Test Conditions
VDD = VDDIO = 3.6 V
-
-
V
V
V
V
VIL1
VIH1
VIL2
Input Low Voltage (TTL input)
Input High Voltage (TTL input)
Input Low Voltage (Schmitt input)
-
-
-
-
-
0.56
-
-
VDD = VDDIO = 1.7 V
VDD = VDDIO = 3.6V
VDD = VDDIO = 1.7V
VDD = VDDIO = 3.6V
2
1.04
-
-
0.3*VDD
0.3*VDD
V
-
VDD = VDDIO = 1.7V
VDD = VDDIO = 3.6V
VDD = VDDIO = 1.7V
0.7*VDD
0.7*VDD
-
-
-
0.2VDD
-
VIH2
Input High Voltage (Schmitt input)
Hysteresis voltage of (Schmitt input)
V
V
VHY
-
VDD = VDDIO = 3.6V, 0 < VIN
VDD, Open-drain or input only
mode
<
ILK
Input Leakage Current
-1
1
A
67.9
53
-
-
-
-
-
-
-
-
-
-
IIL
Logic 0 Input Current (Quasi-bidirectional mode)
Input Pull Up Resistor
uA VDD = VDDIO = 3.6V, VIN = 0V
KΩ VDD = VDDIO = 3.3V
KΩ VDD = VDDIO = 1.8V
KΩ VDD = VDDIO = 3.3V
KΩ VDD = VDDIO = 1.8V
RPU
53
53
RPD
Input Pull down Resistor
53
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher
than the maximum value, if positive current is injected on adjacent pins
Table 8.3-8 PIN input Characteristics
Typ
Max
Symbol
Parameter
Min
Unit
Test Conditions
Source Current
-7.939
-
-6.934
ISR1
uA
VDD = VDDIO = 3.3V
(Quasi-bidirectional Mode, Set GPIO to output
HIGH, Apply GPIO pin VIN=(VDD-0.4)V for VDD
and measure the source current)
-7.939
-20.629
-14.326
3.576
-
-
-
-
-6.934
-3.43
ISR2
ISR3
ISR4
ISK1
uA
mA
mA
mA
VDD = VDDIO = 1.8V
VDD = VDDIO = 3.3V
VDD = VDDIO = 1.8V
VDD = VDDIO = 3.3V
Source Current
(Push-pull Mode, Set GPIO to output HIGH,
Apply GPIO pin VIN=(VDD-0.4)V for VDD and
measure the source current)
-4.392
19.98
Sink Current
(Quasi-bidirectional, Push-pull Mode, Set GPIO
to output LOW, Apply GPIO pin
VIN=(VSS+0.4)V for VSS and measure the
source current)
4.102
-
12.351
ISK2
mA
VDD = VDDIO = 1.8V
Feb 15, 2019
Page 209 of 245
Rev 1.01
M2351
Logic 1 to 0 Transition Current
(Quasi-bidirectional Mode)
VDD = VDDIO = 3.3V
VIN=2.0V
-
-
ITL
-70
4.2
uA
pF
-
-
CIO
I/O pin capacitance
Notes:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS.
Table 8.3-9 PIN Output Characteristics
Symbol
Parameter
Negative going threshold
Min
Typ
Max unit
Test Conditions
-
0.3*VDD
V
V
VDD = 3.3V
-
VILR
(Schmitt input), nRESET
Positive going threshold
(Schmitt Input), nRESET
0.7*VDD
-
VDD = 3.3V
-
VIHR
50
-
56.8
KΩ
RRST
tFR1
Internal nRESET pin pull up resistor
nRESET input filtered time
32
uS
-
-
nRESET input filtered time under SPD and DPD
mode
300
nS
VDD = 3.3V,
-
-
tFR2
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.3-10 nRESET Pin Characteristics
Feb 15, 2019
Page 210 of 245
Rev 1.01
M2351
8.4
AC Electrical Characteristics
8.4.1
External 4~24 MHz High Speed Crystal (HXT) Characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
VDD
Parameter
Operating Voltage
Min. Typ. Max. Unit
Test Conditions
1.7
-
3.0
3.6
-
V
kΩ
Rf
Feedback resister
1000
fHXT
Oscillator frequency
Temperature Range
4
-
-
24
105
MHz
C
VDD = 1.8 ~ 3.3V
THXT
-40
620
1088
1943
2085
230
4MHz
12MHz
16MHz
24MHz
4MHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Current Consumption
(INV-type Crystal)
IHXT_INV
IHXT_GM
TS_GM
mA
A
s
364
12MHz
16MHz
24MHz
4MHz
Current Consumption
(GM-type Crystal)
400
620
2026
602
12MHz
16MHz
24MHz
4MHz
Stable time (GM-type)
440
401
2322
619
443
419
50
12MHz
16MHz
24MHz
TS_INV
Stable time (INV-type)
Clock Duty
s
-
-
45
55
%
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.4-1 External 4~24 MHz High Speed Crystal (HXT) Oscillator
Feb 15, 2019
Page 211 of 245
Rev 1.01
M2351
8.4.1.1 Typical Crystal Application Circuits
Crystal
C1
C2
5~20pF
4~24 MHz
5~20pF
XT_OUT
XT_IN
C1
C2
Figure 8.4-1 Typical Crystal Application Circuit
8.4.2
External 4~24 MHz High Speed Crystal (OSC) Input Clock
Symbol
Parameter
Clock High Time
Min.
Typ.
Max.
Unit
nS
nS
nS
nS
V
Test Conditions
18
tCHCX
tCLCX
tCLCH
tCHCL
-
-
-
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
Input High Voltage
Input Low Voltage
18
-
10
-
10
-
-
0.7*VDD
VIH
VIL
-
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
Feb 15, 2019
Page 212 of 245
Rev 1.01
M2351
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
Note: Guaranteed by design, not tested in production.
Feb 15, 2019
Page 213 of 245
Rev 1.01
M2351
8.4.3
External 32.768 kHz Low Speed Crystal (LXT) Characteristics
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VBAT
Parameter
Operation Voltage
Min. Typ. Max. Unit
Test Conditions
VBAT = 1.7 ~ 3.6 V
VBAT = 3.3V
1.7
-
-
32.768
-
3.6
V
kHz
C
fLXT
Oscillator frequency
Temperature
-
105
-
-40
-
TLXT
ILXT
Operating current
Duty cycle
0.45
-
A
%
45
-
55
-
TS
Stable Time
372
ms
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.4-2 External 32.768 kHz Crystal
8.4.3.1 Typical Crystal Application Circuits
Crystal
C1
C2
32.768 kHz
5~20pF
5~20pF
XT_OUT
XT_IN
C1
C2
Figure 8.4-2 Typical Crystal Application Circuit
8.4.4
External 32.768 kHz Low Speed Crystal (OSC) Input Clock
Parameter
Symbol
tCHCX
Min.
450
Typ.
Max.
Unit
ns
Test Conditions
Clock High Time
Clock Low Time
-
-
-
-
450
ns
tCLCX
Feb 15, 2019
Page 214 of 245
Rev 1.01
M2351
Parameter
Clock Rise Time
Symbol
tCLCH
Min.
Typ.
Max.
Unit
ns
Test Conditions
50
-
-
-
-
-
Clock Fall Time
50
ns
tCHCL
-
0.7*VDD
-
Xin_VIH
Xin_VIL
LXT Input Pin Input High Voltage
LXT Input Pin Input Low Voltage
V
V
0.3*VDD
-
tCLCL
tCLCH
tCLCX
90%
10%
Xin_VIH
Xin_VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.4.5
12 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min.
Typ.
-
Max.
Unit
V
Test Conditions
1.7
3.6
VHRC Supply voltage
Center Frequency
12
MHz
-
-
TA = 25 °C,
-0.35
0.35
%
%
-
-
fHRC
VDD = 3.3V
Internal Oscillator Frequency[*1]
TA = -40C ~ +105 °C,
-3.6
2.7
VDD = 1.7 ~ 3.6V
70
3
IHRC Operating current
TS Stable time
-
-
-
-
A
us
Note: Guaranteed by characterization, not tested in production.
8.4.6
48 MHz Internal High Speed RC Oscillator (HIRC48)
Symbol
Parameter
Min.
Typ.
-
Max.
Unit
V
Test Conditions
1.7
3.6
VHRC Supply voltage
Center Frequency
48
-
-
MHz
TA = 25 °C,
VDD = 3.3V
-0.285
0.8715
-
%
fHRC
Frequency drift over temperarure
and volatge [*1]
TA = -40C ~ +105 °C,
-3.555
-
2.41
-
-
%
VDD = 1.7 ~ 3.6V
100
IHRC Operating current
A
Feb 15, 2019
Page 215 of 245
Rev 1.01
M2351
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
5
TS
Stable time
-
-
us
Note: Guaranteed by characterization, not tested in production.
8.4.7
Symbol
VLRC
10 kHz Internal Low Speed RC Oscillator (LIRC)
Parameter
Supply voltage
Center Frequency
Min.
Typ.
-
Max.
Unit
V
Test Conditions
1.7
3.6
kHz
10
FLRC
Frequency
drift
over
-40.476
49.772
-
%
VDD=1.7V~3.6V, TA=-40~105°C
VDD = 3.3V
temperarure and volatge [*1]
Operating current
Stable time
0.29
200
ILRC
TS
-
-
-
-
A
μs
Note: Guaranteed by characterization, not tested in production.
8.4.8
PLL Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4
24
fPLL_IN
fPLL_OUT
Jitter
IDD
PLL input clock
PLL multiplier output clock
Cycle-to-cycle Jitter[*2]
Power consumption
MHz
MHz
ps
-
-
50
200
250
Peak to peak at 144M
VDD=3.3Vat 200MHz
-
-
-
-
1
mA
Note:
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
Feb 15, 2019
Page 216 of 245
Rev 1.01
M2351
8.4.9
I/O AC Characteristics
Px_SLEWCTL Symbol
Parameter
Conditions
Typ Unit
CL = 51 pF
CL = 30 pF
CL = 51 pF
4.1
2.9
9.7
VDD = 3.6 V
Output high to low level fall time
(90~10%)
t
f(IO)out
VDD = 1.7 V
VDD = 3.6 V
VDD = 1.7 V
VDD = 3.6 V
VDD = 1.7 V
VDD = 3.6 V
VDD = 1.7 V
VDD = 3.6 V
VDD = 1.7 V
VDD = 3.6 V
VDD = 1.7 V
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
CL = 51 pF
CL = 30 pF
7.3
4.4
3.3
10.0
7.3
3.4
2.2
7.4
4.9
00
Output low to high level rise time
(10~90%)
t
r(IO)out
Output high to low level fall time
(90~10%)
t
f(IO)out
01
ns
3.1
2.0
7.2
4.7
3.4
2.2
7.4
4.9
3.1
2.0
7.2
4.7
Output low to high level rise time
(10~90%)
t
r(IO)out
Output high to low level fall time
(90~10%)
t
f(IO)out
10
Output low to high level rise time
(10~90%)
t
r(IO)out
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢅ
3. The maximum frequency is defined by
ꢃꢄ
ꢍꢄ.
ꢌ
ꢀꢁꢂ
ꢆꢄꢇꢄꢈꢉ ꢋꢉ
ꢊ
4. The I/O dynamic current consumption is defined by ꢎꢏꢐꢑ ꢃ ꢒꢏꢏ ꢄꢇꢄ ꢐꢑ ꢄꢇ ꢈꢓꢐꢑ ꢔꢄꢓꢕꢍ
Table 8.4-3 I/O AC Characteristics
Feb 15, 2019
Page 217 of 245
Rev 1.01
M2351
8.5
Analog Electrical Characteristics
8.5.1 LDO
Symbol
Parameter
Min
Typ
-
Max
Unit
V
Test Condition
VDD
DC Power Supply
1.7
3.6
-
-
1.26
1.20
-
-
V
Turbo mode
V
Normal run mode
VLDO
Output Voltage
Temperature
Low leakage power-down
mode
-
0.96
-
V
Ultra low leakage Power-
down mode
-
0.86
-
-
V
TA
-40
105
℃
Note:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 2.2μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
3. For ensuring power stability, a 2.2μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
8.5.2 DC-DC
Typical values are at VDD = 3.3V, TA = 25°C, Vsw is connected to 4.7uH inductance and LDO_CAP is
connected to 2.2uF capacitance unless otherwise specified.
Symbol
Parameter
Min
1.7
1.2
1.15
-
Typ
Max
3.6
Unit
V
Test Condition
VIN
Input Voltage Range
-
1.26
1.20
-
1.4
V
VOUT
Output Voltage Range
1.33
30
V
IOUT_MAX
IQ_DCDC
Maximum DC Output Current
Quiescent Current
mA
VIN>1.7V
-
-
No load, normal mode, only
buck regulator
15
uA
VLINE
Line Regulation
Load Regulation
-5
-5
-
-
5
5
%
%
IOUT=30mA, VIN=1.7V to 3.6V
IOUT=0.2mA to 30mA
VLOAD
IOUT= 2~30mA
PEFF
Power Efficiency
-
80
-
%
LOUT = 4.7uH, DCR ≤ 180mΩ
Note:
1. It is recommended a 2.2μF and 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 2.2μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
Feb 15, 2019
Page 218 of 245
Rev 1.01
M2351
8.5.3 Low-Voltage Reset
Symbol
AVDD
TA
Parameter
Min Typ Max Unit
Test Condition
0
3.6
Supply Voltage
Temperature
-
V
℃
uA
V
-40
105
-
-
0.5
ILVR
Operating Current
Threshold Voltage
Operating Current
-
-
AVDD = 3.6V
1.5
65
VLVR *
IBOD
-
-
-
-
μA
AVDD = 3.6V
BODVL
(SYS_BODCTL[18:16])
= 111
BODVL
(SYS_BODCTL[18:16])
= 110
BODVL
(SYS_BODCTL[18:16])
= 101
BODVL
(SYS_BODCTL[18:16])
= 100
BODVL
(SYS_BODCTL[18:16])
= 011
BODVL
(SYS_BODCTL[18:16])
= 010
BODVL
(SYS_BODCTL[18:16])
= 001
BODVL
(SYS_BODCTL[18:16])
= 000
BODVL
(SYS_BODCTL[18:16])
= 111
BODVL
(SYS_BODCTL[18:16])
= 110
BODVL
(SYS_BODCTL[18:16])
= 101
BODVL
(SYS_BODCTL[18:16])
= 100
BODVL
(SYS_BODCTL[18:16])
= 011
BODVL
(SYS_BODCTL[18:16])
= 010
BODVL
(SYS_BODCTL[18:16])
= 001
BODVL
(SYS_BODCTL[18:16])
= 000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.8
2.6
2.4
2.2
2.0
1.8
1.6
3
Brown-out Voltage
(Falling edge)
VBOD_F
2.8
2.6
2.4
2.2
2.0
1.8
1.6
Brown-out Voltage
(Rising edge)
VBOD_R
-
-
-
-
TBOD_RE
VPOR
Respond Time
Reset Voltage
1
ms
V
1.45
VDD Raising Rate to Ensure
Power-on Reset
-
-
RRVDD
10
us/V
Feb 15, 2019
Page 219 of 245
Rev 1.01
M2351
VDD Falling Rate to Ensure
-
-
-
-
FRVDD
tPOR
500
500
us/V
us
Power-on Reset
Minimum Time for VDD Stays at VPOR to Ensure Power-on
Reset
Note :
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power-up Ramp Condition
Feb 15, 2019
Page 220 of 245
Rev 1.01
M2351
8.5.4 Internal Voltage Reference
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
Typ
1.6
2.0
2.5
3.0
-
Max Unit
Comments
AVDD > 2.0v
AVDD > 2.2v
AVDD > 2.7v
AVDD > 3.2v
-
-
-
-
-
-
-
-
VREF_INT
Internal reference voltage
V
-
-
2
ms
us
CL =4.7 uF, VREF initial=0
CL =0.1 uF, VREF initial=0
Ts
stable time
-
48
Note: Guaranteed by characterization, not tested in production.
VREF
1uF
Figure 8.5-2 Typical Connection with Internal Voltage Reference
Feb 15, 2019
Page 221 of 245
Rev 1.01
M2351
8.5.5 12-bit ADC
8.5.5.1 Fast Speed Channel
Symbol
AVDD
VREF
Parameter
Operating voltage
Min.[*1]
Typ.
Max.[*1]
Unit
V
Test Conditions
AVDD = VDD
3.3
-
-
AVDD
-
3.6
-
Reference voltage
V
℃
TA
Temperature
-40
105
Operating current (AVDD current)
AVDD = VDD =VREF = 3.3V
ADC Clock Rate = 64 MHz
High speed channel
IADC
470
-
520
uA
(Enable ADC and disable all other
analog modules)
Resolution
-
0
-
12
VREF
64
Bit
V
VIN
FADC
TSMP
TCONV
FSPS
TPU
ADC channel input voltage
ADC Clock frequency
Sampling Time
-
0.14
3
-
MHz
1/FADC
High speed channel
-
258
272
3.76
-
Conversion time
17
-
1/FADC TCONV = TSMP + 14
MSPS High speed channel
μs
Sampling Rate (FADC/TCONV
Power-up time
)
-
-
20
-
INL
Integral Non-Linearity Error
-6.6
-1
-
2.7
6.6
2.0
3.0
6.5
-
LSB
LSB
LSB
LSB
LSB
pF
VREF = AVDD
VREF = AVDD
VREF = AVDD
VREF = AVDD
VREF = AVDD
DNL
EG
Differential Non-Linearity Error
Gain error
-
-0.6
-0.37
-5.94
-
-
EOFFSET
EA
Offset error
-
Absolute Error
-
CIN
Internal Capacitance[*1]
Monotonic
5
-
Guaranteed
-
Note:
1. Guaranteed by characterization, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
ꢙ
signal and reduce the ADC accuracy. ꢖꢗꢘ ꢃꢄꢚ
ꢍ ꢥꢄꢖꢐꢦ
ꢠꢣꢤ
ꢄꢇꢄꢞ ꢄꢇꢡꢢꢄꢈꢅ
ꢟꢠ
ꢛꢜꢝ
8.5.5.2 Low Speed Channel
Symbol
AVDD
VREF
Parameter
Min. [*1] Typ. Max. [*1] Unit
Test Conditions
AVDD = VDD
Operating voltage
Reference voltage
Temperature
1.7
-
-
AVDD
-
3.6
-
V
V
℃
TA
-40
105
Feb 15, 2019
Page 222 of 245
Rev 1.01
M2351
Symbol
Parameter
Min. [*1] Typ. Max. [*1] Unit
Test Conditions
AVDD = VDD =VREF = 3.3V
ADC Clock Rate = 34 MHz
low speed channel
223
140
112
72
-
-
-
-
237
147
119
75
IADC1
uA
uA
AVDD = VDD =VREF = 1.7V
ADC Clock Rate = 34 MHz
low speed channel
Operating current (AVDD current)
(Enable ADC and disable all other
analog modules)
AVDD = VDD =VREF = 3.3V
ADC Clock Rate = 14 MHz
low speed channel
IADC2
AVDD = VDD =VREF = 1.7V
ADC Clock Rate = 14 MHz
low speed channel
Resolution
-
0
-
12
VREF
64
Bit
V
VIN
FADC
TSMP
TCONV
FSPS
TPU
ADC channel input voltage
ADC Clock frequency
Sampling Time
-
0.14
3
-
MHz Low speed channel
1/FADC
-
258
272
2
Conversion time
17
-
-
1/FADC TCONV = TSMP + 14
MSPS Low speed channel
μs
Sampling Rate (FADC/TCONV
Power-up time
)
-
20
-3.4
-1
-
-
INL
Integral Non-Linearity Error
-
4.1
2.1
3.6
2.8
7.3
-
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
LSB VREF = AVDD
pF
DNL
EG
Differential Non-Linearity Error
Gain error
-
-3.1
-1.3
2.8
-
-
EOFFSET
EA
Offset error
-
Absolute Error
-
CIN
Internal Capacitance[*1]
Monotonic
5
-
Guaranteed
-
Note: Guaranteed by characterization, not tested in production.
Feb 15, 2019
Page 223 of 245
Rev 1.01
M2351
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer
curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve.
Note: GND < EADC_CHx < VREF
VDD
RIN
12-bit
Converter
EADC_CHx
CIN
Figure 8.5-3 Typical Connection Using the ADC
Feb 15, 2019
Page 224 of 245
Rev 1.01
M2351
8.5.6 Temperature Sensor
Symbol
Parameter
Min Typ Max
Unit
VDD
TA
Operating Voltage
1.7
40
-
-
-
3.6
105
-
V
Temperature Range
°C
ITEMP
Tc
Current Consumption [*3]
Temperature Coefficient [*3]
16
A
mV/°C
mV
-1.77 -1.82 -1.86
Vos
tS
Offset Voltage when TA = 0°C [*3]
710
720
1
730
Stable time[*2]
-
-
-
-
µs
ADC sampling time when reading the temperature (5pF cap load) [*1]
3
µs
TS_temp
Note:
1. VTEMP (mV) = Temperature Coefficient (mV/°C) x Temperature (°C) + Offset (mV)
2. Guaranteed by design, not tested in production
3. Guaranteed by characteristic, not tested in production
8.5.7 Digital to Analog Converter (DAC)
Symbol
Parameter
Analog supply voltage
Min
Typ
-
Max Unit
Comments
AVDD
3.6
1.8
V
bit
V
NR
Resolution
12
VREF
AVDD
±2
VREF ≤ AVDD
Reference supply voltage
1.5
-
-
-
-
-
-
-
-
LSB 12-bit mode
DNL
INL
Differential non-linearity error[*4]
Integral non-linearity error[*4]
±0.5 LSB 10-bit mode
±4
±1
LSB 12-bit mode
LSB 10-bit mode
12-bit mode
LSB
-
-
±6
DACOUT buffer ON
OE
Offset Error[*4]
12-bit mode
-
-
-
-
-
±4
±2
4
LSB
DACOUT buffer OFF
LSB 10-bit mode
12-bit mode
LSB
-12
DACOUT buffer ON
GE
AE
Gain Error[*4]
12-bit mode
-
-
-
-
-
-
±4
±2
LSB
DACOUT buffer OFF
LSB 10-bit mode
12-bit mode
LSB
Absolute Error[*4]
±10
DACOUT buffer ON
Feb 15, 2019
Page 225 of 245
Rev 1.01
M2351
12-bit mode
-
-
±4
LSB
DACOUT buffer OFF
-
-
-
±2
LSB 10-bit mode
℃
TA
Temperature
Monotonic
-40
105
10-bit guaranteed
AVDD
-
VO
Output Voltage
0.2
-
V
DACOUT buffer ON
0.2
Resistive load[*2]
7.5
-
10
-
-
kΩ DACOUT buffer ON
kΩ DACOUT buffer OFF
RLOAD
Ro
Output impedance[*4]
Capacitive load[*3]
-
-
12
50
CLOAD
pF
-
-
AV
DD = 3.6V, no load, lowest code
175
390
-
195
426
240
(0x000)
Current consumption on AVDD supply[*4]
Current consumption on AVDD supply[*4]
Settling Time
IAVDD
IREF
TS
A
-
AV
DD = 3.6V, no load, middle code
(0x800)
VREF =3.6V, no load, middle code
(0x800)
170
A
Full scale: for a 12-bit input code
transition between the lowest and the
highest input codes when DAC_OUT
reaches final value +/-1 LSB,
-
-
5
1
6
-
μs
CLOAD
RLOAD
=50p,
=7.5k
Max frequency for a correct DAC_OUT
Fs
Update Rate
MSPSchange from core i to i+1LSB, CLOAD
50pF and RLOAD >= 5Kohm
=
Wakeup time from OFF state. Input
μs code between lowest and highest
possible codes.
TWAKEUP
PSRR
Wake-up Time
-
-
9
15
Power Supply Rejection Ratio[*1]
-60
-40
dB No RLOAD, CLOAD = 50pF
Note:
1. Guaranteed by design, not tested in production
2. Resistive load between DACOUT and AVSS
.
3. Capacitive load at DACOUT pin.
4. Guaranteed based on test during characterization.
Feb 15, 2019
Page 226 of 245
Rev 1.01
M2351
8.5.8 Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 3.6V and maximum ambient temperature (TA), and
the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Min
Typ
-
Max Unit
Comments
AVDD
3.6
1.8
V
℃
TA
Temperature
-40
-
105
-
-
-
-
MODESEL[1:0] = 00
-
1.5
2.9
11.4
39.3
-
MODESEL[1:0] = 01
MODESEL[1:0] = 10
MODESEL[1:0] = 11
-
-
IDD
Operating current
A
-
0.1
AVDD
0.1
Input common mode voltage range [*2]
-
VCM
VDI
Differential input voltage sensitivity [*2]
Input offset voltage
10
-
20
-
-
12
-
mV Hysteresis disable
mV Hysteresis disable,
HYSSEL[1:0] = 00
Voffset
-
0
-
15
28
39
70
-
-
HYSSEL[1:0] = 01
mV
Vhys
Hysteresis window
DC voltage Gain[*1]
-
-
HYSSEL[1:0] = 10
-
-
HYSSEL[1:0] = 11
Av
-
-
dB
-
Hysteresis disable MODESEL[1:0] = 00
0.14
0.2
0.7
1.5
82
124
-
-
Hysteresis disable MODESEL[1:0] = 01
Td
Propagation delay[*2]
us
-
-
Hysteresis disable MODESEL[1:0] = 10
-
-
Hysteresis disable MODESEL[1:0] = 11
Hysteresis disable MODESEL[1:0] = 00
-
-
-
-
Hysteresis disable MODESEL[1:0] = 01
TSetup
Setup time[*2]
ns
-
-
Hysteresis disable MODESEL[1:0] = 10
274
419
-
-
Hysteresis disable MODESEL[1:0] = 11
Note:
1. Guaranteed by design, not tested in production.
2. Guaranteed by characteristic, not tested in production.
Feb 15, 2019
Page 227 of 245
Rev 1.01
M2351
8.6
Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
1.08
10000
10
Typ
Max
1.32
-
Unit
V
Test Condition
[1]
VFLA
NENDUR
TRET
-
cycles[2]
year
mS
Data Retention
-
-
-
-
-
-
-
-
160
320
50
TERASE
TMER
TPROG
IDD1
Page Erase Time
Mass Erase Time
Program Time
Read Current
92
201
42
-
TA = 25℃
uS
mA
mA
uA
4.12
5
IDD2
Program Current
Erase Current
-
IDD3
-
5
Note:
1. VFLA is source from chip LDO output voltage.
2. Number of program/erase cycles.
3. This table is guaranteed by design, not test in production.
Feb 15, 2019
Page 228 of 245
Rev 1.01
M2351
8.7
I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min
4.7
Max
-
Min
1.2
Max
tLOW
SCL low period
SCL high period
-
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
4
4.7
4
0.6
1.2
0.6
0.6
tHIGH
-
-
-
-
-
-
-
tSU; STA
tHD; STA
tSU; STO
tBUF
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
-
-
4
-
4.7 [3]
1.2 [3]
100
-
tSU;DAT
tHD;DAT
tr
Data setup time
250
-
Data hold time
0 [4]
3.45 [5]
1000
20+0.1Cb [4]
-
0.8[5]
300
300
400
SCL/SDA rise time
-
-
-
300
400
tf
SCL/SDA fall time
-
-
Cb
Capacitive load for each bus line
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz
to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL
signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.7-1 I2C Timing Diagram
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8.8
SPI Dynamic Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
SPI Master Mode (VDD = 3.0~3.6 V, 30 PF loading Capacitor)
ns
ns
ns
ns
ns
tCLKL
tCLKH
tDS
Clock output High time [*1]
Clock output Low time [*1]
Data setup time
-
-
-
-
TSPICLK / 2
TSPICLK / 2
0
2
-
-
-
-
tDH
Data hold time
-
tV
Data output valid time
0
1
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.8-1 SPI Master Mode Timing Diagram
Symbol
Parameter
Min
Typ
Max
Unit
SPI Slave Mode (VDD = 3.0~3.6V, 30 PF Loading Capacitor)
tCLKL
tCLKH
tSS
Clock output High time [*1]
Clock output Low time [*1]
Slave select setup time
Slave select hold time
Data input setup time
Data input hold time
-
-
TSPICLK / 2
Peripheral clock
-
TSPICLK / 2
Peripheral clock
1 TSPICLK + 2ns
-
-
-
-
-
-
-
Peripheral clock
tSH
1 TSPICLK
Peripheral clock
tDS
0
2
-
-
ns
ns
ns
tDH
-
tV
Data output valid time
8
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Clock output High time [*1]
-
-
TSPICLK / 2
ns
tCLKH
Note: The minimum clock period for SPICLK is 41.67 ns (24 MHz).
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Figure 8.8-2 SPI Slave Mode Timing Diagram
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8.9
I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min
39
39
2
Max
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
12
-
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
1
WS setup time
WS hold time
24
0
-
-
I2S slave input clock
duty cycle
DuCy(SCK)
35
65
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
22
10
7
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
8
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
21
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
7
-
0
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
LSB receive(2)
SDreceive
LSB receive
Figure 8.9-1 I2S Master Mode Timing Diagram
Feb 15, 2019
Page 232 of 245
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M2351
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.9-2 I2S Slave Mode Timing Diagram
Feb 15, 2019
Page 233 of 245
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M2351
8.10 USCI - I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min
4.7
4
Max
Min
Max
tLOW
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL low period
SCL high period
-
1.2
-
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
1.2
-
-
-
-
0.6
4
0.6
-
4.7 [3]
250
0 [4]
-
-
1.2 [3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45 [5]
1000
300
400
20+0.1Cb [4]
0.8[5]
300
300
400
SCL/SDA rise time
-
-
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz
to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL
signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.10-1 I2C Timing Diagram
Feb 15, 2019
Page 234 of 245
Rev 1.01
M2351
8.11 USCI - SPI Dynamic Characteristics
Symbol
tCLKH
tCLKL
Parameter
Clock output High time [*1]
Clock output Low time [*1]
Data setup time
Min
Typ
Max
Unit
ns
-
-
-
-
-
-
TSPICLK / 2
ns
ns
ns
ns
TSPICLK / 2
tDS
0
2
-
-
tDH
Data hold time
tV
Data output valid time
-
0
1
Note: The minimum clock period for SPICLK is 41.67 ns (24 MHz).
tCLKH
tCLKL
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.11-1 SPI Master Mode Timing Diagram
Symbol
Parameter
Min
Typ
Max
Unit
ns
tCLKH
tCLKL
tSS
Clock output High time [*1]
Clock output Low time [*1]
Slave select setup time
Slave select hold time
Data input setup time
Data input hold time
-
-
-
TSPICLK / 2
ns
ns
ns
TSPICLK / 2
1 TSPICLK + 2ns
1 TSPICLK
-
-
-
-
-
-
tSH
tDS
0
2
-
-
ns
ns
tDH
-
8
tV
Data output valid time
Clock output High time [*1]
ns
ns
tCLKH
-
-
TSPICLK / 2
Feb 15, 2019
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M2351
Note: The minimum clock period for SPICLK is 41.67 ns (24 MHz).
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.11-2 SPI Slave Mode Timing Diagram
Feb 15, 2019
Page 236 of 245
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M2351
8.12 USB Characteristics
8.12.1 USB Full-Speed PHY Characteristics
Symbol
VDD
Parameter
Min
3
Typ
Max
3.6
-
Unit
V
Test Conditions
Power
3.3
-
VIH
Input High (driven)
Input Low
2.0
-
-
-
-
V
VIL
0.8
-
V
-
VDI
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
0.8
0.8
-
-
2.5
2.0
V
V
Includes VDI range
-
Common-mode Range
Single-ended Receiver
Threshold
VSE
Receiver Hysteresis
Output Low (driven)
Output High (driven)
Output Signal Cross Voltage
Pull-up Resistor
-
200
-
mV
V
-
-
-
-
-
VOL
VOH
VCRS
RPU
RPD
0
-
-
-
-
-
0.3
2.8
3.6
V
1.3
2.0
V
1.425
14.25
1.575
15.75
kΩ
kΩ
Pull-down Resistor
Termination Voltage for Uptream
port pull up (RPU)
VTRM
3.0
-
3.6
V
ZDRV
CIN
Driver Output Resistance
Transceiver Capacitance
Rise Time
-
-
10
-
-
20
Ω
pF
ns
ns
%
Steady state drive*
Pin to GND
CL=50p
TFR
4
-
20
TFF
Fall Time
4
-
20
CL=50p
TFRFF
Rise and Fall Time Matching
90
-
111.11
TFRFF=TFR/TFF
Note:
1. Guaranteed by design, not tested in production.
2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the
USB_VDD33_CAP pin and the closest GND pin of the device.
3. USB_D+ and USB_D- must be connected with series resistors to fit USB Full-speed spec request (28 ~ 44Ω).
Feb 15, 2019
Page 237 of 245
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M2351
8.13 SDIO Characteristics
8.13.1 Default Mode Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
SD_CLK Period
TP_SD_CLK
40
-
-
ns
-
(Data Transfer Mode)
SD_CLK Period
TP_SD_CLK_ID
2,500
-
-
ns
(Identification Mode)
TH_SD_CLK
TL_SD_CLK
SD_CLK High Time
-
-
20
20
-
-
ns
ns
-
-
SD_CLK Low Time
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
THD_SD_IN
5
5
-
-
-
-
-
-
ns
ns
ns
-
-
-
SD_DATA Hold Time from SD_CLK Rising
SD_CLK Falling to
TDLY_SD_OUT
14
Valid SD_DATA Delay
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 8.13-1 SDIO Default Mode
Feb 15, 2019
Page 238 of 245
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M2351
8.13.2 SDIO Dynamic Characteristics
Symbol
TP_SD_CLK
TH_SD_CLK
TL_SD_CLK
Parameter
Min
20
7
Typ
Max
Unit
ns
Test Condition
SD_CLK Period
-
-
-
-
-
-
-
-
-
SD_CLK High Time
SD_CLK Low Time
ns
7
ns
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
THD_SD_IN
6
2
-
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
SD_DATA Hold Time from SD_CLK Rising
SD_CLK Falling to
TDLY_SD_OUT
-
14
-
Valid SD_DATA Delay
THD_SD_OUT SD_DATA Hold Time from SD_CLK Rising
2.5
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 8.13-2 SDIO High-speed Mode
Feb 15, 2019
Page 239 of 245
Rev 1.01
M2351
9 PACKAGE DIMENSIONS
9.1 QFN 33 (5x5x0.8 mm Pitch 0.5 mm)
Feb 15, 2019
Page 240 of 245
Rev 1.01
M2351
9.2 LQFP 64 (7x7x1.4 mm Footprint 2.0 mm)
Feb 15, 2019
Page 241 of 245
Rev 1.01
M2351
9.3 LQFP 128 (14x14x1.4 mm Footprint 2.0 mm)
Feb 15, 2019
Page 242 of 245
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M2351
10 ABBREVIATIONS
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EADC
EBI
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Feb 15, 2019
Page 243 of 245
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M2351
SD
Secure Digital
SPI
Serial Peripheral Interface
Samples per Second
Triple Data Encryption Standard
Touch Key
SPS
TDES
TK
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Feb 15, 2019
Page 244 of 245
Rev 1.01
M2351
11 REVISION HISTORY
Date
Revision
Description
2018.08.24
2019.02.15
1.00
Initial version.
1.01
Added electrical characteristics information.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Feb 15, 2019
Page 245 of 245
Rev 1.01
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