M251SC2AE [NUVOTON]
Arm® Cortex®-M 32-bit Microcontroller;
| 型号： | M251SC2AE |
| 厂家： | 
NUVOTON |
| 描述： | Arm® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总266页 (文件大小：4576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M251/M252
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M251/M252 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
July 2, 2020
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TABLE OF CONTENTS
1 GENERAL DESCRIPTION.............................................................................12
2 FEATURES.....................................................................................................14
2.1 M251/M252 Series Features......................................................................................14
3 PARTS INFORMATION .................................................................................29
3.1 Package Type...............................................................................................................29
3.2 M251/M252 Series Selection Guide .........................................................................30
3.2.1 M251 Base Series (M251Fx / M0251Ex / M0251Zx)................................................ 30
3.2.2 M251 Base Series (M251Lx)........................................................................................ 31
3.2.3 M251 Base Series (M251Sx) ....................................................................................... 33
3.2.4 M251 Base Series (M251Kx) ....................................................................................... 34
3.2.5 M252 USB Series (M252Fx / M0252Ex / M0252Zx) ................................................ 35
3.2.6 M252 USB Series (M252Lx)......................................................................................... 37
3.2.7 M252 USB Series (M252Sx) ........................................................................................ 38
3.2.8 M252 USB Series (M252Kx) ........................................................................................ 39
3.2.9 Naming Rule................................................................................................................... 40
4 PIN CONFIGURATION...................................................................................41
4.1 Pin Configuration..........................................................................................................41
4.1.1 M251 Series Pin Diagram............................................................................................. 41
4.1.2 M251 Series Multi-function Pin Diagram.................................................................... 47
4.1.3 M252 Series Pin Diagram............................................................................................. 84
4.1.4 M252 Series Function Pin Diagram ............................................................................ 90
4.2 Pin Mapping................................................................................................................126
4.3 Pin Function Description...........................................................................................131
5 BLOCK DIAGRAM.......................................................................................137
5.1 M251/M252 Block Diagram......................................................................................137
6 FUNCTIONAL DESCRIPTION .....................................................................138
6.1 Arm® Cortex®-M23 Core ...........................................................................................138
6.2 System Manager........................................................................................................140
6.2.1 Overview ....................................................................................................................... 140
6.2.2 System Reset ............................................................................................................... 140
6.2.3 System Power Distribution ......................................................................................... 146
6.2.4 Power Modes and Wake-up Sources........................................................................ 147
6.2.5 Chip Bus Matrix............................................................................................................ 151
6.2.6 System Memory Map................................................................................................... 151
6.2.7 SRAM Memory Orginization....................................................................................... 153
6.2.8 IRC Auto Trim ............................................................................................................... 154
6.2.9 UART0_TXD/USCI0_DAT0 Modulation with PWM................................................. 154
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6.2.10System Timer (SysTick) .............................................................................................. 155
6.2.11Nested Vectored Interrupt Controller (NVIC) ........................................................... 156
6.3 Clock Controller..........................................................................................................160
6.3.1 Overview ....................................................................................................................... 160
6.3.2 Clock Generator........................................................................................................... 162
6.3.3 System Clock and SysTick Clock .............................................................................. 163
6.3.4 Peripherals Clock......................................................................................................... 164
6.3.5 Power-down Mode Clock............................................................................................ 164
6.3.6 Clock Output................................................................................................................. 165
6.3.7 USB Clock Source....................................................................................................... 166
6.4 Flash Memeory Controller (FMC)............................................................................167
6.4.1 Overview ....................................................................................................................... 167
6.4.2 Features ........................................................................................................................ 167
6.5 General Purpose I/O (GPIO)....................................................................................168
6.5.1 Overview ....................................................................................................................... 168
6.5.2 Features ........................................................................................................................ 168
6.6 PDMA Controller (PDMA).........................................................................................169
6.6.1 Overview ....................................................................................................................... 169
6.6.2 Features ........................................................................................................................ 169
6.7 Timer Controller (TMR) .............................................................................................170
6.7.1 Overview ....................................................................................................................... 170
6.7.2 Features ........................................................................................................................ 170
6.8 Watchdog Timer (WDT) ............................................................................................172
6.8.1 Overview ....................................................................................................................... 172
6.8.2 Features ........................................................................................................................ 172
6.9 Window Watchdog Timer (WWDT) .........................................................................173
6.9.1 Overview ....................................................................................................................... 173
6.9.2 Features ........................................................................................................................ 173
6.10 Real Time Clock (RTC) .......................................................................................174
6.10.1Overview ....................................................................................................................... 174
6.10.2Features ........................................................................................................................ 174
6.11 Basic PWM Generator and Capture Timer (BPWM) ......................................175
6.11.1Overview ....................................................................................................................... 175
6.11.2Features ........................................................................................................................ 175
6.12 PWM Generator and Capture Timer (PWM)....................................................176
6.12.1Overview ....................................................................................................................... 176
6.12.2Features ........................................................................................................................ 176
6.13 UART Interface Controller (UART)....................................................................178
6.13.1Overview ....................................................................................................................... 178
6.13.2Features ........................................................................................................................ 178
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6.14 Smart Card Host Interface (SC).........................................................................180
6.14.1Overview ....................................................................................................................... 180
6.14.2Features ........................................................................................................................ 180
6.15 Serial Peripheral Interface (SPI)........................................................................181
6.15.1Overview ....................................................................................................................... 181
6.15.2Features ........................................................................................................................ 181
6.16 Quad Serial Peripheral Interface (QSPI)..........................................................182
6.16.1Overview ....................................................................................................................... 182
6.16.2Features ........................................................................................................................ 182
6.17 I2C Serial Interface Controller (I2C) ...................................................................183
6.17.1Overview ....................................................................................................................... 183
6.17.2Features ........................................................................................................................ 183
6.18 USCI - Universal Serial Control Interface Controller (USCI).........................184
6.18.1Overview ....................................................................................................................... 184
6.18.2Features ........................................................................................................................ 184
6.19 USCI – UART Mode.............................................................................................185
6.19.1Overview ....................................................................................................................... 185
6.19.2Features ........................................................................................................................ 185
6.20 USCI - SPI Mode..................................................................................................186
6.20.1Overview ....................................................................................................................... 186
6.20.2Features ........................................................................................................................ 186
6.21 USCI - I2C Mode...................................................................................................188
6.21.1Overview ....................................................................................................................... 188
6.21.2Features ........................................................................................................................ 188
6.22 Programmable Serial IO (PSIO) ........................................................................189
6.22.1Overview ....................................................................................................................... 189
6.22.2Features ........................................................................................................................ 189
6.23 External Bus Interface (EBI)...............................................................................191
6.23.1Overview ....................................................................................................................... 191
6.23.2Features ........................................................................................................................ 191
6.24 USB 1.1 Device Controller (USBD)...................................................................192
6.24.1Overview ....................................................................................................................... 192
6.24.2Features ........................................................................................................................ 192
6.25 CRC Controller (CRC).........................................................................................193
6.25.1Overview ....................................................................................................................... 193
6.25.2Features ........................................................................................................................ 193
6.26 Enhanced 12-bit Analog-to-Digital Converter (EADC) ...................................194
6.26.1Overview ....................................................................................................................... 194
6.26.2Features ........................................................................................................................ 194
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6.27 Digital to Analog Converter (DAC).....................................................................196
6.27.1Overview ....................................................................................................................... 196
6.27.2Features ........................................................................................................................ 196
6.28 Analog Comparator Controller (ACMP)............................................................197
6.28.1Overview ....................................................................................................................... 197
6.28.2Features ........................................................................................................................ 197
6.29 OP Amplifier (OPA) ..............................................................................................198
6.29.1Overview ....................................................................................................................... 198
6.29.2Features ........................................................................................................................ 198
6.30 Peripherals Interconnection................................................................................199
6.30.1Overview ....................................................................................................................... 199
6.30.2Peripherals Interconnect Matrix table ....................................................................... 199
7 APPLICATION CIRCUIT ..............................................................................200
7.1 Power Supply Scheme..............................................................................................200
7.2 Peripheral Application Scheme................................................................................201
8 ELECTRICAL CHARACTERISTICS............................................................202
8.1 Absolute Maximum Ratings......................................................................................202
8.1.1 Voltage Characteristics ............................................................................................... 202
8.1.2 Current Characteristics ............................................................................................... 202
8.1.3 Thermal Characteristics.............................................................................................. 203
8.1.4 EMC Characteristics.................................................................................................... 204
8.1.5 Package Moisture Sensitivity (MSL) ......................................................................... 206
8.1.6 Soldering Profile........................................................................................................... 207
8.2 General Operating Conditions .................................................................................208
8.3 DC Electrical Characteristics....................................................................................209
8.3.1 Supply Current Characteristics for M251xC/M251xD/M252xC/M252xD............. 209
8.3.2 Supply Current Characteristics for M251xE/M251xG/M252xE/M252xG............. 212
8.3.3 On-Chip Peripheral Current Consumption ............................................................... 215
8.3.4 Wakeup Time from Low-Power Modes..................................................................... 216
8.3.5 I/O Current Injection Characteristics ......................................................................... 217
8.3.6 I/O DC Characteristics................................................................................................. 217
8.4 AC Electrical Characteristics....................................................................................220
8.4.1 48 MHz Internal High Speed RC Oscillator (HIRC) ................................................ 220
8.4.2 4 MHz Internal Median Speed RC Oscillator (MIRC) ............................................. 221
8.4.3 38.4 kHz Internal Low Speed RC Oscillator (LIRC)................................................ 222
8.4.4 External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) Characteristics
223
8.4.5 External 4~32 MHz High Speed Clock Input Signal Characteristics.................... 226
8.4.6 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
for M251xC/M251xD/M252xC/M252xD ............................................................................... 226
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8.4.7 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
for M251xE/M251xG/M252xE/M252xG............................................................................... 228
8.4.8 External 32.768 kHz Low Speed Clock Input Signal Characteristics................... 229
8.4.9 PLL Characteristics...................................................................................................... 230
8.4.10I/O AC Characteristics................................................................................................. 231
8.5 Analog Characteristics ..............................................................................................233
8.5.1 LDO................................................................................................................................ 233
8.5.2 Reset and Power Control Block Characteristics...................................................... 233
8.5.3 12-bit SAR Analog to Digital Converter (ADC) ........................................................ 235
8.5.4 Analog Comparator Controller (ACMP) .................................................................... 238
8.5.5 Digital to Analog Converter (DAC)............................................................................. 239
8.5.6 OP Amplifier (OPA) ...................................................................................................... 241
8.5.7 Internal Voltage Reference......................................................................................... 242
8.5.8 Temperature Sensor.................................................................................................... 243
8.6 Communications Characteristics.............................................................................244
8.6.1 SPI Dynamic Characteristics...................................................................................... 244
8.6.2 SPI - I2S Dynamic Characteristics............................................................................. 247
8.6.3 I2C Dynamic Characteristics....................................................................................... 249
8.6.4 USCI - SPI Dynamic Characteristics......................................................................... 250
8.6.5 USCI-I2C Dynamic Characteristics............................................................................ 253
8.6.6 USB Characteristics .................................................................................................... 254
8.7 Flash DC Electrical Characteristics.........................................................................255
9 PACKAGE DIMENSIONS ............................................................................256
9.1 TSSOP20 (4.4x6.5x0.9 mm3)...................................................................................256
9.2 TSSOP28 (4.4x9.7x1.0 mm3)...................................................................................257
9.3 QFN 33L (5x5x0.8 mm3) ...........................................................................................258
9.4 LQFP 48L (7x7x1.4 mm3 Footprint 2.0 mm)..........................................................260
9.5 LQFP 64L (7x7x1.4 mm3 Footprint 2.0 mm)..........................................................261
9.6 LQFP 128L (14x14x1.4 mm3 Footprint 2.0 mm) ...................................................262
10ABBREVIATIONS ........................................................................................263
10.1 Abbreviations........................................................................................................263
11REVISION HISTORY....................................................................................265
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LIST OF FIGURES
Figure 4.1-1 M251 Series TSSOP 20-pin Diagram ........................................................................41
Figure 4.1-2 M251 Series TSSOP 28-pin Diagram ........................................................................41
Figure 4.1-3 M251 Series QFN 33-pin Diagram.............................................................................42
Figure 4.1-4 M251 Series LQFP 48-pin Diagram...........................................................................43
Figure 4.1-5 M251 Series LQFP 64-pin Diagram without VBAT ......................................................44
Figure 4.1-6 M251 Series LQFP 64-pin Diagram with VBAT ...........................................................45
Figure 4.1-7 M251 Series LQFP 128-pin Diagram.........................................................................46
Figure 4.1-8 M251FC2AE Multi-function Pin Diagram ...................................................................47
Figure 4.1-9 M251EC2AE Multi-function Pin Diagram...................................................................48
Figure 4.1-10 M251ZC2AE Multi-function Pin Diagram .................................................................50
Figure 4.1-11 M251ZD2AE Function Pin Diagram.........................................................................52
Figure 4.1-12 M251LC2AE/M251LD2AE Multi-function Pin Diagram............................................54
Figure 4.1-13 M251LE3AE Multi-function Pin Diagram..................................................................57
Figure 4.1-14 M251LG6AE Multi-function Pin Diagram .................................................................60
Figure 4.1-15 M251SC2AE/M251SD2AE Multi-function Pin Diagram...........................................63
Figure 4.1-16 M251SE3AE Multi-function Pin Diagram .................................................................66
Figure 4.1-17 M251SG6AE Multi-function Pin Diagram.................................................................70
Figure 4.1-18 M251KE3AE Multi-function Pin Diagram .................................................................74
Figure 4.1-19 M251KG6AE Multi-function Pin Diagram.................................................................79
Figure 4.1-20 M252 Series TSSOP 20-pin Diagram......................................................................84
Figure 4.1-21 M252 Series TSSOP 28-pin Diagram......................................................................84
Figure 4.1-22 M252 Series QFN 33-pin Diagram...........................................................................85
Figure 4.1-23 M252 Series LQFP 48-pin Diagram.........................................................................86
Figure 4.1-24 M252 Series LQFP 64-pin Diagram without VBAT ....................................................87
Figure 4.1-25 M252 Series LQFP 64-pin Diagram with VBAT .........................................................88
Figure 4.1-26 M252 Series LQFP 128-pin Diagram.......................................................................89
Figure 4.1-27 M252FC2AE Function Pin Diagram.........................................................................90
Figure 4.1-28 M252EC2AE Function Pin Diagram.........................................................................91
Figure 4.1-29 M252ZC2AE Function Pin Diagram.........................................................................93
Figure 4.1-30 M252ZD2A Function Pin Diagram ...........................................................................95
Figure 4.1-31 M252LC2AE/M252LD2AE Function Pin Diagram ...................................................98
Figure 4.1-32 M252LE3AE Function Pin Diagram .......................................................................101
Figure 4.1-33 M252LG6AE Function Pin Diagram.......................................................................104
Figure 4.1-34 M252SC2AE/M252SD2AE Function Pin Diagram.................................................107
Figure 4.1-35 M252SE3AE Function Pin Diagram.......................................................................110
Figure 4.1-36 M252SG3AE Function Pin Diagram ......................................................................113
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Figure 4.1-37 M252KE3AE Function Pin Diagram.......................................................................116
Figure 4.1-38 M252KG6AE Function Pin Diagram ......................................................................121
Figure 5.1-1 M251/M252 Block Diagram......................................................................................137
Figure 6.1-1 Cortex® -M23 Block Diagram ....................................................................................138
Figure 6.2-1 System Reset Sources.............................................................................................141
Figure 6.2-2 nRESET Reset Waveform .......................................................................................143
Figure 6.2-3 Power-on Reset (POR) Waveform...........................................................................143
Figure 6.2-4 Low Voltage Reset (LVR) Waveform .......................................................................144
Figure 6.2-5 Brown-out Detector (BOD) Waveform .....................................................................145
Figure 6.2-6 NuMicro® M251/M252 Power Distribution Diagram.................................................146
Figure 6.2-7 Power Mode State Machine.....................................................................................148
Figure 6.2-8 SRAM Memory Organization ...................................................................................153
Figure 6.3-1 Clock Generator Global View Diagram ....................................................................161
Figure 6.3-2 Clock Generator Block Diagram...............................................................................162
Figure 6.3-3 System Clock Block Diagram...................................................................................163
Figure 6.3-4 HXT Stop Protect Procedure....................................................................................164
Figure 6.3-5 SysTick Clock Control Block Diagram .....................................................................164
Figure 6.3-6 Clock Output Block Diagram....................................................................................165
Figure 6.3-7 USB Clock Source ...................................................................................................166
Figure 6.20-1 SPI Master Mode Application Block Diagram ........................................................186
Figure 6.20-2 SPI Slave Mode Application Block Diagram ..........................................................186
Figure 6.21-1 I2C Bus Timing .......................................................................................................188
Figure 6.22-1 PSIO Clock Control Diagram (8-bit Pre-scale Counter in Clock Controller)..........190
Figure 8.1-1 Soldering profile from J-STD-020C..........................................................................207
Figure 8.4-1 Typical Crystal Application Circuit............................................................................225
Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit ........................................................227
Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit ........................................................229
Figure 8.5-1 Power Ramp Up/Down Condition ............................................................................234
Figure 8.5-2 Typical Connection with Internal Voltage Reference ...............................................242
Figure 8.6-1 SPI Master Mode Timing Diagram...........................................................................244
Figure 8.6-2 SPI Slave Mode Timing Diagram.............................................................................246
Figure 8.6-3 I2S Master Mode Timing Diagram............................................................................247
Figure 8.6-4 I2S Slave Mode Timing Diagram..............................................................................248
Figure 8.6-5 I2C Timing Diagram..................................................................................................249
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram .................................................................250
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram ...................................................................252
Figure 8.6-8 USCI-I2C Timing Diagram ........................................................................................253
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List of Tables
Table 1-1 NuMicro® M251/M252 Series Key Features Support Table...........................................13
Table 4.1-1 M251FC2AE Multi-function Pin Table .........................................................................48
Table 4.1-2 M251EC2AE Multi-function Pin Table.........................................................................49
Table 4.1-3 M251ZC2AE Multi-function Pin Table .........................................................................51
Table 4.1-4 M251ZD2AE Multi-function Pin Table .........................................................................53
Table 4.1-5 M251LC2AE/M251LD2AE Multi-function Pin Table....................................................56
Table 4.1-6 M251LE3AE Multi-function Pin Table .........................................................................59
Table 4.1-7 M251LG6AE Multi-function Pin Table .........................................................................62
Table 4.1-8 M251SC2AE/M251SD2AE Multi-function Pin Table...................................................65
Table 4.1-9 M251SE3AE Multi-function Pin Table .........................................................................68
Table 4.1-10 M251SG6AE Multi-function Pin Table.......................................................................72
Table 4.1-11 M251KE3AE Multi-function Pin Table.......................................................................78
Table 4.1-12 M251KG6AE Multi-function Pin Table.......................................................................83
Table 4.1-13 M252FC2AE Multi-function Pin Table.......................................................................91
Table 4.1-14 M252EC2AE Multi-function Pin Table.......................................................................92
Table 4.1-15 M252ZC2AE Multi-function Pin Table.......................................................................94
Table 4.1-16 M252ZD2AE Multi-function Pin Table.......................................................................96
Table 4.1-17 M252LC2AE/M252LD2AE Multi-function Pin Table................................................100
Table 4.1-18 M252LE3AE Multi-function Pin Table .....................................................................103
Table 4.1-19 M252LG6AE Multi-function Pin Table.....................................................................106
Table 4.1-20 M252SC2AE/M252SD2AE Multi-function Pin Table...............................................109
Table 4.1-21 M252SE3AE Multi-function Pin Table.....................................................................112
Table 4.1-22 M252SG6AE Multi-function Pin Table.....................................................................115
Table 4.1-23 M252KE3AE Multi-function Pin Table.....................................................................120
Table 4.1-24 M252KG6AE Multi-function Pin Table.....................................................................125
Table 6.2-1 Reset Value of Registers...........................................................................................143
Table 6.2-2 Power Mode Table ....................................................................................................147
Table 6.2-3 Power Mode Difference Table...................................................................................147
Table 6.2-4 Power Mode Difference Table...................................................................................148
Table 6.2-5 Clocks in Power Modes.............................................................................................149
Table 6.2-6 Condition of Entering Power-down Mode Again .......................................................151
Table 6.2-7 Address Space Assignments for On-Chip Controllers ..............................................152
Table 6.2-8 Exception Model........................................................................................................157
Table 6.2-9 Interrupt Number Table .............................................................................................159
Table 6.13-1 UART Feature List...................................................................................................179
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Table 6.30-1 Peripherals Interconnect Matrix table......................................................................199
Table 8.1-1 Voltage Characteristics .............................................................................................202
Table 8.1-2 Current Characteristics..............................................................................................203
Table 8.1-3 Thermal Characteristics ............................................................................................203
Table 8.1-4 EMC Characteristics for M251xC/M251xD/M252xC/M252xD ..................................204
Table 8.1-5 EMC Characteristics for M251xE/M251xG/M252xE/M252xG ..................................205
Table 8.1-6 Package Moisture Sensitivity(MSL) ..........................................................................206
Table 8.1-7 Soldering Profile ........................................................................................................207
Table 8.2-1 General Operating Conditions...................................................................................208
Table 8.3-1 Current Consumption in Normal Run Mode..............................................................210
Table 8.3-2 Current consumption in Idle Mode ............................................................................210
Table 8.3-3 Chip Current Consumption in Power-down Mode.....................................................211
Table 8.3-4 Current consumption in Normal Run Mode...............................................................213
Table 8.3-5 Current Consumption in Idle Mode ...........................................................................213
Table 8.3-6 Chip Current Consumption in Power-down Mode.....................................................214
Table 8.3-7 Peripheral Current Consumption...............................................................................216
Table 8.3-8 Low-power Mode Wakeup Timings...........................................................................216
Table 8.3-9 I/O Current Injection Characteristics .........................................................................217
Table 8.3-10 I/O Input Characteristics..........................................................................................217
Table 8.3-11 I/O Output Characteristics.......................................................................................218
Table 8.3-12 nRESET Input Characteristics.................................................................................219
Table 8.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics............................220
Table 8.4-2 4 MHz Internal Median Speed RC Oscillator (MIRC) Characteristics.......................221
Table 8.4-338.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics ...........................222
Table 8.4-4 External 4~32 MHz High Speed Crystal (HXT) Oscillator.........................................223
Table 8.4-5 External 4~32 MHz High Speed Crystal Characteristics...........................................224
Table 8.4-6 External 4~32 MHz High Speed Clock Input Signal..................................................226
Table 8.4-7 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................227
Table 8.4-8 External 32.768 kHz Low Speed Crystal Characteristics..........................................227
Table 8.4-9 External 32.768 kHz Low Speed Crystal (LXT) Oscillator ........................................228
Table 8.4-10 External 32.768 kHz Low Speed Crystal Characteristics........................................228
Table 8.4-11 External 32.768 kHz Low Speed Clock Input Signal...............................................229
Table 8.4-12 PLL Characteristics .................................................................................................230
Table 8.4-13 I/O AC Characteristics.............................................................................................232
Table 8.5-1 Reset and power control unit.....................................................................................234
Table 8.5-2 ACMP Characteristics ...............................................................................................238
Table 8.6-1 SPI Master Mode Characteristics..............................................................................244
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Table 8.6-2 SPI Slave Mode Characteristics................................................................................245
Table 8.6-3 I2S Characteristics.....................................................................................................247
Table 8.6-4 I2C Characteristics.....................................................................................................249
Table 8.6-5 USCI-SPI Master Mode Characteristics....................................................................250
Table 8.6-6 USCI-SPI Slave Mode Characteristics......................................................................251
Table 8.6-7 USCI-I2C Characteristics...........................................................................................253
Table 8.6-8 USB Full-Speed Characteristics................................................................................254
Table 8.6-9 USB Full-Speed PHY Characteristics .......................................................................254
Table 10.1-1 List of Abbreviations................................................................................................264
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1 GENERAL DESCRIPTION
The NuMicro® M251/M252 series is a low-power microcontroller platform based on Arm® Cortex® -
M23 core for Armv8-M architecture. It runs up to 48 MHz with 32 ~ 256 Kbytes embedded Flash
memory and 8 ~ 32 Kbytes embedded SRAM, 4 Kbytes Flash loader memory (LDROM) for In-
System Programming (ISP). The 32-bit low-power microcontrollers supports wide supply voltage
from 1.75V ~ 5.5V and operating temperature range from -40℃ ~ +105℃.
Low-power Technology for IoT application
The NuMicro® M251/M252 series behaves low power consumption in Normal Run mode
138μA/MHz at 48MHz, Idle mode 60 μA/MHz, Power-down mode 2.5 μA (RTC on, RAM
retention), Power-down mode 1.7 μA (RTC off, RAM retention) and Deep Power-down mode. The
NuMicro® M251/M252 series integrates RTC with independent VBAT voltage source pin to support
low power mode with main power off and VBAT only. Its low power, wide supply voltage and fast
wake-up features make it suitable for battery-powered IoT applications.
Programmable Serial Interface (PSIO)
The NuMicro® M251/M252 series provides up to 8-channel Nuvoton proprietary interface, named
as “Programmable Serial I/O” (PSIO), which is capable of generating specific waveform to
emulate arbitrary serial communication protocols to connect with specific peripherals by PSIO
hardware engine. PSIO can be treated as extension of popular serial communication standard
(UART, SPI, I2C, etc.), niche serial communication standard and proprietary protocol (SPI-like
protocol for LED-lighting application, etc.). This PSIO hardware engine can simulate
comprehensive serial communication protocol with low CPU loading, low control complexity and
high timing precision at the same time. High elasticity and flexibility makes PSIO a powerful and
useful tool while connecting to diverse peripherals.
Voltage Adjustable Interface (VAI) - Support 2nd I/O voltage without level-shifter
The NuMicro® M251/M252 series integrates Voltage Adjustable Interface (VAI), up to 6 I/O pins to
support the 2nd I/O voltage from 1.65V ~ 5.5V to save level shifter components while connecting to
external devices. These 6 I/O pins can be configured as UART/SPI/ I2C bus by software setting.
eXecute-Only-Memory (XOM) - Protect the intelligent property of developers
The NuMicro® M251/M252 series provides 1-region programable eXecute-Only-Memory (XOM) to
secure critical program code. A tamper detection pin is implemented to avoid malicious damage
from hacker. The 96-bit Unique Identification (UID) and 128-bit Unique Customer Identification
(UCID) are used to enhance the product security.
Crystal-less USB 2.0 full speed device interface
Part numbers of the M252 series are all based on the M251. It supports a crystal-less USB 2.0 full
speed device that can generate precise frequency required by USB protocol without the need of
external crystal to reduce the BOM cost and PCB size.
Rich Pheripherals for comprehensive product application scenarios
The NuMicro® M251/M252 series is equipped with plenty of peripherals such as Timers,
Watchdog Timers, RTC, PDMA, External Bus Interface (EBI), UART, Universal Serial Control
Interface (USCI), QSPI, SPI/ I²S, I2C, ISO-7816-3, GPIOs, up to 24 channels of PWM, makes it
highly suitable for connecting comprehensive external modules and LED lighting control. The
NuMicro® M251/M252 series integrates high performance analog front-end circuit blocks, such as
16 channels of 12-bit 880 kSPS ADC, 12-bit 1 MSPS DAC, analog comparator, operational
amplifier, temperature sensor, low voltage reset (LVR) and brown-out detector (BOD) to enhance
product performance, reduce external components and form factor simultaneously.
The NuMicro® M251/M252 series provides 28 product types. The package types of the
M251/M252 series include TSSOP20 (4.4mm x 6.5mm), TSSOP28 (4.4mmx9.7mm), QFN33
(5mm x 5mm), LQFP48 (7mm x 7mm), LQFP64 (7mm x 7mm) and LQFP128 (14mm x 14mm).
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Pin-to-pin compatible in same package makes optimizing product features and performance easy.
Nuvoton NuMaker M251/M252 evaluation boards and Nu-Link debugger are available for
evaluation and product development. 3rd Party IDEs such as Keil MDK, IAR EWARM and
Eclippse IDE with GNU GCC compilers, are also supported.
Product Line UART
I2C
QSPI SPI/ I2S PSIO USCI Timer PWM PDMA EBI
ADC
DAC ACMP OPA USBD
M251/M252
3
2
1
1
8
3
4
24
8
1
16
1
2
1
1
Table 1-1 NuMicro® M251/M252 Series Key Features Support Table
The NuMicro® M251/M252 series is suitable for a wide range of applications such as:
Smart Home / Smart Home Appliance
Industrial Control / Industrial Automation
Smart City
IoT Device
Security Alarm System
Electronic Payments
Communication Modules
Portable Wireless Data Collector
Smart Door lock
Handheld Medical Device
(GPS) Location Tracker
Electronic Shelf Labels (ESL)
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2 FEATURES
2.1 M251/M252 Series Features
Core and System
Arm® Cortex® -M23 processor, running up to 48 MHz when VDD
1.75V ~ 5.5V
=
Built-in PMSAv8 Memory Protection Unit (MPU)
Built-in Nested Vectored Interrupt Controller (NVIC)
32-bit Single-cycle hardware multiplier and 32-bit 17-cycle
Arm® Cortex® -M23 without
TrustZone®
hardware divider
24-bit system tick timer
Supports Programmble and maskable interrupt
Supports Low Power Sleep mode by WFI and WFE instructions
Supports single cycle I/O access
Supports XOM feature with 1 region
Low Power mode:
– Idle mode
Low power mode and
current
Power-down mode (PD)
– Fast Wake-up Power-down mode (FWPD)
– Deep Power-down mode (DPD)
USCI, RTC, WDT, I2C, Timer, UART, BOD, LVR, POR, GPIO,
USBD, Tamper, ACMP, Debug interface, NMI and Reset pin from
Power-down mode or Fast Wake-up Power-down mode
Wake-up source and
wakeup time
RTC, Wake-up Timer, LVR, Wake-up pins, Tamper, from Deep
Power-down mode
Built-in LDO for wide operating voltage from 1.75V to 5.5V
Core power voltage: 1.5V
Brown-out detector
Power supply and low
voltage detect
– With 7 levels: 4.4V/3.7V/3.0V/2.7V/2.4V/2.0V/1.8V
– Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage levels: 1.55V
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16,
and CRC-32
Cyclic Redundancy
Calculation Unit
Programmable order reverse setting for input data and CRC
checksum
Programmable 1’s complement setting for input data and CRC
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checksum.
Supports 8-/16-/32-bit of data width
Programmable seed value
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
Supports up to 6 VAI pins
Voltage Adjustable
Interface
User Configurable 1.65V ~ 5.5V I/O Interface with a dedicated
power input (VDDIO)
Supports UART0~1, SPI0~1, I2C0~1, USCI2 and SC0 interface
96-bit Unique ID (UID)
Security
128-bit Unique Customer ID (UCID)
Memories
Up to 256 KB application ROM (APROM)
4 KB Flash for user program loader (LDROM)
Up to 48 MHz with zero wait state for consecutive address read
access
12 bytes User Configuration Block to control system initiation.
512B page erase for all embedded Flash
32-bit and multi-word Flash programming function.
Flash
Supports In-System-Programming (ISP), In-Application-
Programming (IAP) update embedded Flash memory
Supports CRC-32 checksum calculation function
Supports Flash all one verification function (hardware can check
page erase verify)
Hardware external read protection of whole Flash memory by
Security Lock Bit
Supports XOM feature with 1 region
Up to 32 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
SRAM
Up to 8 independent configurable channels for automatic data
transfer between memories and peripherals
Peripheral DMA (PDMA)
Channel 0 to 5 support stride features
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Channel 0, 1 support time-out function
Basic and Scatter-Gather Transfer modes
Each channel supports circular buffer management using Scatter-
Gather Transfer mode
Two types of priorities modes: Fixed-priority and Round-robin
modes
Transfer data width of 8, 16, and 32 bits
Single and burst transfer type
Source and destination address can be increment or fixed
PDMA transfer count up to 65536
Request source form software, PSIO, SPI/I2S, UART, USCI,
EADC, DAC, PWM capture event or TIMER
Clocks
Built-in 4.032 MHz internal high speed RC oscillator (MIRC) for
system operation
Built-in 48 MHz internal high speed RC oscillator (HIRC) for
system operation
Built-in 38.4 kHz internal low speed RC oscillator (LIRC) for
Watchdog Timer and wake-up operation.
Built-in 4~32 MHz external high speed crystal oscillator (HXT) for
precise timing operation
Built-in 32.768 kHz external low speed crystal oscillator (LXT) for
RTC function and low-power system operation
Clock Source
Supports one PLL up to 100 MHz for high performance system
operation, sourced from HIRC and HXT
Supports clock on-the-fly switch
Supports clock failure detection for high/low speed external crystal
oscillator
HXT clock frequency accuracy detector
Supports exception (NMI) generated once a clock failure detected
Supports divided clock output
Timers
TIMER mode
4 sets of 32-bit timers with 24-bit up counters and 8-bit prescale
counters
Independent clock source for each timer
32-bit Timer
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Event counting function to count the event from external pin
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Input capture function to capture or reset counter value
External capture pin event for interval measurement.
External capture pin event to reset 24-bit up counter.
Chip wake-up from Idle/Power-down mode if a timer interrupt
signal is generated
Timer interrupt flag or external capture interrupt flag to trigger
BPWM, PWM, EADC, DAC and PDMA.
Internal capture triggered source from ACMP output.
Inter-Timer trigger capture mode
PWM mode
16-bit compare register and period register
Double buffer for period register and compare register
Supports inverse in PWM output
PWM interrupt wake-up from system Power-down mode
Supports maximum clock frequency up to 96 MHz
Each module provides 6 output channels
Supports independent mode for BPWM output/Capture input
channel
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution BPWM counter, each module provides
1 BPWM counter
– Up, down or up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt on the following events:
BPWM
– BPWM counter match 0, period value or compared value
Supports trigger ADC on the following events:
– BPWM counter match 0, period value or compared value
Capture Function Features
– Up to 6 capture input channels with 16-bit resolution
– Supports rising or falling capture condition
– Supports input rising/falling capture interrupt
– Supports rising/falling capture with counter reload option
Supports maximum clock frequency up to 96 MHz
Up to two PWM modules; each module provides 6 output
PWM
channels.
Supports independent mode for PWM output/Capture input
channel
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Supports complementary mode for 3 complementary paired PWM
output channel
– Dead-time insertion with 12-bit resolution
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution PWM counter
– Up, down or up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
– Brake source from pin and system safety events (clock failed,
Brown-out detection and CPU lockup)
– Noise filter for brake source from pin
– Edge detect brake source to control brake state until brake
interrupt cleared
– Level detect brake source to auto recover function after brake
condition removed
Supports interrupt on the following events:
– PWM counter match 0, period value or compared value
– Brake condition happened
Supports trigger ADC on the following events:
– PWM counter match 0, period value or compared value
Capture Function Features
– Up to 12 capture input channels with 16-bit resolution
– Supports rising or falling capture condition
– Supports input rising/falling capture interrupt
– Supports rising/falling capture with counter reload option
– Supports PDMA transfer function for all PWM channels
20-bit free running up counter for WDT time-out interval
Clock sources from LIRC (default), HCLK/2048 or LXT
9 selectable time-out period from 488us ~ 32 sec
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Watchdog
Selectable WDT reset delay period, including 1026, 130, 18 or 3
WDT_CLK reset delay period
Force WDT enabled after chip power on or reset.
WDT time-out wake-up function only if WDT clock source is
selected as LIRC or LXT
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Clock sources from HCLK/2048 (default) or LIRC
Window set by 6-bit down counter with 11-bit prescaler
WWDT counter suspends in Idle/Power-down mode
Supports Interrupt
Window Watchdog
Supports external power pin VBAT
Software compensation by setting frequency compensate register
(FCR),compensated clock accuracy reaches ±5ppm within 5
seconds
RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
RTC
Day of the Week counter
Daylight Saving Time software control
Periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 or 1 second
1 Hz clock output for RTC calibration
Wake-up from idle mode and power down mode
32 kHz oscillator gain control
RTC Time Tick and Alarm Match interrupt
20 bytes spare registers and 1 tamper pin to clear the content of
these spare registers
Tamper
Selectable spare register erase function
Supports Timestamp function
Analog Interfaces
Conversion results held in 19 data registers with valid and overrun
indicators.
Analog input voltage: 0~VREF (Max to AVDD).
Reference voltage from VREF pin, AVDD or internal VREF
12-bit resolution and 10-bit accuracy guaranteed
Up to 16 single-end analog external input channels
Supports 3 internal channels:
EADC
– Band-gap VBG output or Internal voltage reference
– Temperature sensor input
– VBAT voltage measure (VBAT/4)
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Four ADC interrupts (ADINT0~3) with individual interrupt vector
addresses.
ADC clock frequency up to 16 MHz.
Up to 880 kSPS conversion rate.
Configurable ADC internal sampling time
Up to 19 sample modules
– Each of sample module 0~15 which is configurable for ADC
converter channel
– EADC_CH0~15 and trigger source.
– Configurable PDMA
– Configured resolution for 12-bit or 16-bit result
– Supports Left-adjusted result
– Averaging and oversampling (2n times, n=0~8) to support up to
16-bit result
– Sample module 16~18 is fixed for ADC channel 16, 17, 18
input sources as band-gap voltage, temperature sensor, and
battery power (VBAT/4).
– Configurable sampling time for each sample module.
– Conversion results held in 19 data registers with valid and
overrun indicators.
Supports digital comparator to monitor conversion result that can
be under or over the compare register setting
Generate an interrupt when conversion result matches the
compare register setting.
Internal reference voltage source:
– 1.536V, 2.048V, 2.560V, 3.072V, or 4.096V
An A/D conversion can be started by:
– Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18)
– External pin STADC
– Timer0~3 overflow pulse triggers
– ADINT0/1 interrupt EOC (End of conversion) pulse triggers
– PWM triggers
– BPWM triggers
Supports PDMA transfer
Auto turn on/off ADC power at power down or operation mode with
wait state
Analog output voltage: 0~AVDD
Supports 12-or 8-bit output mode
Rail to rail settle time 6us
DAC
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Up to one 12-bit, 1 MSPS voltage type DAC
Reference voltage from internal reference voltage or VREF pin
Conversion updating rate up to 1 MSPS
Supports voltage output buffer mode and bypass voltage output
buffer mode
Supports software and hardware trigger, including Timer0~3 and
external trigger pin to start DAC conversion
Supports PDMA mode
Up to two rail-to-rail analog comparators
4 multiplexed I/O pins at positive node
Negative node:
– One I/O pin
– Band-gap (VBG)
– DAC0 output
– Comparator Reference Voltage (CRV)
Programmable propagation speed and low power consumption
Analog Comparator
(ACMP)
Interrupts generated when compare results change (Interrupt
event condition programmable)
Supports Power-down Wake-up
Supports triggers for break events and cycle-by-cycle control for
PWM
Supports window compare mode and window latch mode
Supports programmable hysteresis window:
–
0 mV, 10 mV, 20 mV or 30 mV
Analog input voltage: 0~AVDD.
Up to 1 operational amplifier
OPA
Supports to use schmitt trigger buffer output for simple comparator
function
Supports schmitt trigger buffer output interrupts.
Internal reference voltage select: 1.536V, 2.048V, 2.560V, 3.072V,
4.096V for EADC, DAC and CRV (comparator reference voltage)
reference voltage
Internal Reference Voltage
Communication Interfaces
Supports up to 3 UARTs: UART0, UART1 and UART2
UART clock source can be from LIRC
UART
UART baud rate clock from LXT(32.768 kHz) with 9600bps in
Power-down mode
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Baud rate up to 10 Mbps
Full-duplex asynchronous communications
Supports one-wire half-duplex communications
Separates receive and transmit 16/16 bytes FIFO
Programmable receiver buffer trigger level
Hardware auto-flow control (CTS and RTS)
IrDA (SIR) function
– Supports 3/16 bit duration for normal mode
RS-485 9-bit mode and direction control
UART0 supports LIN function
– LIN master/slave mode
– Programmable break generation function for transmitter
– Break detection function for receiver
Programmable baud-rate generator up to 1/16 system clock
8-bit receiver FIFO time-out detection function
Programmable transmitting data delay time between the last stop
and the next start bit
Auto-Baud Rate measurement and baud rate compensation
function
Break error, frame error, parity error and receive/transmit FIFO
overflow detection function
Supports RS-485 mode:
– RS-485 9-bit mode
– Hardware or software enables to program nRTS pin to control
RS-485 transmission direction
– nCTS, incoming data, Received Data FIFO reached threshold
and RS-485 Address Match (AAD mode) wake-up function in
Power-down mode.
– Hardware or software enables to program nRTS pin to control
RS-485 transmission direction
Fully programmable serial-interface:
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit
generation and detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports PDMA mode
Smart card mode
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Smart Card Interface
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One ISO 7816-3 port
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR)
and waiting times processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number
limiting function
Supports hardware activation sequence process, and the time
between PWR on and CLK start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when the card
removal is detected
UART mode
Full duplex, asynchronous communications
Separates receiving / transmitting 4 bytes entry FIFO for data
payloads
Supports programmable baud rate generator
Supports programmable receiver buffer trigger level
Programmable transmitting data delay time between the last stop
bit leaving the TX-FIFO and the de-assertion
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1- or 2- stop bit generation
Supports Master or Slave mode operation
Master and slave mode up to 25 MHz (when chip works at VDD
=
3.0 ~ 5.5V)
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
SPI
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
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Supports one data channel half-duplex transfer
Supports receive-only mode
Up to 2 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit and 10-bit addressing mode
Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode
plus (1 Mbps)
Arbitration between simultaneously transmitting masters without
corruption of serial data on the bus
Serial clock synchronization allows devices with different bit rates
I2C
to communicate via one serial bus
Serial clock synchronization can be used as a handshake
mechanism to suspend and resume serial transfer
Supports 14-bit time-out counter requesting the I2C interrupt if the
I2C bus hangs up and timer-out counter overflows
Programmable clocks allow versatile rate control
Multiple address recognition (four slave address with mask option)
Supports setup/hold time programmable
Supports SMBus and PMBus
Multi-address Power-down wake-up function
Supports PDMA transfer
SPI Mode
Up to 1 set of SPI controller
Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit
and receive FIFO buffers which depended on SPI setting of data
width
MSB first or LSB first transfer sequence
Supports byte reorder function
Byte or Word Suspend mode
SPI/I2S
Master and slave mode up to 25 MHz (VDD = 3.0V ~5.5V)
Supports one data channel half-duplex transfer
Supports receive-only mode
Supports PDMA transfer
I2S Mode
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Up to 1 sets of I2S by SPI controllers
Interface with external audio CODEC
Supports Master and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Mono and stereo audio data
PCM mode A, PCM mode B, I2S and MSB justified data format
Each provides two 4-level FIFO data buffers, one for transmitting
and the other for receiving
Generates interrupt requests when buffer levels cross a
programmable boundary
Each supports two PDMA requests, one for transmitting and the
other for receiving
Up to 3 sets of USCI: USCI0, USCI1 and USCI2
Supports UART, SPI and I2C function
Single byte TX and RX buffer mode
USCI_UART
One transmit buffer and two receive buffer for data payload
Hardware auto flow control function and programmable flow
control trigger level
Programmable baud-rate generator
Supports 9-bit data transfer
Baud rate detection by built-in capture event of baud rate
generator
Supports Wake-up function (Data and nCTS Wakeup Only)
Supports PDMA transfer
Universal Serial Control
Interface (USCI)
USCI_SPI
Master or Slave mode operation
Configurable bit length of a transfer word from 4 to 16-bit
One transmit buffer and two receive buffer for data payload
MSB first or LSB first transfer sequence
Word suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Wake-up function: input slave select transition
Supports one data channel half-duplex transfer
USCI_I2C
Full master and slave device capability
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7-bit/10-bit addressing mode
Communication in Standard mode (100 kbps), Fast mode (up to
400 kbps) and Fast mode plus (1 Mbps)
Multi-master bus
One transmit buffer and two receive buffer for data payload
10-bit bus time out capability
Supports Bus monitor mode
Wake-up by data toggle or address match in Power-down mode
Multiple address recognition
Setup/hold time programmable
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for
each bank
Accessible space up to 1 Mbytes for each bank
Byte write in 16-bit data width mode
External Bus Interface
(EBI)
Address/Data multiplexed and separate mode
Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports Continuous Data Access mode
Supports PDMA mode
Four I/O modes:
– Quasi bi-direction
– Push-Pull output
– Open-Drain output
– Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger
setting
GPIO
Independent pull-up/pull-down control
High driver and high sink current I/O (up to 16 mA at 5V, 25°C)
Minimum I/O Speed
– 25 MHz when VDD = 2.7 ~ 5.5 V (-40°C ~ +105°C, CL=35p,
high skew rate enabled)
– 10 MHz when VDD = 1.75 ~ 5.5 V (-40°C ~ +105°C, CL=35p,
high skew rate enabled)
Software selectable slew rate control
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Supports wake-up function
Supports I/O de-bounce with LIRC at power down
I/O configurations of multi-function pin are controlled by module or
MFOS register settings.
Supports up to 8 PSIO pins, from PSIO pin0 to PSIO pin7
Supports 6 clock source selections: HXT, LXT, HIRC, LIRC, PLL,
or PCLK1
Supports one clock divider, which can be divided from 1 to 255
Supports slot controller for timing sequence control
– Supports 4 slot controllers, 8 slots in each slot controller
– Supports counting from 1 PSIO clock to 15 PSIO clocks in
each slot
– Supports 3 slot repeat modes
Normal repeat mode
Normal repeat mode with infinity loops
Whole repeat mode
– Supports 4 slot trigger conditions
Triggered by software
Triggered by falling edge
Triggered by rising edge
Triggered by rising edge or falling edge
PSIO
Supports PSIO PIN for pin state control
Supports 8 check points to connect with slots in each pin
Supports 8 check point actions in each check point.
Supports 7 kinds of check point action to setting
– Output high
– Output low
– Output data
– Output toggle
– Input data
– Input status
– Input status update
Supports 4 I/O modes: input, output, open-drain, and quasi
Supports switch I/O mode in different check points
Supports 4 kinds of Interrupt trigger conditions:
– Two sets of configurable slot interrupt controllers
– Mismatch interrupt when PSIO is enabled with PDMA
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– Transfer Error interrupt
– Slot controller counting done interrupt
Supports PDMA function
Advanced Connectivity
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events
(NEVWK, VBUSDET, USB and BUS)
Suspend function when no bus activity exists for 3 ms
Supports 12 endpoints for configurable
Control/Bulk/Interrupt/Isochronous transfer types and maximum
1024 bytes buffer size
USB 2.0 Full Speed
Provides remote wake-up capability
Start of Frame (SOF) locked clock pulse generation
Supports USB 2.0 Link Power Management (LPM)
Supports Crystal-less function
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M251/M252
3 PARTS INFORMATION
3.1 Package Type
Part No.
M251xC
TSSOP20
TSSOP28
QFN33
LQFP48
LQFP64
LQFP128
M251FC2AE
M251EC2AE
M251ZC2AE
M251LC2AE
M251LD2AE
M251SC2AE
M251SD2AE
M251ZD2AE
M251xD
M251xE
M251LE3AE
M251LG6AE
M251SE3AE
M251SG6AE
M251KE3AE
M251KG6AE
M251xG
M252FC2AE
M252EC2AE
M252ZC2AE
M252ZD2AE
M252xC
M252xD
M252LC2AE
M252LD2AE
M252SC2AE
M252SD2AE
M252xE
M252xG
M252LE3AE
M252LG6AE
M252SE3AE
M252SG6AE
M252KE3AE
M252KG6AE
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3.2 M251/M252 Series Selection Guide
3.2.1
M251 Base Series (M251Fx / M0251Ex / M0251Zx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
8
32
8
32
8
64
12
4
-
-
-
-
-
√
96
√
I/O
15
23
26
26
32-bit Timer/PWM
PWM
4
9
-
11
-
12
-
12
12
BPWM
WDT/WWDT
RTC
√
-
-
√
1
2
√
2
3
USCI
1
2
1
2
UART
QSPI
1
SPI /I2S
I2C
-
-
-
1
2
1
-
SC/UART
EBI
PSIO
-
7
-
-
9
-
-
10
-
4
10
2
12-bit ADC
ACMP
DAC
-
-
OPA
PDMA
5
-
Tamper
VAI
-
-
√
√
VBAT pin
Internal VREF
Package
-
-
TSSOP20
TSSOP28
QFN33
QFN33
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M251/M252
3.2.2
M251 Base Series (M251Lx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
8
64
12
128
16
256
32
4
96
√
I/O
41
4
32-bit Timer/PWM
PWM
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
2
2
3
3
UART
3
1
1
2
1
QSPI
SPI /I2S
I2C
SC/UART
EBI
-
-
√
√
PSIO
4
4
8
8
12-bit ADC
ACMP
12
2
DAC
-
-
-
-
-
-
1
1
8
OPA
PDMA
5
5
8
Tamper
VAI
-
√
VBAT pin
Internal VREF
Package
-
-
LQFP48
July 2, 2020
Page 31 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 32 of 266
Rev 1.01
M251/M252
3.2.3
M251 Base Series (M251Sx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
64
12
128
16
256
32
8
4
96
√
I/O
54
54
53
53
32-bit Timer/PWM
PWM
4
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
2
2
3
3
UART
3
1
1
2
1
QSPI
SPI /I2S
I2C
SC/UART
EBI
-
-
√
√
PSIO
4
4
8
8
12-bit ADC
ACMP
16
2
DAC
-
-
-
-
-
-
1
1
8
OPA
PDMA
5
5
8
Tamper
VAI
√
√
VBAT pin
Internal VREF
Package
-
-
√
√
√
LQFP64
July 2, 2020
Page 33 of 266
Rev 1.01
M251/M252
3.2.4
M251 Base Series (M251Kx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
128
16
256
32
4
96
√
I/O
85
4
32-bit Timer/PWM
PWM
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
3
UART
3
QSPI
1
SPI /I2S
I2C
1
2
SC/UART
EBI
1
√
PSIO
8
12-bit ADC
ACMP
16
2
DAC
-
-
1
1
OPA
PDMA
8
Tamper
VAI
√
√
VBAT pin
Internal VREF
Package
√
√
LQFP128
July 2, 2020
Page 34 of 266
Rev 1.01
M251/M252
3.2.5
M252 USB Series (M252Fx / M0252Ex / M0252Zx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
8
32
8
32
8
64
12
4
-
-
-
-
-
√
96
√
I/O
11
19
22
22
32-bit Timer/PWM
PWM
4
7
-
11
-
12
-
12
8
BPWM
WDT/WWDT
RTC
√
√
1
-
-
√
2
3
USCI
1
2
1
2
UART
2
QSPI
1
SPI /I2S
I2C
-
-
-
1
2
1
-
SC/UART
EBI
PSIO
-
3
-
-
9
-
-
10
-
4
10
2
12-bit ADC
ACMP
DAC
-
-
OPA
PDMA
5
-
Tamper
VAI
-
-
√
√
VBAT pin
Internal VREF
Package
-
-
TSSOP20
TSSOP28
QFN33
QFN33
July 2, 2020
Page 35 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 36 of 266
Rev 1.01
M251/M252
3.2.6
M252 USB Series (M252Lx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
8
64
12
128
16
256
32
4
96
√
I/O
37
4
32-bit Timer/PWM
PWM
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
2
2
3
3
UART
3
1
1
2
1
QSPI
SPI /I2S
I2C
SC/UART
EBI
-
-
√
√
PSIO
4
4
8
8
12-bit ADC
ACMP
12
2
DAC
-
-
-
-
-
-
1
1
8
OPA
PDMA
5
5
8
Tamper
VAI
-
√
VBAT pin
Internal VREF
Package
-
-
LQFP48
July 2, 2020
Page 37 of 266
Rev 1.01
M251/M252
3.2.7
M252 USB Series (M252Sx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
32
64
12
128
16
256
32
8
4
96
√
I/O
50
50
49
49
32-bit Timer/PWM
PWM
4
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
2
2
3
3
UART
3
1
1
2
1
QSPI
SPI /I2S
I2C
SC/UART
EBI
-
-
√
√
PSIO
4
4
8
8
12-bit ADC
ACMP
16
2
DAC
-
-
-
-
-
-
1
1
8
OPA
PDMA
5
5
8
Tamper
VAI
√
√
VBAT pin
Internal VREF
Package
-
-
√
√
√
LQFP64
July 2, 2020
Page 38 of 266
Rev 1.01
M251/M252
3.2.8
M252 USB Series (M252Kx)
PART NUMBER
Flash (KB)
SRAM (KB)
LDROM (KB)
PLL ( MHz)
LXT
128
16
256
32
4
96
√
I/O
81
4
32-bit Timer/PWM
PWM
12
12
√
BPWM
WDT/WWDT
RTC
√
USCI
3
UART
3
QSPI
1
SPI /I2S
I2C
1
2
SC/UART
EBI
1
√
PSIO
8
12-bit ADC
ACMP
16
2
DAC
-
-
1
1
OPA
PDMA
8
Tamper
VAI
√
√
VBAT pin
Internal VREF
Package
√
√
LQFP128
July 2, 2020
Page 39 of 266
Rev 1.01
M251/M252
3.2.9
Naming Rule
51
M2
Core
S
G
6
A
E
Line
Package
Flash
SRAM
Reserve
Temperature
E: -40℃ ~ +105℃
Cortex®-M23 51: Control
F: TSSOP20
(4.4x6.5 mm)
E: TSSOP28
(4.4x9.7 mm)
Z: QFN33
(5x5 mm)
C: 32 KB
D: 64 KB
E: 128 KB
G: 256 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
52: USB
L: LQFP48
(7x7 mm)
S: LQFP64
(7x7 mm)
K: LQFP128
(14x14 mm)
July 2, 2020
Page 40 of 266
Rev 1.01
M251/M252
4 PIN CONFIGURATION
Users can find pin configuration information in chapter 4 or by using NuTool - PinConfig. The NuTool -
PinConfigure contains all NuMicro® Family chip series with all part number, and helps users configure
GPIO multi-function correctly and handily.
4.1 Pin Configuration
4.1.1
M251 Series Pin Diagram
4.1.1.1 M251 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M251FC2AE
1
20
19
18
17
VSS
PF.1
2
3
LDO_CAP
VDD
PF.0
nRESET
PA.0
4
PB.14
PB.13
PB.12
AVDD
5
16 PA.1
15 PA.2
6
PA.3
PF.2
PF.3
PB.2
7
14
13
12
11
PB.5
8
PB.4
9
PB.3
10
Figure 4.1-1 M251 Series TSSOP 20-pin Diagram
4.1.1.2 M251 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M251EC2AE
1
28
27
26
25
24
PC.0
PA.12
2
PC.1
PA.13
3
PF.1
PA.14
4
PF.0
PA.15
5
nRESET
VSS
6
7
23 PA.0
22 PA.1
21 PA.2
LDO_CAP
VDD
8
PB.14
PB.13
PB.12
AVDD
PA.3
PF.2
PF.3
PB.0
PB.1
PB.2
9
20
19
18
17
16
15
10
11
12
13
14
PB.5
PB.4
PB.3
Figure 4.1-2 M251 Series TSSOP 28-pin Diagram
July 2, 2020
Page 41 of 266
Rev 1.01
M251/M252
4.1.1.3 M251 Series QFN 33-Pin Diagram
Corresponding Part Number: M251ZC2AE, M251ZD2AE
25
16
15
14
13
12
11
10
9
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PF.2
Top transparent view
26
LDO_CAP
27
VDD
28
PB.15
QFN33
29
PB.14
30
PB.13
31
PB.12
33 VSS
32
AVDD
PF.3
Figure 4.1-3 M251 Series QFN 33-pin Diagram
July 2, 2020
Page 42 of 266
Rev 1.01
M251/M252
4.1.1.4 M251 Series LQFP 48-Pin Diagram
Corresponding Part Number: M251LC2AE, M251LD2AE, M251LE3AE, M251LG6AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP48
AVSS
PB.7
PB.6
Figure 4.1-4 M251 Series LQFP 48-pin Diagram
July 2, 2020
Page 43 of 266
Rev 1.01
M251/M252
4.1.1.5 M251 Series LQFP 64-Pin Diagram
Corresponding Part Number: M251SC2AE, M251SD2AE, M251SE3AE, M251SG6AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP64
VREF
AVSS
VSS
PB.11
PB.10
PB.9
PA.6
PA.7
PC.6
PC.7
PF.2
PB.8
PB.7
Figure 4.1-5 M251 Series LQFP 64-pin Diagram without VBAT
July 2, 2020
Page 44 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M251SG6AE, M251SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
50
LDO_CAP
51
VDD
52
PC.14
53
PB.15
54
PB.14
55
PB.13
56
PB.12
LQFP64
57
AVDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
Figure 4.1-6 M251 Series LQFP 64-pin Diagram with VBAT
July 2, 2020
Page 45 of 266
Rev 1.01
M251/M252
4.1.1.6 M251 Series LQFP 128-Pin Diagram
Corresponding Part Number: M251KE3AE, M251KG6AE
97
64
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
nRESET
PE.15
PE.14
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
98
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
PE.1
PE.0
NC
NC
NC
VSS
NC
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
NC
NC
VSS
LQFP128
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
PB.11
PB.10
PB.9
PB.8
PB.7
PB.6
NC
PF.2
PF.3
NC
NC
NC
NC
Figure 4.1-7 M251 Series LQFP 128-pin Diagram
July 2, 2020
Page 46 of 266
Rev 1.01
M251/M252
4.1.2
M251 Series Multi-function Pin Diagram
4.1.2.1 M251 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M251FC2AE
M251FC2AE
1
2
20
19
VSS
LDO_CAP
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
VDD
3
18 nRESET
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
4
17 PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
16 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
5
6
15 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
7
14 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5
INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
9
PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3
10
Figure 4.1-8 M251FC2AE Multi-function Pin Diagram
Pin M251FC2AE Pin Function
1
2
3
4
5
6
7
8
9
VSS
LDO_CAP
VDD
PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
AVDD
PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0
PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1
10 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
11 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
12 PF.3/UART0_TXD/I2C0_SCL/XT1_IN
13 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
14 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
15 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
16 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
17 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
nRESET
18
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
19
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
20
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
July 2, 2020
Page 47 of 266
Rev 1.01
M251/M252
Table 4.1-1 M251FC2AE Multi-function Pin Table
4.1.2.2 M251 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M251EC2AE
M251EC2AE
1
2
28
27
26
25
I2C1_SCL / PA.12
PC.0 / I2C0_SDA / PWM1_CH5
I2C1_SDA / PA.13
PC.1 / I2C0_SCL / PWM1_CH4
3
UART0_TXD / PA.14
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
UART0_RXD / PA.15
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
VDD
7
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
8
21 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
9
20 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5
INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3
PB.0 / EADC0_CH0 / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PB.1 / EADC0_CH1 / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3
Figure 4.1-9 M251EC2AE Multi-function Pin Diagram
Pin M251EC2AE Pin Function
1
2
3
4
5
6
7
8
9
PA.12/I2C1_SCL
PA.13/I2C1_SDA
PA.14/UART0_TXD
PA.15/UART0_RXD
VSS
LDO_CAP
VDD
PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
10 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
11 AVDD
12 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0
13 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1
14 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
15 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
16 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
17 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1
18 PF.3/UART0_TXD/I2C0_SCL/XT1_IN
19 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
July 2, 2020
Page 48 of 266
Rev 1.01
M251/M252
20 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
21 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
22 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
23 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4
28 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5
Table 4.1-2 M251EC2AE Multi-function Pin Table
July 2, 2020
Page 49 of 266
Rev 1.01
M251/M252
4.1.2.3 M251 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M251ZC2AE
M251ZC2AE
nRESET
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
Top transparent view
VDDIO
LDO_CAP
VDD
PA.0 / QSPI0_MOSI0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / QSPI0_MISO0 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / QSPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / QSPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO /
PWM1_BRAKE1
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / EADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-10 M251ZC2AE Multi-function Pin Diagram
Pin M251ZC2AE Pin Function
1
2
3
4
PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0
PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1
PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
July 2, 2020
Page 50 of 266
Rev 1.01
M251/M252
5
6
7
8
9
PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1
PF.5/PWM0_CH0/X32_IN/EADC0_ST
PF.4/PWM0_CH1/X32_OUT
PF.3/UART0_TXD/I2C0_SCL/XT1_IN
10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
11 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
12 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
13 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
14 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
15 VDDIO
nRESET
16
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
17
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
18
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
19 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4
20 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5
21 PA.12/I2C1_SCL
22 PA.13/I2C1_SDA
23 PA.14/UART0_TXD
24 PA.15/UART0_RXD
25 VSS
26 LDO_CAP
27 VDD
28 PB.15/EADC0_CH15/USCI0_CTL1/UART0_nCTS/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
29 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
30 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
31 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
32 AVDD
Table 4.1-3 M251ZC2AE Multi-function Pin Table
July 2, 2020
Page 51 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M251ZD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
VDDIO
Top transparent view
LDO_CAP
VDD
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3
PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Figure 4.1-11 M251ZD2AE Function Pin Diagram
Pin M251ZD2AE Pin Function
1
2
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
3
4
5
6
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
July 2, 2020
Page 52 of 266
Rev 1.01
M251/M252
1
7
8
9
PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
11
12 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
13 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
14 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
15 VDDIO
nRESET
16
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
17
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
18
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
19 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
20 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
21 PA.12/I2C1_SCL/BPWM1_CH2
22 PA.13/I2C1_SDA/BPWM1_CH3
23 PA.14/UART0_TXD/BPWM1_CH4
24 PA.15/UART0_RXD/BPWM1_CH5
25 VSS
26 LDO_CAP
27 VDD
28 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
29 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
30
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
31
32 AVDD
Table 4.1-4 M251ZD2AE Multi-function Pin Table
July 2, 2020
Page 53 of 266
Rev 1.01
M251/M252
4.1.2.4 M251 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M251LC2AE, M251LD2AE, M251LE3AE, M251LG6AE
M251LC2AE / M251LD2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
PSIO0_CH2
PSIO0_CH3
/
PWM1_CH0
PWM1_CH1
UART0_TXD
UART0_RXD
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
/
/
/
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5 /
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
BPWM0_CH3
I2C0_SDA BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
/
/
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
CLKO / PWM1_BRAKE1
LQFP48
TM2_EXT
/
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
/
/
USCI0_CLK
/
/
/
UART0_RXD
UART0_TXD
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
/
PWM1_CH5
PWM1_CH4
QSPI0_CLK / XT1_OUT / BPWM1_CH1
/
BPWM1_CH3
/
ACMP1_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
BPWM1_CH2
/
ACMP0_WLAT
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
UART1_TXD
UART1_RXD
/
/
USCI1_DAT0
USCI1_DAT1
/
/
EADC0_CH7
EADC0_CH6
/
/
PB.7
PB.6
/
/
/
/
/
/
/
/
/ XT1_IN / BPWM1_CH0
Figure 4.1-12 M251LC2AE/M251LD2AE Multi-function Pin Diagram
Pin M251LC2AE/M251LD2AE Pin Function
1
2
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
3
July 2, 2020
Page 54 of 266
Rev 1.01
M251/M252
4
5
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
1
6
7
8
9
PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT
PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
19
20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1
29 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2
30 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3
31 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
32 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
33 PA.12/I2C1_SCL/BPWM1_CH2
34 PA.13/I2C1_SDA/BPWM1_CH3
35 PA.14/UART0_TXD/BPWM1_CH4
July 2, 2020
Page 55 of 266
Rev 1.01
M251/M252
36 PA.15/UART0_RXD/BPWM1_CH5
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1
41 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
42 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
43
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
44
45 AVDD
46 AVSS
47 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O
48 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O
Table 4.1-5 M251LC2AE/M251LD2AE Multi-function Pin Table
July 2, 2020
Page 56 of 266
Rev 1.01
M251/M252
M251LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
EADC0_CH7
EADC0_CH6
/
/
Analog16
Analog17
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-13 M251LE3AE Multi-function Pin Diagram
Pin M251LE3AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
3
4
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
7/TM3/INT3
July 2, 2020
Page 57 of 266
Rev 1.01
M251/M252
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
5
6
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
7
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
18
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
19
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
20
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
21
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
22
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
33 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
34 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
July 2, 2020
Page 58 of 266
Rev 1.01
M251/M252
35 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
36 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
41
42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
43
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
44
45 AVDD
46 AVSS
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
47
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
48
Table 4.1-6 M251LE3AE Multi-function Pin Table
July 2, 2020
Page 59 of 266
Rev 1.01
M251/M252
M251LG6AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PSIO0_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
LQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
/
EBI_AD14
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
UART0_RXD
/
USCI0_CLK
/
EBI_AD15
/
ACMP1_P2
/
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
EADC0_CH7
EADC0_CH6
/
/
Analog16
Analog17
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-14 M251LG6AE Multi-function Pin Diagram
Pin M251LG6AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
3
4
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
SIO0_CH7/TM3/INT3
July 2, 2020
Page 60 of 266
Rev 1.01
M251/M252
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
5
6
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
7
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
18
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
19
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
20
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
21
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
22
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
33 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
34 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
July 2, 2020
Page 61 of 266
Rev 1.01
M251/M252
35 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
36 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
41
42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
43
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
44
45 AVDD
46 AVSS
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
47
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
48
Table 4.1-7 M251LG6AE Multi-function Pin Table
July 2, 2020
Page 62 of 266
Rev 1.01
M251/M252
4.1.2.5 M251 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M251SC2AE, M251SD2AE, M251SE3AE, M251SG6AE
M251SC2AE / M251SD2AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
PSIO0_CH2
PSIO0_CH3
/
PWM1_CH0
PWM1_CH1
UART0_TXD
UART0_RXD
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5 /
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
BPWM0_CH3
I2C0_SDA BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
/
/
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS UART0_RXD
BPWM1_CH4 UART1_TXD
/
UART0_nCTS
/
/
EADC0_CH11
EADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
/
/
USCI1_CTL0
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
/
/
USCI1_CTL1
USCI1_CLK
USCI1_DAT0
/
/
/
EADC0_CH9
EADC0_CH8
EADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
I2C1_SMBAL
QSPI0_CLK
/
PWM1_CH3
PWM1_CH2
XT1_OUT /
/
BPWM1_CH1
BPWM1_CH0 TM0
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
/
/
/
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
UART0_RXD
/
I2C0_SDA
/
/
Figure 4.1-15 M251SC2AE/M251SD2AE Multi-function Pin Diagram
Pin M251SC2AE/M251SD2AE Pin Function
1
2
3
PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
July 2, 2020
Page 63 of 266
Rev 1.01
M251/M252
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
4
5
6
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
1
7
8
9
PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT
10 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/SC0_CLK/SPI0_MOSI/TAMPER0
13 PF.14/PWM1_BRAKE0/PWM0_BRAKE0/PSIO0_CH3/PWM0_CH4/CLKO/TM3/INT5
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
27
28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
33
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020
Page 64 of 266
Rev 1.01
M251/M252
36 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1
37 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2
38 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3
39 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
40 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
41 PD.3/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/USCI0_DAT0/SPI0_MISO
44 PD.0/USCI0_CLK/SPI0_MOSI/TM2
45 PA.12/I2C1_SCL/BPWM1_CH2
46 PA.13/I2C1_SDA/BPWM1_CH3
47 PA.14/UART0_TXD/BPWM1_CH4
48 PA.15/UART0_RXD/BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1
53 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
54 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
55
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
64 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O
Table 4.1-8 M251SC2AE/M251SD2AE Multi-function Pin Table
July 2, 2020
Page 65 of 266
Rev 1.01
M251/M252
M251SE3AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
/
/
/
/
LQFP64
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nRTS
/
/
EBI_ADR17
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
I2C1_SMBAL
/
/
/
/
/
EBI_ADR18
EBI_ADR19
EBI_nWRL
/
/
/
EADC0_CH9
/
/
/
Analog14
Analog15
Analog16
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
I2C1_SMBSUS
I2C1_SMBAL
I2C0_SDA QSPI0_CLK
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
XT1_OUT BPWM1_CH1
/
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
/
/
/
TM0
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
USCI1_DAT0
/
EBI_nCS1
/
UART0_RXD
/
/
/
Figure 4.1-16 M251SE3AE Multi-function Pin Diagram
Pin M251SE3AE Pin Function
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
1
2
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
3
4
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020
Page 66 of 266
Rev 1.01
M251/M252
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
7/TM3/INT3
5
6
7
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
13 VBAT
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
26
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
27
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
28
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
29
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
30
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
33
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020
Page 67 of 266
Rev 1.01
M251/M252
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
45 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
46 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
47 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
48 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
53
54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
55
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
64
Table 4.1-9 M251SE3AE Multi-function Pin Table
July 2, 2020
Page 68 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 69 of 266
Rev 1.01
M251/M252
M251SG6AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PSIO0_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
/
EBI_AD14
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
UART0_RXD
/
USCI0_CLK
/
EBI_AD15
/
ACMP1_P2
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD
/
/
EBI_ADR16
EBI_ADR17
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nRTS
/
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
I2C1_SMBAL
/
/
/
USCI1_CTL1
USCI1_CLK
/
/
EBI_ADR18
EBI_ADR19
EBI_nWRL
/
/
/
EADC0_CH9
/
/
/
Analog14
Analog15
Analog16
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
I2C1_SMBSUS
I2C1_SMBAL
I2C0_SDA QSPI0_CLK
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
XT1_OUT BPWM1_CH1
/
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
/
/
/
TM0
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
USCI1_DAT0
/
EBI_nCS1
/
UART0_RXD
/
/
/
Figure 4.1-17 M251SG6AE Multi-function Pin Diagram
Pin M251SG6AE Pin Function
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
1
2
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
3
4
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020
Page 70 of 266
Rev 1.01
M251/M252
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
SIO0_CH7/TM3/INT3
5
6
7
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
13 VBAT
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
26
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
27
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
28
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
29
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
30
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
33
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020
Page 71 of 266
Rev 1.01
M251/M252
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
45 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
46 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
47 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
48 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
53
54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
55
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
64
Table 4.1-10 M251SG6AE Multi-function Pin Table
July 2, 2020
Page 72 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 73 of 266
Rev 1.01
M251/M252
4.1.2.6 M251 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M251KE3AE, M251KG3AE
M251KE3AE
BPWM0_CH5
/
PWM0_CH0
/
PSIO0_CH0
SC0_nCD
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
/
PWM0_CH1 PSIO0_CH1
/
/
USCI0_CTL0
/
98
PE.15
PE.14
VDDIO
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD PSIO0_CH1
/
BPWM0_CH3
BPWM0_CH2
/
/
PWM0_CH2
PWM0_CH3
/
/
PSIO0_CH2
PSIO0_CH3
/
/
USCI0_CTL1
USCI0_DAT1
/
SC0_PWR
SC0_RST
/
EBI_nRD
EBI_nWR
99
UART2_TXD / PSIO0_CH0
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
BPWM0_CH1
/
PWM0_CH4
/
USCI0_DAT0
/
SC0_DAT
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
BPWM0_CH0 PWM0_CH5
/
/
USCI2_CTL0
/
USCI0_CLK
/
SC0_CLK /
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
NC
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
USCI2_DAT1
USCI2_DAT0
/
I2C1_SCL
I2C1_SDA
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
/
/
PE.1
PE.0
NC
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
NC
NC
VSS
NC
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
NC
/
/
/
/
/
/
VSS
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
/
PWM1_CH3
BPWM1_CH0
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
/
BPWM1_CH1
/
TM1
/
INT2
LQFP128
LDO_CAP
VDD
I2C1_SMBAL PWM1_CH2
/
/
/
TM0
/ INT3
EBI_ADR16
/
I2C0_SDA
/
UART1_RXD
/
PWM1_CH1
/
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART1_TXD
/
PWM0_CH5
/
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
PWM0_CH3
/ PWM1_BRAKE0
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
USCI1_DAT1
USCI1_DAT0
/
/
UART1_nCTS
PWM0_CH2
/
/ PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
PE.9
PE.8
NC
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
NC
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PF.2
PF.3
NC
/
/
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
/
UART0_nRTS
/
/
EBI_ADR17
/
/
XT1_IN BPWM1_CH0
/
BPWM1_CH2
BPWM1_CH3
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
EADC0_CH9
/
/
/
/
Analog14
Analog15
Analog16
Analog17
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
EADC0_CH6
NC
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
NC
/
/
/
/
/
/
UART1_RXD
/
/
NC
Figure 4.1-18 M251KE3AE Multi-function Pin Diagram
Pin M251KE3AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
July 2, 2020
Page 74 of 266
Rev 1.01
M251/M252
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
3
4
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
7/TM3/INT3
5
6
7
8
PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O
PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O
PC.10/EBI_ADR6/PWM1_CH2
PC.9/EBI_ADR7/PWM1_CH3
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
9
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
10
11 VSS
12 VDD
13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
17 NC
18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5
19 PD.11/EBI_nCS1/UART1_TXD
20 PD.10/EBI_nCS2/UART1_RXD
21 NC
22 NC
23 NC
24 NC
25 NC
26 NC
27 NC
28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO
29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
30 VBAT
31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
33 NC
34 NC
35 NC
36 NC
July 2, 2020
Page 75 of 266
Rev 1.01
M251/M252
37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
39 NC
40 NC
41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0
42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1
43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0
44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1
45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4
46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5
47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4
48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
52 VSS
53 VDD
54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
56
57
58
59
60
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
61 VDDIO
62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0
63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1
nRESET
64
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
65
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
66
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
July 2, 2020
Page 76 of 266
Rev 1.01
M251/M252
68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3
69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
75 VSS
76 VDD
77 NC
78 NC
79 NC
80 NC
81 NC
82 NC
83 NC
84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4
85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5
86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6
87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7
88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0
93 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
94 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
95 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
96 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5
98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4
99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3
100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2
101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1
102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0
103 NC
July 2, 2020
Page 77 of 266
Rev 1.01
M251/M252
104 NC
105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1
106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0
107 NC
108 NC
109 NC
110 NC
111 NC
112 VSS
113 LDO_CAP
114 VDD
115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
116
117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
118
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
119
120 AVDD
121 VREF
122 AVSS
123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
127
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
128
Table 4.1-11 M251KE3AE Multi-function Pin Table
July 2, 2020
Page 78 of 266
Rev 1.01
M251/M252
M251KG6AE
BPWM0_CH5
/
PWM0_CH0
/
PSIO0_CH0
SC0_nCD
/
/
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
PE.1
PE.0
VSS
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
nRESET
BPWM0_CH4
/
PWM0_CH1 PSIO0_CH1
/
/
USCI0_CTL0
/
PE.15
PE.14
VDDIO
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD PSIO0_CH1
/
BPWM0_CH3
BPWM0_CH2
/
/
PWM0_CH2
PWM0_CH3
/
/
PSIO0_CH2
PSIO0_CH3
/
/
USCI0_CTL1
USCI0_DAT1
/
SC0_PWR
SC0_RST
/
EBI_nRD
UART2_TXD / PSIO0_CH0
/
/ EBI_nWR
BPWM0_CH1
/
PWM0_CH4
/
USCI0_DAT0
/
SC0_DAT
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
BPWM0_CH0 PWM0_CH5
/
/
USCI2_CTL0
/
USCI0_CLK
/
SC0_CLK /
USCI2_DAT1
USCI2_DAT0
/
I2C1_SCL
I2C1_SDA
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
LDO_CAP
VDD
/
/
/
/
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PSIO0_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
VSS
LQFP100
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
TM2_EXT
/
/
/
/
/
SPI0_MISO
/
EBI_AD14
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
UART0_RXD
/
USCI0_CLK
/
EBI_AD15
/
ACMP1_P2
/
/
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
I2C1_SMBAL
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
/
BPWM1_CH1
/
TM1
/ INT2
/
/
/
TM0 / INT3
VREF
EBI_ADR16
/
I2C0_SDA
/
UART1_RXD
UART1_TXD
/
PWM1_CH1
PWM0_CH5
/
AVSS
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
/
/
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD
/
/
EBI_ADR16
EBI_ADR17
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
PWM0_CH3
/ PWM1_BRAKE0
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
/
UART0_nRTS
/
USCI1_DAT1
USCI1_DAT0
/
/
UART1_nCTS
PWM0_CH2
/
/ PWM1_BRAKE1
BPWM1_CH2
BPWM1_CH3
/
/
/
USCI1_CTL1
USCI1_CLK
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
EADC0_CH9
/
/
/
/
Analog14
Analog15
Analog16
Analog17
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
EADC0_CH6
PE.9
PE.8
PF.2
/
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1 PWM0_BRAKE1
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
PWM0_CH0 / PWM0_BRAKE0
/
/
/
/
/
/
UART1_RXD
/
/
EBI_nCS1 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
Figure 4.1-19 M251KG6AE Multi-function Pin Diagram
Pin M251KG6AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
3
4
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
July 2, 2020
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Rev 1.01
M251/M252
SIO0_CH7/TM3/INT3
5
6
7
8
PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O
PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O
PC.10/EBI_ADR6/PWM1_CH2
PC.9/EBI_ADR7/PWM1_CH3
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
9
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
17 NC
18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5
19 PD.11/EBI_nCS1/UART1_TXD
20 PD.10/EBI_nCS2/UART1_RXD
21 NC
22 NC
23 NC
24 NC
25 NC
26 NC
27 NC
28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO
29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
30 VBAT
31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
33 NC
34 NC
35 NC
36 NC
37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
July 2, 2020
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Rev 1.01
M251/M252
39 NC
40 NC
41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0
42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1
43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0
44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1
45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4
46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5
47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4
48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
52 VSS
53 VDD
54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
56
57
58
59
60
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
61 VDDIO
62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0
63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1
nRESET
64
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
65
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
66
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3
69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020
Page 81 of 266
Rev 1.01
M251/M252
70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
75 VSS
76 VDD
77 NC
78 NC
79 NC
80 NC
81 NC
82 NC
83 NC
84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4
85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5
86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6
87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7
88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0
93 PA.12/I2C1_SCL/USCI2_DAT1/PSIO0_CH4/BPWM1_CH2
94 PA.13/I2C1_SDA/USCI2_DAT0/PSIO0_CH5/BPWM1_CH3
95 PA.14/UART0_TXD/USCI2_CLK/PSIO0_CH6/BPWM1_CH4
96 PA.15/UART0_RXD/USCI2_CTL1/PSIO0_CH7/BPWM1_CH5
97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5
98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4
99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3
100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2
101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1
102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0
103 NC
104 NC
105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1
July 2, 2020
Page 82 of 266
Rev 1.01
M251/M252
106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0
107 NC
108 NC
109 NC
110 NC
111 NC
112 VSS
113 LDO_CAP
114 VDD
115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
116
117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
118
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
119
120 AVDD
121 VREF
122 AVSS
123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
127
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
128
Table 4.1-12 M251KG6AE Multi-function Pin Table
July 2, 2020
Page 83 of 266
Rev 1.01
M251/M252
4.1.3
M252 Series Pin Diagram
4.1.3.1 M252 Series TSSOP 20-Pin Diagram
Corresponding Part Number: M252FC2AE
1
20
19
18
17
USB_D-
USB_VBUS
PF.1
2
3
USB_D+
USB_VDD33_CAP
VSS
PF.0
4
nRESET
LDO_CAP
VDD
5
16 PA.0
15 PA.1
6
PB.14
PA.2
PA.3
PF.2
PF.3
7
14
13
12
11
PB.13
8
PB.12
9
AVDD
10
Figure 4.1-20 M252 Series TSSOP 20-pin Diagram
4.1.3.2 M252 Series TSSOP 28-Pin Diagram
Corresponding Part Number: M252EC2AE
1
28
27
26
25
24
PC.0
USB_VBUS
2
PC.1
USB_D-
3
PF.1
USB_D+
4
PF.0
USB_VDD33_CAP
5
nRESET
VSS
6
7
23 PA.0
22 PA.1
21 PA.2
LDO_CAP
VDD
8
PB.14
PB.13
PB.12
AVDD
PA.3
PF.2
PF.3
PB.0
PB.1
PB.2
9
20
19
18
17
16
15
10
11
12
13
14
PB.5
PB.4
PB.3
Figure 4.1-21 M252 Series TSSOP 28-pin Diagram
July 2, 2020
Page 84 of 266
Rev 1.01
M251/M252
4.1.3.3 M252 Series QFN 33-Pin Diagram
Corresponding Part Number: M252ZD2AE, M252ZC2AE
25
16
15
14
13
12
11
10
9
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PF.2
Top transparent view
26
LDO_CAP
27
VDD
28
PB.15
QFN33
29
PB.14
30
PB.13
31
PB.12
33 VSS
32
AVDD
PF.3
Figure 4.1-22 M252 Series QFN 33-pin Diagram
July 2, 2020
Page 85 of 266
Rev 1.01
M251/M252
4.1.3.4 M252 Series LQFP 48-Pin Diagram
Corresponding Part Number: M252LG6AE, M252LE3AE, M252LD2AE, M252LC2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
LQFP48
AVSS
PB.7
PB.6
Figure 4.1-23 M252 Series LQFP 48-pin Diagram
July 2, 2020
Page 86 of 266
Rev 1.01
M251/M252
4.1.3.5 M252 Series LQFP 64-Pin Diagram
Corresponding Part Number: M252SD2AE, M252SC2AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
50
LDO_CAP
51
VDD
52
PC.14
53
PB.15
54
PB.14
55
PB.13
56
PB.12
LQFP64
57
AVDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
Figure 4.1-24 M252 Series LQFP 64-pin Diagram without VBAT
July 2, 2020
Page 87 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M252SG6AE, M252SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
50
LDO_CAP
51
VDD
52
PC.14
53
PB.15
54
PB.14
55
PB.13
56
PB.12
LQFP64
57
AVDD
58
VREF
59
AVSS
VSS
60
PB.11
PA.6
PA.7
PC.6
PC.7
PF.2
61
PB.10
62
PB.9
63
PB.8
64
PB.7
Figure 4.1-25 M252 Series LQFP 64-pin Diagram with VBAT
July 2, 2020
Page 88 of 266
Rev 1.01
M251/M252
4.1.3.6 M252 Series LQFP 128-Pin Diagram
Corresponding Part Number: M252KG6AE, M252KE3AE
97
64
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
nRESET
PE.15
PE.14
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PD.15
VDD
98
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
PE.1
PE.0
NC
NC
NC
VSS
NC
PA.6
PA.7
PC.6
PC.7
PC.8
PE.13
PE.12
PE.11
PE.10
PE.9
PE.8
NC
NC
VSS
ULQFP128
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
AVSS
PB.11
PB.10
PB.9
PB.8
PB.7
PB.6
NC
PF.2
PF.3
NC
NC
NC
NC
Figure 4.1-26 M252 Series LQFP 128-pin Diagram
July 2, 2020
Page 89 of 266
Rev 1.01
M251/M252
4.1.4
M252 Series Function Pin Diagram
4.1.4.1 M252 Series TSSOP 20-Pin Multi-function Pin Diagram
Corresponding Part Number: M252FC2AE
M252FC2AE
1
2
20
19
USB_D-
USB_VBUS
USB_D+
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
USB_VDD33_CAP
3
18 PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
17 nRESET
VSS
4
LDO_CAP
5
16 PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
15 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
14 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
VDD
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
6
7
PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
8
13
12
11
9
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
10
Figure 4.1-27 M252FC2AE Function Pin Diagram
Pin M252FC2AE Pin Function
1
2
3
4
5
6
7
8
9
USB_D-
USB_D+
USB_VDD33_CAP
VSS
LDO_CAP
VDD
PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
10 AVDD
11 PF.3/UART0_TXD/I2C0_SCL/XT1_IN
12 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
13 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
14 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
15 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
16 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
nRESET
17
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
18
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
19
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
20 USB_VBUS
July 2, 2020
Page 90 of 266
Rev 1.01
M251/M252
Table 4.1-13 M252FC2AE Multi-function Pin Table
4.1.4.2 M252 Series TSSOP 28-Pin Multi-function Pin Diagram
Corresponding Part Number: M252EC2AE
M252EC2AE
1
2
28
27
26
25
USB_VBUS
PC.0 / I2C0_SDA / PWM1_CH5
USB_D-
PC.1 / I2C0_SCL / PWM1_CH4
3
USB_D+
PF.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK
PF.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT
4
USB_VDD33_CAP
VSS
LDO_CAP
5
24 nRESET
6
23 PA.0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
22 PA.1 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
VDD
7
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
8
21 PA.2 / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
9
20 PA.3 / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / XT1_OUT
10
11
12
13
14
19
18
17
16
15
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
INT0 / TM0 / PWM0_CH0 / SC0_CLK / I2C0_SCL / EADC0_CH5 / PB.5
INT1 / TM1 / PWM0_CH1 / SC0_DAT / I2C0_SDA / EADC0_CH4 / PB.4
INT2 / TM2 / PWM0_BRAKE0 / PWM0_CH2 / SC0_RST / UART1_TXD / I2C1_SCL / EADC0_CH3 / PB.3
PB.0 / EADC0_CH0 / I2C1_SDA / PWM0_CH5 / PWM1_CH5 / PWM0_BRAKE1
PB.1 / EADC0_CH1 / I2C1_SCL / PWM0_CH4 / PWM1_CH4 / PWM0_BRAKE0
PB.2 / EADC0_CH2 / I2C1_SDA / UART1_RXD / SC0_PWR / PWM0_CH3 / TM3 / INT3
Figure 4.1-28 M252EC2AE Function Pin Diagram
Pin M252EC2AE Pin Function
1
2
3
4
5
6
7
8
9
USB_VBUS
USB_D-
USB_D+
USB_VDD33_CAP
VSS
LDO_CAP
VDD
PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
10 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
11 AVDD
12 PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0
13 PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1
14 PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
15 PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
16 PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
17 PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1
18 PF.3/UART0_TXD/I2C0_SCL/XT1_IN
19 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
July 2, 2020
Page 91 of 266
Rev 1.01
M251/M252
20 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
21 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
22 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
23 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4
28 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5
Table 4.1-14 M252EC2AE Multi-function Pin Table
July 2, 2020
Page 92 of 266
Rev 1.01
M251/M252
4.1.4.3 M252 Series QFN 33-Pin Multi-function Pin Diagram
Corresponding Part Number: M252ZC2AE, M252ZD2AE
M252ZC2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
nRESET
VDDIO
Top transparent view
LDO_CAP
VDD
PA.0 / QSPI0_MOSI0 / SC0_CLK / UART0_RXD / UART1_nRTS / PWM0_CH5
PA.1 / QSPI0_MISO0 / SC0_DAT / UART0_TXD / UART1_nCTS / PWM0_CH4
PA.2 / QSPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / PWM0_CH3
PA.3 / QSPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / UART0_nCTS / USCI0_CTL1 / EADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / UART0_nRTS / USCI0_DAT1 / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / UART0_TXD / USCI0_DAT0 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / UART0_RXD / USCI0_CLK / EADC0_CH12 / PB.12
AVDD
QFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN
Figure 4.1-29 M252ZC2AE Function Pin Diagram
Pin M252ZC2AE Pin Function
1
2
3
PB.5/EADC0_CH5/I2C0_SCL/SC0_CLK/PWM0_CH0/TM0/INT0
PB.4/EADC0_CH4/I2C0_SDA/SC0_DAT/PWM0_CH1/TM1/INT1
PB.3/EADC0_CH3/I2C1_SCL/UART1_TXD/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/INT2
July 2, 2020
Page 93 of 266
Rev 1.01
M251/M252
4
5
6
7
8
9
PB.2/EADC0_CH2/I2C1_SDA/UART1_RXD/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE1
PF.5/PWM0_CH0/X32_IN/EADC0_ST
PF.4/PWM0_CH1/X32_OUT
PF.3/UART0_TXD/I2C0_SCL/XT1_IN
10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT
11 PA.3/QSPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PWM0_CH2/CLKO/PWM1_BRAKE1
12 PA.2/QSPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PWM0_CH3
13 PA.1/QSPI0_MISO0/SC0_DAT/UART0_TXD/UART1_nCTS/PWM0_CH4
14 PA.0/QSPI0_MOSI0/SC0_CLK/UART0_RXD/UART1_nRTS/PWM0_CH5
15 VDDIO
nRESET
16
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT
17
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK
18
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
19 PC.1/QSPI0_MISO0/I2C0_SCL/PWM1_CH4
20 PC.0/QSPI0_MOSI0/I2C0_SDA/PWM1_CH5
21 USB_VBUS
22 USB_D-
23 USB_D+
24 USB_VDD33_CAP
25 VSS
26 LDO_CAP
27 VDD
28 PB.15/EADC0_CH15/USCI0_CTL1/UART0_nCTS/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
29 PB.14/EADC0_CH14/USCI0_DAT1/UART0_nRTS/PWM1_CH1/TM1_EXT/CLKO
30 PB.13/EADC0_CH13/USCI0_DAT0/UART0_TXD/PWM1_CH2/TM2_EXT
31 PB.12/EADC0_CH12/USCI0_CLK/UART0_RXD/PWM1_CH3/TM3_EXT
32 AVDD
Table 4.1-15 M252ZC2AE Multi-function Pin Table
July 2, 2020
Page 94 of 266
Rev 1.01
M251/M252
M252ZD2AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VSS
LDO_CAP
VDD
nRESET
VDDIO
Top transparent view
PA.0 / QSPI0_MOSI0 / SPI0_MOSI / SC0_CLK / UART0_RXD / UART1_nRTS / BPWM0_CH0 / PWM0_CH5
PA.1 / QSPI0_MISO0 / SPI0_MISO / SC0_DAT / UART0_TXD / UART1_nCTS / BPWM0_CH1 / PWM0_CH4
PA.2 / QSPI0_CLK / SPI0_CLK / SC0_RST / I2C0_SMBSUS / UART1_RXD / I2C1_SDA / BPWM0_CH2 / PWM0_CH3
PA.3 / QSPI0_SS / SPI0_SS / SC0_PWR / I2C0_SMBAL / UART1_TXD / I2C1_SCL / BPWM0_CH3 / PWM0_CH2 / CLKO / PWM1_BRAKE1
PF.2 / UART0_RXD / I2C0_SDA / QSPI0_CLK / XT1_OUT / BPWM1_CH1
PWM0_BRAKE1 / TM0_EXT / PWM1_CH0 / PSIO0_CH0 / UART0_nCTS / USCI0_CTL1 / SPI0_SS / EADC0_CH15 / PB.15
CLKO / TM1_EXT / PWM1_CH1 / PSIO0_CH1 / UART0_nRTS / USCI0_DAT1 / SPI0_CLK / EADC0_CH14 / PB.14
TM2_EXT / PWM1_CH2 / PSIO0_CH2 / UART0_TXD / USCI0_DAT0 / SPI0_MISO / ACMP1_P3 / ACMP0_P3 / EADC0_CH13 / PB.13
TM3_EXT / PWM1_CH3 / PSIO0_CH3 / UART0_RXD / USCI0_CLK / SPI0_MOSI / ACMP1_P2 / ACMP0_P2 / EADC0_CH12 / PB.12
AVDD
UQFN33
33 VSS
PF.3 / UART0_TXD / I2C0_SCL / XT1_IN / BPWM1_CH0
Figure 4.1-30 M252ZD2A Function Pin Diagram
Pin M252ZD2AE Pin Function
1
2
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
3
4
5
6
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
July 2, 2020
Page 95 of 266
Rev 1.01
M251/M252
1
7
8
9
PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
10 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
11
12 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
13 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
14 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
15 VDDIO
nRESET
16
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
17
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
18
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
19 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
20 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
21 USB_VBUS
22 USB_D-
23 USB_D+
24 USB_VDD33_CAP
25 VSS
26 LDO_CAP
27 VDD
28 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
29 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
30
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
31
32 AVDD
Table 4.1-16 M252ZD2AE Multi-function Pin Table
July 2, 2020
Page 96 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 97 of 266
Rev 1.01
M251/M252
4.1.4.4 M252 Series LQFP 48-Pin Multi-function Pin Diagram
Corresponding Part Number: M252LC2AE, M252LD2AE, M252LE3AE, M252LG6AE
M252LC2AE / M252LD2AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
PSIO0_CH2
PSIO0_CH3
/
PWM1_CH0
PWM1_CH1
UART0_TXD
UART0_RXD
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
/
/
/
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5 /
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
BPWM0_CH3
I2C0_SDA BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
/
/
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
CLKO / PWM1_BRAKE1
LQFP48
TM2_EXT
/
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
/
/
USCI0_CLK
/
/
/
UART0_RXD
UART0_TXD
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
I2C0_SDA
I2C0_SCL
/
PWM1_CH5
PWM1_CH4
QSPI0_CLK / XT1_OUT / BPWM1_CH1
/
BPWM1_CH3
/
ACMP1_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
BPWM1_CH2
/
ACMP0_WLAT
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
UART1_TXD
UART1_RXD
/
/
USCI1_DAT0
USCI1_DAT1
/
/
EADC0_CH7
EADC0_CH6
/
/
PB.7
PB.6
/
/
/
/
/
/
/
/
/ XT1_IN / BPWM1_CH0
Figure 4.1-31 M252LC2AE/M252LD2AE Function Pin Diagram
Pin M252LC2AE/M252LD2AE Pin Function
1
2
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
3
July 2, 2020
Page 98 of 266
Rev 1.01
M251/M252
4
5
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
1
6
7
8
9
PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT
PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
18 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
19
20 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
21 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
22 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1
29 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2
30 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3
31 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
32 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
33 USB_VBUS
34 USB_D-
35 USB_D+
July 2, 2020
Page 99 of 266
Rev 1.01
M251/M252
36 USB_VDD33_CAP
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1
41 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
42 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
43
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
44
45 AVDD
46 AVSS
47 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O
48 PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O
Table 4.1-17 M252LC2AE/M252LD2AE Multi-function Pin Table
July 2, 2020
Page 100 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M252LE3AE
M252LE3AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
ULQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
EADC0_CH7
EADC0_CH6
/
/
Analog16
Analog17
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-32 M252LE3AE Function Pin Diagram
Pin M252LE3AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
3
4
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
July 2, 2020
Page 101 of 266
Rev 1.01
M251/M252
7/TM3/INT3
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
5
6
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
7
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
18
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
19
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
20
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
21
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
22
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
33 USB_VBUS
July 2, 2020
Page 102 of 266
Rev 1.01
M251/M252
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
41
42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
43
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
44
45 AVDD
46 AVSS
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
47
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
48
Table 4.1-18 M252LE3AE Multi-function Pin Table
July 2, 2020
Page 103 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M252LG6AE
M252LG6AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PF.2
PF.3
/
/
/
/
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PSIO0_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
ULQFP48
TM2_EXT
/
/
/
/
/
SPI0_MISO
/
EBI_AD14
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
UART0_RXD
/
USCI0_CLK
/
EBI_AD15
/
ACMP1_P2
/
/
/
/
/
/
EBI_AD6
EBI_AD7
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
AVSS
/
/
/
/
/
/
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
UART1_TXD
UART1_RXD
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
/
/
EADC0_CH7
EADC0_CH6
/
/
Analog16
Analog17
/
/
PB.7
PB.6
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
/
/
/
/
/
/
/
/
/
/
XT1_IN BPWM1_CH0
/
Figure 4.1-33 M252LG6AE Function Pin Diagram
Pin M252LG6AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
3
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
July 2, 2020
Page 104 of 266
Rev 1.01
M251/M252
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
SIO0_CH7/TM3/INT3
4
5
6
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
7
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
10 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
11 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
12 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
13 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
14 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
15 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
16 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
17 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
18
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
19
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
20
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
21
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
22
23 VDDIO
nRESET
24
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
25
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
26
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
27 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
28 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
29 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
30 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
31 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
32 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
July 2, 2020
Page 105 of 266
Rev 1.01
M251/M252
33 USB_VBUS
34 USB_D-
35 USB_D+
36 USB_VDD33_CAP
37 VSS
38 LDO_CAP
39 VDD
40 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
41
42 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
43
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
44
45 AVDD
46 AVSS
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
47
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
48
Table 4.1-19 M252LG6AE Multi-function Pin Table
July 2, 2020
Page 106 of 266
Rev 1.01
M251/M252
4.1.4.5 M252 Series LQFP 64-Pin Multi-function Pin Diagram
Corresponding Part Number: M252SC2AE, M252SD2AE, M252SE3AE, M252SG6AE
M252SC2AE / M252SD2AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
LDO_CAP
VDD
nRESET
VDDIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
TM1
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PWM0_BRAKE1
CLKO
PWM1_CH2
PWM1_CH3
/
TM0_EXT
TM1_EXT
PSIO0_CH2
PSIO0_CH3
/
PWM1_CH0
PWM1_CH1
UART0_TXD
UART0_RXD
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5 /
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
BPWM0_CH3
I2C0_SDA BPWM0_CH4
PWM0_CH0
/
BPWM0_CH2
PWM0_CH2
PWM0_CH1
/
PWM0_CH3
/
/
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
/
/
/
/
/
LQFP64
PD.15
VDD
/
PWM0_CH5
/
TM3
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
UART0_nRTS
UART1_nCTS UART0_TXD
UART1_nRTS UART0_RXD
BPWM1_CH4 UART1_TXD
/
UART0_nCTS
/
/
EADC0_CH11
EADC0_CH10
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
/
/
USCI1_CTL0
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
/
/
USCI1_CTL1
USCI1_CLK
USCI1_DAT0
/
/
/
EADC0_CH9
EADC0_CH8
EADC0_CH7
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
I2C1_SMBAL
QSPI0_CLK
/
PWM1_CH3
PWM1_CH2
XT1_OUT /
/
BPWM1_CH1
BPWM1_CH0 TM0
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
/
/
/
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
UART0_RXD
/
I2C0_SDA
/
/
Figure 4.1-34 M252SC2AE/M252SD2AE Function Pin Diagram
Pin M252SC2AE/M252SD2AE Pin Function
1
2
3
PB.6/EADC0_CH6/USCI1_DAT1/UART1_RXD/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/INT4/ACMP1_O
PB.5/EADC0_CH5/ACMP1_N/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/UART2_TXD/TM0/INT0
PB.4/EADC0_CH4/ACMP1_P1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/UART2_RXD/TM1/INT1
July 2, 2020
Page 107 of 266
Rev 1.01
M251/M252
PB.3/EADC0_CH3/ACMP0_N/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PWM0_BRAKE0/TM2/IN
T2
4
5
6
PB.2/EADC0_CH2/ACMP0_P1/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/TM3/INT3
PB.1/EADC0_CH1/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_BRAKE0
PB.0/EADC0_CH0/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PWM0_BRAKE
1
7
8
9
PA.11/ACMP0_P0/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/USCI0_DAT0/BPWM0_CH1/TM1_EXT
10 PA.9/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/SC0_CLK/SPI0_MOSI/TAMPER0
13 PF.14/PWM1_BRAKE0/PWM0_BRAKE0/PSIO0_CH3/PWM0_CH4/CLKO/TM3/INT5
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
26 PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/BPWM0_CH4/PWM0_CH1
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/BPWM0_CH3/PWM0_CH2/CLKO/PWM1
_BRAKE1
27
28 PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/BPWM0_CH2/PWM0_CH3
29 PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/BPWM0_CH1/PWM0_CH4
30 PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/BPWM0_CH0/PWM0_CH5
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
33
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
July 2, 2020
Page 108 of 266
Rev 1.01
M251/M252
36 PC.4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/PSIO0_CH1
37 PC.3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/PSIO0_CH2
38 PC.2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/PSIO0_CH3
39 PC.1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/ACMP0_O
40 PC.0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/ACMP1_O
41 PD.3/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/USCI0_DAT0/SPI0_MISO
44 PD.0/USCI0_CLK/SPI0_MOSI/TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/TM1
53 PB.15/EADC0_CH15/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_BRAKE1
54 PB.14/EADC0_CH14/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1_CH2/TM2_
EXT
55
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_CH3/TM3_
EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
64 PB.7/EADC0_CH7/USCI1_DAT0/UART1_TXD/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/INT5/ACMP0_O
Table 4.1-20 M252SC2AE/M252SD2AE Multi-function Pin Table
July 2, 2020
Page 109 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M252SE3AE
M252SE3AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
50
LDO_CAP
51
VDD
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
52
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
53
54
55
56
57
58
59
60
61
62
63
64
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
/
/
/
/
ULQFP64
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nRTS
/
/
EBI_ADR17
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
I2C1_SMBAL
/
/
/
/
/
EBI_ADR18
EBI_ADR19
EBI_nWRL
/
/
/
EADC0_CH9
/
/
/
Analog14
Analog15
Analog16
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
I2C1_SMBSUS
I2C1_SMBAL
I2C0_SDA QSPI0_CLK
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
XT1_OUT BPWM1_CH1
/
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
/
/
/
TM0
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
USCI1_DAT0
/
EBI_nCS1
/
UART0_RXD
/
/
/
Figure 4.1-35 M252SE3AE Function Pin Diagram
Pin M252SE3AE Pin Function
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
1
2
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
3
4
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
July 2, 2020
Page 110 of 266
Rev 1.01
M251/M252
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
7/TM3/INT3
5
6
7
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
13 VBAT
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
26
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
27
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
28
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
29
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
30
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
33
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
July 2, 2020
Page 111 of 266
Rev 1.01
M251/M252
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
53
54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
55
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
64
Table 4.1-21 M252SE3AE Multi-function Pin Table
July 2, 2020
Page 112 of 266
Rev 1.01
M251/M252
Corresponding Part Number: M252SG6AE
M252SG6AE
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
nRESET
VDDIO
50
LDO_CAP
51
VDD
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
52
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
53
54
55
56
57
58
59
60
61
62
63
64
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PSIO0_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
/
EBI_AD14
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
TM3_EXT
/
PWM1_CH3
/
/
UART0_RXD
/
USCI0_CLK
/
EBI_AD15
/
ACMP1_P2
/
/
/
/
/
/
ULQFP64
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
VREF
AVSS
VSS
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD
/
/
EBI_ADR16
EBI_ADR17
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PA.6
PA.7
PC.6
PC.7
PF.2
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
BPWM1_CH1
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
BPWM1_CH4 EBI_nCS0
/
UART0_nRTS
/
/
/
/
/
/
/
BPWM1_CH2
BPWM1_CH3
PWM1_CH4 PWM1_BRAKE0
/
I2C1_SMBAL
/
/
/
USCI1_CTL1
USCI1_CLK
/
/
EBI_ADR18
EBI_ADR19
EBI_nWRL
/
/
/
EADC0_CH9
/
/
/
Analog14
Analog15
Analog16
/
/
/
PB.9
PB.8
PB.7
UART0_nRTS
UART0_nCTS
/
/
/
I2C1_SMBSUS
I2C1_SMBAL
I2C0_SDA QSPI0_CLK
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
XT1_OUT BPWM1_CH1
/
BPWM1_CH1
/
TM1
/ INT2
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
/
/
/
TM0
/
INT3
ACMP0_O
/
INT5
/
/
/
/
/
USCI1_DAT0
/
EBI_nCS1
/
UART0_RXD
/
/
/
Figure 4.1-36 M252SG3AE Function Pin Diagram
Pin M252SG6AE Pin Function
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
1
2
3
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
July 2, 2020
Page 113 of 266
Rev 1.01
M251/M252
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
4
5
6
7
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
SIO0_CH7/TM3/INT3
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
8
9
PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
10 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
11 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
12 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
13 VBAT
14 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
15 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
16 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
17 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
18 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
19 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
20 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
21 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
22 VSS
23 VDD
24 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
25 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
26
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
27
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
28
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
29
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
30
31 VDDIO
nRESET
32
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
33 PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
July 2, 2020
Page 114 of 266
Rev 1.01
M251/M252
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
34
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
35 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
36 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
37 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
38 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
39 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
40 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
41 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
42 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
43 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
44 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
45 USB_VBUS
46 USB_D-
47 USB_D+
48 USB_VDD33_CAP
49 VSS
50 LDO_CAP
51 VDD
52 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
53
54 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
55
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
56
57 AVDD
58 VREF
59 AVSS
60 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
61 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
62 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
63 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
64
Table 4.1-22 M252SG6AE Multi-function Pin Table
July 2, 2020
Page 115 of 266
Rev 1.01
M251/M252
4.1.4.6 M252 Series LQFP 128-Pin Multi-function Pin Diagram
Corresponding Part Number: M252KE3AE, M252KG6AE
M252KE3AE
BPWM0_CH5
/
PWM0_CH0
/
PSIO0_CH0
SC0_nCD
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
/
PWM0_CH1 PSIO0_CH1
/
/
USCI0_CTL0
/
98
PE.15
PE.14
VDDIO
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD PSIO0_CH1
/
BPWM0_CH3
BPWM0_CH2
/
/
PWM0_CH2
PWM0_CH3
/
/
PSIO0_CH2
PSIO0_CH3
/
/
USCI0_CTL1
USCI0_DAT1
/
SC0_PWR
SC0_RST
/
EBI_nRD
EBI_nWR
99
UART2_TXD / PSIO0_CH0
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
BPWM0_CH1
/
PWM0_CH4
/
USCI0_DAT0
/
SC0_DAT
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
BPWM0_CH0 PWM0_CH5
/
/
USCI2_CTL0
/
USCI0_CLK
/
SC0_CLK /
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
NC
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
USCI2_DAT1
USCI2_DAT0
/
I2C1_SCL
I2C1_SDA
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
/
/
PE.1
PE.0
NC
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
NC
NC
VSS
NC
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
NC
/
/
/
/
/
/
VSS
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
/
PWM1_CH3
BPWM1_CH0
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
/
BPWM1_CH1
/
TM1
/
INT2
LQFP128
LDO_CAP
VDD
I2C1_SMBAL PWM1_CH2
/
/
/
TM0
/ INT3
EBI_ADR16
/
I2C0_SDA
/
UART1_RXD
/
PWM1_CH1
/
TM1
UART0_nCTS
UART0_nRTS
/
USCI2_CLK
USCI0_CTL1
USCI0_DAT1
/
QSPI0_CLK
SPI0_SS
SPI0_CLK
/
USCI0_CTL0
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
UART1_TXD
/
PWM0_CH5
/
PWM0_BRAKE1
CLKO
PWM1_CH2 PSIO0_CH2
PWM1_CH3
/
TM0_EXT
/
PWM1_CH0
/
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
USCI0_CLK
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
EADC0_CH15
EADC0_CH14
/
/
Analog8
Analog9
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
PWM0_CH3
/ PWM1_BRAKE0
/
TM1_EXT
/
/
PWM1_CH1
UART0_TXD
/
/
/
/
USCI1_DAT1
USCI1_DAT0
/
/
UART1_nCTS
PWM0_CH2
/
/ PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
SPI0_MISO
SPI0_MOSI
/
/
EBI_AD14
EBI_AD15
/
/
ACMP1_P3
ACMP1_P2
/
/
ACMP0_P3
ACMP0_P2
/
/
EADC0_CH13
EADC0_CH12
/
/
Analog10
Analog11
TM3_EXT
/
/
PSIO0_CH3
/
UART0_RXD
/
PE.9
PE.8
NC
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
NC
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD USCI1_CTL1
USCI1_CLK
/
EBI_ADR16
/
/
EADC0_CH11
EADC0_CH10
/
/
Analog12
Analog13
/
/
PB.11
PB.10
PF.2
PF.3
NC
/
/
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
/
UART0_nRTS
/
/
EBI_ADR17
/
/
XT1_IN BPWM1_CH0
/
BPWM1_CH2
BPWM1_CH3
/
/
/
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
EADC0_CH9
/
/
/
/
Analog14
Analog15
Analog16
Analog17
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
EADC0_CH8
EADC0_CH7
EADC0_CH6
NC
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
NC
/
/
/
/
/
/
UART1_RXD
/
/
NC
Figure 4.1-37 M252KE3AE Function Pin Diagram
Pin M252KE3AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
July 2, 2020
Page 116 of 266
Rev 1.01
M251/M252
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
3
4
PB.2/EADC0_CH2/ACMP0_P1/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/PSIO0_CH
7/TM3/INT3
5
6
7
8
PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O
PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O
PC.10/EBI_ADR6/PWM1_CH2
PC.9/EBI_ADR7/PWM1_CH3
PB.1/EADC0_CH1/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH4/PWM0_
BRAKE0
9
PB.0/EADC0_CH0/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_CH5/PW
M0_BRAKE1
10
11 VSS
12 VDD
13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT
15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
17 NC
18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5
19 PD.11/EBI_nCS1/UART1_TXD
20 PD.10/EBI_nCS2/UART1_RXD
21 NC
22 NC
23 NC
24 NC
25 NC
26 NC
27 NC
28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO
29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
30 VBAT
31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
33 NC
34 NC
35 NC
36 NC
July 2, 2020
Page 117 of 266
Rev 1.01
M251/M252
37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
39 NC
40 NC
41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0
42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1
43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0
44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1
45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4
46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5
47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4
48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
52 VSS
53 VDD
54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
56
57
58
59
60
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5
61 VDDIO
62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0
63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1
nRESET
64
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
65
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
66
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
July 2, 2020
Page 118 of 266
Rev 1.01
M251/M252
68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3
69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
75 VSS
76 VDD
77 NC
78 NC
79 NC
80 NC
81 NC
82 NC
83 NC
84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4
85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5
86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6
87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7
88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5
98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4
99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3
100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2
101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1
102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0
103 NC
July 2, 2020
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Rev 1.01
M251/M252
104 NC
105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1
106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0
107 NC
108 NC
109 NC
110 NC
111 NC
112 VSS
113 LDO_CAP
114 VDD
115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
116
117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
118
PB.12/EADC0_CH12/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_CH3/PWM1_
CH3/TM3_EXT
119
120 AVDD
121 VREF
122 AVSS
123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
127
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
128
Table 4.1-23 M252KE3AE Multi-function Pin Table
July 2, 2020
Page 120 of 266
Rev 1.01
M251/M252
M252KG6AE
BPWM0_CH5
/
PWM0_CH0
/
PSIO0_CH0
SC0_nCD
/
/
/
/
/
/
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
nRESET
BPWM0_CH4
/
PWM0_CH1 PSIO0_CH1
/
/
USCI0_CTL0
/
98
PE.15
PE.14
VDDIO
/
/
EBI_AD9
EBI_AD8
/
/
UART2_RXD PSIO0_CH1
/
BPWM0_CH3
BPWM0_CH2
/
/
PWM0_CH2
PWM0_CH3
/
/
PSIO0_CH2
PSIO0_CH3
/
/
USCI0_CTL1
USCI0_DAT1
/
SC0_PWR
SC0_RST
/
EBI_nRD
EBI_nWR
99
UART2_TXD / PSIO0_CH0
/
/
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
BPWM0_CH1
/
PWM0_CH4
/
USCI0_DAT0
/
SC0_DAT
/
EBI_MCLK
EBI_ALE
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
/
/
/
/
/
/
QSPI0_MOSI0
QSPI0_MISO0
/
/
SPI0_MOSI
SPI0_MISO
/
/
SC0_CLK
SC0_DAT
/
/
UART0_RXD
UART0_TXD
/
/
UART1_nRTS
UART1_nCTS
/
/
PSIO0_CH7
PSIO0_CH6
/
/
USCI2_DAT1
USCI2_DAT0
/
/
BPWM0_CH0
BPWM0_CH1
/
/
PWM0_CH5
PWM0_CH4
/ DAC0_ST
BPWM0_CH0 PWM0_CH5
/
/
USCI2_CTL0
/
USCI0_CLK
/
SC0_CLK /
QSPI0_CLK
QSPI0_SS
/
SPI0_CLK
SPI0_SS SC0_PWR
SPI0_I2SMCLK SC0_nCD
UART0_nCTS UART0_TXD
TM3 INT1
/
SC0_RST
I2C0_SMBAL
UART0_nRTS
I2C0_SCL BPWM0_CH5
/
I2C0_SMBSUS
UART1_TXD
UART0_RXD
/
UART1_RXD
/
I2C1_SDA
PSIO0_CH4
I2C0_SDA USCI2_CTL1
PWM0_CH0
/
PSIO0_CH5
USCI2_CTL0
BPWM0_CH4 /
/
USCI2_CLK
BPWM0_CH3
PWM0_CH1
/
BPWM0_CH2
/
PWM0_CH3
NC
/
/
/
/
/
I2C1_SCL
/
/
/
/
PWM0_CH2
/
CLKO / PWM1_BRAKE1
USCI2_DAT1
USCI2_DAT0
/
I2C1_SCL
I2C1_SDA
/
/
QSPI0_MISO0
QSPI0_MOSI0
/
/
EBI_AD10
EBI_AD11
/
/
PE.1
PE.0
NC
QSPI0_MOSI1
QSPI0_MISO1
/
/
/
/
/
/
/
/
/
/
/
/
/
PD.15
VDD
/
PSIO0_CH7
/
PWM0_CH5
/
/
NC
NC
VSS
NC
PA.6
PA.7
PC.6
PC.7
PC.8
/
/
/
/
/
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
/
/
/
/
UART0_RXD
UART0_TXD
/
I2C1_SDA
I2C1_SCL
/
PWM1_CH5
PWM1_CH4
/
BPWM1_CH3
BPWM1_CH2
/
ACMP1_WLAT
ACMP0_WLAT
/
TM3
TM2
/
INT0
INT1
NC
/
/
/
/
/
/
VSS
UART0_nRTS
UART0_nCTS
/
/
I2C1_SMBSUS
I2C1_SMBAL
/
PWM1_CH3
PWM1_CH2 BPWM1_CH0
BPWM1_CH4
PWM1_CH0 / BPWM1_CH5
/
BPWM1_CH1
/
TM1
/ INT2
ULQFP128
LDO_CAP
VDD
/
/
/
TM0 / INT3
EBI_ADR16
/
I2C0_SDA
/
UART1_RXD
UART1_TXD
/
PWM1_CH1
PWM0_CH5
/
TM1
PSIO0_CH0
PSIO0_CH1
USCI0_DAT0
SPI0_MOSI
/
USCI2_CLK
UART0_nCTS
UART0_nRTS
/
QSPI0_CLK
USCI0_CTL1
USCI0_DAT1
EBI_AD14
ACMP1_P2
/
USCI0_CTL0
SPI0_SS
SPI0_CLK
/
SPI0_I2SMCLK
/
EBI_AD11
/
/
/
/
/
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
PE.13
PE.12
PE.11
PE.10
/
/
/
/
EBI_ADR15
/
/
/
/
I2C0_SCL
/
/
/
PWM0_BRAKE1
CLKO
PWM1_CH2
PSIO0_CH3
/
TM0_EXT
TM1_EXT
PSIO0_CH2
UART0_RXD
/
PWM1_CH0
PWM1_CH1
UART0_TXD
USCI0_CLK
/
/
/
/
/
/
EBI_AD12
EBI_AD13
/
/
/
/
EADC0_CH15
EADC0_CH14
EADC0_CH13
EADC0_CH12
EBI_ADR14
EBI_ADR13
EBI_ADR12
USCI1_CLK
/
UART1_nRTS
/
PWM0_CH4
PWM0_CH3
/ PWM1_BRAKE0
/
/
/
/
/
/
USCI1_DAT1
USCI1_DAT0
/
/
UART1_nCTS
PWM0_CH2
/
/ PWM1_BRAKE1
TM2_EXT
/
/
/
/
/
/
SPI0_MISO
/
/
ACMP1_P3
ACMP0_P2
/
ACMP0_P3
DAC0_OUT
TM3_EXT
/
PWM1_CH3
/
/
/
/
EBI_AD15
/
/
/
PE.9
PE.8
NC
/
/
EBI_ADR11
EBI_ADR10
/
/
USCI1_CTL0
USCI1_CTL1
/
/
UART2_RXD
UART2_TXD
/
PWM0_CH1
PWM0_CH0
/
PWM0_BRAKE1
/
/ PWM0_BRAKE0
VREF
AVSS
NC
BPWM1_CH0
/
SPI0_I2SMCLK
/
I2C1_SCL
/
UART0_nCTS
USCI1_CTL0
UART0_TXD
/
/
EBI_ADR16
EBI_ADR17
/
/
EADC0_CH11
EADC0_CH10
/
/
PB.11
PB.10
PF.2
PF.3
NC
/
/
EBI_nCS1
EBI_nCS0
/
/
UART0_RXD
UART0_TXD
/
I2C0_SDA
I2C0_SCL
/
QSPI0_CLK
/ XT1_OUT / BPWM1_CH1
BPWM1_CH1
I2C1_SMBAL
/
/
I2C1_SDA
UART1_nCTS
UART1_nRTS
/
UART0_nRTS
/
/
/
XT1_IN BPWM1_CH0
/
BPWM1_CH2
BPWM1_CH3
/
/
/
USCI1_CTL1
USCI1_CLK
/
/
EBI_ADR18
EBI_ADR19
/
/
/
/
EADC0_CH9
EADC0_CH8
EADC0_CH7
EADC0_CH6
/
/
/
/
PB.9
PB.8
PB.7
PB.6
/
I2C1_SMBSUS
/
/
/
UART0_RXD
UART1_TXD
/
NC
ACMP0_O
ACMP1_O
/
INT5
INT4
/
PWM1_CH4
PWM1_CH5
/
PWM1_BRAKE0
PWM1_BRAKE1
/
BPWM1_CH4
BPWM1_CH5
/
EBI_nCS0
EBI_nCS1
/
USCI1_DAT0
USCI1_DAT1
/
EBI_nWRL
EBI_nWRH
NC
/
/
/
/
/
/
UART1_RXD
/
/
NC
Figure 4.1-38 M252KG6AE Function Pin Diagram
Pin M252KG6AE Pin Function
PB.5/EADC0_CH5/ACMP1_N/EBI_ADR0/I2C0_SCL/USCI1_CTL0/SC0_CLK/PWM0_CH0/PSIO0_CH4/UART2_TXD/T
M0/INT0
1
2
3
4
PB.4/EADC0_CH4/ACMP1_P1/EBI_ADR1/I2C0_SDA/USCI1_CTL1/SC0_DAT/PWM0_CH1/PSIO0_CH5/UART2_RXD
/TM1/INT1
PB.3/EADC0_CH3/ACMP0_N/EBI_ADR2/I2C1_SCL/UART1_TXD/USCI1_DAT1/SC0_RST/PWM0_CH2/PSIO0_CH6/
PWM0_BRAKE0/TM2/INT2
PB.2/EADC0_CH2/ACMP0_P1/OPA0_O/EBI_ADR3/I2C1_SDA/UART1_RXD/USCI1_DAT0/SC0_PWR/PWM0_CH3/P
SIO0_CH7/TM3/INT3
July 2, 2020
Page 121 of 266
Rev 1.01
M251/M252
5
6
7
8
PC.12/EBI_ADR4/UART0_TXD/I2C0_SCL/SC0_nCD/PWM1_CH0/ACMP0_O
PC.11/EBI_ADR5/UART0_RXD/I2C0_SDA/PWM1_CH1/ACMP1_O
PC.10/EBI_ADR6/PWM1_CH2
PC.9/EBI_ADR7/PWM1_CH3
PB.1/EADC0_CH1/OPA0_N/EBI_ADR8/UART2_TXD/USCI1_CLK/I2C1_SCL/QSPI0_MISO1/PWM0_CH4/PWM1_CH
4/PWM0_BRAKE0
9
PB.0/EADC0_CH0/OPA0_P/EBI_ADR9/UART2_RXD/SPI0_I2SMCLK/I2C1_SDA/QSPI0_MOSI1/PWM0_CH5/PWM1_
CH5/PWM0_BRAKE1
10
11 VSS
12 VDD
13 PA.11/ACMP0_P0/EBI_nRD/USCI0_CLK/BPWM0_CH0/TM0_EXT
14 PA.10/ACMP1_P0/EBI_nWR/USCI0_DAT0/BPWM0_CH1/TM1_EXT/DAC0_ST
15 PA.9/EBI_MCLK/USCI0_DAT1/UART1_TXD/BPWM0_CH2/TM2_EXT
16 PA.8/EBI_ALE/USCI0_CTL1/UART1_RXD/BPWM0_CH3/TM3_EXT/INT4
17 NC
18 PD.12/EBI_nCS0/UART2_RXD/BPWM0_CH5/CLKO/EADC0_ST/INT5
19 PD.11/EBI_nCS1/UART1_TXD
20 PD.10/EBI_nCS2/UART1_RXD
21 NC
22 NC
23 NC
24 NC
25 NC
26 NC
27 NC
28 PF.7/EBI_ADR18/SC0_DAT/SPI0_MISO
29 PF.6/EBI_ADR19/SC0_CLK/SPI0_MOSI/EBI_nCS0/TAMPER0
30 VBAT
31 PF.5/UART2_RXD/UART2_nCTS/PWM0_CH0/BPWM0_CH4/X32_IN/EADC0_ST
32 PF.4/UART2_TXD/UART2_nRTS/PWM0_CH1/BPWM0_CH5/X32_OUT
33 NC
34 NC
35 NC
36 NC
37 PF.3/EBI_nCS0/UART0_TXD/I2C0_SCL/XT1_IN/BPWM1_CH0
38 PF.2/EBI_nCS1/UART0_RXD/I2C0_SDA/QSPI0_CLK/XT1_OUT/BPWM1_CH1
39 NC
July 2, 2020
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Rev 1.01
M251/M252
40 NC
41 PE.8/EBI_ADR10/USCI1_CTL1/UART2_TXD/PWM0_CH0/PWM0_BRAKE0
42 PE.9/EBI_ADR11/USCI1_CTL0/UART2_RXD/PWM0_CH1/PWM0_BRAKE1
43 PE.10/EBI_ADR12/USCI1_DAT0/PWM0_CH2/PWM1_BRAKE0
44 PE.11/EBI_ADR13/USCI1_DAT1/UART1_nCTS/PWM0_CH3/PWM1_BRAKE1
45 PE.12/EBI_ADR14/USCI1_CLK/UART1_nRTS/PWM0_CH4
46 PE.13/EBI_ADR15/I2C0_SCL/UART1_TXD/PWM0_CH5/PWM1_CH0/BPWM1_CH5
47 PC.8/EBI_ADR16/I2C0_SDA/UART1_RXD/PWM1_CH1/BPWM1_CH4
48 PC.7/EBI_AD9/UART0_nCTS/I2C1_SMBAL/PWM1_CH2/BPWM1_CH0/TM0/INT3
49 PC.6/EBI_AD8/UART0_nRTS/I2C1_SMBSUS/PWM1_CH3/BPWM1_CH1/TM1/INT2
50 PA.7/EBI_AD7/UART0_TXD/I2C1_SCL/PWM1_CH4/BPWM1_CH2/ACMP0_WLAT/TM2/INT1
51 PA.6/EBI_AD6/UART0_RXD/I2C1_SDA/PWM1_CH5/BPWM1_CH3/ACMP1_WLAT/TM3/INT0
52 VSS
53 VDD
54 PD.15/PSIO0_CH7/PWM0_CH5/TM3/INT1
55 PA.5/QSPI0_MISO1/UART0_nCTS/UART0_TXD/I2C0_SCL/BPWM0_CH5/PWM0_CH0
PA.4/QSPI0_MOSI1/SPI0_I2SMCLK/SC0_nCD/UART0_nRTS/UART0_RXD/I2C0_SDA/USCI2_CTL1/BPWM0_CH4/P
WM0_CH1
56
57
58
59
60
PA.3/QSPI0_SS/SPI0_SS/SC0_PWR/I2C0_SMBAL/UART1_TXD/I2C1_SCL/PSIO0_CH4/USCI2_CTL0/BPWM0_CH3/
PWM0_CH2/CLKO/PWM1_BRAKE1
PA.2/QSPI0_CLK/SPI0_CLK/SC0_RST/I2C0_SMBSUS/UART1_RXD/I2C1_SDA/PSIO0_CH5/USCI2_CLK/BPWM0_C
H2/PWM0_CH3
PA.1/QSPI0_MISO0/SPI0_MISO/SC0_DAT/UART0_TXD/UART1_nCTS/PSIO0_CH6/USCI2_DAT0/BPWM0_CH1/PW
M0_CH4
PA.0/QSPI0_MOSI0/SPI0_MOSI/SC0_CLK/UART0_RXD/UART1_nRTS/PSIO0_CH7/USCI2_DAT1/BPWM0_CH0/PW
M0_CH5/DAC0_ST
61 VDDIO
62 PE.14/EBI_AD8/UART2_TXD/PSIO0_CH0
63 PE.15/EBI_AD9/UART2_RXD/PSIO0_CH1
nRESET
64
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
PF.0/UART1_TXD/I2C1_SCL/UART0_TXD/BPWM1_CH0/ICE_DAT
65
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
PF.1/UART1_RXD/I2C1_SDA/UART0_RXD/BPWM1_CH1/ICE_CLK
66
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
67 PD.9/EBI_AD7/UART2_nCTS/PSIO0_CH2
68 PD.8/EBI_AD6/UART2_nRTS/PSIO0_CH3
69 PC.5/EBI_AD5/QSPI0_MISO1/UART2_TXD/I2C1_SCL/PWM1_CH0/PSIO0_CH0
70 PC.4/EBI_AD4/QSPI0_MOSI1/UART2_RXD/I2C1_SDA/PWM1_CH1/USCI2_CTL1/PSIO0_CH1
July 2, 2020
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Rev 1.01
M251/M252
71 PC.3/EBI_AD3/QSPI0_SS/UART2_nRTS/I2C0_SMBAL/PWM1_CH2/USCI2_CTL0/PSIO0_CH2
72 PC.2/EBI_AD2/QSPI0_CLK/UART2_nCTS/I2C0_SMBSUS/PWM1_CH3/USCI2_CLK/PSIO0_CH3
73 PC.1/EBI_AD1/QSPI0_MISO0/UART2_TXD/I2C0_SCL/PWM1_CH4/USCI2_DAT0/ACMP0_O
74 PC.0/EBI_AD0/QSPI0_MOSI0/UART2_RXD/I2C0_SDA/PWM1_CH5/USCI2_DAT1/ACMP1_O
75 VSS
76 VDD
77 NC
78 NC
79 NC
80 NC
81 NC
82 NC
83 NC
84 PD.7/UART1_TXD/I2C0_SCL/USCI1_CLK/PSIO0_CH4
85 PD.6/UART1_RXD/I2C0_SDA/USCI1_DAT1/PSIO0_CH5
86 PD.5/I2C1_SCL/USCI1_DAT0/PSIO0_CH6
87 PD.4/USCI0_CTL0/I2C1_SDA/USCI1_CTL1/PSIO0_CH7
88 PD.3/EBI_AD10/USCI0_CTL1/SPI0_SS/USCI1_CTL0/UART0_TXD
89 PD.2/EBI_AD11/USCI0_DAT1/SPI0_CLK/UART0_RXD
90 PD.1/EBI_AD12/USCI0_DAT0/SPI0_MISO
91 PD.0/EBI_AD13/USCI0_CLK/SPI0_MOSI/TM2
92 PD.13/EBI_AD10/SPI0_I2SMCLK/USCI2_CTL0
93 USB_VBUS
94 USB_D-
95 USB_D+
96 USB_VDD33_CAP
97 PE.7/PSIO0_CH0/PWM0_CH0/BPWM0_CH5
98 PE.6/SC0_nCD/USCI0_CTL0/PSIO0_CH1/PWM0_CH1/BPWM0_CH4
99 PE.5/EBI_nRD/SC0_PWR/USCI0_CTL1/PSIO0_CH2/PWM0_CH2/BPWM0_CH3
100 PE.4/EBI_nWR/SC0_RST/USCI0_DAT1/PSIO0_CH3/PWM0_CH3/BPWM0_CH2
101 PE.3/EBI_MCLK/SC0_DAT/USCI0_DAT0/PWM0_CH4/BPWM0_CH1
102 PE.2/EBI_ALE/SC0_CLK/USCI0_CLK/USCI2_CTL0/PWM0_CH5/BPWM0_CH0
103 NC
104 NC
105 PE.1/EBI_AD10/QSPI0_MISO0/I2C1_SCL/USCI2_DAT1
106 PE.0/EBI_AD11/QSPI0_MOSI0/I2C1_SDA/USCI2_DAT0
July 2, 2020
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Rev 1.01
M251/M252
107 NC
108 NC
109 NC
110 NC
111 NC
112 VSS
113 LDO_CAP
114 VDD
115 PC.14/EBI_AD11/SPI0_I2SMCLK/USCI0_CTL0/QSPI0_CLK/USCI2_CLK/TM1
PB.15/EADC0_CH15/EBI_AD12/SPI0_SS/USCI0_CTL1/UART0_nCTS/PSIO0_CH0/PWM1_CH0/TM0_EXT/PWM0_B
RAKE1
116
117 PB.14/EADC0_CH14/EBI_AD13/SPI0_CLK/USCI0_DAT1/UART0_nRTS/PSIO0_CH1/PWM1_CH1/TM1_EXT/CLKO
PB.13/EADC0_CH13/ACMP0_P3/ACMP1_P3/EBI_AD14/SPI0_MISO/USCI0_DAT0/UART0_TXD/PSIO0_CH2/PWM1
_CH2/TM2_EXT
118
PB.12/EADC0_CH12/DAC0_OUT/ACMP0_P2/ACMP1_P2/EBI_AD15/SPI0_MOSI/USCI0_CLK/UART0_RXD/PSIO0_
CH3/PWM1_CH3/TM3_EXT
119
120 AVDD
121 VREF
122 AVSS
123 PB.11/EADC0_CH11/EBI_ADR16/UART0_nCTS/I2C1_SCL/SPI0_I2SMCLK/BPWM1_CH0
124 PB.10/EADC0_CH10/EBI_ADR17/USCI1_CTL0/UART0_nRTS/I2C1_SDA/BPWM1_CH1
125 PB.9/EADC0_CH9/EBI_ADR18/USCI1_CTL1/UART0_TXD/UART1_nCTS/I2C1_SMBAL/BPWM1_CH2
126 PB.8/EADC0_CH8/EBI_ADR19/USCI1_CLK/UART0_RXD/UART1_nRTS/I2C1_SMBSUS/BPWM1_CH3
PB.7/EADC0_CH7/EBI_nWRL/USCI1_DAT0/UART1_TXD/EBI_nCS0/BPWM1_CH4/PWM1_BRAKE0/PWM1_CH4/IN
T5/ACMP0_O
127
PB.6/EADC0_CH6/EBI_nWRH/USCI1_DAT1/UART1_RXD/EBI_nCS1/BPWM1_CH5/PWM1_BRAKE1/PWM1_CH5/IN
T4/ACMP1_O
128
Table 4.1-24 M252KG6AE Multi-function Pin Table
July 2, 2020
Page 125 of 266
Rev 1.01
M251/M252
4.2 Pin Mapping
Different part number with same package might has different function. Please refer to the selection
guide in section 3.2, Pin Configuration in section 4.1 or NuTool - PinConfig.
Corresponding Part Number: M251/M252 Series
M251/M252 Series Pin Mapping
M251 Series
M252 Series
Pin Name
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
PB.5
PB.4
PB.3
PB.2
PC.12
PC.11
PC.10
PC.9
PB.1
PB.0
VSS
8
9
12
13
14
15
1
2
3
4
1
2
3
4
2
3
4
5
1
12
13
14
15
1
2
3
4
1
2
3
4
2
3
4
5
1
2
2
10
11
3
3
4
4
5
5
6
6
7
7
8
8
16
17
5
6
5
6
6
7
9
16
17
5
6
5
6
6
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VDD
PA.11
PA.10
PA.9
PA.8
NC
7
8
8
9
7
8
8
9
9
10
11
9
10
11
10
10
PD.12
PD.11
PD.10
NC
NC
NC
NC
NC
NC
NC
PF.7
PF.6
12
12
July 2, 2020
Page 126 of 266
Rev 1.01
M251/M252
M251 Series
M252 Series
Pin Name
PF.14 or VBAT
VBAT
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
13
13
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PF.5
PF.4
NC
7
8
11
12
14
15
7
8
11
12
14
15
NC
NC
NC
PF.3
PF.2
NC
12
13
18
19
9
13
14
16
17
11
12
18
19
9
13
14
16
17
10
10
NC
PE.8
PE.9
PE.10
PE.11
PE.12
PE.13
PC.8
PC.7
PC.6
PA.7
PA.6
VSS
18
19
20
21
22
23
24
25
26
27
28
29
30
31
18
19
20
21
22
23
24
25
26
27
28
29
30
31
15
16
15
16
VDD
PD.15
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
VDDIO
PE.14
17
18
19
20
21
22
23
17
18
19
20
21
22
23
14
15
16
17
20
21
22
23
11
12
13
14
15
13
14
15
16
20
21
22
23
11
12
13
14
15
July 2, 2020
Page 127 of 266
Rev 1.01
M251/M252
M251 Series
M252 Series
Pin Name
PE.15
nRESET
PF.0
ICE_DAT
PF.1
ICE_CLK
PD.9
PD.8
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
VSS
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
63
64
63
64
18
19
24
25
16
17
24
25
32
33
17
18
24
25
16
17
24
25
32
33
65
66
65
66
20
26
18
26
34
19
26
18
26
34
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
27
28
29
30
31
32
35
36
37
38
39
40
27
28
29
30
31
32
35
36
37
38
39
40
27
28
19
20
27
28
19
20
VDD
NC
NC
NC
NC
NC
NC
NC
PD.7
PD.6
PD.5
PD.4
PD.3
PD.2
PD.1
PD.0
PD.13
PA.12
PA.13
41
42
43
44
41
42
43
44
1
2
21
22
33
34
45
46
July 2, 2020
Page 128 of 266
Rev 1.01
M251/M252
M251 Series
M252 Series
Pin Name
PA.14
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
3
4
23
24
35
36
47
48
95
96
PA.15
USB_VBUS
USB_D-
USB_D+
20
1
1
2
3
21
22
23
33
34
35
45
46
47
93
94
95
2
USB_VDD33_CAP
3
4
24
36
48
96
PE.7
PE.6
PE.5
PE.4
PE.3
PE.2
NC
97
97
98
98
99
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
NC
PE.1
PE.0
NC
NC
NC
NC
NC
VSS
1
2
3
5
6
7
25
26
27
37
38
39
40
41
42
43
44
45
49
50
51
52
53
54
55
56
57
58
59
60
61
4
5
6
5
6
7
25
26
27
37
38
39
40
41
42
43
44
45
49
50
51
52
53
54
55
56
57
58
59
60
61
LDO_CAP
VDD
PC.14
PB.15
PB.14
PB.13
PB.12
AVDD
VREF
28
29
30
31
32
28
29
30
31
32
4
5
6
7
8
9
7
8
8
9
10
11
9
10
11
10
AVSS
PB.11
PB.10
46
46
July 2, 2020
Page 129 of 266
Rev 1.01
M251/M252
M251 Series
M252 Series
Pin Name
PB.9
20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin 20 Pin 28 Pin 32 Pin 48 Pin 64 Pin 128 Pin
62
63
64
1
125
126
127
128
62
63
64
1
125
126
127
128
PB.8
PB.7
47
48
47
48
PB.6
July 2, 2020
Page 130 of 266
Rev 1.01
M251/M252
4.3
Pin Function Description
Group
Pin Name
Type Description
ACMP0_N
A
O
A
A
A
A
I
Analog comparator 0 negative input pin.
ACMP0_O
Analog comparator 0 output pin.
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
Analog comparator 1 output pin.
ACMP0
A
O
A
A
A
A
I
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
BPWM0_CH0
BPWM0_CH1
BPWM0_CH2
BPWM0_CH3
BPWM0_CH4
BPWM0_CH5
BPWM1_CH0
BPWM1_CH1
BPWM1_CH2
BPWM1_CH3
BPWM1_CH4
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
ACMP1
I/O BPWM0 channel 0 output/capture input.
I/O BPWM0 channel 1 output/capture input.
I/O BPWM0 channel 2 output/capture input.
I/O BPWM0 channel 3 output/capture input.
I/O BPWM0 channel 4 output/capture input.
I/O BPWM0 channel 5 output/capture input.
I/O BPWM1 channel 0 output/capture input.
I/O BPWM1 channel 1 output/capture input.
I/O BPWM1 channel 2 output/capture input.
I/O BPWM1 channel 3 output/capture input.
I/O BPWM1 channel 4 output/capture input.
I/O BPWM1 channel 5 output/capture input.
BPWM0
BPWM1
BPWM1_CH5
CLKO
CLKO
DAC0
O
A
I
Clock Out
DAC0_OUT
DAC0_ST
EADC0_CH0
DAC0 channel analog output.
DAC0 external trigger input.
EADC0 channel 0 analog input.
A
EADC0_CH1
EADC0_CH2
EADC0_CH3
EADC0_CH4
A
A
A
A
EADC0 channel 1 analog input.
EADC0 channel 2 analog input.
EADC0 channel 3 analog input.
EADC0 channel 4 analog input.
EADC0
July 2, 2020
Page 131 of 266
Rev 1.01
M251/M252
Group
Pin Name
Type Description
EADC0 channel 5 analog input.
EADC0_CH5
A
A
A
A
A
A
A
A
A
A
A
I
EADC0_CH6
EADC0_CH7
EADC0_CH8
EADC0_CH9
EADC0_CH10
EADC0_CH11
EADC0_CH12
EADC0_CH13
EADC0_CH14
EADC0_CH15
EADC0 channel 6 analog input.
EADC0 channel 7 analog input.
EADC0 channel 8 analog input.
EADC0 channel 9 analog input.
EADC0 channel 10 analog input.
EADC0 channel 11 analog input.
EADC0 channel 12 analog input.
EADC0 channel 13 analog input.
EADC0 channel 14 analog input.
EADC0 channel 15 analog input.
EADC0_ST
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI_AD8
EBI_AD9
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
EBI_AD14
EBI_AD15
EBI_ADR0
EBI_ADR1
EBI_ADR2
EBI_ADR3
EBI_ADR4
EBI_ADR5
EBI_ADR6
EADC0 external trigger input.
I/O EBI address/data bus bit 0.
I/O EBI address/data bus bit 1.
I/O EBI address/data bus bit 2.
I/O EBI address/data bus bit 3.
I/O EBI address/data bus bit 4.
I/O EBI address/data bus bit 5.
I/O EBI address/data bus bit 6.
I/O EBI address/data bus bit 7.
I/O EBI address/data bus bit 8.
I/O EBI address/data bus bit 9.
I/O EBI address/data bus bit 10.
I/O EBI address/data bus bit 11.
I/O EBI address/data bus bit 12.
I/O EBI address/data bus bit 13.
I/O EBI address/data bus bit 14.
I/O EBI address/data bus bit 15.
EBI
O
O
O
O
O
O
O
EBI address bus bit 0.
EBI address bus bit 1.
EBI address bus bit 2.
EBI address bus bit 3.
EBI address bus bit 4.
EBI address bus bit 5.
EBI address bus bit 6.
July 2, 2020
Page 132 of 266
Rev 1.01
M251/M252
Group
Pin Name
Type Description
EBI address bus bit 7.
EBI_ADR7
EBI_ADR8
EBI_ADR9
EBI_ADR10
EBI_ADR11
EBI_ADR12
EBI_ADR13
EBI_ADR14
EBI_ADR15
EBI_ADR16
EBI_ADR17
EBI_ADR18
EBI_ADR19
EBI_ALE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
EBI address bus bit 8.
EBI address bus bit 9.
EBI address bus bit 10.
EBI address bus bit 11.
EBI address bus bit 12.
EBI address bus bit 13.
EBI address bus bit 14.
EBI address bus bit 15.
EBI address bus bit 16.
EBI address bus bit 17.
EBI address bus bit 18.
EBI address bus bit 19.
EBI address latch enable output pin.
EBI external clock output pin.
EBI chip select 0 output pin.
EBI chip select 1 output pin.
EBI chip select 2 output pin.
EBI read enable output pin.
EBI write enable output pin.
EBI high byte write enable output pin
EBI low byte write enable output pin.
EBI_MCLK
EBI_nCS0
EBI_nCS1
EBI_nCS2
EBI_nRD
EBI_nWR
EBI_nWRH
EBI_nWRL
PA.x~PH.x
I2C0_SCL
GPIO
I2C0
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
I2C0_SDA
I2C0_SMBAL
I2C0_SMBSUS
I2C1_SCL
I/O I2C0 data input/output pin.
O
O
I2C0 SMBus SMBALTER pin
I2C0 SMBus SMBSUS pin (PMBus CONTROL pin)
I/O I2C1 clock pin.
I2C1_SDA
I2C1_SMBAL
I2C1_SMBSUS
ICE_CLK
I/O I2C1 data input/output pin.
I2C1
O
O
I2C1 SMBus SMBALTER pin
I2C1 SMBus SMBSUS pin (PMBus CONTROL pin)
Serial wired debugger clock pin
I/O
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.
Serial wired debugger data pin
Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.
External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial
state.
ICE_DAT
nRESET
I/O
I
ICE
Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET
pin.
July 2, 2020
Page 133 of 266
Rev 1.01
M251/M252
Group
INT0
INT1
INT3
INT4
INT5
Pin Name
Type Description
INT0
I
I
External interrupt 0 input pin.
INT1
External interrupt 1 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
Operational amplifier 0 negative input pin.
INT3
I
INT4
I
INT5
I
OPA0_N
A
OPA0_O
A
A
Operational amplifier 0 output pin.
OPA0
OPA0_P
Operational amplifier 0 positive input pin.
PSIO0_CH0
PSIO1_CH0
PSIO2_CH0
PSIO3_CH0
PSIO4_CH0
PSIO5_CH0
PSIO6_CH0
PSIO7_CH0
I/O PSIO 0 channel 0 input/output pin.
I/O PSIO 0 channel 1 input/output pin.
I/O PSIO 0 channel 2 input/output pin.
I/O PSIO 0 channel 3 input/output pin.
I/O PSIO 0 channel 4 input/output pin.
I/O PSIO 0 channel 5 input/output pin.
I/O PSIO 0 channel 6 input/output pin.
I/O PSIO 0 channel 7 input/output pin.
PSIO0
CLKO
CLKO
O
I
Clock Out
PWM0_BRAKE0
PWM0 Brake 0 input pin.
PWM0 Brake 1 input pin.
PWM0_BRAKE1
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM1_BRAKE0
PWM1_BRAKE1
PWM1_CH0
PWM1_CH1
PWM1_CH2
PWM1_CH3
PWM1_CH4
PWM1_CH5
VDD
I
I/O PWM0 channel 0 output/capture input.
I/O PWM0 channel 1 output/capture input.
I/O PWM0 channel 2 output/capture input.
I/O PWM0 channel 3 output/capture input.
I/O PWM0 channel 4 output/capture input.
I/O PWM0 channel 5 output/capture input.
PWM0
I
I
PWM1 Brake 0 input pin.
PWM1 Brake 1 input pin.
I/O PWM1 channel 0 output/capture input.
I/O PWM1 channel 1 output/capture input.
I/O PWM1 channel 2 output/capture input.
I/O PWM1 channel 3 output/capture input.
I/O PWM1 channel 4 output/capture input.
I/O PWM1 channel 5 output/capture input.
PWM1
P
P
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
Ground pin for digital circuit.
Power
VSS
July 2, 2020
Page 134 of 266
Rev 1.01
M251/M252
Group
Pin Name
VDDIO
Type Description
P
P
P
P
Power supply for PA.0~PA.5.
VBAT
Power supply by batteries for RTC.
Power supply for internal analog circuit.
Ground pin for analog circuit.
AVDD
AVSS
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
VREF
A
A
LDO output pin.
Note: This pin needs to be connected with a 1uF capacitor.
LDO_CAP
QSPI0_CLK
I/O Quad SPI0 serial clock pin.
QSPI0_MISO0
QSPI0_MISO1
QSPI0_MOSI0
QSPI0_MOSI1
QSPI0_SS
I/O Quad SPI0 MISO0 (Master In, Slave Out) pin.
I/O Quad SPI0 MISO1 (Master In, Slave Out) pin.
I/O Quad SPI0 MOSI0 (Master Out, Slave In) pin.
I/O Quad SPI0 MOSI1 (Master Out, Slave In) pin.
I/O Quad SPI0 slave select pin.
QSPI0
SC0_CLK
O
Smart Card 0 clock pin.
SC0_DAT
I/O Smart Card 0 data pin.
SC0_PWR
O
O
I
Smart Card 0 power pin.
SC0
SC0_RST
SC0_nCD
Smart Card 0 reset pin.
Smart Card 0 card detect pin.
SPI0_CLK
I/O SPI0 serial clock pin.
SPI0_I2SMCLK
SPI0_MISO
SPI0_MOSI
SPI0_SS
I/O SPI0 I2S master clock output pin
I/O SPI0 MISO (Master In, Slave Out) pin.
I/O SPI0 MOSI (Master Out, Slave In) pin.
I/O SPI0 slave select pin.
SPI0
TAMPER0
I/O TAMPER detector loop pin 0.
TAMPER0
TM0
TM0
I/O Timer0 event counter input/toggle output pin.
I/O Timer0 external capture input/toggle output pin.
I/O Timer1 event counter input/toggle output pin.
I/O Timer1 external capture input/toggle output pin.
I/O Timer2 event counter input/toggle output pin.
I/O Timer2 external capture input/toggle output pin.
I/O Timer3 event counter input/toggle output pin.
I/O Timer3 external capture input/toggle output pin.
TM0_EXT
TM1
TM1
TM2
TM3
TM1_EXT
TM2
TM2_EXT
TM3
TM3_EXT
UART0_RXD
UART0_TXD
UART0_nCTS
UART0_nRTS
I
UART0 data receiver input pin.
UART0 data transmitter output pin.
UART0 clear to Send input pin.
UART0 request to Send output pin.
O
I
UART0
O
July 2, 2020
Page 135 of 266
Rev 1.01
M251/M252
Group
Pin Name
Type Description
UART1_RXD
UART1_TXD
UART1_nCTS
UART1_nRTS
UART2_RXD
UART2_TXD
UART2_nCTS
UART2_nRTS
USB_VBUS
USB_D-
I
UART1 data receiver input pin.
O
I
UART1 data transmitter output pin.
UART1 clear to Send input pin.
UART1 request to Send output pin.
UART2 data receiver input pin.
UART1
O
I
O
I
UART2 data transmitter output pin.
UART2 clear to Send input pin.
UART2 request to Send output pin.
Power supply from USB host or HUB.
USB differential signal D-.
UART2
O
P
A
A
A
USB
USB_D+
USB differential signal D+.
USB_VDD33_CAP
USCI0_CLK
USCI0_CTL0
USCI0_CTL1
USCI0_DAT0
USCI0_DAT1
USCI1_CLK
USCI1_CTL0
USCI1_CTL1
USCI1_DAT0
USCI1_DAT1
USCI2_CLK
USCI2_CTL0
USCI2_CTL1
USCI2_DAT0
USCI2_DAT1
X32_IN
Internal power regulator output 3.3V decoupling pin.
I/O USCI0 clock pin.
I/O USCI0 control 0 pin.
I/O USCI0 control 1 pin.
I/O USCI0 data 0 pin.
I/O USCI0 data 1 pin.
I/O USCI1 clock pin.
I/O USCI1 control 0 pin.
I/O USCI1 control 1 pin.
I/O USCI1 data 0 pin.
I/O USCI1 data 1 pin.
I/O USCI2 clock pin.
I/O USCI2 control 0 pin.
I/O USCI2 control 1 pin.
I/O USCI2 data 0 pin.
I/O USCI2 data 1 pin.
USCI0
USCI1
USCI2
I
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
External high speed crystal input pin.
External high speed crystal output pin.
X32
XT1
X32_OUT
O
I
XT1_IN
XT1_OUT
O
July 2, 2020
Page 136 of 266
Rev 1.01
M251/M252
5 BLOCK DIAGRAM
5.1 M251/M252 Block Diagram
USB* : Only supported in M252 series.
Please refer to the selection guide in section 4.2 for detailed information.
Figure 5.1-1 M251/M252 Block Diagram
July 2, 2020
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6 FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M23 Core
The Cortex® -M23 processor is a low gate count, two-stage, and highly energy efficient 32-bit RISC
processor, which has an AMBA AHB5 interface supporting Arm® TrustZone® technology, a debug
access port supporting serial wire debug and single-cycle I/O ports. It has an NVIC component and
MPU for memory-protection functionality. The processor also supports Security Extension. The
NuMicro® M251/M252 series is embedded with Cortex® -M23 processor.Figure 6.1-1 shows the
functional controller of the processor.
MTB AHB
Cortex-M23 processor
Micro Trace
Buffer
(MTB)
MTB
SRAM
interface
Cross
Trigger
Interface
(CTI)
Wakeup
Interrupt
Controller
(WIC)
Nested
Vectored
Interrupt
(NVIC)
Cortex-M23
processor
core
APB
IRQ and power
control interface
Embedded
Trace
Macrocell
(ETM)
ETM
ATB
interface
Memory Protection
Implementation
Defined Attribution
Unit (IDAU)
Security
Attribution
Unit (SAU)
Data
Watchpoint
and Trace
(DWT)
Flash Patch
and
Breakpoint Unit
(FPB)*
Secure
Memory
Protection Unit
(MPU_S)
Non-secure
Memory
Protection Unit
(MPU_NS)
Slave
AHB
interface
Bus matrix
Processor
ROM
table
Single-cycle
I/O port
AHB Master
Configurable
Optional
* Flash Patching is not supported in the Cortex-M23 processor.
Note: Security attribution unit, ETM, CTI and MTB functions are not supported in M251/M252.
Figure 6.1-1 Cortex® -M23 Block Diagram
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Cortex® -M23 processor features:
Armv8-M Baseline architecture.
Armv8-M Baseline Thumb® -2 instruction set that combines high code density with 32-bit
performance.
Support for single-cycle I/O access.
Power control optimization of system components.
Integrated sleep modes for low power consumption.
Optimized code fetching for reduced Flash and ROM power consumption.
A 32-bit Single cycle Hardware multiplier.
A 32-bit Hardware divider.
Deterministic, high-performance interrupt handling for time-critical applications.
Deterministic instruction cycle timing.
Support for system level debug authentication.
Support for Arm® Debug Interface Architecture ADIv5.1 Serial Wire Debug (SWD).
ETM for instruction trace.
Separated privileged and unprivileged modes.
Security Extension supporting a Secure and a Non-secure state.
Protected Memory System Architecture (PMSAv8) Memory Protection Units (MPUs) for
both Secure and Non-secure states.
Security Attribution Unit (SAU).
SysTick timers for both Secure and Non-secure states.
A Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor with
up to 240 interrupts.
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6.2 System Manager
6.2.1
Overview
System management includes the following sections:
System Reset
System Power Distribution
SRAM Memory Orginization
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be read
from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are from
peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
– Power-on Reset
– Low level on the nRESET pin with glitch filter time 24us
– Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
– Low Voltage Reset (LVR)
– Brown-out Detector Reset (BOD Reset)
– CPU Lockup Reset
Software Reset Sources
– CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
– MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
– CPU Reset for Cortex® -M23 core Only by writing 1 to CPURST (SYS_IPRST0[1])
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Glitch Filter
24 us
nRESET
~50k ohm
@3.3v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M23 only; the other reset sources will reset Cortex® -M23 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
POR
0x001
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
0x1
(CLK_APBCLK0[0])
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HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0800
0x0800
0x0800
0x0800
0x0800
-
0x0800
-
-
except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
BL
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
-
Reload
base
CONFIG0
-
-
-
on base on base on base on
on
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
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Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage
is lower than 0.2 VDD and the state keeps longer than 24 us (glitch filter), chip will be reset. The
nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the
state keeps longer than 24 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the
previous reset source is nRESET reset. Table 6.2-2 shows the nRESET reset waveform.
nRESET
0.7 VDD
24 us
0.2 VDD
24 us
nRESET Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is ready
for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a
POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows
the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR function
will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is
lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until the
AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
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(SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BODEN and BODVL
(SYS_BODCTL[18:16]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until the
AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by BODDGSEL. The
default value of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) is set by Flash controller user
configuration
register
CBODEN
(CONFIG0
[19]),
CBOV
(CONFIG0
[23:21])
and
CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the
CONFIG0 register. Figure 6.2-5 shows the Brown-out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the MCU
from failure status is one way to improve system reliability. The watchdog timer(WDT) is widely used to
check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog
time-out. User may decide to enable system reset during watchdog time-out to recover the system and
take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate
indication of seriously errant kernel software. This is the result of the CPU being locked because of an
unrecoverable exception following the activation of the processor’s built in system state protection
hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M23 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
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LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3
System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components operation.
Digital power from VDD and VSS supplies the power to the internal regulator which provides
a fixed 1.5V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
RTC power from regulator uninterrupted power domain provides, the power for RTC and
20 bytes backup registers.
Analog power (AVDD) should be the same voltage level of the digital power (VDD). Figure 6.2-6 shows
the ower distribution of the M251/M252 series.
Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
VDDIO
12-bit ADC
12-bit DAC
IO Cell
IO Cell
AVDD
AVSS
Temp. Sensor
OPA
Analog
Comparator
1.5V
RTC &
20 bytes backup register
Vbat
LVDR
RTC_LDO
(Low Voltage Reset, Brown-out
Detector)
38.4 kHz
LIRC
Digital Logic
SRAM
Flash
POR15
Oscillator
SW_DPD
1.5V
LDO_CAP
1uF
4 MHz
MIRC
Oscillator
48 MHz HIRC48
Oscillator
Power Management
PLL
GPIO except
PF.4~PF.6 and
PA.0~PA.5
4~32 MHz
crystal
oscillator
Power
On
Control
XT1_IN(PF.3)
USB 1.1
IO Cell
PHY
POR33
5V à 1.5V Regulator
XT1_OUT(PF.2)
M251/M252 Power Distribution
Figure 6.2-6 NuMicro® M251/M252 Power Distribution Diagram
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6.2.4
Power Modes and Wake-up Sources
The M251/M252 series has a power manager unit to support several operating modes for saving
power. Table 6.2-2 lists all power modes in the M251/M252 series.
Mode
CPU Operating Maximum
Speed ( MHz)
LDO_CAP(V) Clock Disable
Normal mode
Idle mode
48
1.5
1.5
All clocks are disabled by control register.
CPU enters Sleep mode
Only CPU clock is disabled.
Power-down mode
CPU enters Deep Sleep mode 1.5
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Fast wake up Power-
down mode (FWPD)
CPU enters Sleep mode
Power off
1.5
1.5
Most clocks are disabled except LIRC/LXT, and
only RTC/WDT/Timer/UART peripheral clocks
still enable if their clock sources are selected as
LIRC/LXT.
Deep Power-down
mode
Only LIRC/LXT still enable for RTC function and
wake-up timer usage
(DPD)
Table 6.2-2 Power Mode Table
There are different power mode entry settings. Each power mode has different entry setting and
leaving condition. Table 6.2-3 shows the entry setting for each power mode. When chip power-on, chip
is running ar normal mode. User can enter each mode by setting SLEEPDEEP (SCR[2]), PDEN
(CLK_PWRCTL:[7]) and PDMSEL (CLK_PMUCTL[2:0]) and execute WFI instruction.
Register/Instruction
Mode
SLEEPDEEP PDEN
PDMSEL
CPU Run WFI Instruction
(SCR[2])
(CLK_PWRCTL[7]) (CLK_PMUCTL[2:0])
Normal mode
0
0
0
0
0
0
NO
Idle mode
YES
(CPU enters Sleep mode)
Power-down mode
1
1
0
YES
(CPU enters Deep Sleep mode)
Fast wake up Power-down mode
(FWPD)
1
1
1
1
2
6
YES
YES
Deep Power-down mode
(CPU enters Sleep mode)
Table 6.2-3 Power Mode Difference Table
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-4 lists the
available clocks for each power mode.
Power Mode
Normal Mode
Idle Mode
Power-Down Mode
Definition
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
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executes WFI instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C, Timer, UART,
BOD, GPIO, EINT, USCI,
USBD and ACMP
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-4 Power Mode Difference Table
Fast wake up
Power-down Mode
CPU Clock OFF
Deep Power-down Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
Power-down Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
Flash Halt
Flash Halt
Flash Halt
POR Reset
nReset Pin
WDT reset
CHIP reset
LVR
BOD reset
Lockup reset
System reset
Power Level 0
CPU Clock ON
HXT, MIRC, HIRC48, LXT, LIRC, HCLK,
PCLK ON
Power Level 3
CPU Clock ON
LXT, LIRC, HCLK and PCLK ON
Flash ON
Flash ON
CPU executes WFI
CPU executes WFI
Interrupts occur
Interrupts occur
Idle Mode (PL0)
Idle Mode (PL3)
CPU Clock OFF
HXT, MIRC, HIRC48, PCLK ON
LXT, LIRC ON
CPU Clock OFF
LXT, LIRC and PCLK ON
Flash Halt
Flash Halt
Figure 6.2-7 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode.
2. LIRC (38.4 kHz OSC) ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
6. If UART clock source is selected as LXT and LXT is on.
Normal Mode
Idle Mode
ON
Power-Down Mode PD
DPD
Halt
HXT (4~32 MHz XTL)
MIRC (4 MHz OSC)
HIRC48 (48 MHz OSC)
LXT (32768 Hz XTL)
LIRC (38.4 kHz OSC)
PLL
ON
ON
Halt
Halt
ON
Halt
ON
ON
Halt
Halt
ON
ON
ON/OFF1
ON/OFF2
Halt
ON/OFF1
ON/OFF2
Halt
ON
ON
ON/OFF
ON/OFF
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LDO
CPU
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
OFF
Halt
HCLK/PCLK
SRAM retention
FLASH
GPIO
Halt
Halt
ON
OFF
Halt
Halt
Halt
Halt
PDMA
TIMER
PWM
Halt
Halt
ON/OFF3
Halt
Halt
Halt
WDT
ON/OFF4
Halt
Halt
WWDT
RTC
Halt
ON/OFF5
ON/OFF6
Halt
ON/OFF5
Halt
UART
SC
Halt
USCI
Halt
Halt
I2C
Halt
Halt
SPI
Halt
Halt
USBD
ADC
Halt
Halt
Halt
Halt
ACMP
Halt
Halt
Table 6.2-5 Clocks in Power Modes
Wake-up sources in Power-down mode:
RTC, WDT, I²C, Timer, UART, USCI, BOD, GPIO, USBD, and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table
6.2-5 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Power-Down Mode
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
PD
Source
DPD
FWKPD
Brown-Out Detector
Interrupt
BOD
Y
Y
N
Y
N
N
Y
N
After software writes 1 to clear BODIF (SYS_BODCTL[4]).
After software writes 1 to clear LVRF (SYS_RSTSTS[3])
LVR
LVR Reset
After software writes 1 to clear LVRWK (CLK_PMUSTS[12])
when DPD mode is entered.
INT
External Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
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GPIO
GPIO Interrupt
Y
N
N
Y
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO(PC.0)
Wake-up pin
Rising or falling edge
event, 1-pin
PINWK(CLK_PMUSTS[0]) is cleared when DPD mode is
entered.
GPIO(PB.0)
Wake-up pin
Rising or falling edge
event, 1-pin
PINWK(CLK_PMUSTS[3]) is cleared when DPD mode is
entered.
N
N
N
N
Y
Y
Y
Y
Y
N
GPIO(PB.2)
Wake-up pin
Rising or falling edge
event, 1-pin
PINWK(CLK_PMUSTS[4]) is cleared when DPD mode is
entered.
GPIO(PB.12) Rising or falling edge
Wake-up pin
PINWK(CLK_PMUSTS[5]) is cleared when DPD mode is
entered.
event, 1-pin
GPIO(PF.6)
Wake-up pin
Rising or falling edge
event, 1-pin
PINWK(CLK_PMUSTS[6]) is cleared when DPD mode is
entered.
TIMER
After software writes 1 to clear TWKF (TIMERx_INTSTS[1])
and TIF (TIMERx_INTSTS[0]).
Timer Interrupt
Wakeup timer
DPD_TMRWK
(CLK_PMUSTS[2])
or
DPD_TMRWK
Wakeup by wake-up
timer time-out
N
Y
Y
N
(CLK_PMUSTS[6]) is cleared when SPD or DPD mode is
entered.
WDT
RTC
After software writes 1 to clear WKF (WDT_CTL[5]) (Write
Protect).
WDT Interrupt
Alarm Interrupt
Y
Y
N
N
After software writes 1 to clear ALMIF (RTC_INTSTS[0]).
After software writes 1 to clear TICKIF (RTC_INTSTS[1]).
Time Tick Interrupt
RTC
RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is
entered.
Wakeup by RTC alarm
N
N
N
Y
Y
Y
Wakeup by RTC tick
time
RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is
entered.
Wakeup by tamper
event
RTCWK (CLK_PMUSTS[2]) is cleared when DPD mode is
entered.
UART
nCTS wake-up
Y
Y
N
N
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
Incoming Data wake-up
Received FIFO
Threshold Wake-up
After
software
writes
1
to
clear
RFRTWKF
Y
Y
N
N
(UARTx_WKSTS[2]).
RS-485 AAD Mode
Wake-up
After
software
writes
1
to
clear
RS485WKF
(UARTx_WKSTS[3]).
Received FIFO
Threshold Time-out
Wake-up
After
software
writes
1
to
clear
TOUTWKF
Y
N
(UARTx_WKSTS[4]).
CTS Toggle
Data Toggle
Data toggle
Y
Y
Y
N
N
N
After software writes 1 to clear WKF (UUART_WKSTS[0]).
After software writes 1 to clear WKF (UUART_WKSTS[0]).
After software writes 1 to clear WKF (UI2C_WKSTS[0]).
USCI UART
USCI I2C
After
software
writes
1
to
clear
WKAKDONE
Address match
Y
N
(UI2C_PROTSTS[16], and then writes
(UI2C_WKSTS[0]).
1
to clear WKF
USCI SPI
I2C
SS Toggle
Y
Y
Y
N
N
N
After software writes 1 to clear WKF (USPI_WKSTS[0]).
After software writes 1 to clear WKAKDONE (I2C_WKSTS[1]).
Then software writes 1 to clear WKIF(I2C_WKSTS[0]).
Address match wake-up
Remote Wake-up
USBD
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
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ACMP
Comparator Power-
Down Wake-Up Interrupt
After software writes 1 to clear WKIF0 (ACMP_STATUS[8])
and WKIF1 (ACMP_STATUS[9]).
Y
N
Table 6.2-6 Condition of Entering Power-down Mode Again
Chip Bus Matrix
6.2.5
The M251/M252 series provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown in Table 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The M251/M252
series only supports little-endian data format.
6.2.6
System Memory Map
The M251/M252 series provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown inTable 6.2-7. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The M251/M252
series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0003_FFFF
0x2000_0000 – 0x2000_7FFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
SRAM0_BA
EXTMEM_BA
FLASH Memory Space (256 Kbytes)
SRAM Memory Space (32 Kbytes)
External Memory Space (256 Mbytes)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_C000 – 0x4000_CFFF
0x4001_0000 – 0x4001_0FFF
0x4003_1000 – 0x4003_1FFF
SYS_BA
CLK_BA
NMI_BA
GPIO_BA
PDMA_BA
FMC_BA
EBI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
External Bus Interface Control Registers
CRC Generator Registers
CRC_BA
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_5000 – 0x4004_5FFF
0x4004_6000 – 0x4004_6FFF
0x4004_7000 – 0x4004_7FFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
WDT_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Enhanced Analog-Digital-Converter (EADC) Control Registers
Analog Comparator 0/ 1 Control Registers
OP Amplifier Control Registers
RTC_BA
EADC_BA
ACMP01_BA
OPA_BA
DAC_BA
DAC Control Registers
TMR01_BA
TMR23_BA
PWM0_BA
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
PWM0 Control Registers
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0x4005_9000 – 0x4005_9FFF
0x4005_A000 – 0x4005_AFFF
0x4005_B000 – 0x4005_BFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x4009_0000 – 0x4009_0FFF
0x400C_0000 – 0x400C_0FFF
0x400C_3000 – 0x400C_3FFF
0x400D_0000 – 0x400D_0FFF
0x400D_1000 – 0x400D_1FFF
0x400D_2000 – 0x400D_2FFF
PWM1_BA
BPWM0_BA
BPWM1_BA
QSPI0_BA
SPI0_BA
PWM1 Control Registers
BPWM0 Control Registers
BPWM1 Control Registers
QSPI0 Control Registers
SPI0 Control Registers
UART0_BA
UART1_BA
UART2_BA
I2C0_BA
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
I2C0 Control Registers
I2C1_BA
I2C1 Control Registers
SC0_BA
Smartcard Host 0 Control Registers
USB Device Control Register
PSIO Control Register
USBD_BA
PSIO_BA
USCI0_BA
USCI1_BA
USCI2_BA
USCI0 Control Registers
USCI1 Control Registers
USCI2 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-7 Address Space Assignments for On-Chip Controllers
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6.2.7
SRAM Memory Orginization
The M251/M252 series supports embedded SRAM with up to 32 Kbytes size.
Supports up to 32 Kbytes SRAM
Supports byte /half word /word write
Supports oversize response error
Table 6.2-9 shows the M251/M252 series SRAM organization. The address between 0x2000_8000 to
0x3FFF_FFFF is illegal memory space and chip will enter hardfault if CPU accesses these illegal
memory addresses.
0x3FFF_FFFF
Reserved
Reserved
Reserved
Reserved
0x2000_8000
32K byte
SRAM bank0
0x2000_4000
0x2000_2000
0x2000_1000
16K byte
SRAM bank0
8K byte
SRAM bank0
4K byte
SRAM bank0
0x2000_0000
32K byte device
16K byte device
4K byte device
8K byte device
Figure 6.2-8 SRAM Memory Organization
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6.2.8
IRC Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator) and MIRC trim (4.032 RC
oscillator), according to the accurate LXT (32.768 kHz crystal oscillator) or internal USB synchronous
mode, automatically gets accurate output frequency, 0.25 % deviation within all temperature ranges.
For instance, the system needs an accurate 4.032 MHz clock. In such case, if neither using use PLL
as the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_MIRCTRIMCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_MIRCTRIMCTL[1:0]
trim frequency selection) to “10”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_MIRCTRIMSTS[0] MIRC frequency lock status) “1” indicates the MIRC output
frequency is accurate within 0.25% deviation.
In HIRC case, the system needs an accurate 48 MHz clock. In such case, if neither using use PLL as
the system clock source nor soldering 32.768 kHz crystal in system, user has to set REFCKSEL
(SYS_HIRCTRIMCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_HIRCTRIMCTL[1:0]
trim frequency selection) to “10”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_HIRCTRIMSTS[8] HIRC frequency lock status) “1” indicates the HIRC output
frequency is accurate within 0.25% deviation.
HIRC trim and MIRC trim only can work properly when the clock sources are stable. When the RC
clock or the reference clock are not stable or the system go into power down, HIRC trim and MIRC trim
need to wait until the clock are stable or system wake up, then it can be enable or it will get a clock
error flag.
6.2.9
UART0_TXD/USCI0_DAT0 Modulation with PWM
This chip supports UART0_TXD/USCI_DAT0 to modulate with PWM channel. User can set
MODPWMSEL(SYS_MODCTL[7:4]) to select which PWM0 channel to modulate with
UART0_TXD/USCI0_DAT0 and set MODEN(SYS_MODCTL[0]) to enable modulation function.
PWM0_CHx
UART0_TXD/USCI0_DAT0
MODH=0
MODH=1
Figure 6.2-11 UART0_TXD/USCI0_DAT0 Modulated with PWM Channel
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6.2.10 System Timer (SysTick)
The Cortex® -M23 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_LOAD value rather than
an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M23 Technical Reference Manual”
and “Arm v8-M Architecture Reference Manual”.
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6.2.11 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the
stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC
from privileged mode, but you can cause interrupts to enter a pending state in user mode if you enable
the Configuration and Control Register. Any other user mode access causes a bus fault. You can
access all NVIC registers using byte, halfword, and word accesses unless otherwise stated. NVIC
registers are located within the SCS (System Control Space). All NVIC registers and system debug
registers are little-endian regardless of the endianness state of the processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-64 interrupts.
A programmable priority level of 0-3 for each interrupt; a higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
6.2.11.1 Exception Model and System Interrupt Map
Table 6.2-8 lists the exception model supported by the M251/M252 series. Software can set 4 levels of
priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority
is denoted as “0x00” and the lowest priority is denoted as “0xC0” (The 6-LSB always 0). The default
priority of all the user-configurable interrupts is “0x00”. Note that priority “0” is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixed
at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start
address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
The vector table contains the initialization value for the stack pointer on reset, and the entry point
addresses for all exception handlers. The vector number on previous page defines the order of entries
in the vector table associated with exception handler entry as illustrated in previous section.
Exception Type
Reset
Vector Number
Vector Address
0x00000004
0x00000008
0x0000000C
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
SVCall
3
-1
4~ 10
11
Reserved
Configurable
Reserved
Configurable
0x0000002C
Reserved
PendSV
12~13
14
0x00000038
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SysTick
15
0x0000003C
Configurable
Configurable
0x00000000 +
Interrupt (IRQ0 ~ IRQ63)
16 ~ 63
(Vector Number)*4
Table 6.2-8 Exception Model
Interrupt Number
(Bit In Interrupt
Registers)
Vector
Number
Interrupt Name
Interrupt Description
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
-
-
System exceptions
0
BODOUT
IRC_INT
Brown-Out low voltage detected interrupt
IRC TRIM interrupt
1
2
PWRWU_INT
Reserved
CLKFAIL
Reserved
RTC_INT
TAMPER_INT
WDT_INT
WWDT_INT
EINT0
Clock controller interrupt for chip wake-up from power-down state
Reserved
3
4
Clock fail detected interrupt
5
Reserved
6
Real time clock interrupt
7
Backup register tamper interrupt
Watchdog Timer interrupt
8
9
Window Watchdog Timer interrupt
External interrupt from PA.0, PD.2 or PE.4 pins
External interrupt from PB.0, PD.3 or PE.5 pins
External interrupt from PC.0 pin
External interrupt from PD.0 pin
External interrupt from PE.0 pin
External interrupt from PF.0 pin
External interrupt from PA[15:0] pin
External interrupt from PB[15:0] pin
External interrupt from PC[15:0] pin
External interrupt from PD[15:0] pin
External interrupt from PE[15:0] pin
External interrupt from PF[15:0] pin
QSPI0 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
EINT1
EINT2
EINT3
EINT4
EINT5
GPA_INT
GPB_INT
GPC_INT
GPD_INT
GPE_INT
GPF_INT
QSPI0_INT
SPI0_INT
BRAKE0_INT
PWM0_P0_INT
PWM0_P1_INT
SPI0 interrupt
PWM0 brake interrupt
PWM0 pair 0 interrupt
PWM0 pair 1 interrupt
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43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
PWM0_P2_INT
BRAKE1_INT
PWM1_P0_INT
PWM1_P1_INT
PWM1_P2_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART0_INT
UART1_INT
I2C0_INT
PWM0 pair 2 interrupt
PWM1 brake interrupt
PWM1 pair 0 interrupt
PWM1 pair 1 interrupt
PWM1 pair 2 interrupt
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
UART0 interrupt
UART1 interrupt
I2C0 interrupt
I2C1_INT
I2C1 interrupt
PDMA_INT
DAC_INT
PDMA interrupt
DAC interrupt
EADC_INT
EADC1_INT
ACMP01_INT
BPWM0
EADC interrupt source 0
EADC interrupt source 1
ACMP0 and ACMP1 interrupt
BPWM0 interrupt
EADC interrupt source 2
EADC interrupt source 3
UART2 interrupt
Reserved
EADC_INT2
EADC_INT
UART2_INT
Reserved
USCI0
USCI0 interrupt
Reserved
Reserved
USCI1
USCI1 interrupt
USBD_INT
BPWM1
USB device interrupt
BPWM1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SC0_INT
Smart card host 0 interrupt
RTC LVR interrupt
USCI2 interrupt
RTCLVR_INT
USCI2
Reserved
Reserved
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78
79
62
63
OPA0
OPA0 interrupt
Reserved
Reserved
Table 6.2-9 Interrupt Number Table
6.2.11.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until
cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all peripheral
clocks. The clock controller also implements the power control function with the individually clock
ON/OFF control, clock source selection and a clock divider. The chip will not enter Power-down mode
until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and Cortex® -M23 core executes
the WFI instruction. After that, chip enters Power-down mode and wait for wake-up interrupt source
triggered to leave Power-down mode. In Power-down mode, the clock controller turns off the 4~32
MHz external high speed crystal (HXT) , 48 MHz internal high speed RC oscillator (HIRC) and 4 MHz
internal median speed RC oscillator (MIRC) to reduce the overall system power consumption Figure
6.3-1 shows the clock generator and the overview of the clock source control.
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NOTE:
Module in AHB or Bus matrix
: xxxx is register name
xxxx
e.g.
AHBCLK : AHBCLK register settings
CLKDIVx : CLKDIV0 ~ 4 register settings
MIRC
4MHz
MIRC
HIRC
PLL
FMC(Read)
ISP
HIRC
48MHz
One per module
CLKDI
Vx
HCLKDIV
PDMA
EBI
7
PLL
/4
HCLK
HCLK
HXT OSC
4-32MHz
AHBCL
CRC
/1 ~ 16
HXT
K
GPIOA~F
LIRC
LXT
LIRC
38.4KHz
HIRC
FMC(Write)
AHBCL
K
LXT
32KHz
RTC, WDT, WWDT
RTC
w/ Tamper
detection
CPU
SRAM
APBCLK
x
CLKSE
Lx
PCLK0SEL
/1,2,4,8,16
CLKSE
WDT
HCLK
/2048
for APB0
APBCLK
x
Peripheral Clock
PCLK0
PCLK1
WWDT
for APB1
Peripheral Clock
Lx
PCLK1SEL
/1,2,4,8,16
SOF
LIRC
MIRC
HIRC
HCLK
LXT
USB Clock TreeCLKDIV
CLKO
x
CLKO
HXT
PLL
APBCL
Kx
USBDIV
/1 ~ 16
HIRC
48MHz USB1.1 Device
Controller
CLKO
1Hz from RTC module
APBCL
Kx
USB1.1
PHY
HCLK
LIRC
BOD
T0~T3
NOTE: T0 for TMR0,
T1 for TMR1,
Peripheral Clock Tree
QSPI0
SPI0
1
T2 for TMR2,
T3 for TMR3
One per module
PLL
HIRC
HXT
SPI0
CLKDI
Vx
SC0DIV
/1 ~ 256
4
SC0
SC0
2
PCLKx
2
APBCL
Kx
Analog Module
One per UART module
CLKDI
Vx
UART0DIV
/1 ~ 16
ACMP0~1
OPA0~2
UART0~2
UART0
3
3
APBCLK
x
LXT
APBCL
Kx
One per TMR module
APBCLK
x
TMR0~3
TMR0
DAC0
4
CLKDI
APBCLK
x
LIRC
Vx
APBCL
Kx
EADCDI
EADC0
V
PWM0~1
PWM0
/1 ~ 256
APBCLK
x
One per module
4
BPWM0~1
BPWM0
APBCL
Kx
One per module
3
5
USCI0~2
I2C0~1
APBCL
Kx
2
CLKDI
Vx
PLL
HIRC
HXT
PCLKx
LIRC
LXT
PSIODIV
/1 ~ 256
NOTE:
1. PCLK0 for OPA0~2,
2. PCLK1 for DAC0, ACMP0~1,EADC0
PSIO
APBCL
Kx
NOTE:
1. PCLK0 for QSPI0, SC0, BPWM0, PWM0, USCI0, USCI2, I2C0, UART0, UART2,
TMR0~1
2. PCLK1 for SPI_I2S0, PWM1, BPWM1, USCI1, I2C1, TMR2~3, UART1, PSIO
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2
Clock Generator
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~32 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT) - PLL source can be selected
from external 4~32 MHz external high speed crystal (HXT), 48 MHz internal high speed
oscillator (HIRC/4) or 4 MHz internal medium speed oscillator (MIRC)
48 MHz internal high speed RC oscillator (HIRC)
38.4 kHz internal low speed RC oscillator (LIRC)
4 MHz internal medium speed oscillator (MIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
LXT
(LXT)
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~32
PLLSRC (CLK_PLLCTL[20:19])
MHz Crystal
(HXT)
XT1_OUT
00
01
HIRCEN (CLK_PWRCTL[2])
PLL FOUT
PLL
/4
Internal 48 MHz
Oscillator
11
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 38.4
kHz Oscillator
(LIRC)
MIRCEN (CLK_PWRCTL[19])
Internal 4 MHz
Oscillator
(MIRC)
MIRC
Figure 6.3-2 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 6 clock sources, which are generated from clock generator block. The clock
source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown
in Figure 6.3-3
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
MIRC
101
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the MIRC clock is enabled automatically.
When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to MIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5]) is
set to 1. User can try to recover HXT by disable HXT and enable HXT again to check if the clock
stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to oscillate after
re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to MIRC procedure is shown in Figure 6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
MIRC
Figure 6.3-4 HXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M23 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The clock
source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block
diagram is shown in Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Figure 6.3-5 SysTick Clock Control Block Diagram
Peripherals Clock
6.3.4
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.8.
6.3.5
Power-down Mode Clock
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When entering Power-down mode, system clocks, some clock sources and some peripheral clocks are
disabled. Some clock sources and peripherals clock are still active in Power-down mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 38.4 kHz internal low speed RC oscillator (LIRC) clock
– 32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock, except for HCLK, PCLK0 and PCLK1(When the modules adopt LXT or
LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by 16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the
frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider
output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to
CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low
state and stays in low state.
CLKOEN
Enable
(CLK_CLKOCTL[4])
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
SOF
DIV1EN
(CLK_CLKOCTL[5])
111
110
101
100
011
010
001
000
1/2
1/22
1/23
…...
1/215 1/216
CLK1HZEN
(CLK_CLKOCTL[6])
PLL
MIRC
LIRC
HIRC
HCLK
LXT
0000
0001
:
16 to 1
MUX
0
1
:
0
1
1110
CLKO
1111
HXT
RTCSEL(RTC_LXTCTL[7])
CLKOSEL (CLK_CLKSEL1[6:4])
LIRC
LXT
0
1
1 Hz clock from LXT
/32768
Figure 6.3-6 Clock Output Block Diagram
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6.3.7
USB Clock Source
The clock source of USB 1.0 is generated from 48Mhz HIRC or programmable PLL output. The
generated clocks are shown in Figure 6.3-7.
USBPLLDIV is the clock divider output frequency, the output formula is
(PLLFOUT frequency) / (USBDIV + 1).
HIRC48M
0
1
USB1.1 Device
Controller
PLLFOUT
USBPLLDIV
/(USBDIV + 1)
USBDSEL
Figure 6.3-7 USB Clock Source
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6.4 Flash Memeory Controller (FMC)
6.4.1 Overview
The FMC is equipped with 32/64/128/256 Kbytes on-chip embedded Flash for application. A User
Configuration block provides for system initiation. A 4 Kbytes loader ROM (LDROM) is used for In-
System-Programming (ISP) function. XOM (Execution Only Memory) setting block to conceal user
program in XOM region. A 512 bytes cache with zero wait cycle is used to improve Flash access
performance. This chip also supports In-Application-Programming (IAP) function. User switches the
code executing without chip reset after the embedded Flash is updated.
6.4.2
Features
Supports 32/64/128/256 Kbytes application ROM (APROM)
Supports 4 Kbytes loader ROM (LDROM)
Supports 1 XOM (Execution Only Memory) region to conceal user program in APROM
Supports 12 bytes User Configuration block to control system initiation.
Supports 512 bytes page erase for all embedded Flash
Supports 32-bit and multi-word Flash programming function
Supports CRC32 checksum calculation function
Supports Flash all one verification function
Supports embedded SRAM remap to system vector memory
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded Flash memory
Supports cache memory to improve Flash access performance and reduce power
consumption
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
This chip has up to 85 General Purpose I/O pins to be shared with other function pins depending on
the chip configuration. These 85 pins are arranged in 6 ports named as PA, PB, PC, PD, PE, and PF.
PA, PB and PE has 16 pins on port. PC has 14 pins on port, PD has 15 pins on port. PF has 8 pins on
port. Each of the 85 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output,
Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins are
depending on CIOINI (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up resistor which
is about 50 k.
6.5.2
Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
– CIOINI = 1, all GPIO pins in input mode after chip reset
Support independent pull-up and pull-down control
Enabling the pin interrupt function will also enable the wake-up function
Improve access efficiency by using single cycle I/O bus
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 8 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.6.2
Features
Supports up to 8 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Request source can be from software,PSIO , SPI/I2S, UART, USCI, EADC,DAC,PWM
capture event and TIMER
Supports Scatter-gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function on channel 0 and channel1
Supports stride function from channel 0 to channel 5
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6.7 Timer Controller (TMR)
6.7.1 Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a
timer control for applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
The timer controller also provides four PWM generators. Each PWM generator supports one PWM
output and two selectable PWM output channels (TMx or TMx_EXT). The output state of PWM output
pin can be control by polarity control, output enable control and output channel select.
6.7.2
Features
6.7.2.1 Timer Function Features
Four sets of 32-bit timers, each timer having one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin (TMx_EXT) event for interval measurement
Supports external capture pin (TMx_EXT) event to reset 24-bit up counter
Supports internal clock (HIRC, LIRC, MIRC) and external clock (HXT, LXT) for capture
event
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
BPWM, PWM, EADC, DAC and PDMA function
Supports internal capture triggered while internal ACMP output signal transition
Supports Inter-Timer trigger mode
Supports event counting source from internal USB SOF signal
6.7.2.2 PWM Function Features
Supports PWM generator with two selectable output channels
Supports 16-bit PWM counter
– Up count operation type
– One-shot or auto-reload counter operation mode
Supports 8-bit prescale from 1 to 256
Supports 16-bit compare register and period register and double buffer for period register
and compare register
Supports tri-state enable and polarity control for each PWM selectable output channels
Supports interrupt on the following events:
– PWM period point, up-count compared point events
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Supports wake-up when interrupt occurs when clock source is LXT or LIRC
PWM can generator output in power down mode
Supports trigger EADC, PDMA, and DAC on the following events:
– PWM period point and up-count compared point events
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake up system from Idle/Power-down mode.
6.8.2
Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 417us ~ 27. 3 s if
WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0]
in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as 38.4
kHz LIRC or LXT.
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6.9 Window Watchdog Timer (WWDT)
6.9.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software running to uncontrollable status by any unpredictable condition.
6.9.2
Features
6-bit down counter value (CNTDAT, WWDT_CNT[5:0]) and 6-bit compare value
(CMPDAT, WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value (PSCSEL, WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
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6.10 Real Time Clock (RTC)
6.10.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers
programmable time tick and alarm match interrupts. The data format of time and calendar messages
are expressed in BCD format. A digital frequency compensation feature is available to compensate
external crystal oscillator frequency accuracy.
6.10.2 Features
Supports external power pin VBAT.
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check.
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM.
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK.
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register.
Supports Leap Year indication in RTC_LEAPYEAR register.
Supports Day of the Week counter in RTC_WEEKDAY register.
Frequency of RTC clock source compensate by RTC_FREQADJ register.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt.
Supports 1 Hz clock output.
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated.
Supports Daylight Saving Time software control in RTC_DSTCTL.
Supports one tamper pin.
Supports 20 bytes spare registers and tamper-pin detection to clear the content of these
spare registers.
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6.11 Basic PWM Generator and Capture Timer (BPWM)
6.11.1 Overview
The chip provides two BPWM generators. Each BPWM supports 6 channels of BPWM output or input
capture. There is a 12-bit prescaler to support flexible clock to the 16-bit BPWM counter with 16-bit
comparator. The BPWM counter supports up, down and up-down counter types, all 6 channels share
one counter. BPWM uses the comparator compared with counter to generate events. These events
are used to generate BPWM pulse, interrupt and trigger signal for EADC to start conversion. For
BPWM output control unit, it supports polarity output, independent pin mask and tri-state output
enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both transition is
happened.
6.11.2 Features
6.11.2.1 BPWM Function Features
Supports maximum clock frequency up to maximum PLL frequency.
Supports up to two BPWM modules; each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit prescalar from 1 to 4096
Supports 16-bit resolution BPWM counter; each module provides 1 BPWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt in the following events:
– BPWM counter matches 0, period value or compared value
Supports trigger EADC in the following events:
– BPWM counter matches 0, period value or compared value
6.11.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.12 PWM Generator and Capture Timer (PWM)
6.12.1 Overview
The chip provides two PWM generators － PWM0 and PWM1. Each PWM supports 6 channels of
PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM
counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.
PWM uses comparator compared with counter to generate events. These events use to generate
PWM pulse, interrupt and trigger signal for ADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. In Complementary mode, there are two
comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control
unit, it supports polarity output, independent pin mask and brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both transition is
happened. Capture function also support PDMA to transfer captured data to memory.
6.12.2 Features
6.12.2.1 PWM function features
Supports maximum clock frequency up to maximum PLL frequency
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
– Dead-time insertion with 12-bit resolution
– Two compared values during one period
Supports 12-bit prescaler from 1 to 4096
Supports 16-bit resolution PWM counter
– Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
– Brake source from pin and system safety events (clock failed, Brown-out detection and
CPU lockup)
– Noise filter for brake source from pin
– Edge detect brake source to control brake state until brake interrupt cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM counter matches 0, period value or compared value
– Brake condition happened
Supports trigger ADC on the following events:
– PWM counter matches 0, period value or compared value
6.12.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
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Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.13 UART Interface Controller (UART)
6.13.1 Overview
The chip provides three channels of Universal Asynchronous Receiver/Transmitters (UART). The
UART controller performs Normal Speed UART and supports flow control function. The UART
controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-
to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten
types of interrupts. The UART controller also supports IrDA SIR, LIN, RS-485 and Single-wire function
modes and auto-baud rate measuring function.
6.13.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next START bit
by setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT.
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable PARITY bit, even, odd, no parity or stick PARITY bit generation and
detection
– Programmable STOP bit, 1, 1.5, or 2 STOP bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART0 with LIN function)
– Supports LIN master/slave mode
– Supports programmable break generation function for transmitter
– Supports break detection function for receiver
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
Support Single-wire function mode.
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UART Feature
UART0
UART1/UART2
SC_UART
USCI-UART
TX: 1byte
RX: 2byte
FIFO
16 Bytes
16 Bytes
4 Bytes
Auto Flow Control (CTS/RTS)
IrDA
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
√
-
LIN
-
RS-485 Function Mode
nCTS Wake-up
Incoming Data Wake-up
√
√
√
√
√
√
-
Received
Data
FIFO
reached
√
√
√
√
-
-
threshold Wake-up
RS-485 Address Match (AAD mode)
Wake-up
-
Auto-Baud Rate Measurement
STOP bit Length
Word Length
√
√
-
√
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
1, 2 bit
5, 6, 7, 8 bits
5, 6, 7, 8 bits
5, 6, 7, 8 bits
6~13 bits
Even / Odd Parity
Stick Bit
√
√
√
√
√
√
-
-
Note: √= Supported
Table 6.13-1 UART Feature List
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6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.14.2 Features
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
One ISO 7816-3 port
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
– Full duplex, asynchronous communications
– Separates receiving / transmitting 4 bytes entry FIFO for data payloads
– Supports programmable baud rate generator
– Supports programmable receiver buffer trigger level
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting EGT (SCn_EGT[7:0])
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1- or 2- stop bit generation
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6.15 Serial Peripheral Interface (SPI)
6.15.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains one of SPI controller performing a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each
SPI controller can be configured as a master or a slave device and supports the PDMA function to
access the data buffer. Each SPI controller also supports I2S mode to connect external audio CODEC.
6.15.2 Features
SPI Mode
– Support one SPI controller
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports Byte or Word Suspend mode
– Supports PDMA transfer
– Supports one data channel half-duplex transfer
– Supports receive-only mode
I2S Mode
– Supports Master or Slave
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Each provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Supports two PDMA requests, one for transmitting and the other for receiving
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6.16 Quad Serial Peripheral Interface (QSPI)
6.16.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access
the data buffer.
6.16.2 Features
Supports one QSPI controller
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports receive-only mode
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6.17 I2C Serial Interface Controller (I2C)
6.17.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are two sets of I2C controllers that support Power-down wake-up function.
6.17.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflow
Programmable clocks allow for versatile rate control
Supports 7-bit addressing and 10-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports setup/hold time programmable
Supports Bus Management (SM/PM compatible) function.
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6.18 USCI - Universal Serial Control Interface Controller (USCI)
6.18.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.18.2 Features
The controller can be individually configured to match the application needs. The following protocols
are supported:
UART
SPI
I2C
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6.19 USCI – UART Mode
6.19.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of asynchronous
data frames. It performs a serial-to-parallel conversion on data received from the peripheral, and a
parallel-to-serial conversion on data transmitted from the controller. The receiver and transmitter being
independent, frames can start at different points in time for transmission and reception.
The UART controller also provides auto flow control. There are three conditions to wake-up the
system.
6.19.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-bit Data Transfer (Support 9-bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.20 USCI - SPI Mode
6.20.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows full
duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as master or Slave mode by setting the SLAVE (USPI_PROTCTL[0]) to
communicate with the off-chip SPI Slave or master device. The application block diagrams in master
and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0, 1, 2
Figure 6.20-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0, 1, 2
Figure 6.20-2 SPI Slave Mode Application Block Diagram
6.20.2 Features
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports PDMA transfer
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Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.21 USCI - I2C Mode
6.21.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA
lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL clock pulse
for each data bit with the MSB being transmitted first, and an acknowledge bit follows each transferred
byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL. A transition on the
SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to Figure
6.21-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.21-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100B. When enable this port, the USCI interfaces to the I2C bus via
two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function to I2C in
advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode.
6.21.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.22 Programmable Serial IO (PSIO)
6.22.1 Overview
Programmable Serial I/O (PSIO) provides a simple way to implement simple serial signal proccesing,
e.g. UART and IR. The PSIO can control when the pin will output high or low and how long the pin
need to output high or low. It also provides the easy way to sample the pin state.
6.22.2 Features
Supports up to 8 PSIO pins, from PSIO pin0 to PSIO pin7
Supports 6 clock sources, they are HXT, LXT, HIRC, LIRC, PLL, PCLK1
Supports one clock divider, which can be divided from 1 to 255
Supports slot controller for timing sequence control
– Supports 4 slot controllers, 8 slots in each slot controller
– Supports counting from 1 PSIO clock to 15 PSIO clocks in each slot
– Supports 3 slot repeat modes:
Normal repeat mode
Normal repeat mode with infinity loops
Whole repeat mode
– Supports 4 slot trigger conditions:
Triggered by software
Triggered by falling edge
Triggered by rising edge
Triggered by rising edge or falling edge
Supports PSIO PIN for pin state control
– Supports 8 check points to connect with slots in each pin
– Supports 8 check point actions in each check point.
– Supports 7 kinds of check point action to setting
Output high
Output low
Output data
Output toggle
Input data
Input status
Input status update
– Supports 4 I/O modes, input, output, open-drain, and quasi
– Supports switch I/O mode in different check points
Supports 4 kinds of Interrupt trigger conditions
– Two sets of configurable slot interrupt controllers
– Mismatch interrupt when PSIO is enabled with PDMA
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– Transfer Error interrupt
– Slot controller counting done interrupt
Supports PDMA function
Clock Controller
PSIOCKEN
PSIO Controller
HIRC
LIRC
PLL
111
100
011
010
001
000
PSIO_CLK
1/(PSIODIV+1)
PCLK1
LXT
HXT
PSIOSEL
PSIODIV
CLKSEL2[30:28] CLKDIV1[31:24]
PSIOSEL
PSIOCKEN
CLK_APBCLK1[31]
Figure 6.22-1 PSIO Clock Control Diagram (8-bit Pre-scale Counter in Clock Controller)
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6.23 External Bus Interface (EBI)
6.23.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.23.2 Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
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6.24 USB 1.1 Device Controller (USBD)
6.24.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is compliant
with USB 2.0 full-speed device specification and supports control/bulk/interrupt/isochronous transfer
types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes from
the USB PHY transceiver. For the APB bus, the CPU can program control registers through it. There
are 1 Kbytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is necessary to
write data to SRAM or read data from SRAM through the APB interface or SIE. User needs to set the
effective starting address of SRAM for each endpoint buffer through buffer segmentation register
(USBD_BUFSEGx).
There are 12 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data sequential
synchronization, endpoint states, current start address, transaction status, and data buffer status for
each endpoint.
There are five different interrupt events in this controller. They are the no-event-wake-up, device plug-
in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend and
resume, etc. Any event will cause an interrupt, and users just need to check the related event flags in
interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt occurring, and
then check the related USB Endpoint Status Register (USBD_EPSTS0 and USBD_EPSTS1) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB controller
will force the output of USB_D+ and USB_D- to level low and its function is disabled. After disable the
SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus Specification
Revision 1.1.
6.24.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (SOF, NEVWK, VBUSDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 1 Kbytes buffer size
Provides remote wake-up capability
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6.25 CRC Controller (CRC)
6.25.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.25.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
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6.26 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.26.1 Overview
The chip contains one 12-bit successive approximation analog-to-digital converter (SAR ADC
converter) with 16 external input channels and 3 internal channels. The ADC converter can be started
by software trigger, PWM0/1 triggers, BPWM0/1 triggers, Timer0~3 overflow pulse triggers, ADINT0,
ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin (EADC0_ST) input signal.
6.26.2 Features
Analog input voltage range: 0~VREF (Max to AVDD)
Reference voltage from VREF pin or AVDD
12-bit resolution and 10-bit accuracy is guaranteed
Up to 16 single-end analog external input channels
3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP), and
Battery power (VBAT/4)
Four EADC interrupts (ADINT0~3) with individual interrupt vector addresses
Maximum EADC clock frequency is 16 MHz
Up to 880 kSPS conversion rate
Configurable EADC internal sampling time.
Up to 19 sample modules:
– Each of sample is configurable for EADC converter channel EADC_CH0~15 and
trigger source
– Sample module 16~18 is fixed for EADC channel 16, 17, 18 input sources as band-
gap voltage, temperature sensor, and battery power (VBAT/4)
– Configurable sampling time for each sample module
– Support left-adjusted result
– 12-bit resolution for conversion result and 16-bit resolution for accumulated conversion
result
– Conversion results are held in 19 data registers with valid and overrun indicators
– Averaging (2n times, n=0~8) to support up to 12-bit result and over-sampling, or called
Accumulation, (2n times, n=0~8) to support up to 16-bit result
An ADC conversion can be started by:
– Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18)
– External pin EADC0_ST
– Timer0~3 overflow pulse triggers
– ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
– PWM0/1 triggers
– BPWM0/1 triggers
Supports configurable PDMA transfer
Auto turn on/off EADC power at power off or operation mode with wait state(10us stable
time)
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Supports digital comparator to monitor conversion result and user can select whether to
generate an interrupt when conversion result matches the compare register setting
Internal reference voltage source: 1.536V, 2.048V, 2.560V, 3.072V, 4.096V and VREF pin
Supports offset cancellation
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6.27 Digital to Analog Converter (DAC)
6.27.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be configured to 12-or 8-
bit output mode and can be used in conjunction with the PDMA controller. The DAC integrates a
voltage output buffer that can be used to reduce output impendence and drive external loads directly
without having to add an external operational amplifier.
6.27.2 Features
Analog output voltage range: 0~AVDD.
Supports 12-or 8-bit output mode.
Rail to rail settle time 6us.
Supports up to one 12-bit 1 MSPS voltage type DAC.
Reference voltage from internal reference voltage (INT_VREF), VREF pin.
DAC maximum conversion updating rate 1 MSPS.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger, including Timer0~3 and external trigger pin to
start DAC conversion.
Supports PDMA mode.
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6.28 Analog Comparator Controller (ACMP)
6.28.1 Overview
The chip provides two comparators. The comparator output is logic 1 when positive input is greater
than negative input; otherwise, the output is 0. Each comparator can be configured to generate an
interrupt when the comparator output value changes.
6.28.2 Features
Analog input voltage range: 0 ~ AVDD
Up to two rail-to-rail analog comparators
Supports hysteresis function
– Supports programmable hysteresis window: 0mV, 10mV, 20mV and 30mV
Supports wake-up function
Supports programmable propagaion speed and low power consumption
Selectable input sources of positive input and negative input
ACMP0 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 4 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
ACMP1 supports:
– 4 multiplexed I/O pins at positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 4 negative sources:
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC0 output (DAC0_OUT)
Shares one ACMP interrupt vector for all comparators
Interrupts generated when compare results change (Interrupt event condition is
programmable)
Supports triggers for break events and cycle-by-cycle control for PWM
Supports window compare mode and window latch mode
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6.29 OP Amplifier (OPA)
6.29.1 Overview
This chip is equipped with one operational amplifier. The OP amplifier outputs is connected to ADC
channel for measurement requirement. The OP amplifier circuit can also be used in the application of
Programmable Gain Amplifier (PGA).
6.29.2 Features
Analog input voltage range: 0~AVDD.
Supports up to 1 operational amplifier
Supports to use schmitt trigger buffer output for simple comparator function.
Supports schmitt trigger buffer output interrupts.
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6.30 Peripherals Interconnection
6.30.1 Overview
Some peripherals have interconnections which allow autonomous communication or synchronous
action between peripherals without needing to involve the CPU. Peripherals interact without CPU
saves CPU resources, reduces power consumption, operates with no software latency and fast
responds.
6.30.2 Peripherals Interconnect Matrix table
Destination
Source
HIRC
TRIM
ACMP BPWM
DAC
EADC
PWM
Timer
UART
ACMP
BandGap
BOD
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
17
-
-
-
-
-
-
-
-
-
14
15
14
-
-
BPWM
Clock Fail
CRV
-
3
-
11
-
-
-
-
1
-
-
-
CPU
Lockup
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
-
-
-
-
-
-
-
-
-
-
DAC
1
-
5
-
8, 9
-
Internal
Module
-
-
-
LIRC
-
-
External
Pin
8, 9,
10
1, 2
5, 6
14
LIRC
LXT
-
-
-
-
-
-
-
-
-
-
-
-
13
-
-
17
-
-
-
-
14, 15
16
PWM
Timer
UART
3
4
-
-
11
12
-
-
19
-
7
-
-
-
-
-
-
19
USB 1.1
Device
-
-
-
13
-
18
-
Table 6.30-1 Peripherals Interconnect Matrix table
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7 APPLICATION CIRCUIT
7.1 Power Supply Scheme
as close to AVDD as possible
L=30Z
EXT_PWR
AVDD
AVSS
1uF+0.1uF+0.01uF
L=30Z
10uF+0.1uF
as close to the
EXT_PWR as possible
VREF
2.2uF+1uF+470pF
L=30Z
as close to VREF as possible
LDO_CAP
1uF
VSS
as close to LDO as possible
VDD/VDDIO
0.1uF*N
VSS
VBAT
L=30Z
0.1uF
VSS
EXT_VSS
as close to VDD/VDDIO/VBAT as possible
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7.2 Peripheral Application Scheme
DVCC
USB Full Speed Slot
100K
100K
10R
27R
27R
USB_VBUS
USB_D-
VDD
ICE_DAT
USB_D+
SWD
Interface
ICE_CLK
nRESET
USB_VCC33_CAP
VSS
1uF
20pF
XT1_IN
4~24 MHz
crystal
20pF
20pF
DVCC
DVCC
XT1_OUT
4.7
K
4.7
K
Crystal
X32_IN
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
I2C Device
32.768 kHz
crystal
20pF
X32_OUT
DVCC
M251/M252 Series
Reset
Circuit
PC COM Port
RS 232 Transceiver
10K
nRST
UART_RXD
UART_TXD
ROUT RIN
UART
TIN
TOUT
10 uF
DVCC
LDO_CAP
LDO
1 uF
SPI_SS
SPI_CLK
SPI Device
SPI_MISO
SPI_MOSI
64K x 16-bit
SRAM
LATCH
Q
D
Addr[15:0]
En
ALE
Audio codec
nCE
nOE
nWE
nLB
nCS
nRD
SPI_I2SMCLK
SPI_CLK(I2S_BCLK)
SPI_SS (I2S_LRCLK)
SPI_MOSI (I2S_DO)
SPI_MISO (I2S_DI)
EBI
Line In
nWR
nWRL
nWRH
Line Out
nUB
Data[15:0]
AD[15:0]
Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
Note 2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
Note 3: It is recommended to use 10Ω series resistor on USB_VBUS pin.
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Stresses above the absolute maximum ratings may cause permanent damage to the device. The
limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.1.1
Voltage Characteristics
Symbol
Description
Min
Max
6.5
6.5
6.5
50
Unit
V
[*1]
VDD-VSS
DC power supply
VDDIO Power Supply
VBAT Power Supply
-0.3
[*1]
VDDIO-VSS
-0.3
V
[*1]
VBAT-VSS
-0.3
V
ΔVDD
Variations between different VDD power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on any other pin[*2]
-
mV
mV
mV
mV
V
|VDD –AVDD
|
-
50
ΔVSS
-
50
|VSS - AVSS
|
-
50
VIN
VSS-0.3
6.5
Note:
1. All main power (VDD, VDDIO, VBAT, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
2. Refer to Table 8.1-2 for the values of the maximum allowed injected current.
Table 8.1-1 Voltage Characteristics
8.1.2
Current Characteristics
Symbol
Description
Min
Max
200
Unit
[*1]
ΣIDD
Maximum current into VDD
-
-
-
-
-
-
-
-
-
IDDIO / IBAT
Maximum current into VDDIO / IBAT
100 / 100
100
ΣISS
Maximum current out of VSS
Maximum current sunk by a I/O Pin
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
Maximum injected current by a I/O Pin
Maximum injected current by total I/O Pins
20
20
mA
IIO
100
100
[*3]
IINJ(PIN)
±5
[*3]
ΣIINJ(PIN)
±25
Note:
1. Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
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Table 8.1-2 Current Characteristics
8.1.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (℃)
θJA = thermal resistance junction-ambient (℃/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
-40
Typ
Max
105
125
150
Unit
T
A
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
T
J
-40
℃
T
-65
ST
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
-
-
-
-
-
-
38
30
-
-
-
-
-
-
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
℃/Watt
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
Thermal resistance junction-ambient
33-pin QFN(5x5 mm)
39.6
60
[*1]
θJA
Thermal resistance junction-ambient
48-pin LQFP(7x7 mm)
Thermal resistance junction-ambient
64-pin LQFP(7x7 mm)
58
Thermal resistance junction-ambient
128-pin LQFP(14x14 mm)
38.5
Note:
1. Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.1-3 Thermal Characteristics
July 2, 2020
Page 203 of 266
Rev 1.01
M251/M252
8.1.4
EMC Characteristics
8.1.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.1.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.1.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of
narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-6000
-1000
-150
Typ
Max
+6000
+1000
+150
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
-4.4
Fast transient voltage burst
+4.4
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-4 EMC Characteristics for M251xC/M251xD/M252xC/M252xD
July 2, 2020
Page 204 of 266
Rev 1.01
M251/M252
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-6000
-500
-150
-4.4
Typ
Max
+6000
+500
+150
+4.4
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
Fast transient voltage burst
Note:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human Body
Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.1-5 EMC Characteristics for M251xE/M251xG/M252xE/M252xG
July 2, 2020
Page 205 of 266
Rev 1.01
M251/M252
8.1.5
Package Moisture Sensitivity (MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge
20-pin TSSOP(4.4x6.5 mm)[*1]
28-pin TSSOP(4.4x9.7 mm) [*1]
33-pin QFN(5x5 mm) [*1]
MSL
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
48-pin LQFP(7x7 mm) [*1]
64-pin LQFP(7x7 mm) [*1]
128-pin LQFP(14x14 mm) [*1]
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.1-6 Package Moisture Sensitivity(MSL)
July 2, 2020
Page 206 of 266
Rev 1.01
M251/M252
8.1.6
Soldering Profile
Figure 8.1-1 Soldering profile from J-STD-020C
Porfile Feature
Pb Free Package
3℃/sec. max
Average ramp-up rate (217℃ to peak)
Preheat temperature 150℃ ~200℃
Temperature maintained above 217℃
Time with 5℃ of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260℃
Ramp-down rate
6℃/sec ax.
8 min. max
Time 25℃ to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.1-7 Soldering Profile
July 2, 2020
Page 207 of 266
Rev 1.01
M251/M252
8.2 General Operating Conditions
(VDD-VSS = 1.75 ~ 5.5V, TA = 25C, HCLK = 48 MHz unless otherwise specified.)
Symbol
TA
Parameter
Temperature
Min
-40
-
Typ
Max
105
48
Unit
℃
Test Conditions
-
-
fHCLK
Internal AHB clock frequency
MHz
VDD
VDDIO
VBAT
Operation voltage
1.75
1.65
1.75
-
-
5.5
5.5
5.5
VDDIO Operation voltage
VBAT Operation voltage
Analog operation voltage
Analog reference voltage
LDO output voltage
-
V
[*1]
AVDD
VDD
-
VREF
VLDO
VBG
1.75
-
AVDD
-
1.5
815
1
Band-gap voltage
795
840
mV
µF
Ω
[*2]
CLDO
LDO output capacitor on each pin
ESR of CLDO output capacitor
[*3]
RESR
-
-
-
0.5
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
[*3]
IRUSH
60
150
mA
µC
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
VDD = 1.8 V, TA = 105 °C,
IRUSH = 60 mA for 15 µs
[*3]
ERUSH
-
0.9
-
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3 V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.To ensure stability, an external 1 μF output capacitor, CLDO must be connected between the LDO_CAP pin and the
closest GND pin of the device. Solid tantalum and multilayer ceramic capacitors are suitable as output capacitor.
Additional 100 nF bypass capacitor between LDO_CAP pin and the closest GND pin of the device helps decrease
output noise and improves the load transient response.
3.Guaranteed by design, not tested in production
Table 8.2-1 General Operating Conditions
July 2, 2020
Page 208 of 266
Rev 1.01
M251/M252
8.3 DC Electrical Characteristics
8.3.1 Supply Current Characteristics for M251xC/M251xD/M252xC/M252xD
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1.75 ~ 5.5 V unless otherwise
specified.
VDD = AVDD = VDDIO
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program run CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
5.4
4.1
6.05
4.6
6.25
4.8
6.45
5.1
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals disable.
3.2
3.65
2.3
3.85
2.5
4.1
HCLK is set as HIRC, PLL or
HXT clock.
2.0
2.8
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals disable.
0.74
0.55
0.45
0.95
0.75
0.6
1.15
0.9
1.35
1.1
2 MHz
HCLK is set as MIRC clock.
1 MHz
0.80
1.0
Normal run mode with PL3
(PLSEL = 11), executed from
Flash, all peripherals disable.
38.4 kHz
0.01
0.01
0.02
0.02
0.06
0.06
0.16
0.16
HCLK is set as LIRC or LXT
clock..
32.768 kHz
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
15
10
16.6
11.5
9.0
16.8
11.8
9.3
17
12
IDD_RUN
mA
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals enable.
8.0
4.5
1.4
0.95
0.65
9.5
5.5
2.1
1.6
1.3
HCLK is set as HIRC, PLL or
HXT clock.
5.05
1.65
1.15
0.85
5.3
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals enable.
1.85
1.35
1.1
2 MHz
HCLK is set as MIRC clock.
1 MHz
Normal run mode with PL3
(PLSEL = 11), executed from
Flash, all peripherals enable
38.4 kHz
0.02
0.03
0.06
0.17
HCLK is set as LIRC or LXT
clock..
32.768 kHz
0.02
0.03
0.06
0.17
July 2, 2020
Page 209 of 266
Rev 1.01
M251/M252
Note:
1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-1 Current Consumption in Normal Run Mode
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
2.25
2.6
2.8
3.0
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
32 MHz
24 MHz
12 MHz
4 MHz
2 MHz
1 MHz
2.05
1.6
2.4
1.9
2.6
2.1
2.8
2.3
HCLK is set as HIRC, PLL or
HXT clock.
1.2
1.45
0.62
0.57
0.53
1.65
0.8
1.85
1.0
0.47
0.42
0.39
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
0.77
0.73
0.97
0.93
HCLK is set as MIRC clock.
Idle mode with PL3 (PLSEL =
11), all peripherals disable
38.4 kHz
0.01
0.01
0.02
0.02
0.06
0.06
0.16
0.16
HCLK is set as LIRC or LXT
clock.
32.768 kHz
IDD_IDLE
mA
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
12
8.1
13.3
9.1
13.4
9.3
13.7
9.5
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
HCLK is set as HIRC, PLL or
HXT clock.
6.6
7.4
7.6
7.8
3.9
4.4
4.6
4.8
1.25
0.8
1.5
1.7
1.9
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
2 MHz
1.0
1.2
1.4
HCLK is set as MIRC clock.
1 MHz
0.58
0.74
0.95
1.15
Idle mode with PL3 (PLSEL =
11), all peripherals enable
38.4 kHz
0.02
0.02
0.03
0.03
0.06
0.06
0.17
0.17
HCLK is set as LIRC or LXT
clock.
32.768 kHz
Note:
1. When analog peripheral blocks such as USB, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-2 Current consumption in Idle Mode
July 2, 2020
Page 210 of 266
Rev 1.01
M251/M252
Typ[*2]
Max[*3][*4]
LXT[*1] LIRC
32.768 38.4
Symbol
Test Conditions
Unit
T
=
T
=
T
=
T =
A
A
A
A
kHz
kHz
25 °C 25 °C 85 °C 105 °C
Deep Power-down mode, all peripherals disable
-
-
1.45
3.5
15.5
76
IDD_DPD
µA
Deep Power-down mode, RTC enable and run
Power-down mode, all peripherals disable
Power-down mode, RTC enable and run
Power-down mode, WDT/Timer enable and run
V
-
-
-
2.0
1.7
3.95
3.7
16
23.5
25
78
128
129
130
131
292
293
295
296
V
-
-
2.5
4.55
5.65
6.2
IDD_PD
µA
V
V
-
3.65
4.3
26
Power-down mode, WDT/Timer/UART/RTC enable and
run, WDT use LIRC, UART/Timer/RTC use LXT
V
-
26.5
171
173
174
175
Fast wake up Power-down mode, all peripherals disable
Fast wake up Power-down mode, RTC enable and run
100
101
102
103
140
141
142
143
V
-
-
IDD_FWPD
µA
Fast wake up Power-down mode, WDT/Timer enable and
run
V
V
Fast wake up Power-down mode, WDT/Timer/UART/RTC
enable and run, WDT use LIRC, UART/Timer/RTC use
LXT
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for L1 gain level
2. VDD = AVDD = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as USB, ADC and ACMP are ON, an additional power consumption should be
considered.
Table 8.3-3 Chip Current Consumption in Power-down Mode
July 2, 2020
Page 211 of 266
Rev 1.01
M251/M252
8.3.2
Supply Current Characteristics for M251xE/M251xG/M252xE/M252xG
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 1.75 ~ 5.5 V unless otherwise
specified.
VDD = AVDD = VDDIO = VBAT
When the peripherals are enabled HCLK is the system clock, fPCLK0, 1 = fHCLK
Program runs CoreMark® code in Flash.
.
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
6.2
4.55
3.6
6.95
5.15
4.05
2.55
0.95
0.75
0.6
7.15
5.35
4.25
2.75
1.15
0.9
7.35
5.65
4.55
3.0
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals disable.
HCLK is set as HIRC, PLL or
HXT clock.
2.25
0.74
0.55
0.45
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals disable.
1.35
1.1
2 MHz
HCLK is set as MIRC clock.
1 MHz
0.80
1.0
Normal run mode with PL3
(PLSEL = 11), executed from
Flash, all peripherals disable.
38.4 kHz
0.01
0.01
0.02
0.02
0.06
0.06
0.2
0.2
HCLK is set as LIRC or LXT
clock..
32.768 kHz
IDD_RUN
mA
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
17.5
11.5
9.5
19.5
13
19.8
13.3
10.8
6.3
20
13.5
11
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals enable.
10.5
6.1
HCLK is set as HIRC, PLL or
HXT clock.
5.5
6.5
2.3
1.7
1.35
Normal run mode with PL0
(PLSEL = 00), executed from
Flash, all peripherals enable.
1.6
1.85
1.25
0.95
2.05
1.45
1.15
2 MHz
1.0
HCLK is set as MIRC clock.
1 MHz
0.7
Normal run mode with PL3
(PLSEL = 11), executed from
Flash, all peripherals enable
38.4 kHz
0.02
0.02
0.03
0.03
0.07
0.07
0.22
0.22
HCLK is set as LIRC or LXT
clock..
32.768 kHz
July 2, 2020
Page 212 of 266
Rev 1.01
M251/M252
Note:
1. When analog peripheral blocks such as ADC, OPA, DAC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are ON, an
additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-4 Current consumption in Normal Run Mode
Typ [*1]
Max[*1][*2]
Symbol
Conditions
FHCLK
Unit
T
= 25 °C
T
= 25 °C
T
= 85 °C
T = 105 °C
A
A
A
A
48 MHz
2.4
2.75
2.95
3.05
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
32 MHz
24 MHz
12 MHz
4 MHz
2 MHz
1 MHz
2.25
1.7
2.6
1.9
2.8
2.1
3.0
2.3
HCLK is set as HIRC, PLL or
HXT clock.
1.25
0.48
0.42
0.39
1.5
1.7
1.9
0.62
0.57
0.53
0.8
1.0
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
0.77
0.73
0.97
0.93
HCLK is set as MIRC clock.
Idle mode with PL3 (PLSEL =
11), all peripherals disable
38.4 kHz
0.01
0.01
0.02
0.02
0.06
0.06
0.2
0.2
HCLK is set as LIRC or LXT
clock.
32.768 kHz
IDD_IDLE
mA
48 MHz
32 MHz
24 MHz
12 MHz
4 MHz
13
9.2
7.5
4.5
1.3
0.85
0.6
14.5
10.5
8.5
14.7
10.7
8.7
14.9
10.9
8.9
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
HCLK is set as HIRC, PLL or
HXT clock.
5.1
5.3
5.5
1.55
1.1
1.75
1.3
1.95
1.5
Idle mode with PL0 (PLSEL =
00), all peripherals disable.
2 MHz
HCLK is set as MIRC clock.
1 MHz
0.8
1.0
1.2
Idle mode with PL3 (PLSEL =
11), all peripherals enable
38.4 kHz
0.02
0.02
0.03
0.03
0.07
0.07
0.22
0.22
HCLK is set as LIRC or LXT
clock.
32.768 kHz
Note:
1. When analog peripheral blocks such as USB, OPA, DAC, ADC, ACMP, PLL, HIRC, MIRC, LIRC, HXT and LXT are
ON, an additional power consumption should be considered.
2. Based on characterization, not tested in production unless otherwise specified.
Table 8.3-5 Current Consumption in Idle Mode
July 2, 2020
Page 213 of 266
Rev 1.01
M251/M252
Typ[*2]
Max[*3][*4]
LXT[*1] LIRC
32.768 38.4
Symbol
Test Conditions
Unit
T
= 25 T = 25
T
=
T =
A
A
A
°C
A
kHz
kHz
°C
85 °C 105 °C
Deep Power-down mode, all peripherals disable
-
-
1.4
3.5
16.5
80
IDD_DPD
µA
Deep Power-down mode, RTC enable and run
Power-down mode, all peripherals disable
Power-down mode, RTC enable and run
Power-down mode, WDT/Timer enable and run
V
-
-
-
1.9
1.8
4.3
3.7
4.7
6
TBD
30
TBD
155
157
159
161
490
492
494
496
V
-
-
2.45
3.9
31
IDD_PD
µA
V
V
-
32.5
34
Power-down mode, WDT/Timer/UART/RTC enable and
run, WDT use LIRC, UART/Timer/RTC use LXT
V
-
4.5
6.9
260
261
262
263
Fast wake up Power-down mode, all peripherals disable
Fast wake up Power-down mode, RTC enable and run
160
161
162
163
315
316
318
320
V
-
-
IDD_FWPD
µA
Fast wake up Power-down mode, WDT/Timer enable and
run
V
V
Fast wake up Power-down mode, WDT/Timer/UART/RTC
enable and run, WDT use LIRC, UART/Timer/RTC use
LXT
V
Note:
1. Crystal used: AURUM XF66RU000032C0 with a CL of 20 pF for L3 gain level
2. VDD = AVDD = VBAT = 3.3V, LVR17 enabled, POR disabled and BOD disabled.
3. Based on characterization, not tested in production unless otherwise specified.
4. When analog peripheral blocks such as USB, OPA, DAC, ADC and ACMP are ON, an additional power consumption
should be considered.
Table 8.3-6 Chip Current Consumption in Power-down Mode
July 2, 2020
Page 214 of 266
Rev 1.01
M251/M252
8.3.3
On-Chip Peripheral Current Consumption
The typical values for TA= 25 °C and VDD = AVDD = VBAT = 3.3 V unless otherwise
specified.
All GPIO pins are set as output high of push pull mode without multi-function.
HCLK is the system clock, fHCLK = 48 MHz, fPCLK0, 1 = fHCLK
.
The result value is calculated by measuring the difference of current consumption
between all peripherals clocked off and only one peripheral clocked on.
The peripheral clock selection keeps reset default setting.
[*1]
Peripheral
EADC[*2]
ACMP01[*3]
PWM0
IDD
0.55
Unit
0.067
0.72
PWM1
0.75
BPWM0
BPWM1
WDT/WWDT
QSPI
0.36
0.39
0.05
0.44
SPI/I2S
UART0
UART1
UART2
I2C0
0.64
0.40
0.34
0.33
0.058
0.087
0.28
mA
I2C1
USCI0
USCI1
0.26
USCI2
0.27
SC0
0.22
0.75 (4 channels)
1.4 (8 channels)
0.12
PSIO0
EBI
TMR0
TMR1
TMR2
TMR3
RTC
0.28
0.30
0.29
0.26
0.046
July 2, 2020
Page 215 of 266
Rev 1.01
M251/M252
USB FS Device[*4]
CRC
1.03
0.045
0.57
PDMA
FMC
0.43
Note:
1. Guaranteed by characterization results, not tested in production.
2. When the ADC is turned on, add an additional power consumption per ADC for the analog part.
3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part.
4. When the USB is turned on, add an additional power consumption per USB for the analog part.
Table 8.3-7 Peripheral Current Consumption
8.3.4
Wakeup Time from Low-Power Modes
The wakeup times given in Table 8.2-1 is measured on a wakeup phase with a 48 MHz HIRC
oscillator.
Symbol
Parameter
Typ
5
Max
6
Unit
tWU_IDLE
Wakeup from IDLE mode
cycles
[*1][*2]
tWU_DPD
Wakeup from deep Power-down mode
Wakeup from normal Power-down mode
Wakeup from fast wake up Power-down mode
190
19
250
30
[*1][*2]
[*1][*2]
tWU_NPD
µS
tWU_FWPD
12
15
Note:
1. Based on test during characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
Table 8.3-8 Low-power Mode Wakeup Timings
July 2, 2020
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Rev 1.01
M251/M252
8.3.5
I/O Current Injection Characteristics
In general, I/O current injection due to external voltages below VSS or above VDD should be avoided
during normal product operation. However, the analog compoenent of the MCU is most likely to be
affected by the injection current , but it is not easily clarified when abnormal injection accidentally
happens. It is recommended to add a Schottky diode (pin to ground or pin to VDD) to pins that include
analog function which may potentially injection currents.
Negative
injection
Positive
injection
Symbol
Parameter
Unit
Test Condition
-0
-0
0
0
Injected current on nReset pins
Injected current on PF2~PF5, PA10,
PA11 and PB0~PB15 for analog
input function
Injected current by a I/O Pin
mA
IINJ(PIN)
Injected current on any other I/O
except analog input pin
-5
+5
Table 8.3-9 I/O Current Injection Characteristics
I/O DC Characteristics
8.3.6
8.3.6.1 PIN Input Characteristics
Symbol
Parameter
Min
Typ
Max
0.3*VDD
0.8
Unit
Test Conditions
Input low voltage (Schmitt trigger)
0
-
0
-
VDD = 4.5 V
VIL
V
Input low voltage (TTL trigger)
Input high voltage (Schmitt trigger)
Input high voltage (TTL trigger)
Hysteresis voltage of schmitt input
0
-
0.7
VDD = 2.7 V
VDD = 1.8 V
0
-
0.5
0.7*VDD
-
VDD
VDD
VDD
VDD
-
2
1.5
0.8
-
-
VDD = 5.5 V
VDD = 3.3 V
VDD = 1.8 V
VIH
V
V
-
-
[*1]
VHY
0.2*VDD
VSS < VIN < VDD
,
-1
-1
-
-
1
1
Open-drain or input only mode
[*2]
ILK
Input leakage current
A
VDD < VIN < 5 V, Open-drain or
input only mode on any other 5v
tolerance pins
[*1]
RPU
Pull up resistor
45
45
52
52
57
57
kΩ
kΩ
[*1]
RPD
Pull down resistor
Note:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
Table 8.3-10 I/O Input Characteristics
July 2, 2020
Page 217 of 266
Rev 1.01
M251/M252
8.3.6.2 I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 4.5 V
-7.5
-7.75
-8
µA
VIN=(VDD-0.4) V
Source current for quasi-
bidirectional mode and
high level
VDD = 2.7 V
-7.4
-7.2
-7.7
-4.9
-2.9
19
-7.7
-7.6
-8
-8
-8
µA
µA
mA
mA
mA
mA
mA
mA
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
[*1] [*2]
ISR
VDD = 4.5 V
-8.3
-5.5
-3.5
21
VIN=(VDD-0.4) V
VDD = 2.7 V
Source current for push-
pull mode and high level
-5.2
-3.2
20
VIN=(VDD-0.4) V
VDD = 1.8 V
VIN=(VDD-0.4) V
VDD = 4.5 V
VIN= 0.4 V
VDD = 2.7 V
VIN= 0.4 V
Sinkcurrent for push-pull
mode and low level
[*1] [*2]
ISK
12
13
14
VDD = 1.8 V
VIN= 0.4 V
7
8
9
Output high level voltage
for
mode
quasi-bidirectional VDD – 0.4
-
-
VDD
V
ISR = -7.2 µA
[*1]
VDD ≥ 2.7 V
VOH
V
V
V
ISR = -4.9 mA
Output high level voltage
for push-pull mode
VDD – 0.4
VDD
VDD ≥ 1.8 V
ISR = -2.9 mA
VDD ≥ 2.7 V
ISR = 12 mA
Output low level voltage
for push-pull mode
[*1]
VOL
VSS
-
0.4
-
VDD ≥ 1.8 V
V
ISR = 7 mA
[*1]
CIO
I/O pin capacitance
-
5
pF
Note:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.3-11 I/O Output Characteristics
July 2, 2020
Page 218 of 266
Rev 1.01
M251/M252
8.3.6.3 nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Internal nRESET pull up resistor
Min
Typ
-
Max Unit
Test Conditions
-
0.3*VDD
V
V
VIHR
0.7*VDD
-
-
47
-
[*1]
RRST
45
-
53
24
24
TBD
0.1
kΩ
Normal run and Idle mode
-
-
Fast wake up Power-down mode
Power-down mode
[*1]
tFR
nRESET input filtered pulse time
µS
-
-
-
-
Deep Power-down mode
Note:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin
Table 8.3-12 nRESET Input Characteristics
July 2, 2020
Page 219 of 266
Rev 1.01
M251/M252
8.4 AC Electrical Characteristics
8.4.1
48 MHz Internal High Speed RC Oscillator (HIRC)
The 48 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.75
-
5.5
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
47.52
-1
48
-
48.48
1
MHz
%
TA = 25 °C,
VDD = 3.3V
TA = 0C ~ +105 °C,
-2[*1]
-
2[*1]
%
fHRC
VDD = 1.75 ~ 5.5V
Frequency drift over temperarure and
volatge
TA = -20C ~ +105 °C,
-3[*1]
-
3[*1]
%
VDD = 1.75 ~ 5.5V
TA = -40C ~ +105 °C,
-4[*1]
-
4[*1]
800
16
%
VDD = 1.75 ~ 5.5V
[*1]
IHRC
Operating current
Stable time
-
-
500
14
µA
µS
TA = -40C ~ +105 °C,
[*2]
TS
VDD = 1.75 ~ 5.5V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-148 MHz Internal High Speed RC Oscillator(HIRC) Characteristics
July 2, 2020
Page 220 of 266
Rev 1.01
M251/M252
8.4.2
4 MHz Internal Median Speed RC Oscillator (MIRC)
The 4 MHz RC oscillator is calibrated in production.
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
1.75
-
5.5
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
3.951
-2
4.032
-
4.112
2
MHz
%
TA = 25 °C,
VDD = 3.3V
FMRC
Frequency drift over temperarure and
volatge
TA = -40C ~ +105 °C,
-10[*1]
-
-
-
10[*1]
30
%
VDD = 1.75 ~ 5.5V
[*1]
IMRC
Operating current
Stable time
-
-
µA
µS
TA = -40C ~ +105 °C,
[*2]
TS
24
VDD = 1.75 ~ 5.5V
Note:
1. Guaranteed by characterization result, not tested in production.
2. Guaranteed by design.
Table 8.4-2 4 MHz Internal Median Speed RC Oscillator (MIRC) Characteristics
July 2, 2020
Page 221 of 266
Rev 1.01
M251/M252
8.4.3
38.4 kHz Internal Low Speed RC Oscillator (LIRC)
Min[*1]
Typ
Max[*1]
Unit
Symbol
Parameter
Operating voltage
Test Conditions
VDD
1.75
-
5.5
V
TA = 25 °C,
VDD = 3.3V
Oscillator frequnecy
-
38.4
-
-
kHz
%
TA = 25 °C,
VDD = 3.3V
-2
2
[*2]
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105°C
-15
-
15
%
VDD=1.75V~5.5V
Without software calibration
ILRC
TS
Operating current
Stable time
-
-
0.85
-
1
µA
VDD = 3.3V
TA=-40~105°C
70
μS
VDD=1.75V~5.5V
Note:
1. Guaranteed by characterization, not tested in production.
2. The 38.4 kHz low speed RC oscillator can be calibrated by user.
3. Guaranteed by design.
Table 8.4-338.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics
July 2, 2020
Page 222 of 266
Rev 1.01
M251/M252
8.4.4
External 4~32 MHz High Speed Crystal/Ceramic Resonator (HXT) Characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[*1]
Typ
Max[*1]
Unit
V
Test Conditions
1.75
-
1000
-
5.5
-
Rf
Internal feedback resister
Oscillator frequency
-
kΩ
fHXT
4
32
MHz
4 MHz, Gain = L0, CL = 12.5
pF, ESR = 120Ω
-
-
-
-
-
45
80
150
250
430
600
760
8 MHz, Gain = L1, CL = 12.5
pF, ESR = 60Ω
12 MHz, Gain = L2, CL = 12.5
pF, ESR = 25Ω
150
230
280
IHXT
Current consumption
µA
16 Mhz, Gain = L3, CL = 12.5
pF, ESR = 25Ω
24 MHz, Gain = L4, CL = 12.5
pF, ESR = 25Ω
32 MHz, Gain = L7, CL = 12.5
pF, ESR = 25Ω
-
-
630
1550
2950
4 MHz, Gain = L0, CL = 12.5
pF, ESR = 120Ω
2550
8 MHz, Gain = L1, CL = 12.5
pF, ESR = 60Ω
-
-
-
-
-
900
550
400
300
250
1250
850
700
650
610
12 MHz, Gain = L2, CL = 12.5
pF, ESR = 25Ω
TS
Stable time
µs
16 Mhz, Gain = L3, CL = 12.5
pF, ESR = 25Ω
24 MHz, Gain = L4, CL = 12.5
pF, ESR = 25Ω
32 MHz, Gain = L7, CL = 12.5
pF, ESR = 25Ω
DuHXT
Vpp
Duty cycle
40
-
-
60
-
%
V
Peak-to-peak amplitude
1.6
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-4 External 4~32 MHz High Speed Crystal (HXT) Oscillator
July 2, 2020
Page 223 of 266
Rev 1.01
M251/M252
Symbol
Parameter
Min
Typ
Max[*1]
Unit
Test Conditions
Crystal @4 MHz, CL = 12.5 pF,
Gain = L0
-
-
120
Crystal @8 MHz, CL = 12.5 pF,
Gain = L1
-
-
-
-
-
-
-
-
-
-
60
25
25
25
25
Crystal @12 MHz, CL = 12.5
pF, Gain = L2
Rs
Equivalent series resisotr(ESR)
Ω
Crystal @16 MHz, CL = 12.5
pF, Gain = L3
Crystal @24 MHz, CL = 12.5
pF, Gain = L4
Crystal @32 MHz, CL = 12.5
pF, Gain = L7
Note:
1. Guaranteed by characterization, not tested in production.
2. Safety factor (Sf) must be higher than 5 for HXT to determine the oscillator safe operation during the application life. If
Safety factor isn’t enough, the HXT gain need be changed to higher driving level.
ꢃꢄ
ꢐꢂꢄ
ꢑ
ꢁꢂꢄ
ꢎꢏꢏꢂ
ꢁꢂ
ꢀ
ꢅꢆꢇꢈꢉꢊꢋꢂꢌꢍꢄ
ꢄ
ꢑ
RADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is
only used to measure Safety factor (Sf) of crystal in engineer stage, not for mass produciton.
XT1_OUT
XT1_IN
RADD
C2
C1
Table 8.4-5 External 4~32 MHz High Speed Crystal Characteristics
8.4.4.1 Typical Crystal Application Circuits
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 20 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 32 MHz
10 ~ 20 pF
10 ~ 20 pF
without
July 2, 2020
Page 224 of 266
Rev 1.01
M251/M252
XT1_OUT
XT1_IN
R1
C1
C2
Figure 8.4-1 Typical Crystal Application Circuit
July 2, 2020
Page 225 of 266
Rev 1.01
M251/M252
8.4.5
External 4~32 MHz High Speed Clock Input Signal Characteristics
For clock input mode, the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the table below. The characteristics result from
tests performed uses a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
1
-
32
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
nS
nS
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
nS
nS
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-6 External 4~32 MHz High Speed Clock Input Signal
8.4.6
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
for M251xC/M251xD/M252xC/M252xD
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Parameter
Min[*1]
Typ Max[*1] Unit
Test Conditions
July 2, 2020
Page 226 of 266
Rev 1.01
M251/M252
Symbol
VDD
Parameter
Min[*1]
1.75
-40
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
5.5
105
-
V
Temperature range
TLXT
C
Rf
Internal feedback resistor
Oscillator frequency
-
15
MΩ
kHz
FLXT
32.768
ESR=35 kΩ, CL = 12.5 pF, Gain =
L1
-
-
-
0.6
0.74
1
2.0
2.5
3.0
ESR=70 kΩ, CL = 12.5 pF, Gain =
L2
ILXT
Current consumption from VDD
A
ESR=70 kΩ, CL = 12.5 pF, Gain =
L3
TsLXT
DuLXT
Stable time
-
30
-
2
-
-
70
-
S
%
V
Duty cycle
[*1]
Vpp
Peak-to-peak amplitude
0.4
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-7 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Min
Typ
Max
Unit
Test Conditions
Equivalnet Series Resisotr(ESR)
-
35
70
kΩ
Crystal @32.768 kHz
Table 8.4-8 External 32.768 kHz Low Speed Crystal Characteristics
8.4.6.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
5 ~ 20 pF
5 ~ 20 pF
without
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-2 Typical 32.768 kHz Crystal Application Circuit
July 2, 2020
Page 227 of 266
Rev 1.01
M251/M252
8.4.7
External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) Characteristics
for M251xE/M251xG/M252xE/M252xG
The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in
order to minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VBAT
TLXT
Parameter
Min[*1]
1.75
-40
Typ Max[*1] Unit
Test Conditions
Operation voltage
-
-
5.5
105
-
V
Temperature range
C
Rf
Internal feedback resistor
Oscillator frequency
-
15
MΩ
kHz
FLXT
32.768
0.49
0.55
-
-
4.6
ESR=35 kΩ, CL = 6 pF, Gain = L1
ESR=35 kΩ, CL = 6 pF, Gain = L2
4.75
ESR=35 kΩ, CL = 12.5 pF, Gain =
L3
-
-
-
-
-
0.76
0.87
0.97
1.4
5
ESR=35 kΩ, CL = 12.5 pF, Gain =
L4
5.3
5.55
6.4
7.5
ILXT
Current consumption from VBAT
A
ESR=35 kΩ, CL = 12.5 pF, Gain =
L5
ESR=70 kΩ, CL = 12.5 pF, Gain =
L6
ESR=70 kΩ, CL = 12.5 pF, Gain =
L7
1.ƒ
TsLXT
DuLXT
Vpp
Stable time
-
30
-
2
-
-
70
-
S
%
V
Duty cycle
Peak-to-peak amplitude
0.3
Note:
1. Guaranteed by characterization, not tested in production.
Table 8.4-9 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
Symbol
Rs
Parameter
Min
Typ
Max
Unit
Test Conditions
Equivalnet Series Resisotr(ESR)
-
35
70
kΩ
Crystal @32.768 kHz
Table 8.4-10 External 32.768 kHz Low Speed Crystal Characteristics
8.4.7.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R1
32.768 kHz, ESR < 70 KΩ
5 ~ 20 pF
5 ~ 20 pF
without
July 2, 2020
Page 228 of 266
Rev 1.01
M251/M252
X32_OUT
X32_IN
R1
C1
C2
Figure 8.4-3 Typical 32.768 kHz Crystal Application Circuit
8.4.8
External 32.768 kHz Low Speed Clock Input Signal Characteristics
For clock input mode the LXT oscillator is switched off and X32_IN is a standard input pin to receive
external clock. The external clock signal has to respect the table below. The characteristics result from
tests performed uses a wavefrom generator.
Symbol
fLXT_ext
tCHCX
Parameter
External clock source frequency
Clock high time
Min[*1]
-
Typ
Max[*1]
Unit
kHz
nS
Test Conditions
32.768
-
-
-
450
450
-
-
tCLCX
Clock low time
nS
tCLCH
Clock rise time
Low (10%) to high level (90%)
rise time
-
-
-
-
50
50
nS
nS
tCHCL
Clock fall time
High (90%) to low level (10%) fall
time
DuE_LXT
Xin_VIH
Xin_VIL
Duty cycle
30
0.7*VDD
VSS
-
-
-
70
VDD
%
V
LXT input pin input high voltage
LXT input pin input low voltage
VBAT = VDD
VBAT = VDD
0.3*VDD
V
External
clock source
X32_IN
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Note:
1. Guaranteed by design, not tested in production.
Table 8.4-11 External 32.768 kHz Low Speed Clock Input Signal
July 2, 2020
Page 229 of 266
Rev 1.01
M251/M252
8.4.9
PLL Characteristics
Symbol
fPLL_in
Parameter
PLL input clock
Min[*1]
Typ
Max[*1]
24
Unit
MHz
MHz
MHz
MHz
µS
Test Conditions
4
16
4
-
-
-
-
-
fPLL_OUT
fPLL_REF
fPLL_VCO
TL
PLL multiplier output clock
PLL reference clock
100
8
PLL voltage controlled oscillator
PLL locking time
64
-
100
100
Jitter[*2]
Cycle-to-cycle Jitter
Power consumption
-
-
-
500
2
pS
f
VDD=5.5V @ PLL_VCO = 100
IDD
1
mA
MHz
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
Table 8.4-12 PLL Characteristics
July 2, 2020
Page 230 of 266
Rev 1.01
M251/M252
8.4.10 I/O AC Characteristics
Symbol
Parameter
Typ.
Max[*1]
.
Unit
Test Conditions[*2]
-
CL = 30 pF, V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
6.5
4.5
10
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
Output high (90%) to low level (10%) fall time
(Normal Slew Rate)
7
16.5
11.5
5
tf(IO)out
nS
3.5
8
Output high (90%) to low level (10%) fall time
(High Slew Rate)
5
12.5
8
7.5
5
12
Output low (10%) to high level (90%) rise time
(Normal Slew Rate)
nS
8
20.5
13.5
6.5
4.5
10
tr(IO)out
Output low (10%) to high level (90%) rise time
(High Slew Rate)
nS
6.5
18
10.5
47
70
I/O maximum frequency
(Normal Slew Rate)
[*3]
fmax(IO)out
30
MHz
44
18
July 2, 2020
Page 231 of 266
Rev 1.01
M251/M252
-
-
-
-
-
-
-
CL = 10 pF, V
>= 1.8 V
>= 4.5 V
>= 4.5 V
>= 2.7 V
>= 2.7 V
>= 1.8 V
>= 1.8 V
= 3.3 V,
26
55
80
36
56
21
35
DD
DD
DD
DD
DD
DD
DD
DD
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
CL = 10 pF, V
CL = 30 pF, V
I/O maximum frequency
(High Slew Rate)
MHz
2.77
-
f(IO)out = 24 MHz
CL = 10 pF, V
= 3.3 V,
DD
1.19
0.69
0.3
-
-
-
f(IO)out = 24 MHz
[*4]
IDIO
I/O dynamic current consumption
mA
CL = 30 pF, V
= 3.3 V,
= 3.3 V,
DD
f(IO)out = 6 MHz
CL = 10 pF, V
DD
f(IO)out = 6 MHz
Note:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
ꢕ
3. The maximum frequency is defined by ꢒꢓꢊꢔ ꢁꢂꢖꢂꢗꢂꢘꢉ ꢐꢉ ꢛꢂ.
ꢙ
ꢚ
4. The I/O dynamic current consumption is defined by ꢜꢝꢞꢟ ꢁ ꢠꢝꢝ ꢂꢗꢂꢒꢞꢟ ꢂꢗ ꢘꢡꢞꢟ ꢢꢂꢡꢣꢛ
Table 8.4-13 I/O AC Characteristics
July 2, 2020
Page 232 of 266
Rev 1.01
M251/M252
8.5 Analog Characteristics
8.5.1 LDO
Symbol
Parameter
Power supply
Min
1.75
-
Typ
-
Max
5.5
-
Unit
V
Test Condition
VDD
VLDO
Output voltage
Temperature
1.5
V
TA
-40
-
105
℃
Note:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF capacitor must be connected between LDO_CAP pin and the closest VSS pin of the
device.
3. VLDO is only used to supply internal power.
8.5.2
Reset and Power Control Block Characteristics
The parameters in the table below are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
Min
Typ
70
Max
100
3
Unit
Test Conditions
AVDD = 5.5V
[*1]
IPOR
-
-
µA
[*1]
ILVR
0.3
AVDD = 5.5V
[*1]
IBOD
AVDD = 5.5V, Normal
mode
-
-
40
3
60
6
AVDD = 5.5V, Low
Power mode
VPOR
VLVR
VBOD
POR reset voltage
LVR reset voltage
1.40
1.55
1.70
1.90
2.30
2.60
2.90
3.60
4.25
1.76
1.96
2.36
2.66
2.96
3.66
4.31
-
1.5
1.65
1.7
V
-
1.6
BOD brown-out detect voltage
(Falling edge)
1.80
2.00
2.40
2.70
3.00
3.70
4.40
1.88
2.08
2.48
2.78
3.08
3.78
4.48
200
1.90
2.10
2.50
2.80
3.10
3.80
4.50
2.00
2.20
2.60
2.90
3.20
3.90
4.60
2000
BODVL = 1
BODVL = 2
BODVL = 3
BODVL = 4
BODVL = 5
BODVL = 6
BODVL = 7
BODVL = 1
BODVL = 2
BODVL = 3
BODVL = 4
BODVL = 5
BODVL = 6
BODVL = 7
-
BOD brown-out detect voltage
(Rising edge)
[*1]
TLVR_SU
LVR startup time
µS
July 2, 2020
Page 233 of 266
Rev 1.01
M251/M252
[*1]
[*1]
TLVR_RE
LVR respond time
BOD startup time
BOD respond time
-
-
20
50
-
-
TBOD_SU
1000
2000
[*1]
TBOD_RE
-
1
-
2
Normal mode
Low Power mode
POR Enabled
POR Enabled
LVR Enabled
-
30000
[*1]
RVDDR
VDD rise time rate
VDD fall time rate
10
10
250
-
20000
µS/V
[*1]
RVDDF
-
-
-
-
BOD Enabled for
Normal mode
10
-
-
Note:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.5-1 Reset and power control unit
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Figure 8.5-1 Power Ramp Up/Down Condition
July 2, 2020
Page 234 of 266
Rev 1.01
M251/M252
8.5.3
12-bit SAR Analog to Digital Converter (ADC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
TA
Temperature
-40
105
-
℃
AV
=
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
1.75
1.75
0
-
-
-
5.5
V
V
V
VDD
DD
AVDD
VREF
ADC channel input voltage
AVDD = VDD =VREF = 3.3 V
FADC = 16 MHz
ADC Operating current (AVDD
current)
+ VREF
[*1]
IADC
-
-
355
µA
TCONV = 18 * TADC
NR
Resolution
12
-
Bit
[*1]
FADC
ADC Clock frequency
4
16
MHz
1/TADC
TSMP = ( EXTSMPT(EADC_SCTL
x[31:24]) + 1 ) * TADC
TSMP
Sampling Time
Conversion time
1
-
-
256
273
1/FADC
TCONV
18
1/FADC TCONV = TSMP + 17 * TADC
FSPS = FADC / TCONV
[*1]
FSPS
Sampling Rate
250
-
888.8 kSPS
EXTSMPT(ADC_ESMPCTL[7:0])
= 0
TEN
Enable to ready time
TBD
-3
-
-
-
μS
VREF = AVDD, REX = 50Ω
+3
LSB
except TSSOP20 and TSSOP28
INL[*1]
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
VREF = AVDD, REX = 50Ω
-TBD
-1
+TBD
+3
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TSSOP20 and TSSOP28
VREF = AVDD, REX = 50Ω
-
-
-
-
-
-
-
except TSSOP20 and TSSOP28
DNL[*1]
VREF = AVDD, REX = 50Ω
-TBD
-6
+TBD
+6
TSSOP20 and TSSOP28
VREF = AVDD, REX = 50Ω
except TSSOP20 and TSSOP28
[*1]
EG
VREF = AVDD, REX = 50Ω
-TBD
-3
+TBD
+3
TSSOP20 and TSSOP28
VREF = AVDD, REX = 50Ω
except TSSOP20 and TSSOP28
[*1]
EO
Offset error
T
VREF = AVDD, REX = 50Ω
-TBD
-1.5
+TBD
+6.5
TSSOP20 and TSSOP28
[*1]
EA
Absolute Error
VREF = AVDD, , REX = 50Ω
except TSSOP20 and TSSOP28
VREF = AVDD, REX = 50Ω
-TBD
TBD
-
+TBD
-
TSSOP20 and TSSOP28
ENOB[*1]
Effective number of bits
TBD
bits FADC = 16 MHz
July 2, 2020
Page 235 of 266
Rev 1.01
ꢒ
ꢧꢝꢅ ꢂꢗꢂꢡꢞꢨ ꢂꢗ ꢩꢪ ꢛ
ꢘꢫꢨꢐꢕ
M251/M252
Symbol
SINAD[*1]
SNR[*1]
Parameter
Signal-to-noise and distortion ratio
Signal-to-noise ratio
Min
TBD
TBD
TBD
-
Typ
TBD
TBD
TBD
26
Max
Unit
Test Conditions
AVDD = VDD =VREF = 1.8 V ~ 5.5 V
REX = 50Ω
-
-
dB
Input Frequency = 1 kHz ~ 20 kHz
TA = 25 °C
THD[*1]
Total harmonic distortion
Internal Capacitance
-
[*1]
CIN
30
-
pF
kΩ
kΩ
[*1]
RIN
Internal Switch Resistance
External input impedance
-
0.5
-
[*1]
REX
-
33
Note:
1. Guaranteed by characterization result, not tested in production.
2. REX max formula is used to determine the maximum external impedance allowed for 1/4 LSB error. N = 12 (based on
12-bit resoluton) and k is the number of sampling clocks (TSMP). CEX represents the capacitance of PCB and pad and
is combined with REX into a low-pass filter. Once the REX and CEX values are too large, it is possible to filter the real
signal and reduce the ADC accuracy.
ꢦ
ꢤꢌꢥ ꢁꢂ
ꢬꢂꢤꢞꢨ
VDD
EADC_CHx
RIN
REX
12-bit
Converter
VEX
CIN
CEX
Note: Injection current is a important topic of ADC accuracy. Injecting current on any analog input pins
should be avoided to protect the conversion being performed on another analog input. It is
recommended to add Schottky diodes (pin to ground and pin to power) to analog pins which may
potentially inject currents.
July 2, 2020
Page 236 of 266
Rev 1.01
M251/M252
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
July 2, 2020
Page 237 of 266
Rev 1.01
M251/M252
8.5.4
Analog Comparator Controller (ACMP)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VDD = AVDD
AVDD
Analog supply voltage
1.75
-40
-
-
5.5
V
TA
Temperature
105
℃
-
-
-
-
38
10
3
90
30
10
6
MODESEL = 11
MODESEL = 10
MODESEL = 01
MODESEL = 00
[*2]
IACMP
ACMP operating current
A
1.2
1/2 AVDD
AVDD -0.1
[*2]
VCM
Input common mode voltage range
0.1
[*2]
VDI
Differential input voltage sensitivity
Input offset voltage
-
-
10
±10
10
-
mV Hysteresis disable (HYSSEL = 00)
mV Hysteresis disable (HYSSEL = 00)
HYSSEL = 01
[*2]
±20
20
40
60
-
Voffset
-
[*2]
Vhys
Hysteresis window
DC voltage Gain
-
20
mV HYSSEL = 10
HYSSEL = 11
-
30
Av[*1]
43
-
70
dB
175
350
250
600
MODESEL = 11
-
MODESEL = 10
nS
[*2]
Td
Propagation delay
-
700 2000
1400 4500
250 + 450 +
MODESEL = 01
-
MODESEL = 00
µS
[*2]
TSetup
Setup time
-
Td
Td
[*2]
ACRV
CRV output voltage
Unit resistor value
Operating current
-5
-
-
5
%
AVDD x (1/6+CRVCTL/24)
[*2]
RCRV
4.7
30
-
kΩ
[*2]
IDD_CRV
-
120
A
Note:
1. Guaranteed by design, not tested in production.
2. Guaranteed by characteristic, not tested in production.
Table 8.5-2 ACMP Characteristics
July 2, 2020
Page 238 of 266
Rev 1.01
M251/M252
8.5.5
Digital to Analog Converter (DAC)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the typical values
for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Min
Typ
Max
Unit
Test Condition
AVDD
2.5
-
5.5
V
-
-
NR
Resolution
12
-
bit
V
VREF
VREF ≤ AVDD
Reference supply voltage
1.65
AVDD
±1
-
-
-
-
-
-
-
-
LSB 12-bit mode
DNL[*2]
Differential non-linearity error
Integral non-linearity error
±0.5 LSB 8-bit mode
12-bit mode
±2
LSB
INL[*2]
±0.5 LSB 8-bit mode
12-bit mode
-
-
±25
LSB
DACOUT buffer ON
OE[*2]
12-bit mode
Offset Error
-
-
-
-
-
-
±5
±2
LSB
DACOUT buffer OFF
LSB 8-bit mode
12-bit mode
LSB
±20
DACOUT buffer ON
GE[*2]
12-bit mode
Gain Error
-
-
-
-
-
-
±4
±2
±8
LSB
DACOUT buffer OFF
LSB 8-bit mode
12-bit mode
LSB
DACOUT buffer ON
AE[*2]
12-bit mode
Absolute Error
-
-
-
-
±4
±2
LSB
DACOUT buffer OFF
LSB 8-bit mode
-
-
Monotonic
10-bit guaranteed
-
AVDD
-
DACOUT buffer ON
DACOUT buffer OFF
0.2
-
-
V
V
0.2
[*1]
VO
Output Voltage
VREF
1*LSB
-
1*LSB
[*2] [*3]
RLOAD
Resistive load
DACOUT buffer ON
5
-
-
-
kΩ
kΩ
pF
[*2]
RO
Output impedance
Capacitive load
DACOUT buffer OFF
-
8
-
20
50
[*2] [*4]
CLOAD
-
July 2, 2020
Page 239 of 266
Rev 1.01
M251/M252
AVDD
= 5.5V, no load, lowest code
(0x000)
[*2]
IDAC_AVDD
-
340
550
280
A
A
μS
DAC operating current on AVDD supply
DAC operating current on VREF supply
AVDD
= 5.5V, no load, middle code
(0x800)
VREF =5.5V, no load, middle code
(0x800)
[*2]
IDAC_VREF
-
-
Full scale: for a 12-bit input code
transition between the lowest and the
highest input codes when DAC_OUT
reaches final value +/-1 LSB,
[*2]
TB
Settling Time
-
-
3
-
4
1
CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
Max. frequency for
MSPS DAC_OUT change from core i to
a
correct
FS
Update Rate
i+1LSB, CLOAD ≤ 50pF, RLOAD ≥ 5kΩ
Wakeup time from OFF state. Input
code between lowest and highest
possible codes.
TWAKEUP
Wake-up Time
-
-
9
15
μS
DAC clock source = 1MHz
PSRR[*1] Power Supply Rejection Ratio
Note:
-60
-40
dB
No RLOAD, CLOAD = 50pF
1. Guaranteed by design, not tested in production
2. Guaranteed by characteristic, not tested in production.
3. Resistive load between DACOUT and AVSS
.
4. Capacitive load at DACOUT pin.
July 2, 2020
Page 240 of 266
Rev 1.01
M251/M252
8.5.6
OP Amplifier (OPA)
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the
typical values for TA = 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Analog supply voltage
Min
Typ
Max
Unit
Test Condition
AVDD
2.5
-
5.5
V
TA
Temperature
-40
-
105
℃
IOPA
OPA operating current
-
500
1400
A
V
[*2]
VCM
Common mode input range
Output Saturation Voltage
0.1
0.1
-
-
AVDD-0.1
AVDD-0.1
[*2]
VOS
V
RLOAD = 4 KΩ
After Offset voltage calibration
VCM=AVDD/2
-
-
±1
±1
±3
±5
mV
mV
[*2]
VOFFSET0
Input offset voltage
After Offset voltage calibration
VCM=0.1 ~ AVDD – 0.1
CMRR[*1] Common Mode Rejection Ratio
PSRR[*1] Power Supply Rejection Ratio
GBW[*2] Bandwidth
-
-
-
89
120
5
-
-
-
dB AVDD=3.3V, VCM=AVDD/2
dB AVDD=3.3V, VCM=AVDD/2
MHz AVDD=3.3V, VCM=AVDD/2
SR[*2]
Slew rate
-
7.5
-
RLOAD = 4 KΩ, CLOAD = 50pF
V/S
AO[*1]
PM[*1]
GM[*1]
Open loop gain
-
-
91
63
TBD
2
-
-
dB
Phase Margin
degreeAVDD=3.3V, VCM=AVDD/2
Gain Margin
-
-
dB
S
kΩ
pF
[*2]
TWAKEUP
Wake up time from disable state
Resistive load
-
20
-
[*2]
RLOAD
4
-
-
[*2]
CLOAD
Capacitive load
-
50
Note:
1. Guaranteed by design, not tested in production
2.
Guaranteed by characteristic, not tested in production.
July 2, 2020
Page 241 of 266
Rev 1.01
M251/M252
8.5.7
Internal Voltage Reference
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Min
1.49
1.98
2.48
2.97
3.97
Typ
Max
1.59
2.11
2.64
3.17
4.22
Unit
Test Condition
AVDD >= 2.0 V
1.536
2.048
2.560
3.072
4.096
AVDD >= 2.4 V
AVDD >= 2.9 V
AVDD >= 3.4 V
AVDD >= 4.5 V
Internal reference voltage
V
VREF_INT
CL =4.7 uF, VREF initial=0V, Preload is
enabled.
-
-
-
0.5
9.3
24
0.8
13
mS
mS
S
CL =4.7 uF, VREF initial=5.5V, Preload is
enabled.
Ts[*1]
Stable time
CL =1 uF, VREF initial=0V, Preload is
enabled.
180
CL =1 uF, VREF initial=5.5V, Preload is
enabled.
-
-
2
-
2.6
1
mS
mA
[*1]
IVREF_INT
Note:
1. Guaranteed by characterization, not tested in production.
Internal VREF Operating current
VREF
1uF
Note: VREF_INT is only supported while package includes VREF pin with external capacitor.
Figure 8.5-2 Typical Connection with Internal Voltage Reference
July 2, 2020
Page 242 of 266
Rev 1.01
M251/M252
8.5.8
Temperature Sensor
The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (TA), and the
typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Symbol
Parameter
Temperature sensor offset voltage
Temperature Coefficient
Operating current
Min
690
-1.74
-
Typ
720
-1.83
16
Max
750
-1.9
30
Unit
mV
Test Condition
[*1]
TA = 0°C
VTEMP_OS
[*1]
mV/°C
A
TC
[*1]
ITEMP
Note:
1. Guaranteed by characterization, not tested in production
2. Guaranteed by design, not tested in production
3. VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV)
July 2, 2020
Page 243 of 266
Rev 1.01
M251/M252
8.6 Communications Characteristics
8.6.1
SPI Dynamic Characteristics
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
24
Unit
-
-
-
-
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
FSPICLK
SPI clock frequency
-
24
MHz
1/ TSPICLK
-
16
nS
nS
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
tDH
-
4.5
4.5
4.5
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
tV
Data output valid time
-
-
Note:
1.Guaranteed by design.
Table 8.6-1 SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-1 SPI Master Mode Timing Diagram
July 2, 2020
Page 244 of 266
Rev 1.01
M251/M252
Specificaitons[*1]
Test Conditions
Symbol
Parameter
Min
Typ
Max
11.2
8.8
Unit
-
-
-
-
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
FSPICLK
SPI clock frequency
-
MHz
1/ TSPICLK
-
4.6
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
nS
nS
1
TSPICLK
+ 2ns
-
-
-
-
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1
tSS
Slave select setup time
TSPICLK
+ 2ns
nS
1
TSPICLK
+ 3ns
-
-
-
-
1
tSH
tDS
tDH
Slave select hold time
nS
TSPICLK
Data input setup time
Data input hold time
1.5
-
-
-
-
-
-
nS
nS
3.5
-
-
-
-
35
42
74
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
tV
Data output valid time
nS
Note:
1.Guaranteed by design.
Table 8.6-2 SPI Slave Mode Characteristics
July 2, 2020
Page 245 of 266
Rev 1.01
M251/M252
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-2 SPI Slave Mode Timing Diagram
July 2, 2020
Page 246 of 266
Rev 1.01
M251/M252
8.6.2
SPI - I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min[*1]
Max[*1]
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
80
80
2
-
-
Master fPCLK = 48 MHz, data: 24 bits, audio
frequency = 128 kHz
6
-
Master mode
Master mode
Slave mode
Slave mode
nS
WS hold time
2
WS setup time
24
0
-
WS hold time
-
I2S slave input clock duty
cycle
DuCy(SCK)
30
70
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Note:
10
7
7
4
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
nS
Data output valid time
Data output hold time
Data output valid time
Data output hold time
25
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
4
-
4
-
0
1.Guaranteed by design.
Table 8.6-3 I2S Characteristics
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-3 I2S Master Mode Timing Diagram
July 2, 2020
Page 247 of 266
Rev 1.01
M251/M252
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.6-4 I2S Slave Mode Timing Diagram
July 2, 2020
Page 248 of 266
Rev 1.01
M251/M252
8.6.3
I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µS
µS
µS
µS
µS
µS
nS
µS
nS
nS
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-4 I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-5 I2C Timing Diagram
July 2, 2020
Page 249 of 266
Rev 1.01
M251/M252
8.6.4
USCI - SPI Dynamic Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
24
Unit
Test Conditions
-
-
-
-
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
FSPICLK
SPI clock frequency
-
24
MHz
1/ TSPICLK
-
16
nS
nS
tCLKH
tCLKL
tDS
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
TSPICLK / 2
TSPICLK / 2
2
4
-
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
tDH
9
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
tV
Data output valid time
-
9
-
8.5
Note:
1.Guaranteed by design.
Table 8.6-5 USCI-SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.6-6 USCI-SPI Master Mode Timing Diagram
July 2, 2020
Page 250 of 266
Rev 1.01
M251/M252
Symbol
Parameter
Min[*1]
Typ
Max[*1] Unit
Test Conditions
-
-
-
-
6.3
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
FSPICLK
SPI clock frequency
-
5.6
4.2
MHz
1/ TSPICLK
-
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
nS
nS
1
TSPICLK
+ 2ns
-
-
-
-
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1
tSS
Slave select setup time
TSPICLK
+ 2ns
nS
1
TSPICLK
+ 3ns
-
-
-
-
1
tSH
tDS
tDH
Slave select hold time
nS
TSPICLK
Data input setup time
Data input hold time
2
4
-
-
-
-
-
-
-
-
nS
nS
79
88
117
4.5 V ≤ VDD ≤ 5.5 V, CL = 30 pF
2.7 V ≤ VDD ≤ 5.5 V, CL = 30 pF
1.8 V ≤ VDD ≤ 5.5 V, CL = 30 pF
tV
Data output valid time
-
nS
-
Note:
1.Guaranteed by design.
Table 8.6-6 USCI-SPI Slave Mode Characteristics
July 2, 2020
Page 251 of 266
Rev 1.01
M251/M252
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.6-7 USCI-SPI Slave Mode Timing Diagram
July 2, 2020
Page 252 of 266
Rev 1.01
M251/M252
8.6.5
USCI-I2C Dynamic Characteristics
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µS
µS
µS
µS
µS
µS
nS
µS
nS
nS
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Note:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 8.6-7 USCI-I2C Characteristics
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-8 USCI-I2C Timing Diagram
July 2, 2020
Page 253 of 266
Rev 1.01
M251/M252
8.6.6
USB Characteristics
8.6.6.1 USB Full-Speed Characteristics
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
USB full speed transceiver
operating voltage
VBUS
4.4
-
5.25
V
-
USB Internal power regulator
output
[*2]
VDD33
3.0
3.3
3.6
V
-
VIH
VIL
VDI
Input high (driven)
Input low
2.0
-
-
-
-
-
0.8
-
V
V
V
-
-
Differential input sensitivity
0.2
|(USB_D+) - (USB_D-)|
Differential
VCM
0.8
-
2.5
V
Includes VDI range
common-mode range
Single-ended receiver threshold
Receiver hysteresis
0.8
-
-
2.0
-
V
mV
V
-
-
-
-
-
-
VSE
200
VOL
VOH
VCRS
RPU
Output low (driven)
0
-
-
-
-
0.3
3.6
2.0
1.9
Output high (driven)
2.8
1.3
1.19
V
Output signal cross voltage
Pull-up resistor
V
kΩ
Termination voltage for
upstream port pull-up (RPU)
VTRM
3.0
-
3.6
V
-
[*3]
ZDRV
Driver output resistance
Transceiver capacitance
-
-
10
-
-
Ω
Steady state drive
Pin to GND
CIN
26
pF
Note:
1. Guaranteed by characterization result, not tested in production.
2. To ensure stability, an external 1 μF output capacitor, 1uF external capacitor must be connected between the
USB_VDD33_CAP pin and the closest GND pin of the device.
3. USB_D+ and USB_D- must be connected with external series resistors to fit USB Full-speed spec request (28 ~
44Ω).
Table 8.6-8 USB Full-Speed Characteristics
8.6.6.2 USB Full-Speed PHY Characteristics
Symbol
TFR
Parameter
Min[*1]
Typ
Max[*1]
20
Unit
nS
nS
%
Test Conditions
CL=50 pF
rise time
fall time
4
4
-
-
-
TFF
20
CL=50 pF
TFRFF
rise and fall time matching
90
111.11
TFRFF = TFR/TFF
Note:
1. Guaranteed by characterization result, not tested in production.
Table 8.6-9 USB Full-Speed PHY Characteristics
July 2, 2020
Page 254 of 266
Rev 1.01
M251/M252
8.7 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.5
20
60
7
Max
Unit
V
Test Condition
[1]
VFLA
-
-
-
-
-
-
-
-
-
-
-
-
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
mS
µS
TA = 25℃
mA
mA
mA
IDD2
Program current
Erase current
8
IDD3
12
NENDUR
TRET
Endurance
100,000
10
-
-
-
-
cycles[2]
year
TJ = -40℃~125℃
100 kcycle[3] TJ = 85℃
Data retention
Note:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
July 2, 2020
Page 255 of 266
Rev 1.01
M251/M252
9 PACKAGE DIMENSIONS
9.1 TSSOP20 (4.4x6.5x0.9 mm3)
July 2, 2020
Page 256 of 266
Rev 1.01
M251/M252
9.2 TSSOP28 (4.4x9.7x1.0 mm3)
July 2, 2020
Page 257 of 266
Rev 1.01
M251/M252
9.3 QFN 33L (5x5x0.8 mm3)
July 2, 2020
Page 258 of 266
Rev 1.01
M251/M252
July 2, 2020
Page 259 of 266
Rev 1.01
M251/M252
9.4 LQFP 48L (7x7x1.4 mm3 Footprint 2.0 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
0.024 0.030
0.45
0
L
L
Y
0.039
0.004
7
1
0.10
7
0
0
July 2, 2020
Page 260 of 266
Rev 1.01
M251/M252
9.5 LQFP 64L (7x7x1.4 mm3 Footprint 2.0 mm)
July 2, 2020
Page 261 of 266
Rev 1.01
M251/M252
9.6 LQFP 128L (14x14x1.4 mm3 Footprint 2.0 mm)
July 2, 2020
Page 262 of 266
Rev 1.01
M251/M252
10 ABBREVIATIONS
10.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EADC
EBI
Enhanced Analog-to-Digital Converter
External Bus Interface
EMAC
EPWM
FIFO
FMC
FPU
Ethernet MAC Controller
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
Pulse Width Modulation
July 2, 2020
Page 263 of 266
Rev 1.01
M251/M252
QEI
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 10.1-1 List of Abbreviations
July 2, 2020
Page 264 of 266
Rev 1.01
M251/M252
11 REVISION HISTORY
Date
Revision
Description
2020.04.10
1.00
Initial version.
1. Revised stable time test condition of internal reference voltage in section 8.5.7.
2. Revised RADD connection that is closed to XT1_OUT pin in Table 8.4-5.
3. Revised tWU_DPD value in Table 8.3-8
4. Revised application circuit in Chapter 7.
2020.07.02
1.01
5. Revised IDD_FWPD value in Table 8.3-3.
6. Added a 10Ω series resistor on USB_Vbus in section 7.2
7. Updated OPA characteristics in section 8.5.6.
8. Updated supply current characteristics for M251xE/M251xG/M252xE/M252xG in
section 8.3.2.
July 2, 2020
Page 265 of 266
Rev 1.01
M251/M252
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
July 2, 2020
Page 266 of 266
Rev 1.01
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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