M4521LE6AE_技术文档

M4521

Arm^®Cortex^®-M

32-bit Microcontroller

NuMicro^®Family

M4521 Series

Datasheet

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Oct. 15, 2018

Page 1 of 117

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M4521

TABLE OF CONTENTS

1

2

GENERAL DESCRIPTION -------------------------------------------------8

FEATURES----------------------------------------------------------------9

NuMicro^®M4521 Features ................................................................. 9

Abbreviations ------------------------------------------------------------ 14

PARTS INFORMATION LIST AND PIN CONFIGURATION ---------------- 16

NuMicro^®M4521 Selection Guide....................................................... 16

2.1

3

4

4.1

4.1.1

4.1.2

4.2

4.2.1

4.2.2

4.3

NuMicro^®M4521 Naming Rule ---------------------------------------------------- 16

NuMicro^®M4521 USB Series Selection Guide ------------------------------------- 17

Pin Configuration .......................................................................... 18

NuMicro^®M4521 Series LQFP48 Pin Diagram ------------------------------------- 18

NuMicro^®M4521 Series LQFP64 Pin Diagram ------------------------------------- 19

Pin Description............................................................................. 20

M4521 Series LQFP48 Pin Description -------------------------------------------- 20

M4521 Series LQFP64 Pin Description -------------------------------------------- 27

GPIO Multi-function Pin Summary ------------------------------------------------- 35

4.3.1

4.3.2

4.3.3

5

6

BLOCK DIAGRAM ------------------------------------------------------- 42

NuMicro^®M4521 Series Block Diagram................................................ 42

FUNCTIONAL DESCRIPTION-------------------------------------------- 43

Arm^®Cortex^®-M4 Core.................................................................... 43

System Manager........................................................................... 46

5.1

6.1

6.2

6.2.1

6.2.2

Overview------------------------------------------------------------------------- 46

System Reset -------------------------------------------------------------------- 46

Power Modes and Wake-up Sources ---------------------------------------------- 53

System Power Distribution -------------------------------------------------------- 55

System Memory Map ------------------------------------------------------------- 57

SRAM Memory Organization ------------------------------------------------------ 60

System Timer (SysTick)----------------------------------------------------------- 62

Nested Vectored Interrupt Controller (NVIC) --------------------------------------- 62

Clock Controller............................................................................ 63

Overview------------------------------------------------------------------------- 63

Clock Generator ------------------------------------------------------------------ 65

System Clock and SysTick Clock -------------------------------------------------- 66

Peripherals Clock----------------------------------------------------------------- 67

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.3

6.3.1

6.3.2

6.3.3

6.3.4

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6.3.5

6.3.6

Power-down Mode Clock---------------------------------------------------------- 68

Clock Output --------------------------------------------------------------------- 68

Flash Memeory Controller (FMC) ....................................................... 70

Overview------------------------------------------------------------------------- 70

Features ------------------------------------------------------------------------- 70

External Bus Interface (EBI) ............................................................. 71

Overview------------------------------------------------------------------------- 71

Features ------------------------------------------------------------------------- 71

General Purpose I/O (GPIO)............................................................. 72

Overview------------------------------------------------------------------------- 72

Features ------------------------------------------------------------------------- 72

PDMA Controller (PDMA) ................................................................ 73

Overview------------------------------------------------------------------------- 73

Features ------------------------------------------------------------------------- 73

Timer Controller (TMR) ................................................................... 74

Overview------------------------------------------------------------------------- 74

Features ------------------------------------------------------------------------- 74

PWM Generator and Capture Timer (PWM)........................................... 75

Overview------------------------------------------------------------------------- 75

Features ------------------------------------------------------------------------- 75

Watchdog Timer (WDT) .................................................................. 77

Overview----------------------------------------------------------------------- 77

Features ----------------------------------------------------------------------- 77

Window Watchdog Timer (WWDT) ..................................................... 78

Overview----------------------------------------------------------------------- 78

Features ----------------------------------------------------------------------- 78

Real Time Clock (RTC) ................................................................... 79

Overview----------------------------------------------------------------------- 79

Features ----------------------------------------------------------------------- 79

UART Interface Controller (UART)...................................................... 80

Overview----------------------------------------------------------------------- 80

Features ----------------------------------------------------------------------- 80

Smart Card Host Interface (SC) ......................................................... 82

Overview----------------------------------------------------------------------- 82

Features ----------------------------------------------------------------------- 82

6.4

6.4.1

6.4.2

6.5

6.5.1

6.5.2

6.6

6.6.1

6.6.2

6.7

6.7.1

6.7.2

6.8

6.8.1

6.8.2

6.9

6.9.1

6.9.2

6.10

6.10.1

6.10.2

6.11

6.11.1

6.11.2

6.12

6.12.1

6.12.2

6.13

6.13.1

6.13.2

6.14

6.14.1

6.14.2

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6.15

6.15.1

6.15.2

6.16

I²C Serial Interface Controller (I²C)...................................................... 83

Overview----------------------------------------------------------------------- 83

Features ----------------------------------------------------------------------- 83

Serial Peripheral Interface (SPI)......................................................... 84

Overview----------------------------------------------------------------------- 84

Features ----------------------------------------------------------------------- 84

USB Device Controller (USBD).......................................................... 85

Overview----------------------------------------------------------------------- 85

Features ----------------------------------------------------------------------- 85

USB 1.1 Host Controller (USBH) ........................................................ 86

Overview----------------------------------------------------------------------- 86

Features ----------------------------------------------------------------------- 86

CRC Controller (CRC) .................................................................... 87

Overview----------------------------------------------------------------------- 87

Features ----------------------------------------------------------------------- 87

Enhanced 12-bit Analog-to-Digital Converter (EADC) ............................... 88

Overview----------------------------------------------------------------------- 88

Features ----------------------------------------------------------------------- 88

6.16.1

6.16.2

6.17

6.17.1

6.17.2

6.18

6.18.1

6.18.2

6.19

6.19.1

6.19.2

6.20

6.20.1

6.20.2

7

8

APPLICATION CIRCUIT ------------------------------------------------- 89

ELECTRICAL CHARACTERISTICS--------------------------------------- 90

Absolute Maximum Ratings .............................................................. 90

DC Electrical Characteristics............................................................. 91

8.1

8.2

8.2.1

On-chip peripheral current consumption ------------------------------------------- 96

AC Electrical Characteristics............................................................. 98

External 4~20 MHz High Speed Crystal (HXT) Input Clock-------------------------- 98

External 4~20 MHz High Speed Crystal (HXT) Oscillator---------------------------- 98

22.1184 MHz Internal High Speed RC Oscillator (HIRC) ---------------------------- 99

32.768 kHz External Low Speed Crystal (LXT) Input Clock------------------------- 100

32.768 kHz External Low Speed Crystal (LXT) Oscillator -------------------------- 100

10 kHz Internal Low Speed RC Oscillator (LIRC) ---------------------------------- 101

Analog Characteristics ...................................................................102

PIN AC characteristics ----------------------------------------------------------- 102

12-bit SAR ADC ----------------------------------------------------------------- 103

LDO ---------------------------------------------------------------------------- 105

Low Voltage Reset--------------------------------------------------------------- 105

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.4

8.4.1

8.4.2

8.4.3

8.4.4

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8.4.5

8.4.6

8.4.7

8.4.8

8.4.9

Brown-out Detector -------------------------------------------------------------- 105

Power-on Reset ----------------------------------------------------------------- 106

Temperature Sensor------------------------------------------------------------- 106

Internal Voltage Reference------------------------------------------------------- 107

USB PHY ----------------------------------------------------------------------- 107

Flash DC Electrical Characteristics ....................................................109

I²C Dynamic Characteristics ............................................................110

SPI Dynamic Characteristics............................................................111

Dynamic Characteristics of Data Input and Output Pin ----------------------------- 111

8.5

8.6

8.7

8.7.1

9

PACKAGE DIMENSIONS -----------------------------------------------114

LQFP 64L (7x7x1.4 mm footprint 2.0 mm)............................................114

LQFP 48L (7x7x1.4mm footprint 2.0mm) .............................................115

9.1

9.2

10 REVISION HISTORY----------------------------------------------------116

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List of Figures

Figure 4.1-1 NuMicro^®M4521 Selection Code.............................................................................. 16

Figure 4.2-1 NuMicro^®M4521 Series LQFP 48-pin Diagram ........................................................ 18

Figure 4.2-2 NuMicro^®M4521 Series LQFP 64-pin Diagram ........................................................ 19

Figure 5.1-1 NuMicro^®M4521 Series Block Diagram.................................................................... 42

Figure 6.1-1 Cortex^®-M4 Block Diagram........................................................................................ 43

Figure 6.2-1 System Reset Sources.............................................................................................. 47

Figure 6.2-2 nRESET Reset Waveform......................................................................................... 49

Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 50

Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 51

Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 52

Figure 6.2-6 Power Mode State Machine ...................................................................................... 53

Figure 6.2-7 NuMicro^®M4521 Series Power Distribution Diagram ............................................... 56

Figure 6.2-8 SRAM Block Diagram................................................................................................ 60

Figure 6.2-9 SRAM Memory Organization..................................................................................... 61

Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 64

Figure 6.3-2 Clock Generator Block Diagram................................................................................ 65

Figure 6.3-3 System Clock Block Diagram .................................................................................... 66

Figure 6.3-4 HXT Stop Protect Procedure..................................................................................... 67

Figure 6.3-5 SysTick Clock Control Block Diagram....................................................................... 67

Figure 6.3-6 Clock Source of Clock Output ................................................................................... 68

Figure 6.3-7 Clock Output Block Diagram ..................................................................................... 69

Figure 8.3-1 Typical Crystal Application Circuit ............................................................................. 99

Figure 8.3-2 HIRC Accuracy vs. Temperature............................................................................. 100

Figure 8.3-3 Typical Crystal Application Circuit ........................................................................... 101

Figure 8.4-1 Typical connection diagram using the ADC ............................................................ 104

Figure 8.4-2 Power-up Ramp Condition ...................................................................................... 106

Figure 8.6-1 I²C Timing Diagram ................................................................................................. 110

Figure 8.7-1 SPI Master Mode Timing Diagram .......................................................................... 111

Figure 8.7-2 SPI Slave Mode Timing Diagram ............................................................................ 113

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List of Tables

Table 2.1-1 List of Abbreviations.................................................................................................... 15

Table 4.3-1 M4521 GPIO Multi-function Table .............................................................................. 41

Table 6.2-1 Reset Value of Registers............................................................................................ 49

Table 6.2-2 Power Mode Difference Table .................................................................................... 53

Table 6.2-3 Clocks in Power Modes .............................................................................................. 54

Table 6.2-4 Condition of Entering Power-down Mode Again......................................................... 55

Table 6.2-5 Address Space Assignments for On-Chip Controllers................................................ 59

Table 6.13-1 NuMicro^®M4521 Series UART Feature ................................................................... 81

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M4521

1 GENERAL DESCRIPTION

The NuMicro^®M4521 series 32-bit microcontroller powered by Arm^®Cortex^®-M4F with DSP and

FPU runs up to 72 MHz. It is embedded with 128 KB Flash ROM, 32 KB SRAM and independent

4 KB In System Programming Flash ROM. The M4521 series is equipped with plenty of

peripherals: 3 sets of UART with 16-byte FIFO, 2 sets of I²C that support SMBus and PMBus, SPI

and Quad-SPI, ISO-7816, USB full-speed device/host, and EBI that provides great flexibility

through adding external memory. It also offers four 32-bit timers, two watchdog timers, 8-ch

peripheral DMA, 12-ch 16-bit PWM, and 16-ch 12-bit SAR ADC with 1 MSPS conversion rate.

The M4521 series provides two special designs. One is high-resolution 144 MHz PWM with high-

speed timer (resolution<7ns). In conjunction with a driver ADC, it delivers hardware brake

protection and pulse capture functions to save MCU computing resource and effectively perform

advanced computing task in motor control application, making the M4521 series exceptionally

outstanding in industrial automation control. The other is VAI (Voltage Adjustment Interface)

which supports voltage level adjustment on individual I/O (1.8V-5.5V) for saving additional cost on

adjusting the interface voltage difference with external components.

The M4521 series also provides the wide operating voltage (2.5V-5.5V), industrial operating

temperature (-40°C - 105°C), 5V-tolerance input I/O to significantly enhance system stability. The

22.1184 MHz internal RC oscillator (HIRC variation < ±2%) and 32.768 kHz external crystal

oscillator can trim HIRC (HIRC variation < ±0.25%) working at -40˚C- 105˚C to enhance system

immunity and fulfill the high precision demand of communications. The M4521 series is

specifically suitable for high-performance and high-precision applications, such as industrial

automation, home automation, security alarm system, and gaming peripherals.

The M4521 series is suitable for a wide range of applications such as:



Industrial Automation

PLCs

Home Automation

Security Alarm System

Power Metering

Data Collector

RFID Reader

System Supervisors

Smart Card Reader

Printer

Bar Code Scanner

Motor Control

Digital Power

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M4521

2 FEATURES

2.1 NuMicro^®M4521 Features

Core

–

Arm^®Cortex^®-M4F core running up to 72 MHz

Supports DSP extension with hardware divider

Supports IEEE 754 compliant Floating-point Unit (FPU)

Supports Memory Protection Unit (MPU)

One 24-bit system timer

Supports Low Power Sleep mode by WFI and WFE instructions

Single-cycle 32-bit hardware multiplier

Supports programmable 16 level priorities of Nested Vectored Interrupt Controller

(NVIC)

–

Supports programmable mask-able interrupts

Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V

Flash Memory

–

Supports 128 KB application ROM (APROM)

Supports 4 KB Flash for loader (LDROM)

Supports Data Flash with configurable memory size

Supports In-System-Programming (ISP), In-Application-Programming (IAP) update

embedded Flash memory

–

Supports 2 KB page erase for all embedded Flash

SRAM Memory

–

32 KB embedded SRAM

Supports byte-, half-word- and word-access

Supports PDMA mode

PDMA (Peripheral DMA)

–

Supports 8 independent configurable channels for automatic data transfer between

memories and peripherals

–

Supports Normal and Scatter-Gather Transfer modes

Supports two types of priorities modes: Fixed-priority and Round-robin modes

Supports byte-, half-word- and word-access

Auto increment of the source and destination address

Supports single and burst transfer type

Clock Control

–

Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation

(variation < 2% at -40˚C ~ +105˚C)

–

Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-

up operation

Built-in 4~20 MHz external high speed crystal oscillator (HXT) for precise timing

operation

Built-in 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and

low-power system operation

Supports one PLL up to 144 MHz for high performance system operation, sourced

from HIRC and HXT

–

Supports clock failure detection for high/low speed external crystal oscillator

Supports exception (NMI) generated once a clock failure detected

Supports clock output

GPIO

–

Four I/O modes

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M4521

–

TTL/Schmitt trigger input selectable

I/O pin configured as interrupt source with edge/level trigger setting

Supports high driver and high sink current I/O (up to 20 mA at 5V)

Supports software selectable slew rate control

Supports 5V-tolerance function for following pins



PA.0 ~ PA.3, PC.0 ~ PC.7, PD.2 ~ PD.3, PD.7, PD.12 ~ PD.15, PE.0, PE.8 ~

PE.13, PF.2, PF.5 ~ PF.7

–

Supports up to 49/35 GPIOs for LQFP64/48 respectively

Timer

–

Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter

Independent clock source for each timer

Provides One-shot, Periodic, Toggle and Continuous Counting operation modes

Supports event counting function to count the event from external pin

Supports input capture function to capture or reset counter value

Watchdog Timer

–

Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT

8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)

Able to wake up from Power-down or Idle mode

Interrupt or reset selectable on watchdog time-out

Window Watchdog Timer

–

Supports multiple clock sources from HCLK/2048 (default selection) and LIRC

Window set by 6-bit counter with 11-bit prescale

Able to wake up from Power-down or Idle mode

Interrupt or reset selectable on time-out

RTC

–

Supports external power pin V_BAT

Supports software compensation by setting frequency compensate register (FCR)

Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)

Supports Alarm registers (second, minute, hour, day, month, year)

Selectable 12-hour or 24-hour mode

Automatic leap year recognition

Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,

1/4, 1/2 and 1 second

–

Supports wake-up function

Supports 80 bytes spare registers

Programmable spare register erase function

Supports 32KHz Oscillator gain control

Supports tamper detection function

PWM

–

Supports up to 12 independent PWM outputs with 16-bit resolution

Supports maximum clock frequency up to 144MHz

Supports 12-bit clock prescale

Supports one-shot or auto-reload counter operation mode

Supports up, down or up-down PWM counter type

Supports synchronous function

Supports dead time with maximum divided 12-bit prescale

Supports brake function source from pin, comparator output and system safety events

Supports PWM auto recovery function after brake condition removed

Supports mask function and tri-state output for each PWM pin

Supports PWM events interrupt

Supports trigger EADC start conversion

Supports up to 12 independent input capture channels with rising/falling capture and

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with counter reload option

–

Supports capture counter with 16-bit resolution

Supports capture interrupt

Supports capture PDMA mode

UART

–

Supports up to four UARTs – UART0, UART1, UART2 and UART3

Supports 16-byte FIFOs with programmable level trigger

Supports auto flow control ( CTS and RTS)

Supports IrDA (SIR) function

Supports RS-485 9-bit mode and direction control

Programmable baud-rate generator up to 1/16 system clock

Supports wake-up function

Supports PDMA mode

Smart Card Interface

–

One set of ISO-7816-3 port

Compliant to ISO-7816-3 T=0, T=1

Separate receive / transmit 4 bytes entry FIFO for data payloads

Programmable transmission clock frequency

Programmable receiver buffer trigger level

Programmable guard time selection (11 ETU ~ 266 ETU)

A 24-bit and two 8 bit time-out counters for Answer to Request (ATR) and waiting times

processing

–

Supports auto inverse convention function

Supports stop clock level and clock stop (clock keep) function

Supports transmitter and receiver error retry and error limit function

Supports hardware activation/deactivation sequence process

Supports hardware warm reset sequence process

Supports hardware auto deactivation sequence when detect the card is removal

Supports UART function

 Quad SPI

–

Supports one set of SPI Quad controller – SPI0

Supports Master or Slave mode operation

Supports 2-bit Transfer mode

Supports Dual and Quad I/O Transfer mode

Configurable bit length of a transfer word from 8 to 32-bit

Provides separate 8-level depth transmit and receive FIFO buffers

Supports MSB first or LSB first transfer sequence

Supports the byte reorder function

Supports Byte or Word Suspend mode

Supports PDMA operation

Supports 3-wired, no slave select signal, bi-direction interface

Master up to 32 MHz, and Slave up to 16 MHz (when chip works at V_DD= 5V)

 SPI

–

Supports one set of SPI controller – SPI1

Supports Master or Slave mode operation

Configurable bit length of a transfer word from 8 to 32-bit

Provides separate 4-level depth transmit and receive FIFO buffers

Supports MSB first or LSB first transfer sequence

Supports the byte reorder function

Supports Byte or Word Suspend mode

Supports PDMA operation

Supports 3-wire, no slave select signal, bi-direction interface

Master mode up to 36 MHz and Slave mode up to 18 MHz (when chip works at V_DD

=

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5V)

I²C

–

Supports up to two sets of I²C devices

Supports Master/Slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

–

Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

–

Programmable clocks allow versatile rate control

Supports multiple address recognition (four slave address with mask option)

Supports SMBus and PMBus

Supports speed up to 1Mbps

Supports multi-address Power-down wake-up function

USB 2.0 Full-Speed Device Controller

–

Supports one set of USB 2.0 FS device

Compliant to USB specification version 2.0

On-chip USB Transceiver

Supports Control, Bulk In/Out, Interrupt and Isochronous transfers

Auto suspend function when no bus signaling for 3 ms

Provides 8 programmable endpoints

Supports 512 Bytes internal SRAM as USB buffer

Provides remote wake-up capability

Start of Frame (SOF) locked clock pulse generation for crystal-less feature (48MHz

internal RC oscillator for USB crystal-less only)

On-chip 5V to 3.3V LDO for USB PHY

–

USB 2.0 Full-Speed Host Controller

–

Compliant with USB Revision 1.1 Specification

Compatible with OHCI (Open Host Controller Interface) Revision 1.0

Supports full-speed (12 Mbps) and low-speed (1.5 Mbps) USB devices

Supports Control, Bulk, Interrupt, Isochronous transfers

Supports an integrated Root Hub

Supports port power control and port over current detection

Built-in DMA

EBI

–

Supports two dedicated external chip select pins for each memory block

Supports external accessible space up to 1 Mbytes (need 20-bit address width) for

each bank. Real addressable space size is dependent on package pin out

Supports 8-/16-bit data width

Supports byte write in 16-bit data width mode

Supports PDMA mode

Supports Address/Data multiplexed Mode

Supports LCD interface i80 mode

Supports Timing parameters individual adjustment for each memory block

–

EADC

–

Analog input voltage range: 0~ V_REF(Max to AV_DD)

Supports single 12-bit SAR ADC conversion

12-bit resolution and 10-bit accuracy is guaranteed

Up to 1MSPS conversion rate at 5.0V

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M4521

–

Up to 16 external single-ended analog input channels

Up to 8 differential analog input pairs

Supports single ADC interrupt

Supports external V_REFpin

Support internal reference voltages from Band-gap and Voltage divider

An A/D conversion can be triggered by Software enable, External pin, Timer 0~3

overflow pulse trigger and PWM trigger

–

Supports 3 internal channels for V_BAT, band-gap VBG input and Temperature sensor

input

–

Supports PDMA transfer

Cyclic Redundancy Calculation Unit

–

Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32

Programmable initial value

Supports programmable order reverse setting for input data and CRC checksum

Supports programmable 1’s complement setting for input data and CRC checksum.

Supports 8-/16-/32-bit of data width

–

Interrupt generated once checksum error occurs

Voltage Adjustable Interface

–

Supports user Configurable 1.8~5.5V I/O Interface with a dedicated power input (V_DDIO

)

Supports UART1, SPI0, SPI1, I²C1 or I²C0 interface

Supports 96-bit Unique ID (UID)

Supports 128-bit Unique Customer ID (UCID)

One built-in temperature sensor with 1℃ resolution

Brown-out detector

–

With 4 levels: 4.4 V/ 3.7 V/ 2.7 V/ 2.2 V

Supports Brown-out Interrupt and Reset option

Low Voltage Reset

–

Threshold voltage levels: 2.0 V

Operating Temperature: -40℃~105℃

Packages

–

LQFP 64-pin (7mm x 7mm)

LQFP 48-pin (7mm x 7mm)

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M4521

3 ABBREVIATIONS

Acronym

ACMP

ADC

AES

APB

AHB

BOD

CAN

DAP

DES

EBI

Description

Analog Comparator Controller

Analog-to-Digital Converter

Advanced Encryption Standard

Advanced Peripheral Bus

Advanced High-Performance Bus

Brown-out Detection

Controller Area Network

Debug Access Port

Data Encryption Standard

External Bus Interface

EPWM

FIFO

FMC

FPU

GPIO

HCLK

HIRC

HXT

IAP

Enhanced Pulse Width Modulation

First In, First Out

Flash Memory Controller

Floating-point Unit

General-Purpose Input/Output

The Clock of Advanced High-Performance Bus

22.1184 MHz Internal High Speed RC Oscillator

4~24 MHz External High Speed Crystal Oscillator

In Application Programming

In Circuit Programming

ICP

ISP

In System Programming

LDO

LIN

Low Dropout Regulator

Local Interconnect Network

10 kHz internal low speed RC oscillator (LIRC)

Memory Protection Unit

LIRC

MPU

NVIC

PCLK

PDMA

PLL

Nested Vectored Interrupt Controller

The Clock of Advanced Peripheral Bus

Peripheral Direct Memory Access

Phase-Locked Loop

PWM

QEI

Pulse Width Modulation

Quadrature Encoder Interface

Secure Digital

SD

SPI

Serial Peripheral Interface

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M4521

SPS

Samples per Second

TDES

TK

Triple Data Encryption Standard

Touch Key

TMR

UART

UCID

USB

Timer Controller

Universal Asynchronous Receiver/Transmitter

Unique Customer ID

Universal Serial Bus

WDT

WWDT

Watchdog Timer

Window Watchdog Timer

Table 2.1-1 List of Abbreviations

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M4521

4 PARTS INFORMATION LIST AND PIN CONFIGURATION

4.1 NuMicro^®M4521 Selection Guide

4.1.1

NuMicro^®M4521 Naming Rule

ARM–Based

32-bit Microcontroller

-X X X X X

M4521

CPU Core

®

Cortex -M4

Temperature

E: -40^oC ~ +105^oC

Reserved

Package Type

L: LQFP 48 7x7mm

S: LQFP 64 7x7mm

SRAM Size

6: 32KB

Flash ROM

E: 128KB

Figure 4.1-1 NuMicro^®M4521 Selection Code

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M4521

4.1.2

NuMicro^®M4521 USB Series Selection Guide

Connectivity

Dual Role

M4521LE6AE 128 32

M4521SE6AE 128 32

4

35

49

4

3+1

4+1

1

2

--

10

12

--

-- 10-ch

-- 16-ch

√

8-bit

√

LQFP 48

(Device/Host)

Dual Role

16-bit

LQFP 64*

(Device/Host)

*Marked in this table (4+1) means 4 UART + 1 SC UART

*SC (ISO-7816) supports full duplex UART mode

*Package dimension of LQFP64* of M4521 series is 7x7x1.4 mm footprint 2.0mm

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M4521

4.2 Pin Configuration

4.2.1

NuMicro^®M4521 Series LQFP48 Pin Diagram

Corresponding Part Number: M4521LE6AE

PA.3

PA.2

PA.1

PA.0

V_DD

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

PE.0

PC.4

PC.3

PC.2

PC.1

AV_DD

V_REF

PB.0

PB.1

PB.2

PB.3

PB.4

PC.0

LQFP 48-pin

LDO_CAP

V_SS

PF.4/XT1_IN

PF.3/XT1_OUT

PD.7

PF.2

Figure 4.2-1 NuMicro^®M4521 Series LQFP 48-pin Diagram

Oct. 15, 2018

Page 18 of 117

Rev.1.00

M4521

4.2.2

NuMicro^®M4521 Series LQFP64 Pin Diagram

Corresponding Part Number: M4521SE6AE

PA.3

PA.2

PA.1

PA.0

V_SS

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PC.5

PC.4

PC.3

PC.2

PC.1

V_DD

PC.0

AV_DD

V_REF

LDO_CAP

V_DD

LQFP 64-pin

PB.0

PB.1

PB.2

PB.3

PB.4

PB.8

PB.11

PB.12

V_SS

PF.4/XT1_IN

PF.3/XT1_OUT

PD.7

PD.15

PD.14

PD.13

PD.12

Figure 4.2-2 NuMicro^®M4521 Series LQFP 64-pin Diagram

Oct. 15, 2018

Page 19 of 117

Rev.1.00

M4521

4.3 Pin Description

4.3.1

M4521 Series LQFP48 Pin Description

Corresponding Part Number: M4521LE6AE

MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)

PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.

PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.

Pin No.

Pin Name

PB.5

Type

I/O

A

MFP*

MFP0

MFP1

MFP2

MFP3

MFP7

MFP9

MFP0

MFP1

MFP2

MFP3

MFP7

MFP0

MFP1

MFP2

MFP3

MFP7

MFP10

MFP0

Description

1

General purpose digital I/O pin.

EADC analog input channel 13.

SPI0 1st MOSI (Master Out, Slave In) pin.

SPI1 MOSI (Master Out, Slave In) pin.

EBI address/data bus bit 6.

EADC_CH13

SPI0_MOSI0

SPI1_MOSI

EBI_AD6

UART2_RXD

PB.6

I/O

A

Data receiver input pin for UART2.

General purpose digital I/O pin.

EADC analog input channel 14.

SPI0 1st MISO (Master In, Slave Out) pin.

SPI1 MISO (Master In, Slave Out) pin.

EBI address/data bus bit 5.

2

EADC_CH14

SPI0_MISO0

SPI1_MISO

EBI_AD5

PB.7

I/O

A

3

General purpose digital I/O pin.

EADC analog input channel 15.

SPI0 serial clock pin.

EADC_CH15

SPI0_CLK

SPI1_CLK

EBI_AD4

STADC

I/O

I

SPI1 serial clock pin

EBI address/data bus bit 4.

ADC external trigger input.

4

5

nRESET

External reset input: active LOW, with an internal pull-up.

Set this pin low reset to initial state.

PD.0

I/O

A

MFP0

MFP1

MFP3

MFP8

MFP0

MFP1

MFP2

MFP3

MFP6

General purpose digital I/O pin.

EADC analog input channel 6.

EADC_CH6

UART0_RXD

INT3

I

Data receiver input pin for UART0.

External interrupt3 input pin.

I

6

7

AV_SS

P

Ground pin for analog circuit.

PD.1

I/O

A

General purpose digital I/O pin.

EADC analog input channel 11.

PWM0 counter synchronous trigger input pin.

Data transmitter output pin for UART0.

Timer0event counter input / toggle output

EADC_CH11

PWM0_SYNC_IN

UART0_TXD

T0

I

O

I/O

Oct. 15, 2018

Page 20 of 117

Rev.1.00

M4521

Pin No.

Pin Name

EBI_nRD

PD.2

Type

MFP*

MFP7

MFP0

MFP1

MFP3

MFP6

MFP7

MFP8

MFP0

MFP1

MFP3

MFP6

MFP7

MFP8

MFP0

MFP1

MFP8

MFP0

MFP1

MFP0

MFP1

MFP0

MFP3

MFP4

MFP6

MFP7

MFP0

MFP1

MFP3

MFP0

MFP1

MFP3

MFP0

Description

O

EBI read enable output pin.

8

I/O

General purpose digital I/O pin.

ADC external trigger input.

STADC

T0_EXT

PWM0_BRAKE0

EBI_nWR

INT0

I

Timer0 external capture input

PWM0 break input 0

O

I

EBI write enable output pin.

External interrupt0 input pin.

9

PD.3

I/O

I

General purpose digital I/O pin.

Timer2 event counter input / toggle output

Timer1 external capture input

PWM0 break input 1

T2

T1_EXT

PWM0_BRAKE1

EBI_MCLK

INT1

I

O

I

EBI external clock output pin

External interrupt1 input pin.

10

11

V_BAT

Power supply by batteries for RTC and PF.0~PF.2.

General purpose digital I/O pin.

External 32.768 kHZ (low speed) crystal output pin.

External interrupt5 input pin.

PF.0

I/O

O

X32_OUT

INT5

I

12

13

14

PF.1

I/O

I

General purpose digital I/O pin.

External 32.768 kHZ (low speed) crystal input pin.

General purpose digital I/O pin.

TAMPER detector loop pin

X32_IN

PF.2

I/O

I

TAMPER

PD.7

General purpose digital I/O pin.

PWM0 counter synchronous trigger input pin.

Timer1 event counter input / toggle output

PWM0 output/capture input.

PWM0_SYNC_IN

T1

I/O

O

PWM0_CH5

EBI_nRD

PF.3

EBI read enable output pin.

15

16

I/O

O

General purpose digital I/O pin.

External 4~20 MHz (high speed) crystal output pin.

I2C1 clock pin.

XT1_OUT

I2C1_SCL

PF.4

I/O

I

General purpose digital I/O pin.

External 4~20 MHz (high speed) crystal input pin.

I2C1 data input/output pin.

XT1_IN

I2C1_SDA

V_SS

I/O

A

17

18

Ground pin for digital circuit.

LDO_CAP

A

LDO output pin.

Note: This pin needs to be connected with a 1uF

Oct. 15, 2018

Page 21 of 117

Rev.1.00

M4521

Pin No.

Pin Name

Type

MFP*

Description

capacitor.

19

PC.0

I/O

I

MFP0

MFP2

MFP3

MFP6

MFP7

MFP8

MFP9

MFP11

MFP0

MFP1

MFP3

MFP6

MFP7

MFP9

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP3

MFP4

MFP5

MFP6

General purpose digital I/O pin.

SPI1 serial clock pin.

SPI1_CLK

UART2_nCTS

PWM0_CH0

EBI_AD8

INT2

Clear to Send input pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 8.

External interrupt2 input pin.

Data transmitter output pin for UART3.

Timer3 external capture input.

General purpose digital I/O pin.

Clock Out

I/O

I

UART3_TXD

T3_EXT

O

I

20

PC.1

I/O

O

CLKO

UART2_nRTS

PWM0_CH1

EBI_AD9

UART3_RXD

PC.2

O

Request to Send output pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 9.

Data receiver input pin for UART3.

General purpose digital I/O pin.

SPI1 slave select pin.

I/O

I

21

22

23

24

SPI1_SS

UART2_TXD

PWM0_CH2

EBI_AD10

PC.3

O

Data transmitter output pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 10.

General purpose digital I/O pin.

SPI1 MOSI (Master Out, Slave In) pin.

Data receiver input pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 11.

General purpose digital I/O pin.

SPI1 MISO (Master In, Slave Out) pin.

I2C1 clock pin.

I/O

I

SPI1_MOSI

UART2_RXD

PWM0_CH3

EBI_AD11

PC.4

I/O

I

SPI1_MISO

I2C1_SCL

PWM0_CH4

EBI_AD12

PE.0

PWM0 output/capture input.

EBI address/data bus bit 12.

General purpose digital I/O pin.

I2C1 data input/output pin.

I2C1_SDA

T2_EXT

Timer2 external capture input

SmartCard card detect pin.

PWM0 output/capture input.

SC0_CD

I

PWM0_CH0

I/O

Oct. 15, 2018

Page 22 of 117

Rev.1.00

M4521

Pin No.

Pin Name

EBI_nCS1

INT4

Type

O

MFP*

MFP7

MFP8

MFP0

MFP1

MFP0

MFP1

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP0

MFP1

MFP2

MFP3

MFP4

MFP0

Description

EBI chip select 1 enable output pin.

External interrupt4 input pin.

General purpose digital I/O pin.

Serial wired debugger clock pin

General purpose digital I/O pin.

Serial wired debugger data pin

General purpose digital I/O pin.

SPI1 MISO (Master In, Slave Out) pin.

SPI0 1st MISO (Master In, Slave Out) pin.

Clear to Send input pin for UART1.

I2C0 SMBus SMBALTER# pin

SmartCard data pin.

I

25

26

27

PF.5

I/O

I

ICE_CLK

PF.6

I/O

I

ICE_DAT

PE.10

SPI1_MISO

SPI0_MISO0

UART1_nCTS

I2C0_SMBAL

SC0_DAT

UART3_TXD

I2C1_SCL

PE.11

O

I/O

O

Data transmitter output pin for UART3.

I2C1 clock pin.

I/O

O

28

General purpose digital I/O pin.

SPI1 MOSI (Master Out, Slave In) pin.

SPI0 1st MOSI (Master Out, Slave In) pin.

Request to Send output pin for UART1.

I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)

SmartCard clock pin.

SPI1_MOSI

SPI0_MOSI0

UART1_nRTS

I2C0_SMBSUS

SC0_CLK

UART3_RXD

I2C1_SDA

PE.12

O

I

Data receiver input pin for UART3.

I2C1 data input/output pin.

I/O

O

29

General purpose digital I/O pin.

SPI1 slave select pin

SPI1_SS

SPI0_SS

SPI0 slave select pin.

UART1_TXD

I2C0_SCL

PE.13

Data transmitter output pin for UART1.

I2C0 clock pin.

I/O

I

30

General purpose digital I/O pin.

SPI1 serial clock pin

SPI1_CLK

SPI0_CLK

UART1_RXD

I2C0_SDA

V_DDIO

SPI0 serial clock pin.

Data receiver input pin for UART1.

I2C0 data input/output pin.

I/O

A

31

32

Power supply for PE.10~PE.13.

Power supply from USB* host or HUB.

USB_VBUS

A

Oct. 15, 2018

Page 23 of 117

Rev.1.00

M4521

Pin No.

33

Pin Name

USB_D-

Type

MFP*

MFP0

Description

I

USB differential signal D-.

34

USB_D+

USB differential signal D+.

35

PF.7

I/O

A

General purpose digital I/O pin.

Internal power regulator output 3.3V decoupling pin.

36

USB_VDD33_CAP

Note: This pin needs to be connected with a 1uF

capacitor.

37

38

39

40

41

PA.3

I/O

I

MFP0

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

MFP1

MFP3

MFP5

MFP6

MFP7

MFP10

MFP0

MFP1

MFP3

MFP5

MFP6

MFP7

MFP8

MFP0

General purpose digital I/O pin.

Data receiver input pin for UART0.

Request to Send output pin for UART0.

I2C0 clock pin.

UART0_RXD

UART0_nRTS

I2C0_SCL

SC0_PWR

PWM1_CH2

EBI_AD3

O

I/O

O

SmartCard power pin.

I/O

O

PWM1 output/capture input.

EBI address/data bus bit 3.

General purpose digital I/O pin.

Data transmitter output pin for UART0.

Clear to Send input pin for UART0.

I2C0 data input/output pin.

PA.2

UART0_TXD

UART0_nCTS

I2C0_SDA

SC0_RST

PWM1_CH3

EBI_AD2

I

I/O

O

SmartCard reset pin.

I/O

O

PWM1 output/capture input.

EBI address/data bus bit 2.

General purpose digital I/O pin.

Request to Send output pin for UART1.

Data receiver input pin for UART1.

SmartCard data pin.

PA.1

UART1_nRTS

UART1_RXD

SC0_DAT

PWM1_CH4

EBI_AD1

I

I/O

I

PWM1 output/capture input.

EBI address/data bus bit 1.

ADC external trigger input.

STADC

PA.0

General purpose digital I/O pin.

Clear to Send input pin for UART1.

Data transmitter output pin for UART1.

SmartCard clock pin.

UART1_nCTS

UART1_TXD

SC0_CLK

PWM1_CH5

EBI_AD0

O

I/O

I

PWM1 output/capture input.

EBI address/data bus bit 0.

External interrupt0 input pin.

INT0

V_DD

A

Power supply for I/O ports and LDO source for internal

PLL and digital function.

Oct. 15, 2018

Page 24 of 117

Rev.1.00

M4521

Pin No.

42

Pin Name

AV_DD

Type

MFP*

MFP0

Description

A

I

Power supply for internal analog circuit.

43

V_REF

Voltage reference input for ADC.

Note: This pin needs to be connected with a 1uF

capacitor.

44

PB.0

I/O

A

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP8

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP9

MFP11

General purpose digital I/O pin.

EADC analog input.

EADC_CH0

SPI0_MOSI1

UART2_RXD

T2

I/O

I

SPI0 2nd MOSI (Master Out, Slave In) pin.

Data receiver input pin for UART2.

Timer2 event counter input / toggle output

EBI low byte write enable output pin.

External interrupt1 input pin.

I/O

O

EBI_nWRL

INT1

I

45

PB.1

I/O

A

General purpose digital I/O pin.

EADC analog input channel 1.

EADC_CH1

SPI0_MISO1

UART2_TXD

T3

I/O

O

SPI0 2nd MISO (Master In, Slave Out) pin.

Data transmitter output pin for UART2.

Timer3 event counter input / toggle output

SmartCard reset pin.

I/O

O

SC0_RST

PWM0_SYNC_OUT

EBI_nWRH

PB.2

O

PWM0 counter synchronous trigger output pin.

EBI high byte write enable output pin

General purpose digital I/O pin.

EADC analog input channel 2.

O

46

I/O

A

EADC_CH2

SPI0_CLK

SPI1_CLK

UART1_RXD

SC0_CD

I/O

I

SPI0 serial clock pin.

SPI1 serial clock pin

Data receiver input pin for UART1.

SmartCard card detect pin.

I

UART3_RXD

T2_EXT

I

Data receiver input pin for UART3.

Timer2 external capture input.

I

47

PB.3

I/O

A

General purpose digital I/O pin.

EADC analog input channel 3.

EADC_CH3

SPI0_MISO0

SPI1_MISO

UART1_TXD

EBI_ALE

I/O

O

SPI0 1st MISO (Master In, Slave Out) pin.

SPI1 MISO (Master In, Slave Out) pin.

Data transmitter output pin for UART1.

EBI address latch enable output pin.

Data transmitter output pin for UART3.

Timer0 external capture input.

O

UART3_TXD

T0_EXT

O

I

Oct. 15, 2018

Page 25 of 117

Rev.1.00

M4521

Pin No.

Pin Name

PB.4

Type

I/O

A

MFP*

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP9

MFP11

Description

48

General purpose digital I/O pin.

EADC analog input channel 4.

SPI0 slave select pin.

EADC_CH4

SPI0_SS

SPI1_SS

UART1_nCTS

EBI_AD7

UART2_TXD

T1_EXT

I/O

I

SPI1 slave select pin

Clear to Send input pin for UART1.

EBI address/data bus bit 7.

Data transmitter output pin for UART2.

Timer1 external capture input.

I/O

O

I

Oct. 15, 2018

Page 26 of 117

Rev.1.00

M4521

4.3.2

M4521 Series LQFP64 Pin Description

Corresponding Part Number: M4521SE6AE

MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)

PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.

PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.

Pin No.

Pin Name

PB.15

Type

I/O

A

MFP*

MFP0

MFP1

MFP7

MFP0

MFP1

MFP2

MFP3

MFP7

MFP9

MFP0

MFP1

MFP2

MFP3

MFP7

MFP0

MFP1

MFP2

MFP3

MFP7

MFP10

MFP0

Description

1

General purpose digital I/O pin.

EADC analog input channel 12.

EBI chip select 1 enable output pin.

General purpose digital I/O pin.

EADC analog input channel 13.

SPI0 1st MOSI (Master Out, Slave In) pin.

SPI1 MOSI (Master Out, Slave In) pin.

EBI address/data bus bit 6.

EADC_CH12

EBI_nCS1

PB.5

O

2

I/O

A

EADC_CH13

SPI0_MOSI0

SPI1_MOSI

EBI_AD6

UART2_RXD

PB.6

I/O

A

Data receiver input pin for UART2.

General purpose digital I/O pin.

EADC analog input channel 14.

SPI0 1st MISO (Master In, Slave Out) pin.

SPI1 MISO (Master In, Slave Out) pin.

EBI address/data bus bit 5.

3

EADC_CH14

SPI0_MISO0

SPI1_MISO

EBI_AD5

PB.7

I/O

A

4

General purpose digital I/O pin.

EADC analog input channel 15.

SPI0 serial clock pin.

EADC_CH15

SPI0_CLK

SPI1_CLK

EBI_AD4

STADC

I/O

I

SPI1 serial clock pin

EBI address/data bus bit 4.

ADC external trigger input.

5

6

nRESET

External reset input: active LOW, with an internal pull-up.

Set this pin low reset to initial state.

PD.0

I/O

A

MFP0

MFP1

MFP3

MFP8

MFP11

MFP0

MFP1

General purpose digital I/O pin.

EADC analog input channel 6.

Data receiver input pin for UART0.

External interrupt3 input pin.

EADC_CH6

UART0_RXD

INT3

I

T3

I/O

P

Timer3 event counter input / toggle output.

Ground pin for analog circuit.

7

8

AV_SS

PD.8

I/O

A

General purpose digital I/O pin.

EADC analog input channel 7.

EADC_CH7

Oct. 15, 2018

Page 27 of 117

Rev.1.00

M4521

Pin No.

Pin Name

EBI_nCS0

PD.9

Type

O

I/O

A

MFP*

MFP7

MFP0

MFP1

MFP7

MFP0

MFP1

MFP2

MFP3

MFP6

MFP7

MFP0

MFP1

MFP3

MFP6

MFP7

MFP8

MFP0

MFP1

MFP3

MFP6

MFP7

MFP8

MFP0

MFP1

MFP8

MFP0

MFP1

MFP0

MFP1

MFP0

MFP3

MFP6

MFP7

Description

EBI chip select 0 enable output pin.

General purpose digital I/O pin.

EADC analog input channel 10.

EBI address latch enable output pin.

General purpose digital I/O pin.

EADC analog input channel 11.

PWM0 counter synchronous trigger input pin.

Data transmitter output pin for UART0.

Timer0event counter input / toggle output

EBI read enable output pin.

9

EADC_CH10

EBI_ALE

PD.1

O

I/O

A

10

11

12

EADC_CH11

PWM0_SYNC_IN

UART0_TXD

T0

I

O

I/O

O

I/O

I

EBI_nRD

PD.2

General purpose digital I/O pin.

ADC external trigger input.

STADC

T0_EXT

PWM0_BRAKE0

EBI_nWR

INT0

I

Timer0 external capture input.

PWM0 break input 0

I

O

I

EBI write enable output pin.

External interrupt0 input pin.

PD.3

I/O

I

General purpose digital I/O pin.

Timer2 event counter input / toggle output

Timer1 external capture input

PWM0 break input 1

T2

T1_EXT

PWM0_BRAKE1

EBI_MCLK

INT1

I

O

I

EBI external clock output pin

External interrupt1 input pin.

13

14

V_BAT

Power supply by batteries for RTC and PF.0~PF.2.

General purpose digital I/O pin.

External 32.768 kHZ (low speed) crystal output pin.

External interrupt5 input pin.

PF.0

I/O

O

X32_OUT

INT5

I

15

16

17

PF.1

I/O

I

General purpose digital I/O pin.

External 32.768 kHZ (low speed) crystal input pin.

General purpose digital I/O pin.

TAMPER detector loop pin

X32_IN

PF.2

I/O

O

TAMPER

PD.12

General purpose digital I/O pin.

Data transmitter output pin for UART3.

PWM1 output/capture input.

UART3_TXD

PWM1_CH0

EBI_ADR16

I/O

O

EBI address bus bit 16.

Oct. 15, 2018

Page 28 of 117

Rev.1.00

M4521

Pin No.

Pin Name

PD.13

Type

I/O

I

MFP*

MFP0

MFP3

MFP6

MFP7

MFP0

MFP3

MFP6

MFP7

MFP0

MFP3

MFP6

MFP7

MFP0

MFP3

MFP4

MFP6

MFP7

MFP0

MFP1

MFP3

MFP0

MFP1

MFP3

MFP0

Description

18

General purpose digital I/O pin.

Data receiver input pin for UART3.

PWM1 output/capture input.

UART3_RXD

PWM1_CH1

EBI_ADR17

PD.14

I/O

O

EBI address bus bit 17.

19

20

21

I/O

I

General purpose digital I/O pin.

Clear to Send input pin for UART3.

PWM1 output/capture input.

UART3_nCTS

PWM1_CH2

EBI_ADR18

PD.15

I/O

O

EBI address bus bit 18.

I/O

O

General purpose digital I/O pin.

Request to Send output pin for UART3.

PWM1 output/capture input.

UART3_nRTS

PWM1_CH3

EBI_ADR19

PD.7

I/O

O

EBI address bus bit 19.

I/O

I

General purpose digital I/O pin.

PWM0 counter synchronous trigger input pin.

Timer1 event counter input / toggle output

PWM0 output/capture input.

PWM0_SYNC_IN

T1

I/O

O

PWM0_CH5

EBI_nRD

PF.3

EBI read enable output pin.

22

23

I/O

O

General purpose digital I/O pin.

External 4~20 MHz (high speed) crystal output pin.

I2C1 clock pin.

XT1_OUT

I2C1_SCL

PF.4

I/O

I

General purpose digital I/O pin.

External 4~20 MHz (high speed) crystal input pin.

I2C1 data input/output pin.

XT1_IN

I2C1_SDA

V_SS

I/O

A

24

25

Ground pin for digital circuit.

V_DD

A

Power supply for I/O ports and LDO source for internal

PLL and digital function.

26

27

LDO_CAP

A

MFP0

LDO output pin.

Note: This pin needs to be connected with a 1uF

capacitor.

PC.0

I/O

I

MFP0

MFP2

MFP3

MFP6

MFP7

MFP8

MFP9

General purpose digital I/O pin.

SPI1 serial clock pin.

SPI1_CLK

UART2_nCTS

PWM0_CH0

EBI_AD8

INT2

Clear to Send input pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 8.

I/O

I

External interrupt2 input pin.

Data transmitter output pin for UART3.

UART3_TXD

O

Oct. 15, 2018

Page 29 of 117

Rev.1.00

M4521

Pin No.

Pin Name

T3_EXT

Type

I

MFP*

MFP11

MFP0

MFP1

MFP3

MFP6

MFP7

MFP9

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP2

MFP3

MFP6

MFP7

MFP0

MFP6

MFP7

MFP0

MFP3

MFP6

MFP7

MFP9

MFP0

MFP3

MFP6

MFP7

Description

Timer3 external capture input.

General purpose digital I/O pin.

Clock Out

28

PC.1

I/O

O

CLKO

UART2_nRTS

PWM0_CH1

EBI_AD9

O

Request to Send output pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 9.

I/O

I

UART3_RXD

PC.2

Data receiver input pin for UART3.

General purpose digital I/O pin.

SPI1 slave select pin.

29

30

31

SPI1_SS

UART2_TXD

PWM0_CH2

EBI_AD10

PC.3

O

Data transmitter output pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 10.

General purpose digital I/O pin.

SPI1 MOSI (Master Out, Slave In) pin.

Data receiver input pin for UART2.

PWM0 output/capture input.

EBI address/data bus bit 11.

General purpose digital I/O pin.

SPI1 MISO (Master In, Slave Out) pin.

I2C1 clock pin.

I/O

I

SPI1_MOSI

UART2_RXD

PWM0_CH3

EBI_AD11

PC.4

I/O

O

SPI1_MISO

I2C1_SCL

PWM0_CH4

EBI_AD12

PC.5

PWM0 output/capture input.

EBI address/data bus bit 12.

General purpose digital I/O pin.

PWM0 output/capture input.

EBI address/data bus bit 13.

General purpose digital I/O pin.

I2C1 SMBus SMBALTER# pin

PWM1 output/capture input.

EBI address/data bus bit 14.

Data transmitter output pin for UART0.

General purpose digital I/O pin.

I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)

PWM1 output/capture input.

EBI address/data bus bit 15.

32

33

PWM0_CH5

EBI_AD13

PC.6

I2C1_SMBAL

PWM1_CH0

EBI_AD14

UART0_TXD

PC.7

I/O

O

34

I/O

O

I2C1_SMBSUS

PWM1_CH1

EBI_AD15

I/O

Oct. 15, 2018

Page 30 of 117

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M4521

Pin No.

35

Pin Name

UART0_RXD

PF.5

Type

I

MFP*

MFP9

MFP0

MFP1

MFP0

MFP1

MFP0

MFP1

MFP2

MFP4

MFP5

MFP9

MFP10

MFP11

MFP0

MFP1

MFP2

MFP4

MFP5

MFP10

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

Description

Data receiver input pin for UART0.

General purpose digital I/O pin.

Serial wired debugger clock pin

General purpose digital I/O pin.

Serial wired debugger data pin

General purpose digital I/O pin.

Data transmitter output pin for UART1.

SPI0 2nd MISO (Master In, Slave Out) pin.

I2C1 clock pin.

I/O

I

ICE_CLK

36

PF.6

I/O

O

ICE_DAT

PE.8

37

UART1_TXD

SPI0_MISO1

I2C1_SCL

SC0_PWR

CLKO

I/O

O

SmartCard power pin.

O

Clock Out

PWM0_BRAKE0

T1

I

PWM0 break input 0

I/O

I

Timer1 event counter input / toggle output

General purpose digital I/O pin.

Data receiver input pin for UART1.

SPI0 2nd MOSI (Master Out, Slave In) pin.

I2C1 data input/output pin.

38

PE.9

UART1_RXD

SPI0_MOSI1

I2C1_SDA

SC0_RST

PWM1_BRAKE1

T2

I/O

O

SmartCard reset pin.

I

PWM1 break input 1

I/O

I

Timer2 event counter input / toggle output

General purpose digital I/O pin.

SPI1 MISO (Master In, Slave Out) pin.

SPI0 1st MISO (Master In, Slave Out) pin.

Clear to Send input pin for UART1.

I2C0 SMBus SMBALTER# pin

SmartCard data pin.

39

PE.10

SPI1_MISO

SPI0_MISO0

UART1_nCTS

I2C0_SMBAL

SC0_DAT

UART3_TXD

I2C1_SCL

PE.11

O

I/O

O

Data transmitter output pin for UART3.

I2C1 clock pin.

I/O

O

40

General purpose digital I/O pin.

SPI1 MOSI (Master Out, Slave In) pin.

SPI0 1st MOSI (Master Out, Slave In) pin.

Request to Send output pin for UART1.

I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)

SmartCard clock pin.

SPI1_MOSI

SPI0_MOSI0

UART1_nRTS

I2C0_SMBSUS

SC0_CLK

O

Oct. 15, 2018

Page 31 of 117

Rev.1.00

M4521

Pin No.

Pin Name

UART3_RXD

I2C1_SDA

PE.12

Type

I

MFP*

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP0

MFP1

MFP2

MFP3

MFP4

MFP0

Description

Data receiver input pin for UART3.

I2C1 data input/output pin.

General purpose digital I/O pin.

SPI1 slave select pin

I/O

O

41

SPI1_SS

SPI0_SS

SPI0 slave select pin.

UART1_TXD

I2C0_SCL

PE.13

Data transmitter output pin for UART1.

I2C0 clock pin.

I/O

I

42

General purpose digital I/O pin.

SPI1 serial clock pin

SPI1_CLK

SPI0_CLK

UART1_RXD

I2C0_SDA

V_DDIO

SPI0 serial clock pin.

Data receiver input pin for UART1.

I2C0 data input/output pin.

Power supply for PE.8~PE.13.

Power supply from USB* host or HUB.

USB differential signal D-.

USB differential signal D+.

General purpose digital I/O pin.

Internal power regulator output 3.3V decoupling pin.

I/O

A

43

44

45

46

47

48

USB_VBUS

USB_D-

A

I

USB_D+

I

PF.7

I/O

A

USB_VDD33_CAP

Note: This pin needs to be connected with a 1uF

capacitor.

49

50

51

PA.3

I/O

I

MFP0

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

General purpose digital I/O pin.

Data receiver input pin for UART0.

Request to Send output pin for UART0.

I2C0 clock pin.

UART0_RXD

UART0_nRTS

I2C0_SCL

SC0_PWR

PWM1_CH2

EBI_AD3

O

I/O

O

SmartCard power pin.

I/O

O

PWM1 output/capture input.

EBI address/data bus bit 3.

General purpose digital I/O pin.

Data transmitter output pin for UART0.

Clear to Send input pin for UART0.

I2C0 data input/output pin.

SmartCard reset pin.

PA.2

UART0_TXD

UART0_nCTS

I2C0_SDA

SC0_RST

PWM1_CH3

EBI_AD2

I

I/O

O

I/O

PWM1 output/capture input.

EBI address/data bus bit 2.

General purpose digital I/O pin.

PA.1

Oct. 15, 2018

Page 32 of 117

Rev.1.00

M4521

Pin No.

Pin Name

UART1_nRTS

UART1_RXD

SC0_DAT

PWM1_CH4

EBI_AD1

STADC

Type

O

MFP*

MFP1

MFP3

MFP5

MFP6

MFP7

MFP10

MFP0

MFP1

MFP3

MFP5

MFP6

MFP7

MFP8

MFP0

Description

Request to Send output pin for UART1.

Data receiver input pin for UART1.

SmartCard data pin.

I

I/O

I

PWM1 output/capture input.

EBI address/data bus bit 1.

ADC external trigger input.

General purpose digital I/O pin.

Clear to Send input pin for UART1.

Data transmitter output pin for UART1.

SmartCard clock pin.

52

PA.0

UART1_nCTS

UART1_TXD

SC0_CLK

PWM1_CH5

EBI_AD0

INT0

O

I/O

I

PWM1 output/capture input.

EBI address/data bus bit 0.

External interrupt0 input pin.

Ground pin for digital circuit.

53

54

V_SS

A

V_DD

A

Power supply for I/O ports and LDO source for internal

PLL and digital function.

55

56

AV_DD

V_REF

A

I

MFP0

Power supply for internal analog circuit.

Voltage reference input for ADC.

Note: This pin needs to be connected with a 1uF

capacitor.

57

PB.0

I/O

A

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP8

MFP0

MFP1

MFP2

MFP3

MFP4

MFP5

MFP6

MFP7

MFP0

General purpose digital I/O pin.

EADC_CH0

SPI0_MOSI1

UART2_RXD

T2

EADC analog input.

I/O

I

SPI0 2nd MOSI (Master Out, Slave In) pin.

Data receiver input pin for UART2.

Timer2 event counter input / toggle output

EBI low byte write enable output pin.

External interrupt1 input pin.

I/O

O

EBI_nWRL

INT1

I

58

PB.1

I/O

A

General purpose digital I/O pin.

EADC_CH1

SPI0_MISO1

UART2_TXD

T3

EADC analog input channel 1.

I/O

O

SPI0 2nd MISO (Master In, Slave Out) pin.

Data transmitter output pin for UART2.

Timer3 event counter input / toggle output

SmartCard reset pin.

I/O

O

SC0_RST

PWM0_SYNC_OUT

EBI_nWRH

PB.2

O

PWM0 counter synchronous trigger output pin.

EBI high byte write enable output pin

General purpose digital I/O pin.

O

59

I/O

Oct. 15, 2018

Page 33 of 117

Rev.1.00

M4521

Pin No.

Pin Name

EADC_CH2

SPI0_CLK

SPI1_CLK

UART1_RXD

SC0_CD

Type

A

MFP*

MFP1

MFP2

MFP3

MFP4

MFP5

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP9

MFP11

MFP0

MFP1

MFP2

MFP3

MFP4

MFP7

MFP9

MFP11

MFP0

MFP1

MFP4

MFP6

MFP0

MFP1

MFP0

MFP1

Description

EADC analog input channel 2.

SPI0 serial clock pin.

I/O

I

SPI1 serial clock pin

Data receiver input pin for UART1.

SmartCard card detect pin.

I

UART3_RXD

T2_EXT

I

Data receiver input pin for UART3.

Timer2 external capture input.

General purpose digital I/O pin.

EADC analog input channel 3.

SPI0 1st MISO (Master In, Slave Out) pin.

SPI1 MISO (Master In, Slave Out) pin.

Data transmitter output pin for UART1.

EBI address latch enable output pin.

Data transmitter output pin for UART3.

Timer0 external capture input.

General purpose digital I/O pin.

EADC analog input channel 4.

SPI0 slave select pin.

I

60

PB.3

I/O

A

EADC_CH3

SPI0_MISO0

SPI1_MISO

UART1_TXD

EBI_ALE

I/O

O

UART3_TXD

T0_EXT

O

I

61

PB.4

I/O

A

EADC_CH4

SPI0_SS

I/O

I

SPI1_SS

SPI1 slave select pin

UART1_nCTS

EBI_AD7

Clear to Send input pin for UART1.

EBI address/data bus bit 7.

I/O

O

UART2_TXD

T1_EXT

Data transmitter output pin for UART2.

Timer1 external capture input.

General purpose digital I/O pin.

EADC analog input channel 5.

Request to Send output pin for UART1.

PWM0 output/capture input.

General purpose digital I/O pin.

EADC analog input channel 8.

General purpose digital I/O pin.

EADC analog input channel 9.

I

62

PB.8

I/O

A

EADC_CH5

UART1_nRTS

PWM0_CH2

PB.11

O

I/O

A

63

64

EADC_CH8

PB.12

I/O

A

EADC_CH9

Oct. 15, 2018

Page 34 of 117

Rev.1.00

M4521

4.3.3

GPIO Multi-function Pin Summary

MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)

PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.

PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.

Group

Pin Name

EADC_CH0

EADC_CH1

EADC_CH2

EADC_CH3

EADC_CH4

EADC_CH5

EADC_CH6

EADC_CH7

EADC_CH8

EADC_CH9

EADC_CH10

EADC_CH11

EADC_CH12

EADC_CH13

EADC_CH14

EADC_CH15

STADC

GPIO

PB.0

PB.1

PB.2

PB.3

PB.4

PB.8

PD.0

PD.8

PB.11

PB.12

PD.9

PD.1

PB.15

PB.5

PB.6

PB.7

PD.2

PB.7

PA.1

PC.1

PE.8

PA.0

PA.1

PA.2

PA.3

PB.7

PB.6

PB.5

PB.4

PC.0

PC.1

MFP*

MFP1

MFP10

MFP1

MFP9

MFP7

Type

A

Description

ADC0 analog input.

A

ADC1 analog input.

A

ADC2 analog input.

A

ADC3 analog input.

A

ADC4 analog input.

A

ADC5 analog input.

A

ADC6 analog input.

A

ADC7 analog input.

A

ADC8 analog input.

EADC

A

ADC9 analog input.

A

ADC10 analog input.

ADC11 analog input.

ADC12 analog input.

ADC13 analog input.

ADC14 analog input.

ADC15 analog input.

ADC external trigger input.

Clock Out

A

I

STADC

I

STADC

I

CLKO

O

CLKO

O

Clock Out

EBI_AD0

I/O

EBI address/data bus bit 0.

EBI address/data bus bit 1.

EBI address/data bus bit 2.

EBI address/data bus bit 3.

EBI address/data bus bit 4.

EBI address/data bus bit 5.

EBI address/data bus bit 6.

EBI address/data bus bit 7.

EBI address/data bus bit 8.

EBI address/data bus bit 9.

EBI_AD1

EBI_AD2

EBI_AD3

EBI_AD4

EBI

EBI_AD5

EBI_AD6

EBI_AD7

EBI_AD8

EBI_AD9

Oct. 15, 2018

Page 35 of 117

Rev.1.00

M4521

Group

Pin Name

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

EBI_AD15

EBI_ADR16

EBI_ADR17

EBI_ADR18

EBI_ADR19

EBI_ALE

GPIO

PC.2

PC.3

PC.4

PC.5

PC.6

PC.7

PD.12

PD.13

PD.14

PD.15

PD.9

PB.3

MFP*

MFP7

MFP4

Type

I/O

O

Description

EBI address/data bus bit 10.

EBI address/data bus bit 11.

EBI address/data bus bit 12.

EBI address/data bus bit 13.

EBI address/data bus bit 14.

EBI address/data bus bit 15.

EBI address bus bit 16.

O

EBI address bus bit 17.

O

EBI address bus bit 18.

O

EBI address bus bit 19.

O

EBI address latch enable output pin.

EBI external clock output pin

EBI chip select 0 enable output pin.

EBI chip select 1 enable output pin.

EBI read enable output pin.

EBI write enable output pin.

EBI high byte write enable output pin

EBI low byte write enable output pin.

I2C0 clock pin.

EBI_ALE

O

EBI_MCLK

EBI_nCS0

EBI_nCS1

EBI_nRD

PD.3

PD.8

PE.0

O

PB.15

PD.1

PD.2

PB.1

O

EBI_nWR

O

EBI_nWRH

EBI_nWRL

I2C0_SCL

I2C0_SDA

I2C0_SMBAL

I2C0_SMBSUS

O

PB.0

O

PE.12

PA.3

I/O

O

I2C0 clock pin.

PE.13

PA.2

I2C0 data input/output pin.

I2C0 SMBus SMBALTER# pin

I2C0

PE.10

PE.11

O

I2C0 SMBus SMBSUS# pin (PMBus

CONTROL pin)

I2C1_SCL

I2C1_SDA

PF.3

PC.4

PE.8

PE.10

PF.4

PE.0

PE.9

PE.11

MFP3

MFP4

MFP11

MFP3

MFP4

MFP11

I/O

I2C1 clock pin.

I2C1

I2C1 data input/output pin.

Oct. 15, 2018

Page 36 of 117

Rev.1.00

M4521

Group

Pin Name

GPIO

PC.6

PC.7

MFP*

MFP3

Type

O

Description

I2C1_SMBAL

I2C1_SMBSUS

I2C1 SMBus SMBALTER# pin

O

I2C1 SMBus SMBSUS# pin (PMBus

CONTROL pin)

ICE_CLK

PF.5

PF.6

PD.2

PA.0

PD.3

PB.0

PC.0

PD.0

PE.0

PF.0

PD.2

PE.8

PD.3

PC.0

PE.0

PC.1

PC.2

PB.8

PC.3

PC.4

PD.7

PC.5

PD.1

PD.7

PB.1

PE.9

PD.12

PC.6

PD.13

PC.7

PD.14

PA.3

MFP1

MFP8

MFP6

MFP10

MFP6

MFP2

MFP3

MFP6

MFP10

MFP6

I

I/O

I

Serial wired debugger clock pin

Serial wired debugger data pin

External interrupt0 input pin.

External interrupt1 input pin.

External interrupt2 input pin.

External interrupt3 input pin.

External interrupt4 input pin.

External interrupt5 input pin.

PWM0 break input 0

ICE

ICE_DAT

INT0

INT1

INT0

I

INT1

I

INT1

I

INT2

INT3

INT4

INT5

INT2

I

INT3

I

INT4

I

INT5

I

PWM0_BRAKE0

PWM0_BRAKE1

PWM0_CH0

PWM0_CH1

PWM0_CH2

PWM0_CH3

PWM0_CH4

PWM0_CH5

PWM0_SYNC_IN

PWM0_SYNC_OUT

PWM1_BRAKE1

PWM1_CH0

PWM1_CH1

PWM1_CH2

I

PWM0 break input 0

I

PWM0 break input 1

I/O

I

PWM0 output/capture input.

PWM0 counter synchronous trigger input pin.

PWM0 counter synchronous trigger output pin.

PWM1 break input 1

PWM0

I

O

I

I/O

PWM1 output/capture input.

PWM1

Oct. 15, 2018

Page 37 of 117

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M4521

Group

Pin Name

PWM1_CH3

PWM1_CH4

PWM1_CH5

SC0_CD

GPIO

PD.15

PA.2

PA.1

PA.0

PE.0

PB.2

PE.11

PA.0

PE.10

PA.1

PE.8

PA.3

PE.9

PA.2

PB.1

PB.7

PE.13

PB.2

PB.6

PE.10

PB.3

PE.8

PB.1

PB.5

PE.11

PE.9

PB.0

PE.12

PB.4

PB.7

PE.13

PB.2

PC.0

PB.6

MFP*

MFP6

MFP5

MFP2

MFP3

MFP1

MFP3

MFP2

MFP3

Type

I/O

I

Description

PWM1 output/capture input.

SmartCard card detect pin.

SmartCard clock pin.

SC0_CD

I

SC0_CLK

O

SC0_CLK

O

SmartCard clock pin.

SC0_DAT

I/O

O

SmartCard data pin.

SC0

SC0_DAT

SmartCard data pin.

SC0_PWR

SC0_RST

SmartCard power pin.

O

SmartCard power pin.

O

SmartCard reset pin.

SC0_RST

O

SmartCard reset pin.

SC0_RST

O

SmartCard reset pin.

SPI0_CLK

SPI0_MISO0

SPI0_MISO1

SPI0_MOSI0

SPI0_MOSI1

SPI0_SS

I/O

SPI0 serial clock pin.

SPI0 1st MISO (Master In, Slave Out) pin.

SPI0 2nd MISO (Master In, Slave Out) pin.

SPI0 1st MOSI (Master Out, Slave In) pin.

SPI0 2nd MOSI (Master Out, Slave In) pin.

SPI0 slave select pin.

SPI0

SPI0_SS

SPI0 slave select pin.

SPI1_CLK

SPI1_MISO

SPI1 serial clock pin

SPI1

SPI1 serial clock pin

SPI1 serial clock pin.

SPI1 MISO (Master In, Slave Out) pin.

Oct. 15, 2018

Page 38 of 117

Rev.1.00

M4521

Group

Pin Name

SPI1_MISO

SPI1_MOSI

SPI1_SS

TAMPER

T0

GPIO

PE.10

PB.3

PC.4

PB.5

PE.11

PC.3

PE.12

PC.2

PB.4

PF.2

PD.1

PD.2

PB.3

PD.7

PE.8

PD.3

PB.4

PD.3

PB.0

PE.9

PE.0

PB.2

PB.1

PD.0

PE.6

PC.0

PD.0

PA.3

PC.7

PD.1

PA.2

PC.6

PA.2

PA.3

MFP*

MFP1

MFP3

MFP2

MFP3

MFP1

MFP2

MFP1

MFP2

MFP3

MFP1

MFP6

MFP3

MFP11

MFP4

MFP11

MFP3

MFP11

MFP1

MFP4

MFP11

MFP4

MFP11

MFP4

MFP11

MFP3

MFP11

MFP3

MFP2

MFP9

MFP3

MFP2

MFP9

MFP3

Type

I/O

I

Description

SPI1 MISO (Master In, Slave Out) pin.

SPI1 MOSI (Master Out, Slave In) pin.

SPI1 slave select pin

SPI1 slave select pin.

SPI1 slave select pin

TAMPER

TMR0

TAMPER detector loop pin

Timer0event counter input / toggle output

Timer0 external capture input

T0_EXT

T1

I

Timer0 external capture input

I/O

I

Timer1 event counter input / toggle output

Timer1 external capture input

T1

TMR1

TMR2

TMR3

T1_EXT

T2

I

Timer1 external capture input

I/O

I

Timer2 event counter input / toggle output

Timer2 external capture input

T2

T2_EXT

T3

I

Timer2 external capture input

I/O

I

Timer3 event counter input / toggle output

Timer3 external capture input

T3

T3_EXT

UART0_RXD

UART0_TXD

UART0_nCTS

UART0_nRTS

I

Timer3 external capture input

I

Data receiver input pin for UART0.

Data transmitter output pin for UART0.

Clear to Send input pin for UART0.

Request to Send output pin for UART0.

I

O

UART0

O

I

O

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Group

Pin Name

GPIO

PE.9

PE.13

PA.1

PB.2

PE.8

PE.12

PA.0

PB.3

PE.10

PA.0

PB.4

PE.11

PA.1

PB.8

PC.3

PB.0

PB.5

PC.2

PB.1

PB.4

PC.0

PC.1

PD.13

PB.2

PE.11

PC.1

PD.12

PB.3

PE.10

PC.0

PD.14

PD.15

PF.1

MFP*

MFP1

MFP3

MFP4

MFP1

MFP3

MFP4

MFP3

MFP1

MFP4

MFP3

MFP1

MFP4

MFP3

MFP9

MFP3

MFP9

MFP3

MFP9

MFP3

MFP9

MFP3

MFP1

Type

Description

UART1_RXD

UART1_TXD

UART1_nCTS

UART1_nRTS

UART2_RXD

UART2_TXD

UART2_nCTS

UART2_nRTS

UART3_RXD

UART3_TXD

UART3_nCTS

UART3_nRTS

X32_IN

I

Data receiver input pin for UART1.

Data transmitter output pin for UART1.

Clear to Send input pin for UART1.

Request to Send output pin for UART1.

Data receiver input pin for UART2.

Data transmitter output pin for UART2.

Clear to Send input pin for UART2.

Request to Send output pin for UART2.

Data receiver input pin for UART3.

Data transmitter output pin for UART3.

Clear to Send input pin for UART3.

Request to Send output pin for UART3.

I

O

I

UART1

I

O

I

O

I

UART2

O

I

O

I

UART3

O

I

External 32.768 kHZ (low speed) crystal input

pin.

LXT

X32_OUT

PF.0

MFP1

O

External 32.768 kHZ (low speed) crystal output

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Group

Pin Name

GPIO

MFP*

Type

Description

pin.

XT1_IN

PF.4

PF.3

MFP1

I

External 4~20 MHz (high speed) crystal input

pin.

HXT

XT1_OUT

O

External 4~20 MHz (high speed) crystal output

pin.

Table 4.3-1 M4521 GPIO Multi-function Table

Oct. 15, 2018

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5 BLOCK DIAGRAM

5.1 NuMicro^®M4521 Series Block Diagram

Figure 5.1-1 NuMicro^®M4521 Series Block Diagram

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6 FUNCTIONAL DESCRIPTION

6.1 Arm^®Cortex^®-M4 Core

The Cortex^®-M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA

AHB-Lite interfaces for best parallel performance and includes an NVIC component. The

processor with optional hardware debug functionality can execute Thumb code and is compatible

with other Cortex-M profile processors. The profile supports two modes -Thread mode and

Handler mode. Handler mode is entered as a result of an exception. An exception return can only

be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of

an exception return. The Cortex^®-M4F is a processor with the same capability as the Cortex^®-M4

processor and includes floating point arithmetic functionality. The NuMicro^®M4521 family is

embedded with Cortex^®-M4F processor. Throughout this document, the name Cortex^®-M4 refers

to both Cortex^®-M4 and Cortex^®-M4F processors. Figure 6.1-1 shows the functional controller of

the processor.

Figure 6.1-1 Cortex^®-M4 Block Diagram

Cortex^®-M4 processor features:



A low gate count processor core, with low latency interrupt processing that has:

–

A subset of the Thumb instruction set, defined in the ARMv7-M Architecture

Reference Manual

–

Banked Stack Pointer (SP)

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–

Hardware integer divide instructions, SDIV and UDIV

Handler and Thread modes

Thumb and Debug states

Support for interruptible-continued instructions LDM, STM, PUSH, and POP for

low interrupt latency

–

Automatic processor state saving and restoration for low latency Interrupt

Service Routine (ISR) entry and exit

–

Support for ARMv6 big-endian byte-invariant or little-endian accesses

Support for ARMv6 unaligned accesses



Floating Point Unit (FPU) in the Cortex^®-M4F processor providing:

–

32-bit instructions for single-precision (C float) data-processing operations

Combined Multiply and Accumulate instructions for increased precision (Fused

MAC)

–

Hardware support for conversion, addition, subtraction, multiplication with

optional accumulate, division, and square-root

–

Hardware support for denormals and all IEEE rounding modes

32 dedicated 32-bit single precision registers, also addressable as 16 double-

word registers

–

Decoupled three stage pipeline



Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core

to achieve low latency interrupt processing. Features include:

–

External interrupts. Configurable from 1 to 240 (the NuMicro^®M4521 family

configured with 64 interrupts)

–

Bits of priority, configurable from 3 to 8

Dynamic reprioritization of interrupts

Priority grouping which enables selection of preempting interrupt levels and

nonpreempting interrupt levels

–

Support for tril-chaining and late arrival of interrupts, which enables back-to-back

interrupt processing without the overhead of state saving and restoration

between interrupts.

–

Processor state automatically saved on interrupt entry, and restored on interrupt

exit with on instruction overhead

Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode



Memory Protection Unit (MPU). An optional MPU for memory protection, including:

–

Eight memory regions

Sub Region Disable (SRD), enabling efficient use of memory regions

The ability to enable a background region that implements the default memory

map attributes



Low-cost debug solution that features:

–

Debug access to all memory and registers in the system, including access to

memory mapped devices, access to internal core registers when the core is

halted, and access to debug control registers even while SYSRESETn is

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asserted.

–

Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)

debug access

Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

and code patches

Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,

data tracing, and system profiling

Optional Instrumentation Trace Macrocell (ITM) for support of printf() style

debugging

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

(TPA), including Single Wire Output (SWO) mode

Optional Embedded Trace Macrocell (ETM) for instruction trace.



Bus interfaces:

–

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode,

Dcode, and System bus interfaces

–

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB)

interface

–

Bit-band support that includes atomic bit-band write and read operations.

Memory access alignment

Write buffer for buffering of write data

Exclusive access transfers for multiprocessor systems

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6.2 System Manager

6.2.1

Overview

The system manager provides the functions of system control, power modes, wake-up sources,

reset sources, system memory map, product ID and multi-function pin control. The following

sections describe the functions for



System Reset



Power Modes and Wake-up Sources

System Power Distribution



SRAM Memory Organization

System Control Register for Part Number ID, Chip Reset and Multi-function Pin

Control



System Timer (SysTick)

Nested Vectored Interrupt Controller (NVIC)

System Control register

6.2.2

System Reset

The system reset can be issued by one of the events listed below. These reset event flags can be

read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip

through peripheral reset signals. Software reset can trigger reset through control registers.



Hardware Reset Sources

–

Power-on Reset (POR)

Low level on the nRESET pin

Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)

Low Voltage Reset (LVR)

Brown-out Detector Reset (BOD Reset)

CPU Lockup Reset



Software Reset Sources

–

CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])

MCU Reset to reboot but keeping the booting setting from APROM or LDROM by

writing 1 to SYSRESETREQ (AIRCR[2])

–

CPU Reset for Cortex^®-M4 core Only by writing 1 to CPURST (SYS_IPRST0[1])

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Glitch Filter

36 us

nRESET

~50k ohm

@5v

POROFF(SYS_PORCTL[15:0])

Power-on

Reset

V_DD

LVREN(SYS_BODCTL[7])

Reset Pulse Width

3.2ms

Low Voltage

Reset

AV_DD

BODRSTEN(SYS_BODCTL[3])

Brown-out

Reset

WDT/WWDT

Reset

System Reset

Reset Pulse Width

64 WDT clocks

Reset Controller

CPU Lockup

Reset

Reset Pulse Width

2 system clocks

CHIP Reset

CHIPRST(SYS_IPRST0[0])

MCU Reset

SYSRSTREQ(AIRCR[2])

Reset Pulse Width

2 system clocks

Software Reset

CPU Reset

CPURST(SYS_IPRST0[1])

Figure 6.2-1 System Reset Sources

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There are a total of 9 reset sources in the NuMicro^®family. In general, CPU reset is used to reset

Cortex-M4 only; the other reset sources will reset Cortex-M4 and all peripherals. However, there

are small differences between each reset source and they are listed in Table 6.2-1.

Reset Sources

POR

0x001

nRESET

WDT

LVR

BOD

Lockup

CHIP

MCU

CPU

Register

SYS_RSTSTS

Bit 1 = 1

Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1

Bit 5 = 1 Bit 7 =

1

CHIPRST

0x0

-

(SYS_IPRST0[0])

BODEN

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

-

(SYS_BODCTL[0])

CONFIG0 CONFIG0 CONFIG0 CONFIG0

CONFIG0 CONFIG0 CONFIG0

BODVL

(SYS_BODCTL[2:1])

BODRSTEN

(SYS_BODCTL[3])

HXTEN

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

(CLK_PWRCTL[0])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

LXTEN

0x0

0x1

-

(CLK_PWRCTL[1])

WDTCKEN

0x1

(CLK_APBCLK0[0])

HCLKSEL

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

(CLK_CLKSEL0[2:0])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

WDTSEL

0x3

0x0

0x3

-

(CLK_CLKSEL1[1:0])

HXTSTB

-

(CLK_STATUS[0])

LXTSTB

-

(CLK_STATUS[1])

PLLSTB

-

(CLK_STATUS[2])

HIRCSTB

-

(CLK_STATUS[4])

CLKSFAIL

0x0

(CLK_STATUS[7])

RSTEN

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

CONFIG0

(WDT_CTL[1])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

WDTEN

(WDT_CTL[7])

WDT_CTL

0x0700

-

0x0700

-

except bit 1 and bit 7.

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WDT_ALTCTL

WWDT_RLDCNT

WWDT_CTL

0x0000

-

0x0000

0x3F0800

0x0000

0x3F

-

0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -

WWDT_STATUS

WWDT_CNT

0x0000

0x3F

0x0000

0x3F

0x0000

0x3F

0x0000

0x3F

0x0000

0x3F

-

BS

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

CONFIG0

(FMC_ISPCTL[1])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

FMC_DFBA

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

-

Reload

from

CONFIG1

-

CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1

CBS

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

Reload

from

CONFIG0

(FMC_ISPSTS[2:1])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

PGFF

0x0

-

0x0

-

0x0

-

(FMC_ISPSTS[5])

VECMAP

Reload

base

Reload

on base

Reload

base

CONFIG0

on base on base on base on

on

(FMC_ISPSTS[23:9])

CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0

Other

Peripheral Reset Value

-

Registers

FMC Registers

Reset Value

Note: ‘-‘ means that the value of register keeps original setting.

Table 6.2-1 Reset Value of Registers

6.2.2.1 nRESET Reset

The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an

asynchronous reset input pin and can be used to reset system at any time. When the nRESET

voltage is lower than 0.2 V_DDand the state keeps longer than 36 us (glitch filter), chip will be

reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above

0.7 V_DDand the state keeps longer than 36 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be

set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset

waveform.

nRESET

0.7 V_DD

36 us

0.2 V_DD

36 us

nRESET

Reset

Figure 6.2-2 nRESET Reset Waveform

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6.2.2.2 Power-on Reset (POR)

The Power-on reset (POR) is used to generate a stable system reset signal and forces the

system to be reset when power-on to avoid unexpected behavior of MCU. When applying the

power to MCU, the POR module will detect the rising voltage and generate reset signal to system

until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be

set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by

writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.

V_POR

0.1V

V_DD

Power-on

Reset

Figure 6.2-3 Power-on Reset (POR) Waveform

6.2.2.3 Low Voltage Reset (LVR)

If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN

(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR

function will be active. Then LVR function will detect AV_DDduring system operation. When the

AV_DDvoltage is lower than V_LVRand the state keeps longer than De-glitch time set by LVRDGSEL

(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until

the AV_DDvoltage rises above V_LVRand the state keeps longer than De-glitch time set by

LVRDGSEL (SYS_BODCTL[14:12]). The LVRF(SYS_RSTSTS[3]) will be set to 1 if the previous

reset source is LVR. The default setting of Low Voltage Reset is enabled without De-glitch

function. Figure 6.2-4 shows the Low Voltage Reset waveform.

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AV_DD

V_LVR

T₁

T₂

( < LVRDGSEL)

( =LVRDGSEL)

T₃

( =LVRDGSEL)

Low Voltage Reset

LVREN

200 us

Delay for LVR stable

Figure 6.2-4 Low Voltage Reset (LVR) Waveform

6.2.2.4 Brown-out Detector Reset (BOD Reset)

If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit

BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AV_DDduring system

operation. When the AV_DDvoltage is lower than V_BODand the state keeps longer than De-glitch

time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the

chip in reset state until the AV_DDvoltage rises above V_BODand the state keeps longer than De-

glitch time set by BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and

BODRSTEN is set by Flash controller user configuration register CBODEN (CONFIG0 [23]),

CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can determine the

initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector

waveform.

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AV_DD

V_BODH

V_BODL

Hysteresis

T₁

T₂

(< BODDGSEL)

(= BODDGSEL)

BODOUT

T₃

(= BODDGSEL)

BODRSTEN

Brown-out

Reset

Figure 6.2-5 Brown-out Detector (BOD) Waveform

6.2.2.5 Watchdog Timer Reset (WDT)

In most industrial applications, system reliability is very important. To automatically recover the

MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is

widely used to check if the system works fine. If the MCU is crashed or out of control, it may

cause the watchdog time-out. User may decide to enable system reset during watchdog time-out

to recover the system and take action for the system crash/out-of-control after reset.

Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a

watchdog reset and handle the failure of MCU after watchdog time-out reset by checking

WDTRF(SYS_RSTSTS[2]).

6.2.2.6 CPU Lockup Reset

CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives

immediate indication of seriously errant kernel software. This is the result of the CPU being locked

because of an unrecoverable exception following the activation of the processor’s built in system

state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored.

6.2.2.7 CPU Reset, CHIP Reset and MCU Reset

The CPU Reset means only Cortex^®-M4 core is reset and all other peripherals remain the same

status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset

signal.

The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and

BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the

CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.

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The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be

reloaded from CONFIG setting and keep its original software setting for booting from APROM or

LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.

6.2.3

Power Modes and Wake-up Sources

There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the

available clocks for each power mode.

Power Mode

Definition

Normal Mode

Idle Mode

Power-Down Mode

CPU is in active state

CPU is in sleep state

CPU is in sleep state and all

clocks stop except LXT and

LIRC. SRAM content retended.

Entry Condition

Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable

system reset released

and power down enable and

executes WFI instruction.

Wake-up Sources

N/A

All interrupts

RTC, WDT, I²C, Timer, UART,

BOD, GPIO and USBD

Available Clocks

After Wake-up

All

All except CPU clock

LXT and LIRC

N/A

CPU back to normal mode

Table 6.2-2 Power Mode Difference Table

System reset released

Normal Mode

CPU Clock ON

HXT, HIRC, LXT, LIRC, HCLK, PCLK ON

Flash ON

CPU executes WFI

Interrupts occur

1. SCR(SCB[2]) = 1

Wake-up events

occur

2. PD_EN(PWRCTL[7]) = 1 and

PDWTCPU(PWRCTL[8]) = 1

3. CPU executes WFI

Idle Mode

Power-down Mode

CPU Clock OFF

HXT, HIRC, HCLK, PCLK OFF

LXT, LIRC ON

HXT, HIRC, LXT, LIRC, HCLK, PCLK ON

Flash Halt

Figure 6.2-6 Power Mode State Machine

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1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.

2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.

3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.

4. If WDT clock source is selected as LIRC and LIRC is on.

5. If RTC clock source is selected as LXT and LXT is on.

Normal Mode

ON

Idle Mode

Power-Down Mode

Halt

HXT (4~20 MHz XTL)

ON

Halt

ON

HIRC (12/16 MHz OSC)

ON

Halt

LXT (32768 Hz XTL)

ON

ON/OFF¹

ON/OFF²

Halt

LIRC (10 kHz OSC)

PLL

ON

LDO

ON

CPU

ON

Halt

HCLK/PCLK

SRAM retention

FLASH

EBI

ON

Halt

ON

Halt

ON

Halt

GPIO

ON

Halt

PDMA

TIMER

PWM

ON

Halt

ON

ON/OFF³

Halt

ON

WDT

ON

ON/OFF⁴

Halt

WWDT

RTC

ON

ON/OFF⁵

Halt

UART

ON

SC

ON

Halt

I²C

ON

Halt

SPI

ON

Halt

USBD

EADC

ON

Halt

ON

Halt

Table 6.2-3 Clocks in Power Modes

Wake-up sources in Power-down mode:

RTC, WDT, I²C, Timer, UART, BOD, GPIO and USBD

After chip enters power down, the following wake-up sources can wake chip up to normal mode.

Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.

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*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter

Power-down mode.

Wake-Up

Wake-Up Condition

System Can Enter Power-Down Mode Again Condition*

Source

BOD

Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].

GPIO

GPIO Interrupt

Timer Interrupt

After software write 1 to clear the INTSRC[n] bit.

TIMER

After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF

(TIMERx_INTSTS[0]).

WDT

RTC

WDT Interrupt

Alarm Interrupt

After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).

After software writes 1 to clear ALMIF (RTC_INTSTS[0]).

After software writes 1 to clear TICKIF (RTC_INTSTS[1]).

Time Tick Interrupt

Snoop Detection Interrupt After software writes 1 to clear SNPDIF (RTC_INTSTS[2]).

UART

RX Data wake-up

nCTS wake-up

After software writes 1 to clear DATWKIF (UARTx_INTSTS[17]).

After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).

I²C

Falling edge in the I2C_SDA

or I2C_CLK

After software writes 1 to clear WKIF( I2C_WKSTS[0]).

After software writes 1 to clear BUSIF (USBD_INTSTS[0]).

USBD

Remote Wake-up

Table 6.2-4 Condition of Entering Power-down Mode Again

6.2.4

System Power Distribution

In this chip, power distribution is divided into five segments:



Analog power from AV_DDand AV_SSprovides the power for analog components

operation. The V_REFshould be connected with an external 1uF capacitor that should

be located close to the V_REFpin to avoid power noise for analog applications.

Digital power from V_DDand V_SSsupplies the power to the internal regulator which

provides a fixed 1.8 V power for digital operation and I/O pins.



USB transceiver power from V_BUSoffers the power for operating the USB transceiver.

RTC power from V_BATprovides the power for PF.0~PF.2, RTC and 80 bytes backup

registers.



A dedicated power from V_DDIOsupplies the power for PE.8~PE.13.

The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external

capacitor which should be located close to the corresponding pin. Analog power (AV_DD) should be

the same voltage level of the digital power (V_DD). Figure 6.2-7 shows the NuMicro^®M4521 series

power distribution.

Oct. 15, 2018

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32.768 kHz

crystal

oscillator

USB_D+

USB_D-

USB

Transceiver

IO Cell

Internal

Reference

Voltage

12-bit ADC

USB_VDD33_CAP

1uF

3.3V

AV_DD

AV_SS

1.8V

Brown-out

Detector

Low Voltage

Reset

RTC &

80 bytes

backup

register

V_BATto 1.8V

LDO

5V to 3.3V

LDO

V_BUS

Temperature

Sensor

SRAM

Flash

Digital Logic

IO Cell

PE.8~PE.13

1.8V

LDO_CAP

1uF

22.1184 MHz

10 kHz

PLL

POR18

HIRC

LIRC

Oscillator

V_DDIO

GPIO except

PF.0 ~PF.2 and

PE.8~PE.13

4~24 MHz

crystal

oscillator

XT1_OUT

XT1_IN

V_DDto 1.8V

LDO

Power On

Control

POR50

IO Cell

M4521 Power Distribution

Figure 6.2-7 NuMicro^®M4521 Series Power Distribution Diagram

Oct. 15, 2018

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6.2.5

System Memory Map

The NuMicro^®M4521 series provides 4G-byte addressing space. The memory locations assigned to

each on-chip controllers are shown in Table 6.2-5. The detailed register definition, memory space, and

programming will be described in the following sections for each on-chip peripheral. The M4521 series

only supports little-endian data format.

Address Space

Token

Controllers

Flash and SRAM Memory Space

0x0000_0000 – 0x0001_FFFF

0x0004_0000 – 0x0005_FFFF

0x0006_0000 – 0x0007_FFFF

0x2000_4000 – 0x2000_7FFF

0x2000_8000 – 0x2000_BFFF

0x2000_C000 – 0x2000_FFFF

0x6000_0000 – 0x6FFF_FFFF

FLASH_BA

Reserved

FLASH Memory Space (128KB)

Reserved

SRAM1_BA

Reserved

SRAM Memory Space

Reserved

EXTMEM_BA

External Memory Space for EBI Interface (256 MB)

Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)

0x4000_0000 – 0x4000_01FF

0x4000_0200 – 0x4000_02FF

0x4000_0300 – 0x4000_03FF

0x4000_4000 – 0x4000_4FFF

0x4000_8000 – 0x4000_8FFF

0x4000_9000 – 0x4000_9FFF

0x4000_B000 – 0x4000_BFFF

0x4000_C000 – 0x4000_CFFF

0x4000_D000 – 0x4000_DFFF

0x4001_0000 – 0x4001_0FFF

0x4001_9000 – 0x4001_9FFF

0x4003_0000 – 0x4003_0FFF

0x4003_1000 – 0x4003_1FFF

0x5000_8000 – 0x5000_FFFF

SYS_BA

CLK_BA

NMI_BA

System Control Registers

Clock Control Registers

NMI Control Registers

GPIO Control Registers

Peripheral DMA Control Registers

USB Host Control Registers

Reserved

GPIO_BA

PDMA_BA

UHC_BA

Reserved

FMC_BA

Reserved

EBI_BA

Flash Memory Control Registers

Reserved

External Bus Interface Control Registers

Reserved

CRC_BA

Reserved

CRC Generator Registers

Reserved

APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)

0x4004_0000 – 0x4004_0FFF

0x4004_1000 – 0x4004_1FFF

0x4004_3000 – 0x4004_3FFF

0x4004_4000 – 0x4004_4FFF

0x4004_5000 – 0x4004_5FFF

0x4004_6000 – 0x4004_6FFF

0x4004_7000 – 0x4004_7FFF

WDT_BA

RTC_BA

EADC_BA

Reserved

Watchdog Timer Control Registers

Real Time Clock (RTC) Control Register

Enhanced Analog-Digital-Converter (EADC) Control Registers

Reserved

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0x4004_8000 – 0x4004_8FFF

0x4004_9000 – 0x4004_9FFF

0x4004_D000 – 0x4004_DFFF

0x4005_0000 – 0x4005_0FFF

0x4005_1000 – 0x4005_1FFF

0x4005_8000 – 0x4005_8FFF

0x4005_9000 – 0x4005_9FFF

0x4005_C000 – 0x4005_CFFF

0x4005_D000 – 0x4005_DFFF

0x4006_0000 – 0x4006_0FFF

0x4006_1000 – 0x4006_1FFF

0x4006_2000 – 0x4006_2FFF

0x4006_3000 – 0x4006_3FFF

0x4007_0000 – 0x4007_0FFF

0x4007_1000 – 0x4007_1FFF

0x4007_2000 – 0x4007_2FFF

0x4007_3000 – 0x4007_3FFF

0x4007_4000 – 0x4007_4FFF

0x4007_5000 – 0x4007_5FFF

0x4008_0000 – 0x4008_0FFF

0x4008_1000 – 0x4008_1FFF

0x4008_2000 – 0x4008_2FFF

0x4008_3000 – 0x4008_3FFF

0x4008_4000 – 0x4008_4FFF

0x4009_0000 – 0x4009_0FFF

0x4009_1000 – 0x4009_1FFF

0x4009_2000 – 0x4009_2FFF

0x4009_3000 – 0x4009_3FFF

0x4009_4000 – 0x4009_4FFF

0x4009_5000 – 0x4009_5FFF

0x400A_0000 – 0x400A_0FFF

0x400A_1000 – 0x400A_1FFF

0x400B_0000 – 0x400B_0FFF

0x400B_1000 – 0x400B_1FFF

0x400B_0000 – 0x400B_0FFF

Reserved

TMR01_BA

TMR23_BA

PWM0_BA

PWM1_BA

Reserved

SPI0_BA

SPI1_BA

Reserved

UART0_BA

UART1_BA

UART2_BA

UART3_BA

Reserved

I2C0_BA

Reserved

Timer0/Timer1 Control Registers

Timer2/Timer3 Control Registers

PWM0 Control Registers

PWM1 Control Registers

Reserved

SPI0 Control Registers

SPI1 Control Registers

Reserved

UART0 Control Registers

UART1 Control Registers

UART2 Control Registers

UART3 Control Registers

Reserved

I²C0 Control Registers

I²C1 Control Registers

Reserved

I2C1_BA

Reserved

SC0_BA

Reserved

Smartcard Host 0 Control Registers

Reserved

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0x400B_1000 – 0x400B_1FFF

0x400C_0000 – 0x400C_0FFF

0x400E_0000 – 0x400E_0FFF

0x400E_2000 – 0x400E_2FFF

0x5008_0000 – 0x5008_0FFF

Reserved

USBD_BA

Reserved

USB Device Control Register

Reserved

System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)

0xE000_E010 – 0xE000_E0FF

0xE000_E100 – 0xE000_ECFF

0xE000_ED00 – 0xE000_ED8F

SCS_BA

System Timer Control Registers

External Interrupt Controller Control Registers

System Control Registers

Table 6.2-5 Address Space Assignments for On-Chip Controllers

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M4521

6.2.6

SRAM Memory Organization

The M4521 series supports embedded SRAM with total 32 KB size and the SRAM organization is

separated to two banks: SRAM bank0 and SRAM bank1. Each of these two banks has 16 KB

address space and can be accessed simultaneously.



Supports total 32 KB SRAM

Supports byte / half word / word write

Supports fixed 16 KB SRAM bank for independent access

Supports oversize response error

Supports remap address to 0x1000_0000

AHB interface

SRAM decoder

controller

SRAM bank0

SRAM bank1

AHB interface

SRAM decoder

controller

Figure 6.2-8 SRAM Block Diagram

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M4521

Figure 6.2-9 shows the M4521 series SRAM organization. There are two SRAM banks in M4521

and each bank is addressed to 16 KB. The bank0 address space is from 0x2000_0000 to

0x2000_3FFF. The bank1 address space is from 0x2000_4000 to 0x2000_7FFF. The address

between 0x2000_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if

CPU accesses these illegal memory addresses.

The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can read

SRAM bank0 through 0x2000_0000 to 0x2000_3FFF or 0x1000_0000 to 0x1000_3FFF, and read

SRAM bank1 through 0x2000_4000 to 0x2000_7FFF or 0x1000_4000 to 0x1000_7FFF.

0x3FFF_FFFF

Reserved

0x2000_8000

0x2000_7FFF

0x1000_7FFF

remapping

16 KB

SRAM bank1

0x2000_4000

0x2000_3FFF

0x1000_4000

0x1000_3FFF

remapping

16 KB

SRAM bank0

0x2000_0000

0x1000_0000

32 KB device

Figure 6.2-9 SRAM Memory Organization

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6.2.7

System Timer (SysTick)

The Cortex^®-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit

clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The

counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.

When system timer is enabled, it will count down from the value in the SysTick Current Value

Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value

Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks.

When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit

clears on reads.

The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to

zero before enabling the feature. This ensures the timer will count from the SYST_LOAD value

rather than an arbitrary value when it is enabled.

If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is

reloaded with this value. This mechanism can be used to disable the feature independently from

the timer enable bit.

For more detailed information, please refer to the “Arm^®Cortex^®-M4 Technical Reference

Manual” and “Arm^®v6-M Architecture Reference Manual”.

6.2.8

Nested Vectored Interrupt Controller (NVIC)

The NVIC and the processor core interface are closely coupled to enable low latency interrupt

processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of

the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access

the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user

mode if you enable the Configuration and Control Register. Any other user mode access causes a

bus fault. You can access all NVIC registers using byte, halfword, and word accesses unless

otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC

registers and system debug registers are little-endian regardless of the endianness state of the

processor.

The NVIC supports:



An implementation-defined number of interrupts, in the range 1-240 interrupts.

A programmable priority level of 0-15 for each interrupt; a higher level corresponds to

a lower priority, so level 0 is the highest interrupt priority.



Level and pulse detection of interrupt signals.

Dynamic reprioritization of interrupts.

Grouping of priority values into group priority and subpriority fields.

Interrupt tail-chaining.

An external Non Maskable Interrupt (NMI)

WIC with Ultra-low Power Sleep mode support

The processor automatically stacks its state on exception entry and unstacks this state on

exception exit, with no instruction overhead. This provides low latency exception handling.

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6.3 Clock Controller

6.3.1

Overview

The clock controller generates clocks for the whole chip, including system clocks and all

peripheral clocks. The clock controller also implements the power control function with the

individually clock ON/OFF control, clock source selection and a clock divider. The chip will not

enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and

Cortex^®-M4 core executes the WFI instruction. After that, chip enters Power-down mode and wait

for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the

clock controller turns off the 4~20 MHz external high speed crystal (HXT) and 22.1184 MHz

internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure

6.3-1 shows the clock generator and the overview of the clock source control.

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M4521

CPUCLK

HCLK

CPU

48 MHz

22.1184 MHz

CRC

EBI

111

011

010

001

000

22.1184

MHz

10 kHz

1/(HCLKDIV+1)

PLLFOUT

PDMA

32.768 kHz

4~24 MHz

4~24

MHz

PCLK0

PCLK1

I2C0

I2C1

32.768

kHz

CLK_CLKSEL0[2:0]

10 kHz

22.1184 MHz

1

0

22.1184 MHz

PLL FOUT

111

101

4~24 MHz

10 kHz

TMR 0

TMR 1

CLK_PLLCTL[19]

T0~T1

PCLK0

011

010

10 kHz

BOD

32.768 kHz

4~24 MHz

001

000

22.1184 MHz

FMC

USB

48 MHz

1

0

CLK_CLKSEL1 [10:8]

CLK_CLKSEL1[14:12]

1/(USBDIV+1)

PLLFOUT

CLK_CLKSEL0[8]

22.1184 MHz

10 kHz

PCLK1

111

101

1/(EADCDIV+1)

RTC

EADC

TMR 2

TMR 3

10 kHz

32.768 kHz

T2~T3

PCLK1

1

0

011

010

32.768 kHz

4~24 MHz

001

000

CLK_CLKSEL3[8]

22.1184 MHz

CLK_CLKSEL1[18:16]

CLK_CLKSEL1[22:20]

11

10

HCLK

Clock Output

32.768 kHz

4~24 MHz

01

00

22.1184 MHz

1/2

111

011

010

001

000

HCLK

CPUCLK

1

0

CLK_CLKSEL1[29:28]

22.1184 MHz

4~24 MHz

32.768 kHz

4~24 MHz

SysTick

11

10

SYST_CTRL[2]

PCLK0

PLLFOUT

SPI0

01

00

CLK_CLKSEL0[5:3]

4~24 MHz

PCLK0

1

0

CLK_CLKSEL2[3:2]

22.1184 MHz

PWM 0

PLLFOUT

11

10

CLK_CLKSEL2[0]

PCLK1

PLLFOUT

SPI1

01

00

PCLK1

4~24 MHz

1

0

PWM 1

PLLFOUT

CLK_CLKSEL2[5:4]

CLK_CLKSEL2[1]

22.1184 MHz

PCLK0

11

10

10 kHz

1/2048

11

10

01

1/(SC0DIV+1)

SC0

PLLFOUT

4~24 MHz

HCLK

WDT

01

00

32.768 kHz

CLK_CLKSEL1[1:0]

CLK_CLKSEL3[1:0]

10 kHz

22.1184 MHz

32.768 kHz

PLLFOUT

11

10

11

WWDT

HCLK

1/2048

10

01

00

1/(UARTDIV+1)

UART 0-3

CLK_CLKSEL1[31:30]

4~24 MHz

CLK_CLKSEL1[25:24]

Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.

Figure 6.3-1 Clock Generator Global View Diagram

Oct. 15, 2018

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6.3.2

Clock Generator

The clock generator consists of 6 clock sources, which are listed below:



32.768 kHz external low speed crystal oscillator (LXT)

4~20 MHz external high speed crystal oscillator (HXT)

Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected

from external 4~20 MHz external high speed crystal (HXT) or 22.1184 MHz internal

high speed oscillator (HIRC)



22.1184 MHz internal high speed RC oscillator (HIRC)

10 kHz internal low speed RC oscillator (LIRC)

48 MHz internal high speed RC oscillator (HIRC48M)

LXTEN (CLK_PWRCTL[1])

X32_IN

External 32.768

kHz Crystal

LXT

(LXT)

X32_OUT

HXTEN (CLK_PWRCTL[0])

HXT

XT1_IN

External 4~24

PLLSRC (CLK_PLLCTL[19])

MHz Crystal

(HXT)

XT1_OUT

0

1

PLL FOUT

PLL

HIRCEN (CLK_PWRCTL[2])

Internal

22.1184 MHz

Oscillator

(HIRC)

HIRC

LIRC

LIRCEN (CLK_PWRCTL[3])

Internal 10 kHz

Oscillator

(LIRC)

HIRC48MEN (CLK_PWRCTL[24])

Internal 48 MHz

Oscillator

HIRC48M

(HIRC48M)

Figure 6.3-2 Clock Generator Block Diagram

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M4521

6.3.3

System Clock and SysTick Clock

The system clock has 5 clock sources generated from clock generator block. The clock source

switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in

Figure 6.3-3.

HCLKSEL

(CLK_CLKSEL0[2:0])

HIRC

111

CPUCLK

LIRC

PLLFOUT

LXT

CPU

AHB

011

010

001

000

HCLK

PCLK0

PCLK1

11//((HHCCLLKK_DNIV++11) )

HCLKDIV

(CLK_CLKDIV0[3:0])

APB0

APB1

HXT

CPU in Power Down Mode

Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.

Figure 6.3-3 System Clock Block Diagram

There are two clock fail detectors to observe HXT and LXT clock source and they have individual

enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled

automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.

When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop

being detected on the following condition: system clock source comes from HXT or system clock

source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the

HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5])

is set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the

clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to

oscillate after re-enable action and user can switch system clock to HXT again.

The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.3-4.

Oct. 15, 2018

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M4521

Set HXTFDEN To enable

HXT clock detector

NO

HXTFIF = 1?

YES

System clock source =

“HXT” or “PLL with

HXT” ?

System clock keep

original clock

NO

YES

Switch system clock to

HIRC

Figure 6.3-4 HXT Stop Protect Procedure

The clock source of SysTick in Cortex^®-M4 core can use CPU clock or external clock

(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The

clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The

block diagram is shown in Figure 6.3-5.

STCLKSEL

(CLK_CLKSEL0[5:3])

HIRC

111

011

010

001

000

1/2

HCLK

HXT

LXT

STCLK

HXT

Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.

Figure 6.3-5 SysTick Clock Control Block Diagram

6.3.4

Peripherals Clock

The peripherals clock has different clock source switch setting, which depends on the different

peripheral. Please refer to the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 6.3.8.

Oct. 15, 2018

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M4521

6.3.5

Power-down Mode Clock

When entering Power-down mode, system clocks, some clock sources and some peripheral

clocks are disabled. Some clock sources and peripherals clock are still active in Power-down

mode.

For theses clocks, which still keep active, are listed below:



Clock Generator

–

10 kHz internal low speed RC oscillator (LIRC) clock

32.768 kHz external low speed crystal oscillator (LXT) clock



Peripherals Clock (When the modules adopt LXT or LIRC as clock source)

6.3.6

Clock Output

This device is equipped with a power-of-2 frequency divider which is composed by16 chained

divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one

multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided

clocks with the frequency from F_in/2¹to F_in/2¹⁶where F_inis input clock frequency to the clock

divider.

The output formula is F_out= F_in/2^(N+1), where F_inis the input clock frequency, F_outis the clock

divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).

When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When

writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock

reaches low state and stays in low state.

CLKOSEL (CLK_CLKSEL1[29:28])

CLKOCKEN (CLK_APBCLK0[6])

HIRC

11

HCLK

CLKO_CLK

10

01

00

LXT

HXT

Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.

Figure 6.3-6 Clock Source of Clock Output

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M4521

CLKOEN

(CLK_CLKOCTL[4])

Enable

FREQSEL

(CLK_CLKOCTL[3:0])

divide-by-2 counter

16 chained

divide-by-2 counter

DIV1EN

(CLK_CLKOCTL[5])

CLKO_CLK

1/2

1/2²

1/2³

…...

1/2¹⁵1/2¹⁶

CLK1HZEN

(CLK_CLKOCTL[6])

0000

0001

:

16 to 1

MUX

0

1

:

0

1

1110

CLKO

1111

RTCSEL(CLK_CLKSEL3[8])

LIRC

LXT

0

1

1 Hz clock from RTC

/32768

Figure 6.3-7 Clock Output Block Diagram

Oct. 15, 2018

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M4521

6.4 Flash Memeory Controller (FMC)

6.4.1

Overview

The M4521 series is equipped with 128 KB on-chip embedded Flash for application and

configurable Data Flash to store some application dependent data. A User Configuration block is

provided for system initiation. A 4 KB loader ROM (LDROM) is used for In-System-Programming

(ISP) function. A 4KB cache with zero wait cycle is used to improve Flash access performance.

This chip also supports In-Application-Programming (IAP) function, user switches the code

executing without the chip reset after the embedded Flash updated.

6.4.2

Features



Supports 128 KB application ROM (APROM).

Supports 4 KB loader ROM (LDROM).

Supports Data Flash with configurable memory size.

Supports 8 bytes User Configuration block to control system initiation.

Supports 2 KB page erase for all embedded Flash.

Supports 32-bit/64-bit and multi-word Flash programming function.

Supports fast Flash programming verification function.

Supports checksum calculation function.

Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update

embedded Flash memory.



Supports cache memory to improve Flash access performance and reduce power

consumption.

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M4521

6.5 External Bus Interface (EBI)

6.5.1

Overview

The M4521 series is equipped with an external bus interface (EBI) for external device used. To

save the connections between external device and the M4521, the EBI operates in address bus

and data bus multiplex mode. The EBI supports two chip selects that can connect two external

devices with different timing setting requirement.

6.5.2

Features



Supports address bus and data bus multiplex mode to save the address pins

Supports two chip selects with polarity control for each bank

Supports external accessible space up to 1 Mbytes (need 20-bit address width) for each

bank. Real addressable space size is dependent on package pin out



Supports variable external bus base clock (MCLK) which based on HCLK

Supports 8-bit or 16-bit data width for each chip select



Supports LCD interface i80 mode

Supports variable address latch enable time (tALE)



Supports variable data access time (tACC) and data access hold time (tAHD) for each chip

select



Supports configurable idle cycle for different access condition: Idle of Write command finish

(W2X) and Idle of Read-to-Read (R2R)

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M4521

6.6 General Purpose I/O (GPIO)

6.6.1

Overview

The M4521 series has up to 49 General Purpose I/O pins to be shared with other function pins

depending on the chip configuration. These 49 pins are arranged in 6 ports named as PA, PB,

PC, PD, PE and PF. Each of the 49 pins is independent and has the corresponding register bits to

control the pin mode function and data.

The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull

output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all

pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up

resistor which is about 110 k ~ 300 k for V_DDis from 5.0 V to 2.5 V.

6.6.2

Features



Four I/O modes:

–

Quasi-bidirectional mode

Push-Pull Output mode

Open-Drain Output mode

Input only with high impendence mode



TTL/Schmitt trigger input selectable

I/O pin can be configured as interrupt source with edge/level setting

Supports High Drive and High Slew Rate I/O mode

Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting

–

CIOIN = 0, all GPIO pins in Quasi-bidirectional mode after chip reset

CIOIN = 1, all GPIO pins in input mode after chip reset



I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode

Enabling the pin interrupt function will also enable the wake-up function

Supports 5V-tolerance function for following pins

–

PA.0 ~ PA.3, PC.0 ~ PC.7, PD.2 ~ PD.3, PD.7, PD.12 ~ PD.15, PE.0, PE.8 ~ PE.13,

PF.2, PF.5 ~ PF.7

Oct. 15, 2018

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M4521

6.7 PDMA Controller (PDMA)

6.7.1

Overview

The peripheral direct memory access (PDMA) controller is used to provide high-speed data

transfer. The PDMA controller can transfer data from one address to another without CPU

intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free

for other applications. The PDMA controller has a total of 8 channels and each channel can

perform transfer between memory and peripherals or between memory and memory.

6.7.2

Features



Supports 8 independently configurable channels

Supports selectable 2 level of priority (fixed priority or round-robin priority)

Supports transfer data width of 8, 16, and 32 bits

Supports source and destination address increment size can be byte, half-word, word or no

increment



Supports software and SPI, UART, ADC and PWM request

Supports Scatter-Gather mode to perform sophisticated transfer through the use of the

descriptor link list table



Supports single and burst transfer type

Supports time-out function for each channel

Oct. 15, 2018

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M4521

6.8 Timer Controller (TMR)

6.8.1

Overview

The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily

implement a timer control for applications. The timer can perform functions, such as frequency

measurement, delay timing, clock generation, and event counting by external input pins, and

interval measurement by external capture pins.

6.8.2

Features



Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter

Independent clock source for each timer

Provides one-shot, periodic, toggle-output and continuous counting operation modes

24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])

Supports event counting function

24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])

Supports external capture pin event for interval measurement

Supports external capture pin event to reset 24-bit up counter

Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated

Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM

and EADC function

Oct. 15, 2018

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6.9 PWM Generator and Capture Timer (PWM)

6.9.1

Overview

The M4521 series provides two PWM generators － PWM0 and PWM1. Each PWM supports 6

channels of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to

the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up, down and up-

down counter types. PWM using comparator compared with counter to generate events. These

events use to generate PWM pulse, interrupt and trigger signal for EADC to start conversion.

The PWM generator supports two standard PWM output modes: Independent mode and

Complementary mode, they have difference architecture. There are two output functions based

on standard output modes: Group function and Synchronous function. Group function can be

enabled under Independent mode or complementary mode. Synchronous function only enabled

under complementary mode. Complementary mode has two comparators to generate various

PWM pulse with 12-bit dead-time generator and another free trigger comparator to generate

trigger signal for EADC. For PWM output control unit, it supports polarity output, independent pin

mask and brake functions.

The PWM generator also supports input capture function. It supports latch PWM counter value to

corresponding register when input channel has a rising transition, falling transition or both

transition is happened. Capture function also support PDMA to transfer captured data to memory.

6.9.2

Features

6.9.2.1 PWM function features



Supports maximum clock frequency up to144MHz

Supports up to two PWM modules, each module provides 6 output channels.

Supports independent mode for PWM output/Capture input channel

Supports complementary mode for 3 complementary paired PWM output channel

–

Dead-time insertion with 12-bit resolution

Synchronous function for phase control

Two compared values during one period



Supports 12-bit pre-scalar from 1 to 4096

Supports 16-bit resolution PWM counter

–

Up, down and up/down counter operation type



Supports one-shot or auto-reload counter operation mode

Supports group function

Supports synchronous function

Supports mask function and tri-state enable for each PWM pin

Supports brake function

–

Brake source from pin, analog comparator and system safety events (clock failed,

Brown-out detection and CPU lockup).

–

Noise filter for brake source from pin

Edge detect brake source to control brake state until brake interrupt cleared

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M4521

–

Level detect brake source to auto recover function after brake condition removed



Supports interrupt on the following events:

–

PWM counter match zero, period value or compared value

Brake condition happened

Supports trigger EADC on the following events:

–

PWM counter match zero, period value or compared value

PWM counter match free trigger comparator compared value (only for EADC)

6.9.2.2 Capture Function Features



Supports up to 12 capture input channels with 16-bit resolution

Supports rising or falling capture condition

Supports input rising/falling capture interrupt

Supports rising/falling capture with counter reload option

Supports PDMA transfer function for PWM all channels

Oct. 15, 2018

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6.10 Watchdog Timer (WDT)

6.10.1 Overview

The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an

unknown state. This prevents system from hanging for an infinite period of time. Besides, this

Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.

6.10.2 Features



18-bit free running up counter for WDT time-out interval

Selectable time-out interval (2⁴~ 2¹⁸) and the time-out interval is 1.6 ms ~ 26.214s if

WDT_CLK = 10 kHz.



System kept in reset state for a period of (1 / WDT_CLK) * 63

Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset

delay period



Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in

Config0 register

Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or

LXT.

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6.11 Window Watchdog Timer (WWDT)

6.11.1 Overview

The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified

window period to prevent software run to uncontrollable status by any unpredictable condition.

6.11.2 Features



6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the

WWDT time-out window period flexible



Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of

WWDT counter

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6.12 Real Time Clock (RTC)

6.12.1 Overview

The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC

offers programmable time tick and alarm match interrupts. The data format of time and calendar

messages are expressed in BCD format. A digital frequency compensation feature is available to

compensate external crystal oscillator frequency accuracy.

The RTC controller also offers 80 bytes spare registers to store user’s important information. The

spare registers content is cleared when specified event on tamper pin is detected.

6.12.2 Features



Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in

RTC_CAL (year, month, day) for RTC time and calendar check

Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in

RTC_TALM and RTC_CALM

Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in

RTC_TAMSK and RTC_CAMSK



Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register

Supports Leap Year indication in RTC_LEAPYEAR register

Supports Day of the Week counter in RTC_WEEKDAY register

Frequency of RTC clock source compensate by RTC_FREQADJ register

All time and calendar message expressed in BCD format

Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,

1/16, 1/8, 1/4, 1/2 and 1 second



Supports RTC Time Tick and Alarm Match interrupt

Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is

generated



Supports 80 bytes spare registers and a snoop pin detection to clear the content of these

spare registers

Oct. 15, 2018

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6.13 UART Interface Controller (UART)

6.13.1 Overview

The M4521 series provides four channels of Universal Asynchronous Receiver/Transmitters

(UART). UART Controller performs Normal Speed UART and supports flow control function. The

UART Controller performs a serial-to-parallel conversion on data received from the peripheral and

a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel

supports ten types of interrupts. The UART controller also supports IrDA SIR, RS-485 and auto-

baud rate measuring function.

6.13.2 Features



Full-duplex asynchronous communications

Separates receive and transmit 16/16 bytes entry FIFO for data payloads

Supports hardware auto-flow control

Programmable receiver buffer trigger level

Supports programmable baud rate generator for each channel individually

Supports nCTS and RX data wake-up function

Supports 8-bit receiver buffer time-out detection function

Programmable transmitting data delay time between the last stop and the next start bit by

setting DLY (UART_TOUT [15:8])



Supports Auto-Baud Rate measurement

Supports break error, frame error, parity error and receive/transmit buffer overflow detection

function



Fully programmable serial-interface characteristics

–

Programmable number of data bit, 5-, 6-, 7-, 8- bit character

Programmable parity bit, even, odd, no parity or stick parity bit generation and detection

Programmable stop bit, 1, 1.5, or 2 stop bit generation



Supports IrDA SIR function mode

Supports for 3/16 bit duration for normal mode

Supports RS-485 function mode

–

Supports RS-485 9-bit mode

Supports hardware or software enables to program nRTS pin to control RS-485

transmission direction

UART Feature

UART0 / UART1

UART2 / UART3

SC_UART

FIFO

16 Bytes

4 Bytes

Auto Flow Control (CTS/RTS)

IrDA

√

-

RS-485 Function Mode

Auto-Flow Control

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nCTS Wake-up

√

-

RX Data Wake-up

Auto-Baud Rate Measurement

STOP Bit Length

Word Length 5, 6,7, 8 bits

Even / Odd Parity

Stick Bit

√

-

√

-

1, 1.5, 2 bit

1, 2 bit

√

-

√= Supported

Table 6.13-1 NuMicro^®M4521 Series UART Feature

Oct. 15, 2018

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6.14 Smart Card Host Interface (SC)

6.14.1 Overview

The Smart Card Interface controller (SC controller) is based on ISO/INTENC 7816-3 standard and

fully compliant with PC/SC Specifications. It also provides status of card insertion/removal.

6.14.2 Features



ISO-7816-3 T = 0, T = 1 compliant.

EMV2000 compliant

One ISO-7816-3 port

Separates receive/transmit 4 byte entry FIFO for data payloads.

Programmable transmission clock frequency.

Programmable receiver buffer trigger level.

Programmable guard time selection (11 ETU ~ 267 ETU).

A 24-bit and two 8-bit timers for Answer to Request (ATR) and waiting times processing.

Supports auto inverse convention function.

Supports transmitter and receiver error retry and error number limiting function.

Supports hardware activation sequence, hardware warm reset sequence and hardware

deactivation sequence process.

Supports hardware auto deactivation sequence when detected the card removal.

Supports UART mode

–

Full duplex, asynchronous communications.

Separates receiving / transmitting 4 bytes entry FIFO for data payloads.

Supports programmable baud rate generator.

Supports programmable receiver buffer trigger level.

Programmable transmitting data delay time between the last stop bit leaving the TX-

FIFO and the de-assertion by setting EGT (SC_EGT[7:0]).

–

Programmable even, odd or no parity bit generation and detection.

Programmable stop bit, 1- or 2- stop bit generation

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6.15 I²C Serial Interface Controller (I²C)

6.15.1 Overview

I²C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data

exchange between devices. The I²C standard is a true multi-master bus including collision

detection and arbitration that prevents data corruption if two or more masters attempt to control

the bus simultaneously.

There are two sets of I²C controller which supports Bus Management (System Management

(SM)/Power Management (PM) bus compatible) and Power-down wake-up function.

6.15.2 Features

The I²C bus uses two wires (SDA and SCL) to transfer information between devices connected to

the bus. The main features of the I²C bus include:



Supports up to two I²C ports

Master/Slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of serial data on

the bus



Serial clock synchronization allow devices with different bit rates to communicate via one

serial bus

Built-in 14-bit time-out counter requesting the I²C interrupt if the I²C bus hangs up and timer-

out counter overflows.



Programmable clocks allow for versatile rate control

Supports 7-bit addressing mode

Supports multiple address recognition ( four slave address with mask option)

Supports Bus Management (SM/PM compatible) function

Supports Power-down wake-up function

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6.16 Serial Peripheral Interface (SPI)

6.16.1 Overview

The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and

allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-

direction interface. The M4521 series contains up to three sets of SPI controllers performing a

serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial

conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a

master or a slave device.

SPI0 controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also

supports Dual and Quad I/O Transfer mode.

6.16.2 Features



Up to two sets of SPI controllers

Supports Master or Slave mode operation

Supports 2-bit Transfer mode

Supports Dual and Quad I/O Transfer mode for SPI0

Configurable bit length of a transaction word from 8 to 32-bit

Provides separate 4-/8-level depth transmit and receive FIFO buffers

Supports MSB first or LSB first transfer sequence

Supports Byte Reorder function

Supports PDMA transfer

Supports 3-Wire, no slave selection signal, bi-direction interface

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6.17 USB Device Controller (USBD)

6.17.1 Overview

There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is

compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/

Isochronous transfer types.

In this device controller, there are two main interfaces: the APB bus and USB bus which comes

from the USB PHY transceiver. For the APB bus, the CPU can program control registers through

it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is

necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User

needs to set the effective starting address of SRAM for each endpoint buffer through buffer

segmentation register (USBD_BUFSEGx).

There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT

endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are

implemented in this block. The block of “Endpoint Control” is also used to manage the data

sequential synchronization, endpoint state, current start address, transaction status, and data

buffer status for each endpoint.

There are four different interrupt events in this controller. They are the no-event-wake-up, device

plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend

and resume, etc. Any event will cause an interrupt, and users just need to check the related event

flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt

occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to

acknowledge what kind of event occurring in this endpoint.

A software-disconnect function is also supported for this USB controller. It is used to simulate the

disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB

controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.

After disable the SE0 bit, host will enumerate this USB device again.

For more information on the Universal Serial Bus, please refer to Universal Serial Bus

Specification Revision 1.1.

6.17.2 Features



Compliant with USB 2.0 Full-Speed specification

Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB and

BUS)



Supports Control/Bulk/Interrupt/Isochronous transfer types

Supports suspend function when no bus activity existing for 3 ms

Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and

maximum 512 bytes buffer size



Provides remote wake-up capability

Oct. 15, 2018

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6.18 USB 1.1 Host Controller (USBH)

6.18.1 Overview

This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller

Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to

manage the devices and data transfer of Universal Serial Bus (USB).

The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer

between system memory and USB bus, port power control and port over current detection.

The USBH is responsible for detecting the connect and disconnect of USB devices, managing

data transfer, collecting status and activity of USB bus, providing power control and detecting over

current of attached USB devices.

6.18.2 Features



Supports Universal Serial Bus (USB) Specification Revision 1.1.

Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.

Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.

Supports Control, Bulk, Interrupt and Isochronous transfers.

Supports an integrated Root Hub.

Supports a USB host port shared with USB device (OTG function).

Supports port power control and port over current detection.

Supports DMA for real-time data transfer.

Oct. 15, 2018

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6.19 CRC Controller (CRC)

6.19.1 Overview

The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable

polynomial settings.

6.19.2 Features



Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32

–

CRC-CCITT: X¹⁶+ X¹²+ X⁵+ 1

CRC-8: X⁸+ X²+ X + 1

CRC-16: X¹⁶+ X¹⁵+ X²+ 1

CRC-32: X³²+ X²⁶+ X²³+ X²²+ X¹⁶+ X¹²+ X¹¹+ X¹⁰+ X⁸+ X⁷+ X⁵+ X⁴+ X²+ X + 1



Programmable seed value

Supports programmable order reverse setting for input data and CRC checksum

Supports programmable 1’s complement setting for input data and CRC checksum

Supports 8/16/32-bit of data width

–

8-bit write mode: 1-AHB clock cycle operation

16-bit write mode: 2-AHB clock cycle operation

32-bit write mode: 4-AHB clock cycle operation



Supports using PDMA to write data to perform CRC operation

Oct. 15, 2018

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M4521

6.20 Enhanced 12-bit Analog-to-Digital Converter (EADC)

6.20.1 Overview

The M4521 series contains one 12-bit successive approximation analog-to-digital converter

(SAR A/D converter) with 16 external input channels and 3 internal channels. The A/D

converter can be started by software trigger, PWM0/1 triggers, timer0~3 overflow pulse

triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin

(STADC) input signal.

6.20.2 Features



Analog input voltage range: 0~V_REF(Max to AV_DD).

Reference voltage from V_REFpin or AV_DD.

12-bit resolution and 10-bit accuracy is guaranteed.

Up to 16 single-end analog external input channels or 8 pair differential analog input

channels.



3 internal channels, they are band-gap voltage (V_BG), temperature sensor (V_TEMP), and

Battery power (V_BAT

)



Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses.

Maximum ADC clock frequency is 20 MHz.

Up to 1 Msps conversion rate.

Configurable ADC internal sampling time.

Up to 19 sample modules

–

Each of sample module 0~15 which is configurable for ADC converter channel

EADC_CH0~15 and trigger source.

–

Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap

voltage, temperature sensor, and battery power (V_BAT).

–

Double buffer for sample module 0~3

Configurable sampling time for each sample module.

Conversion results are held in 19 data registers with valid and overrun indicators.



An A/D conversion can be started by:

–

Write 1 to SWTRGn (EADC_SWTRG[n], n = 0~18)

External pin STADC

Timer0~3 overflow pulse triggers

ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers

PWM triggers



Supports PDMA transfer

Oct. 15, 2018

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M4521

7 APPLICATION CIRCUIT

AVCC

V_REF

AV_DD

USB_VBUS

USB_D-

33R

USB

USB_D+

FB

DVCC

V_DD

V_DDIO

15k(HOST Only)

0.1uF

1uF

V_BAT

V_SS

Power

0.1uF

USB_VDD33_CAP

FB

1uF

AV_SS

DVCC

V_DD

SPI_SS

SPI_CLK

SPI_MISO

SPI_MOSI

CS

CLK

MISO

MOSI

V_DD

V_SS

ICE_DAT

ICE_CLK

nRESET

V_SS

SWD

Interface

M4521 Series

20p

SPI Device

XT1_IN

DVCC

4.7K

DVCC

4.7K

4~ 24 MHz

crystal

20p

XT1_OUT

X32_IN

CLK

DIO

I2C_SCL

I2C_SDA

V_DD

V_SS

I²C Device

Crystal

DVCC

32.768kHz

crystal

20p

X32_OUT

SC_PWR

DVCC

SC_RST

SC_CLK

SC_DAT

Smart Card Slot

Reset

Circuit

10K

SC_ Detect

nRST

10uF/10V

PC COM Port

RS 232 Transceiver

ROUT RIN

RXD

TXD

LDO CAP

_

UART

TIN

TOUT

LDO

1uF

Oct. 15, 2018

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M4521

8 ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings

Symbol

V_DD V_SS

V_IN

Parameter

Min

-0.3

V_SS- 0.3

4

Max

+7.0

V_DD+ 0.3

20

Unit

V

DC Power Supply

Input Voltage

V

1/t_CLCL

T_A

Oscillator Frequency

MHz

Operating Temperature

-40

+105

+150

120

℃

T_ST

Storage Temperature

-55

I_DD

Maximum Current into V_DD

-

mA

I_SS

Maximum Current out of V_SS

120

Maximum Current sunk by a I/O pin

Maximum Current sourced by a I/O pin

Maximum Current sunk by total I/O pins

Maximum Current sourced by total I/O pins

35

I_IO

100

Note: Exposure to conditions beyond those listed under absolute maximum ratings may

adversely affect the lift and reliability of the device.

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M4521

8.2 DC Electrical Characteristics

(V_DD- V_SS= 2.5 ~ 5.5 V, T_A= 25C)

SPECIFICATION

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Operation voltage

V_DD

2.5

-

5.5

V

V_DD= 2.5 V ~ 5.5 V up to 72 MHz

Power supply for

PE.8~PE.13

V_DDIO

1.8

2.5

-

5.5

0.3

V

RTC Operation

voltage for

PF.0~PF.2

V_BAT

Power Ground

V_SS/ AV_SS

-0.3

0

V

LDO Output Voltage

V_LDO

1.8

V_DD≥ 2.5 V

Band-gap Voltage

V_BG

1.175

1.21

1.225

0.3

V_DD= 2.5 V ~ 5.5 V, T_A= 25C

Allowed voltage

difference for V_DD

and AV_DD

V_DD-AV_DD

-0.3

0

V

All digital

modules

V_DD

HXT

HIRC

PLL

50

I_DD1

-

mA

Operating Current

Normal Run Mode

HCLK = 72 MHz

while(1){}

5.5V

12 MHz

X

V

X

25

48

22

I_DD2

I_DD3

I_DD4

-

mA

3.3V

12 MHz

X

V

X

executed from flash

43

25

41

22

17

8

I_DD5

I_DD6

I_DD7

I_DD8

I_DD9

I_DD10

I_DD11

-

mA

5.5V

3.3V

5.5V

3.3V

12 MHz

X

V

X

V

X

V

X

V

X

V

Operating Current

Normal Run Mode

HCLK = 50 MHz

while(1){}

executed from flash

Operating Current

Normal Run Mode

X

HCLK =22.1184

MHz

17

X

while(1){}

8

I_DD12

-

mA

3.3V

X

V

X

executed from flash

10

6

Operating Current

Normal Run Mode

HCLK = 12 MHz

while(1){}

I_DD13

I_DD14

I_DD15

I_DD16

I_DD17

-

mA

5.5V

3.3V

5.5V

12 MHz

X

V

X

V

X

V

8

executed from flash

4

3

Operating Current

Oct. 15, 2018

Page 91 of 117

Rev.1.00

M4521

SPECIFICATION

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Normal Run Mode

HCLK =4 MHz

while(1){}

2

3

2

I_DD18

I_DD19

I_DD20

-

mA

5.5V

3.3V

12 MHz

X

V

X

executed from flash

LXT

All digital

modules

V_DD

HIRC

PLL

(kHz)

146

I_DD21

-

uA

Operating Current

HCLK = 32.768 kHz

while(1){}

5.5V

32.768

X

V

X

134

uA

I_DD22

I_DD23

I_DD24

executed from flash

133

121

3.3V

32.768

X

V

X

-

HXT

/LXT

LIRC

(kHz)

All digital

modules

V_DD

PLL

Operating Current

Normal Run Mode

HCLK = 10 kHz

while(1){}

131

I_DD25

μA

5.5V

3.3V

X

10

X

V

X

V

X

128

118

115

I_DD26

I_DD27

I_DD28

-

μA

Executed from

Flash

Operating Current

Idle Mode

All digital

modules

V_DD

HXT

HIRC

PLL

30

I_IDLE1

-

mA

HCLK = 72 MHz

5.5V

3.3V

5.5V

3.3V

5.5V

3.3V

5.5V

12 MHz

X

V

X

V

X

V

X

V

X

V

X

V

X

V

X

V

X

V

X

10

28

7

I_IDLE2

I_IDLE3

I_IDLE4

I_IDLE5

I_IDLE6

I_IDLE7

I_IDLE8

I_IDLE9

I_IDLE10

I_IDLE11

I_IDLE12

I_IDLE13

I_IDLE14

-

mA

32

10

29

8

Operating Current

Idle Mode

HCLK = 50 MHz

11

2

Operating Current

Idle Mode

X

HCLK =22.1184

MHz

10

2

X

7

Operating Current

Idle Mode

12 MHz

3

HCLK =12 MHz

5

2

I_IDLE15

I_IDLE16

-

mA

3.3V

12 MHz

X

V

X

Oct. 15, 2018

Page 92 of 117

Rev.1.00

M4521

SPECIFICATION

Parameter

Symbol

Test Conditions

Min.

Typ.

2.2

Max.

Unit

Operating Current

Idle Mode

I_IDLE17

I_IDLE18

I_IDLE19

I_IDLE20

-

mA

5.5V

12 MHz

X

V

X

1.1

HCLK =4 MHz

1.8

0.6

-

mA

3.3V

12 MHz

X

V

X

Operating Current

Idle Mode

LXT

All digital

modules

V_DD

HIRC

PLL

(kHz)

136

I_IDLE21

-

uA

32.768 kHz

5.5V

32.768

X

V

X

126

123

114

I_IDLE22

I_IDLE23

I_IDLE24

uA

3.3V

32.768

X

V

X

Operating Current

Idle Mode

HXT

/LXT

LIRC

(kHz)

All digital

modules

V_DD

PLL

128

I_IDLE25

-

uA

at 10 kHz

5.5V

3.3V

X

10

X

V

X

V

X

125

115

112

I_IDLE26

I_IDLE27

I_IDLE28

-

μA

Standby Current

LXT

HXT/HI

RC/PLL

RAM

retension

V_DD

RTC

Power-down Mode

(Deep Sleep Mode)

(kHz)

21.08

I_PWD1

A

5.5V

X

10

X

V

22.18

23.21

I_PWD2

I_PWD3

A

32.768

10 &

32.768

23.23

I_PWD4

5.5V

X

V

A

19.38

20.44

21.50

I_PWD5

I_PWD6

I_PWD7

3.3V

X

10

X

V

A

32.768

10 &

32.768

21.55

2.01

I_PWD8

I_VBAT

I_IN

3.3V

X

V

A

V_BAT= 5.0 V, 32.768 kHz external low speed crystal

oscillator (LXT), RTC ON and V_DD/AV_DDpower

domain OFF.

uA

RTC Operating

Current

V_BAT= 3.0 V, 32.768 kHz external low speed crystal

oscillator (LXT), RTC ON and V_DD/AV_DDpower

domain OFF.

1.91

-45

uA

Input Current at

/RESET^[1]

-55

-30

V_DD= 3.3V, V_IN= 0.45V

A

Oct. 15, 2018

Page 93 of 117

Rev.1.00

M4521

SPECIFICATION

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Logic 0 Input

Current (Quasi-

bidirectional mode)

I_IL

-

-67

-75

V_DD= V_DDIO= V_BAT= 5.5 V, V_IN= 0V

A

Logic 1 to 0

Transition Current

(Quasi-bidirectional

mode) [*3]

I_TL

-

-610

-650

V_DD= V_DDIO= V_BAT=5.5 V, V_IN= 2.0V

A

V_DD= V_DDIO= V_BAT=5.5 V, 0 < V_IN< V_DD

Input Leakage

Current

I_LK

-1

-

+1

A

Open-drain or input only mode

-0.3

-

0.8

0.6

V_DD= V_DDIO= V_BAT= 4.5 V

V_DD= V_DDIO= V_BAT= 2.5 V

Input Low Voltage

(TTL input)

V_IL1

V

Input Low Voltage

(TTL input for PE8

~ PE13)

V_DD= V_BAT= 2.5 ~ 5.5 V

V_IL2

-0.3

-

0.3

V

V_DDIO= 1.8 V

V_DD

+

2.0

1.5

-

V_DD= V_DDIO= V_BAT= 5.5 V

V_DD= V_DDIO= V_BAT= 3.0 V

0.3

Input High Voltage

(TTL input)

V_IH1

V_DD

+

0.3

Input High Voltage

(TTL input for PE8

~ PE13)

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO

0.3

+

V_IH2

V_HY

V_IL3

1.0

-

V_DDIO= 1.8 V

Hysteresis voltage of

PA, PB, PC, PD,PE,

PF (Schmitt input)

0.2V_DD

V

0

-

0.8

0.4

V

V_DD= 4.5 V

V_DD= 2.5 V

Input Low Voltage

XT1[*2]

V_DD

0.3

+

3.5

-

V

V_DD= 5.5 V

V_DD= 3.0 V

Input High Voltage

XT1[*2]

V_IH3

V_DD

0.3

+

2.4

0.6

0

X32 Output Pin

V_XOUT

0.9

V

Input Low Voltage

X32I[*4]

V_XOUT-

0.3

V_IL4

-

V

Input High Voltage

X32I[*4]

V_XOUT

+0.3

V_IH4

1.8

V

Negative going

threshold

V_IL5

-0.3

-

0.2 V_DD

V

(Schmitt input),

nRST

Positive going

threshold

V_DD

+

V_IH5

0.7 V_DD

V

0.3

(Schmitt input),

nRST

Internal nRESET

pin pull up resistor

R_RST

40

150

kΩ

Oct. 15, 2018

Page 94 of 117

Rev.1.00

M4521

SPECIFICATION

Parameter

Symbol

V_IL6

Test Conditions

V_DD= V_DDIO= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 1.8 V ~ 5.5V

Min.

Typ.

Max.

Unit

Input Low Voltage

(Schmitt input)

-0.3

-

0.3 V_DD

V

Input Low Voltage

0.3

V_DDIO

V_IL7

-0.3

-

V

(Schmitt input for

PE8~ PE13)

Input High Voltage

(Schmitt input)

V_DD+

0.3

V_IH6

0.7 V_DD

V_DD= V_DDIO= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 1.8 V ~ 5.5V

Input High Voltage

0.7

V_DDIO

0.3

+

V_IH7

(Schmitt input for

PE8~ PE13)

Source Current

(Quasi-bidirectional

Mode)

I_SR11

I_SR12

I_SR13

-300

-50

-400

-80

-

V_DD= V_DDIO= V_BAT= 4.5 V, V_S= 2.4 V

V_DD= V_DDIO= V_BAT= 2.7 V, V_S= 2.2 V

V_DD= V_DDIO= V_BAT= 2.5 V, V_S= 2.0 V

A

-40

-73

Source Current

(Quasi-bidirectional

Mode for PE8~

PE13)

V_DD= V_BAT= 2.5 ~ 5.5 V

I_SR14

-11

-19

A

V_DDIO= 1.8 V, V_S= 1.6 V

Source Current

(Push-pull Mode)

I_SR21

I_SR22

I_SR23

-20

-3

-26

-5.2

-5

-

mA

V_DD= V_DDIO= V_BAT= 4.5 V, V_S= 2.4 V

V_DD= V_DDIO= V_BAT= 2.7 V, V_S= 2.2 V

V_DD= V_DDIO= V_BAT= 2.5 V, V_S= 2.0 V

-2.5

Source Current

(Set IO as Push-pull

Mode and basic

driving strength

V_DD= V_BAT= 2.5 ~ 5.5 V

I_SR24

-1

-1.5

mA

V_DDIO= 1.8 V, V_S= 1.6 V

Only for

PE8~PE13)

Source Current

V_DD= V_BAT= 2.5 ~ 5.5 V

I_SR31

I_SR32

I_SR33

I_SR34

-28

-5.3

-4.9

-1.5

-47

-8.8

-8.1

-2.5

-

mA

(Set IO as Push-pull

Mode and high

driving strength

V_DDIO= 4.5 V, V_S= 2.4 V

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 2.7 V, V_S= 2.2 V

Only for

PE8~PE13)

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 2.5 V, V_S= 2.0 V

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 1.8 V, V_S= 1.6 V

Sink Current

I_SK11

I_SK12

I_SK13

10

6

17

11

10

-

mA

V_DD= V_DDIO= V_BAT= 4.5 V, V_S= 0.45 V

V_DD= V_DDIO= V_BAT= 2.7 V, V_S= 0.45 V

V_DD= V_DDIO= V_BAT= 2.5 V, V_S= 0.45 V

(Quasi-bidirectional,

Open-Drain and

Push-pull Mode)

5

Sink Current

V_DD= V_BAT= 2.5 ~ 5.5 V

I_SK14

3.6

6

mA

(Only for

PE8~PE13)

V_DDIO= 1.8 V, V_S= 0.45 V

Oct. 15, 2018

Page 95 of 117

Rev.1.00

M4521

SPECIFICATION

Parameter

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Sink Current

V_DD= V_BAT= 2.5 ~ 5.5 V

I_SK21

I_SK22

I_SK23

I_SK24

14.7

24.5

mA

(Set IO as high

driving strength

V_DDIO= 4.5 V, V_S= 0.45 V

V_DD= V_BAT= 2.5 ~ 5.5 V

Only for

PE8~PE13)

9.2

8.5

5.4

15.3

14.1

9

mA

V_DDIO= 2.7 V, V_S= 0.45 V

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 2.5 V, V_S= 0.45 V

V_DD= V_BAT= 2.5 ~ 5.5 V

V_DDIO= 1.8 V, V_S= 0.45 V

Notes:

1. nRESET pin is a Schmitt trigger input.

2. XT1_IN is a CMOS input.

3. All pins can source a transition current when they are being externally driven from 1 to 0. In the

condition of V_DD=5.5V, the transition current reaches its maximum value when V_INapproximates to

2V.

4. If X32I is as external clock input, the input high voltage should be lower than 1.8V to avoid chip

damage.

8.2.1 On-chip peripheral current consumption

ALL GPIO pins are in push pull mode, output high.



LDO = 1.8V

The typical values for TA= 25 °C and V_DD= AV_DD= 3.3 V unless otherwise specified.

When the peripherals are enabled HCLK is the system clock, f_HCLK= 72 MHz, f_{PCLK0, 1}= f_HCLK/2.

Peripheral

Unit

I_DD

PDMA0 ON

ISP ON

EBI ON

USBH ON

CRC ON

FMC ON

1.026

0.000

0.343

1.488

0.220

0.745

0.433

0.417

0.568

0.578

0.486

0.507

0.086

0.428

0.357

1.154

0.924

1.556

1.527

1.634

1.549

1.634

0.964

WDT ON

RTC ON

TMR0 ON

TMR1 ON

TMR2 ON

TMR3 ON

CLKO ON

I2C0 ON

I2C1 ON

SPI0 ON

SPI1 ON

UART0 ON

UART1 ON

UART2 ON

UART3 ON

USBDC ON

EADC ON

uA

Oct. 15, 2018

Page 96 of 117

Rev.1.00

M4521

SC0 ON

PWM0 ON

PWM1 ON

1.243

1.850

1.640

Note: Guaranteed by characterization results, not tested in production

Oct. 15, 2018

Page 97 of 117

Rev.1.00

M4521

8.3 AC Electrical Characteristics

8.3.1 External 4~20 MHz High Speed Crystal (HXT) Input Clock

t_CLCL

t_CLCH

90%

10%

V_IH

t_CLCX

V_IL

t_CHCL

t_CHCX

Note: Duty cycle is 50%.

Symbol

t_CHCX

t_CLCX

t_CLCH

t_CHCL

V_IH

Parameter

Min

Typ

Max

Unit

ns

V

Test Conditions

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

Input High Voltage

Input Low Voltage

10

-

10

2

15

2

0.7V_DD

0

15

V_DD

0.3V_DD

V_IL

V

8.3.2 External 4~20 MHz High Speed Crystal (HXT) Oscillator

Symbol

V_HXT

Parameter

Operation Voltage

Temperature

Min.

2.5

-40

-

Typ.

Max

5.5

105

-

Unit

V

Test Conditions

-

T_A

℃

-

12 MHz, V_DD= 5.5V

12 MHz, V_DD= 3.3V

-

2

mA

MHz

I_HXT

Operating Current

Clock Frequency

-

0.8

-

f_HXT

4

20

8.3.2.1 Typical Crystal Application Circuits

Crystal

C1

10~20 pF

C2

4 MHz ~ 20 MHz

10~20 pF

Oct. 15, 2018

Page 98 of 117

Rev.1.00

M4521

XTAL1

XTAL2

4~20 MHz

Crystal

C1

C2

Vss

Figure 8.3-1 Typical Crystal Application Circuit

8.3.3 22.1184 MHz Internal High Speed RC Oscillator (HIRC)

Symbol

Parameter

Supply Voltage

Center Frequency

Min

1.62

-

Typ

1.8

Max

Unit

V

Test Conditions

V_HRC

1.98

-

22.1184

-

MHz

%

-

T_A= 25 ℃, V_DD= 5 V

-1

+1

+2

f_HRC

Calibrated Internal

T_A= -40 ~ 105

Oscillator Frequency

-2

-

%

V_DD= 2.5 V ~ 5 .5 V

T_A= 25 ℃, V_DD= 5 V

I_HRC

Operating Current

790

-

μA

us

T_S

Stable time

20

HIRC oscillator accuracy vs. temperature

0.80%

0.60%

0.40%

0.20%

0.00%

-0.20%

-0.40%

-0.60%

-0.80%

-1.00%

-1.20%

-1.40%

-50

0

50

100

150

Max

Min

TA ℃

Note: Number of test samples: 10.

Oct. 15, 2018

Page 99 of 117

Rev.1.00

M4521

Figure 8.3-2 HIRC Accuracy vs. Temperature

8.3.4 32.768 kHz External Low Speed Crystal (LXT) Input Clock

t_CLCL

t_CLCH

90%

10%

Xin_V_IH

t_CLCX

Xin_V_IL

t_CHCL

t_CHCX

Note: Duty cycle is 50%.

Symbol

t_CHCX

Parameter

Min

TBD

Xout+0.3

0

Typ

Max

-

Unit

ns

V

Test Conditions

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

-

t_CLCX

-

t_CLCH

TBD

1.8

t_CHCL

Xin_V_IH

Xin_V_IL

Xout

LXT Input Pin Input High Voltage

LXT Input Pin Input Low Voltage

LXT Output Pin

Xout-0.3

0.9

V

0.6

V

8.3.5 32.768 kHz External Low Speed Crystal (LXT) Oscillator

Parameter

Operation Voltage V_BAT

Condition

Min.

2.5

Typ.

Max.

5.5

Unit

-

V

℃

Operation Temperature

Operation Current

Clock Frequency

-40

105

32.768KHz at V_BAT=5V

External crystal

1.6

A

-

32.768

-

kHz

8.3.5.1 LXT Typical Crystal Application Circuits

CRYSTAL

C₁

C₂

10~20 pF

32.768 kHz

10~20 pF

Oct. 15, 2018

Page 100 of 117

Rev.1.00

M4521

X32_IN

X32_OUT

Crystal

C1

C2

Vss

Figure 8.3-3 Typical Crystal Application Circuit

8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC)

Symbol

Parameter

Supply Voltage

Center Frequency

Min

2.5

-

Typ

-

Max

5.5

-

Unit

V

Test Conditions

V_LRC

-

10

kHz

V_DD= 2.5 V ~ 5.5 V

-30

-50

-

+30

+50

%

T_A= 25

f_LRC

Oscillator Frequency

V_DD= 2.5 V ~ 5.5 V

T_A= -40 ~ +105

Oct. 15, 2018

Page 101 of 117

Rev.1.00

M4521

8.4 Analog Characteristics

8.4.1 PIN AC characteristics



C_L= 51 pF

Px_SLEWCTL

Symbol

Parameter

Conditions

Typ

Unit

6.87

V

= 5.5 V

= 3.3 V

= 5.5 V

= 3.3 V

DD

Output high to low level fall time

(90~10%)

t

f(IO)out

r(IO)out

10.31

Basic Slew

Rate

6.6

output low to high level rise

time (10~90%)

t

10.4

ns

4.67

6.82

5.66

8.46

V

= 5.5 V

= 3.3 V

= 5.5 V

= 3.3 V

DD

Output high to low level fall time

(90~10%)

t

f(IO)out

Higher Slew

Rate

output low to high level rise

time (10~90%)

t

r(IO)out

Oct. 15, 2018

Page 102 of 117

Rev.1.00

M4521

8.4.2 12-bit SAR ADC

Symbol

Parameter

Min

Typ

Max

Unit

Bit

Test Condition

-

DNL

INL

E_O

E_G

E_A

Resolution

12

-

Differential Nonlinearity Error

Integral Nonlinearity Error

Offset Error

-

±2

-

LSB

-

3

-

Gain Error (Transfer Gain)

Absolute Error

-3

-

4

-

Monotonic

Guaranteed

-

21

AV_DD= 4.5~5.5 V

AV_DD= 2.5~5.5 V

F_ADC

ADC Clock Frequency

MHz

8.4

AV_DD= 4.5~5.5 V

T_CONV= 21 clock

F_ADC= 21 Mhz

-

1000

400

kSPS

F_S

Sample Rate (F_ADC/T_CONV)

AV_DD= 2.5~5.5 V

T_CONV= 21 clock

F_ADC= 8.4 Mhz

-

kSPS

1/F_ADC

Default: 6 (1/F_ADC

)

T_ACQ

Acquisition Time (Sample Stage)

Total Conversion Time

2~9

EADC_SCTLx[31:24]=0

TCONV = TACQ+ 15

T_CONV

16~23

Default: 21 (1/F_ADC)

EADC_SCTLx[31:24]=0

#1

AV_DD

Supply Voltage

2.5

-

2.8

-

5.5

V

mA

V

-

#1

I_DDA

Supply Current (Avg.)

Analog Input Voltage

Reference Voltage

Input Capacitance

Input Load

-

0

-

V_REF

AV_DD

-

AV_DD= 5 V

#1

V_IN

-

V_REF

2.5

-

V

AV_DD= 5 V

#1

C_IN

6

pF

kΩ

-

#1

R_IN

-

6.5

-

Note:

#1: Design by guarantee, no test in production.

Oct. 15, 2018

Page 103 of 117

Rev.1.00

M4521

E_F(Full scale error) = E_O+ E_G

Gain Error Offset Error

E_G

E_O

4095

4094

4093

4092

Ideal transfer curve

7

6

5

4

3

2

1

ADC

output

code

Actual transfer curve

DNL

1 LSB

4095

Analog input voltage

(LSB)

Offset Error

E_O

Note: The INL is the peak difference between the transition point of the steps of the calibrated

transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the

offset and gain error from the actual transfer curve.

Typical connection diagram using the ADC

VDD

(1)

RIN

12-bit

Converter

AINx

(1)

CIN

Figure 8.4-1 Typical connection diagram using the ADC

(1) Refer to ADC spec for the values of R_IN, C_IN

Oct. 15, 2018

Page 104 of 117

Rev.1.00

M4521

8.4.3 LDO

Symbol

V_DD

Parameter

DC Power Supply

Output Voltage

Temperature

Min

Typ

-

Max

Unit

V

Test Condition

2.5

5.5

-

V_LDO

T_A

1.8

25

V

℃

-40

105

Notes:

1. It is recommended a 0.1μF bypass capacitor is connected between V_DDand the closest V_SSpin of

the device.

2. For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin and the

closest V_SSpin of the device.

8.4.4 Low Voltage Reset

Symbol

AV_DD

T_A

Parameter

Supply Voltage

Temperature

Min

0

Typ

-

Max

5.5

105

5

Unit

V

Test Condition

-

℃

-40

-

25

1

-

I_LVR

Quiescent Current

μA

V

AV_DD= 5.5 V

T_A= 105 ℃

2.00

2.20

2.45

V_LVR

Threshold Voltage

1.90

1.70

2.00

1.90

2.10

V

T_A= 25 ℃

T_A= -40 ℃

8.4.5 Brown-out Detector

Symbol

AV_DD

T_A

Parameter

Supply Voltage

Temperature

Min

0

Typ

-

Max

5.5

Unit

V

Test Condition

-

℃

μA

V

-40

-

25

105

140

4.6

-

I_BOD

Quiescent Current

-

AV_DD= 5.5 V

4.2

3.5

2.55

2.05

4.3

3.6

2.6

2.1

4.4

3.7

2.7

2.2

4.5

3.8

2.75

2.25

BOV_VL [1:0] = 11

BOV_VL [1:0] = 10

BOV_VL [1:0] = 01

BOV_VL [1:0] = 00

BOV_VL [1:0] = 11

BOV_VL [1:0] = 10

BOV_VL [1:0] = 01

BOV_VL [1:0] = 00

3.9

V

Brown-out Voltage

(Falling edge)

V_BOD

2.85

2.35

4.7

V

4.0

V

Brown-out Voltage

(Rising edge)

V_BOD

2.9

V

2.4

V

Oct. 15, 2018

Page 105 of 117

Rev.1.00

M4521

8.4.6 Power-on Reset

Symbol

T_A

Parameter

Min

-40

1.6

Typ

25

2

Max

105

2.4

Unit

℃

Test Condition

Temperature

Reset Voltage

-

V_POR

V

VDD Start Voltage to Ensure

Power-on Reset

V_POR

RR_VDD

t_POR

-

100

mV

V/ms

ms

VDD Raising Rate to Ensure

Power-on Reset

0.025

0.5

-

Minimum Time for VDD Stays at

VPOR to Ensure Power-on Reset

V_DD

t_POR

RR_VDD

V_POR

Time

Figure 8.4-2 Power-up Ramp Condition

8.4.7 Temperature Sensor

Symbol

Parameter

Temperature

Current Consumption

Gain

Min

-40

-

Typ

-

Max

105

-

Unit

℃

Test Condition

T_A

I_TEMP

-

16

μA

mV/℃

-1.55

735

-1.672

748

-1.75

755

-

Offset

mV

T_A= 0 ℃

Note:

1. The temperature sensor formula for the output voltage (Vtemp) is as below equation.

2. Vtemp (mV) = Gain (mV/ ) x Temperature ( ) + Offset (mV)

Oct. 15, 2018

Page 106 of 117

Rev.1.00

M4521

8.4.8 Internal Voltage Reference

Symbol

V_VREF

Parameter

Min.

2.5

Typ.

Max.

5.5

Unit

V

Test Condition

-

AV_DD

V_ref1

V_ref2

V_ref3

V_ref4

Vref(2.56V)

2.483

1.986

2.98

2.560

2.048

3.072

4.096

2.637

2.109

3.164

4.219

V

AV_DD>= 2.9V

AV_DD>= 2.5V

AV_DD>= 3.4V

AV_DD>= 4.5V

Vref(2.048V)

Vref(3.072V)

Vref(4.096V)

V

3.973

V

8.4.9 USB PHY

8.4.9.1 Low-full-Speed DC Electrical Specifications

Symbol

Parameter

Input High (driven)

Min.

2.0

-

Typ.

Max.

Unit

V

Test Conditions

V_IH

V_IL

V_DI

-

Input Low

0.8

V

-

Differential Input Sensitivity

0.2

V

|PADP-PADM|

Differential

V_CM

0.8

-

2.5

2.0

V

Includes V_DIrange

-

Common-mode Range

Single-ended Receiver

Threshold

V_SE

Receiver Hysteresis

-

0

200

mV

V

-

V_OL

Output Low (driven)

-

0.3

3.6

2.0

1.575

-

V_OH

V_CRS

R_PU

Z_DRV

C_IN

Output High (driven)

Output Signal Cross Voltage

Pull-up Resistor

2.8

1.3

1.425

-

V

-

V

-

kΩ

Ω

Driver Output Resistance

Transceiver Capacitance

10

-

Steady state drive*

Pin to GND

-

20

pF

*Driver output resistance doesn’t include series resistor resistance.

8.4.9.2 USB Full-Speed Driver Electrical Characteristics

Symbol

Parameter

Min.

4

Typ.

Max.

20

Unit

ns

Test Conditions

C_L=50p

T_FR

T_FF

Rise Time

Fall Time

-

4

20

ns

C_L=50p

T_FRFF

Rise and Fall Time Matching

90

111.11

%

T_FRFF=T_FR/T_FF

8.4.9.3 USB LDO Specification

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

Oct. 15, 2018

Page 107 of 117

Rev.1.00

M4521

V_BUS

V_DD33

C_bp

V_BUSPin Input Voltage

LDO Output Voltage

4.0

5.0

3.3

1.0

5.5

V

-

External Bypass Capacitor

uF

Oct. 15, 2018

Page 108 of 117

Rev.1.00

M4521

8.5 Flash DC Electrical Characteristics

Symbol

Parameter

Supply Voltage

Endurance

Min

Typ

Max

Unit

V

Test Condition

[2]

V_FLA

-

1.8

-

N_ENDUR

T_RET

20,000

-

cycles^[1]

year

ms

Data Retention

Page Erase Time

Program Time

Read Current

Program Current

Erase Current

100

20

60

-

T_ERASE

T_PROG

I_DD1

-

T_A= 25

-

us

-

13.5

mA

I_DD2

-

10

12

-

mA

I_DD3

-

mA

Notes:

1. Number of program/erase cycles.

2. V_FLAis source from chip LDO output voltage.

Oct. 15, 2018

Page 109 of 117

Rev.1.00

M4521

8.6 I²C Dynamic Characteristics

Standard Mode^[1][2]

Fast Mode^[1][2]

Symbol

Parameter

Unit

Min.

4.7

Max.

-

Min.

1.2

Max.

t_LOW

SCL low period

SCL high period

-

uS

nS

uS

nS

pF

t_HIGH

4

4.7

4

-

0.6

-

t_{SU; STA}

t_{HD; STA}

t_{SU; STO}

t_BUF

Repeated START condition setup time

START condition hold time

STOP condition setup time

Bus free time

-

1.2

-

0.6

4

0.6

-

4.7^[3]

250

0^[4]

-

1.2^[3]

-

t_SU;DAT

t_HD;DAT

t_r

Data setup time

-

100

-

Data hold time

3.45^[5]

1000

300

400

0^[4]

0.8^[5]

300

400

SCL/SDA rise time

20+0.1Cb

t_f

SCL/SDA fall time

-

C_b

Capacitive load for each bus line

-

Notes:

1. Guaranteed by design, not tested in production.

2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must

be higher than 8 MHz to achieve the maximum fast mode I²C frequency.

3. I²C controller must be retriggered immediately at slave mode after receiving STOP condition.

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to

bridge the undefined region of the falling edge of SCL.

5. The maximum hold time of the Start condition has only to be met if the interface does not stretch

the low period of SCL signal.

Repeated

START

STOP

START

STOP

SDA

SCL

t_BUF

t_LOW

t_r

t_f

t_HIGH

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_SU;DAT

Figure 8.6-1 I²C Timing Diagram

Oct. 15, 2018

Page 110 of 117

Rev.1.00

M4521

8.7 SPI Dynamic Characteristics

8.7.1 Dynamic Characteristics of Data Input and Output Pin

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)

t_W(SCKH)

t_W(SCKL)

SPI high and low time, peripheral clock

= 20MHz

22.5

-

27.5

ns

t_DS

Data input setup time

Data input hold time

Data output valid time

Data output hold time

2

4

-

ns

t_H(MI)

t_V

1

-

t_H(MO)

0

SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)

t_W(SCKH)

t_W(SCKL)

SPI high and low time, peripheral clock

= 20MHz

22.5

-

27.5

ns

t_DS

Data input setup time

Data input hold time

Data output valid time

Data output hold time

2

4

ns

t_H(MI)

t_V

-

1

-

t_H(MO)

0

CLKPOL=0

TXNEG=1

RXNEG=0

SPI Clock

CLKPOL=1

TXNEG=0

RXNEG=1

t_V

tr(SCK)

tf(SCK)

SPI data output

(SPI_MOSI)

Data Valid

t_DS

t_DH

SPI data input

(SPI_MISO)

Data Valid

CLKPOL=0

TXNEG=0

RXNEG=1

SPI Clock

CLKPOL=1

TXNEG=1

RXNEG=0

t_V

SPI data output

(SPI_MOSI)

Data Valid

t_DH

Data Valid

t_DS

SPI data input

(SPI_MISO)

Data Valid

Figure 8.7-1 SPI Master Mode Timing Diagram

Oct. 15, 2018

Page 111 of 117

Rev.1.00

M4521

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)

Peripheral

clock

t_SS

Slave select setup time

Slave select hold time

3

2

-

Peripheral

clock

t_SH

t_DS

Data input setup time

Data input hold time

Data output access time

Data output valid time

Data output hold time

2

5.5

-

ns

t_H(SI)

t_a(SO)

t_V

-

18.5-

-

18

24.5

-

t_H(SO)

6

SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)

Peripheral

clock

t_SS

Slave select setup time

Slave select hold time

3

2

-

Peripheral

clock

t_SH

t_DS

Data input setup time

Data input hold time

Data output access time

Data output valid time

Data output hold time

2

6

-

ns

t_H(SI)

t_a(SO)

t_V

-

24

30

-

23

-

t_H(SO)

7

Oct. 15, 2018

Page 112 of 117

Rev.1.00

M4521

SSACTPOL=1

SSACTPOL=0

t_SS

t_SH

SPI SS

CLKPOL=0

TXNEG=1

RXNEG=0

SPI Clock

CLKPOL=1

TXNEG=0

RXNEG=1

t_V

SPI data output

(SPI_MISO)

Data Valid

t_DH

t_DS

SPI data input

(SPI_MOSI)

Data Valid

SSACTPOL=1

t_SS

t_SH

SPI SS

SSACTPOL=0

CLKPOL=0

TXNEG=0

RXNEG=1

SPI Clock

CLKPOL=1

TXNEG=1

RXNEG=0

ta(so)

t_V

SPI data output

(SPI_MISO)

Data Valid

t_DH

Data Valid

t_DS

SPI data input

(SPI_MOSI)

Data Valid

Figure 8.7-2 SPI Slave Mode Timing Diagram

Oct. 15, 2018

Page 113 of 117

Rev.1.00

M4521

9 PACKAGE DIMENSIONS

9.1 LQFP 64L (7x7x1.4 mm footprint 2.0 mm)

Oct. 15, 2018

Page 114 of 117

Rev.1.00

M4521

9.2 LQFP 48L (7x7x1.4mm footprint 2.0mm)

H

36

25

37

24

H

13

48

12

1



Controlling dimension

:

Millimeters

Dimension in inch

Dimension in mm

Symbol

Min Nom Max Min Nom Max

A

1

0.002 0.004 0.006 0.05

0.053 0.055 0.057 1.35

0.10 0.15

A

2

1.40

1.45

0.25

0.20

7.10

0.65

9.10

A

0.006

0.004

0.008 0.010 0.15 0.20

b

c

D

0.006

0.10 0.15

0.008

7.00

6.90

0.35

0.272 0.276 0.280

E

0.020

0.354

0.014

0.350

0.018

0.026

0.50

e

H

D

0.358 8.90 9.00

9.10

0.60 0.75

1.00

E

H

0.024 0.030

0.45

0

L

Y

0.039

0.004

7

1

0.10

7

0

Oct. 15, 2018

Page 115 of 117

Rev.1.00

M4521

10 REVISION HISTORY

Date

Revision

Description

2018.10.15

1.00

Initial version.

Oct. 15, 2018

Page 116 of 117

Rev.1.00

M4521

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any

malfunction or failure of which may cause loss of human life, bodily injury or severe property

damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic

energy control instruments, airplane or spaceship instruments, the control or operation of

dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all

types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay

claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the

damages and liabilities thus incurred by Nuvoton.

Oct. 15, 2018

Page 117 of 117

Rev.1.00


型号：	M4521LE6AE
厂家：	NUVOTON
描述：	ArmÂ® CortexÂ®-M 32-bit Microcontroller 微控制器
文件：	总117页 (文件大小：2555K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M4521LE6AE [NUVOTON]

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