MINI52-TDC [NUVOTON]
ARM Cortexâ¢-M0 32-BIT MICROCONTROLLER;
| 型号： | MINI52-TDC |
| 厂家： | 
NUVOTON |
| 描述： | ARM Cortexâ¢-M0 32-BIT MICROCONTROLLER |
| 文件： | 总70页 (文件大小：1838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NuMicro MINI51 DE Series Datasheet
ARM Cortex™-M0
32-BIT MICROCONTROLLER
NuMicro Mini51™ DE Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicroTM microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 22, 2014
Page 1 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Table of Contents
1
2
3
4
GENERAL DESCRIPTION.................................................................................................7
FEATURES...........................................................................................8
ABBREVIATIONS.................................................................................12
PARTS INFORMATION LIST AND PIN CONFIGURATION ..............................13
NuMicro Mini51 Series Selection Code..........................................................13
NuMicro Mini51 Series Product Selection Guide...............................................14
PIN CONFIGURATION ...............................................................................15
4.1
4.2
4.3
4.3.1
4.3.2
LQFP 48-pin .................................................................................................... 15
QFN 33-pin ................................................................................................................................16
TSSOP 20-pin............................................................................................................................17
Mini54FHC (TSSOP20-pin)........................................................................................................17
Pin Description .........................................................................................18
4.3.3
4.3.4
4.4
5.1
6.1
5
6
BLOCK DIAGRAM ................................................................................22
NuMicro Mini51™ Block Diagram ...................................................................22
Functional Description ............................................................................23
Memory Organization .................................................................................23
6.1.1
6.1.2
Overview....................................................................................................................................23
System Memory Map .................................................................................................................23
Nested Vectored Interrupt Controller (NVIC)......................................................24
Overview....................................................................................................................................24
Features.....................................................................................................................................24
Exception Model and System Interrupt Map...............................................................................25
Vector Table ..............................................................................................................................26
Operation Description ................................................................................................................27
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
System Manager .......................................................................................28
Overview....................................................................................................................................28
System Reset ............................................................................................................................28
System Power Architecture........................................................................................................28
Whole System Memory Mapping ...............................................................................................30
6.3.1
6.3.2
6.3.3
6.3.4
6.4
Clock Controller ........................................................................................31
Overview....................................................................................................................................31
System Clock and SysTick Clock...............................................................................................32
ISP Clock Source Selection .......................................................................................................33
6.4.1
6.4.2
6.4.3
May 22, 2014
Page 2 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.4.4
6.4.5
6.4.6
Module Clock Source Selection .................................................................................................33
Power-down Mode Clock ...........................................................................................................34
Frequency Divider Output ..........................................................................................................34
6.5
Analog Comparator (ACMP) .........................................................................36
Overview....................................................................................................................................36
Features.....................................................................................................................................36
Analog-to-Digital Converter (ADC)..................................................................37
Overview....................................................................................................................................37
Features.....................................................................................................................................37
Flash Memory Controller (FMC).....................................................................38
Overview....................................................................................................................................38
Features.....................................................................................................................................38
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
General Purpose I/O (GPIO).........................................................................39
Overview....................................................................................................................................39
Features.....................................................................................................................................39
I2C Serial Interface Controller (I2C) ................................................................40
Overview....................................................................................................................................40
Features.....................................................................................................................................40
Enhanced PWM Generator...........................................................................41
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1 Overview....................................................................................................................................41
6.10.2 Features.....................................................................................................................................41
6.11
Serial Peripheral Interface (SPI).....................................................................43
6.11.1 Overview....................................................................................................................................43
6.11.2 Features.....................................................................................................................................43
6.12
Timer Controller (TMR) ...............................................................................44
6.12.1 Overview....................................................................................................................................44
6.12.2 Features.....................................................................................................................................44
6.13
UART Controller (UART) .............................................................................45
6.13.1 Overview....................................................................................................................................45
6.13.2 Features.....................................................................................................................................45
6.14
Watchdog Timer (WDT)...............................................................................46
6.14.1 Overview....................................................................................................................................46
6.14.2 Features.....................................................................................................................................46
7
ARM® Cortex™-M0 core ........................................................................47
7.1
Overview.................................................................................................47
May 22, 2014
Page 3 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
7.2
7.3
Features .................................................................................................47
System Timer (SysTick) ..............................................................................48
8
9
APPLICATION CIRCUIT.........................................................................49
MINI51XXDE ELECTRICAL CHARACTERISTICS .........................................50
Absolute Maximum Ratings ..........................................................................50
DC Electrical Characteristics.........................................................................50
AC Electrical Characteristics.........................................................................58
9.1
9.2
9.3
9.3.1
9.3.2
External Input Clock...................................................................................................................58
External 4~24 MHz High Speed Crystal (HXT)...........................................................................58
Typical Crystal Application Circuits ............................................................................................59
22.1184 MHz Internal High Speed RC Oscillator (HIRC)............................................................59
10 kHz Internal Low Speed RC Oscillator(LIRC)........................................................................60
Analog Characteristics ................................................................................61
10-bit SARADC..........................................................................................................................61
LDO & Power Management .......................................................................................................62
Low Voltage Reset.....................................................................................................................62
Brown-out Detector ....................................................................................................................63
Power-on Reset .........................................................................................................................63
Comparator................................................................................................................................64
9.3.3
9.3.4
9.3.5
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.5
Flash DC Electrical Characteristics.................................................................65
10 PACKAGE DIMENSIONS........................................................................66
10.1
10.2
10.3
10.4
48-pin LQFP ............................................................................................66
33-pin QFN (4 mm x 4 mm)..........................................................................67
33-pin QFN (5 mm x 5 mm)..........................................................................68
20-pin TSSOP ..........................................................................................69
11 REVISION HISTORY .......................................................................................................70
May 22, 2014
Page 4 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
LIST OF FIGURES
Figure 4.1-1 NuMicro Mini51 Series Selection Code ................................................................ 13
Figure 4.3-1 NuMicro Mini51 Series LQFP 48-pin Diagram ...................................................... 15
Figure 4.3-2 NuMicro Mini51 Series QFN 33-pin Diagram........................................................ 16
Figure 4.3-3 NuMicro Mini51 Series TSSOP 20-pin Diagram ................................................... 17
Figure 4.3-4 NuMicro Mini51 Series TSSOP 20-pin Diagram ................................................... 17
Figure 5.1-1 NuMicro Mini51 Series Block Diagram ................................................................. 22
Figure 6.3-1 NuMicro Mini51 Series Power Architecture Diagram ............................................ 29
Figure 6.4-1 Clock Generator Block Diagram .............................................................................. 31
Figure 6.4-2 System Clock Block Diagram .................................................................................. 32
Figure 6.4-3 SysTick Clock Control Block Diagram ..................................................................... 32
Figure 6.4-4 AHB Clock Source for HCLK................................................................................... 33
Figure 6.4-5 Peripherals Clock Source Selection for PCLK ......................................................... 33
Figure 6.4-6 Clock Source of Frequency Divider ......................................................................... 35
Figure 6.4-7 Block Diagram of Frequency Divider ....................................................................... 35
Figure 7.1-1 Functional Block Diagram ....................................................................................... 47
Figure 9-1Mini5xDE Typical Crystal Application Circuit ............................................................... 59
Figure 9-2Power-up Ramp Condition .......................................................................................... 64
May 22, 2014
Page 5 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
LIST OF TABLES
Table 4.1-1 List of Abbreviations................................................................................................. 12
Table 4.2-1NuMicro Mini51 Series Product Selection Guide .................................................... 14
Table 6.1-1 Address Space Assignments for On-Chip Modules .................................................. 23
Table 6.2-1 Exception Model....................................................................................................... 25
Table 6.2-2 System Interrupt Map Vector Table.......................................................................... 26
Table 6.2-3 Vector Table Format................................................................................................. 26
Table 6.3-1 Memory Mapping Table............................................................................................ 30
Table 6.4-1 Peripheral Clock Source Selection Table ................................................................. 34
May 22, 2014
Page 6 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
1
GENERAL DESCRIPTION
The NuMicro Mini51™ series 32-bit microcontroller is embedded with ARM® Cortex™-M0 core for
industrial control and applications which require high performance, high integration, and low cost.
The Cortex™-M0 is the newest ARM® embedded processor with 32-bit performance at a cost
equivalent to the traditional 8-bit microcontroller.
The NuMicro Mini51™ series can run up to 24 MHz and operate at 2.5V ~ 5.5V, -40℃ ~ 105℃,
and thus can afford to support a variety of industrial control and applications which need high
CPU performance. The NuMicro Mini51™ series offers 4K/8K/16K-bytes embedded program
flash, size configurable data flash (shared with program flash), 2K-byte flash for the ISP, and 2K-
byte SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the
NuMicro Mini51™ series in order to reduce component count, board space and system cost.
These useful functions make the NuMicro Mini51™ series powerful for a wide range of
applications.
Additionally, the NuMicro Mini51™ series is equipped with ISP (In-System Programming) and ICP
(In-Circuit Programming) functions, which allow the user to update the program memory without
removing the chip from the actual end product.
May 22, 2014
Page 7 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
2
FEATURES
Core
ARM® Cortex™-M0 core running up to 24 MHz
One 24-bit system timer
Supports Low Power Sleep mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-level of priority
Supports Serial Wire Debug (SWD) interface and two watch points/four
breakpoints
Built-in LDO for wide operating voltage ranged: 2.5 V to 5.5 V
Memory
4 KB/ 8 KB/ 16 KB Flash memory for program memory (APROM)
Configurable Flash memory for data memory (Data Flash)
2 KB Flash for loader (LDROM)
2 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
Switch clock sources on-the-fly
4 ~ 24 MHz external crystal input (HXT)
32.768 kHz external crystal input (LXT) for Power-down wake-up and system
operation clock
O
22.1184 MHz internal oscillator (HIRC) (1% accuracy at 25 C, 5V)
O
Dynamically calibrating the HIRC OSC to 22.1184 MHz ±1% from -40 C to
O
105 C by external 32.768K crystal oscillator (LXT)
10 kHz internal low-power oscillator (LIRC) for Watchdog Timer and Power-
down wake-up
I/O Port
Up to 30 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Input-only with high impendence
Push-pull output
Open-drain output
Quasi-bidirectional
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink I/O mode
Configurable default I/O mode of all pins after POR
Timer
May 22, 2014
Page 8 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Provides two channel 32-bit timers. One 8-bit pre-scale counter with 24-bit up
counter for each timer
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous operation modes
24-bit up counter value is readable through TDR (Timer Data Register)
Provides trigger counting/free counting/counter reset function triggered by
external capture pin or internal comparator signal
Provides event counter function
Supports wake-up from Idle or Power-down mode
WDT (Watchdog Timer)
Multiple clock sources
Supports wake-up from Idle or Power-down mode
Interrupt or reset selectable on watchdog time-out
PWM
Independent 16-bit PWM duty control units with maximum six outputs
Supports group/synchronous/independent/ complementary modes
Supports One-shot or Auto-reload mode
Supports Edge-aligned and Center-aligned type
Programmable dead-zone insertion between complementary channels
Each output has independent polarity setting control
Hardware fault brake protections
Supports duty, period, and fault break interrupts
Supports duty/period trigger ADC conversion
Timer comparing matching event trigger PWM to do phase change
Supports comparator event trigger PWM to force PWM output low for current
period
Provides interrupt accumulation function
UART (Universal Asynchronous Receiver/Transmitters)
One UART device
Buffered receiver and transmitter, each with 16-byte FIFO
Optional flow control function (CTSn and RTSn)
Supports IrDA (SIR) function
Programmable baud-rate generator up to 1/16 system clock
Supports RS-485 function
SPI (Serial Peripheral Interface)
One SPI devices
Supports Master/Slave mode
May 22, 2014
Page 9 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
I2C
Full-duplex synchronous serial data transfer
Provides 3-wire function
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte Suspend mode in 32-bit transmission
4-level depth FIFO buffer
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Supports Power-down wake-up function
Support FIFO function
ADC (Analog-to-Digital Converter)
10-bit SAR ADC with 300K SPS
Up to 8-ch single-end input and one internal input from band-gap
Conversion started either by software trigger, PWM trigger, or external pin
trigger
Supports conversion value monitoring (or comparison) for threshold voltage
detection
Analog Comparator
Two analog comparators with programmable 16-level internal voltage reference
Build-in CRV (comparator reference voltage)
Supports Hysteresis function
Interrupt when compared results changed
ISP (In-System Programming) and ICP (In-Circuit Programming)
BOD (Brown-out Detector)
With 4 programmable threshold levels: 4.4V/3.7V/2.7V/2.2V
May 22, 2014
Page 10 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Threshold voltage level: 2.0V
Operating Temperature: -40℃~105℃
Reliability: EFT > ± 4KV, ESD HBM pass 4KV
Packages:
Green package (RoHS)
48-pin LQFP (7x7), 33-pin QFN (5x5) , 33-pin QFN (4x4), 20-pin TSSOP
May 22, 2014
Page 11 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
AHB
APB
Analog Comparator Controller
Analog-to-Digital Converter
Advanced High-Performance Bus
Advanced Peripheral Bus
BOD
DAP
FIFO
FMC
GPIO
HCLK
HIRC
HXT
ICP
Brown-out Detection
Debug Access Port
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Circuit Programming
ISP
In System Programming
ISR
Interrupt Service Routine
LDO
LIRC
LXT
Low Dropout Regulator
10 kHz internal low speed RC oscillator (LIRC)
32.768 kHz External Low Speed Crystal Oscillator
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Pulse Width Modulation
NVIC
PCLK
PWM
SPI
Serial Peripheral Interface
SPS
Samples per Second
TMR
UART
UCID
WDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Table 4.1-1 List of Abbreviations
May 22, 2014
Page 12 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro Mini51 Series Selection Code
MINI 5X
X E
- X
CPU core
ARM Cortex M0
Temperature
E: - 40℃ ~ +105℃
C:- 40℃ ~ +125℃
Version
Flash ROM
D: Version
H: Version
51: 4 KB Flash ROM
52: 8 KB Flash ROM
54: 16 KB Flash ROM
Package Type
F: TSSOP20
Z: QFN 33 (5x5)
T: QFN 33 (4x4)
L: LQFP 48 (7x7)
Figure 4.1-1 NuMicro Mini51 Series Selection Code
May 22, 2014
Page 13 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4.2 NuMicro Mini51 Series Product Selection Guide
ISP
Part No. APROM RAM Data Flash Loader I/O Timer
ROM
Connectivity
ISP
IRC
Comp. PWM ADC
ICP 22.1184 Package
IAP
UART SPI I2C
MHz
up to 2x
MINI51FDE 4 KB 2 KB Configurable 2 KB
17 32-bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
3
6
6
6
3
6
6
6
3
6
6
6
6
4x10-bit
8x10-bit
8x10-bit
8x10-bit
4x10-bit
8x10-bit
8x10-bit
8x10-bit
4x10-bit
8x10-bit
8x10-bit
8x10-bit
3x10-bit
v
v
TSSOP20
LQFP48
up to 2x
MINI51LDE 4 KB 2 KB Configurable 2 KB
30 32-bit
2
2
2
-
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
up to 2x
MINI51ZDE 4 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(5x5)
up to 2x
MINI51TDE 4 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(4x4)
up to 2x
MINI52FDE 8 KB 2 KB Configurable 2 KB
17 32-bit
TSSOP20
LQFP48
up to 2x
MINI52LDE 8 KB 2 KB Configurable 2 KB
30 32-bit
2
2
2
-
up to 2x
MINI52ZDE 8 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(5x5)
up to 2x
MINI52TDE 8 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(4x4)
up to 2x
MINI54FDE 16 KB 2 KB Configurable 2 KB
17 32-bit
TSSOP20
LQFP48
up to 2x
MINI54LDE 16 KB 2 KB Configurable 2 KB
30 32-bit
2
2
2
-
up to 2x
MINI54ZDE 16 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(5x5)
up to 2x
MINI54TDE 16 KB 2 KB Configurable 2 KB
29 32-bit
QFN33
(4x4)
up to 2x
*MINI54FHC 16 KB 2 KB Configurable 2 KB
17 32-bit
TSSOP20
Table 4.2-1NuMicro Mini51 Series Product Selection Guide
* Mini54FHC is a special part number, not pin to pin compatible to others Mini51series part number.
May 22, 2014
Page 14 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4.3 PIN CONFIGURATION
4.3.1 LQFP 48-pin
NC
36
NC
1
ACMP0_P, AIN5, P1.5
P0.4, SPISS,PWM5
35
2
P0.5, MOSI
P0.6, MISO
P0.7, SPICLK
NC
3
34
33
32
31
30
29
28
27
26
25
/RESET
4
ACMP1_N, AIN6, P3.0
AVSS
P5.4
5
6
Mini51
LQFP 48-pin
ACMP1_P, AIN7, P3.1
7
P4.7, ICE_DAT
ACMP1_P, T0EX, STADC, INT0,
P3.2
8
P4.6, ICE_CLK
NC
NC
ACMP1_P, SDA, T0, P3.4
9
ACMP1_P, SCL, T1, P3.5
10
11
12
NC
NC
P2.6, PWM4, ACMP1_O
P2.5, PWM3
Figure 4.3-1 NuMicro Mini51 Series LQFP 48-pin Diagram
May 22, 2014
Page 15 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4.3.2 QFN 33-pin
32 31 30 29 28 27 26 25
ACMP0_P,AIN5, P1.5
P0.4, SPISS,PWM5
P0.5, MOSI
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
/RESET
ACMP1_N,AIN6, P3.0
P5.4
P0.6, MISO
P0.7, SPICLK
Mini51
QFN 33-pin
ACMP1_P,AIN7, P3.1
P4.7, ICE_DAT
P4.6, ICE_CLK
P2.6, PWM4,ACMP1_O
P2.5, PWM3
ACMP1_P,
T0EX,STADC,INT0, P3.2
ACMP1_P, SDA, T0, P3.4
33 VSS
10 11 12 13 14 15 16
ACMP1_P, SCL, T1, P3.5
9
Top Transparent View
Figure 4.3-2 NuMicro Mini51 Series QFN 33-pin Diagram
May 22, 2014
Page 16 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4.3.3 TSSOP 20-pin
RX,AIN2,P1.2 1
20 VDD
TX,AIN3,P1.3 2
AIN4,P1.4 3
AIN5,P1.5 4
/RESET 5
19 P0.4,SPISS,PWM5
18 P0.5,MOSI
17 P0.6,MISO
16 P0.7,SPICLK
15 P4.7,ICE_DAT
14 P4.6,ICE_CLK
13 P2.5,PWM3
12 P2.4,PWM2
11 Vss
Mini51
SSOP
20-Pin
INT0,TOEX,STADC,P3.2 6
T0,SDA,P3.4 7
T1,SCL,P3.5 8
XTAL2,P5.1 9
XTAL1,P5.0 10
Figure 4.3-3 NuMicro Mini51 Series TSSOP 20-pin Diagram
4.3.4 Mini54FHC (TSSOP20-pin)
VDD
1
20 P0.4,SPISS,PWM5
19 P0.5,MOSI
RX,AIN2,P1.2 2
TX,AIN3,P1.3 3
AIN4,P1.4 4
18 P0.6,MISO
17 P0.7,SPICLK
16 P4.7,ICE_DAT
15 P4.6,ICE_CLK
14 P2.6,PWM4
13 P2.5,PWM3
12 P2.4,PWM2
11 P2.3,PWM1
Mini54FHC
SSOP
/RESET 5
20-pin
INT0,TOEX,STADC,P3.2 6
T0,SDA,P3.4 7
T1,SCL,P3.5 8
VSS 9
PWM0,P2.2 10
Figure 4.3-4 NuMicro Mini51 Series TSSOP 20-pin Diagram
Page 17 of 70
May 22, 2014
Revision 1.01
NuMicro MINI51 DE Series Datasheet
4.4 Pin Description
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
TSSOP Mini54FHCT
20-pin SSOP20-pin
1
---
1
---
---
NC
---
I/O
AI
Not connected
P1.5
General purpose digital I/O pin
ADC analog input pin
2
4
---
AIN5
ACMP0_P
AI
Analog comparator positive input pin
The Schmitt trigger input pin for hardware device reset. A “Low”
on this pin for 768 clock counter of Internal RC 22.1184 MHz while
the system clock is running will reset the device. /RESET pin has
an internal pull-up resistor allowing power-on reset by simply
connecting an external capacitor to GND.
3
4
2
3
5
5
/RESET
I(ST)
P3.0
I/O
AI
AI
AP
I/O
I/O
AI
AI
I/O
I
General purpose digital I/O pin
ADC analog input pin
---
---
AIN6
ACMP1_N
AVSS
Analog comparator negative input pin
Ground pin for analog circuit
General purpose digital I/O pin
General purpose digital I/O pin
ADC analog input pin
5
6
---
4
---
---
---
---
P5.4
P3.1
7
5
---
---
AIN7
ACMP1_P
P3.2
Analog comparator positive input pin
General purpose digital I/O pin
External interrupt 0 input pin
ADC external trigger input pin
Timer 0 external capture/reset trigger input pin
Analog comparator positive input pin
General purpose digital I/O pin
Timer 0 external event counter input pin
I2C data I/O pin
INT0
8
6
6
6
STADC
T0EX
ACMP1_P
P3.4
I
I
AI
I/O
I/O
I/O
AI
I/O
I/O
I/O
AI
---
---
---
T0
9
7
8
7
8
7
8
SDA
ACMP1_P
P3.5
Analog comparator positive input pin
General purpose digital I/O pin
Timer 1 external event counter input pin
I2C clock I/O pin
T1
10
SCL
ACMP1_P
NC
Analog comparator positive input pin
Not connected.
11
12
13
---
---
---
---
---
--
---
---
--
NC
Not connected.
NC
Not connected.
May 22, 2014
Page 18 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
TSSOP Mini54FHCT
20-pin SSOP20-pin
P3.6
I/O
O
General purpose digital I/O pin.
ACMP0_O
CKO
Analog comparator output pin.
14
9
---
---
O
Frequency divider output pin.
T1EX
I
Timer 1 external capture/reset trigger input pin.
General purpose digital I/O pin.
P5.1
I/O
15
16
10
11
9
---
---
The output pin from the internal inverting amplifier. It emits the
inverted signal of XTAL1.
XTAL2
P5.0
O
I/O
I
General purpose digital I/O pin.
10
The input pin to the internal inverting amplifier. The system clock
could be from external crystal or resonator.
XTAL1
12
33
---
17
18
11
---
9
VSS
P
P
Ground pin for digital circuit.
---
LDO_CAP
LDO output pin.
General purpose digital I/O pin.
19
---
---
---
P5.5
I/O
User program must enable pull-up resistor in the QFN-33
package.
P5.2
I/O
I
General purpose digital I/O pin.
External interrupt 1 input pin.
Not connected.
20
21
22
13
---
14
---
---
---
---
---
10
INT1
NC
---
I/O
O
P2.2
General purpose digital I/O pin.
PWM0 output of PWM unit.
General purpose digital I/O pin.
PWM1 output of PWM unit.
General purpose input/output digital pin.
PWM2 output of PWM unit.
General purpose digital I/O pin.
PWM3 output of PWM unit.
General purpose digital I/O pin.
PWM4 output of PWM unit.
Analog comparator output pin.
Not connected.
PWM0
P2.3
I/O
O
23
24
25
15
16
17
---
12
13
11
12
13
PWM1
P2.4
I/O
O
PWM2
P2.5
I/O
O
PWM3
P2.6
I/O
O
26
18
---
14
PWM4
ACMP1_O
NC
O
27
28
29
---
---
19
---
---
14
---
---
15
---
---
I/O
NC
Not connected.
P4.6
General purpose digital I/O pin.
May 22, 2014
Page 19 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
TSSOP Mini54FHCT
20-pin SSOP20-pin
ICE_CLK
P4.7
I
Serial wired debugger clock pin.
I/O
I/O
---
I/O
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
Serial wired debugger data pin.
Not connected.
30
31
32
20
---
21
15
---
16
16
---
17
ICE_DAT
NC
P0.7
General purpose digital I/O pin.
SPI serial clock pin.
SPICLK
P0.6
General purpose digital I/O pin.
SPI MISO (master in/slave out) pin.
General purpose digital I/O pin.
SPI MOSI (master out/slave in) pin.
General purpose digital I/O pin.
SPI slave select pin.
33
34
22
23
17
18
18
19
MISO
P0.5
MOSI
P0.4
I/O
I/O
O
35
36
24
---
19
---
20
---
SPISS
PWM5
NC
PWM5 output of PWM unit.
Not connected.
---
I/O
O
P0.1
General purpose digital I/O pin.
UART RTS pin.
RTSn
RX
37
25
---
---
I
UART data receiver input pin.
SPI slave select pin.
SPISS
P0.0
I/O
I/O
I
General purpose digital I/O pin.
UART CTS pin.
38
26
---
---
CTSn
TX
O
UART transmitter output pin.
Not connected.
39
40
---
---
---
---
---
---
NC
---
---
I/O
AI
P
NC
Not connected.
P5.3
General purpose digital I/O pin.
ADC analog input pin.
41
27
28
---
20
---
1
AIN0
VDD
42
43
Power supply for digital circuit.
Power supply for analog circuit.
General purpose digital I/O pin.
ADC analog input pin.
AVDD
P1.0
P
I/O
AI
AI
I/O
AI
44
45
29
30
---
1
---
2
AIN1
ACMP0_P
P1.2
Analog comparator positive input pin.
General purpose digital I/O pin.
ADC analog input pin.
AIN2
May 22, 2014
Page 20 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
TSSOP Mini54FHCT
20-pin SSOP20-pin
RX
I
UART data receiver input pin.
ACMP0_P
P1.3
AI
I/O
Analog comparator positive input pin.
General purpose digital I/O pin.
AIN3
AI
O
ADC analog input pin.
46
31
2
3
TX
UART transmitter output pin.
ACMP0_P
P1.4
AI
I/O
I/O
AI
Analog comparator positive input pin.
General purpose digital I/O pin.
PWM5: PWM output/Capture input.
Analog comparator negative input pin.
AIN4
47
48
32
---
3
4
ACMP0_N
--
--
NC
---
Not connected.
[1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin, ST:
Schmitt trigger, A: Analog input.
May 22, 2014
Page 21 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
5
BLOCK DIAGRAM
5.1 NuMicro Mini51™ Block Diagram
Figure 5.1-1 NuMicro Mini51 Series Block Diagram
May 22, 2014
Page 22 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6
FUNCTIONAL DESCRIPTION
6.1 Memory Organization
6.1.1 Overview
The NuMicro Mini51 series provides 4G-byte addressing space. The addressing space
assigned to each on-chip controllers is shown the following table. The detailed register definition,
addressing space, and programming details will be described in the following sections for each
on-chip peripheral. The NuMicro Mini51 series only supports little-endian data format.
6.1.2 System Memory Map
The memory locations assigned to each on-chip controllers are shown in the following table.
Addressing Space
Token
Modules
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_3FFF
0x2000_0000 – 0x2000_07FF
FLASH_BA
SRAM_BA
Flash Memory Space (16 KB)
SRAM Memory Space (2 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
GCR_BA
CLK_BA
INT_BA
GP_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO (P0~P5) Control Registers
Flash Memory Control Registers
FMC_BA
APB Modules Space (0x4000_0000 – 0x401F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
WDT_BA
TMR_BA
I2C_BA
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C Interface Control Registers
SPI_BA
SPI with Master/slave Function Control Registers
PWM Control Registers
PWM_BA
UART_BA
ACMP_BA
ADC_BA
UART Control Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
System Control Space (0xE000_E000 – 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCB_BA
System Timer Control Registers
Nested Vectored Interrupt Control Registers
System Control Block Registers
Table 6.1-1 Address Space Assignments for On-Chip Modules
May 22, 2014
Page 23 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.2 Nested Vectored Interrupt Controller (NVIC)
6.2.1 Overview
The Cortex™-M0 CPU provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor core and provides following features.
6.2.2 Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority change
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
May 22, 2014
Page 24 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.2.3 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro Mini51 series. Software can
set four levels of priority on some of these exceptions as well as on all interrupts. The highest
user-configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default
priority of all the user-configurable interrupts is 0. Note that the priority 0 is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
2
NMI
-2
Hard Fault
Reserved
3
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
Reserved
12 ~ 13
14
PendSV
SysTick
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-1 Exception Model
Interrupt Number
(Bit In Interrupt
Registers)
Exception
Number
Source
Module
Power-Down
Wake-Up
Interrupt Name
Interrupt Description
1 ~ 15
16
-
-
-
System exceptions
-
0
1
2
3
BOD_OUT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
Yes
Yes
Yes
Yes
17
WDT
GPIO
GPIO
Watchdog Timer interrupt
18
External signal interrupt from P3.2 pin
External signal interrupt from P5.2 pin
19
EINT1
External signal interrupt from GPIO
group P0~P1
20
21
4
5
GP0/1_INT
GPIO
GPIO
Yes
Yes
External signal interrupt from GPIO
group P2~P4 except P3.2
GP2/3/4_INT
22
23
6
PWM_INT
BRAKE_INT
TMR0_INT
TMR1_INT
-
PWM
PWM
TMR0
TMR1
-
PWM interrupt
PWM interrupt
Timer 0 interrupt
Timer 1 interrupt
-
No
No
7
24
8
9
Yes
Yes
25
26 ~ 27
28
10 ~ 11
12
UART_INT
UART
UART interrupt
Yes
May 22, 2014
Page 25 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Interrupt Number
(Bit In Interrupt
Registers)
Exception
Number
Source
Module
Power-Down
Wake-Up
Interrupt Name
Interrupt Description
29
30
31
13
14
15
-
-
SPI
-
-
SPI_INT
-
SPI interrupt
-
No
External signal interrupt from GPIO
group P5 except P5.2
32
33
16
17
GP5_INT
GPIO
HIRC
Yes
HIRC_TRIM_IN
T
HIRC trim interrupt
No
I2C interrupt
-
34
18
I2C_INT
-
I2C
-
Yes
35 ~ 40
19 ~ 24
Analog Comparator 0 or Comparator 1
interrupt
41
42 ~ 43
44
25
26 ~ 27
28
ACMP_INT
-
ACMP
-
Yes
-
Clock controller interrupt for chip wake-
up from Power-down state
PWRWU_INT
CLKC
Yes
No
45
29
ADC_INT
-
ADC
-
ADC interrupt
-
46 ~ 47
30 ~ 31
Table 6.2-2 System Interrupt Map Vector Table
6.2.4 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x00000000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
0x00
Description
Initial Stack Pointer Value
Exception Number * 0x04
Exception Entry Pointer using that Exception Number
Table 6.2-3 Vector Table Format
May 22, 2014
Page 26 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.2.5 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
May 22, 2014
Page 27 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.3 System Manager
6.3.1 Overview
System management includes the following sections:
System Reset
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.3.2 System Reset
The system reset can be included by one of the following listed events. For these reset events
flags can be read by RSTSRC register.
Power-On Reset (POR)
Low level on the Reset Pin (/RESET)
Watchdog Timer Time-out Reset (WDT)
Brown-out Detector Reset (BOD)
Cortex™-M0 MCU Reset
CPU Reset
6.3.3 System Power Architecture
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies power to the I/O pins and internal regulator
which provides a fixed 1.8V power for digital operation.
Build-in a capacitor for internal voltage regulator
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
as the digital power (VDD). The following figure shows the power distribution of the Mini51TMDE
series.
May 22, 2014
Page 28 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Analog Comparator
AVDD
AVSS
10-bit
SAR-ADC
Low
Voltage
Reset
Brown
Out
Detector
Internal
FLASH
Digital Logic
22.1184 MHz and
10 kHz Oscillator
LDO_CAP
GPIO Pins
1.8V
POR18
5V to 1.8V
LDO
IO cell
VDD VSS
Mini51TM Series Power Distribution
Figure 6.3-1 NuMicro Mini51 Series Power Architecture Diagram
May 22, 2014
Page 29 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.3.4 Whole System Memory Mapping
Mini51/52/54
System Control
4 GB
0xFFFF_FFFF
|
System Control
0xE000_ED00 SCS_BA
0xE000_E100 SCS_BA
0xE000_E010 SCS_BA
Reserved
System Control
Reserved
Reserved
Reserved
AHB
External Interrupt Control
System Timer Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_E00F
|
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
0x5020_0000
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
AHB peripherals
FMC
0x5000_C000 FMC_BA
0x5000_4000 GP_BA
GPIO Control
Interrupt Multiplexer Control 0x5000_0300 INT_BA
Clock Control
0x5000_0200 CLK_BA
0x5000_0000 GCR_BA
Reserved
|
System Global Control
0x4020_0000
0x401F_FFFF
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
ADC Control
0x400E_0000 ADC_BA
0x400D_0000 CMP_BA
0x4005_0000 UART_BA
0x4004_0000 PWM_BA
0x4003_0000 SPI_BA
0x4002_0000 I2C_BA
0x4001_0000 TMR_BA
0x4000_4000 WDT_BA
Reserved
|
ACMP Control
UART Control
0x2000_0800
0x2000_07FF
0x2000_0000
0x1FFF_FFFF
PWM Control
SPI Control
2 KB SRAM
Reserved
0.5 GB
I2C Control
Timer0/Timer1 Control
WDT Control
|
0x0000_4000
16 KB on-chip Flash (Mini54)0x0000_3FFF
8 KB on-chip Flash (Mini52) 0x0000_1FFF
0x0000_0FFF
4 KB on-chip Flash (Mini51)
0x0000_0000
0 GB
Table 6.3-1 Memory Mapping Table
May 22, 2014
Page 30 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.4 Clock Controller
6.4.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex™-M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit
Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC) to reduce
the overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
The clock generator consists of 3 sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT) or 32.768 kHz (LXT) external
low speed crystal oscillator
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTLCLK_EN (PWRCON[1:0])
HXT or LXT
4~24 MHz HXT
or
32.768 kHz LXT
XTAL1
XTAL2
OSC22M_EN (PWRCON[2])
HIRC
LIRC
22.1184 MHz
HIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.4-1 Clock Generator Block Diagram
May 22, 2014
Page 31 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.4.2 System Clock and SysTick Clock
The system clock has three clock sources which are generated from clock generator block. The
clock source switches depending on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown below.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
Reserved
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLK_N (CLKDIV[3:0])
PCLK
4~24 MHz HXT or
32.768 kHz LXT
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.4-2 System Clock Block Diagram
The clock source of SysTick in CortexTM-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switches depending on the setting of the register STCLK_S (CLKSEL0[5:3]). The
block diagram is shown below.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
HIRC
1/2
1/2
1/2
111
011
HCLK
4~24 MHz HXT or
32.768 kHz LXT
STCLK
010
001
Reserved
4~24 MHz HXT or
32.768 kHz LXT
000
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.4-3 SysTick Clock Control Block Diagram
May 22, 2014
Page 32 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.4.3 ISP Clock Source Selection
The clock source of ISP is from AHB clock (HCLK). Please refer to the register AHBCLK.
HCLK
ISP (In System
Programmer)
ISP_EN (AHBCLK[2])
Figure 6.4-4 AHB Clock Source for HCLK
6.4.4 Module Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
Please refer to the CLKSEL1 and APBCLK register description in section Error! Reference
source not found..
PCLK
Watch Dog Timer
WDT_EN (APBCLK[0])
Timer0
TMR0_EN (APBCLK[2])
Timer1
TMR1_EN (APBCLK[3])
Frequency Divider
FDIV_EN (APBCLK[6])
I2C
I2C_EN (APBCLK[8])
SPI
SPI_EN (APBCLK[12])
UART
UART_EN (APBCLK[16])
PWM01
PWM01_EN (APBCLK[20])
PWM23
PWM23_EN (APBCLK[21])
PWM45
PWM45_EN (APBCLK[22])
ADC
ADC_EN (APBCLK[28])
ACMP
CMP_EN (APBCLK[30])
Figure 6.4-5 Peripherals Clock Source Selection for PCLK
May 22, 2014
Page 33 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Ext. CLK (HXT Or LXT)
HIRC
No
LIRC
Yes
Yes
Yes
No
PCLK
Yes
Yes
Yes
Yes
Yes
No
WDT
Timer0
Timer1
I2C
Yes
Yes
Yes
No
Yes
Yes
No
SPI
No
No
No
UART
PWM
ADC
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
No
No
ACMP
No
Table 6.4-1 Peripheral Clock Source Selection Table
6.4.5 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripheral clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
10 kHz internal low speed oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock (If PD_32K = 1 and
XTLCLK_EN[1:0] = 10)
Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)
Watchdog Clock
Timer 0/1 Clock
6.4.6 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to the CKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
if DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CKO pin directly.
May 22, 2014
Page 34 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
22.1184 MHz
HIRC
11
10
01
00
HCLK
FRQDIV_CLK
Reserved
4~24 MHz HXT or
32.768 kHz LXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
Figure 6.4-6 Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
FSEL
(FRQDIV[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
FRQDIV_CLK
DIVIDER1
(FRQDIV[5])
1/2
1/22
1/23
…...
1/215 1/216
000
000
0
1
:
16 to 1
MUX
0
1
:
CKO
111
111
0
1
Figure 6.4-7 Block Diagram of Frequency Divider
May 22, 2014
Page 35 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.5 Analog Comparator (ACMP)
6.5.1 Overview
The NuMicro Mini51 Series contains two comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input greater than
negative input, otherwise the output is 0. Each comparator can be configured to generate interrupt
when the comparator output value changes.
6.5.2 Features
Analog input voltage range: 0 ~ AVDD
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
May 22, 2014
Page 36 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.6 Analog-to-Digital Converter (ADC)
6.6.1 Overview
The NuMicro Mini51 series contains one 10-bit successive approximation analog-to-digital
converters (SAR A/D converter) with eight input channels. The A/D converters can be started by
software, external pin (STADC/P3.2) or PWM trigger.
6.6.2 Features
Analog input voltage range: 0 ~ Analog Supply Voltage from AVDD
10-bit resolution and 8-bit accuracy is guaranteed
Up to eight single-end analog input channels
300 KSPS (AVDD 4.5V - 5.5V) and 200 KSPS (AVDD 2.5V - 5.5V) conversion rate
An A/D conversion is performed one time on a specified channel
An A/D conversion can be started by:
Software write 1 to ADST bit
External pin STADC
PWM trigger with optional start delay period
Each conversion result is held in data register with valid and overrun indicators
Conversion results can be compared with specified value and user can select whether
to generate an interrupt when conversion result matches the compare register setting
Channel 7 supports 2 input sources: External analog voltage and internal fixed band-
gap voltage
May 22, 2014
Page 37 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.7 Flash Memory Controller (FMC)
6.7.1 Overview
The NuMicro Mini51TM series is equipped with 4K/8K/16K bytes on chip embedded flash memory
for application program (APROM) that can be updated through ISP procedure. In-System-
Programming (ISP) and In-Application-Programming (IAP) enable user to update program
memory when chip is soldered on PCB. After chip power on CortexTM-M0 CPU fetches code from
APROM or LDROM decided by boot select (CBS) in CONFIG0. By the way, the NuMicro Mini51TM
series also provides Data Flash region that is shared with APROM and its start address is
configurable and defined by user in CONFIG1.
6.7.2 Features
Running up to 24 MHz with zero wait state for discontinuous address read access
4/8/16 Kbytes application program memory (APROM)
2 Kbytes in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address
All embedded flash memory supports 512 bytes page erase
In System Program (ISP)/In Application Program (IAP) to update on chip flash memory
May 22, 2014
Page 38 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.8 General Purpose I/O (GPIO)
6.8.1 Overview
The NuMicro Mini51TM series have up to 30 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 30 pins are arranged in 6 ports named
as P0, P1, P2, P3, P4 and P5. Each of the 30 pins is independent and has the corresponding
register bits to control the pin mode function and data.
The I/O type of each pin can be configured by software individually as Input, Push-pull output,
Open-drain output, or Quasi-bidirectional mode. For Quasi-bidirectional mode, each I/O pin is
equipped with a very weak individual pull-up resistor about 110 kΩ ~ 300 kΩ for VDD is from 5.0 V
to 2.5 V.
6.8.2 Features
Four I/O modes:
Input-only with high impendence
Push-pull output
Open-drain output
Quasi-bidirectional
TTL/Schmitt trigger input mode selected by Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function
High driver and high sink I/O mode support
Configurable default I/O mode of all pins after reset by CIOINI (Config0[10]) setting
CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOINI = 1, all GPIO pins in Input tri-state mode after chip reset (default)
May 22, 2014
Page 39 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.9 I2C Serial Interface Controller (I2C)
6.9.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously. The I2C also supports Power-down wake up function.
6.9.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus include:
Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter that requests the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
External pull-up needed for higher output pull-up speed
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address registers with mask option)
Supports Power-down wake-up function
Support FIFO function
May 22, 2014
Page 40 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.10 Enhanced PWM Generator
6.10.1 Overview
The NuMicro Mini51 series has built one PWM unit which is specially designed for motor driving
control applications. The PWM unit supports six PWM generators which can be configured as six
independent PWM outputs, PWM0~PWM5, or as three complementary PWM pairs, (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5) with three programmable dead-zone generators.
Every complementary PWM pairs share one 8-bit prescaler. There are six clock dividers providing
five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. Each PWM output has
independent 16-bit counter for PWM period control, and 16-bit comparators for PWM duty control.
The six PWM generators provide twelve independent PWM interrupt flags which are set by
hardware when the corresponding PWM period counter comparison matched period and duty.
Each PWM interrupt source with its corresponding enable bit can request PWM interrupt. The
PWM generators can be configured as One-shot mode to produce only one PWM cycle signal or
Auto-reload mode to output PWM waveform continuously.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be loaded into the 16-bit down
counter/ comparator at the end of current period. The double buffering feature avoids glitch at
PWM outputs.
Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. In order to
control motor more precisely, we provide some registers that not only configure PWM but also
Timer, ADC and ACMP, by doing so, it can save more CPU time and control motor with ease
especially in BLDC.
6.10.2 Features
The PWM unit supports the following features:
Independent 16-bit PWM duty control units with maximum six port pins:
Six independent PWM outputs – PWM0, PWM1, PWM2, PWM3, PWM4, and
PWM5
Three complementary PWM pairs, with each pin in a pair mutually complement
to each other and capable of programmable dead-zone insertion – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0,
PWM1), (PWM2, PWM3) and (PWM4, PWM5)
Group control bit – PWM2 and PWM4 are synchronized with PWM0, PWM3 and
PWM5 are synchronized with PWM1
One-shot (only support edge alignment mode) or Auto-reload mode PWM
Up to 16-bit resolution
Supports Edge-aligned and Center-aligned mode
Programmable dead-zone insertion between complementary paired PWMs
Each pin of PWM0 to PWM5 has independent polarity setting control
Hardware fault brake protections
May 22, 2014
Page 41 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Two Interrupt source types:
Synchronously requested at PWM frequency when down counter
comparison matched (edge- and center-aligned mode) or underflow (edge-
aligned mode)
Requested when external fault brake asserted
BKP0: EINT0 or CPO1
BKP1: EINT1 or CPO0
The PWM signals before polarity control stage are defined in the view of positive logic.
The PWM ports is active high or active low are controlled by polarity control register.
Supports independently rising CMR matching (in Center-aligned mode), CNR
matching (in Center-aligned mode), falling CMR matching, period matching to trigger
ADC conversion
Timer comparing matching event trigger PWM to do phase change in BLDC
application
Supports ACMP output event trigger PWM to force PWM output at most one period
low, this feature is usually for step motor control
Provides interrupt accumulation function
May 22, 2014
Page 42 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.11 Serial Peripheral Interface (SPI)
6.11.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction
interface. The SPI controller performing a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
SPI controller can be configured as a master or a slave device.
6.11.2 Features
•
•
•
•
•
•
•
Supports Master or Slave mode operation
Configurable transfer bit length
Provides four 32-bit FIFO buffers
Supports MSB first or LSB first transfer
Supports byte reorder function
Supports byte or word suspend mode
Supports Slave 3-wire mode
May 22, 2014
Page 43 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.12 Timer Controller (TMR)
6.12.1 Overview
The Timer Controller includes two 32-bit timers, TIMER0 ~ TIMER1, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.12.2 Features
Two sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each channel (TMR0_CLK, TMR1_CLK)
Provides four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224); T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external pin (T0, T1)
24-bit capture value is readable through TCAP (Timer Capture Data Register)
Supports external capture pin (T0EX, T1EX) for interval measurement
Supports internal signal (CPO0, CPO1) for interval measurement
Supports external capture pin (T0EX, T1EX) to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
May 22, 2014
Page 44 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.13 UART Controller (UART)
6.13.1 Overview
The NuMicro Mini51 series provides one channel of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART, and supports
flow control function. The UART Controller performs a serial-to-parallel conversion on data
received from the peripheral, and a parallel-to-serial conversion on data transmitted from the
CPU. The UART controller also supports IrDA SIR Function, and RS-485 function mode.
6.13.2 Features
Full duplex, asynchronous communications
Separates 16-byte receive and transmitted FIFO for data payloads
Supports hardware auto flow control, flow control function (CTS, RTS) and
programmable RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY(UA_TOR[15:8]) register
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit
Programmable stop bit, 1, 1.5, or 2 stop bit
Supports IrDA SIR function mode
Supports 3/16-bit duration for normal mode
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enable to program RTS pin to control RS-485
transmission direction directly
May 22, 2014
Page 45 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
6.14 Watchdog Timer (WDT)
6.14.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.14.2 Features
18-bit free running up counter for Watchdog Timer time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period is
104 ms ~ 26.3168 s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer time-out wake-up function only if WDT clock source is selected
as 10 kHz
May 22, 2014
Page 46 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
7
ARM® CORTEX™-M0 CORE
7.1 Overview
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other CortexTM-M
profile processors. The profile supports two modes - Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset and can be entered as a result of an exception return.
The following figure shows the functional controller of the processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
unit
Cortex-M0
Processor
core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 7.1-1 Functional Block Diagram
7.2 Features
A low gate count processor
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model:
This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant
exception model that enables the use of pure C functions as interrupt handlers
Low power Idle mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC
May 22, 2014
Page 47 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Idle
mode
Debug support
Four hardware breakpoints
Two watch points
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
7.3 System Timer (SysTick)
The Cortex™-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When
the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on
reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer to count from the SYST_RVR value
rather than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
May 22, 2014
Page 48 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
8
APPLICATION CIRCUIT
DVCC
[1]
AVCC
SPISS
SPICLK
MISO
AVDD
CS
VDD
CLK
MISO
MOSI
SPI Device
FB
FB
DVCC
VDD
VSS
MOSI
Power
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
AVSS
4.7K
CLK
DIO
SCL
SDA
VDD
I2C Device
VDD
VSS
ICE_DAT
ICE_CLK
SWD
Interface
/RESET
VSS
20p
20p
XTAL1
XTAL2
Mini5xxDE
LQFP48
Crystal
4~24 MHz
crystal
DVCC
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
/RESET
RX
TX
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
Note: For the SPI device, the Mini5x chip supply
voltage must be equal to SPI device working
voltage. For example, when the SPI Flash
working voltage is 3.3 V, the Mini5x chip supply
voltage must also be 3.3V.
LDO
May 22, 2014
Page 49 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
9
MINI51XXDE ELECTRICAL CHARACTERISTICS
9.1
Absolute Maximum Ratings
Symbol Parameter
Min
-0.3
Max
+7.0
Unit
V
VDD− VSS DC Power Supply
VIN
Input Voltage
VSS -0.3
VDD +0.3
V
1/tCLCL
TA
Oscillator Frequency
4
24
MHz
Operating Temperature
-40
+105
℃
℃
TST
IDD
ISS
Storage Temperature
-55
+150
120
120
35
Maximum Current into VDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects
the life and reliability of the device.
9.2
DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25°C)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
Operation voltage
2.5
-
5.5
V
VDD = 2.5V ~ 5.5V up to 24 MHz
VSS / AVSS
VLDO
Power Ground
-0.3
-
-
V
LDO Output Voltage
1.62
1.20
1.8
1.98
1.28
V
V
VDD ≥ 2.5 V
1.24
VDD = 2.5V ~ 5.5V, TA = 25°C
VBG
Band-gap Voltage
VDD = 2.5V ~ 5.5V,
1.18
-0.3
1.24
0
1.32
0.3
V
V
TA = -40°C~105°C
Allowed Voltage
Difference for VDD and
AVDD
VDD-AVDD
-
Operating Current
Normal Run Mode
HCLK = 24 MHz
while(1){}
VDD
HXT
HIRC
5.5V
24 MHz
Disable
Enabled
IDD1
-
9.2
-
mA
Executed from Flash
All digital
modules
May 22, 2014
Page 50 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
5.5V
24 MHz
Disabled
Disabled
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
-
-
-
-
-
-
-
7.0
7.1
5.0
6.1
3.9
6.0
3.9
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
3.3V
24 MHz
Disable
Enabled
All digital
modules
VDD
HXT
HIRC
3.3 V
24 MHz
Disabled
Disabled
All digital
modules
VDD
HXT
HIRC
5.5V
Disabled
Enabled
Enabled
All digital
modules
.
VDD
HXT
HIRC
5.5V
Disabled
Enabled
Disabled
Operating Current
Normal Run Mode
HCLK =22.1184
MHz
All digital
modules
while(1){}
VDD
HXT
HIRC
3.3V
Executed from Flash
Disabled
Enabled
Enabled
All digital
modules
VDD
HXT
HIRC
3.3V
Disabled
Enabled
Disabled
All digital
modules
May 22, 2014
Page 51 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
5.5 V
12 MHz
Disabled
Enabled
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
-
-
-
-
-
-
-
5.5
4.3
3.9
2.8
3.2
2.8
1.8
-
-
-
-
-
-
-
mA
All digital
modules
VDD
HXT
HIRC
5.5 V
12 MHz
Disabled
Disabled
mA
mA
Operating Current
Normal Run Mode
HCLK = 12MHz
while(1){}
All digital
modules
VDD
HXT
HIRC
3.3 V
Executed from Flash
12 MHz
Disabled
Enabled
All digital
modules
VDD
HXT
HIRC
3.3 V
12 MHz
Disabled
Disabled
mA
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
5.5 V
4 MHz
Disabled
Enabled
All digital
modules
Operating Current
Normal Run Mode
HCLK =4 MHz
VDD
HXT
HIRC
5.5 V
4 MHz
Disabled
Disabled
while(1){}
All digital
modules
Executed from Flash
VDD
HXT
HIRC
3.3 V
4 MHz
Disabled
Enabled
All digital
modules
May 22, 2014
Page 52 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
3.3 V
4 MHz
IDD16
-
1.4
-
mA
Disabled
Disabled
All digital
modules
VDD
HXT
5.5 V
Disabled
ꢀisabled
Enabled
Enabled
HIRC
LIRC
IDD17
-
225
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
5.5 V
Disabled
Disabled
Enabled
Disabled
IDD18
-
225
-
μA
HIRC
LIRC
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
All digital
modules
VDD
HXT
3.3 V
Executed from Flash
Disaꢀled
Disabled
Enabled
Enabled
HIRC
LIRC
IDD19
-
200
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
3.3 V
Disabled
Disabled
Enabled
Disaꢀled
IDD20
-
200
-
μA
HIRC
LIRC
All digital
modules
VDD
HXT
HIRC
5.5V
Operating Current
Idle Mode
24 MHz
Disable
Enabled
IIDLE1
-
7.1
-
mA
HCLK = 24MHz
All digital
modules
May 22, 2014
Page 53 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
5.5V
24 MHz
Disabled
Disabled
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
-
-
-
-
-
-
-
4.9
5.1
2.9
4.1
2.0
4.1
1.9
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
3.3V
24 MHz
Disable
Enabled
All digital
modules
VDD
HXT
HIRC
5.5V
24 MHz
Disabled
Disabled
All digital
modules
VDD
HXT
HIRC
5.5V
Disabled
Enabled
Enabled
All digital
modules
.
VDD
HXT
HIRC
5.5V
Disabled
Enabled
Disabled
All digital
modules
Operating Current
Idle Mode
HCLK=22.1184 MHz
VDD
HXT
HIRC
3.3V
Disabled
Enabled
Enabled
All digital
modules
VDD
HXT
HIRC
3.3V
Disabled
Enabled
Disabled
All digital
modules
May 22, 2014
Page 54 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
5.5 V
12 MHz
Disabled
Enabled
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
-
-
-
-
-
-
-
4.4
3.3
2.9
1.8
2.9
2.5
1.5
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
5.5 V
12 MHz
Disabled
Disabled
All digital
modules
Operating Current
Idle Mode
HCLK =12 MHz
VDD
HXT
HIRC
3.3 V
12 MHz
Disabled
Enabled
All digital
modules
VDD
HXT
HIRC
3.3 V
12 MHz
Disabled
Disabled
All digital
modules
VDD
HXT
HIRC
5.5 V
4 MHz
Disabled
Enabled
All digital
modules
VDD
HXT
HIRC
5.5 V
4 MHz
Operating Current
Idle Mode
Disabled
Disabled
HCLK =4 MHz
All digital
modules
VDD
HXT
HIRC
3.3 V
4 MHz
Disabled
Enabled
All digital
modules
May 22, 2014
Page 55 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
HXT
HIRC
3.3 V
4 MHz
IIDLE16
-
1.1
-
mA
Disabled
Disabled
All digital
modules
VDD
HXT
5.5 V
Disabled
Disabled
Enabled
Enabled
HIRC
LIRC
IIDLE17
-
225
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
5.5 V
Disabled
Disabled
Enabled
Disabled
IIDLE18
IIDLE19
IIDLE20
-
-
-
225
200
200
-
-
-
μA
μA
μA
HIRC
LIRC
All digital
modules
Operating Current
Idle Mode
at 10 kHz
VDD
HXT
3.3 V
Disabled
Disabled
Enabled
Enabled
HIRC
LIRC
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
3.3 V
Disabled
Disabled
Enabled
Disabled
HIRC
LIRC
All digital
modules
VDD = 5.5 V, All oscillators and analog
blocks turned off.
IPWD1
-
-
10
9
-
-
µA
µA
Standby Current
Power-down Mode
VDD = 3.3 V, All oscillators and analog
blocks turned off.
(Deep Sleep Mode)
IPWD2
Logic 0 Input Current
P0/1/2/3/4/5 (Quasi-
bidirectional Mode)
IIL
-
-70
-75
VDD = 5.5 V, VIN = 0V
µA
May 22, 2014
Page 56 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Logic 1 to 0
Transition Current
P0/1/2/3/4/5 (Quasi-
bidirectional Mode)
[*3]
ITL
-
-690
-
-750
+1
VDD = 5.5 V, VIN = 2.0V
µA
VDD = 5.5 V, 0 < VIN< VDD
Input Leakage
Current P0/1/2/3/4/5
ILK
-1
µA
Open-drain or input only mode
Input Low Voltage
P0/1/2/3/4/5 (TTL
Input)
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VIL1
V
Input High Voltage
P0/1/2/3/4/5 (TTL
Input)
VDD + 0.3
VDD + 0.3
0.8
VIH1
VIL3
VIH3
V
V
Input Low Voltage
XTAL1[*2]
0
0.4
3.5
2.4
VDD + 0.3
VDD + 0.3
V
Input High Voltage
XTAL1[*2]
Negative-going
Threshold
VILS
-0.3
-
-
0.2VDD
V
V
-
-
(Schmitt Input),
/RESET
Positive-going
Threshold
VIHS
RRST
VILS
0.7 VDD
VDD + 0.3
150
(Schmitt Input),
/RESET
Internal /RESETPin
Pull-up Resistor
40
kΩ VDD = 2.5 V ~ 5.5V
Negative-going
Threshold
-0.3
-
-
0.3VDD
V
V
-
-
(Schmitt input),
P0/1/2/3/4/5
Positive-going
Threshold
VIHS
0.7 VDD
VDD + 0.3
(Schmitt input),
P0/1/2/3/4/5
ISR11
ISR12
ISR13
ISR21
ISR22
ISR23
ISK11
ISK12
-300
-50
-40
-20
-3
-400
-80
-73
-26
-5
-
-
-
-
-
-
-
-
VDD = 4.5 V, VS = 2.4 V
VDD = 2.7 V, VS = 2.2 V
VDD = 2.5 V, VS = 2.0 V
µA
µA
µA
Source Current
P0/1/2/3/4/5 (Quasi-
bidirectional Mode)
mA VDD = 4.5 V, VS = 2.4 V
mA VDD = 2.7 V, VS = 2.2 V
mA VDD = 2.5 V, VS = 2.0 V
mA VDD = 4.5 V, VS = 0.45 V
mA VDD = 2.7 V, VS = 0.45 V
Source Current
P0/1/2/3/4/5 (Push-
pull Mode)
-2.5
10
-5
15
Sink Current
P0/1/2/3/4/5 (Quasi-
bidirectional, Open-
6
9
May 22, 2014
Page 57 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
Drain and Push-pull
Mode)
ISK13
5
8
-
mA VDD = 2.5 V, VS = 0.45 V
Notes:
1. /RESET pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0, P1, P2, P3, P4 and P5 can source a transition current when they are being externally
driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value
when VIN approximates to 2V.
9.3
AC Electrical Characteristics
9.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Clock High Time
Min
Typ
Max
Unit
Test Conditions
tCHCX
tCLCX
tCLCH
tCHCL
10
10
2
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
-
15
15
2
9.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
-
-
-
TA
℃
-
2.5
1.0
-
mA
mA
12 MHz, VDD = 5.5V
12 MHz, VDD = 3.3V
-
IHXT
Operating Current
Clock Frequency
-
-
fHXT
4
24
MHz
May 22, 2014
Page 58 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
9.3.3 Typical Crystal Application Circuits
Crystal
C1
C2
4MHz ~ 24 MHz
10~20 pF
10~20 pF
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 9-1Mini5xDE Typical Crystal Application Circuit
9.3.4 22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VHRC
Supply Voltage
1.62
-
1.8
1.98
V
-
-
Center Frequency
22.1184
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40℃~105℃
-2
-
-
+2
-
%
V
DD=2.5 V~ 5.5 V
TA = 25 ℃,VDD = 5 V
μA
IHRC
Operating Current
700
May 22, 2014
Page 59 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
HIRC oscillator accuracy vs. temperature
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
Max
Min
-40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100110
TA ℃
9.3.5 10 kHz Internal Low Speed RC Oscillator(LIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VLRC
Supply Voltage
2.5
-
-
5.5
-
V
-
-
Center Frequency
10
kHz
VDD=2.5V~ 5.5V
-10
-40
-
-
+10
+40
%
%
TA = 25℃
fLRC
Oscillator Frequency
VDD=2.5V~ 5.5V
TA = -40℃~+105℃
May 22, 2014
Page 60 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
9.4
Analog Characteristics
9.4.1 10-bit SARADC
Symbol Parameter
Min
Typ
Max
Unit
Bit
Test Condition
-
DNL
INL
EO
EG
EA
-
Resolution
-
-
-
-
-
-
-
10
-
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
-1~1.5 -1~+2.5
LSB
LSB
LSB
LSB
LSB
-
-
±1
±2
2
-
1
-
Gain Error (Transfer Gain)
Absolute Error
-1
-3
4
-
3
-
Monotonic
Guaranteed
-
-
-
-
-
-
4.2
2.8
AVDD = 4.5~5.5 V
AVDD =2.5~5.5 V
AVDD = 4.5~5.5 V
AVDD = 2.5~5.5 V
FADC
ADC Clock Frequency
MHz
-
-
-
300
200
kSPS
kSPS
1/FADC
1/FADC
V
FS
Sample Rate (FADC/TCONV)
TACQ
TCONV
AVDD
IDDA
N+1
N+14
-
Acquisition Time (Sample Stage)
Total Conversion Time
Supply Voltage
N is sampling counter,
N=0,1,2, 4,8, 16,32, 4,
128, 256,1024
2.5
5.5
-
μA
-
0
-
600
-
-
AVDD = 5.5 V
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
Input Load
VIN
AVDD
V
-
-
-
CIN
3.2
6
-
-
pF
kΩ
RIN
-
Note: ADC voltage reference is same with AVDD
May 22, 2014
Page 61 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
1023
1022
1021
1020
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
1023
Analog input voltage
(LSB)
Offset Error
EO
9.4.2 LDO & Power Management
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Min
2.5
Typ
Max
5.5
Unit
V
Test Condition
-
-
-
VLDO
TA
1.62
-40
1.8
25
1.98
105
V
℃
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
9.4.3 Low Voltage Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AVDD
Supply Voltage
0
-
5.5
V
-
May 22, 2014
Page 62 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
℃
μA
V
TA
Temperature
-40
-
25
1
105
5
-
ILVR
Quiescent Current
AVDD =5.5V
TA=25℃
TA=-40℃
TA =105℃
1.90
1.70
2.00
2.00
1.90
2.20
2.10
2.05
2.45
VLVR
Threshold Voltage
V
V
9.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Min
0
Typ
Max
5.5
Unit
V
Test Condition
-
Supply Voltage
Temperature
-
℃
-40
-
25
105
-
IBOD
Quiescent Current
-
140
μA
V
V
V
V
V
V
V
V
AVDD =5.5V
4.2
3.5
2.5
2.0
4.3
3.5
2.5
2.0
4.38
3.68
2.68
2.18
4.52
3.8
4.55
3.85
2.85
2.35
4.75
4.05
3.05
2.55
BOD_VL [1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
BOD_VL [1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
Brown-out Detector
(Falling edge)
VBOD
Brown-out Detector
(Rising edge)
VBOD
2.77
2.25
9.4.5 Power-on Reset
Symbol
TA
Parameter
Min
-40
1.6
Typ
25
2
Max
105
2.4
Unit
℃
Test Condition
Temperature
-
-
VPOR
Reset Voltage
V
VDD Start Voltage to Ensure
Power-on Reset
VPOR
-
-
-
100
-
mV
VDD Raising Rate to Ensure
Power-on Reset
RRVDD
0.025
V/ms
Minimum Time for VDD Stays
at VPOR to Ensure Power-
on Reset
tPOR
0.5
-
-
ms
May 22, 2014
Page 63 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
VDD
tPOR
RRVDD
VPOR
Time
Figure 9-2Power-up Ramp Condition
9.4.6 Comparator
Symbol
VCMP
TA
Parameter
Min
2.5
Typ
Max
5.5
Unit
V
Test Condition
Supply Voltage
Temperature
-
℃
-40
-
25
40
10
-
105
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
80
20
μA
mV
V
AVDD=5V
-
-
-
-
0.1
0.1
40
AVDD -0.1
AVDD– 0.1
-
Input Common Mode Range
DC Gain
-
V
70
dB
V
COM=1.2 V,
TPGD
Propagation Delay
-
200
-
ns
VDIFF=0.1 V
VHYS
TSTB
Hysteresis
Stable time
-
-
±30
-
±60
1
mV
VCOM=1.2 V
μs
May 22, 2014
Page 64 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
9.5
Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
Typ
1.8
-
Max
Unit
V
Test Condition
[2]
VFLA
1.62
1.98
NENDUR
TRET
20,000
-
-
-
-
-
-
-
cycles[1]
year
ms
TA =85℃
Data Retention
Page Erase Time
Program Time
Read Current
Program Current
Erase Current
10
-
-
TERASE
TPROG
IDD1
20
60
6
-
us
-
mA
IDD2
-
8
mA
IDD3
-
12
mA
Notes:
1. Number of program/erase cycles.
2. FLA is source from chip LDO output voltage.
V
3. Guaranteed by design, not test in production.
May 22, 2014
Page 65 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
10 PACKAGE DIMENSIONS
10.1 48-pin LQFP
May 22, 2014
Page 66 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
10.2 33-pin QFN (4 mm x 4 mm)
May 22, 2014
Page 67 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
10.3 33-pin QFN (5 mm x 5 mm)
May 22, 2014
Page 68 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
10.4 20-pin TSSOP
May 22, 2014
Page 69 of 70
Revision 1.01
NuMicro MINI51 DE Series Datasheet
11 REVISION HISTORY
Revision
Date
Description
1.00
Oct. 18, 2013
May 20, 2014
Preliminary version
1.01
Supported the Mini54FHC for NuMicro Mini51 series.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
May 22, 2014
Page 70 of 70
Revision 1.01
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明