MINI55LDE [NUVOTON]
ARM® Cortex®-M0 32-bit Microcontroller;
| 型号： | MINI55LDE |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总74页 (文件大小：1564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mini55
ARM® Cortex® -M0
32-bit Microcontroller
NuMicro® Family
Mini55 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Apr 18, 2017
Page 1 of 74
Rev.1.00
Mini55
Table of Contents
1
2
3
4
GENERAL DESCRIPTION .......................................................................7
FEATURES .........................................................................................8
ABBREVIATIONS................................................................................11
PARTS INFORMATION LIST AND PIN CONFIGURATION ..............................12
NuMicro® Mini55 Series Naming Rule.............................................................12
NuMicro® Mini55 Series Product Selection Guide...............................................13
PIN CONFIGURATION ..............................................................................14
4.1
4.2
4.3
4.3.1
4.3.2
LQFP 48-pin ...................................................................................................14
QFN 33-pin ....................................................................................................15
Pin Description ........................................................................................16
4.4
5.1
6.1
5
6
BLOCK DIAGRAM ...............................................................................20
NuMicro® Mini55 Block Diagram ...................................................................20
Functional Description...........................................................................21
ARM® Cortex® -M0 Core..............................................................................21
6.1.1
6.1.2
Overview .......................................................................................................21
Features........................................................................................................21
System Manager......................................................................................23
Overview .......................................................................................................23
System Reset..................................................................................................23
Power Modes and Wake-up Sources......................................................................29
System Power Architecture .................................................................................31
System Memory Mapping ...................................................................................32
Memory Organization ........................................................................................32
System Timer (SysTick) .....................................................................................34
Nested Vectored Interrupt Controller (NVIC) .............................................................35
System Control Registers (SCB) ...........................................................................38
Clock Controller .......................................................................................39
Overview .......................................................................................................39
Auto-trim........................................................................................................41
System Clock and SysTick Clock ..........................................................................41
Peripherals Clock Source Selection .......................................................................42
Power-down Mode Clock ....................................................................................43
Frequency Divider Output ...................................................................................43
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
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6.4
Flash Memory Controller (FMC)....................................................................45
Overview .......................................................................................................45
Features........................................................................................................45
General Purpose I/O (GPIO)........................................................................46
Overview .......................................................................................................46
Features........................................................................................................46
Timer Controller (TMR) ..............................................................................47
Overview .......................................................................................................47
Features........................................................................................................47
Enhanced PWM Generator .........................................................................48
Overview .......................................................................................................48
Features........................................................................................................48
Watchdog Timer (WDT)..............................................................................51
Overview .......................................................................................................51
Features........................................................................................................51
UART Controller (UART) ............................................................................52
Overview .......................................................................................................52
Features........................................................................................................52
I2C Serial Interface Controller (I2C) ................................................................53
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1 Overview .......................................................................................................53
6.10.2 Features........................................................................................................53
6.11
Serial Peripheral Interface (SPI)....................................................................54
6.11.1 Overview .......................................................................................................54
6.11.2 Features........................................................................................................54
6.12
Analog-to-Digital Converter (ADC).................................................................55
6.12.1 Overview .......................................................................................................55
6.12.2 Features........................................................................................................55
6.13
Analog Comparator (ACMP) ........................................................................56
6.13.1 Overview .......................................................................................................56
6.13.2 Features........................................................................................................56
6.14
Hardware Divider (HDIV) ............................................................................57
6.14.1 Overview .......................................................................................................57
6.14.2 Features........................................................................................................57
7
8
APPLICATION CIRCUIT........................................................................58
ELECTRICAL CHARACTERISTICS ..........................................................59
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8.1
8.2
8.3
Absolute Maximum Ratings .........................................................................59
DC Electrical Characteristics........................................................................60
AC Electrical Characteristics........................................................................65
External Input Clock ..........................................................................................65
External 4~24 MHz High Speed Crystal (HXT) ..........................................................65
Typical Crystal Application Circuits ........................................................................65
48 MHz Internal High Speed RC Oscillator (HIRC) .....................................................66
10 kHz Internal Low Speed RC Oscillator (LIRC) .......................................................66
Analog Characteristics ...............................................................................67
10-bit SARADC................................................................................................67
LDO & Power Management.................................................................................68
Brown-out Detector...........................................................................................68
Power-on Reset...............................................................................................69
Comparator ....................................................................................................69
Flash DC Electrical Characteristics ................................................................70
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
9
PACKAGE DIMENSIONS ......................................................................71
48-pin LQFP (7 mm x 7 mm)........................................................................71
33-pin QFN (4 mm x 4 mm) .........................................................................72
9.1
9.3
10 REVISION HISTORY............................................................................73
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List of Figures
Figure 4.1-1 NuMicro® Mini55 Series Selection Code ................................................................... 12
Figure 4.3-1 NuMicro® Mini55 Series LQFP 48-pin Diagram......................................................... 14
Figure 4.3-2 NuMicro® Mini55 Series QFN 33-pin Diagram .......................................................... 15
Figure 5.1-1 NuMicro® Mini55 Series Block Diagram .................................................................... 20
Figure 6.1-1 Functional Block Diagram.......................................................................................... 21
Figure 6.2-1 System Rese Resources ........................................................................................... 24
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 26
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 26
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 27
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 28
Figure 6.2-6 Power Mode State Machine ...................................................................................... 29
Figure 6.2-7 NuMicro® Mini55 Series Power Architecture Diagram .............................................. 31
Figure 6.3-1 Clock Generator Block Diagram ................................................................................ 39
Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 40
Figure 6.3-3 System Clock Block Diagram .................................................................................... 41
Figure 6.3-4 SysTick Clock Control Block Diagram....................................................................... 42
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK ................................................... 42
Figure 6.3-6 Clock Source of Frequency Divider........................................................................... 44
Figure 6.3-7 Block Diagram of Frequency Divider ......................................................................... 44
Figure 6.7-1 Application Circuit Diagram ....................................................................................... 50
Figure 8-1 Mini55 Typical Crystal Application Circuit..................................................................... 66
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List of Tables
Table 3-1 List of Abbreviations....................................................................................................... 11
Table 4.2-1 NuMicro® Mini55 Series Product Selection Guide...................................................... 13
Table 4.4-1 NuMicro® Mini55 Series Pin Description..................................................................... 19
Table 6.2-1 Reset Value of Registers ............................................................................................ 25
Table 6.2-2 Power Mode Difference Table .................................................................................... 29
Table 6.2-3 Clocks in Power Modes .............................................................................................. 30
Table 6.2-4 Condition of Entering Power-down Mode Again......................................................... 31
Table 6.2-5 Memory Mapping Table .............................................................................................. 32
Table 6.2-6 Address Space Assignments for On-Chip Modules ................................................... 33
Table 6.2-7 Exception Model ......................................................................................................... 36
Table 6.2-8 System Interrupt Map Vector Table............................................................................ 37
Table 6.2-9 Vector Table Format ................................................................................................... 37
Table 6.3-1 Peripheral Clock Source Selection Table ................................................................... 43
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1
GENERAL DESCRIPTION
The NuMicro® Mini55 series 32-bit microcontroller is embedded with ARM® Cortex® -M0 core for
industrial control and applications which require high performance, high integration, and low cost.
The Cortex® -M0 is the newest ARM® embedded processor with 32-bit performance at a cost
equivalent to the traditional 8-bit microcontroller.
The Mini55 series can run up to 48 MHz and operate at 2.1V ~ 5.5V, -40℃ ~ 105℃, and thus can
afford to support a variety of industrial control and applications which need high CPU
performance. The Mini55 series offers 17.5K-bytes embedded program flash, size configurable
Data Flash (shared with program flash), 2K-byte flash for the ISP, and 2K-byte SRAM.
Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC,
Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the
Mini55 series in order to reduce component count, board space and system cost. These useful
functions make the Mini55 series powerful for a wide range of applications.
Additionally, the Mini55 series is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update the program memory without removing
the chip from the actual end product. The Mini55 series also supports In-Application-Programming
(IAP) function, user switches the code executing without the chip reset after the embedded flash
updated.
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2
FEATURES
Core
ARM® Cortex® -M0 core running up to 48 MHz
One 24-bit system timer
Supports low power Idle mode
A single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-level of priority
Supports Serial Wire Debug (SWD) interface and two watchpoints/four
breakpoints
Built-in LDO for wide operating voltage: 2.1V to 5.5V
Memory
17.5 KB Flash memory for program memory (APROM)
Configurable Flash memory for data memory (Data Flash)
2 KB Flash for loader (LDROM)
2 KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
Switch clock sources on-the-fly
Support 4 ~ 24 MHz external high speed crystal oscillator (HXT) for precise
timing operation
Support 32.768 kHz external low speed crystal oscillator (LXT) for idle wake-up
and system operation clock
Built-in 48 MHz internal high speed RC oscillator (HIRC) for system operation
(1% accuracy at 250C, 5V)
Dynamically calibrating the HIRC OSC to 48 MHz ±2% from -40℃ to 105℃
by external 32.768K crystal oscillator (LXT)
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and
wake-up operation
I/O Port
Up to 33 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi-bidirectional input/output
Push-Pull output
Open-Drain output
Input only with high impendence
Optional Schmitt trigger input
Timer
Provides two channel 32-bit Timers; one 8-bit pre-scaler counter with 24-bit up-
timer for each timer
Supports Event Counter mode
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Supports Toggle Output mode
Supports external trigger in Pulse Width Measurement mode
Supports external trigger in Pulse Width Capture mode
Support Continuous Capture function can continuous capture 4 edge on
one signal
WDT (Watchdog Timer)
Programmable clock source and time-out period
Supports wake-up function in Power-down mode and Idle mode
Interrupt or reset selectable on watchdog time-out
PWM
Up to three built-in 16-bit PWM generators, providing six PWM outputs or three
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-time generator
for each PWM generator
PWM interrupt synchronized to PWM period
Supports edge-alignment or center-alignment
Supports fault detection
UART (Universal Asynchronous Receiver/Transmitters)
Two UART devices
Buffered receiver and transmitter, 16-byte FIFO for first UART (UART0), and 4-
byte FIFO for second UART (UART1)
Optional flow control function (CTSn and RTSn) in first UART 0 only
Supports IrDA (SIR) function
Programmable baud-rate generator up to 1/16 system clock
Supports RS-485 function
SPI (Serial Peripheral Interface)
I2C
One SPI device
Master up to 25 MHz, and Slave up to 10 MHz
Supports Master/Slave mode
Full-duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
RX latching data can be either at rising edge or at falling edge of serial clock
TX sending data can be either at rising edge or at falling edge of serial clock
Supports Byte Suspend mode in 32-bit transmission
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
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Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer
Programmable clocks allow for versatile rate control
Supports multiple address recognition (four slave addresses with mask option)
ADC (Analog-to-Digital Converter)
10-bit SAR ADC with 500 kSPS
Up to 12-ch single-end input and one internal input from band-gap
Conversion started either by software trigger or external pin trigger
Analog Comparator
Two analog comparators with programmable 16-level internal voltage reference
Built-in CRV (comparator reference voltage)
Hardware Divider
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends
to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Waiting for calculation ready automatically when reading quotient and remainder
ISP (In-System Programming), ICP (In-Circuit Programming), and IAP (In-Application-
Programming) update
BOD (Brown-out Detector)
With 8 programmable threshold levels:
4.4V/3.7V/3.0V/2.7V/2.4V/2.2V/2.0V/1.7V
Supports Brown-out interrupt and reset option
96-bit unique ID
LVR (Low Voltage Reset)
Threshold voltage level: 2.0V
Operating Temperature: -40℃~105℃
Reliability: EFT > ± 3KV, ESD HBM pass 6KV
Packages:
Green package (RoHS)
48-pin LQFP (7x7), 33-pin QFN (4x4)
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3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
AHB
APB
BOD
DAP
FIFO
FMC
GPIO
HCLK
HIRC
HXT
ICP
Analog Comparator Controller
Analog-to-Digital Converter
Advanced High-Performance Bus
Advanced Peripheral Bus
Brown-out Detection
Debug Access Port
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
48 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Circuit Programming
ISP
In System Programming
ISR
Interrupt Service Routine
LDO
LIRC
LXT
Low Dropout Regulator
10 kHz internal low speed RC oscillator (LIRC)
32.768 kHz External Low Speed Crystal Oscillator
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Phase-Locked Loop
NVIC
PCLK
PLL
PWM
SPI
Pulse Width Modulation
Serial Peripheral Interface
SPS
TMR
UART
UCID
WDT
Samples per Second
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Table 3-1 List of Abbreviations
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4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® Mini55 Series Naming Rule
ARM–Based
32-bit Microcontroller
Mini55-X X X
CPU Core
®
Corte -M0
Temperature
E: -40oC ~ +105oC
Flash ROM
55 : 17.5 KB Flash ROM
Reserved
Package Type
L: LQFP 48 7x7mm
T: QFN 33 4x4mm
Figure 4.1-1 NuMicro® Mini55 Series Selection Code
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4.2 NuMicro® Mini55 Series Product Selection Guide
Connectivity
ISP
Part Number APROM RAM Data Flash Loader
ROM
ISP
ICP
IAP
Timer
ADC
IRC
48MHz
I/O
Comp. PWM
Package
UART SPI I2C
(32-bit)
(10-bit)
MINI55LDE 17.5 KB 2 KB Configurable 2 KB
MINI55TDE 17.5 KB 2 KB Configurable 2 KB
33
29
2
2
2
2
1
1
1
1
2
2
6
6
12
12
v
v
v
v
LQFP48
QFN33(4x4)
Table 4.2-1 NuMicro® Mini55 Series Product Selection Guide
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4.3 PIN CONFIGURATION
4.3.1 LQFP 48-pin
NC
NC
1
36
35
34
33
32
31
30
29
28
27
26
25
TX1, CPP0, AIN5, P1.5
2
P0.4, SPISS,PWM5
P0.5, MOSI
P0.6, MISO
P0.7, SPICLK
NC
3
nRESET
CPN1, AIN6, P3.0
AVSS
4
5
AIN8, P5.4
6
Mini55
LQFP 48-pin
CPP1, AIN7, P3.1
CPP1, T0EX, STADC, INT0, P3.2
AIN9, CPP1, SDA, T0, P3.4
AIN10, CPP1, SCL, T1, P3.5
P3.7
7
P4.7, ICE_DAT
8
P4.6, ICE_CLK
NC
9
P2.7
10
11
12
P2.6, PWM4, CPO1
P2.5, PWM3, TX1
NC
Figure 4.3-1 NuMicro® Mini55 Series LQFP 48-pin Diagram
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4.3.2 QFN 33-pin
32 31 30 29 28 27 26 25
TX1, CPP0,AIN5, P1.5
P0.4, SPISS,PWM5
P0.5, MOSI
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
nRESET
CPN1,AIN6, P3.0
AIN8, P5.4
P0.6, MISO
P0.7, SPICLK
Mini55
QFN 33-pin
CPP1,AIN7, P3.1
P4.7, ICE_DAT
P4.6, ICE_CLK
P2.6, PWM4,CPO1
P2.5, PWM3, TX1
CPP1, T0EX,STADC,INT0, P3.2
AIN9, CPP1, SDA, T0, P3.4
AIN10, CPP1, SCL, T1, P3.5
33 VSS
9
10 11 12 13 14 15 16
Figure 4.3-2 NuMicro® Mini55 Series QFN 33-pin Diagram
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4.4 Pin Description
Pin Number
Pin Name
Pin Type
Description
LQFP
QFN
48-pin 33-pin
1
NC
Not connected
P1.5
I/O
AI
AI
O
General purpose digital I/O pin
ADC analog input pin
AIN5
2
1
ACMP0_P
TX1
Analog comparator positive input pin
UART1 transmitter output pin
The Schmitt trigger input pin for hardware device
reset. A “Low” on this pin for 768 clock counter of
Internal RC 48 MHz while the system clock is running
will reset the device. nRESET pin has an internal
pull-up resistor allowing power-on reset by simply
connecting an external capacitor to GND.
3
4
2
3
nRESET
I(ST)
P3.0
I/O
AI
AI
AP
I/O
AI
I/O
AI
AI
I/O
I
General purpose digital I/O pin
ADC analog input pin
AIN6
ACMP1_N
AVSS
Analog comparator negative input pin
Ground pin for analog circuit
General purpose digital I/O pin
ADC analog input pin
5
6
33
4
P5.4
AIN8
P3.1
General purpose digital I/O pin
ADC analog input pin
7
8
9
5
6
7
AIN7
ACMP1_P
P3.2
Analog comparator positive input pin
General purpose digital I/O pin
External interrupt 0 input pin
ADC external trigger input pin
Timer 0 external capture/reset trigger input pin
Analog comparator positive input pin
General purpose digital I/O pin
Timer 0 external event counter input pin
I2C data I/O pin
INT0
STADC
T0EX
ACMP1_P
P3.4
I
I
AI
I/O
I/O
I/O
T0
SDA
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ACMP1_P
AIN9
AI
Analog comparator positive input pin
ADC analog input pin
AI
P3.5
I/O
I/O
I/O
AI
General purpose digital I/O pin
Timer 1 external event counter input pin
I2C clock I/O pin
T1
10
8
SCL
ACMP1_P
AIN10
P3.7
Analog comparator positive input pin
ADC analog input pin
AI
11
12
13
I/O
General purpose digital I/O pin
Not connected
NC
NC
Not connected
P3.6
I/O
O
General purpose digital I/O pin
Analog comparator output pin
Frequency divider output pin
Timer 1 external capture/reset trigger input pin
ADC analog input pin
ACMP0_O
CKO
14
9
O
T1EX
AIN11
P5.1
I
AI
I/O
General purpose digital I/O pin
15
16
10
11
The output pin from the internal inverting amplifier. It
emits the inverted signal of XT_IN.
XT_OUT
P5.0
O
I/O
I
General purpose digital I/O pin
The input pin to the internal inverting amplifier. The
system clock could be from external crystal or
resonator.
XT_IN
12
33
17
18
VSS
P
P
Ground pin for digital circuit
LDO_CAP
LDO output pin
General purpose digital I/O pin
19
20
P5.5
I/O
User program must enable pull-up resistor in the
QFN-33 package.
P5.2
INT1
NC
I/O
I
General purpose digital I/O pin
External interrupt 1 input pin
Not connected
13
14
21
22
P2.2
I/O
General purpose digital I/O pin
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PWM0
P2.3
O
PWM0 output of PWM unit
General purpose digital I/O pin
PWM1 output of PWM unit
General purpose input/output digital pin
PWM2 output of PWM unit
UART1 data receiver input pin
General purpose digital I/O pin
PWM3 output of PWM unit
UART1 transmitter output pin
General purpose digital I/O pin
PWM4 output of PWM unit
Analog comparator output pin
General purpose digital I/O pin
Not connected
I/O
O
23
24
15
16
PWM1
P2.4
I/O
O
PWM2
RX1
I
P2.5
I/O
O
25
26
17
18
PWM3
TX1
O
P2.6
I/O
O
PWM4
ACMP1_O
P2.7
O
27
28
I/O
NC
P4.6
I/O
I
General purpose digital I/O pin
Serial wired debugger clock pin
General purpose digital I/O pin
Serial wired debugger data pin
Not connected
29
19
20
ICE_CLK
P4.7
I/O
I/O
30
31
32
ICE_DAT
NC
P0.7
I/O
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin
SPI serial clock pin
21
22
23
SPICLK
P0.6
General purpose digital I/O pin
SPI MISO (master in/slave out) pin
General purpose digital I/O pin
SPI MOSI (master out/slave in) pin
General purpose digital I/O pin
SPI slave select pin
33
34
MISO
P0.5
MOSI
P0.4
I/O
I/O
O
35
24
SPISS
PWM5
NC
PWM5 output of PWM unit
Not connected
36
37
P0.1
I/O
O
General purpose digital I/O pin
UART0 RTS pin
25
RTSn
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RX0
I
UART0 data receiver input pin
SPI slave select pin
SPISS
P0.0
I/O
I/O
I
General purpose digital I/O pin
UART0 CTS pin
38
26
CTSn
TX0
O
UART0 transmitter output pin
Not connected
39
40
NC
NC
Not connected
P5.3
I/O
AI
AI
P
General purpose digital I/O pin
ADC analog input pin
41
27
28
29
AIN0
ADC VREF
VDD
External voltage reference of ADC
Power supply for digital circuit
Power supply for analog circuit
General purpose digital I/O pin
ADC analog input pin
42
43
AVDD
P1.0
P
I/O
AI
AI
I/O
AI
I
44
AIN1
ACMP0_P
P1.2
Analog comparator positive input pin
General purpose digital I/O pin
ADC analog input pin
AIN2
45
30
31
32
RX
UART data receiver input pin
Analog comparator positive input pin
General purpose digital I/O pin
ADC analog input pin
ACMP0_P
P1.3
AI
I/O
AI
O
AIN3
46
TX
UART transmitter output pin
Analog comparator positive input pin
External interrupt 0 input pin
General purpose digital I/O pin
PWM5: PWM output/Capture input
Analog comparator negative input pin
UART1 data receiver input pin
General purpose digital I/O pin
ACMP0_P
INT0
AI
I
P1.4
I/O
I/O
AI
I
AIN4
47
48
ACMP0_N
RX1
P1.6
I/O
Table 4.4-1 NuMicro® Mini55 Series Pin Description
[1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin, ST:
Schmitt trigger, A: Analog input.
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5
BLOCK DIAGRAM
5.1 NuMicro® Mini55 Block Diagram
Figure 5.1-1 NuMicro® Mini55 Series Block Diagram
Apr 18, 2017
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6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
6.1.1 Overview
The Cortex® -M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processors. The profile supports two modes - Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset and can be entered as a result of an exception return.
Figure 6.1-1 shows the functional controller of the processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
unit
Cortex-M0
Processor
core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
6.1.2 Features
A low gate count processor
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model:
This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant
exception model that enables the use of pure C functions as interrupt handlers
Low power Idle mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
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NVIC
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Idle
mode
Debug support
Four hardware breakpoints
Two watch points
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Reset
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset events flags
can be read by SYS_RSTSTS register.
Hardware Reset
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD)
Software Reset
CPU Reset
Write 1 to CPURST (SYS_IPRST0[1])
Whole Chip Reset
Write 1 to SYSRESETREQ (SYS_AIRCR[2])
Write 1 to CHIPRST (SYS_IPRST0[0])
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Glitch Filter
36 us
nRESET
~50k ohm
@5v
Power On
Reset
VDD
Reset Pulse Width
3.2ms
Low Voltage
Reset
System Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown Out
Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
SYSRSTREQ Reset
AIRCR[2]
CHIP_RST Reset
SYS_IPRST0[0]
Reset Pulse Width
2 system clocks
CPU Reset
SYS_IPRST0[1]
Figure 6.2-1 System Rese Resources
There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex-M0 only; the other reset sources will reset Cortex-M0 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
POR
nRESET
WDT
LVR
BOD
CHIP
MCU
CPU
Register
SYS_RSTSTS
0x001
Bit 1 = 1
-
Bit 2 = 1
-
0x001
Bit 4 = 1
-
Bit 0 = 1
-
Bit 5 = 1
-
Bit 7 = 1
-
CHIPRST
0x0
-
(SYS_IPRST0[0])
BODEN
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
-
Reload from
CONFIG0
Reload
from
CONFIG0
-
(SYS_BODCTL[0])
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
XTLEN
0x0
0x1
0x8
0x3
0x0
-
0x0
0x1
0x8
-
0x0
0x0
0x0
0x1
0x8
-
0x0
(CLK_PWRCTL[1:0])
WDTCKEN
-
-
-
-
-
(CLK_APBCLK0[0])
HCLKSEL
0x8
0x3
0x8
-
0x8
-
0x8
-
(CLK_CLKSEL0[2:0])
WDTSEL
-
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(CLK_CLKSEL1[1:0])
XLTSTB
0x0
-
-
-
-
-
-
-
(CLK_STATUS[0])
LIRCSTB
0x0
(CLK_STATUS[3])
HIRCSTB
0x0
-
-
-
-
-
-
-
-
-
(CLK_STATUS[4])
CLKSFAIL
0x0
0x0
-
-
-
-
(CLK_STATUS[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
0x0700
-
-
-
-
BS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload from
CONFIG0
(FMC_ISPCTL[1])
ISPEN
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload from
CONFIG1
-
-
-
-
-
-
CBS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload from
CONFIG0
(FMC_ISPSTS[2:1))
VECMAP
Reload
Reload
Reload
Reload
Reload
Reload
base on
CONFIG0
base on
CONFIG0
base on
CONFIG0
base on
CONFIG0
base on
CONFIG0
base on
CONFIG0
(FMC_ISPSTS[20:9])
Other Peripheral
Registers
Reset Value
Reset Value
FMC Registers
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
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nRESET
0.7 VDD
0.2 VDD
32 us
32 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by
writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
Low Voltage Reset detects AVDD during system operation. When the AVDD voltage is lower than
VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR
reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state
keeps longer than De-glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous
reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform.
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AVDD
VLVR
T1
T2
( < de-glitch time) ( = de-glitch time)
Low Voltage Reset
T3
( = de-glitch time)
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Threshold
Voltage Selection BODVL[1:0] (SYS_BODCTL[2:1]), BODVL[2] (SYS_BODCTL[7]) and Brown-
Out Detector Selection Extension BODVLEXT (SYS_BODCTL[0]). Brown-Out Detector function
will detect AVDD during system operation. When the AVDD voltage is lower than VBOD and the state
keeps longer than De-glitch time (Max(20*HCLK cycles, 1*LIRC cycle)), chip will be reset if
BODRSTEN (SYS_BODCTL[3]) is enabled. The BOD reset will control the chip in reset state until
the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time. The default
value of BODVL[1:0] (SYS_BODCTL[2:1]), BODVL[2] (SYS_BODCTL[7]), BODVLEXT
(SYS_BODCTL[0]) and BODRSTEN (SYS_BODCTL[3]) is set by flash controller user
configuration register CBOVEXT (CONFIG0 [23]), CBOV[1:0] (CONFIG0 [22:21]), CBOV[2]
(CONFIG0 [19]) and CBORST(CONFIG0[20]) respectively. User can determine the initial BOD
setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< de-glitch time) (= de-glitch time)
BODOUT
T3
(= de-glitch time)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking WDTRF
(SYS_RSTSTS[2]).
6.2.2.6 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST (SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST (SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS (FMC_ISPCTL[1]) will not
be reloaded from CONFIG0 setting and keep its original software setting for booting from APROM
or LDROM. User can set the SYSRESETREQ (AIRCR[2]) to 1 to assert the MCU Reset.
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6.2.3 Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state
and all clocks stop
except LXT and LIRC.
SRAM content
retended.
Entry Condition
Chip is in normal
mode after system
reset released
CPU executes WFI
instruction.
CPU sets sleep mode
enable and power
down enable and
executes WFI
instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer,
UART, BOD and
GPIO
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal
mode
CPU back to normal
mode
Table 6.2-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP (SCS_SCR[2]) = 1
2. PDEN (CLK_PWRCTL[7]) = 1 and
PDWKIF (CLK_PWRCTL[8]) = 1
3. CPU executes WFI
Wake-up events
occur
Idle Mode
Power-down Mode
CPU Clock OFF
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
Flash Halt
Figure 6.2-6 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
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Normal Mode
ON
Idle Mode
ON
Power-down Mode
HXT (4~20 MHz XTL)
Halt
Halt
HIRC (12/16 MHz OSC)
ON
ON
LXT (32768 Hz XTL)
ON
ON
ON/OFF1
ON/OFF2
Halt
LIRC (10 kHz OSC)
PLL
ON
ON
ON
ON
LDO
ON
ON
ON
CPU
ON
Halt
ON
Halt
HCLK/PCLK
SRAM retention
FLASH
GPIO
ON
Halt
ON
ON
ON
ON
ON
Halt
ON
ON
Halt
TIMER
PWM
ON
ON
ON/OFF3
Halt
ON
ON
WDT
ON
ON
ON/OFF4
Halt
UART
ON
ON
I2C
ON
ON
Halt
SPI
ON
ON
Halt
ADC
ON
ON
Halt
ACMP
ON
ON
Halt
Table 6.2-3 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, UART, BOD and GPIO
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN (CLK_PWRCTL[7]) and execute WFI to enter
Power-down mode.
Wake-up
Wake-up condition
System can enter Power-down mode again condition*
Source
Brown-Out Detector
Interrupt
BOD
After software writes 1 to clear SYS_BODCTL[BODIF].
After software write 1 to clear the Px_INTSRC[n] bit.
GPIO
GPIO Interrupt
Timer Interrupt
WDT Interrupt
TIMER
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
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UART
I2C
nCTS wake-up
After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).
After software writes 1 to clear WKIF ( I2C_STATUS1[0]).
Falling edge in the
I2C_SDA or I2C_CLK
Table 6.2-4 Condition of Entering Power-down Mode Again
6.2.4 System Power Architecture
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation. AVDD must be equal to VDD to avoid leakage current.
Digital power from VDD and VSS supplies power to the I/O pins and internal regulator
which provides a fixed 1.8V power for digital operation.
Built-in a capacitor for internal voltage regulator
The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should
be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
as the digital power (VDD). Figure 6.2-7 shows the power distribution of the Mini55 series.
AVDD
Low
Voltage
Reset
Brown
Out
Detector
10-bit
SAR-ADC
Analog
Comparator
AVSS
48 MHz
HIRC
10 kHz
LIRC
FLASH
SRAM
Oscillator
Oscillator
1.8V
LDO_CAP
POR18
Digital Logic
4~24 MHz
or
32.768 kHz
crystal
XT_OUT
XT_IN
2.1~5.5V
to 1.8V
LDO
IO cell
GPIO Pins
oscillator
VDD VSS
Figure 6.2-7 NuMicro® Mini55 Series Power Architecture Diagram
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6.2.5 System Memory Mapping
Mini55
System Control
System Control
4 GB
0xFFFF_FFFF
0xE000_ED00
0xE000_E100
0xE000_E010
SCS_BA
SCS_BA
SCS_BA
Reserved
|
External Interrupt Control
System Timer Control
0xE000_F000
0xE000_EFFF
0xE000_E000
0xE000_E00F
|
System Control
Reserved
0x6002_0000
0x6001_FFFF
0x6000_0000
0x5FFF_FFFF
|
Reserved
Reserved
AHB peripherals
0x5020_0000
0x501F_FFFF
0x5000_0000
0x4FFF_FFFF
HDIV
0x5001_4000
0x5000_C000
0x5000_4000
FMC_BA
FMC_BA
GP_BA
FMC
AHB
GPIO Control
Interrupt Multiplexer Control 0x5000_0300
INT_BA
CLK_BA
SYS_BA
Clock Control
0x5000_0200
0x5000_0000
Reserved
|
System Global Control
0x4020_0000
0x401F_FFFF
APB
|
1 GB
0x4000_0000
0x3FFF_FFFF
APB peripherals
UART1 Control
ADC Control
0x4015_0000
0x400E_0000
0x400D_0000
0x4005_0000
0x4004_0000
0x4003_0000
0x4002_0000
0x4001_0000
0x4000_4000
UART1_BA
ADC_BA
CMP_BA
UART0_BA
PWM_BA
SPI_BA
Reserved
|
ACMP Control
UART0 Control
PWM Control
0x2000_0800
0x2000_07FF
0x2000_0000
0x1FFF_FFFF
SPI Control
2 KB SRAM
Reserved
I2C0 Control
0.5 GB
I2C0_BA
TMR_BA
WDT_BA
Timer0/Timer1 Control
WDT Control
|
0x0000_4600
0x0000_45FF
17.5 KB on-chip Flash (Mini5
|
0 GB
0x0000_0000
Table 6.2-5 Memory Mapping Table
6.2.6 Memory Organization
6.2.6.1 Overview
The NuMicro® Mini55 series provides 4G-byte addressing space. The addressing space assigned
to each on-chip controllers is shown in Table 6.2-6. The detailed register definition, addressing
space, and programming details will be described in the following sections for each on-chip
peripheral. The Mini55 series only supports little-endian data format.
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6.2.6.2 System Memory Map
The memory locations assigned to each on-chip controllers are shown in Table 6.2-6.
Addressing Space
Token
Modules
Flash and SRAM Memory Space
0x0000_0000 – 0x0000_7FFF
0x2000_0000 – 0x2000_07FF
FLASH_BA
SRAM_BA
Flash Memory Space (32 KB)
SRAM Memory Space (4 KB)
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
0x5001_4000 – 0x5001_7FFF
SYS_BA
CLK_BA
INT_BA
GP_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO (P0~P5) Control Registers
Flash Memory Control Registers
Hardware Divider Control Register
FMC_BA
HDIV_BA
APB Modules Space (0x4000_0000 – 0x401F_FFFF)
0x4000_4000 – 0x4000_00FF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
0x4015_0000 – 0x4015_3FFF
WDT_BA
TMR_BA
I2C0_BA
SPI_BA
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI with Master/slave Function Control Registers
PWM Control Registers
PWM_BA
UART0_BA
ACMP_BA
ADC_BA
UART1_BA
UART0 Control Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
UART1 Control Registers
System Control Space (0xE000_E000 – 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
Nested Vectored Interrupt Control Registers
System Control Block Registers
Table 6.2-6 Address Space Assignments for On-Chip Modules
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6.2.7 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When
the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on
reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer to count from the SYST_RVR value
rather than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.8 Nested Vectored Interrupt Controller (NVIC)
6.2.8.1 Overview
The Cortex® -M0 CPU provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor core and provides following features.
6.2.8.2 Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority change
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.8.3 Exception Model and System Interrupt Map
Table 6.2-7 lists the exception model supported by NuMicro® Mini55 series. Software can set four
levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of
all the user-configurable interrupts is 0. Note that the priority 0 is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
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Exception Name
Reset
Vector Number
Priority
-3
1
2
NMI
-2
Hard Fault
Reserved
3
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
Reserved
12 ~ 13
14
PendSV
SysTick
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 6.2-7 Exception Model
Interrupt Number
(Bit In Interrupt Interrupt Name
Registers)
Exception
Number
Source
Module
Power-down
Wake-up
Interrupt Description
1 ~ 15
16
-
-
-
System exceptions
-
0
1
2
3
BODOUT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
Yes
Yes
Yes
Yes
17
WDT
GPIO
GPIO
Watchdog Timer interrupt
18
External signal interrupt from P3.2 pin
External signal interrupt from P5.2 pin
19
EINT1
External signal interrupt from GPIO
group P0~P1
20
21
4
5
GP0/1_INT
GPIO
GPIO
Yes
Yes
External signal interrupt from GPIO
group P2~P4 except P3.2
GP2/3/4_INT
22
23
6
PWM_INT
BRAKE_INT
TMR0_INT
TMR1_INT
-
PWM
PWM
TMR0
TMR1
-
PWM interrupt
PWM Brake interrupt
Timer 0 interrupt
Timer 1 interrupt
-
No
No
7
8
24
Yes
Yes
25
9
26 ~ 27
28
10 ~ 11
12
UART0_INT
UART1_INT
SPI_INT
-
UART0
UART1
SPI
UART0 interrupt
UART1 interrupt
SPI interrupt
-
Yes
Yes
No
29
13
30
14
31
15
-
External signal interrupt from GPIO
group P5 except P5.2
32
16
GP5_INT
GPIO
Yes
HIRC_TRIM_IN
T
33
34
17
18
HIRC
I2C0
HIRC trim interrupt
I2C0 interrupt
No
I2C0_INT
Yes
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Interrupt Number
(Bit In Interrupt Interrupt Name
Registers)
Exception
Number
Source
Module
Power-down
Wake-up
Interrupt Description
35 ~ 40
41
19 ~ 24
25
-
-
-
Analog Comparator 0 or Comparator 1
interrupt
ACMP_INT
-
ACMP
-
Yes
42 ~ 43
44
26 ~ 27
28
-
Clock controller interrupt for chip wake-
up from Power-down state
PWRWU_INT
CLKC
Yes
No
45
29
ADC_INT
-
ADC
-
ADC interrupt
-
46 ~ 47
30 ~ 31
Table 6.2-8 System Interrupt Map Vector Table
6.2.8.4 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table
based address is fixed at 0x00000000. The vector table contains the initialization value for the
stack pointer on reset, and the entry point addresses for all exception handlers. The vector
number on previous page defines the order of entries in the vector table associated with the
exception handler entry as illustrated in previous section.
Vector Table Word Offset (Bytes)
0x00
Description
Initial Stack Pointer Value
Exception Number * 0x04
Exception Entry Pointer using that Exception Number
Table 6.2-9 Vector Table Format
6.2.8.5 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.2.9 System Control Registers (SCB)
The Cortex® -M0 status and operating mode control are managed System Control Registers. Including
CPUID, Cortex® -M0 interrupt priority and Cortex® -M0 power management can be controlled through
these system control registers.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference Manual”
and “ARM® v6-M Architecture Reference Manual”.
Apr 18, 2017
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the PDEN
(CLK_PWRCTL[7]) bit is set to 1. After that, chip enters Power-down mode and waits for wake-up
interrupt source triggered to exit Power-down mode. In Power-down mode, the clock controller
turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal high speed RC
oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-1 and Figure 6.3-2
show the clock generator and the overview of the clock source control.
The clock generator consists of 3 sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT) or 32.768 kHz (LXT) external
low speed crystal oscillator
48 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTLEN (CLK_PWRCTL[1:0])
4~24 MHz HXT
XT1_IN
HXT or LXT
or
32.768 kHz LXT
XT1_OUT
HIRCEN (CLK_PWRCTL[2])
HIRC
48 MHz
HIRC
LIRCEN (CLK_PWRCTL[3])
LIRC
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-1 Clock Generator Block Diagram
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HIRC
48 MHz
111
011
010
001
000
CPUCLK
HCLK
CPU
ISP
10 kHz
4~24
MHz or
32.768k
Hz
Reserved
Reserved
1/(HCLKDIV+1)
PCLK
I2C 0
4~24 MHz or
32.768kHz
10 kHz
ACMP
HIRC
External trigger
HCLK
CLKSEL0[2:0]
111
011
010
001
000
TMR 1
TMR 0
10 kHz
4~24 MHz or
32.768kHz
CLKSEL1[14:12]
HIRC
FMC
CLKSEL1[10:8]
CPUCLK
HIRC
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
HCLK
SYST_CSR[2]
4~24 MHz or
32.768kHz
Reserved
HCLK
HCLK
HCLK
PWMCH45
PWMCH23
PWMCH01
4~24 MHz or
32.768kHz
CLKSEL0[5:3]
10 kHz
11
10
00
HCLK
1/2048
WDT
4~24 MHz or
32.768kHz
CLKSEL1[1:0]
HCLK
1
HIRC
SPI
10, 11
01
4~24 MHz or
0
32.768kHz
Reserved
CLKSEL1[4]
4~24 MHz or
32.768kHz
00
1/(UART0DIV+1)
1/(UART1DIV+1)
UART 0
UART 1
CLKSEL1[27:26]
CLKSEL1[25:24]
HIRC
HCLK
11
10
01
00
1/(ADC_DIV+1)
ADC
BOD
Reserved
HIRC
HCLK
10 kHz
11
10
01
00
4~24 MHz or
32.768kHz
FREQDIV
Reserved
CLKSEL1[3:2]
4~24 MHz or
32.768kHz
Note: Before clock switching, both the pre-
selected and newly selected clock sources
must be turned on and stable.
CLKSEL2[3:2]
Figure 6.3-2 Clock Generator Global View Diagram
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6.3.2 Auto-trim
This chip supports auto-trim function: the HIRC trim (48 MHz internal RC oscillator), according to
the accurate LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output
frequency, 1 % deviation within all temperature ranges. For instance, the system needs an
accurate 48 MHz clock. In such case, if users do not want to use 48 MHz HXT as the system
clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL
(SYS_IRCTCTL[0] trim frequency selection) to “1”, and the auto-trim function will be enabled.
Interrupt status bit FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) high indicates
the HIRC output frequency is accurate within 1% deviation. To get better results, it is
recommended to set both LOOPSEL (SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT
(SYS_IRCTCTL[7:6] trim value update limitation count) to “11”.
6.3.3 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram
is shown in Figure 6.3-3.
HCLKSEL (CLK_CLKSEL0[2:0])
HIRC
111
10 kHz LIRC
011
CPUCLK
CPU
Reserved
010
HCLK
1/(HCLK_N+1)
AHB
APB
Reserved
001
000
HCLKDIV (CLK_CLKDIV[3:0])
PCLK
4~24 MHz HXT or
32.768 kHz LXT
CPU in Power Down Mode
Legend:
Note: Before clock switching, both the pre-
selected and newly selected clock sources
must be turned on and stable.
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-3 System Clock Block Diagram
The source of PCLK is equal to HCLK in system clock architecture.
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
CLKSRC(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources.
The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]).
The block diagram is shown in Figure 6.3-4.
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STCLKSEL (CLK_CLKSEL0[5:3])
HIRC
1/2
1/2
1/2
111
011
CPUCLK
HCLK
4~24 MHz HXT or
32.768 kHz LXT
1
0
STCLK
010
001
Reserved
4~24 MHz HXT or
SYST_CSR[2]
32.768 kHz LXT
000
Legend:
Note: Before clock switching, both the pre-
selected and newly selected clock sources
must be turned on and stable.
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-4 SysTick Clock Control Block Diagram
6.3.4 Peripherals Clock Source Selection
The peripheral clock has different clock source switch settings depending on different peripherals.
Please refer to the CLK_CLKSEL1 and CLK_APBCLK register description in NuMicro® Mini55
Series Technical Reference Manual section 6.3.8. Please to note that, while switching clock
source from one to another, user must wait until both clock sources are running stabled.
PCLK
Watch Dog Timer
WDTCKEN (CLK_APBCLK[0])
Timer0
TMR0CKEN (CLK_APBCLK[2])
Timer1
TMR1CKEN (CLK_APBCLK[3])
Frequency Divider
CLKOCKEN (CLK_APBCLK[6])
I2C0
I2C0CKEN (CLK_APBCLK[8])
SPI
SPIEN (CLK_APBCLK[12])
UART0
UART0CKEN (CLK_APBCLK[16])
UART1
UART1CKEN (CLK_APBCLK[17])
PWM01
PWMCH01CKEN (CLK_APBCLK[20])
PWM23
PWMCH23CKEN (CLK_APBCLK[21])
PWM45
PWMCH45CKEN (CLK_APBCLK[22])
ADC
ADCCKEN (CLK_APBCLK[28])
ACMP
ACMPCKEN (CLK_APBCLK[30])
Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK
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Peripheral Clok
Selectable
Ext. CLK (HXT Or
LXT)
HIRC
LIRC
HCLK
WDT
Timer0
Timer1
I2C0
Yes
Yes
Yes
No
Yes
Yes
Yes
-
No
Yes
Yes
-
Yes
Yes
Yes
-
Yes
Yes
Yes
-
SPI
Yes
Yes
Yes
No
Yes
Yes
Yes
-
No
Yes
Yes
-
No
No
No
-
Yes
No
No
-
UART0
UART1
PWM
ADC
Yes
No
Yes
-
Yes
-
No
-
Yes
-
ACMP
Table 6.3-1 Peripheral Clock Source Selection Table
Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to PCLK.
6.3.5 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripheral clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
10 kHz internal low speed oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock (If PDLXT = 1 and
XTLEN[1:0] = 10)
Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)
Watchdog Clock
Timer 0/1 Clock
6.3.6 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed of 16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to the CLKO pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
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When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
If DIV1EN (CLK_CLKOCTL[5]) set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FREQSEL (CLK_CLKSEL2[3:2])
CLKOCKEN (CLK_APBCLK[6])
HIRC
11
HCLK
CLKO_CLK
10
01
00
LIRC
4~24 MHz HXT or
32.768 kHz LXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 48 MHz internal high speed RC oscillator
Note: Before clock switching, both the pre-
selected and newly selected clock sources
must be turned on and stable.
Figure 6.3-6 Clock Source of Frequency Divider
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
FREQSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
CLKO_CLK
1/22
1/23
…...
1/215 1/216
DIV1EN
(CLK_CLKOCTL[5])
1/2
0000
0001
:
16 to 1
MUX
0
:
CLKO
1110
1
1111
Figure 6.3-7 Block Diagram of Frequency Divider
Apr 18, 2017
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NuMicro® Mini55 series is equipped with 17.5 Kbytes on-chip embedded flash for application
and Data Flash to store some application dependent data. A User Configuration block provides
for system initialization. A 2 Kbytes loader ROM (LDROM) is used for In-System-Programming
(ISP) function. This chip also supports In-Application-Programming (IAP) function, user switches
the code executing without the chip reset after the embedded flash updated.
6.4.2 Features
Supports 17.5 Kbytes application ROM (APROM).
Supports 2 Kbytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded flash.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
Apr 18, 2017
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The NuMicro® Mini55 series has up to 33 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 33 pins are arranged in 6 ports named
as P0, P1, P2, P3, P4 and P5. Each of the 33 pins is independent and has the corresponding
register bits to control the pin mode function and data.
The I/O type of each pin can be configured by software individually as Input, Push-pull output,
Open-drain output, or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins is
stay in input mode and each port data register Px_DOUT[n] resets to 1. For Quasi-bidirectional
mode, each I/O pin is equipped with a very weak individual pull-up resistor about 110 k ~ 300
k for VDD is from 5.0 V to 2.1 V.
6.5.2 Features
Four I/O modes:
Quasi-bidirectional mode
Push-pull output
Open-drain output
Input-only with high impendence
Quasi-bidirectional TTL/Schmitt trigger input mode selected by SYS_Px_MFP[23:16]
I/O pin configured as interrupt source with edge/level setting
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function
High driver and high sink I/O mode support
Configurable default I/O mode of all pins after reset by CIOINI (Config0[10]) setting
CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOINI = 1, all GPIO pins in Input tri-state mode after chip reset
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6.6 Timer Controller (TMR)
6.6.1 Overview
The Timer Controller includes two 32-bit timers, TMR0 and TMR1, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, event counting by external input pins, and interval
measurement by external capture pins.
6.6.2 Features
Two sets of 32-bit timer with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMRTx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Supports internal capture triggered while internal ACMP output signal transition
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6.7 Enhanced PWM Generator
6.7.1 Overview
The NuMicro® Mini55 series has built in one PWM unit (PWM0) which is specially designed for
motor driving control applications. The PWM0 supports six PWM generators which can be
configured as six independent PWM outputs, PWM0_CH0~PWM0_CH5, or as three
complementary PWM pairs, (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and
(PWM0_CH4, PWM0_CH5) with three programmable dead-time generators.
Every complementary PWM pairs share one 8-bit prescaler. There are six clock dividers providing
five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. Each PWM output has
independent 16-bit counter for PWM period control, and 16-bit comparators for PWM duty control.
The six PWM generators provide twelve independent PWM interrupt flags which are set by
hardware when the corresponding PWM period counter comparison matched period and duty.
Each PWM interrupt source with its corresponding enable bit can request PWM interrupt. The
PWM generators can be configured as One-shot mode to produce only one PWM cycle signal or
Auto-reload mode to output PWM waveform continuously.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers, the updated value will be loaded into the 16-bit down
counter/ comparator at the end of current period. The double buffering feature avoids glitch at
PWM outputs.
Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. In order to
control motor more precisely, we provide some registers that not only configure PWM but also
Timer, ADC and ACMP, by doing so, it can save more CPU time and control motor with ease
especially in BLDC.
6.7.2 Features
The PWM0 supports the following features:
Six independent 16-bit PWM duty control units with maximum six port pins:
Six independent PWM outputs – PWM0_CH0, PWM0_CH1, PWM0_CH2,
PWM0_CH3, PWM0_CH4, and PWM0_CH5
Three complementary PWM pairs, with each pin in a pair mutually complement
to each other and capable of programmable dead-time insertion – (PWM0_CH0,
PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)
Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0_CH0,
PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)
Group control bit – PWM0_CH2 and PWM0_CH4 are synchronized with PWM0_CH0,
PWM0_CH3 and PWM0_CH5 are synchronized with PWM0_CH1
One-shot (only support edge-aligned type) or Auto-reload mode PWM
Up to 16-bit resolution
Supports edge-aligned and center-aligned mode
Supports asymmetric PWM generating in center-aligned mode
Supports center loading in center-aligned mode
Programmable dead-time insertion between complementary paired PWMs
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Each pin of PWM0_CH0 to PWM0_CH5 has independent polarity setting control
Hardware fault brake protections
Supports software trigger
Two Interrupt source types:
Synchronously requested at PWM frequency when down counter
comparison matched (edge- and center-aligned type) or underflow (edge-
aligned type)
Requested when external fault brake asserted
BKP0: EINT0 or CPO1
BKP1: EINT1 or CPO0
The PWM signals before polarity control stage are defined in the view of positive logic.
The PWM ports is active high or active low are controlled by polarity control register
Supports mask aligned function
Supports independently rising CMP matching, PERIOD matching, falling CMP
matching (in Center-aligned type), period matching to trigger ADC conversion
Timer comparing matching event trigger PWM to do phase change in BLDC
application
Supports ACMP output event trigger PWM to force PWM output at most one period
low, this feature is usually for step motor control
Provides interrupt accumulation function
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Trapezoidal Commutation System Architecture
+VDC Bus
Hyper Terminal
UART Interface
DC Bus
+
BLDC
Isolation
circuit
UART
N
S
MINI58
+5V
+5V
UART
Timer
DC Bus
-
nINT0
CPO0
Push
Button
3-Phase Inverter
(IPM, MOSFET, IGBT)
CH0
CH1
CH2
CH3
CH4
CH5
PWM0
ADC
AIN[6]
AIN[0]
AIN[1]
AIN[2]
AIN[3]
AIN[7]
+VDC Bus
+5V
Option 1
Option 2
Sensorless circuit
Figure 6.7-1 Application Circuit Diagram
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6.8 Watchdog Timer (WDT)
6.8.1 Overview
The Watchdog Timer is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer
supports the function to wake-up system from Idle/Power-down mode.
6.8.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) WDT_CLK cycles and the time-out interval is 1.6 ms ~
26.214s if WDT_CLK = 10 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT
Apr 18, 2017
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Mini55
6.9 UART Controller (UART)
6.9.1 Overview
The NuMicro® Mini55 series provides two channels of Universal Asynchronous
Receiver/Transmitters (UART). The UART0 performs supports flow control function. The UART0
performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-
serial conversion on data transmitted from the CPU. The UART0 controller also supports IrDA
SIR Function, and RS-485 function mode. The UART0 channel supports six types of interrupts.
The UART1 channel supports five types of interrupts. The UART1 only performs a serial-to-
parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on
data transmitted from the CPU. The UART0 has 16 bytes Receiver/Transmitter FIFO. The UART1
has 4 bytes Receiver/Transmitter FIFO.
6.9.2 Features
Full duplex, asynchronous communications
Separates receive/transmit 16/16 bytes entry FIFO for data payloads (Only Available in
UART0)
Separates receive/transmit 4/4 byte buffer for data payloads (Only Available in UART1)
Supports hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level (Only Available in UART0)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function (Only Available in UART0)
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting UART_TOUT[15:8] register
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5, 6, 7, 8 character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode (Only Available in UART0)
Supports 3/16-bit duration for normal mode
Supports RS-485 function mode (Only Available in UART0)
Supports RS-485 9-bit mode
Supports hardware or software enable to program RTS pin to control RS-485
transmission direction directly
Apr 18, 2017
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Mini55
6.10 I2C Serial Interface Controller (I2C)
6.10.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method for data
exchange between devices. The I2C standard is a true multi-master bus including collision detection
and arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously. There are two sets of I2C controller and only I2C0 supports Power-down wake-up
function.
6.10.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus include:
Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter that requests the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address registers with mask option)
Supports Power-down wake-up function
Supports two-level buffer function
Apr 18, 2017
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Mini55
6.11 Serial Peripheral Interface (SPI)
6.11.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction
interface. The SPI controller performing a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
SPI controller can be configured as a master or a slave device.
6.11.2 Features
Supports Master or Slave mode operation
Configurable transfer bit length
Provides four 32-bit FIFO buffers
Supports MSB first or LSB first transfer
Supports byte reorder function
Supports byte or word suspend mode
Supports Slave 3-wire mode
Apr 18, 2017
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Mini55
6.12 Analog-to-Digital Converter (ADC)
6.12.1 Overview
The Mini55 series contains one 10-bit successive approximation analog-to-digital converters
(SAR A/D converter) with 12 input channels. The A/D converters can be started by software,
external pin (STADC/P3.2) or PWM trigger.
6.12.2 Features
Analog input voltage range: 0 ~ Analog Supply Voltage from AVDD
10-bit resolution and 8-bit accuracy is guaranteed
Up to 12 single-end analog input channels
Maximum ADC clock frequency is 8 MHz, and 16 ADC clocks per sample
Two operating modes
Single mode: A/D conversion is performed one time on a specified channel
PWM sequence mode: When PWM trigger, two of three ADC channels from 0 to 2
will automatically convert analog data in the sequence of channel [0,1] or
channel[1,2] or channel[0,2] defined by MODESEL (ADC_SEQCTL[3:2])
An A/D conversion can be started by:
Software write 1 to SWTRG bit
External pin STADC
PWM trigger with optional start delay period
Each Conversion result is held in data register with valid and overrun indicators
Conversion results can be compared with specified value and user can select whether
to generate an interrupt when conversion result matches the compare register setting
Channel 0 supports 2 input sources: External analog voltage and ADC input internal
fixed band-gap voltage
Channel 7 supports 2 input sources: internal fixed band-gap voltage and ADC input
Apr 18, 2017
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Mini55
6.13 Analog Comparator (ACMP)
6.13.1 Overview
The NuMicro® Mini55 series contains two comparators which can be used in a number of different
configurations. The comparator output is logic 1 when positive input is greater than negative input,
otherwise the output is 0. Each comparator can be configured to generate interrupt when the
comparator output value changes.
6.13.2 Features
Analog input voltage range: 0 ~ AVDD
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
ACMP0 supports:
Four positive sources
P1.5, P1.0, P1.2, or P1.3
Three negative sources
P1.4
Internal Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
ACMP1 supports:
Four positive sources
P3.1, P3.2, P3.4, or P3.5
Three negative sources
P3.0
Internal Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Apr 18, 2017
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Mini55
6.14 Hardware Divider (HDIV)
6.14.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider
is a signed, integer divider with both quotient and remainder outputs.
6.14.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-
bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
Apr 18, 2017
Page 57 of 74
Rev.1.00
Mini55
7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
AVDD
SPI_SS
SPI_CLK
CS
CLK
VDD
SPI Device
FB
FB
DVCC
MISO
MOSI
SPI_MISO
SPI_MOSI
VDD
VSS
Power
0.1uF
0.1uF
VSS
AVSS
VDD
DVCC
4.7K
DVCC
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
4.7K
20p
20p
[2]
CLK
DIO
XT1_IN
I2Cx_SCL
I2Cx_SDA
VDD
Mini55LDE
LQFP48
I2C Device
4~24 MHz
or
32.768 kHz
crystal
VSS
Crystal
XT1_OUT
DVCC
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
nRESET
[2]
UARTx_RXD
UARTx_TXD
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
Note 1: For the SPI device, the Mini55 chip
supply voltage must be equal to SPI device
working voltage. For example, when the SPI
LDO
Flash working voltage is 3.3 V, the Mini58 chip
supply voltage must also be 3.3V.
Note 2: x denotes 0 or 1.
Apr 18, 2017
Page 58 of 74
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Mini55
8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
Max
+7.0
VDD +0.3
24
Unit
V
DC Power Supply
-0.3
Input Voltage
VSS -0.3
V
1/tCLCL
TA
Oscillator Frequency
4
MHz
℃
Operating Temperature
-40
+105
+150
120
℃
TST
Storage Temperature
-55
IDD
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may
adversely affects the life and reliability of the device.
Apr 18, 2017
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Mini55
8.2 DC Electrical Characteristics
(VDD - VSS = 2.1 ~ 5.5 V, TA = 25C)
Symbol Parameter
Min
2.1
Typ
-
Max
5.5
Unit Test Conditions
VDD
Operation voltage
V
VDD = 2.1V ~ 5.5V up to 48 MHz
VSS / AVSS Power Ground
-0.3
-
-
V
V
VLDO
LDO Output Voltage 1.62
Allowed Voltage
1.8
1.98
VDD ≥ 2.1 V
VDD-AVDD Difference for VDD and -0.3
AVDD
0
0.3
-
V
-
All Didital
Modules
VDD
5.5V
5.5V
3.3V
3.3V
VDD
HXT HIRC PLL
IDD1
-
16.8
mA
Operating Current
Normal Run Mode
HCLK = 48 MHz
while(1){}
X
V
X
V
IDD2
IDD3
IDD4
-
-
-
11.5
16.1
11.1
-
-
-
mA
mA
mA
X
X
V
V
X
X
X
V
Executed from Flash
X
V
X
X
All Didital
Modules
HXT HIRC PLL
IDD5
-
15.7
-
mA
Operating Current
Normal Run Mode
HCLK = 44.2368 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
VDD
X
V
X
V
IDD6
IDD7
IDD8
-
-
-
10.8
15.1
10.4
-
-
-
mA
mA
mA
X
X
V
V
X
X
X
V
Executed from Flash
X
V
X
X
All Didital
Modules
HXT HIRC PLL
24
IDD9
-
8.0
-
mA
Operating Current
Normal Run Mode
HCLK = 24 MHz
while(1){}
5.5V
5.5V
X
X
X
X
X
X
V
X
V
MHz
24
MHz
IDD10
IDD11
-
-
6.5
8.0
-
-
mA
mA
24
MHz
3.3V
3.3V
Executed from Flash
24
MHz
IDD12
-
-
6.5
-
-
mA
mA
X
X
X
All Didital
Modules
VDD
5.5V
5.5V
3.3V
HXT HIRC PLL
Operating Current
Normal Run Mode
HCLK = 24 MHz
while(1){}
IDD13
10.0
X
V
X
V
IDD14
IDD15
-
-
7.1
9.7
-
-
mA
mA
X
X
V
V
X
X
X
V
Executed from Flash
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Mini55
IDD16
-
-
6.9
9.3
-
-
mA
mA
X
V
X
X
3.3V
VDD
All Digital
Modules
HXT HIRC PLL
IDD17
Operating Current
Normal Run Mode
HCLK = 22.1184 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
VDD
X
X
V
V
V
V
X
X
X
X
V
X
V
X
IDD18
IDD19
IDD20
-
-
-
6.7
9.0
6.5
-
-
-
mA
mA
mA
X
X
Executed from Flash
All Digital
Modules
HXT HIRC PLL
12
IDD21
-
4.5
-
mA
Operating Current
Normal Run Mode
HCLK = 12MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
X
X
X
X
V
X
V
X
MHz
12
MHz
IDD22
IDD23
IDD24
-
-
-
3.5
4.5
3.5
-
-
-
mA
mA
mA
12
MHz
Executed from Flash
12
MHz
All Digital
Modules
HXT HIRC PLL
4
IDD25
-
2.0
-
mA
Operating Current
Normal Run Mode
HCLK = 4 MHz
while(1){}
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
X
X
X
X
V
X
V
X
MHz
4
MHz
IDD26
IDD27
IDD28
-
-
-
1.6
2.0
1.6
-
-
-
mA
mA
mA
4
MHz
Executed from Flash
4
MHz
All Digital
Modules
HXT LIRC PLL
IDD29
-
100
-
μA
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
IDD30
IDD31
IDD32
-
-
-
100
90
-
-
-
μA
μA
μA
X
V[4]
X
Executed from Flash
90
All Digital
Modules
HXT HIRC PLL
IIDLE1
-
10.0
-
mA
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
IIDLE5
-
-
-
-
4.6
9.6
4.5
9.3
-
-
-
-
mA
mA
mA
mA
HCLK = 48 MHz
All Digital
Modules
Operating Current
HXT HIRC PLL
Apr 18, 2017
Page 61 of 74
Rev.1.00
Mini55
Idle Mode
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
HCLK = 44.2368 MHz
IIDLE6
IIDLE7
IIDLE8
-
-
-
4.3
9.0
4.2
-
-
-
mA
mA
mA
All Digital
Modules
HXT HIRC PLL
24
IIDLE9
-
4.0
-
mA
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
X
X
X
X
V
X
V
X
MHz
Operating Current
Idle Mode
24
MHz
IIDLE10
IIDLE11
IIDLE12
-
-
-
2.2
4.0
2.0
-
-
-
mA
mA
mA
HCLK = 24MHz
24
MHz
24
MHz
All Digital
Modules
HXT HIRC PLL
IIDLE13
-
6.1
-
mA
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE14
IIDLE15
IIDLE16
-
-
-
3.2
5.9
3.2
-
-
-
mA
mA
mA
HCLK = 24 MHz
All Digital
Modules
HXT HIRC PLL
IIDLE17
-
5.7
-
mA
5.5V
5.5V
3.3V
3.3V
VDD
X
X
X
X
V
V
V
V
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE18
IIDLE19
IIDLE20
-
-
-
3.0
5.6
3.0
-
-
-
mA
mA
mA
HCLK=22.1184 MHz
All Digital
Modules
HXT HIRC PLL
IIDLE9
-
2.5
-
mA
5.5V
5.5V
3.3V
3.3V
VDD
V
V
V
V
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
-
-
-
1.5
2.5
1.5
-
-
-
mA
mA
mA
HCLK =12 MHz
All Digital
Modules
HXT HIRC PLL
Operating Current
Idle Mode
IIDLE13
-
-
1.5
1.0
-
-
mA
mA
5.5V
5.5V
V
V
X
X
X
X
V
X
HCLK = 4 MHz
IIDLE14
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Rev.1.00
Mini55
IIDLE15
IIDLE16
-
-
1.5
1.0
-
-
mA
mA
3.3V
3.3V
VDD
V
V
X
X
X
X
V
X
All Digital
Modules
HXT LIRC PLL
IDD17
-
90
-
μA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
V
V
V
V
X
X
X
X
V[4]
Operating Current
Idle Mode
IDD18
IDD19
IDD20
-
-
-
90
80
80
-
-
-
μA
μA
μA
X
HCLK = 10 kHz
V[4]
X
VDD = 5.5 V, All oscillators and analog
blocks turned off.
IPWD1
1.5
1.4
-
-
A
A
-
-
Standby Current
Power-down Mode
(Deep Sleep Mode)
VDD = 3.3 V, All oscillators and analog
blocks turned off.
IPWD2
Logic 0 Input Current
P0/1/2/3/4/5 (Quasi-
bidirectional Mode)
IIL
-70
-75
VDD = 5.5 V, VIN = 0V
A
A
-
Logic 1 to 0
Transition Current
P0/1/2/3/4/5 (Quasi-
bidirectional Mode)
[*3]
ITL
-590
-
-750
+1
VDD = 5.5 V, VIN = 2.0V
-
VDD = 5.5 V, 0 < VIN< VDD
Input Leakage
Current P0/1/2/3/4
ILK
-1
A
Open-drain or input only mode
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
Input Low Voltage
P0/1/2/3/4 (TTL Input)
VIL1
V
0.6
VDD + 0.3
VDD + 0.3
0.8
Input High Voltage
P0/1/2/3/4 (TTL Input)
VIH1
VIL3
VIH3
V
V
Input Low Voltage
XTAL1[*2]
0
0.4
3.5
2.4
VDD + 0.3
VDD + 0.3
V
V
Input High Voltage
XTAL1[*2]
Negative-going
Threshold
VILS
-0.3
-
-
0.2 VDD
-
(Schmitt Input),
nRESET
Positive-going
Threshold
VIHS
0.7 VDD
17.5
VDD + 0.3
150
V
-
(Schmitt Input),
nRESET
Internal nRESETPin
Pull-up Resistor
RRST
kΩ
VDD = 2.1 V ~ 5.5V
Apr 18, 2017
Page 63 of 74
Rev.1.00
Mini55
Negative-going
Threshold
VILS
-0.3
-
-
0.3 VDD
V
V
-
-
(Schmitt input),
P0/1/2/3/4/5
Positive-going
Threshold
VIHS
0.7 VDD
-300
VDD + 0.3
(Schmitt input),
P0/1/2/3/4/5
ISR11
ISR12
ISR13
ISR21
ISR22
ISR23
ISK11
ISK12
ISK13
-400
-80
-73
-26
-5
-
-
-
-
-
-
-
-
-
VDD = 4.5 V, VSS = 2.4 V
VDD = 2.7 V, VSS = 2.2 V
VDD = 2.5 V, VSS = 2.0 V
VDD = 4.5 V, VSS = 2.4 V
VDD = 2.7 V, VSS = 2.2 V
VDD = 2.5 V, VSS = 2.0 V
VDD = 4.5 V, VSS = 0.45 V
VDD = 2.7 V, VSS = 0.45 V
VDD = 2.5 V, VSS = 0.45 V
A
Source Current
P0/1/2/3/4/5 (Quasi- -50
bidirectional Mode)
-40
A
A
-20
mA
mA
mA
mA
mA
mA
Source Current
P0/1/2/3/4/5 (Push-
pull Mode)
-3
-2.5
10
6
-5
Sink Current
15
9
P0/1/2/3/4/5 (Quasi-
bidirectional, Open-
Drain and Push-pull
Mode)
5
8
Note1: nRST pin is a Schmitt trigger input.
Note2: XT_IN is a CMOS input.
Note3: Pins of P0, P1, P2, P3, P4 and P5 can source a transition current when they are being
externally driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its
maximum value when VIN approximates to 2V.
Note4: Only enable modules which support 10 kHz LIRC clock source
Apr 18, 2017
Page 64 of 74
Rev.1.00
Mini55
8.3 AC Electrical Characteristics
8.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Min
Typ
Max
Unit
ns
Test Conditions
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
10
10
2
-
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
15
15
ns
tCHCL
2
ns
8.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Min.
2.1
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
Operation Voltage
Temperature
-
-
TA
℃
-
-
IHXT
fHXT
Operating Current
Clock Frequency
410
-
uA
12 MHz, VDD = 5.5V
-
4
24
MHz
8.3.3 Typical Crystal Application Circuits
Crystal
C1
C2
10~20 pF
4 MHz ~ 24 MHz
10~20 pF
Apr 18, 2017
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Mini55
XT_IN
XT_OUT
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 8-1 Mini55 Typical Crystal Application Circuit
8.3.4 48 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min
1.62
-
Typ
1.8
48
Max
Unit
V
Test Conditions
VHRC
Supply Voltage
Center Frequency
1.98
-
-
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40℃~105℃
-3[1]
-
-
+3[1]
-
%
VDD = 2.1 V~ 5.5 V
TA = 25 ℃, VDD = 5 V
IHRC
Operating Current
700
μA
Note: These parameters are characterized but not tested.
8.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Min
2.1
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
VLRC
Supply Voltage
Center Frequency
-
-
10
kHz
fLRC
VDD = 2.1 V ~ 5.5 V
Oscillator Frequency
-50[1]
-
+50[1]
%
TA = -40℃ ~ +105℃
Note: These parameters are characterized but not tested.
Apr 18, 2017
Page 66 of 74
Rev.1.00
Mini55
8.4 Analog Characteristics
8.4.1 10-bit SARADC
Symbol
Parameter
Min
Typ
Max
Unit
Bit
Test Condition
-
Resolution
-
-
-
-
-
-
-
10
-
DNL
INL
EO
EG
EA
-
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
-1~1.5 -1~+3
LSB
LSB
LSB
LSB
LSB
-
±1
1
±2
2
-
-
Gain Error (Transfer Gain)
Absolute Error
-1
3
-1.5
5
-
-
Monotonic
Guaranteed
-
-
-
-
-
-
-
-
-
-
8
AVDD = 4.5~5.5 V
AVDD = 2.1~5.5 V
AVDD = 4.5~5.5 V
AVDD = 2.1~5.5 V
FADC
ADC Clock Frequency
MHz
5.4
500
300
kSPS
kSPS
FS
Sample Rate (FADC/TCONV)
TACQ
TCONV
AVDD
IDDA
VIN
Acquisition Time (Sample Stage) N+1
1/FADC N is sampling counter,
N=0,1,2, 4,8, 16,32, 4,
Total Conversion Time
Supply Voltage
N+14
1/FADC
128, 256,1024
2.1
-
5.5
V
-
μA
V
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
Input Load
-
200
-
-
AVDD = 5.5 V
0
-
AVDD
-
-
-
CIN
12
7
-
-
pF
RIN
-
kΩ
Note: ADC voltage reference is same with AVDD
Apr 18, 2017
Page 67 of 74
Rev.1.00
Mini55
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
1023
1022
1021
1020
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
1023
Analog input voltage
(LSB)
Offset Error
EO
8.4.2 LDO & Power Management
Symbol
VDD
Parameter
Min
2.1
Typ
-
Max
5.5
Unit
V
Test Condition
DC Power Supply
Output Voltage
Temperature
-
-
VLDO
TA
1.62
-40
1.8
25
1.98
105
V
℃
Note: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
8.4.3 Brown-out Detector
Symbol
AVDD
TA
Parameter
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
Supply Voltage
Temperature
-
-
℃
-40
25
105
Apr 18, 2017
Page 68 of 74
Rev.1.00
Mini55
IBOD
Quiescent Current
-
100
4.3
3.7
3.0
2.7
2.4
2.2
2.0
1.7
-
μA
V
V
V
V
V
V
V
V
AVDD =5.5V
BOV_VL [2:0] = 3
BOV_VL [2:0] = 2
BOV_VL [2:0] = 7
BOV_VL [2:0] = 1
BOV_VL [2:0] = 6
BOV_VL [2:0] = 0
BOV_VL [2:0] = 5
BOV_VL [2:0] = 4
Brown-out Detector
(Falling edge)
VBOD
8.4.4 Power-on Reset
Symbol
TA
Parameter
Min
Typ
25
Max
Unit
℃
Test Condition
Temperature
Reset Voltage
-40
105
-
-
VPOR
1.25
V
8.4.5 Comparator
Symbol
VCMP
TA
Parameter
Min
2.1
-40
-
Typ
-
Max
5.5
105
80
Unit
Test Condition
Supply Voltage
Temperature
V
℃
25
40
10
-
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
μA
mV
AVDD=5V
20
-
-
-
-
0.1
AVDD – 0.1 V
AVDD – 0.1 V
Input Common Mode Range 0.1
-
DC Gain
-
-
60
-
-
dB
VCOM=1.2 V,
VDIFF=0.1 V
TPGD
Propagation Delay
200
ns
VHYS
TSTB
Hysteresis
Stable time
-
-
±30
-
-
mV
VCOM=1.2 V
1.2
μs
Apr 18, 2017
Page 69 of 74
Rev.1.00
Mini55
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Min
Typ
1.8
-
Max
Unit
V
Test Condition
[2]
VFLA
Supply Voltage
Endurance
1.62
1.98
NENDUR
TRET
20,000
-
-
-
-
-
-
-
cycles[1]
year
ms
TA =85℃
Data Retention
Sector Erase Time
Program Time
Read Current
Program Current
Erase Current
10
-
-
TERASE
TPROG
IDD1
6
7.5
4
us
-
mA
-
IDD2
3.5
2
mA
-
IDD3
mA
-
Note1: Number of program/erase cycles.
Note2: VFLA is source from chip LDO output voltage.
Note3: Guaranteed by design, not test in production.
Apr 18, 2017
Page 70 of 74
Rev.1.00
Mini55
9
PACKAGE DIMENSIONS
9.1 48-pin LQFP (7 mm x 7 mm)
Apr 18, 2017
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Rev.1.00
Mini55
9.3 33-pin QFN (4 mm x 4 mm)
Apr 18, 2017
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Rev.1.00
Mini55
10 REVISION HISTORY
Date
Revision
Description
2017.04.18
1.00
Preliminary version.
Apr 18, 2017
Page 73 of 74
Rev.1.00
Mini55
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Apr 18, 2017
Page 74 of 74
Rev.1.00
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