MS51BBAAE [NUVOTON]
8-bit Microcontroller;
| 型号： | MS51BBAAE |
| 厂家： | 
NUVOTON |
| 描述： | 8-bit Microcontroller 微控制器 |
| 文件： | 总81页 (文件大小：1748K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1T 8051
8-bit Microcontroller
NuMicro® Family
MS51 Series
MS51EB0AE
MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51TC0AE
MS51PC0AE
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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TABLE OF CONTENTS
1
2
3
GENERAL DESCRIPTION.................................................................................7
FEATURES ........................................................................................................8
PARTS INFORMATION ................................................................................... 12
3.1 MS51 Series Package Type ...................................................................................... 12
3.2 MS51 Series Selection Gude .................................................................................... 12
3.3 MS51 Series Selection Code..................................................................................... 13
PIN CONFIGURATION .................................................................................... 14
4
4.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Multi Function Pin Diagram...................................................................... 14
4.1.1 QFN 33-pin Package Pin Diagram .............................................................................14
4.1.2 LQFP 32-pin Package Pin Diagram ...........................................................................15
4.1.3 TSSOP 28-pin Package Pin Diagram ........................................................................16
4.1.4 TSSOP 20-pin Package Pin Diagram ........................................................................16
4.1.5 QFN 20-pin Package Pin Diagram .............................................................................17
4.2 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Pin Description........................................................................................... 18
5
6
BLOCK DIAGRAM........................................................................................... 22
5.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Block Diagram............................................................................................ 22
FUNCTIONAL DESCRIPTION......................................................................... 23
6.1 Memory Organization.................................................................................................. 23
6.1.1 Overview..........................................................................................................................23
6.2 Flash Memory Control ................................................................................................ 24
6.2.1 Reset................................................................................................................................24
6.3 General Purpose I/O (GPIO) ..................................................................................... 33
6.4 Timer.............................................................................................................................. 34
6.4.1 Timer/Counter 0 And 1...................................................................................................34
6.4.2 Timer2 And Input Capture .............................................................................................34
6.4.3 Timer 3.............................................................................................................................36
6.5 Pulse Width Modulated (PWM)................................................................................. 37
6.5.1 Overview..........................................................................................................................37
6.6 Watchdog Timer (WDT).............................................................................................. 39
6.6.1 Overview..........................................................................................................................39
6.7 Self Wake-Up Timer (WKT) ....................................................................................... 40
6.7.1 Overview..........................................................................................................................40
6.8 Serial Port (UART0 & UART1) .................................................................................. 41
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6.8.1 Overview..........................................................................................................................41
6.9 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4).......................................................... 42
6.9.1 Overview..........................................................................................................................42
6.10 Inter-Integrated Circuit (I2C)................................................................................. 44
6.10.1Overview..........................................................................................................................44
6.11 Serial Peripheral Interface (SPI) ......................................................................... 45
6.11.1Overview..........................................................................................................................45
6.12 12-Bit Analog-To-Digital Converter (ADC) ......................................................... 48
6.12.1Overview..........................................................................................................................48
APPLICATION CIRCUIT.................................................................................. 49
7.1 Power supply scheme................................................................................................. 49
7.2 Peripheral Application scheme.................................................................................. 50
ELECTRICAL CHARACTERISTICS................................................................ 51
8.1 General Operating Conditions................................................................................... 51
8.2 DC Electrical Characteristics..................................................................................... 52
7
8
8.2.1 Supply Current Characteristics.....................................................................................52
8.2.2 Wakeup Time from Low-Power Modes .......................................................................54
8.2.3 I/O DC Characteristics...................................................................................................55
8.3 AC Electrical Characteristics ..................................................................................... 58
8.3.1 Internal High Speed RC Oscillator (HIRC) .................................................................58
8.3.2 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
60
8.3.3 External 4~24 MHz High Speed Clock Input Signal Characteristics ......................61
8.3.4 10 kHz Internal Low Speed RC Oscillator (LIRC) .....................................................62
8.3.5 I/O AC Characteristics ...................................................................................................63
8.4 Analog Characteristics................................................................................................ 64
8.4.1 Reset and Power Control Block Characteristics........................................................64
8.4.2 12-bit SAR ADC..............................................................................................................66
8.5 Flash DC Electrical Characteristics .......................................................................... 68
8.6 Absolute Maximum Ratings....................................................................................... 69
8.6.1 Voltage Characteristics..................................................................................................69
8.6.2 Current Characteristics..................................................................................................69
8.6.3 Thermal Characteristics.................................................................................................70
8.6.4 EMC Characteristics ......................................................................................................71
8.6.5 Package Moisture Sensitivity(MSL).............................................................................72
8.6.6 Soldering Profile .............................................................................................................73
9
PACKAGE DIMENSIONS................................................................................ 74
9.1 QFN 33-pin (4.0 x 4.0 x 0.8 mm) .............................................................................. 74
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9.2 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)............................................................................. 75
9.3 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ......................................................................... 76
9.4 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ........................................................................ 77
9.5 QFN 20-pin (3.0 x 3.0 x 0.6mm) .............................................................................. 78
10 ABBREVIATIONS............................................................................................ 79
10.1 Abbreviations List .................................................................................................. 79
11 REVISION HISTORY........................................................................................ 80
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LIST OF FIGURES
Figure 4.1-1 Pin Assignment of LQFP-32 Package....................................................................... 14
Figure 4.1-2 Pin Assignment of LQFP-32 Package....................................................................... 15
Figure 4.1-3 Pin Assignment of TSSOP28 Package ..................................................................... 16
Figure 4.1-4 Pin Assignment of TSSOP20 Package ..................................................................... 16
Figure 4.1-5 Pin Assignment of QFN20 Package.......................................................................... 17
Figure 5.1-1 Functional Block Diagram.......................................................................................... 22
Figure 6.2-1 CONFIG0 Any Reset Reloading................................................................................ 29
Figure 6.2-2 CONFIG2 Power-On Reset Reloading...................................................................... 31
Figure 6.4-1 Timer 2 Block Diagram .............................................................................................. 35
Figure 6.4-2 Timer 3 Block Diagram .............................................................................................. 36
Figure 6.7-1 Self Wake-Up Timer Block Diagram.......................................................................... 40
Figure 6.9-1 SC Controller Block Diagram..................................................................................... 42
Figure 6.11-1 SPI Block Diagram................................................................................................... 45
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection ........................................................ 46
Figure 6.11-3 SPI Single-Master, Single-Slave Interconnection.................................................... 46
Figure 7.1-1 NuMicro® MS51 Power supply circuit........................................................................ 49
Figure 7.2-1 NuMicro® MS51 Peripheral interface circuit .............................................................. 50
Figure 8.6-1 Soldering profile from J-STD-020C ........................................................................... 73
Figure 9.1-1 QFN-33 Package Dimension..................................................................................... 74
Figure 9.2-1 LQFP-32 Package Dimension................................................................................... 75
Figure 9.3-1 TSSOP-28 Package Dimension ................................................................................ 76
Figure 9.4-1 TSSOP-20 Package Dimension ................................................................................ 77
Figure 9.5-1 QFN-20 Package Dimension for MS51XC0BE ......................................................... 78
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LIST OF TABLES
Table 6.5-1 PWM Pin Define And Enable Control Register........................................................... 38
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars.......................................... 39
Table 6.9-1 Smart Card or UART Pin Define And Enable Control Register.................................. 43
Table 8.1-1 General operating conditions...................................................................................... 51
Table 8.2-1 Current consumption in Normal Run mode ................................................................ 52
Table 8.2-2 Current consumption in Idle mode.............................................................................. 53
Table 8.2-3 Chip Current Consumption in Power down mode ...................................................... 53
Table 8.2-4 Low-power mode wakeup timings .............................................................................. 54
Table 8.2-5 I/O input characteristics .............................................................................................. 55
Table 8.2-6 I/O output characteristics ............................................................................................ 56
Table 8.2-7 nRESET Input Characteristics.................................................................................... 57
Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics............................ 58
Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics.............................. 59
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator .......................................... 60
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal ................................................... 61
Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ............................... 62
Table 8.3-6 I/O AC characteristics ................................................................................................. 63
Table 8.4-1 Reset and power control unit...................................................................................... 64
Table 8.4-2 Minimum Brown-out Detect Pulse Width.................................................................... 65
Table 8.4-3 ADC characteristics .................................................................................................... 66
Table 8.5-1 Flash memory characteristics..................................................................................... 68
Table 8.6-1 Voltage characteristics................................................................................................ 69
Table 8.6-2 Current characteristics................................................................................................ 69
Table 8.6-3 Thermal characteristics............................................................................................... 70
Table 8.6-4 EMC characteristics.................................................................................................... 71
Table 8.6-5 Package Moisture Sensitivity(MSL)............................................................................ 72
Table 8.6-6 Soldering Profile.......................................................................................................... 73
Table 10.1-1 List of Abbreviations.................................................................................................. 79
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1 GENERAL DESCRIPTION
The MS51 is an embedded Flash type, 8-bit high performance 1T 8051-based microcontroller. The
instruction set is fully compatible with the standard 80C51 and performance enhanced.
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE contains
a 32 Kbytes and MS51EB0AE contains a 16 Kbytes of main Flash called APROM, in which the contents
of User Code resides. The MS51 Flash supports In-Application-Programming (IAP) function, which
enables on-chip firmware updates. IAP also makes it possible to configure any block of User Code array
to be used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction.
There is an additional Flash called LDROM, in which the Boot Code normally resides for carrying out
In-System-Programming (ISP). The LDROM size is configurable with a maximum of 4 Kbytes. To
facilitate programming and verification, the Flash allows to be programmed and read electronically by
parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for
security.
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE provides
rich peripherals including 256 bytes of SRAM, 2 Kbytes of auxiliary RAM (XRAM), Up to 29 general
purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-channel input capture module,
one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-bit auto-reload Timer3 for general
purpose or baud rate generator, two UARTs with frame error detection and automatic address
recognition, three ISO 7816-3 interfaces, one SPI, one I2C, six basic PWM output channels, six
enhanced PWM output channels, eight-channel shared pin interrupt for all I/O, and one 12-bit ADC. The
peripherals are equipped with 24 sources with 4-level-priority interrupts capability.
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE series is
equipped with three clock sources and supports switching on-the-fly via software. The three clock
sources include external clock input, 10 kHz internal oscillator, and one 16 MHz internal precise
oscillator that is factory trimmed to ±1% at room temperature. The MS51 provides additional power
monitoring detection such as power-on reset and 4-level brown-out detection, which stabilizes the
power-on/off sequence for a high reliability system design.
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE
microcontroller operation consumes a very low power with two economic power modes to reduce power
consumption － Idle and Power-down mode, which are software selectable. Idle mode turns off the CPU
clock but allows continuing peripheral operation. Power-down mode stops the whole system clock for
minimum power consumption. The system clock of the MS51 can also be slowed down by software
clock divider, which allows for a flexibility between execution performance and power consumption.
With high performance CPU core and rich well-designed peripherals, the MS51EB0AE / MS51FC0AE /
MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE benefits to meet a general purpose, home
appliances, or motor control system accomplishment.
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2 FEATURES
Core and System
Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs).
8051
Power on Reset (POR)
POR with 1.15V threshold voltage level
Brown-out Detector
(BOD)
4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)
LVR with 2.0V threshold voltage level
96-bit Unique ID (UID)
Security
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM
Memories
Up to 32 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means whole
APROM can be use as Data Flash
Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG
256 Bytes on-chip RAM.
SRAM
Additional 2 KBytes on-chip auxiliary RAM (XRAM) accessed
by MOVX instruction.
Clocks
4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
External Clock Source
Default 16 MHz high-speed internal oscillator (HIRC) trimmed
to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
Internal Clock Source
Selectable 24 MHz high-speed internal oscillator (HIRC).
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10 kHz low-speed internal oscillator (LIRC) calibrating to ±1%
by software from high-speed internal oscillator
Timers
Two 16-bit Timers/Counters 0 and 1 compatible with
standard 8051.
One 16-bit Timer2 with three-channel input capture module
and 9 input pin can be selected.
16-bit Timer
One 16-bit auto-reload Timer3, which can be the baud rate
clock source of UART0 and UART1.
6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 6.40 ms ~ 1.638s since
WDT_CLK = 10 kHz (LIRC).
Watchdog
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
16-bit free running up counter for time-out interval.
Clock sources from LIRC
Wake-up Timer
Able self Wake-up wake up from Power-down or Idle mode,
and auto reload count value.
Supports Interrupt
Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports up to Three PWM modules, each module provides
6 output channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired
PWM output channels
PWM
Dead-time insertion with 8-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM
pin
Supports brake function
Supports trigger ADC on the following events
Analog Interfaces
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 8 single-end analog input channels
Analog-to-Digital
Converter (ADC)
1 internal channels, they are band-gap voltage (VBG).
Maximum ADC peripheral clock frequency is 1 MHz.
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Up to 500 KSPS sampling rate.
Software Write 1 to ADCS bit.
External pin (STADC) trigger
PWM trigger.
Support continues convert function auto store the A/D
conversion result in XRAM.
Communication Interfaces
Supports up to 2 UARTs: UART0, UART1,
Up to three sets ISO 7816-3 device configuration as UART
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9th bit.
UART
TXD and RXD pins of UART0 exchangeable via software.
1 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
7-bit addressing mode
I2C
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if
the I2C bus hangs up and timer-out counter overflows
Supports hold time programmable
1 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
slave mode up to 12 MHz
SPI
Up to three sets ISO 7816-3 device
Supports ISO 7816-3 compliant T=0, T=1
Supports full-duplex UART mode.
ISO-7816
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
GPIO
Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level
trigger setting
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̅̅̅̅̅̅̅
̅̅̅̅̅̅̅
Standard interrupt pins INT0 and INT1.
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input
mode.
Maximum I/O Speed is 24 MHz
Enabling the pin interrupt function will also enable the wake-
up function
ESD & EFT
HBM pass 8 kV
> ± 4.4 kV
ESD
EFT
150 mA pass
Latch-up
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3 PARTS INFORMATION
3.1 MS51 Series Package Type
MSOP10
TSSOP14
TSSOP20
QFN20
TSSOP28
LQFP32
QFN33
MS51BA9AE
MS51DA9AE
MS51FB9AE
MS51FC0AE
MS51XB9AE
MS51XB9BE
MS51XC0BE
MS51EC0AE
MS51EB0AE
MS51PC0AE
MS51TC0AE
Part
No.
3.2 MS51 Series Selection Gude
Connectivity
Part Number
MS51BA9AE
MS51DA9AE
MS51XB9AE
MS51XB9BE
MS51FB9AE
MS51EB0AE
MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51PC0AE
MS51TC0AE
8
1
1
1
1
1
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
8
4
4
4
4
4
4
4
4
4
4
4
5
5
-
-
2
2
2
2
2
2
2
2
2
2
2
-
1
5-ch
8-ch
MSOP10
TSSOP14
QFN20[3]
QFN20[3]
TSSOP20
TSSOP28
TSSOP20
QFN20
8
12
18
18
18
26
18
18
26
30
30
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
16
16
16
32
32
32
32
32
6
-
8-ch
6
-
8-ch
6
-
8-ch
11
11
8
3
2
2
3
3
3
15-ch
10-ch
10-ch
15-ch
15-ch
15-ch
11
12
12
TSSOP28
LQFP32
QFN33
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO 7816-3 configurable as UART function, GPIO defined as UART2 ~ UART4.
3. Detailed package information please refer to MS51FB9AE / MS51XB9AE / MS51XB9BE series document.
4. This document is only for MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE
products.
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3.3 MS51 Series Selection Code
MS
51
F
B
9
A
E
Core
Line
Package
Flash
SRAM
Reserve
Temperature
1T 8051
Industry
51: Base
B: MSOP10 (3x3 mm)
D: TSSOP14 (4.4x5.0 mm)
E: TSSOP28 (4.4x9.7 mm)
F: TSSOP20 (4.4x6.5 mm)
I: SOP8 (4x5 mm)
A: 8 KB
0: 2 KB
E:-40 ~ 105°C
B: 16 KB
C: 32 KB
1: 4 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
8: 64 KB
9: 1 KB
O: SOP20 (300 mil)
P: LQFP32 (7x7 mm)
T: QFN33 (4x4 mm)
A: 96 KB
U: SOP28 (300 mil)
X: QFN20 (3x3mm)
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4 PIN CONFIGURATION
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool -
PinConfigure contains all Nuvoton NuMicro® Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
4.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Multi Function Pin Diagram
4.1.1
QFN 33-pin Package Pin Diagram
Corresponding Part Number: MS51TC0AE
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
P2.1 / ADC_CH9 / PWM2_CH0
Top transparent view
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
P2.4 / ADC_CH12 / T0
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
QFN33
P1.3 / STADC / I2C0_SCL / ADC_CH13
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
P3.6 / UART1_RXD
UART0_RXD / ADC_CH2 / P0.7
33 VSS
UART3_RXD / PWM3_CH1 / P3.4
P3.7 / UART1_TXD
Figure 4.1-1 Pin Assignment of LQFP-32 Package
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4.1.2
LQFP 32-pin Package Pin Diagram
Corresponding Part Number: MS51PC0AE
25
16
15
14
13
12
11
10
9
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
P2.1 / ADC_CH9 / PWM2_CH0
26
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
P2.4 / ADC_CH12 / T0
27
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
28
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
LQFP32
29
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
P1.3 / STADC / I2C0_SCL / ADC_CH13
30
UART0_TXD / ADC_CH3 / P0.6
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
31
UART0_RXD / ADC_CH2 / P0.7
P3.6 / UART1_RXD
P3.7 / UART1_TXD
32
UART3_RXD / PWM3_CH1 / P3.4
Figure 4.1-2 Pin Assignment of LQFP-32 Package
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4.1.3
TSSOP 28-pin Package Pin Diagram
Corresponding Part Number: MS51EC0AE
1
2
28
27
26
25
24
VSS
P1.7 / ADC_CH0 / INT1 / UART2_RXD / SPI0_CLK
P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI
P2.0 / nRESET
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
3
4
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
PWM1_CH1 / ADC_CH14 / PWM0_BRAKE / I2C0_SDA / PWM0_CH1 / P1.4
ADC_CH13 / I2C0_SCL / STADC / P1.3
P3.4 / PWM3_CH1 / UART3_RXD
5
P0.7 / ADC_CH2 / UART0_RXD
6
23 P0.6 / ADC_CH3 / UART0_TXD
7
22 P0.5 / ADC_CH4 / IC6 / PWM0_CH2 / T0 / UART3_TXD / PWM2_CH0
T0 / ADC_CH12 / P2.4
8
21 P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
20 P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
UART4_TXD / PWM1_CH0 / ADC_CH11 / P2.3
UART4_RXD / PWM1_CH1 / ADC_CH10 / P2.2
PWM2_CH0 / ADC_CH9 / P2.1
9
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
10
11
12
13
14
19
18
17
16
15
P3.3 / PWM0_CH0 / CLKO / PWM0_BRAKE
SPI0_SS / P3.5
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
PWM1_CH0 / UART3_TXD / IC0 / PWM0_CH0 / P1.2
PWM1_CH1 / UART3_RXD / PWM0_CH1 / IC1 / CLKO / ADC_CH7 / P1.1
Figure 4.1-3 Pin Assignment of TSSOP28 Package
TSSOP 20-pin Package Pin Diagram
4.1.4
Corresponding Part Number: MS51FC0AE
1
2
20
19
18
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
3
UART0_RXD / ADC_CH2 / P0.7
nRESET / P2.0
4
17 P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
5
16 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
15 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
14 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
6
7
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P1.3 / STADC / I2C0_SCL / ADC_CH13
8
13
12
11
9
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
10
Figure 4.1-4 Pin Assignment of TSSOP20 Package
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4.1.5
QFN 20-pin Package Pin Diagram
Corresponding Part Number: MS51XC0BE
16
17
18
19
20
10
9
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P1.3 / STADC / I2C0_SCL / ADC_CH13
Top transparent view
QFN20
33 VSS
8
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
7
P1.5 / PWM0_CH5 / SPI0_SS / IC7 / UART3_TXD / PWM3_CH1
VDD
6
UART0_RXD / ADC_CH2 / P0.7
Figure 4.1-5 Pin Assignment of QFN20 Package
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4.2
MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Pin Description
Pin Number
MS51PC0AE
Symbol
Multi-Function Description[1]
MS51XC0BE MS51FC0AE
MS51EC0AE
TSSOP28
LQFP 32
MS51TC0AE
QFN 33
QFN 20
TSSOP20
6
4
9
7
3
1
6
4
VDD
Supply voltage VDD for operation.
Ground potential.
VSS
P0.0
Port 0 bit 0.
PWM0_CH3
PWM2_CH1
IC3
PWM0 output channel 3.
PWM2 output channel 1.
Input capture channel 3.
SPI master output/slave input.
UART1 receive input.
SPI0_MOSI
UART1_RXD
13
16
16
23
External 4~24 MHz (high speed) crystal input
pin.
XT1_IN
OSCIN
T1
If the EXTEN[1:0] = 10b, OSCIN is the external
clock input pin.
External count input to Timer/Counter 1 or its
toggle output.
P0.1
Port 0 bit 1.
PWM0_CH4
PWM3_CH0
IC4
PWM0 output channel 4.
PWM3 output channel 0.
Input capture channel 4.
SPI master input/slave output.
14
15
16
17
18
19
17
19
20
24
26
27
SPI0_MISO
External 4~24 MHz (high speed) crystal output
pin.
XT1_OUT
P0.2
Port 0 bit 2.
I2C clock.
I2C0_SCL
UART1_RXD
ICE_CLK
P0.3
UART1 receive input.
ICE / ICP clock input.
Port 0 bit 3.
ADC_CH6
PWM0_CH5
PWM3_CH1
IC5
ADC input channel 6.
PWM0 output channel5
PWM3 output channel1
Input capture channel 5.
UART2 transmit data output.
Smart Card 0 clock pin
Port 0 bit 4.
UART2_TXD
SC0_CLK
P0.4
ADC_CH5
PWM0_CH3
PWM2_CH1
IC3
ADC input channel 5.
PWM0 output channel 3.
PWM2 output channel 1.
Input capture channel 3.
UART2 receive input.
Smart Card 0 data pin
External start ADC trigger
Port 0 bit 5.
17
20
21
28
UART2_RXD
SC0_DAT
STADC
P0.5
ADC_CH4
PWM0_CH2
PWM2_CH0
IC6
ADC input channel 4.
PWM0 output channel 2.
PWM2 output channel 0.
Input capture channel 6.
UART3 transmit data output.
Smart card clock pin.
18
19
1
2
22
23
29
30
UART3_TXD
SC1_CLK
External count input to Timer/Counter 0 or its
toggle output.
T0
P0.6
Port 0 bit 6.
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Pin Number
MS51PC0AE
LQFP 32
MS51TC0AE
QFN 33
Symbol
Multi-Function Description[1]
MS51XC0BE MS51FC0AE
MS51EC0AE
TSSOP28
QFN 20
TSSOP20
ADC_CH3
UART0_TXD
P0.7
ADC input channel 3.
UART0 transmit data output.
Port 0 bit 7.
20
3
24
31
22
ADC_CH2
UART0_RXD
P1.0
ADC input channel 2.
UART0 transmit data output.
Port 1 bit 0.
PWM0_CH2
PWM2_CH0
IC2
PWM0 output channel 2.
PWM2 output channel 0.
Input capture channel 2.
SPI0 clock.
12
15
15
SPI0_CLK
UART1_TXD
P1.1
UART1 receive input.
Port 1 bit 1
ADC_CH7
PWM0_CH1
PWM1_CH1
IC1
ADC input channel 7.
PWM0 output channel 1.
PWM1 output channel 1.
Input capture channel 1.
UART3 receive input.
Smart Card 1 data pin.
System clock output.
Port 1 bit 2.
11
14
14
21
UART3_RXD
SC1_DAT
CLKO
P1.2
PWM0_CH0
PWM1_CH0
IC0
PWM0 output channel 0.
PWM1 output channel 0.
Input capture channel 0.
UART3 transmit data output.
Smart Card 1 clock pin.
Port 1 bit 3.
10
9
13
12
11
13
7
20
12
11
UART3_TXD
SC1_CLK
P1.3
ADC_CH13
I2C0_SCL
STADC
ADC input channel 13.
I2C0 clock.
External start ADC trigger
Port 1 bit 4.
P1.4
ADC_CH14
PWM0_CH1
PWM1_CH1
I2C0_SDA
ADC input channel 14.
PWM0 output channel 1.
PWM1 output channel 1.
I2C0 data.
8
6
PWM0_BRAKE PWM0 Fault Brake input.
P1.5
Port 1 bit 5.
PWM0_CH5
PWM3_CH1
IC7
PWM0 output channel 5.
PWM3 output channel 1.
Input capture channel 7.
SPI0 slave select input.
UART3 transmit data output.
Smart card 2 clock pin
Port 1 bit 6.
7
10
4
7
SPI0_SS
UART3_TXD
SC1_CLK
P1.6
I2C0 data.
I2C0_SDA
UART1_TXD
ICE_DAT
P1.7
5
3
8
6
2
5
3
UART1 transmit data output.
ICE data input or output.
Port 1 bit 7.
ADC_CH0
PWM3_CH0
SPI0_CLK
UART2_RXD
SC0_DAT
ADC input channel 0.
PWM3 output channel 0.
SPI0 clock.
28
UART2 receive input.
Smart Card 0 data pin
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Pin Number
MS51PC0AE
LQFP 32
Symbol
Multi-Function Description[1]
MS51XC0BE MS51FC0AE
MS51EC0AE
QFN 20
TSSOP20
TSSOP28
MS51TC0AE
QFN 33
INT1
External interrupt 1 input.
Port 2 bit 0 input pin available when RPD
(CONFIG0.2) is programmed as 0.
P2.0
It is a Schmitt trigger input pin for hardware
device reset. A low on this pin resets the
device. nRESET pin has an internal pull-up
resistor allowing power-on reset by simply
connecting an external capacitor to VSS.
1
4
26
1
nRESET
P2.1
Port 2 bit 1.
-
-
-
-
11
10
16
15
ADC_CH9
PWM2_CH0
P2.2
ADC input channel 9.
PWM2 output channel 0.
Port 2 bit 2.
ADC_CH10
PWM1_CH1
UART4_RXD
SC2_DAT6
P2.3
ADC input channel 10.
PWM1 output channel 1.
UART4 receive input.
Smart card 2 data pin
Port 2 bit 3.
ADC_CH11
PWM1_CH0
UART4_TXD
SC2_CLK6
P2.4
ADC input channel 11.
PWM1 output channel 0.
UART4 transmit data output.
Smart card 2 clock pin
Port 2 bit 4.
-
-
-
-
-
-
9
8
5
14
13
8
ADC_CH12
ADC input channel 12.
External count input to Timer/Counter 0 or its
toggle output.
T0
P2.5
Port 2 bit 5.
ADC_CH15
SPI0_MISO
UART3_RXD
SC1_DAT6
P3.0
ADC input channel 15.
SPI master input/slave output.
UART3 receive input.
Smart card 1 data pin
Port 3 bit 0.
ADC_CH1
PWM2_CH1
PI0_MOSI
UART2_TXD
SC0_CLK6
INT0
ADC input channel 1.
PWM2 output channel 1.
SPI master output/slave input.
UART2 transmit data output.
Smart card 0 clock pin
External interrupt 0 input.
2
5
27
2
If the EXTEN[1:0] = 11b, OSCIN is the external
clock input pin.
OSCIN
P3.1
Port 3 bit 1.
-
-
-
-
-
-
18
19
PWM2_CH1
P3.2
PWM2 output channel 1.
Port 3 bit 2.
PWM3_CH0
P3.3
PWM3 output channel 0.
Port 3 bit 3.
PWM0_CH0
CLK_OUT
PWM3 output channel 0.
System clock output.
-
-
18
25
PWM0_BRAKE PWM0 Fault Brake input.
P3.4
Port 3 bit 4.
PWM3_CH1
UART3_RXD
SC1_DAT
P3.5
PWM3 output channel 0.
UART3 receive input.
Smart card 0 data pin
Port 3 bit 5.
-
-
-
-
25
12
32
17
SPI0_SS
SPI0 slave select input.
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Pin Number
MS51PC0AE
LQFP 32
Symbol
Multi-Function Description[1]
MS51XC0BE MS51FC0AE
MS51EC0AE
QFN 20
TSSOP20
TSSOP28
MS51TC0AE
QFN 33
P3.6
Port 3 bit 6.
-
-
-
-
-
9
UART1_TXD
P3.7
UART1 transmit data output.
Port 3 bit 7.
-
10
UART1_RXD
UART1 receive input.
Note:
1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description.
2. UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX (AUXR1.2).
3. [I2C] alternate function remapping option. I2C pins is software switched by I2CPX (I2CON.0).
4. [STADC] alternate function remapping option. STADC pin is software switched by
STADCPX(ADCCON1.6).
5. PIOx register decides which pins are PWM or GPIO.
6. UART2_TXD and UART2_RXD pin is defined by AUXR2 register. UART3_TXD, UART3_RXD,
UART4_TXD and UART4_RXD pin defined by AUXR3 register.
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5 BLOCK DIAGRAM
5.1 MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE /
MS51PC0AE Block Diagram
Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline
of the device. User can find all the peripheral functions of the device in the diagram.
1T High
Power
VDD
POR / LVR / BOD
Performance
8051 Core
VSS
Management
T0
T1
32 KB APROM
Flash
Memory
Access
Timer 0/1
Max. 4KB
LDROM Flash
Timer 2
with
3
ICAP0~2
Input Capture
Max. Bytes
Data Flash
(page: 128B)
Timer 3
Digital
Peripheral
Self Wake-up
Timer
256 bytes
Internal RAM
Watchdog Timer
2 Kbytes XRAM
(Auxiliary RAM)
UART0/1_TX
UART0/1_RX
Serial Ports
(UART 0/1)
8
8
P0[7:0]
P0
P1
P2
P3
UART2/3/4_TX
UART2/3/4_RX
UART2/3/4
(ISO 7816-3 port)
P1[7:0]
GPIO
6
8
I2C0_SDA
I2C0_SCL
I2C0
SPI0
P2[5:0]
P3[7:0]
SPI0_MOSI
SPI0_MISO
SPI0_SS
SPI0_SCK
PWM0CH0~5
6
6
8
Any Port
GPIO Interrupt
PWM0/1/2/3
PWM1/2/3CH0~1
FB0
INT0
INT1
15
External Interrupt
AIN0~7, 9~15 Analog
12-bit ADC
STADC
Peripheral
System Clock
16/24 MHz Internal
RC Oscillator
(HIRC)
System Clock
Source
4-24 MHz
Oscillator Circuit
(HXT)
XIN
Clock Divider
10 kHz Internal RC
Oscillator
XOUT
(LIRC)
Figure 5.1-1 Functional Block Diagram
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6 FUNCTIONAL DESCRIPTION
6.1 Memory Organization
6.1.1
Overview
A standard 80C51 based microcontroller divides the memory into two different sections, Program
Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the
Data Memory is used to store data or variations during the program execution.
The Data Memory occupies a separate address space from Program Memory. In MS51, there are 256
bytes of internal scratch-pad RAM. For many applications those need more internal RAM, the MS51
provides another on-chip 2 Kbytes of RAM, which is called XRAM, accessed by MOVX instruction.
The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application
ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG
bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have
different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash
control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O
pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these
modes.
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6.2
Flash Memory Control
Reset
6.2.1
Overview
The MS51 has several options to place device in reset condition. It also offers the software flags to
indicate the source, which causes a reset. In general, most SFR go to their Reset value irrespective of
the reset condition, but there are several reset source indicating flags whose state depends on the
source of reset. User can read back these flags to determine the cause of reset using software. There
are five ways of putting the device into reset state. They are power-on reset, brown-out reset, external
reset, WDT reset, and software reset.
Power-On Reset (POR) and Low Voltage Reset (LVR)
The MS51 incorporates an internal power-on reset (POR) and a low voltage reset (LVR). During a
power-on process of rising power supply voltage VDD, the POR or LVR will hold the MCU in reset mode
when VDD is lower than the voltage reference thresholds. This design makes CPU not access program
Flash while the VDD is not adequate performing the Flash reading. If an undetermined operating code is
read from the program Flash and executed, this will put CPU and even the whole system in to an
erroneous state. After a while, VDD rises above the threshold where the system can work, the selected
oscillator will start and then program code will execute from 0000H. At the same time, a power-on flag
POF (PCON.4) will be set 1 to indicate a cold reset, a power-on process complete. Note that the contents
of internal RAM will be undetermined after a power-on. It is recommended that user gives initial values
for the RAM block.
The POF is recommended to be cleared to 0 via software to check if a cold reset or warm reset
performed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1
again. If the reset is a warm reset caused by other reset sources, POF will remain 0. User may take a
different course to check other reset flags and deal with the warm reset event. For detailed electrical
characteristics, refer to the table 35-7 and 35-8.
PCON
–
Power
Control
Register
SFR Address
Reset Value
POR: 0001_0000b
PCON
87H, All pages
Others: 000U _0000b
7
6
5
4
3
2
1
0
SMOD
R/W
SMOD0
R/W
LPR
RW
POF
R/W
GF1
R/W
GF0
R/W
PD
R/W
IDL
R/W
Bit
Name
POF
Description
4
Power-on reset flag
This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-on reset complete.
This bit remains its value after any other resets. This flag is recommended to be cleared via
software.
Brown-Out Reset
The brown-out detection circuit is used for monitoring the VDD level during execution. When VDD drops
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to the selected brown-out trigger level (VBOD), the brown-out detection logic will reset the MCU if BORST
(BODCON0.2) setting 1. After a brown-out reset, BORF (BODCON0.1) will be set as 1 via hardware.
BORF will not be altered by any reset other than a power-on reset or brown-out reset itself. This bit can
be set or cleared by software.
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BODCON0
–
Brown-out
Detection
Control
0
Register
SFR Address
Reset Value
POR,CCCC XC0X b
BOD, UUUU XU1X b
Others,UUUU XUUX b
BODCON0
A3H, Page 0, TA protected
7
6
5
4
3
2
1
0
BOS
R
BODEN
R/W
BOV[2:0]
R/W
BOF
R/W
BORST
R/W
BORF
R/W
Bit
Name
Description
1
BORF
Brown-out reset flag
When the MCU is reset by brown-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software.
External Reset and Hard Fault Reset
̅̅̅̅̅̅
The external reset pin RST is an input with a Schmitt trigger. An external reset is accomplished by
̅̅̅̅̅̅
holding the RST pin low for at least 24 system clock cycles to ensure detection of a valid hardware reset
signal. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is a
synchronous operation and requires the clock to be running to cause an external reset.
̅̅̅̅̅̅
̅̅̅̅̅̅
Once the device is in reset condition, it will remain as long as RST pin is low. After the RST high is
removed, the MCU will exit the reset state and begin code executing from address 0000H. If an external
reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is slightly different.
Since the Power-down mode stops system clock, the reset signal will asynchronously cause the system
clock resuming. After the system clock is stable, MCU will enter the reset state.
There is a RSTPINF (AUXR0.6) flag, which indicates an external reset took place. After the external
reset, this bit will be set as 1 via hardware. RSTPINF will not change after any reset other than a power-
on reset or the external reset itself. This bit can be cleared via software.
Hard Fault reset will occur if CPU fetches instruction address over Flash size, HardF (AUXR0.5) flag
will be set via hardware. HardF will not change after any reset other than a power-on reset or the external
reset itself. This bit can be cleared via software. If MCU run in OCD debug mode and OCDEN = 0, hard
fault reset will be disabled. Only HardF flag be asserted.
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AUXR1
1
–
Auxiliary
Register
Register
SFR Address
Reset Value
POR: 0000 0000b,
Software reset: 1U00 0000b,
nRESET pin: U100 0000b,
Others: UUU0 0000b
AUXR1
A2H , Page 0
7
6
5
4
3
2
1
0
0
SWRF
R/W
RSTPINF
R/W
HardF
R/W
SLOW
R/W
GF2
R/W
UART0PX
R/W
DPS
R/W
R
Bit
Name
Description
6
RSTPINF
External reset flag
When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
5
HardF
Hard Fault reset flag
Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset
and this bit will be set via hardware. It is recommended that the flag be cleared via software.
Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only
HardF flag be asserted.
Watchdog Timer Reset
The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock
source. User can clear the WDT at any time, causing it to restart the counter. When the selected time-
out occurs but no software response taking place for a while, the WDT will reset the system directly and
CPU will begin execution from 0000H.
Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps
unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via
software.
WDCON – Watchdog Timer Control
Register
SFR Address
Reset Value
POR 0000_0111 b
WDT 0000_1UUU b
Others 0000_UUUU b
WDCON
AAH, Page 0, TA protected
7
6
5
4
3
2
1
0
WDTR
R/W
WDCLR
R/W
WDTF
R/W
WIDPD
R/W
WDTRF
R/W
WDPS[2:0]
R/W
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Bit
Name
Description
3
WDTRF
WDT reset flag
When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software after reset.
Software Reset
The MS51 provides a software reset, which allows the software to reset the whole system just similar to
an external reset, initializing the MCU as it reset state. The software reset is quite useful in the end of
an ISP progress. For example, if an ISP of Boot Code updating User Code finishes, a software reset
can be asserted to re-boot CPU to execute new User Code immediately. Writing 1 to SWRST
(CHPCON.7) will trigger a software reset. Note that this bit is writing TA protection. The instruction that
sets the SWRST bit is the last instruction that will be executed before the device reset. See demo code
below.
If a software reset occurs, SWRF (AUXR0.7) will be automatically set by hardware. User can check it
as the reset source indicator. SWRF keeps unchanged after any reset other than a power-on reset or
software reset itself. SWRF can be cleared via software.
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CONFIG0
7
6
-
5
4
3
-
2
1
0
-
CBS
R/W
OCDPWM
R/W
OCDEN
R/W
RPD
R/W
LOCK
R/W
-
-
-
Factory default value: 1111 1111b
Bit
Name
Description
7
CBS
CONFIG boot select
This bit defines from which block that MCU re-boots after resets except software reset.
1 = MCU will re-boot from APROM after resets except software reset.
0 = MCU will re-boot from LDROM after resets except software reset.
5
4
OCDPWM
PWM output state under OCD halt
This bit decides the output state of PWM when OCD halts CPU.
1 = Tri-state pins those are used as PWM outputs.
0 = PWM continues.
Note that this bit is valid only when the corresponding PIO bit of PWM channel is set as 1.
OCDEN
OCD enable
1 = OCD Disabled.
0 = OCD Enabled.
Note: If MCU run in OCD debug mode and OCDEN = 0, hard fault reset will be disabled and
only Hard F flag be asserted.
2
1
RPD
Reset pin disable
1 = The reset function of P2.0/Nrst pin Enabled. P2.0/Nrst functions as the external reset pin.
0 = The reset function of P2.0/Nrst pin Disabled. P2.0/Nrst functions as an input-only pin P2.0.
LOCK
Chip lock enable
1 = Chip is unlocked. Flash Memory is not locked. Their contents can be read out through a
parallel Writer/ICP programmer.
0 = Chip is locked. Whole Flash Memory is locked. Their contents read through a parallel
Writer or ICP programmer will be all blank (FFH). Programming to Flash Memory is invalid.
Note that CONFIG bytes are always unlocked and can be read. Hence, once the chip is
locked, the CONFIG bytes cannot be erased or programmed individually. The only way to
disable chip lock is execute “whole chip erase”. However, all data within the Flash Memory
and CONFIG bits will be erased when this procedure is executed.
If the chip is locked, it does not alter the IAP function.
7
6
-
5
4
3
-
2
1
0
-
CONFIG0
CHPCON
CBS
OCDPWM
OCDEN
RPD
LOCK
Software reset does not reload
7
6
5
-
4
-
3
-
2
-
1
0
SWRST
IAPFF
BS
IAPEN
Figure 6.2-1 CONFIG0 Any Reset Reloading
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CONFIG1
7
-
6
-
5
-
4
-
3
-
2
1
0
LDSIZE[2:0]
R/W
-
-
-
-
-
Factory default value: 1111 1111b
Bit
Name
Description
2:0
LDSIZE[2:0]
LDROM size select
This field selects the size of LDROM.
111 = No LDROM. APROM is 32 Kbytes.
110 = LDROM is 1 Kbytes. APROM is 31 Kbytes.
101 = LDROM is 2 Kbytes. APROM is 30 Kbytes.
100 = LDROM is 3 Kbytes. APROM is 29 Kbytes.
0xx = LDROM is 4 Kbytes. APROM is 28 Kbytes.
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CONFIG2
7
6
5
4
3
2
1
-
0
-
CBODEN
R/W
CBOV[2:0]
R/W
BOIAP
R/W
CBORST
R/W
-
-
Factory default value: 1111 1111b
Bit Name Description
CBODEN
7
CONFIG brown-out detect enable
1 = Brown-out detection circuit on.
0 = Brown-out detection circuit off.
5:4
CBOV[1:0]
CONFIG brown-out voltage select
11 = VBOD is 2.2V.
10 = VBOD is 2.7V.
01 = VBOD is 3.7V.
00 = VBOD is 4.4V.
3
2
BOIAP
Brown-out inhibiting IAP
This bit decides whether IAP erasing or programming is inhibited by brown-out status. This bit
is valid only when brown-out detection is enabled.
1 = IAP erasing or programming is inhibited if VDD is lower than VBOD
.
0 = IAP erasing or programming is allowed under any workable VDD
.
CBORST
CONFIG brown-out reset enable
This bit decides whether a brown-out reset is caused by a power drop below VBOD
.
1 = Brown-out reset Enabled.
0 = Brown-out reset Disabled.
7
6
5
4
4
3
2
1
0
CONFIG2
CBODEN
CBOV[2:0]
BOIAP
CBORST
-
-
7
6
5
3
2
1
0
BODCON0
BODEN
BOV[2:0]
BOF
BORST
BORF
BOS
Figure 6.2-2 CONFIG2 Power-On Reset Reloading
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CONFIG4
7
6
5
4
3
-
2
-
1
-
0
-
WDTEN[3:0]
R/W
-
-
-
-
Factory default value: 1111 1111b
Bit Name
WDTEN[3:0]
Description
7:4
WDT enable
This field configures the WDT behavior after MCU execution.
1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control.
0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Power-
down mode.
Others = WDT is Enabled as a time-out reset timer and it keeps running during Idle or Power-
down mode.
3:0
-
Reserved
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6.3
General Purpose I/O (GPIO)
The MS51 has a maximum of 30 general purpose I/O pins which 29 bit-addressable general I/O pins
grouped as 4 ports, P0 to P3, and 1 input only pin as P20. Each port has its port control register (Px
register). The writing and reading of a port control register have different meanings. A write to port
control register sets the port output latch logic value, whereas a read gets the port pin logic state. These
four modes are quasi-bidirectional (standard 8051 port structure), push-pull, input-only, and open-drain
modes. Each port spends two special function registers PxM1 and PxM2 to select the I/O mode of port
Px. The list below illustrates how to select the I/O mode of Px.n. Note that the default configuration of is
input-only (high-impedance) after any reset.
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6.4
Timer
Timer/Counter 0 And 1
Overview
6.4.1
Timer/Counter 0 and 1 on MS51 are two 16-bit Timers/Counters. Each of them has two 8-bit registers
those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and
TL0, the lower 8-bit register. Similarly Timer/Counter 1 has two 8-bit registers, TH1 and TL1. TCON and
TMOD can configure modes of Timer/Counter 0 and 1.
ꢀ
The Timer or Counter function is selected by the C/T bit in TMOD. Each Timer/Counter has its own
selection bit. TMOD.2 selects the function for Timer/Counter 0 and TMOD.6 selects the function for
Timer/Counter 1
When configured as a “Timer”, the timer counts the system clock cycles. The timer clock is 1/12 of the
system clock (FSYS) for standard 8051 capability or direct the system clock for enhancement, which is
selected by T0M (CKCON.3) bit for Timer 0 and T1M (CKCON.4) bit for Timer 1. In the “Counter” mode,
the countering register increases on the falling edge of the external input pin T0. If the sampled value is
high in one clock cycle and low in the next, a valid 1-to-0 transition is recognized on T0 or T1 pin.
The Timers 0 and 1 can be configured to automatically to toggle output whenever a timer overflow
occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer
toggle outputs. This function is enabled by control bits T0OE and T1OE in the CKCON register, and
apply to Timer 0 and Timer 1 respectively. The port outputs will be logic 1 prior to the first timer overflow
ꢀ
when this mode is turned on. In order for this mode to function, the C/T bit should be cleared selecting
the system clock as the clock source for the timer.
Note that the TH0 (TH1) and TL0 (TL1) are accessed separately. It is strongly recommended that in
mode 0 or 1, user should stop Timer temporally by clearing TR0 (TR1) bit before reading from or writing
to TH0 (TH1) and TL0 (TL1). The free-running reading or writing may cause unpredictable result.
6.4.2
Timer2 And Input Capture
Overview
Timer 2 is a 16-bit up counter cascaded with TH2, the upper 8 bits register, and TL2, the lower 8 bit
register. Equipped with RCMP2H and RCMP2L, Timer 2 can operate under compare mode and auto-
̅̅̅̅̅̅
reload mode selected by CM/RL2 (T2CON.0). An 3-channel input capture module makes Timer 2 detect
and measure the width or period of input pulses. The results of 3 input captures are stores in C0H and
C0L, C1H and C1L, C2H and C2L individually. The clock source of Timer 2 is from the system clock
pre-scaled by a clock divider with 8 different scales for wide field application. The clock is enabled when
TR2 (T2CON.2) is 1, and disabled when TR2 is 0. The following registers are related to Timer 2 function.
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C0L
C0H
1000
0111
0110
0101
0100
0011
0010
0001
0000
P1.5/IC7
P0.5/IC6
P0.3/IC5
P0.1/IC4
P0.4/IC3
P0.0/IC3
P1.0/IC2
P1.1/IC1
P1.2/IC0
CAPF0
CAPF1
CAPF0
[00]
[01]
[10]
CAP0
CAP1
CAP2
Noise
Filter
Input Capture Interrupt
CAPF2
ENF0
(CAPCON2.4)
or
CAPEN0
(CAPCON0.4)
CAP0LS[1:0]
(CAPCON1[1:0])
Input Capture 0 Module
Input Capture 1 Module
Input Capture 2 Module
Input Capture Flags (CAPF[2:0])
CAPF0
CAPF1
CAPF2
CMPCR
(T2MOD.2)
Clear
Counter
Clear Timer 2
CAPCR[1]
(T2MOD.3)
Clear Timer 2
FSYS
Pre-scalar
TL2
TH2
TF2
Timer 2 Interrupt
T2DIV[2:0]
(T2MOD[6:4])
TR2
(T2CON.2)
00
01
10
11
CAPF0
CAPF1
CAPF2
=
LDEN[1]
(T2MOD.7)
LDTS[1:0]
(T2MOD[1:0])
RCMP2L
RCMP2H
Timer 2 Module
[1] Once CAPCR and LDEN are both set, an input capture event only clears TH2 and TL2 without reloading RCMP2H and RCMP2L contents.
Figure 6.4-1 Timer 2 Block Diagram
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6.4.3
Timer 3
Overview
Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the pre-
scale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine its
overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over FFFFH,
TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and RL3
registers to be reloaded into the internal 16-bit counter. If ET3 (EIE1.1) is set as 1, Timer 3 interrupt
service routine will be served. TF3 is auto-cleared by hardware after entering its interrupt service routine.
Timer 3 can also be the baud rate clock source of both UARTs..
Timer 3
Overflow
FSYS
TF3
(T3CON.4)
Pre-scalar
(1/1~1/128)
Internal 16-bit Counter
Timer 3 Interrupt
TR3
(T3CON.3)
T3PS[2:0]
(T3CON[2:0])
0
7
0
7
RL3
RH3
Figure 6.4-2 Timer 3 Block Diagram
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6.5 Pulse Width Modulated (PWM)
6.5.1 Overview
The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can
used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a
simple digital to analog converter output through a low pass filter circuit.
The MS51 PWM0 is especially designed for motor control by providing three pairs, maximum 16-bit
resolution of PWM0 output with programmable period and duty. The architecture makes user easy to
drive the one-phase or three-phase brushless DC motor (BLDC), or three-phase AC induction motor.
Each of six PWM can be configured as one of independent mode, complementary mode, or synchronous
mode. If the complementary mode is used, a programmable dead-time insertion is available to protect
MOS turn-on simultaneously. The PWM waveform can be edge-aligned or center-aligned with variable
interrupt points.
The MS51 PWM1/2/3 provide individual configurable period and duty. maximum 16-bit resolution output.
Each of two PWM1/2/3 can be configured as one of independent mode, complementary mode, or
synchronous mode.The PWM1/2/3 waveform can be edge-aligned or center-aligned with variable
interrupt points.
PWM output pin define and enable control register table.
Control register 1
Control register2
Bit name
PWM1C0P
-
Output
Pin
PWM Channel
PWM0_CH0
PWM0_CH1
SFR Byte Name Bit name
Value
SFR Byte Name
AUXR4[1:0]
-
Value
00
-
P1.2
P3.3
P1.1
P1.4
P0.5
P1.0
P0.4
P0.0
P0.1
P0.3
P1.5
P2.3
P1.2
P2.2
P1.4
P1.1
P2.1
P1.0
P0.5
P3.0
PIOCON0
PIOCON2
PIOCON0
PIOCON1
PIOCON1
PIOCON0
PIOCON1
PIOCON0
PIOCON0
PIOCON0
PIOCON1
PIOCON2
PIOCON0
PIOCON2
PIOCON1
PIOCON0
PIOCON2
PIOCON0
PIOCON1
PIOCON2
PIO12
PIO33
PIO11
PIO14
PIO05
PIO10
PIO04
PIO00
PIO01
PIO03
PIO15
PIO23
PIO12
PIO22
PIO14
PIO11
PIO21
PIO10
PIO05
PIO30
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AUXR4[3:2]
AUXR4[3:2]
AUXR4[5:4]
-
PWM1C1P
PWM1C1P
PWM2C0P
-
00
00
00
-
PWM0_CH2
PWM0_CH3
AUXR4[7:6]
AUXR4[7:6]
AUXR5[1:0]
AUXR5[3:2]
AUXR5[3:2]
PWM2C1P
PWM2C1P
PWM3C0P
PWM3C1P
PWM3C1P
00
00
00
00
00
01
10
01
10
11
00
01
10
00
PWM0_CH4
PWM0_CH5
AUXR4[1:0]
AUXR4[3:2]
PWM1C0P
PWM1C1P
PWM1_CH0
PWM1_CH1
PWM2_CH0
PWM2_CH1
AUXR4[5:4]
AUXR4[7:6]
PWM2C0P
PWM2C1P
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Control register 1
Control register2
Bit name
Output
Pin
PWM Channel
SFR Byte Name Bit name
Value
SFR Byte Name
Value
P3.1
P0.0
P0.4
P3.2
P0.1
P1.7
P3.4
P1.5
P0.3
PIOCON2
PIOCON0
PIOCON1
PIOCON2
PIOCON0
PIOCON1
PIOCON2
PIOCON1
PIOCON0
PIO31
PIO00
PIO04
PIO32
PIO01
PIO17
PIO34
PIO15
PIO03
1
1
1
1
1
1
1
1
1
01
10
11
01
10
-
PWM3_CH0
PWM3_CH1
AUXR5[1:0]
AUXR5[3:2]
PWM3C0P
PWM3C1P
01
10
11
Table 6.5-1 PWM Pin Define And Enable Control Register
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6.6 Watchdog Timer (WDT)
6.6.1 Overview
The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to reset
whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT
reset recover the system. It provides a system monitor, which improves the reliability of the system.
Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or
electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the
periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system,
which is able to operate during Idle or Power-down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the
WDT to operate as a time-out reset timer or a general purpose timer.
1
The Watchdog time-out interval is determined by the formula
× 64 , where
F
LIRC × clockdividerscalar
FLIRC is the frequency of internal 10 kHz oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
WDPS.2
WDPS.1
WDPS.0
Clock Divider Scale
WDT Time-Out Timing[1]
6.40 ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/1
1/4
25.60 ms
1/8
51.20 ms
1/16
1/32
1/64
1/128
1/256
102.40 ms
204.80 ms
409.60 ms
819.20 ms
1.638 s
Note: This is an approximate value since the deviation of LIRC.
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars
Since the limitation of the maxima vaule of WDT timer delay. To up MS51 from idle mode or power down
mode suggest use WKT function see Chapter 6.7 Self Wake-Up Timer (WKT).
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6.7 Self Wake-Up Timer (WKT)
6.7.1 Overview
The MS51 has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in
low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode.
When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power
management mode. WKT has one clock source, internal 10 kHz. Note that the system clock frequency
must be twice over WKT clock. If WKT starts counting, the selected clock source will remain active once
the device enters Idle or Power-down mode. Note that the selected clock source of WKT will not
automatically enabled along with WKT configuration. User should manually enable the selected clock
source and waiting for stability to ensure a proper operation.
The WKT is implemented simply as a 8-bit auto-reload, up-counting timer with pre-scale 1/1 to 1/2048
selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK register to determine its
overflow rate. The WKTR (WKCON.3) can be set to start counting. When the counter rolls over FFH,
WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of the RWK register
to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT interrupt service routine
will be served.
WKT
Overflow
10 kHz Internal
Oscillator
FLIRC
Pre-scalar
(1/1~1/2048)
WKTF
(WKCON.4)
Internal 16-bit Counter
WKT Interrupt
WKPS[2:0]
(WKCON[2:0])
0
15
WKTR
(WKCON.3)
RWK
Figure 6.7-1 Self Wake-Up Timer Block Diagram
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6.8 Serial Port (UART0 & UART1)
6.8.1 Overview
The MS51 includes two enhanced full duplex serial ports enhanced with automatic address recognition
and framing error detection. As control bits of these two serial ports are implemented the same.
Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to
serial port 0.
Each serial port supports one synchronous communication mode, Mode 0, and three modes of full
duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it can
transmit and receive simultaneously. The serial port is also receiving-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the register.
The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads the
transmitting register, and reading SBUF accesses a physically separate receiving register. There are
four operation modes in serial port. In all four modes, transmission initiates by any instruction that uses
SBUF as a destination register.
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6.9 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4)
6.9.1 Overview
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE provides
ISO 7816-3 Interface controller (SC controller) with asynchronous protocal based on ISO/IEC 7816-3
standard. Software controls GPIO pins as the smartcard reset function and card detection function. This
controller also provides UART emulation for high precision baud rate communication.
Internal Data Bus
Control and Status
RX_FIFO
TX_FIFO
Registers
RX_IN
TX_OUT
RX Shift
Register
TX/RX
Control Unit
TX Shift
Register
Baud Rate
Generator
ETU Clock
Generator
Figure 6.9-1 SC Controller Block Diagram
ISO-7816-3 T = 0, T = 1 compliant
Programmable transmission clock frequency
Programmable extra guard time selection
Supports auto inverse convention function
Supports UART mode
– Full duplex, asynchronous communications
– Supports programmable baud rate generator for each channel
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting SCnEGT register
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1 or 2 stop bit generation
Following is the ISO 7816-3 multi function pin define
SFR Define
URAT Pin
UART2_TXD
UART2_RXD
SC Pin
Pin Name
SFR Byte Name
SFR Bit Name
Value
01
P0.3
P3.0
P0.4
P1.7
SC0_CLK
SC0_DAT
AUXR2[7:6]
UART2TXP
UART2RXP
10
01
AUXR2[5:4]
10
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SFR Define
URAT Pin
SC Pin
Pin Name
SFR Byte Name
SFR Bit Name
Value
P1.2
P1.5
P0.5
P1.1
P2.5
P3.4
P2.3
P2.2
01
10
11
01
10
11
01
01
UART3_TXD
SC1_CLK
AUXR3[3:2]
UART3TXP
UART3RXP
UART3_RXD
SC1_DAT
AUXR3[1:0]
UART4_TXD
UART4_RXD
SC2_CLK
SC2_DAT
AUXR3[7:6]
AUXR3[5:4]
UART4TXP
UART4RXP
Table 6.9-1 Smart Card or UART Pin Define And Enable Control Register
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6.10 Inter-Integrated Circuit (I2C)
6.10.1 Overview
The MS51 provides two Inter-Integrated Circuit (I2C) bus to serves as an serial interface between the
microcontrollers and the I2C devices such as EEPROM, LCD module, temperature sensor, and so on.
The I2C bus used two wires design (a serial data line I2C0_SDA and a serial clock line I2C0_SCL) to
transfer information between devices.
The I2C bus uses bi-directional data transfer between masters and slaves. There is no central master
and the multi-master system is allowed by arbitration between simultaneously transmitting masters. The
serial clock synchronization allows devices with different bit rates to communicate via one serial bus.
The I2C bus supports four transfer modes including master transmitter, master receiver, slave receiver,
and slave transmitter. The I2C interface only supports 7-bit addressing mode. A special mode General
Call is also available. The I2C can meet both standard (up to 100kbps) and fast (up to 400k bps) speeds.
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6.11 Serial Peripheral Interface (SPI)
6.11.1 Overview
The MS51 provides two Serial Peripheral Interface (SPI) block to support high-speed serial
communication. SPI is a full-duplex, high-speed, synchronous communication bus between
microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It
provides either Master or Slave mode, high-speed rate up to FSYS/2, transfer complete and write collision
flag. For a multi-master system, SPI supports Master Mode Fault to protect a multi-master conflict.
FSYS
S
Divider
/2, /4, /8, /16
MISO
MOSI
M
MSB
LSB
Write Data Buffer
8-bit Shift Register
Read Data Buffer
M
S
Select
CLOCK
SPCLK
SS
Clock Logic
MSTR
SPIEN
SPI Status Control Logic
SPI Status Register
SPI Interrupt
SPI Control Register
Internal
Data Bus
Figure 6.11-1 SPI Block Diagram
Figure15.1 SPI Block Diagram shows SPI block diagram. It provides an overview of SPI architecture in
this device. The main blocks of SPI are the SPI control register logic, SPI status logic, clock rate control
logic, and pin control logic. For a serial data transfer or receiving, The SPI block exists a write data
buffer, a shift out register and a read data buffer. It is double buffered in the receiving and transmit
directions. Transmit data can be written to the shifter until when the previous transfer is not complete.
Receiving logic consists of parallel read data buffer so the shift register is free to accept a second data,
as the first received data will be transferred to the read data buffer.
The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
̅̅̅̅
(SPCLK), and Slave Select (SS). The MOSI pin is used to transfer a 8-bit data in series from the Master
to the Slave. Therefore, MOSI is an output pin for Master device and an input for Slave. Respectively,
the MISO is used to receive a serial data from the Slave to the Master.
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The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift clock
is used to synchronize the data movement both in and out of the devices through their MOSI and MISO
pins. The shift clock is driven by the Master mode device for eight clock cycles. Eight clocks exchange
one byte data on the serial lines. For the shift clock is always produced out of the Master device, the
system should never exist more than one device in Master mode for avoiding device conflict.
̅̅̅̅
Each Slave peripheral is selected by one Slave Select pin (SS). The signal should stay low for any Slave
̅̅̅̅
access. When SS is driven high, the Slave device will be inactivated. If the system is multi-slave, there
̅̅̅̅
should be only one Slave device selected at the same time. In the Master mode MCU, the SS pin does
̅̅̅̅
not function and it can be configured as a general purpose I/O. However, SS can be used as Master
Mode Fault detection via software setting if multi-master environment exists. The MS51 also provides
̅̅̅̅
auto-activating function to toggle SS between each byte-transfer.
Master/Slave
MCU1
Master/Slave
MCU2
MISO
MOSI
SPCLK
SS
MISO
MOSI
SPCLK
SS
0
0
I/O
PORT
1
2
3
I/O
PORT
1
2
3
Slave device 1
Slave device 2
Slave device 3
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection
Figure 6.11-2 shows a typical interconnection of SPI devices. The bus generally connects devices
together through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The Master
̅̅̅̅
devices select the individual Slave devices by using four pins of a parallel port to control the four SS
̅̅̅̅
pins. MCU1 and MCU2 play either Master or Slave mode. The SS should be configured as Master Mode
Fault detection to avoid multi-master conflict.
MOSI
MISO
MOSI
MISO
SPI shift register
SPI shift register
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SPCLK SPCLK
SPI clock
generator
SS
SS
*
Master MCU
* SS configuration follows DISMODF and SSOE bits.
Slave MCU
GND
Figure 6.11-3 SPI Single-Master, Single-Slave Interconnection
Figure 6.11-3 shows the simplest SPI system interconnection, single-master and signal-slave. During a
transfer, the Master shifts data out to the Slave via MOSI line. While simultaneously, the Master shifts
data in from the Slave via MISO line. The two shift registers in the Master MCU and the Slave MCU can
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be considered as one 16-bit circular shift register. Therefore, while a transfer data pushed from Master
into Slave, the data in Slave will also be pulled in Master device respectively. The transfer effectively
exchanges the data, which was in the SPI shift registers of the two MCUs.
By default, SPI data is transferred MSB first. If the LSBFE (SPCR.5) is set, SPI data shifts LSB first.
This bit does not affect the position of the MSB and LSB in the data register. Note that all the following
description and figures are under the condition of LSBFE logic 0. MSB is transmitted and received first.
There are three SPI registers to support its operations, including SPI control register (SPCR), SPI status
register (SPSR), and SPI data register (SPDR). These registers provide control, status, data storage
functions, and clock rate selection. The following registers relate to SPI function.
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6.12 12-Bit Analog-To-Digital Converter (ADC)
6.12.1 Overview
The MS51EB0AE / MS51FC0AE / MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE is
embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog
input signal to a 12-bit binary representation of that signal. The MS51EB0AE / MS51FC0AE /
MS51XC0BE / MS51EC0AE / MS51TC0AE / MS51PC0AE is selected as 8-channel inputs in single end
mode. The internal band-gap voltage 1.22 V also can be the internal ADC input. The analog input,
multiplexed into one sample and hold circuit, charges a sample and hold capacitor. The output of the
sample and hold capacitor is the input into the converter. The converter then generates a digital result
of this analog level via successive approximation and stores the result in the result registers. The ADC
controller also supports continuous conversion and storage result data into XRAM.
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7 APPLICATION CIRCUIT
7.1 Power supply scheme
EXT_PWR
10uF+0.1uF
MS51
Series
as close to the EXT_PWR as possible
VDD
VSS
EXT_VSS
0.1uF
as close to VDD as possible
Figure 7.1-1 NuMicro® MS51 Power supply circuit
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7.2 Peripheral Application scheme
DVCC
ICE / ICP
DVCC
Interface
CS
SPI_SS
SPI_CLK
VDD
VSS
SPI
Device
CLK
100K 100K
SPI_MISO
SPI_MOSI
MISO
MOSI
VDD
ICE_DAT
100 *
ICE_CLK
nRESET
100 *
VSS
DVCC
MS51 Series
DVCC
20pF
20pF
4.7K
4.7K
XT1_IN
I2C
Device
4~32 MHz
crystal
HXT
CLK
DIO
VDD
VSS
I2C_SCL
I2C_SDA
XT1_OUT
DVCC
10K
RS 232 Transceiver
nRESET
RIN
UART_RXD
UART_TXD
ROUT
TIN
Reset
Circuit
UART
10 uF
TOUT
PC COM Port
*ICE/ICP interface ICE_DAT/ICE_CLK pin 100ohm resister is selectable only for filter the disturb of noise on the circuit.
Note:
1. It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.
2. It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin.
3. It is optional add 100ohm resistor series between ICE_DAT/ICE_CLK pin to help filtering noise interference.
4. The HXT external capacitor value please reference Section 8.3.2.2Typical Crystal Application Circuits Capacitors Value
Figure 7.2-1 NuMicro® MS51 Peripheral interface circuit
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8 ELECTRICAL CHARACTERISTICS
Please refer to the relative Datasheet for detailed information about the MS51 electrical characteristics.
8.1 General Operating Conditions
(VDD-VSS = 2.4 ~ 5.5V, TA = 25C, Fsys = 16 MHz unless otherwise specified.)
Symbol
TA
Parameter
Temperature
Min
-40
2.4
Typ
Max
105
5.5
Unit
Test Conditions
-
℃
VDD
Operation voltage
-
[*1]
AVDD
Analog operation voltage
VDD
V
1.17
1.14
1.30
1.33
TA = 25 °C
VBG
Band-gap voltage[2]
1.22
TA = -40°C ~105 °C,
Note:
1.It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between VDD and
AVDD can be tolerated during power-on and power-off operation .
2.Based on characterization, tested in production.
Table 8.1-1 General operating conditions
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8.2 DC Electrical Characteristics
8.2.1 Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 2.4V ~ 5.5 V and maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise
specified.
VDD = AVDD
When the peripherals clock base is the system clock Fsys.
Program run “while (1);” in Flash.
Typ [6]
Max[6][7]
Symbol
Conditions
Fsys
Unit
T
= 25 °C
T
= -40 °C
T
= 25 °C
T = 105 °C
A
A
A
A
24 MHz(HIRC)[1]
@5.5V
3.6
24 MHz(HIRC)[1]
@3.3V
3.2
2.9
3.3
3.1
4.2
4.6
4.8
24 MHz(HIRC)[1]
@2.4V
Normal run mode,
IDD_RUN
executed from Flash, all
peripherals disable
16 MHz (HIRC) [1]
@5.5V
mA
16 MHz (HIRC) [1]
@3.3V
3.4
3.9
4.6
16 MHz (HIRC) [1]
@2.4V
2.8
10 kHz (LIRC)[2]
0.30
0.32
0.46
2.33
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 Current consumption in Normal Run mode
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Typ [3]
Max[3][4]
= 85 °C
Symbol
Conditions
Fsys
Unit
T
= 25 °C
2.8
T
= 25 °C
T
T = 105 °C
A
A
A
A
24 MHz(HIRC)[1]
@5.5V
24 MHz(HIRC)[1]
@3.3V
2.4
2.2
2.2
1.9
2.9
3.2
3.8
24 MHz(HIRC)[1]
@2.4V
Idle mode, executed from
Flash, all peripherals
disable
16 MHz (HIRC)[1]
@5.5V
mA
IDD_IDLE
16 MHz (HIRC)[1]
@3.3V
2.5
0.5
2.6
0.9
3.2
2.3
16 MHz (HIRC)[1]
@2.4V
1.8
0.3
10 kHz (LIRC)[2]
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-2 Current consumption in Idle mode
Typ[1]
Max[2]
= 25 °C
Symbol
Test Conditions
Unit
T
= 25 °C
T
= -40 °C
6.2
T
T = 105 °C
A
A
A
A
Power down mode, all peripherals disable@5.5V
Power down mode, all peripherals disable@3.3V
Power down mode, all peripherals disable@2.4V
6.5
6
9
55
5.8
IDD_PD
µA
Power down mode, LVR enable all other peripherals
disable
7.5
6.7
10[3]
197
57
Power down mode, LVR enable BOD enable all
other peripherals disable
180
165
292
Notes:
1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 disabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Table 8.2-3 Chip Current Consumption in Power down mode
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8.2.2
Wakeup Time from Low-Power Modes
Symbol
Parameter
Typ
Max
6
Unit
cycles
µs
[1]
tWU_IDLE
Wakeup from IDLE mode
5
-
Fsys = HIRC @16MHz
Fsys = HIRC @ 24MHz
30
30
[2][3]
tWU_NPD
Wakeup from Power down mode
µs
Notes:
1. Measured on a wakeup phase with a 16 MHz HIRC oscillator.
2. Based on test during characterization, not tested in production.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first.
Table 8.2-4 Low-power mode wakeup timings
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8.2.3
I/O DC Characteristics
8.2.3.1 PIN Input Characteristics
Symbol
Parameter
Input low voltage
Min
Typ
Max
Unit
Test Conditions
VIL
0
-
0.3*VDD
V
Input low voltage
(I/O with TTL input)
VIL1
VIH
VSS-0.3
-
-
0.2VDD-0.1
VDD+0.3
V
V
0.2VDD+0.9
Input high voltage
Input high voltage
VIH1
0.7*VDD
-
VDD
V
V
(I/O with Schmitt trigger input and Xin)
[1]
VHY
Hysteresis voltage of schmitt input
Input leakage current
-
0.2*VDD
-
VSS < VIN < VDD
,
-1
1
Open-drain or input only mode
[2]
ILK
A
VDD < VIN < 5.5 V,
Open-drain or input only mode
-1
1
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than
the maximum value, if positive current is injected on adjacent pins
Table 8.2-5 I/O input characteristics
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8.2.3.2 I/O Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD = 5.5 V
-7.4
-
-7.5
µA
VIN =(VDD-0.4) V
VDD = 3.3 V
-7.3
-7.3
-57.2
-9
-
-
-
-
-
-
-
-
-
-7.5
-7.5
-58.3
-9.6
-6.6
-4.9
-20
µA
µA
Source current for quasi-
bidirectional mode and high
level
VIN =(VDD-0.4) V
VDD = 2.4 V
VIN =(VDD-0.4) V
VDD = 5.5 V
VIN = 2.4 V
µA
[1] [2]
ISR
VDD = 5.5 V
mA
mA
mA
mA
mA
mA
VIN =(VDD-0.4) V
VDD = 3.3 V
-6
VIN =(VDD-0.4) V
Source current for push-pull
mode and high level
VDD = 2.7 V
-4.2
-18
18
VIN =(VDD-0.4) V
VDD = 5.5 V
VIN = 2.4 V
VDD = 5.5 V
VIN = 0.4 V
20
VDD = 3.3 V
VIN = 0.4 V
Sink current for push-pull
mode and low level
[1] [2]
ISK
16
18
VDD = 2.4 V
VIN = 0.4 V
9.7
-
-
11
-
mA
pF
[1]
CIO
I/O pin capacitance
5
Notes:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS
.
Table 8.2-6 I/O output characteristics
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8.2.3.3 nRESET Input Characteristics
Symbol
VILR
Parameter
Negative going threshold, nRESET
Positive going threshold, nRESET
Min
Typ
Max Unit
Test Conditions
-
0.7*VDD
45
-
0.3*VDD
V
V
VIHR
-
-
-
-
60
65
-
VDD = 5.5 V
[1]
RRST
Internal nRESET pull up resistor
nRESET input response time
KΩ
45
VDD = 2.4 V
-
1.5
-
Normal run and Idle mode
Power down mode
[1]
tFR
µs
10
25
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.2-7 nRESET Input Characteristics
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8.3 AC Electrical Characteristics
8.3.1 Internal High Speed RC Oscillator (HIRC)
8.3.1.1 16MHz RC Oscillator (HIRC)
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
2.4
-
5.5
V
TA = 25 °C,
VDD = 3.3
Oscillator frequnecy
-
16[1]
-
MHz
%
TA = 25 °C,
VDD = 3.3V
-1[3]
-2[4]
-
-
1[3]
FHRC
TA = -20 C ~ +105 °C,
Frequency drift over temperarure and
volatge
2[4]
%
VDD = 2.4 ~ 5.5V
TA = -40 C ~ -20 °C,
-4[4]
4[4]
550
5
%
µA
µs
VDD = 2.4 ~ 5.5V
[2]
IHRC
Operating current
Stable time
-
-
490
3
TA = -40C ~ +105 °C,
[3]
TS
VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics
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8.3.1.2 24MHz RC Oscillator (HIRC)
Symbol.
Parameter
Operating voltage
Min
Typ
Max
Unit
Test Conditions
VDD
2.4
-
5.5
V
TA = 25 °C,
VDD = 3.3
Oscillator frequnecy
-
24[1]
-
MHz
%
TA = 25 °C,
VDD = 3.3V
-1[3]
-2[4]
-
-
1[3]
FHRC
TA = -20C ~ +85 °C,
Frequency drift over temperarure and
volatge
2[4]
%
VDD = 2.4 ~ 5.5V
TA = -40C ~ +105 °C,
-4[4]
4[4]
550
5
%
µA
µs
VDD = 2.4 ~ 5.5V
[2]
IHRC
Operating current
Stable time
-
-
490
3
TA = -40C ~ +105 °C,
[3]
TS
VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics
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8.3.2
External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close as
possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order to
minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for
more details on the resonator characteristics (frequency, package, accuracy).
Symbol
VDD
Parameter
Operating voltage
Min[1]
Typ
-
Max[1]
5.5
Unit
V
Test Conditions[2]
1.8
Rf
Internal feedback resister
Oscillator frequency
-
4
-
500
-
-
kΩ
fHXT
24
MHz
80
180
300
500
650
975
3700
1050
850
550
570
60
4 MHz, Gain = L0
-
110
180
230
360
3500
950
700
450
400
-
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
4 MHz, Gain = L0
8 MHz, Gain = L1
12 MHz, Gain = L2
16 Mhz, Gain = L3
24 MHz, Gain = L4
IHXT
Current consumption
-
µA
-
-
-
-
TS
Stable time
Duty cycle
-
µs
%
-
-
DuHXT
40
Notes:
1. Guaranteed by characterization, not tested in production.
2. L0 ~ L4 defined by SFR XLTCON[6:4] HXSG
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator
Typical Crystal Application Circuits Capacitors Value
For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF
range, designed for high-frequency applications, and selected to match the requirements of the crystal
or resonator. The crystal manufacturer typically specifies a load capacitance which is the series
combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a
rough estimate of the combined pin and board capacitance) when sizing C1 and C2.
CRYSTAL
C1
C2
R1
4 MHz ~ 24 MHz
10 ~ 25 pF
10 ~ 25 pF
without
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8.3.3
External 4~24 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result from
tests performed using a wavefrom generator.
Symbol
Parameter
Min[*1]
Typ
Max[*1]
Unit
Test Conditions
External user clock source
frequency
fHXT_ext
4
-
24
MHz
tCHCX
tCLCX
tCLCH
Clock high time
Clock low time
8
8
-
-
-
-
ns
ns
Low (10%) to high level (90%)
rise time
Clock rise time
Clock fall time
-
-
-
-
10
10
ns
ns
High (90%) to low level (10%)
fall time
tCHCL
DuE_HXT
VIH
Duty cycle
40
0.7*VDD
VSS
-
-
-
60
VDD
%
V
Input high voltage
Input low voltage
VIL
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal
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8.3.4
10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Operating voltage
Min
2.4
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
VDD
Oscillator frequnecy
10
kHz
TA = 25 °C,
VDD = 5V
-10[1]
-35[2]
-
-
10[1]
35[2]
%
%
FLRC
Frequency drift over temperarure
and volatge
TA=-40~105°C
Without software calibration
[3]
ILRC
Operating current
Stable time
-
-
0.85
500
1
-
µA
VDD = 3.3V
TS
μs
TA=-40~105°C
Notes:
1. Guaranteed by characterization, tested in production.
2. Guaranteed by characterization, not tested in production.
3. Guaranteed by design.
Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
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8.3.5
I/O AC Characteristics
Symbol
Parameter
Typ.
4.6
2.9
6.6
4.3
8.5
8.0
4.0
2.1
4.9
3.0
9.5
5.4
5.6
3.4
8.1
5.1
15.1
9.6
4.8
2.1
6.4
3.0
12.7
5.4
Max[*1]
.
Unit
Test Conditions[*2]
5.1
3.3
8
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 2.4 V
CL = 10 pF, VDD >= 2.4 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 2.4 V
CL = 10 pF, VDD >= 2.4 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 2.4 V
CL = 10 pF, VDD >= 2.4 V
CL = 30 pF, VDD >= 5.5 V
CL = 10 pF, VDD >= 5.5 V
CL = 30 pF, VDD >= 3.3 V
CL = 10 pF, VDD >= 3.3 V
CL = 30 pF, VDD >= 2.4 V
CL = 10 pF, VDD >= 2.4 V
CL = 30 pF, VDD >= 2.4 V
CL = 10 pF, VDD >= 2.4 V
Normal mode[4] output high (90%) to low level (10%)
falling time
tf(IO)out
tf(IO)out
tr(IO)out
ns
5
12.5
10.7
4.3
2.5
5.8
3.7
13.8
7.4
6.1
3.7
9.4
5.8
20.3
12.4
5.2
2.5
7.4
3.7
16.9
7.4
High slew rate mode [5] output high (90%) to low level
(10%) falling time
ns
Normal mode[4] output low (10%) to high level (90%)
rising time
ns
High slew rate mode [5] output low (10%) to high level
(90%) rising time
tr(IO)out
ns
[*3]
fmax(IO)out
I/O maximum frequency
24
24
MHz
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
2
3. The maximum frequency is defined by 푓푚푎푥
=
.
)
푟
3 × (푡 +푡
ꢁ
4. PxSR.n bit value = 0, Normal output slew rate
5. PxSR.n bit value = 1, high speed output slew rate
Table 8.3-6 I/O AC characteristics
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8.4 Analog Characteristics
8.4.1
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
POR operating current
LVR operating current
BOD operating current
POR reset voltage
Min
10
Typ
Max
20
Unit
Test Conditions
AVDD = 5.5V
[*1]
IPOR
µA
[*1]
ILVR
0.5
-
-
0.5
1.15
2.0
4.4
3.7
2.7
2.2
-
1
AVDD = 5.5V
[*1]
IBOD
2.9
1.3
2.4
4.55
3.85
2.80
2.35
80
AVDD = 5.5V
VPOR
VLVR
VBOD
1
V
-
LVR reset voltage
1.7
4.25
3.55
2.60
2.10
60
-
BOD brown-out detect voltage
BOV[1:0] = [0,0]
BOV[1:0] = [0,1]
BOV[1:0] = [1,0]
BOV[1:0] = [1,1]
-
[*1]
TLVR_SU
LVR startup time
LVR respond time
µs
[1]
TLVR_RE
0.4
180
180
2.5
-
4
Fsys = HIRC@16MHz
Fsys = LIRC
-
350
320
5
[1]
TBOD_SU
BOD startup time
BOD respond time
-
Fsys = HIRC@16MHz
Fsys = HIRC@16MHz
[1]
TBOD_RE
-
Notes:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
Table 8.4-1 Reset and power control unit
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
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Rev 1.02
BODFLT
(BODCON1.1)
System Clock
Source
BOD Operation Mode
Minimum Brown-out Detect Pulse Width
0
Normal mode
(LPBOD[1:0] = [0,0])
Any clock source
Any clock source
Any clock source
Any clock source
Typ. 1μs
Low power mode 1
(LPBOD[1:0] = [0,1])
16 (1/FLIRC
)
)
Low power mode 2
(LPBOD[1:0] = [1,0])
64 (1/FLIRC
Low power mode 3
(LPBOD[1:0] = [1,1])
256 (1/ FLIRC
)
1
Normal operation: 32 (1/FSYS
Idle mode: 32 (1/FSYS
Power-down mode: 2 (1/FLIRC
)
HIRC/ECLK
)
Normal mode
(LPBOD[1:0] = [0,0])
)
LIRC
2 (1/FLIRC)
Low power mode 1
(LPBOD[1:0] = [0,1])
Any clock source
18 (1/FLIRC
)
)
Low power mode 2
(LPBOD[1:0] = [1,0])
Any clock source
Any clock source
66 (1/FLIRC
Low power mode 3
(LPBOD[1:0] = [1,1])
258 (1/ FLIRC
)
Table 8.4-2 Minimum Brown-out Detect Pulse Width
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Rev 1.02
8.4.2
12-bit SAR ADC
Symbol
TA
Parameter
Min
Typ
Max
Unit
Test Conditions
Temperature
-40
-
105
℃
AVDD
VREF
VIN
Analog operating voltage
Reference voltage
2.7
2.7
0
-
-
-
5.5
V
V
V
AVDD = VDD
VREF = AVDD
AVDD
VREF
ADC channel input voltage
AVDD = VDD =VREF = 5.5 V
FADC = 500 kHz
[1]
IADC
Operating current (AVDD + VREF current)
Resolution
-
-
418
µA
TCONV = 17 * TADC
NR
12
Bit
μs
μs
2.375
2.417
52.6
19
13.3
421
413
17
FSYS = 16MHz;
FSYS = 24MHz;
Conversion Time
[2]
TADC
TADC = TSMP +TADCEC
kHz FSYS = 16MHz;
kHz FSYS = 24MHz;
Conversion Rate
FADC = 1/TADC
FADC
75.2
0.375
-
-
μs
μs
μs
FSYS = 16MHz;
TSMP
Sampling Time [2]z
Fsys = 24MHz;
ADCAQT = 1 by software[3]
0.417
11.3
TADCEC
Encoding Time
2
-
-
-
-
-
-
-
-
-
This value is fixed by ADC module
[1]
FADCEC
Encoding Rate
500
-
kHz This value is fixed by ADC module
μs
TEN
Enable to ready time
Integral Non-Linearity Error
Differential Non-Linearity Error
Gain error
20
-3
INL[*1]
DNL[*1]
+3
LSB VREF = AVDD =VDD
LSB VREF = AVDD=VDD
LSB VREF = AVDD=VDD
LSB VREF = AVDD=VDD
LSB VREF = AVDD=VDD
-2
+4
[*1]
EG
-3.5
-2
+0.4
+2.8
+7
[*1]
EO
Offset error
T
[*1]
EA
Absolute Error
-7
Notes:
1. Guaranteed by characterization result, not tested in production.
2. ADC Convertion time = ADC Sampling Time (TSMP) + ADC Encoding Time (TADCEC).
4* ADCAQT 6
3. ADC Sampling Time =.
（FADC base on ADCDIV (ADCCON1[5:4])
F
ADC
6
If HIRC = 16MHz, ADC Sampling Time Minimum condition
(ADCAQT = 0, ADCDIV = 0), ADC Sampling Time
16MHz
4*7 6
16MHz / 8
Maximum condition
(ADCAQT = 7, ADCDIV = 7)
4*1 6
24MHz
If HIRC = 24MHz, ADC Sampling Time Minimum condition
(ADCAQT = 1, ADCDIV = 0), Since the minimum
sampling time must over 370ns that means when FADCAQT = 24MHz, ADCAQT must be set as 1 by software at least.
4*7 6
24MHz / 8
ADC Sampling Time Maximum condition
(ADCAQT = 7, ADCDIV = 7)
Table 8.4-3 ADC characteristics
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Rev 1.02
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
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Rev 1.02
8.5 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Supply voltage
Min
Typ
1.8
5
Max
Unit
V
Test Condition
[1]
VFLA
1.62
1.98
TERASE
TPROG
IDD1
Page erase time
Program time
Read current
-
-
-
-
-
-
-
-
-
-
ms
µs
10
4
TA = 25℃
mA
mA
mA
IDD2
Program current
Erase current
4
IDD3
12
NENDUR
Endurance
100,000
50
-
-
-
-
cycles[2]
year
TJ = -40℃~125℃
100 kcycle[3] TA = 55℃
100 kcycle[3] TA = 85℃
100 kcycle[3] TA = 105℃
-
-
-
TRET
Data retention
25
year
10
year
Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Table 8.5-1 Flash memory characteristics
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Rev 1.02
8.6 Absolute Maximum Ratings
Volrage Stesses above the absolute maximum ratings may cause permanent damage to the device.
The limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.6.1
Voltage Characteristics
Symbol
Description
Min
Max
6.5
50
Unit
V
[*1]
VDD-VSS
DC power supply
-0.3
ΔVDD
|VDD –AVDD
ΔVSS
Variations between different power pins
Allowed voltage difference for VDD and AVDD
Variations between different ground pins
Allowed voltage difference for VSS and AVSS
Input voltage on I/O
-
mV
mV
mV
mV
V
|
-
50
-
50
|VSS - AVSS
|
-
50
VIN
VSS-0.3
5.5
Notes:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
Table 8.6-1 Voltage characteristics
8.6.2
Current Characteristics
Symbol
Description
Min
Max
200
200
22
Unit
[*1]
ΣIDD
Maximum current into VDD
Maximum current out of VSS
-
-
-
-
-
-
ΣISS
Maximum current sunk by a I/O Pin
mA
Maximum current sourced by a I/O Pin
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins[*2]
10
IIO
100
100
Note:
1.
Maximum allowable current is a function of device maximum power dissipation.
2.
This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3.
A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN<VSS. IINJ(PIN) must never be
exceeded. It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage
supply pin.
Table 8.6-2 Current characteristics
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Rev 1.02
8.6.3
Thermal Characteristics
The average junction temperature can be calculated by using the following equation:
T
T
+ (P
x
)
J
=
A
D
θJA
TA = ambient temperature (°C)
θJA = thermal resistance junction-ambient (°C/Watt)
P
D
= sum of internal and I/O power dissipation
Symbol
Description
Min
Typ
Max
105
125
150
Unit
T
A
-40
Operating ambient temperature
Operating junction temperature
Storage temperature
-
-
-
T
J
-40
-65
-
°C
T
ST
Thermal resistance junction-ambient
20-pin QFN(3x3 mm)
°C/Watt
°C/Watt
℃/Watt
℃/Watt
℃/Watt
68
38
30
62
28
-
-
-
-
-
Thermal resistance junction-ambient
20-pin TSSOP(4.4x6.5 mm)
-
Thermal resistance junction-ambient
28-pin TSSOP(4.4x9.7 mm)
[*1]
θJA
Thermal resistance junction-ambient
32-pin LQFP(7x7 mm)
Thermal resistance junction-ambient
33-pin QFN(4x4 mm)
Note:
1.
Determined according to JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions
Table 8.6-3 Thermal characteristics
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Rev 1.02
8.6.4
EMC Characteristics
8.6.4.1 Electrostatic discharge (ESD)
For the Nuvoton MCU products, there are ESD protection circuits which built into chips to avoid any
damage that can be caused by typical levels of ESD.
8.6.4.2 Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
8.6.4.3 Electrical fast transients (EFT)
In some application circuit compoment will produce fast and narrow high-frequency trasnients bursts of
narrow high-frequency transients on the power distribution system..
Inductive loads:
– Relays, switch contactors
– Heavy-duty motors when de-energized etc.
The fast transient immunity requirements for electronic products are defined in IEC 61000-4-4 by
International ElectrotechnicalCommission (IEC).
Symbol
Description
Electrostatic discharge,human body mode
Electrostatic discharge,charge device model
Pin current for latch-up[*3]
Min
-8000
-1000
-400
Typ
Max
+8000
+1000
+400
Unit
[*1]
VHBM
-
-
-
-
V
[*2]
VCDM
LU[*3]
mA
kV
[*4] [*5]
VEFT
-4.4
Fast transient voltage burst
+4.4
Notes:
1. Determined according to ANSI/ESDA/JEDEC JS-001 Standard, Electrostatic Discharge Sensitivity Testing – Human
Body Model (HBM) – Component Level
2. Determined according to ANSI/ESDA/JEDEC JS-002 standard for Electrostatic Discharge Sensitivity (ESD) Testing –
Charged Device Model (CDM) – Component Level.
3. Determined according to JEDEC EIA/JESD78 standard.
4. Determinded according to IEC 61000-4-4 Electrical fast transient/burst immunity test.
5. The performace cretia class is 4A.
Table 8.6-4 EMC characteristics
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Rev 1.02
8.6.5
Package Moisture Sensitivity(MSL)
The MSL rating of an IC determines its floor life before the board mounting once its dry bag has been
opened. All Nuvoton surface mount chips have a moisture level classification. The information is also
displayed on the bag packing.
Pacakge[1]
MSL
20-pin QFN(3x3 mm)
MSL 3
MSL 3
MSL 3
MSL 3
MSL 3
20-pin TSSOP(4.4x6.5 mm)
28-pin TSSOP (4.4 x 9.7 x 1.0 mm)
32-pin LQFP (7.0 x 7.0 x 1.4 mm)
33-pin QFN ( 4.0 x 4.0 x0.8 mm)
Note:
1. Determined according to IPC/JEDEC J-STD-020
Table 8.6-5 Package Moisture Sensitivity(MSL)
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Rev 1.02
8.6.6
Soldering Profile
Figure 8.6-1 Soldering profile from J-STD-020C
Porfile Feature
Pb Free Package
3°C/sec. max
Average ramp-up rate (217°C to peak)
Preheat temperature 150°C ~200°C
Temperature maintained above 217°C
Time with 5°C of actual peak temperature
Peak temperature range
60 sec. to 120 sec.
60 sec. to 150 sec.
> 30 sec.
260°C
Ramp-down rate
6°C/sec ax.
8 min. max
Time 25°C to peak temperature
Note:
1. Determined according to J-STD-020C
Table 8.6-6 Soldering Profile
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Rev 1.02
9 PACKAGE DIMENSIONS
9.1 QFN 33-pin (4.0 x 4.0 x 0.8 mm)
Figure 9.1-1 QFN-33 Package Dimension
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Rev 1.02
9.2
LQFP 32-pin (7.0 x 7.0 x 1.4 mm)
Figure 9.2-1 LQFP-32 Package Dimension
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Rev 1.02
9.3
TSSOP 28-pin (4.4 x 9.7 x 1.0 mm)
Figure 9.3-1 TSSOP-28 Package Dimension
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Rev 1.02
9.4
TSSOP 20-pin (4.4 x 6.5 x 0.9 mm)
Figure 9.4-1 TSSOP-20 Package Dimension
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Rev 1.02
9.5
QFN 20-pin (3.0 x 3.0 x 0.6mm)
Figure 9.5-1 QFN-20 Package Dimension for MS51XC0BE
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Rev 1.02
10 ABBREVIATIONS
10.1 Abbreviations List
Acronym
ADC
BOD
GPIO
Fsys
HIRC
IAP
Description
Analog-to-Digital Converter
Brown-out Detection
General-Purpose Input/Output
Frequency of system clock
12 MHz Internal High Speed RC Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIRC
LVR
10 kHz internal low speed RC oscillator (LIRC)
Low Voltage $eset
PDMA
POR
PWM
SPI
Peripheral Direct Memory Access
Power On Reset
Pulse Width Modulation
Serial Peripheral Interface
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
UART
UCID
WKT
WDT
Wakeup Timer
Watchdog Timer
Table 10.1-1 List of Abbreviations
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Rev 1.02
11 REVISION HISTORY
Date
Revision
Chapter
Description
2019.11.28
1.00
Initial release
Section 3.2
Modified selection guide table MS51FC0AE/MS51XC0BE ISO
7816-3 number to 2. Added description for MS51FC0AE.
Added P3.0 PWM2_CH1 pin define in Pin Description table.
Modified EFT level to 4.4kV
2019.12.25
2021.02.25
1.01
1.02
Section 4.2
Section 8.6.4
Section 3.2
Section 8.4.2
Section 9.1
Added description for MS51EB0AE.
Added ADC sampling timing data of FSYS = 24MHz.
Modified QFN33 package dimension to add lead length L1
condition.
Section 9.5
Modified QFN20 package dimension to add lead length L1
condition.
Feb. 25, 2021
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Rev 1.02
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages
and liabilities thus incurred by Nuvoton.
Feb. 25, 2021
81 of 81
Rev 1.02
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