N32901UDN [NUVOTON]
Display Control Application Processor;
| 型号： | N32901UDN |
| 厂家： | 
NUVOTON |
| 描述： | Display Control Application Processor |
| 文件： | 总70页 (文件大小：2028K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N3290X DATASHEET
N3290x
Datasheet
Display Control Application
Processor
Nuvoton Technology Corp.
http://www.nuvoton.com/
1
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
The information in this document is subject to change without notice.
The Nuvoton Technology Corp. shall not be liable for technical or editorial errors or
omissions contained herein; nor for incidental or consequential damages resulting from
the furnishing, performance, or use of this material.
This documentation may not, in whole or in part, be copied, photocopied, reproduced,
translated, or reduced to any electronic medium or machine readable form without prior
consent, in writing, from the Nuvoton Technology Corp.
Nuvoton Technology Corp. All rights reserved.
Nuvoton Technology Corp.
http://www.nuvoton.com/
2
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
N3290x
Display Control Application Processor
Table of Contents
1.
GENERAL DESCRIPTION......................................................................................................................................5
1.1 Applications..............................................................................................................................................5
2.
3.
FEATURES ..........................................................................................................................................................6
PIN DIAGRAM....................................................................................................................................................12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
N32901U1DN (LQFP-128).....................................................................................................................12
N32903U5DN (LQFP-128).....................................................................................................................13
N32905U3DN (LQFP-128).....................................................................................................................14
N32901R1DN (LQFP-64).......................................................................................................................15
N32903R5DN (TQFP-64 EPAD)............................................................................................................16
N32905R3DN (TQFP-64 EPAD)............................................................................................................17
N3290xKxDN (LQFP128) ......................................................................................................................18
N32901R7DN (TQFP-64 EPAD)............................................................................................................19
4.
5.
PIN DESCRIPTION............................................................................................................................................20
4.1
4.2
4.3
4.4
4.5
N3290xUxDN Pin Description................................................................................................................20
N32901R1DN, N32903R5DN and N32905R3DN Pin Description.........................................................28
N3290xKxDN series Pin Description .....................................................................................................33
N32901R7DN TQFP64 pin list...............................................................................................................44
Pin Type Description..............................................................................................................................48
ELECTRICAL SPECIFICATION.........................................................................................................................49
5.1
5.2
5.3
5.4
5.5
Absolute Maximum Rating.....................................................................................................................49
DC Characteristics (Normal I/O)............................................................................................................49
Audio DAC Characteristics ....................................................................................................................50
ADC Characteristics .................................................................................................................................51
AC Characteristics (Digital Interface).........................................................................................................52
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
Clock Input Characteristics................................................................................................................52
SDRAM Interface...............................................................................................................................53
Sensor/Video-In Interface..................................................................................................................54
I2S Interface......................................................................................................................................55
LCD/Display Interface........................................................................................................................56
SPI Interface......................................................................................................................................58
NAND Interface .................................................................................................................................59
SD Card Interface..............................................................................................................................60
Nuvoton Technology Corp.
http://www.nuvoton.com/
3
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.6
5.7
Power-on Sequence...............................................................................................................................61
Thermal characteristics of LQFP-128 Package.....................................................................................61
6.
7.
N3290X SERIES PART SELECTION GUIDE....................................................................................................62
6.1 Part Number Definition...........................................................................................................................63
PACKAGE OUTLINE .........................................................................................................................................64
7.1
7.2
7.3
LQFP-128 (14X14X1.4mm body, 0.4mm pitch).....................................................................................64
LQFP-64 (10X10X1.4mm body, 0.5mm pitch).......................................................................................65
TQFP-64 (10X10X1.0mm body, 0.5mm pitch) ......................................................................................66
8.
REVISION HISTORY .........................................................................................................................................69
Nuvoton Technology Corp.
http://www.nuvoton.com/
4
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
1. GENERAL DESCRIPTION
The N3290x seires built on the ARM926EJ-S CPU core and integrated with JPEG codec, CMOS
sensor interface, 32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of
application needs while saving the BOM cost. The combination of ARM926 @ 200MHz, synchronous
DRAM, 2D BitBLT accelerator, CMOS image sensor interface, LCD panel interface, USB 1.1 Host &
USB2.0 HS Device makes N3290x series the best choice for LCD ELA devices.
Maximum resolution for N3290 series is XVGA (1,024x768) @ TFT LCD panel. The 2D BitBLT
accelerator accelerates the graphic compution to make the rendering smooth and off-load CPU to save
power consumption.
The N3290x seires is well-positioned in terms of cost/performance for the applications which bitmap
graphics is extensively used or CMOS Image Sensor (CIS) interface is required.
The N3290x series is for application under Linux OS and leverage the driver availability of emerging
functionalities like Wi-Fi, browser, etc. On the other hand, the open source code environment also give
the product development more flexible.
To meet the different requirement of the overall system BOM cost, the different size of DRAM is
stacked with N3290x main SoC into one package, that is, multi-chip package (MCP). The N32901x
series particularly designed with 1Mbitx16 3.3V SDRAM. The N32903x series particularly designed
with 4Mbitx16 1.8V DDR SDRAM. One 16Mbitx16 1.8V DDR2 SDRAM stacked inside the N32905x
series to ensure higher performance and minimize the system design efforts, like EMI & noise
coupling. Total BOM cost could be reduced by employing 2-layer PCB along with the elimination of
damping resistors, EMI prevention components, etc. Advantages including, but not limited to, less PCB
space, shorter lead time, and higher / reliable production yield.
1.1 Applications
ELA (Educational Learning Aid)
HMI
Security
Home Appliance
Advertisement
Nuvoton Technology Corp.
http://www.nuvoton.com/
5
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
2. FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
Frequency up to 200MHz@1.8V core power operation voltage
JTAG interface supported for development and debugging
Internal SRAM & ROM
8KB internal SRAM and 16KB IBR internal booting ROM supported
IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
Memory card
SD card
SD-to-NAND flash bridge
Raw NAND Flash
SPI Flash
USB
EDMA (Enhanced DMA)
Totally 5 DMA channels supported
4 peripheral DMA channels for transfer between memory and on-chip
peripherals, such as ADC, UART and SPI
One dedicated channel for memory-to-memory transfer
Byte, half-word and word data width types supported
Single and burst transfer modes supported
Block transfer supported in memory-to-memory transfer channel
Color format transformation supported in memory-to-memory transfer
channel
Source color format could be RGB555, RGB565 and YCbCr422
Destination color format could be RGB555, RGB565 and YCbCr422
Auto reload supported for continuous data transfer
Interrupt generation supported in the half-of-transfer or end-of-transfer
Capture (CMOS Sensor I/F)
CCIR601 & CCIR656 interfaces supported for connection to CMOS image
sensor
Resolution up to 2M pixel for Still Image Capture, 640x480 (VGA) resolution
for MJPEG Video Streaming
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color format supported for data
storing to system memory
Planar and packet data formats supported for data storing to system
memory
Image cropping supported with the cropping window up to 4096x2048
Image scaling-down supported
Vertical and horizontal scaling-down for preview mode supported
The scaling factor is N/M
Two pairs of configurable 8-bit N and 8-bit M for vertical and
horizontal scaling-down
The value of N has to equal to or less than M
Frame rate control supported
Combines two interlace fields to a single frame supported for data in from
TV-decoder
Nuvoton Technology Corp.
http://www.nuvoton.com/
6
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
JPEG Codec
Baseline Sequential mode JPEG codec function compliant with ISO/IEC
10918-1 international JPEG standard supported.
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y
only) format image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and
gray-level (Y only) format image
Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-
table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control
in encode mode
Support rotate function in encode mode
Packet Format
Support to encode interleaved YUYV format input image, output
bitstream 4:2:2 and 4:2:0 format
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image RGB555, RGB565 and RGB888 formats.
The encoded JPEG bit-stream format is fully compatible with JFIF and
EXIF standards
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-
table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for
Y444 for decode mode
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control
in encode mode
2D Accelerator
BitBLT operation
2x2 transform matrix with effects:
Scale
Translate
Rotate
Shear
Fill
Alpha blending and color transformation supported
Source format for operations: supported color format of source bitmap
Rectangle Fill with single color – ARGB8888
Fill with blending effect supported
Supported color formats
Source
Nuvoton Technology Corp.
http://www.nuvoton.com/
7
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
1 bit/pixel, 2 bits/pixel, 4 bits/pixel, 8 bits/pixel with RGB color
palette
Destination
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
VPOST
8/16/18-bit SYNC type and 8/9/16/18-bit MPU type TFT LCD supported
Color format supported:
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for
data in
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for
data out
XGA (1024x768), SVGA (800x600), WVGA (800x480), D1 (720X480), VGA
(640x480), WQVGA (480x272), QVGA (320x240) and HVGA (640x240)
resolution supported
The maximum resolution is up to D1 (720X480) for TV output
The maximum resolution is up to 1024X768 for TFT LCD panel for still
image displaying
The maximum resolution is up to 480x272 for TFT LCD panel for MJPEG
video displaying up to 25fps.
Display scaler – to fit different size of LCD panels
Horizontal: At most 4.0x scale
Vertical: At most 3.0x scale
For SYNC type LCD:
For 8-bit bus
CCIR601 YCbCr422 packet mode (NTSC/PAL) supported
CCIR601 RGB Dummy mode (NTSC/PAL) supported
CCIR656 interface supported
RGB Through mode supported
For 16/18-bit bus
Parallel pixel data output mode (1-pixel/1-clock)
Color format transform supported:
Color format transform between YCbCr422 and RGB565
Color format transform from YCbCr422 to RGB888
Support OSD function to overlap system information like battery life,
brightness tuning, volume tuning or muting, etc.
Frame Switch Controller
Frame relation controlled between VPOST and Capture supported
2 modes supported to switch Frame Buffer Base
Frame Ratio Mode (16 selectable ratio)
Frame sync mode
Double/triple buffers supported
SPU (Sound Processing Unit)
32 stereo channels supported
PCM8/PCM16/4-bit MDPCM/TONE source format supported
7-bit volume control supported for each of 32 channels
5-bit pan control supported for each L/R of 32 channels
10-band equalizer supported
Nuvoton Technology Corp.
http://www.nuvoton.com/
8
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Special code supported for loop playing and event detection
Audio DAC
16-bit stereo DAC supported with headphone driver output
H/W volume control supported
I2S Controller
I2S interface supported to connect external audio codec
16/18/20/24-bit data format supported
Storage Interface Controller
Interface to NAND Flash:
8-bit data bus width supported
SLC and MLC type NAND Flash supported
512B, 2KB, 4KB, and 8KB page size NAND Flash supported
ECC4, ECC8, ECC12 and ECC15 algorithm supported for ECC generation,
error detection and error correction
PBA-NAND flash supported
Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported
SD-to-NAND flash bridge supported
DMA function supported to accelerate the data transfer between system
memory and NAND Flash or SD/MMC/SDIO/SDHC/micro-SD
USB Device Controller
USB2.0 HS (High-Speed) x 1 port
6 configurable endpoints supported
Control, Bulk, Interrupt and Isochronous transfers supported
Suspend and remote wakeup supported
USB Host Controller
USB1.1 Host one H/W Engine, two pin locations.
Fully compliant with USB Revision 1.1 specification
Open Host Controller Interface (OHCI) Revision 1.0 compatible
Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported
Control, Bulk, Interrupt and Isochronous transfers supported
Timer & Watch-Dog Timer
Two 32-bit with 8-bit pre-scalar timers supported
One programmable 24-bit Watch-Dog Timer supported
PWM
4 PWM channel outputs supported
16-bit counter supported for each PWM channel
Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM
channels
Two clock-dividers supported and each divider shared by two PWM channels
Two Dead-Zone generators supported and each generator shared by two
PWM channels
Auto reloaded mode and one-shot pulse mode supported
Capture function supported
Nuvoton Technology Corp.
http://www.nuvoton.com/
9
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
UART
A high speed UART supported:
Baud rate is up to 1M bps
4 signals TX, RX, CTS and RTS supported
A normal UART supported:
Baud rate is up to 115.2K bps
2 signals TX and RX supported only
SPI
SPI controller is supported
N3290xRxDN and N3290xUxDN series support one SPI controller
N3290xKxDN series can support up to two SPI controllers
Both master and slave mode are supported in SPI interface
Two chip selection signals for two SPI devices
I2C
One I2C channel supported
Compatible with Philips’s I2C standard and only master mode supported
Multi-master operation supported
Advanced Interrupt Controller
Total 32 interrupt source supported
Configurable interrupt type:
Low-active level triggered interrupt
High-active level triggered interrupt
Low-active edge (falling edge) triggered interrupt
High-active edge (rising edge) triggered interrupt
Individual interrupt mask bit for each interrupt source
8 different priority levels supported
Daisy-chain priority mechanism supported for interrupts with same priority
level
Low priority interrupt automatic masking supported for interrupt nesting
RTC
Independent power plane supported
32.768 KHz crystal oscillation circuit supported
Time counter (second, minute, hour) and Calendar counter (day, month,
year) supported
Alarm supported (second, minute, hour, day, month and year)
12/24-hour mode and Leap year supported
Alarm to wake chip up from Standby mode or from Power-down mode
supported
Wake chip up from Power-down mode by input pin supported
Power-off chip by register setting supported
Power-on timeout is supported for low battery protection
GPIO
80 programmable general purpose I/Os supported and separated into 5
groups
Individual configuration supported for each I/O signal
Configurable interrupt control functions supported
Nuvoton Technology Corp.
http://www.nuvoton.com/
10
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Configurable de-bounce circuit supported for interrupt function
ADC
Multi-channel, 10-bit ADC supported
2 channels dedicated for 4-wire resistive touch sensor inputs
2 channels dedicated for Audio ADC with Microphone pre-Amp & AGC
3 channels reserved for various purposes, like LVD (Low Voltage
Detection), keypad input, and light sensor
Input voltage range from 0V ~ 3.3V supported
Maximum 25MHz input clock supported
Maximum 400K/s conversion rate supported
LVR (Low Voltage Reset) supported
Power Management
Advanced power management including Power Down, Deep Standby, CPU
Standby, and Normal Operating modes
Normal Operating Mode
Core power is 1.8V and chip is in normal operation
CPU Standby Mode
Core power is 1.8V and only ARM CPU clock is turned OFF
Deep Standby Mode
Core power is 1.8V and all IP clocks are turned OFF
Power Down Mode
Only the RTC power is ON. Other 3.3V and 1.8V power are OFF
Software Support
Development Tools
Bootloader / Diagnostic Program / NAND Writer Program: ADS 1.2 or
RVDS 2.x or 3.x
Linux Kernel (2.6.17.14) / System Manager: GCC 4.2
TurboWriter / Sync Tool: Microsoft VC 6.0
NAND Flash File System
FAT12, FAT16 and FAT32 with long filename are supported
Hidden disk is supported
RAM disk is supported
S/W audio Library
Decoders with ADPCM / MP3 / ACC / OGG / WMA format support
32-polyphony Wavetable MIDI synthesizer
Programmable sampling rate and target bit rate
USB Driver
MS (Mass Storage) Class
HID (Human Interface Device) Class
Operating Voltage
I/O: 3.3V
Core: 1.8V for 200MHz
Package
LQFP-128 MCP
TPFP-64 MCP with EPAD
LQFP-64 MCP
Nuvoton Technology Corp.
http://www.nuvoton.com/
11
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3. PIN DIAGRAM
3.1 N32901U1DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSS
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDD33
GPD[12]/ SPI0_CLK
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
MVDD33
MVSS
NC
90
80
70
GPE[4]/
GPE[5]/
MVSS
VDD18
UD_CDET
10
/
GPE[6]
HUR_RTS
TRST_/
/SPI0_CS1_/
GPD[4]
GPE[7]/
GPE[2]/
GPE[3]
/
SDCLK
TDO
TDI
HUR_CTS
PWM3
SDDAT[0]
SDDAT[1]
XIN
/
/
/
/
/
/
/
/
/
/
/
GPD[3]
GPD[2]
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSS
MVDD33
MVSS
MVDD33
MVDD33
NC
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD33
VSS
30
RTC_XOUT
ADC_AIN[3]
MVSS
/
/LVDATA[17]
GPE[1] SVSYNC
Nuvoton Technology Corp.
http://www.nuvoton.com/
12
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.2 N32903U5DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSS
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDD18
GPD[12]/ SPI0_CLK
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
MVDD18
MVSS
MVREF
MVSS
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
10
/
GPE[6]
HUR_RTS
TRST_/
/SPI0_CS1_/
GPD[4]
GPE[7]/
GPE[2]/
GPE[3]
/
SDCLK
TDO
TDI
HUR_CTS
PWM3
SDDAT[0]
SDDAT[1]
XIN
/
/
/
/
/
/
/
/
/
/
/
GPD[3]
GPD[2]
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSS
MVDD18
MVSS
MVDD18
MVDD18
MVREF
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD18
VSS
30
RTC_XOUT
ADC_AIN[3]
MVSS
/
/LVDATA[17]
GPE[1] SVSYNC
Nuvoton Technology Corp.
http://www.nuvoton.com/
13
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.3 N32905U3DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSS
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDD18
GPD[12]/ SPI0_CLK
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
MVDD18
MVSS
MVREF
MVSS
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
10
/
GPE[6]
HUR_RTS
TRST_/
/SPI0_CS1_/
GPD[4]
GPE[7]/
GPE[2]/
GPE[3]
/
SDCLK
TDO
TDI
HUR_CTS
PWM3
SDDAT[0]
SDDAT[1]
XIN
/
/
/
/
/
/
/
/
/
/
/
GPD[3]
GPD[2]
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSS
MVDD18
MVSS
MVDD18
MVDD18
MVREF
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD18
VSS
30
RTC_XOUT
ADC_AIN[3]
MVSS
/
/LVDATA[17]
GPE[1] SVSYNC
Nuvoton Technology Corp.
http://www.nuvoton.com/
14
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.4 N32901R1DN (LQFP-64)
GPD[13]
/
1
5
SPI0_CS0_
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_HPVDD33
ADAC_HPVSS33
GPD[14]/
GPD[15]/
SPI0_DI
SPI0_DO
45
40
35
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
MVDD33
VSS
GPE[6] /
GPE[7] /
SDCMD
SDCLK
VDD18
UD_CDET
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
HUR_RXD / PWM2 / GPD[2]
HUR_TXD / PWM1 / GPD[1]
10
15
XIN
XOUT
RST_
GPA[1]/
SD_CD
VSS
PLL_VDD18
UD_DM
GPA[3]/
UHL_DP1
/UHL_DM1
/SPI0_CS1_
GPA[4]
GPA[5]
UD_DP
ADC_AIN[2]
UD_VDD33
Nuvoton Technology Corp.
http://www.nuvoton.com/
15
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.5 N32903R5DN (TQFP-64 EPAD)
GPD[13]
/
1
5
SPI0_CS0_
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_HPVDD33
ADAC_HPVSS33
GPD[14]/
GPD[15]/
SPI0_DI
SPI0_DO
45
40
35
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
MVDD18
MVREF
VDD18
GPE[6] /
GPE[7] /
SDCMD
SDCLK
UD_CDET
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
HUR_RXD / PWM2 / GPD[2]
HUR_TXD / PWM1 / GPD[1]
10
15
XIN
XOUT
RST_
GPA[1]/
SD_CD
MVREF
PLL_VDD18
UD_DM
GPA[3]/
UHL_DP1
/UHL_DM1
/SPI0_CS1_
GPA[4]
GPA[5]
UD_DP
ADC_AIN[2]
UD_VDD33
Nuvoton Technology Corp.
http://www.nuvoton.com/
16
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.6 N32905R3DN (TQFP-64 EPAD)
GPD[13]
/
1
5
SPI0_CS0_
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_HPVDD33
ADAC_HPVSS33
GPD[14]/
GPD[15]/
SPI0_DI
SPI0_DO
45
40
35
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
MVDD18
MVREF
VDD18
GPE[6] /
GPE[7] /
SDCMD
SDCLK
UD_CDET
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
HUR_RXD / PWM2 / GPD[2]
HUR_TXD / PWM1 / GPD[1]
10
15
XIN
XOUT
RST_
GPA[1]/
SD_CD
MVREF
PLL_VDD18
UD_DM
GPA[3]/
UHL_DP1
/UHL_DM1
/SPI0_CS1_
GPA[4]
GPA[5]
UD_DP
ADC_AIN[2]
UD_VDD33
Nuvoton Technology Corp.
http://www.nuvoton.com/
17
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.7 N3290xKxDN (LQFP128)
Nuvoton Technology Corp.
http://www.nuvoton.com/
18
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
3.8 N32901R7DN (TQFP-64 EPAD)
Nuvoton Technology Corp.
http://www.nuvoton.com/
19
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
4. PIN DESCRIPTION
4.1 N3290xUxDN Pin Description
Pin No Name
SPCLK
Type
Group
Description
IOU CAP
Sensor Interface Pixel Clock, Input
GPIO Port B Bit 1
GPB[1]
1
IOU GPIOB
IOU SD1
IOU USB
OU CAP
IOU JTAG
IOU SD1
IOU USB
IOU I2C
SD1_DAT[0]
SD Port 1 Data Bit 0
UHL_DM1
SCLKO
USB Host 1.0 Lite Port 1, D-E154
Clock to Sensor Module, Output
GPIO Port B Bit 0
GPB[0]
2
3
SD1_DAT[1]
UHL_DP1
ISDA
SD Port 1 Data Bit 1
USB Host 1.0 Lite Port 1, D+
I2C Interface Data
GPB[14]
LFMARK
LMVSYNC
ISCK
IOU GPIOB
GPIO Port B Bit 14
IU
LCD
MPU LCD Interface Frame Mark, Input
MPU LCD Interface Mode VSYNC, Output
I2C Interface Clock, Output
GPIO Port B Bit 13
OU LCD
OU I2C
4
5
GPB[13]
SPI0_CLK
GPD[12]
IOU GPIOB
IOU SPI0
IOU GPIOD
SPI Port 0 Clock;Output in Master Mode;Input in Slave Mode
GPIO Port D Bit 12
SPI Port 0 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
GPIO Port D Bit 13
SPI0_CS0_
IOU SPI0
6
GPD[13]
SPI0_DI
IOU GPIOD
IU
SPI0
SPI Port 0 Data Input
7
8
GPD[14]
SPI0_DO
GPD[15]
SD0_DAT[2]
GPE[4]
IOU GPIOD
OU SPI0
GPIO Port D Bit 14
SPI Port 0 Data Output
IOU GPIOD
IOU SD0
GPIO Port D Bit 15
SD Port 0 Data Bit 2
9
IOU GPIOE
IOU SD0
GPIO Port E Bit 4
SD0_DAT[3]
GPE[5]
SD Port 0 Data Bit 3
10
11
IOU GPIOE
IOU SD0
GPIO Port E Bit 5
SD0_CMD
GPE[6]
SD Port 0 Command/Response
GPIO Port E Bit 6
IOU GPIOE
OU SD0
SD0_CLK
GPE[7]
SD Port 0 Clock, Output
12
13
IOU GPIOE
IOU SD0
GPIO Port E Bit 7
SD0_DAT[0]
SD Port 0 Data Bit 0
Nuvoton Technology Corp.
http://www.nuvoton.com/
20
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
GPE[2]
Type
Group
Description
IOU GPIOE
IOU SD0
GPIO Port E Bit 2
SD0_DAT[1]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
14
GPE[3]
XIN
IOU GPIOE
15
16
17
18
I
XTAL
XTAL
Core
12MHz Crystal Input
12MHz Crystal Output
Core Logic Power (1.8V)
SDRAM I/F Ground (0V)
SDRAM Power, please follow that:
XOUT
VDD18
VSSQ
O
P
G
MVDD
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
19
20
21
MVDD
VSSQ
MVDD
P
G
P
MVDD
MVDD
MVDD
MVDD=3.3V powered when N32901U1DN is installation
SDRAM Ground (0V)
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
MVDD=3.3V powered when N32901U1DN is installation
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
22
23
MVDD
P
MVDD
MVDD=3.3V powered when N32901U1DN is installation
when N32901U1DN is installation
NC
--
P
NC
1/2 MVDD (0.9V) for DDR_VREF, when N32903U5DN or
N32905U3DN are installation
MVREF
MVDD
24
25
26
27
28
29
PLL_UD_VDD18
UD_VSS
P
G
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
USB
USB
USB
USB
USB
USB2.0 Device Ground (0V)
UD_DM
I/O
I/O
P
USB 2.0 Device D-.
UD_DP
USB 2.0 Device D+.
UD_VDD33
UD_REXT
USB 2.0 Device PHY 3.3V
O
External Resistor 12.1K resistor connected to ground
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
30
MVDD
P
MVDD
MVDD=3.3V powered when N32901U1DN is installation
Ground (0V)
31
32
VSS
G
GND
LVDATA[17]
IOU LCD
SYNC/MPU LCD Interface Data Bit 17
Nuvoton Technology Corp.
http://www.nuvoton.com/
21
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
SVSYNC
Type
IU
Group
CAP
Description
Sensor Interface VSYNC, Input
GPIO Port E Bit 1
GPE[1]
IOU GPIOE
IOU LCD
LVDATA[16]
SHSYNC
GPE[0]
SYNC/MPU LCD Interface Data Bit 16
Sensor Interface HSYNC, Input
GPIO Port E Bit 0
33
34
IU
CAP
IOU GPIOE
IOU LCD
LVDATA[15]
GPC[15]
SYNC/MPU LCD Interface Data Bit 15
GPIO Port C Bit 15
IOU GPIOC
SPDATA[7]
KPI_SI[7]
LVDATA[14]
GPC[14]
IU
IU
CAP
KPI
Sensor Interface Data Bit 7, Input
KPI Scan In Bit 7
IOU LCD
SYNC/MPU LCD Interface Data Bit 14
GPIO Port C Bit 14
IOU GPIOC
35
36
37
38
39
SPDATA[6]
KPI_SI[6]
LVDATA[13]
GPC[13]
IU
IU
CAP
KPI
Sensor Interface Data Bit 6, Input
KPI Scan In Bit 6
IOU LCD
SYNC/MPU LCD Interface Data Bit 13
GPIO Port C Bit 13
IOU GPIOC
SPDATA[5]
KPI_SI[5]
LVDATA[12]
GPC[12]
IU
IU
CAP
KPI
Sensor Interface Data Bit 5, Input
KPI Scan In Bit 5
IOU LCD
SYNC/MPU LCD Interface Data Bit 12
GPIO Port C Bit 12
IOU GPIOC
SPDATA[4]
KPI_SI[4]
LVDATA[11]
GPC[11]
IU
IU
CAP
KPI
Sensor Interface Data Bit 4, Input
KPI Scan In Bit 4
IOU LCD
SYNC/MPU LCD Interface Data Bit 11
GPIO Port C Bit 11
IOU GPIOC
SPDATA[3]
KPI_SI[3]
LVDATA[10]
GPC[10]
IU
IU
CAP
KPI
Sensor Interface Data Bit 3, Input
KPI Scan In Bit 3
IOU LCD
SYNC/MPU LCD Interface Data Bit 10
GPIO Port C Bit 10
IOU GPIOC
SPDATA[2]
KPI_SI[2]
LVDATA[9]
GPC[9]
IU
IU
CAP
KPI
Sensor Interface Data Bit 2, Input
KPI Scan In Bit 2
IOU LCD
SYNC/MPU LCD Interface Data Bit 9
GPIO Port C Bit 9
IOU GPIOC
40
41
SPDATA[1]
KPI_SI[1]
LVDATA[8]
IU
IU
CAP
KPI
Sensor Interface Data Bit 1, Input
KPI Scan In Bit 1
IOU LCD
SYNC/MPU LCD Interface Data Bit 8
Nuvoton Technology Corp.
http://www.nuvoton.com/
22
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
GPC[8]
Type
Group
Description
IOU GPIOC
GPIO Port C Bit 8
SPDATA[0]
IU
IU
CAP
KPI
Sensor Interface Data Bit 0, Input
KPI Scan In Bit 0
KPI_SI[0]
LVDATA[7]
GPC[7]
IOU LCD
SYNC/MPU LCD Interface Data Bit 7
GPIO Port C Bit 7
42
43
IOU GPIOC
IOU LCD
LVDATA[6]
GPC[6]
SYNC/MPU LCD Interface Data Bit 6
GPIO Port C Bit 6
IOU GPIOC
CFG[10]
LVDATA[5]
GPC[5]
IU
SYSTEM
Chip Power-On Configuration Bit [10], Input
SYNC/MPU LCD Interface Data Bit 5
GPIO Port C Bit 5
IOU LCD
44
45
IOU GPIOC
CFG[9]
IU
SYSTEM
Chip Power-On Configuration Bit [9], Input
GPIO Port C Bit 4
LVDATA[4]
GPC[4]
IOU LCD
IOU GPIOC
GPIO Port C Bit 4
CFG[8]
IU
SYSTEM
Chip Power-On Configuration Bit [8], Input
SYNC/MPU LCD Interface Data Bit 3
GPIO Port C Bit 3
LVDATA[3]
GPC[3]
IOU LCD
IOU GPIOC
IOU LCD
IOU GPIOC
IOU LCD
IOU GPIOC
IOU LCD
IOU GPIOC
OU LCD
46
47
48
49
LVDATA[2]
GPC[2]
SYNC/MPU LCD Interface Data Bit 2
GPIO Port C Bit 2
LVDATA[1]
GPC[1]
SYNC/MPU LCD Interface Data Bit 1
GPIO Port C Bit 1
LVDATA[0]
GPC[0]
SYNC/MPU LCD Interface Data Bit 0
GPIO Port C Bit 0
LVDE
SYNC LCD Interface Data Enable, Output, High Active
MPU LCD Interafec Register Select
GPIO Port D Bit 11
50
51
LRS
OU LCD
GPD[11]
LVSYNC
LRD
IOU GPIOD
OU LCD
SYNC LCD Interface VSYNC, Output, High Active
MPU I80 mode LCD Interface Read, active low
MPU M68 mode LCD Interface Read Write Enable/Disable ,
High Enable
OU LCD
LEN
OU LCD
GPD[10]
LHSYNC
LWR
IOU GPIOD
OU LCD
OU LCD
LCD Interface Data Enable, High Active.
SYNC LCD Interface HSYNC, Output, High Active
MPU I80 mode LCD Interfacer Write, active low
MPU M68 mode LCD interface R/W, High is read command
and Low is write instruction
52
LR/W
OU LCD
Nuvoton Technology Corp.
http://www.nuvoton.com/
23
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
GPD[9]
Type
IOU GPIOD
Core
Group
Description
GPIO Port D Bit 9
Core Logic Power (1.8V)
53
VDD18
P
LPCLK
OU LCD
OU LCD
IOU GPIOB
SYNC LCD Interface Pixel Clock, Output
MPU LCD Interface Chip Enable, active low
GPIO Port B Bit 15
54
LCS
GPB[15]
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
VDD33
P
G
I
I/O
I/O Power (3.3V)
ADC_VSS33
ADC_TP_YM
ADC_TP_XM
ADC_TP_XP
ADC_TP_YP
ADC_VDD33
ADC_AIN[0]
ADC_AIN[1]
ADC_AIN[2]
VSS
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
GND
ADC
RTC
RTC
RTC
ADC Ground (0V)
Touch Panel YM
I
Touch Panel XM
I
Touch Panel XP
I
Touch Panel YP
P
I
ADC Power (3.3V)
ADC MIC+
I
ADC MIC-
I
ADC Analog Input Channel 2
Ground (0V)
G
I
ADC_AIN[3]
RTC_XOUT
RTC_XIN
ADC Analog Input Channel 3
32768Hz Crystal Output
32768Hz Crystal Input
O
I
Wakeup Enable or Power switch Input with Low Active (an external
pull high resistor is need)
RTC_RWAKE_
I
Power Enable for external power IC enable pin, Open-Drain output
(an external pull high resistor is need)
70
71
72
RTC_RPWR
RTC_VDD1.8V
VDD33
O
P
P
RTC
RTC
I/O
RTC Power (1.8V)
I/O Power (3.3V)
GPA[6]
IOU GPIOA
OU SPI1
OU KPI
GPIO Port A Bit 6
73
74
SPI1_CS1_
KPI_SO[4]
GPA[5]
SPI Port 1 Device Select 1, Output, Low Active
KPI Scan Out Bit 4
IOU GPIOA
OU SPI0
OU KPI
GPIO Port A Bit 5
SPI0_CS1_
KPI_SO[3]
GPA[4]
SPI Port 0 Device Select 1, Output, Low Active
KPI Scan Out Bit 3
IOU GPIOA
IOU USB
OU KPI
GPIO Port A Bit 4
75
76
UHL_DM1
KPI_SO[2]
GPA[3]
USB Host 1.0 Lite Port 1, D-
KPI Scan Out Bit 2
IOU GPIOA
IOU USB
GPIO Port A Bit 3
UHL_DP1
USB Host 1.0 Lite Port 1, D+
Nuvoton Technology Corp.
http://www.nuvoton.com/
24
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
KPI_SO[1]
Type
Group
Description
OU KPI
KPI Scan Out Bit 1
GPA[2]
IOU GPIOA
OU LCD
GPIO Port A Bit 2
LMVSYNC
LFMARK
KPI_SO[0]
GPA[1]
MPU LCD Interface VSYNC, Output
77
IU
LCD
MPU LCD Interface Frame Mark, Input
KPI Scan Out Bit 0
OU KPI
IOU GPIOA
GPIO Port A Bit 1
78
79
80
SD_CD_
GPA[0]
IU
IOU GPIOA
IU SYSTEM
OU SYSTEM
ID JTAG
SD
SD Card Detect, Input, Low Active
GPIO Port A Bit 0
RST_
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface Test Clock, Input
GPIO Port D Bit 0
WDT_RST_
TCK
GPD[0]
SPI1_CS1_
PWM0
IOD GPIOD
OD SPI1
OD PWM
81
82
83
84
85
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
TMS
IU
JTAG
JTAG Interface Test Mode Select, Input
GPIO Port D Bit 1
GPD[1]
HUR_TXD
PWM1
IOU GPIOD
OU UART
OU PWM
High-Speed UART TX Data, Output
PWM Channel 1
TDI
IU
IOU GPIOD
IU UART
JTAG
JTAG Interface Test Data In, Input
GPIO Port D Bit 2
GPD[2]
HUR_RXD
PWM2
High-Speed UART RX Data, Input
PWM Channel 2
OU PWM
OU JTAG
IOU GPIOD
TDO
JTAG Interface Test Data Out, Output
GPIO Port D Bit 3
GPD[3]
HUR_CTS
PWM3
IU
OU PWM
IU JTAG
UART
High-Speed UART Clear-To-Send, Input, Low Active
PWM Channel 3
TRST_
JTAG Interface Test Reset, Input, Low Active
GPIO Port D Bit 4
GPD[4]
HUR_RTS
SPI0_CS1_
UD_CDET
VDD18
IOU GPIOD
OU UART
OU SPI0
High-Speed UART Reset-To-Send, Output, Low Active
SPI Port 0 Device Select 1, Output, Low Active
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
86
87
88
89
I
USB
P
G
P
Core
MVSS
MVDD
MVDD
SDRAM I/F Ground (0V)
MVREF
1/2 MVDD (0.9V) for DDR_VREF, when N32903U5DN and
Nuvoton Technology Corp.
http://www.nuvoton.com/
25
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
NC
Type
Group
Description
N32905U3DN are installation
when N32901U1DN is installation
SDRAM Ground (0V)
--
NC
90
VSSQ
G
MVDD
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
91
MVDD
P
P
MVDD
MVDD
MVDD=3.3V powered when N32901U1DN is installation
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903U5DN or N32905U3DN
are installation
92
MVDD
MVDD=3.3V powered when N32901U1DN is installation
Audio DAC Headphone Driver Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio Headphone Left Channel Output
Ground (0V)
93
94
95
96
97
98
ADAC_HPVSS33
ADAC_HPVDD33
ADAC_HPOUT_L
VSS
G
P
AUDIO
AUDIO
AUDIO
GND
O
G
O
G
ADAC_HPOUT_R
ADAC_AVSS33
AUDIO
AUDIO
Audio Headphone Right Channel Output
Audio DAC Ground (0V)
Audio DAC Reference Voltage Output, please connect 1uF
capacitor to DAC ground
99
ADAC_VREF
O
AUDIO
100
101
102
ADAC_AVDD33
ADAC_AVDD33
VDD18
P
P
P
AUDIO
AUDIO
Core
Audio DAC Power (3.3V)
Audio DAC Power (3.3V)
Core Logic Power (1.8V)
GPA[7]
IOU GPIOA
OU KPI
GPIO Port A Bit 7
103
104
105
106
107
108
KPI_SO[5]
ND[0]
KPI Scan Out Bit 5
IOU NAND
NAND Interface Data Bit [0]
CFG[0]
IU
SYSTEM
Chip Power-On Configuration Bit [0], Input
NAND Interface Data Bit [1]
ND[1]
IOU NAND
CFG[1]
IU
SYSTEM
Chip Power-On Configuration Bit [1], Input
NAND Interface Data Bit [2]
ND[2]
IOU NAND
CFG[2]
IU
SYSTEM
Chip Power-On Configuration Bit [2], Input
NAND Interface Data Bit [3]
ND[3]
IOU NAND
CFG[3]
IU
SYSTEM
Chip Power-On Configuration Bit [3], Input
NAND Interface Data Bit [4]
ND[4]
IOU NAND
CFG[4]
IU
SYSTEM
Chip Power-On Configuration Bit [4], Input
Nuvoton Technology Corp.
http://www.nuvoton.com/
26
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
Type
Group
Description
ND[5]
109
IOU NAND
NAND Interface Data Bit [5]
CFG[5]
IU
SYSTEM
Chip Power-On Configuration Bit [5], Input
NAND Interface Data Bit [6]
ND[6]
110
IOU NAND
CFG[6]
IU
SYSTEM
Chip Power-On Configuration Bit [6], Input
NAND Interface Data Bit [7]
ND[7]
111
IOU NAND
CFG[7]
IU
IU
SYSTEM
NAND
Chip Power-On Configuration Bit [7], Input
NAND Interface Busy 1, Input, Low Active
GPIO Port D Bit 6
NBUSY1_
GPD[6]
112
113
114
115
IOU GPIOD
IOU SD2
SD2_DAT[2]
NBUSY0_
GPD[5]
SD Port 2 Data Bit 2
IU
NAND
NAND Interface Busy 0, Input, Low Active
GPIO Port D Bit 5
IOU GPIOD
IOU SD2
SD2_DAT[3]
NWR_
SD Port 2 Data Bit 3
OU NAND
IOU GPIOD
IOU SD2
NAND Interface Write Enable, Output, Low Active
GPIO Port D Bit 8
GPD[8]
SD2_CMD
NRE_
SD Port 2 Command/Response
NAND Interface Read Enable, Output, Low Active
GPIO Port D Bit 7
OU NAND
IOU GPIOD
OU SD2
GPD[7]
SD2_CLK
NCLE
SD Port 2 Clock, Output
OU NAND
IOU GPIOE
OU NAND
IOU GPIOE
OU NAND
IOU GPIOE
IOU SD2
NAND Interface Command-Latch-Enable, Output, High Active
GPIO Port E Bit 11
116
117
GPE[11]
NALE
NAND Interface Address-Latch-Enable, Output, High Active
GPIO Port E Bit 10
GPE[10]
NCS1_
NAND Interface Chip Select 1, Output, Low Active
GPIO Port E Bit 9
118
119
120
121
122
123
GPE[9]
SD2_DAT[0]
VSS
SD Port 2 Data Bit 0
G
GND
Ground (0V)
NCS0_
IU
NAND
NAND Interface Chip Select 0, Output, Low Active
GPIO Port E Bit 8
GPE[8]
IOU GPIOE
IOU SD2
SD2_DAT[1]
VDD33
SD Port 2 Data Bit 1
P
I/O
I/O Power (3.3V)
URTXD
GPA[10]
SPI1_CS1_
URRXD
OU UART
IOU GPIOA
OU SPI1
UART TX Data, Output
GPIO Port A Bit 10
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
IU
UART
Nuvoton Technology Corp.
http://www.nuvoton.com/
27
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
GPA[11]
Type
Group
Description
IOU GPIOA
OU LCD
GPIO Port A Bit 11
LMVSYNC
LFMARK
SPDATA[1]
GPB[6]
MPU LCD Interface VSYNC, Output
IU
IU
LCD
CAP
MPU LCD Interface Frame Mark, Input
Sensor Interface Data Bit 1, Input
GPIO Port B Bit 6
124
125
IOU GPIOB
I2S_DIN
IU
IU
I²S
I2S Interface Data Input
SPDATA[0]
GPB[5]
CAP
Sensor Interface Data Bit 0, Input
GPIO Port B Bit 5
IOU GPIOB
OU I2S
I2S_DOUT
SD1_DAT[2]
SFIELD
I2S Interface Data Output
SD Port 1 Data Bit 2
IOU SD1
IU
CAP
Sensor Interface Even/ODD Field Indicator, Input
GPIO Port B Bit 4
GPB[4]
IOU GPIOB
OU I²S
126
127
128
I2S_WS
I2S Interface Word Select, Output
SD Port 1 Data Bit 3
SD1_DAT[3]
SVSYNC
GPB[3]
IOU SD1
IU
IOU GPIOB
IU I²S
IOU SD1
IU CAP
CAP
Sensor Interface VSYNC, Input
GPIO Port B Bit 3
I2S_BCLK
SD1_CMD
SHSYNC
GPB[2]
I2S Interface Clock, Input
SD Port 1 Command/Response
Sensor Interface HSYNC, Input
GPIO Port B Bit 2
IOU GPIOB
OU I²S
I2S_MCLK
SD1_CLK
Clock to I2S Codec, Output
SD Port 1 Clock, Output
OU SD1
4.2 N32901R1DN, N32903R5DN and N32905R3DN Pin Description
Pin No Name
Type Group
Description
SPI Port 0 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
GPIO Port D Bit 13
SPI0_CS0_
IOU SPI0
1
GPD[13]
SPI0_DI
GPD[14]
SPI0_DO
GPD[15]
SD0_DAT[2]
GPE[4]
IOU GPIOD
IU SPI0
SPI Port 0 Data Input
2
3
4
IOU GPIOD
OU SPI0
GPIO Port D Bit 14
SPI Port 0 Data Output
GPIO Port D Bit 15
IOU GPIOD
IOU SD0
SD Port 0 Data Bit 2
IOU GPIOE
GPIO Port E Bit 4
Nuvoton Technology Corp.
http://www.nuvoton.com/
28
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
SD0_DAT[3]
Type Group
IOU SD0
Description
SD Port 0 Data Bit 3
GPIO Port E Bit 5
5
6
7
8
9
GPE[5]
IOU GPIOE
IOU SD0
SD0_CMD
GPE[6]
SD Port 0 Command/Response
GPIO Port E Bit 6
IOU GPIOE
OU SD0
SD0_CLK
GPE[7]
SD Port 0 Clock, Output
GPIO Port E Bit 7
IOU GPIOE
IOU SD0
SD0_DAT[0]
GPE[2]
SD Port 0 Data Bit 0
GPIO Port E Bit 2
IOU GPIOE
IOU SD0
SD0_DAT[1]
GPE[3]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
IOU GPIOE
10
11
XIN
I
XTAL
XTAL
12MHz Crystal Input
12MHz Crystal Output
XOUT
O
1/2 MVDD (0.9V) for DDR_VREF, when N32903R5DN or
N32905R3 are installation
MVREF
P
MVDD
12
VSSQ
G
P
MVDD
SDRAM I/F Ground (0V), when N32901R1DN is installation
13
14
15
16
17
18
PLL_UD_VDD18
UD_DM
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
I/O USB
I/O USB
USB 2.0 Device D-.
UD_DP
USB 2.0 Device D+.
UD_VDD33
UD_REXT
VSS
P
O
G
USB
USB
GND
USB 2.0 Device PHY 3.3V
External Resistor 12.1K resistor connected to ground
Ground (0V)
GPC[15]
IOU GPIOC
IU CAP
GPIO Port C Bit 15
19
20
21
22
23
SPDATA[7]
GPC[14]
Sensor Interface Data Bit 7, Input
GPIO Port C Bit 14
IOU GPIOC
IU CAP
SPDATA[6]
GPC[13]
Sensor Interface Data Bit 6, Input
GPIO Port C Bit 13
IOU GPIOC
IU CAP
SPDATA[5]
GPC[12]
Sensor Interface Data Bit 5, Input
GPIO Port C Bit 12
IOU GPIOC
IU CAP
SPDATA[4]
GPC[11]
Sensor Interface Data Bit 4, Input
GPIO Port C Bit 11
IOU GPIOC
IU CAP
SPDATA[3]
GPC[10]
Sensor Interface Data Bit 3, Input
GPIO Port C Bit 10
IOU GPIOC
IU CAP
24
25
SPDATA[2]
GPC[9]
Sensor Interface Data Bit 2, Input
GPIO Port C Bit 9
IOU GPIOC
Nuvoton Technology Corp.
http://www.nuvoton.com/
29
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
SPDATA[1]
Type Group
IU CAP
Description
Sensor Interface Data Bit 1, Input
GPIO Port C Bit 8
GPC[8]
IOU GPIOC
IU CAP
26
SPDATA[0]
VDD18
Sensor Interface Data Bit 0, Input
Core Logic Power (1.8V)
I/O Power (3.3V)
27
28
29
30
31
32
33
P
P
G
P
I
Core
I/O
VDD33
ADC_VSS33
ADC_VDD33
ADC_AIN[0]
ADC_AIN[1]
ADC_AIN[2]
GPA[5]
ADC
ADC
ADC
ADC
ADC
ADC Ground (0V)
ADC Power (3.3V)
ADC MIC+
I
ADC MIC-
I
ADC Analog Input Channel 2
GPIO Port A Bit 5
IOU GPIOA
OU SPI0
34
35
36
37
38
SPI0_CS1_
GPA[4]
SPI Port 0 Device Select 1, Output, Low Active
GPIO Port A Bit 4
IOU GPIOA
IOU USB
UHL_DM1
GPA[3]
USB Host 1.0 Lite Port 1, D-
IOU GPIOA
IOU USB
GPIO Port A Bit 3
UHL_DP1
GPA[1]
USB Host 1.0 Lite Port 1, D+
GPIO Port A Bit 1
IOU GPIOA
IU SD
SD_CD_
RST_
SD Card Detect, Input, Low Active
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
GPIO Port D Bit 1
IU SYSTEM
OU SYSTEM
IOU GPIOD
OU UART
OU PWM
IOU GPIOD
IU UART
OU PWM
WDT_RST_
GPD[1]
39
40
HUR_TXD
PWM1
High-Speed UART TX Data, Output
PWM Channel 1
GPD[2]
GPIO Port D Bit 2
HUR_RXD
PWM2
High-Speed UART RX Data, Input
PWM Channel 2
41
42
UD_CDET
VDD18
I
USB
Core
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
P
1/2 MVDD (0.9V) for DDR_VREF, when N32903R5DN or
N32905R3 are installation
MVREF
MVSS
P
MVDD
MVDD
43
44
G
SDRAM I/F Ground (0V), when N32901R1DN is installation
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903R5DN or N32905R3DN are
installation
MVDD
P
MVDD
Nuvoton Technology Corp.
http://www.nuvoton.com/
30
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
Type Group
Description
MVDD=3.3V powered when N32901R1DN is installation
45
46
47
48
49
ADAC_HPVSS33
G
P
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
Audio DAC Headphone Driver Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio Headphone Left Channel Output
Audio Headphone Right Channel Output
Audio DAC Ground (0V)
ADAC_HPVDD33
ADAC_HPOUT_L
ADAC_HPOUT_R
ADAC_AVSS33
O
O
G
Audio DAC Reference Voltage Output, please connect 1uF
capacitor to DAC ground
50
ADAC_VREF
O
AUDIO
51
52
ADAC_AVDD33
VDD18
P
P
AUDIO
Core
Audio DAC Power (3.3V)
Core Logic Power (1.8V)
GPA[7]
IOU GPIOA
IU SYSTEM
GPIO Port A Bit 7
53
54
CFG[0]
Chip Power-On Configuration Bit [0], Input
I/O Power (3.3V)
VDD33
P
I/O
URTXD
OU UART
IOU GPIOA
OU SPI1
IU UART
IOU GPIOA
OU LCD
IU LCD
UART TX Data, Output
55
56
57
58
GPA[10]
SPI1_CS1_
URRXD
GPIO Port A Bit 10
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
GPA[11]
LMVSYNC
LFMARK
SPDATA[1]
GPB[6]
GPIO Port A Bit 11
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
Sensor Interface Data Bit 1, Input
GPIO Port B Bit 6
IU CAP
IOU GPIOB
IU I²S
I2S_DIN
I2S Interface Data Input
SPDATA[0]
GPB[5]
IU CAP
Sensor Interface Data Bit 0, Input
GPIO Port B Bit 5
IOU GPIOB
OU I2S
I2S_DOUT
SD1_DAT[2]
SFIELD
I2S Interface Data Output
IOU SD1
IU CAP
SD Port 1 Data Bit 2
Sensor Interface Even/ODD Field Indicator, Input
GPIO Port B Bit 4
GPB[4]
IOU GPIOB
OU I²S
59
60
I2S_WS
I2S Interface Word Select, Output
SD Port 1 Data Bit 3
SD1_DAT[3]
SVSYNC
GPB[3]
IOU SD1
IU CAP
Sensor Interface VSYNC, Input
GPIO Port B Bit 3
IOU GPIOB
Nuvoton Technology Corp.
http://www.nuvoton.com/
31
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No Name
I2S_BCLK
Type Group
IU I²S
Description
I2S Interface Clock, Input
SD Port 1 Command/Response
Sensor Interface HSYNC, Input
GPIO Port B Bit 2
SD1_CMD
SHSYNC
GPB[2]
IOU SD1
IU CAP
IOU GPIOB
OU I²S
61
62
63
I2S_MCLK
SD1_CLK
SPCLK
Clock to I2S Codec, Output
SD Port 1 Clock, Output
Sensor Interface Pixel Clock, Input
GPIO Port B Bit 1
OU SD1
IOU CAP
IOU GPIOB
IOU SD1
IOU USB
OU CAP
IOU JTAG
IOU SD1
IOU USB
IOU SPI0
IOU GPIOD
GPB[1]
SD1_DAT[0]
UHL_DM1
SCLKO
SD Port 1 Data Bit 0
USB Host 1.0 Lite Port 1, D-E154
Clock to Sensor Module, Output
GPIO Port B Bit 0
GPB[0]
SD1_DAT[1]
UHL_DP1
SPI0_CLK
GPD[12]
SD Port 1 Data Bit 1
USB Host 1.0 Lite Port 1, D+
SPI Port 0 Clock;Output in Master Mode;Input in Slave Mode
GPIO Port D Bit 12
64
Ground (0V), EPAD is for TQFP package and used for
N32903R5DN & N32905R3DN
EPAD
VSS
G
GND
Nuvoton Technology Corp.
http://www.nuvoton.com/
32
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
4.3 N3290xKxDN series Pin Description
Pin
No
Name
Type Group
Description
1
SHSYNC
GPB[2]
IU
CAP
GPIOB
I²S
Sensor Interface HSYNC, Input
GPIO Port B Bit 2
IOU
OU
I2S_MCLK
Clock to I2S Codec, Output
SD1_CLK
SPCLK
OU
SD1
SD Port 1 Clock, Output
Sensor Interface Pixel Clock, Input
GPIO Port B Bit 1
2
3
4
IOU
IOU
IOU
IOU
OU
CAP
GPIOB
SD1
GPB[1]
SD1_DAT[0]
UHL_DM1
SCLKO
SD Port 1 Data Bit 0
USB
CAP
JTAG
SD1
USB Host 1.0 Lite Port 1, D-E154
Clock to Sensor Module, Output
GPIO Port B Bit 0
GPB[0]
IOU
IOU
IOU
IOU
IOU
IU
SD1_DAT[1]
UHL_DP1
ISDA
SD Port 1 Data Bit 1
USB
I2C
USB Host 1.0 Lite Port 1, D+
I2C Interface Data
GPB[14]
LFMARK
LMVSYNC
ISCK
GPIOB
LCD
GPIO Port B Bit 14
MPU LCD Interface Frame Mark, Input
MPU LCD Interface Mode VSYNC, Output
I2C Interface Clock, Output
GPIO Port B Bit 13
OU
LCD
5
6
OU
I2C
GPB[13]
SPI0_CLK
IOU
IOU
GPIOB
SPI0
SPI Port 0 Clock;Output in Master Mode;Input in
Slave Mode
GPD[12]
IOU
IOU
GPIOD
SPI0
GPIO Port D Bit 12
7
SPI0_CS0_
SPI Port 0 Device Select 0, Low Active;Output in
Master Mode;Input in Slave Mode
GPD[13]
SPI0_DI
GPD[14]
SPI0_DO
GPD[15]
SD0_DAT[2]
GPE[4]
IOU
IU
GPIOD
SPI0
GPIO Port D Bit 13
SPI Port 0 Data Input
GPIO Port D Bit 14
SPI Port 0 Data Output
GPIO Port D Bit 15
SD Port 0 Data Bit 2
GPIO Port E Bit 4
8
IOU
OU
IOU
IOU
IOU
GPIOD
SPI0
9
GPIOD
SD0
10
GPIOE
Nuvoton Technology Corp.
http://www.nuvoton.com/
33
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
11
12
13
14
15
SD0_DAT[3]
GPE[5]
IOU
IOU
IOU
IOU
OU
IOU
IOU
IOU
IOU
IOU
I
SD0
SD Port 0 Data Bit 3
GPIO Port E Bit 5
GPIOE
SD0
SD0_CMD
GPE[6]
SD Port 0 Command/Response
GPIO Port E Bit 6
GPIOE
SD0
SD0_CLK
GPE[7]
SD Port 0 Clock, Output
GPIO Port E Bit 7
GPIOE
SD0
SD0_DAT[0]
GPE[2]
SD Port 0 Data Bit 0
GPIO Port E Bit 2
GPIOE
SD0
SD0_DAT[1]
GPE[3]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
GPIOE
XTAL
XTAL
Core
16
17
18
19
20
XIN
12MHz Crystal Input
12MHz Crystal Output
Core Logic Power (1.8V)
SDRAM I/F Ground (0V)
XOUT
O
VDD18
P
VSSQ
G
MVDD
MVDD
MVDD
P
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903K5DN or
N32905K5DN are installation
MVDD=3.3V powered when N32901K3DN is
installation
21
22
VSSQ
MVDD
G
P
MVDD
MVDD
SDRAM Ground (0V)
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903K5DN or
N32905K5DN are installation
MVDD=3.3V powered when N32901K3DN is
installation
23
24
VSS
G
--
P
GND
NC
Ground (0V)
NC
when N32901K3DN is installation
MVREF
MVDD
1/2 MVDD (0.9V) for DDR_VREF, when
N32903K5DN or N32905K5DN are installation
25
PLL_UD_VDD18
P
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
Nuvoton Technology Corp.
http://www.nuvoton.com/
34
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
26
27
28
29
30
UD_VSS
UD_DM
G
USB
USB
USB
USB
USB
USB2.0 Device Ground (0V)
USB 2.0 Device D-.
I/O
I/O
P
UD_DP
USB 2.0 Device D+.
UD_VDD33
UD_REXT
USB 2.0 Device PHY 3.3V
O
External Resistor 12.1K resistor connected to
ground
31
32
33
LVDATA[17]
SVSYNC
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 17
Sensor Interface VSYNC, Input
GPIO Port E Bit 1
CAP
GPE[1]
IOU
IOU
IU
GPIOE
LCD
LVDATA[16]
SHSYNC
SYNC/MPU LCD Interface Data Bit 16
Sensor Interface HSYNC, Input
GPIO Port E Bit 0
CAP
GPE[0]
IOU
IOU
IOU
IU
GPIOE
LCD
LVDATA[15]
GPC[15]
SYNC/MPU LCD Interface Data Bit 15
GPIO Port C Bit 15
GPIOC
CAP
SPDATA[7]
KPI_SI[7]
LVDATA[14]
GPC[14]
Sensor Interface Data Bit 7, Input
KPI Scan In Bit 7
IU
KPI
34
35
36
37
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 14
GPIO Port C Bit 14
GPIOC
CAP
SPDATA[6]
KPI_SI[6]
LVDATA[13]
GPC[13]
Sensor Interface Data Bit 6, Input
KPI Scan In Bit 6
IU
KPI
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 13
GPIO Port C Bit 13
GPIOC
CAP
SPDATA[5]
KPI_SI[5]
LVDATA[12]
GPC[12]
Sensor Interface Data Bit 5, Input
KPI Scan In Bit 5
IU
KPI
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 12
GPIO Port C Bit 12
GPIOC
CAP
SPDATA[4]
KPI_SI[4]
LVDATA[11]
GPC[11]
Sensor Interface Data Bit 4, Input
KPI Scan In Bit 4
IU
KPI
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 11
GPIO Port C Bit 11
GPIOC
CAP
SPDATA[3]
KPI_SI[3]
Sensor Interface Data Bit 3, Input
KPI Scan In Bit 3
IU
KPI
Nuvoton Technology Corp.
http://www.nuvoton.com/
35
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
38
39
40
LVDATA[10]
GPC[10]
SPDATA[2]
KPI_SI[2]
LVDATA[9]
GPC[9]
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 10
GPIO Port C Bit 10
GPIOC
CAP
Sensor Interface Data Bit 2, Input
KPI Scan In Bit 2
IU
KPI
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 9
GPIO Port C Bit 9
GPIOC
CAP
SPDATA[1]
KPI_SI[1]
LVDATA[8]
GPC[8]
Sensor Interface Data Bit 1, Input
KPI Scan In Bit 1
IU
KPI
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 8
GPIO Port C Bit 8
GPIOC
CAP
SPDATA[0]
KPI_SI[0]
LVDATA[7]
GPC[7]
Sensor Interface Data Bit 0, Input
KPI Scan In Bit 0
IU
KPI
41
42
IOU
IOU
IOU
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 7
GPIO Port C Bit 7
GPIOC
LCD
LVDATA[6]
GPC[6]
SYNC/MPU LCD Interface Data Bit 6
GPIO Port C Bit 6
GPIOC
SYSTEM
LCD
CFG[10]
Chip Power-On Configuration Bit [10], Input
SYNC/MPU LCD Interface Data Bit 5
GPIO Port C Bit 5
43
44
LVDATA[5]
GPC[5]
IOU
IOU
IU
GPIOC
SYSTEM
LCD
CFG[9]
Chip Power-On Configuration Bit [9], Input
GPIO Port C Bit 4
LVDATA[4]
GPC[4]
IOU
IOU
IU
GPIOC
SYSTEM
LCD
GPIO Port C Bit 4
CFG[8]
Chip Power-On Configuration Bit [8], Input
SYNC/MPU LCD Interface Data Bit 3
GPIO Port C Bit 3
45
46
47
48
LVDATA[3]
GPC[3]
IOU
IOU
IOU
IOU
IOU
IOU
IOU
IOU
GPIOC
LCD
LVDATA[2]
GPC[2]
SYNC/MPU LCD Interface Data Bit 2
GPIO Port C Bit 2
GPIOC
LCD
LVDATA[1]
GPC[1]
SYNC/MPU LCD Interface Data Bit 1
GPIO Port C Bit 1
GPIOC
LCD
LVDATA[0]
GPC[0]
SYNC/MPU LCD Interface Data Bit 0
GPIO Port C Bit 0
GPIOC
Nuvoton Technology Corp.
http://www.nuvoton.com/
36
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
49
LVDE
OU
LCD
SYNC LCD Interface Data Enable, Output, High
Active
LRS
OU
LCD
MPU LCD Interface Register Select
GPIO Port D Bit 11
GPD[11]
IOU
GPIOD
Note. By design limitation, GPD[11] function will
be disable when SPI1 is used.
50
LVSYNC
LRD
OU
OU
OU
LCD
LCD
LCD
SYNC LCD Interface VSYNC, Output, High Active
MPU I80 mode LCD Interface Read, active low
LEN
MPU M68 mode LCD Interface Read Write
Enable/Disable , High Enable
GPD[10]
VSS
IOU
G
GPIOD
GND
LCD
LCD Interface Data Enable, High Active.
Ground (0V)
51
52
LHSYNC
LWR
OU
OU
OU
SYNC LCD Interface HSYNC, Output, High Active
MPU I80 mode LCD Interface Write, active low
LCD
LR/W
LCD
MPU M68 mode LCD interface R/W, High is read
command and Low is write instruction
GPD[9]
IOU
GPIOD
Core
LCD
LCD
GPIOB
I/O
GPIO Port D Bit 9
53
54
VDD18
P
Core Logic Power (1.8V)
SYNC LCD Interface Pixel Clock, Output
MPU LCD Interface Chip Enable, active low
GPIO Port B Bit 15
LPCLK
OU
LCS
OU
GPB[15]
IOU
55
56
57
58
59
60
61
62
63
64
65
66
VDD33
P
G
I
I/O Power (3.3V)
ADC_VSS33
ADC_TP_YM
ADC_TP_XM
ADC_TP_XP
ADC_TP_YP
ADC_VDD33
ADC_AIN[2]
ADC_AIN[3]
ADC_AIN[4]
RTC_XOUT
RTC_XIN
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
RTC
RTC
ADC Ground (0V)
Touch Panel YM
I
Touch Panel XM
I
Touch Panel XP
I
Touch Panel YP
P
I
ADC Power (3.3V)
ADC Analog Input Channel 2
ADC Analog Input Channel 3
ADC Analog Input Channel 4
32768Hz Crystal Output
32768Hz Crystal Input
I
I
O
I
Nuvoton Technology Corp.
http://www.nuvoton.com/
37
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
67
68
69
RTC_VDD1.8V
VDD33
P
RTC
RTC Power (1.8V)
I/O Power (3.3V)
GPIO Port A Bit 6
P
I/O
GPA[6]
IOU
OU
OU
IOU
OU
OU
IOU
IOU
OU
IOU
IOU
OU
IOU
OU
IU
GPIOA
SPI1
SPI1_CS1_
KPI_SO[4]
GPA[5]
SPI Port 1 Device Select 1, Output, Low Active
KPI Scan Out Bit 4
KPI
70
71
72
73
GPIOA
SPI0
GPIO Port A Bit 5
SPI0_CS1_
KPI_SO[3]
GPA[4]
SPI Port 0 Device Select 1, Output, Low Active
KPI Scan Out Bit 3
KPI
GPIOA
USB
GPIO Port A Bit 4
UHL_DM1
KPI_SO[2]
GPA[3]
USB Host 1.0 Lite Port 1, D-
KPI Scan Out Bit 2
KPI
GPIOA
USB
GPIO Port A Bit 3
UHL_DP1
KPI_SO[1]
GPA[2]
USB Host 1.0 Lite Port 1, D+
KPI Scan Out Bit 1
KPI
GPIOA
LCD
GPIO Port A Bit 2
LMVSYNC
LFMARK
KPI_SO[0]
GPA[1]
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
KPI Scan Out Bit 0
LCD
OU
IOU
IU
KPI
74
GPIOA
SD
GPIO Port A Bit 1
SD_CD_
GPA[0]
SD Card Detect, Input, Low Active
GPIO Port A Bit 0
75
76
IOU
IU
GPIOA
SYSTEM
SYSTEM
JTAG
GPIOD
SPI1
RST_
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface Test Clock, Input
GPIO Port D Bit 0
WDT_RST_
TCK
OU
ID
77
GPD[0]
IOD
OD
OD
IU
SPI1_CS1_
PWM0
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
PWM
JTAG
GPIOD
UART
PWM
78
TMS
JTAG Interface Test Mode Select, Input
GPIO Port D Bit 1
GPD[1]
IOU
OU
OU
HUR_TXD
PWM1
High-Speed UART TX Data, Output
PWM Channel 1
Nuvoton Technology Corp.
http://www.nuvoton.com/
38
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
79
TDI
IU
JTAG
GPIOD
UART
PWM
JTAG Interface Test Data In, Input
GPIO Port D Bit 2
GPD[2]
HUR_RXD
PWM2
TDO
IOU
IU
High-Speed UART RX Data, Input
PWM Channel 2
OU
OU
IOU
IU
80
JTAG
GPIOD
UART
JTAG Interface Test Data Out, Output
GPIO Port D Bit 3
GPD[3]
HUR_CTS
High-Speed UART Clear-To-Send, Input, Low
Active
PWM3
OU
IU
PWM
PWM Channel 3
81
TRST_
JTAG
GPIOD
UART
JTAG Interface Test Reset, Input, Low Active
GPIO Port D Bit 4
GPD[4]
HUR_RTS
IOU
OU
High-Speed UART Reset-To-Send, Output, Low
Active
SPI0_CS1_
UD_CDET
VDD18
OU
I
SPI0
USB
SPI Port 0 Device Select 1, Output, Low Active
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
82
83
84
P
Core
MVDD
MVDD
P
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903K5DN or
N32905K5DN are installation
MVDD=3.3V powered when N32901K3DN is
installation
85
86
MVSS
G
P
MVDD
MVDD
SDRAM I/F Ground (0V)
MVREF
1/2 MVDD (0.9V) for DDR_VREF, when
N32903K5DN or N32905K5DN are installation
NC
--
G
P
NC
when N32901K3DN is installation
SDRAM Ground (0V)
87
88
VSSQ
MVDD
MVDD
MVDD
SDRAM Power, please follow that:
MVDD=1.8V powered when N32903K5DN or
N32905K5DN are installation
MVDD=3.3V powered when N32901K3DN is
installation
Nuvoton Technology Corp.
http://www.nuvoton.com/
39
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
89
90
91
92
93
94
95
VDD33
P
I/O
I/O Power (3.3V)
ADAC_HPVSS33
ADAC_HPVDD33
ADAC_HPOUT_L
ADAC_HPOUT_R
ADAC_AVSS33
ADAC_VREF
G
P
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
Audio DAC Headphone Driver Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio Headphone Left Channel Output
Audio Headphone Right Channel Output
Audio DAC Ground (0V)
O
O
G
O
Audio DAC Reference Voltage Output, please
connect 1uF capacitor to DAC ground
96
97
98
ADAC_AVDD33
VDD18
GPA[7]
KPI_SO[5]
ND[0]
P
AUDIO
Core
Audio DAC Power (3.3V)
P
Core Logic Power (1.8V)
IOU
OU
IOU
IU
GPIOA
KPI
GPIO Port A Bit 7
KPI Scan Out Bit 5
99
NAND
NAND Interface Data Bit [0]
CFG[0]
ND[1]
SYSTEM
NAND
Chip Power-On Configuration Bit [0], Input
NAND Interface Data Bit [1]
100
101
102
103
104
105
106
107
IOU
IU
CFG[1]
ND[2]
SYSTEM
NAND
Chip Power-On Configuration Bit [1], Input
NAND Interface Data Bit [2]
IOU
IU
CFG[2]
ND[3]
SYSTEM
NAND
Chip Power-On Configuration Bit [2], Input
NAND Interface Data Bit [3]
IOU
IU
CFG[3]
ND[4]
SYSTEM
NAND
Chip Power-On Configuration Bit [3], Input
NAND Interface Data Bit [4]
IOU
IU
CFG[4]
ND[5]
SYSTEM
NAND
Chip Power-On Configuration Bit [4], Input
NAND Interface Data Bit [5]
IOU
IU
CFG[5]
ND[6]
SYSTEM
NAND
Chip Power-On Configuration Bit [5], Input
NAND Interface Data Bit [6]
IOU
IU
CFG[6]
ND[7]
SYSTEM
NAND
Chip Power-On Configuration Bit [6], Input
NAND Interface Data Bit [7]
IOU
IU
CFG[7]
NBUSY1_
GPD[6]
SD2_DAT[2]
NBUSY0_
SYSTEM
NAND
Chip Power-On Configuration Bit [7], Input
NAND Interface Busy 1, Input, Low Active
GPIO Port D Bit 6
IU
IOU
IOU
IU
GPIOD
SD2
SD Port 2 Data Bit 2
108
NAND
NAND Interface Busy 0, Input, Low Active
Nuvoton Technology Corp.
http://www.nuvoton.com/
40
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
GPD[5]
IOU
IOU
OU
GPIOD
SD2
GPIO Port D Bit 5
SD2_DAT[3]
NWR_
SD Port 2 Data Bit 3
109
110
NAND
GPIOD
SD2
NAND Interface Write Enable, Output, Low Active
GPIO Port D Bit 8
GPD[8]
IOU
IOU
OU
SD2_CMD
NRE_
SD Port 2 Command/Response
NAND Interface Read Enable, Output, Low Active
GPIO Port D Bit 7
NAND
GPIOD
SD2
GPD[7]
IOU
OU
SD2_CLK
NCLE
SD Port 2 Clock, Output
111
112
113
OU
NAND
NAND Interface Command-Latch-Enable, Output,
High Active
GPE[11]
NALE
IOU
OU
GPIOE
NAND
GPIO Port E Bit 11
NAND Interface Address-Latch-Enable, Output,
High Active
GPE[10]
NCS1_
IOU
OU
IOU
IOU
G
GPIOE
NAND
GPIOE
SD2
GPIO Port E Bit 10
NAND Interface Chip Select 1, Output, Low Active
GPIO Port E Bit 9
GPE[9]
SD2_DAT[0]
VSS
SD Port 2 Data Bit 0
114
115
GND
Ground (0V)
NCS0_
IU
NAND
GPIOE
SD2
NAND Interface Chip Select 0, Output, Low Active
GPIO Port E Bit 8
GPE[8]
IOU
IOU
P
SD2_DAT[1]
VDD33
SD Port 2 Data Bit 1
116
117
I/O
I/O Power (3.3V)
URTXD
OU
IOU
OU
IU
UART
GPIOA
SPI1
UART TX Data, Output
GPA[10]
SPI1_CS1_
URRXD
GPIO Port A Bit 10
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
118
119
UART
GPIOA
LCD
GPA[11]
LMVSYNC
LFMARK
SPDATA[7]
GPB[12]
SPI1_DO
IOU
OU
IU
GPIO Port A Bit 11
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
Sensor Interface Data Bit 7, Input
GPIO Port B Bit 12
LCD
IU
CAP
IOU
OU
GPIOB
SPI1
SPI Port 1 Data Output
Nuvoton Technology Corp.
http://www.nuvoton.com/
41
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
LVDATA[23]
SPDATA[6]
GPB[11]
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 23
Sensor Interface Data Bit 6, Input
GPIO Port B Bit 11
120
CAP
IOU
IU
GPIOB
SPI1
LCD
SPI1_DI
SPI Port 1 Data Input
LVDATA[22]
SPDATA[5]
GPB[10]
IOU
IU
SYNC/MPU LCD Interface Data Bit 22
Sensor Interface Data Bit 5, Input
GPIO Port B Bit 10
121
CAP
IOU
IOU
GPIOB
SPI1
SPI1_CS0_
SPI Port 1 Device Select 0, Low Active;Output in
Master Mode;Input in Slave Mode
LVDATA[21]
SPDATA[4]
GPB[9]
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 21
Sensor Interface Data Bit 4, Input
GPIO Port B Bit 9
122
CAP
IOU
IOU
GPIOB
SPI1
SPI1_CLK
SPI Port 1 Clock;Output in Master Mode;Input in
Slave Mode
LVDATA[20]
SPDATA[3]
GPB[8]
IOU
IU
LCD
SYNC/MPU LCD Interface Data Bit 20
Sensor Interface Data Bit 3, Input
GPIO Port B Bit 8
123
124
125
CAP
IOU
IOU
IU
GPIOB
LCD
LVDATA[19]
SPDATA[2]
GPB[7]
SYNC/MPU LCD Interface Data Bit 19
Sensor Interface Data Bit 2, Input
GPIO Port B Bit 7
CAP
IOU
IOU
IU
GPIOB
LCD
LVDATA[18]
SPDATA[1]
GPB[6]
SYNC/MPU LCD Interface Data Bit 18
Sensor Interface Data Bit 1, Input
GPIO Port B Bit 6
CAP
IOU
IU
GPIOB
I²S
I2S_DIN
I2S Interface Data Input
126
127
SPDATA[0]
GPB[5]
IU
CAP
GPIOB
I2S
Sensor Interface Data Bit 0, Input
GPIO Port B Bit 5
IOU
OU
IOU
IU
I2S_DOUT
SD1_DAT[2]
SFIELD
I2S Interface Data Output
SD1
SD Port 1 Data Bit 2
CAP
GPIOB
I²S
Sensor Interface Even/ODD Field Indicator, Input
GPIO Port B Bit 4
GPB[4]
IOU
OU
I2S_WS
I2S Interface Word Select, Output
SD1_DAT[3]
IOU
SD1
SD Port 1 Data Bit 3
Nuvoton Technology Corp.
http://www.nuvoton.com/
42
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin
No
Name
Type Group
Description
128
SVSYNC
GPB[3]
IU
CAP
GPIOB
I²S
Sensor Interface VSYNC, Input
GPIO Port B Bit 3
IOU
IU
I2S_BCLK
I2S Interface Clock, Input
SD1_CMD
IOU
SD1
SD Port 1 Command/Response
Nuvoton Technology Corp.
http://www.nuvoton.com/
43
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
4.4 N32901R7DN TQFP64 pin list
Pin No
1
Name
SPI0_CLK
Type
Group
Description
IOU SPI0
SPI Port 0 Clock;Output in Master Mode;Input in Slave Mode
GPIO Port D Bit 12
GPD[12]
IOU GPIOD
SPI Port 0 Device Select 0, Low Active;Output in Master
Mode;Input in Slave Mode
GPIO Port D Bit 13
SPI0_CS0_
IOU SPI0
2
GPD[13]
SPI0_DI
GPD[14]
SPI0_DO
GPD[15]
XIN
IOU GPIOD
IU SPI0
SPI Port 0 Data Input
3
4
IOU GPIOD
OU SPI0
GPIO Port D Bit 14
SPI Port 0 Data Output
IOU GPIOD
GPIO Port D Bit 15
5
6
7
8
9
I
XTAL
12MHz Crystal Input
XOUT
O
P
P
P
XTAL
12MHz Crystal Output
VDD18
Core
Core Logic Power (1.8V)
MVDD33
PLL_UD_VDD18
MVDD33
SDRAM Power (3.3V)
PLL & USB PLL & USB2.0 Device Core Power (1.8V)
10 UD_DM
I/O USB
I/O USB
USB 2.0 Device D-.
11 UD_DP
USB 2.0 Device D+.
12 UD_VDD33
13 UD_REXT
P
USB
USB
USB 2.0 Device PHY 3.3V
O
External Resistor 12.1K resistor connected to ground
SYNC/MPU LCD Interface Data Bit 15
GPIO Port C Bit 15
LVDATA[15]
IOU LCD
14
GPC[15]
IOU GPIOC
IOU LCD
LVDATA[14]
SYNC/MPU LCD Interface Data Bit 14
GPIO Port C Bit 14
15
GPC[14]
IOU GPIOC
IOU LCD
LVDATA[13]
SYNC/MPU LCD Interface Data Bit 13
GPIO Port C Bit 13
16
GPC[13]
IOU GPIOC
IOU LCD
LVDATA[12]
SYNC/MPU LCD Interface Data Bit 12
GPIO Port C Bit 12
17
GPC[12]
IOU GPIOC
IOU LCD
LVDATA[11]
SYNC/MPU LCD Interface Data Bit 11
GPIO Port C Bit 11
18
GPC[11]
IOU GPIOC
IOU LCD
LVDATA[10]
SYNC/MPU LCD Interface Data Bit 10
GPIO Port C Bit 10
19
GPC[10]
IOU GPIOC
IOU LCD
LVDATA[9]
SYNC/MPU LCD Interface Data Bit 9
GPIO Port C Bit 9
20
GPC[9]
IOU GPIOC
IOU LCD
21 LVDATA[8]
SYNC/MPU LCD Interface Data Bit 8
Nuvoton Technology Corp.
http://www.nuvoton.com/
44
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No
Name
GPC[8]
Type
Group
Description
IOU GPIOC
IOU LCD
GPIO Port C Bit 8
LVDATA[7]
GPC[7]
SYNC/MPU LCD Interface Data Bit 7
GPIO Port C Bit 7
22
23
24
25
26
27
28
29
IOU GPIOC
IOU LCD
LVDATA[6]
GPC[6]
SYNC/MPU LCD Interface Data Bit 6
GPIO Port C Bit 6
IOU GPIOC
IOU LCD
LVDATA[5]
GPC[5]
SYNC/MPU LCD Interface Data Bit 5
GPIO Port C Bit 5
IOU GPIOC
IOU LCD
LVDATA[4]
GPC[4]
GPIO Port C Bit 4
IOU GPIOC
IOU LCD
GPIO Port C Bit 4
LVDATA[3]
GPC[3]
SYNC/MPU LCD Interface Data Bit 3
GPIO Port C Bit 3
IOU GPIOC
IOU LCD
LVDATA[2]
GPC[2]
SYNC/MPU LCD Interface Data Bit 2
GPIO Port C Bit 2
IOU GPIOC
IOU LCD
LVDATA[1]
GPC[1]
SYNC/MPU LCD Interface Data Bit 1
GPIO Port C Bit 1
IOU GPIOC
IOU LCD
LVDATA[0]
GPC[0]
SYNC/MPU LCD Interface Data Bit 0
GPIO Port C Bit 0
IOU GPIOC
OU LCD
LVDE
SYNC LCD Interface Data Enable, Output, High Active
MPU LCD Interafec Register Select
GPIO Port D Bit 11
30 LRS
OU LCD
GPD[11]
LVSYNC
IOU GPIOD
OU LCD
SYNC LCD Interface VSYNC, Output, High Active
MPU I80 mode LCD Interface Read, active low
LCD Interface Data Enable, High Active.
SYNC LCD Interface HSYNC, Output, High Active
MPU I80 mode LCD Interface Write, active low
GPIO Port D Bit 9
31 LRD
OU LCD
GPD[10]
LHSYNC
IOU GPIOD
OU LCD
32 LWR
OU LCD
GPD[9]
LPCLK
IOU GPIOD
OU LCD
SYNC LCD Interface Pixel Clock, Output
MPU LCD Interface Chip Enable, active low
GPIO Port B Bit 15
33 LCS
GPB[15]
OU LCD
IOU GPIOB
34 ADC_VDD33
35 RTC_VDD1.8V
36 VDD33
P
P
P
ADC
RTC
I/O
ADC Power (3.3V)
RTC Power (1.8V)
I/O Power (3.3V)
GPA[5]
37
IOU GPIOA
OU SPI0
GPIO Port A Bit 5
SPI0_CS1_
SPI Port 0 Device Select 1, Output, Low Active
Nuvoton Technology Corp.
http://www.nuvoton.com/
45
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No
38
Name
GPA[4]
Type
Group
Description
IOU GPIOA
IOU USB
GPIO Port A Bit 4
UHL_DM1
GPA[3]
USB Host 1.0 Lite Port 1, D-
GPIO Port A Bit 3
IOU GPIOA
IOU USB
39
UHL_DP1
GPA[2]
USB Host 1.0 Lite Port 1, D+
GPIO Port A Bit 2
IOU GPIOA
OU LCD
40 LMVSYNC
LFMARK
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface Test Clock, Input
GPIO Port D Bit 0
IU LCD
RST_
41
IU SYSTEM
OU SYSTEM
ID JTAG
IOD GPIOD
OD SPI1
WDT_RST_
TCK
GPD[0]
42
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
PWM0
TMS
OD PWM
IU JTAG
IOU GPIOD
OU UART
OU PWM
IU JTAG
IOU GPIOD
IU UART
OU PWM
OU JTAG
IOU GPIOD
OU PWM
IU JTAG
IOU GPIOD
OU SPI0
JTAG Interface Test Mode Select, Input
GPIO Port D Bit 1
GPD[1]
43
HUR_TXD
High-Speed UART TX Data, Output
PWM Channel 1
PWM1
TDI
JTAG Interface Test Data In, Input
GPIO Port D Bit 2
GPD[2]
44
HUR_RXD
High-Speed UART RX Data, Input
PWM Channel 2
PWM2
TDO
JTAG Interface Test Data Out, Output
GPIO Port D Bit 3
45 GPD[3]
PWM3
PWM Channel 3
TRST_
JTAG Interface Test Reset, Input, Low Active
GPIO Port D Bit 4
46 GPD[4]
SPI0_CS1_
47 UD_CDET
48 VDD18
49 MVDD33
50 VDDQ
51 AVDD33
52 VDD18
53 GPA[7]
SPI Port 0 Device Select 1, Output, Low Active
USB Device Connect Detect, Input, High Active
Core Logic Power (1.8V)
I
USB
P
P
P
P
P
Core
MVDD33
MVDD33
AUDIO
Core
SDRAM I/O Power (3.3V)
SDRAM Power (3.3V)
Audio DAC Power (3.3V)
Core Logic Power (1.8V)
IOU GPIOA
GPIO Port A Bit 7
Nuvoton Technology Corp.
http://www.nuvoton.com/
46
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Pin No
Name
CFG[0]
Type
Group
Description
OU SYSTEM
IOU GPIOD
IOU SD2
Chip Power-On Configuration Bit [0], Input
GPIO Port D Bit 6
GPD[6]
54
55
56
57
58
59
SD2_DAT[2]
GPD[5]
SD Port 2 Data Bit 2
IOU GPIOD
IOU SD2
GPIO Port D Bit 5
SD2_DAT[3]
GPD[8]
SD Port 2 Data Bit 3
IOU GPIOD
IOU SD2
GPIO Port D Bit 8
SD2_CMD
GPD[7]
SD Port 2 Command/Response
GPIO Port D Bit 7
IOU GPIOD
OU SD2
SD2_CLK
GPE[9]
SD Port 2 Clock, Output
GPIO Port E Bit 9
IOU GPIOE
IOU SD2
SD2_DAT[0]
GPE[8]
SD Port 2 Data Bit 0
IOU GPIOE
IOU SD2
GPIO Port E Bit 8
SD2_DAT[1]
SD Port 2 Data Bit 1
60 VDD33
URTXD
61 GPA[10]
SPI1_CS1_
P
I/O
I/O Power (3.3V)
OU UART
IOU GPIOA
OU SPI1
IU UART
IOU GPIOA
OU LCD
IU LCD
UART TX Data, Output
GPIO Port A Bit 10
SPI Port 1 Device Select 1, Output, Low Active
UART RX Data, Input
URRXD
GPA[11]
LMVSYNC
LFMARK
ISDA
GPIO Port A Bit 11
62
MPU LCD Interface VSYNC, Output
MPU LCD Interface Frame Mark, Input
I2C Interface Data
IOU I2C
GPB[14]
LFMARK
LMVSYNC
ISCK
IOU GPIOB
IU LCD
GPIO Port B Bit 14
63
64
MPU LCD Interface Frame Mark, Input
MPU LCD Interface Mode VSYNC, Output
I2C Interface Clock, Output
GPIO Port B Bit 13
OU LCD
OU I2C
GPB[13]
IOU GPIOB
EPAD VSS
P
GND
Ground (0V)
Nuvoton Technology Corp.
http://www.nuvoton.com/
47
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
4.5 Pin Type Description
TYPE
I
DESCRIPTION
Input
O
Output
I/O
IU
Input / Output
Input with internal pull high (50K)
Output with internal pull high (50K)
Bi-direction with internal pull high (50K)
Input with internal pull low (50K)
Output with internal pull low (50K)
Bi-direction with internal pull low (50K)
Analog Power or Digital Power
Analog GND or Digital GND
OU
IOU
ID
OD
IOD
P
G
Nuvoton Technology Corp.
http://www.nuvoton.com/
48
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5. ELECTRICAL SPECIFICATION
5.1 Absolute Maximum Rating
Parameters
Values
Ambient Temperature
-20 °C ~ 85 °C
-40 °C ~ 125 °C
-0.3V ~ 3.6V
-0.5V ~ 2.5V
-0.5V ~ 4.6V
100mA
Storage Temperature
Voltage On Any Pin
Power Supply Voltage (Core Logic)
Power Supply Voltage (I/O Buffer)
Injection Current (Latch-Up Testing)
5.2 DC Characteristics (Normal I/O)
Symbol
VDD33
VDD18
Parameter
Condition
Min.
Typ.
Max.
Unit
I/O Buffer Post-Driver Voltage
3.0
3.3
3.6
V
Core Logic and I/O Buffer Pre- CPU=200MHz
Driver Voltage
1.62
3.0
1.8
3.3
1.98
3.6
V
V
SDRAM Operation Voltage
(only for N32901x series)
DDR/DDR2 Operation Voltage
(for N32903x/N32905x series)
RTC Power Supply
MVDD33
MVDD18
1.7
1.8
1.9
V
RTC_VDD
IRTC_VDD
VIH
-
1.2
-
1.8
-
V
uA
V
RTC Supply Current
Input High Voltage
Input Low Voltage
Threshold Point
RTC_VDD<VDD18
4
-
-
2.0
-0.3
1.45
5.5
0.8
1.74
VIL
V
VT
1.58
V
Schmitt Trigger Low to High
Threshold Point
VT+
VT-
1.44
0.89
1.50
0.94
1.56
0.99
V
V
Schmitt Trigger High to Low
Threshold Point
FCPU = 200MHz,
MCLK = 100MHz,
VDD18 = 1.8V
-
160
ICC
Core Power Supply Current
-
mA
-
-
IL
Input Leakage Current
-10
-10
10
10
uA
uA
IOZ
Tri-State Output Leakage
Nuvoton Technology Corp.
http://www.nuvoton.com/
49
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Current
RPU
RPD
VOL
VOH
Pull-Up Resistor
39
40
-
65
56
-
116
108
0.4
-
k
k
V
Pull-Down Resistor
Output Low Voltage
Output High Voltage
-
2.4
V
Low Level Output
Current
4mA I/O
4mA I/O
VOL = 0.4V
VOH = 2.4V
-
-
-
-
IOL
4.0
5.9
mA
mA
High Level Output
Current
IOH
5.3 Audio DAC Characteristics
Test conditions: RL = 10K / 50pF, BW = 20Hz ~ 20KHz, Freq.= 1KHz, Sample Rate = 48KHz.
Parameter
Operating Voltage
Min
Typ
Max
Unit
V
3.0
3.3
3.6
Reference Voltage
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DAC_VDD/2
0.1
-
-
Reference Capacitor
uF
Full Scale output voltage
Full Scale output voltage
Maximum Output Power
Maximum Output Power @ 32ohm load
Maximum Output Power @ 16ohm load
L-Channel SNR
0.74
Vrms
Vpp
mW
mW
mW
dBV
dBV
dB
-
2.08
-
52
46
41
-
-
-
86
85
-64
-64
-63
-63
-62
-62
-
-
-
-
-
-
-
-
R-Channel SNR
L-Channel THD+N
R-Channel THD+N
dB
L-Channel THD+N @ 32ohm load
R-Channel THD+N @ 32ohm load
L-Channel THD+N @ 16ohm load
R-Channel THD+N @ 16ohm load
dB
dB
dB
dB
Nuvoton Technology Corp.
http://www.nuvoton.com/
50
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.4 ADC Characteristics
Parameter
Min.
Typ.
Max.
Unit
SAR ADC Input Voltage Range
Resolution of ADC
3.0
-
-
-
3.6
10
V
bit
Signal-to-Noise Plus Distortion of ADC from Line In
-
TBD
-
dB
Integral Non-Linearity of ADC
-
-
±2.0
±0.8
-
-
LSB
LSB
Differential Non-Linearity of ADC
No Missing Code
-
-
10
-
-
bit
AD Conversion Rate=ADCCLK/16
400
KHz
Nuvoton Technology Corp.
http://www.nuvoton.com/
51
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5 AC Characteristics (Digital Interface)
5.5.1 Clock Input Characteristics
TXIN
XIN
TXINWH
TXINWL
FXIN = 1 / TXIN
XINDUTY = TXINWH / ( TXINWH + TXINWL )
Symbol
FXIN
Parameter
Clock Input Frequency
Clock Input Duty Cycle
Min.
-
Typ.
12
Max.
Unit
MHz
%
-
XINDUTY
45
50
55
Nuvoton Technology Corp.
http://www.nuvoton.com/
52
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.2 SDRAM Interface
TMCLK
MCLK
TMWL
TMWH
Command Out
MCS_
MRAS_
MCAS_
MWE_
MA
TMODLY
TMOH
MBA
MDQS0
MDQS1
TMDQSH
TMDQSL
TMDSU
TMDH
Data Output
MD[15:0]
Symbol
Parameter
Min.
6
Typ.
Max.
12
Unit
ns
TMCLK
TMWL
TSWH
MCLK Clock Cycle Time
MCLK Clock Low Time
MCLK Clock High Time
-
-
-
0.45
0.45
0.55
0.55
TMCLK
TMCLK
ns
Command and Address Output
Delay Time
TMODLY
-
-
-
2
-
Command and Address Output
Hold Time
ns
TMOH
2
TMDQSH
TMDQSL
TMDSU
TMDH
MDQS0/MDQS1 High Time
MDQS0/MDQS1 Low Time
0.4
0.4
-
-
-
-
-
0.6
0.6
-
TMCLK
TMCLK
ns
MD to MDQS0/MDQS1 Setup Time
MD to MDQS0/MDQS1 Hold Time
IO reference voltage
0.6
0.6
-
ns
VREF
0.49
0.51
VDD
Nuvoton Technology Corp.
http://www.nuvoton.com/
53
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.3 Sensor/Video-In Interface
FSPCLK
TSWL
TSWH
SPCLK
TSISU
TSIH
SHSYNC
SVSYNC
SFIELD
SPDATA[7:0]
Symbol
FSPCLK
TSWL
Parameter
Min.
-
Typ.
Max.
50
Unit
MHz
ns
SPCLK Clock Frequency
SPCLK Clock Low Time
SPCLK Clock High Time
-
-
-
10
-
-
10
TSWH
ns
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Setup Time
ns
1.0
1.0
TSISU
-
-
-
-
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Hold Time
ns
TSIH
Nuvoton Technology Corp.
http://www.nuvoton.com/
54
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.4 I2S Interface
FABCLK
TAWL
TAWH
I2S_BCLK
TAISU
TAIH
Input Mode
I2S_DIN
Output Mode
I2S_WS
I2S_DOUT
TAODLY
TAOH
Symbol
Parameter
Min.
Typ.
Max.
Unit
MHz
ns
FABCLK
TAWL
TAWH
TAISU
TAIH
I2S_BCLK Clock Frequency
I2S_BCLK Clock Low Time
I2S_BCLK Clock High Time
I2S_DIN Setup Time
-
-
-
-
-
-
16
-
31.25
31.25
10
-
ns
-
ns
I2S_DIN Hold Time
10
-
ns
I2S_DOUT Output Delay
Time
ns
TAODLY
TAOH
-
-
-
0.5
-
I2S_DOUT Output Hold Time
0.1
ns
Nuvoton Technology Corp.
http://www.nuvoton.com/
55
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.5 LCD/Display Interface
SYNC Type LCD
FLPCLK
TLWL
TLWH
LPCLK
LHSYNC
LVSYNC
LVDE
LVDATA[15:0]
TLODLY
TLOH
Symbol
FLPCLK
TLWL
Parameter
LPCLK Clock Frequency
Min.
-
Typ.
Max.
Unit
MHz
ns
-
-
-
27
-
LPCLK Clock Low Time
LPCLK Clock High Time
18.5
18.5
TLWH
-
ns
LHSYNC, LVSYNC, LVDE and
LVDATA Output Delay Time
ns
TLODLY
-
-
-
1.3
-
LHSYNC, LVSYNC, LVDE and
LVDATA Output Hold Time
ns
TLOH
0.67
Nuvoton Technology Corp.
http://www.nuvoton.com/
56
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
MPU Type LCD
LPCLK (CS_)
TLAS
TLAH
LVDE (RS)
TLCSS
TLCSH
TLWR
80 Mode:
LHSYNC (WR_)
TLDODLY
TLDOH
LVDATA[15:0]
TLEN
68 Mode:
LVSYNC (EN)
Symbol
TLCSS
Parameter
Condition
Min.
Typ.
Max.
Unit
PCLK
PCLK
PCLK
PCLK
PCLK
CS_ to WR_ Setup Time
CS_ to WR_ Hold Time
RS to WR_ Setup Time
RS to WR_ Hold Time
2
1
1
1
-
-
-
-
-
-
-
-
TLCSH
TLAS
-
TLAH
-
TLDODLY
LVDATA Output Delay
Time
1
TLDOH
LVDATA
Time
Output
Hold
1
-
-
PCLK
TLWR
TLEN
WR_ Pulse Width
EN Pulse Width
80 Mode
68 Mode
1
1
-
-
-
-
PCLK
PCLK
Note: PCLK is the period of one APB bus clock.
Nuvoton Technology Corp.
http://www.nuvoton.com/
57
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.6 SPI Interface
FSPCLK
TSPWL
TSPWH
SPI0_CLK
TSPISU
TSPIH
Input Mode
SPI0_DI
Output Mode
SPI0_DO
TSPODLY
TSPOH
Symbol
Parameter
Min.
-
Typ.
Max.
Unit
MHz
ns
FSPCLK
TSPWL
TSPWH
TSPISU
TSPIH
SPI0_CLK Clock Frequency
SPI0_CLK Clock Low Time
SPI0_CLK Clock High Time
SPI0_DI Setup Time
-
-
-
-
-
-
-
25
-
20
20
10
10
-
-
ns
-
ns
SPI0_DI Hold Time
-
ns
TSPODLY
TSPOH
SPI0_DO Output Delay Time
SPI0_DO Output Hold Time
1
-
ns
0.2
ns
Nuvoton Technology Corp.
http://www.nuvoton.com/
58
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.7 NAND Interface
NCS0_
NCS1_
NALE
NCLE
TNWL
TNWH
NWR_
TNODLY
TNOH
ND[7:0]
(write)
NRE_
TNISU
TNIH
ND[7:0]
(Read)
Symbol
Parameter
Min.
10
10
-
Typ.
Max.
Unit
ns
TNWL
TNWH
TNODLY
TNOH
TNISU
TNIH
Write Pulse Low Width
NWR_ High Hold Time
-
-
-
-
-
-
-
-
ns
ND[7:0] Output Delay Time
ND[7:0] Output Hold Time
ND[7:0] Data in Setup Time
ND[7:0] Data in hold time
2.5
-
ns
10
3.2
1
ns
-
ns
-
ns
Nuvoton Technology Corp.
http://www.nuvoton.com/
59
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.5.8 SD Card Interface
FSDCLK
TSDWL
TSDWH
SDCLK
TSDISU
TSDIH
Input Mode
SDCMD,
SDDAT[3:0]
Output Mode
SDCMD,
SDDAT[3:0]
TSDODLY
TSDOH
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock SDCLK
Clock Frequency in Data
Transfer Mode
FSDCLK
-
-
-
24
MHz
KHz
Clock Frequency in
Identification Mode
FSDCLK
100
400
TSDWL
TSDWH
Clock Low Time
Clock High Time
10
10
-
-
-
-
ns
ns
Input SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDISU
TSDIH
Input Setup Time
Input Hold Time
6
2
-
-
-
-
ns
ns
Output SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDODLY
TSDOH
Output Delay Time
Output Hold Time
-
-
-
14
-
ns
ns
2.5
Nuvoton Technology Corp.
http://www.nuvoton.com/
60
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
5.6 Power-on Sequence
5.7 Thermal characteristics of LQFP-128 Package
Thermal Performance of LQFP-128 under Forced Convection
Nuvoton Technology Corp.
http://www.nuvoton.com/
61
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
6. N3290X SERIES PART SELECTION GUIDE
Mass
Production
Part No.
N32901R1DN
N32903R5DN
N32905R3DN
N32901R7DN
N32901U1DN
N32903U5DN
N32905U3DN
N32901K3DN
N32903K5DN
N32905K5DN
2
8
32
2
2
8
32
2
8
√
√
√
√
√
√
√
√
√
√
-
-
-
-
√
√
√
√
√
√
2
2
2
1
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
HS MJPEG
-
-
-
√
√
√
√
√
√
√
-
-
-
-
-
-
1
1
1
-
2
2
2
3
3
3
√
√
√
-
√
√
√
-
-
-
-
-
4
4
4
4
4
4
16
16
16
-
16
16
16
16
16
16
-
-
-
-
-
-
-
-
-
-
1
1
1
-
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
-
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
-
-
-
-
√
√
√
√
√
√
2
2
2
4
4
4
4
4
4
4
√
√
√
-
√
√
√
√
√
√
34
LQFP64
√
√
√
√
√
√
√
√
√
√
34 TQFP64-EP
34 TQFP64-EP
44 TQFP64-EP
64 LQFP128
64 LQFP128
64 LQFP128
70 LQFP128
70 LQFP128
70 LQFP128
16 QVGA
18 QVGA
18
18
24
24
24
VGA
VGA
VGA
VGA
VGA
-
-
32
Nuvoton Technology Corp.
http://www.nuvoton.com/
62
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
6.1
Part Number Definition
Nuvoton Technology Corp.
http://www.nuvoton.com/
63
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
7. PACKAGE OUTLINE
7.1 LQFP-128 (14X14X1.4mm body, 0.4mm pitch)
Nuvoton Technology Corp.
http://www.nuvoton.com/
64
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
7.2 LQFP-64 (10X10X1.4mm body, 0.5mm pitch)
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.063
Max
1.60
A
1
A
2
A
b
c
0.002
0.05
0.15
1.45
0.27
0.20
0.006
0.053 0.055 0.057 1.35
1.40
0.20
0.007
0.004
0.17
0.09
0.008 0.011
0.008
10.00
10.00
0.50
0.393
D
E
e
0.393
0.020
D
H
HE
L
L
y
12.00
12.00
0.60
0.472
0.472
0.030
7
0.024
0.039
0.75
7
0.45
0
0.018
0
1.00
1
0.10
3.5
0.004
3.5
0
Nuvoton Technology Corp.
http://www.nuvoton.com/
65
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
7.3 TQFP-64 (10X10X1.0mm body, 0.5mm pitch)
Nuvoton Technology Corp.
http://www.nuvoton.com/
66
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Nuvoton Technology Corp.
http://www.nuvoton.com/
67
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
UNIT: mm
Nuvoton Technology Corp.
http://www.nuvoton.com/
68
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
8. REVISION HISTORY
VERSION
DATE
DESCRIPTION
A0
A1
Jul. 25, 2012
Aug. 1, 2012
Initial release.
Add stacked DRAM size into order Information
Add N32901U1DN Information
Correct the N32905U2DN Pin Diagram
Extend Operation Temperature Range
Add Parts Feature Difference Table
Add Part Number Definition
A2
Aug. 30, 2012
A3
Oct. 15, 2012
Oct. 26, 2012
A3.1
Add CCIR Still Image and Video Recommanded Resolutions.
Add LCD Display for Still Image and Video Recommanded Resolutions.
Modify One SPI H/W Engine to Support Two SPI Devices by Two Chip
Selection Signals when SPI0 is in Master Mode. For LQFP128 package, only
SPI0 is active.
A3.2
Nov. 8, 2012
Add USB 1.1 Host One H/W Controller, Three Different Pin Locations Information.
Remove Adobe Flash Feature from Comparision Table.
Update the AC characteristics.
A3.3
A3.4
A4.0
Nov. 10, 2012
Jan. 21, 2013
Mar. 15, 2013
Add N32903R1DN
Add N32901R1DN Information.
A5.0
May 1, 2013
Add N32901U2DN Information.
A5.1
A5.2
A5.3
May 3, 2013
Mar. 17, 2014
Aug. 13, 2014
Add SDRAM and DDR Operation Voltage Spec
Add N32905U3DN
Revise Audio DAC Characteristics of Full Scale output voltage
Add N32903U2DN to pin diagram
A5.4
Sept. 10, 2014
Add N32903U2DN, N32901R1DN & N32901U2DN to Ordering Information
Comparison table for N3290x series
Add N32905R3DN
A5.5
A5.6
Oct. 23, 2014
Dec. 15, 2015
Removed VPOST supports LCD VSYNC/MPU-24bit BUS
Revised pin desciprion.
Add N32905U4DN to pin diagram
A5.7
May 17, 2016
Add N32905U4DN to ordering information
Add the notice with chip F version
Add MPU LCD pin description
A5.8
Jul. 29, 2016
Revised DRAM operating voltage 3.3V/1.8V description
Updated N32903U2DN part number to pin description.
Add part no. N3290xKxDN series
A5.9
A6.0
A6.1
A6.2
Sept. 30, 2016
Mar. 26, 2018
May 18, 2018
Oct. 10, 2018
Add part no. N32901R7DN
N3290x series part no. selection updated in Q4, 2018
Nuvoton Technology Corp.
http://www.nuvoton.com/
69
Release Date: Oct., 2018
Rev. A6.2
N3290X DATASHEET
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Nuvoton Technology Corp.
http://www.nuvoton.com/
70
Release Date: Oct., 2018
Rev. A6.2
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明