N32912R7DN [NUVOTON]
ARM926EJ-S Based Media Processor with Video Decode Accelerator;
| 型号： | N32912R7DN |
| 厂家： | 
NUVOTON |
| 描述： | ARM926EJ-S Based Media Processor with Video Decode Accelerator |
| 文件： | 总34页 (文件大小：1872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N3291xUxDN
Data Sheet
ARM926EJ-S Based Media Processor with
Video Decode Accelerator
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 1 -
N3291xUxDN Data Sheet
The information in this document is subject to change without notice.
The Nuvoton Technology Corp. shall not be liable for technical or editorial errors or omissions
contained herein; nor for incidental or consequential damages resulting from the furnishing,
performance, or use of this material.
This documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or
reduced to any electronic medium or machine readable form without prior consent, in writing, from the
Nuvoton Technology Corp.
Nuvoton Technology Corp. All rights reserved.
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 2 -
N3291xUxDN Data Sheet
Table of Contents
1. GENERAL DESCRIPTION ...................................................................................................4
1.1 Applications .......................................................................................................................4
2. FEATURES...........................................................................................................................5
3. PIN DIAGRAM ....................................................................................................................12
3.1 N3291xUxDN (LQFP-128)...............................................................................................12
4. PIN DESCRIPTION.............................................................................................................13
4.1 Pin Description ................................................................................................................13
4.2 Pin Type Description........................................................................................................26
5. ELECTRICAL SPECIFICATION .........................................................................................27
5.1 Absolute Maximum Rating...............................................................................................27
5.2 DC Characteristics (Normal I/O)......................................................................................27
5.3 Audio DAC Characteristics ..............................................................................................29
5.4 ADC Characteristics ........................................................................................................30
5.5 AC Characteristics (Digital Interface)...............................................................................30
5.6 Thermal characteristics of SLQFP-128 Package.............................................................31
6. ORDERING INFORMATION...............................................................................................32
6.1 Part Number Definition ....................................................................................................32
6.2 Difference between N3291xU1DN and N32916xU2DN...................................................32
7. PACKAGE OUTLINE..........................................................................................................33
7.1 128L LQFP (14X14X1.4mm body, 0.4mm pitch).............................................................33
8. REVISION HISTORY ..........................................................................................................34
Nuvoton Technology Corp.
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Release Date: Jun. 2013
Revision A3
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N3291xUxDN Data Sheet
1. GENERAL DESCRIPTION
The N3291xUxDN is specially designed for accelerating video stream decoding performance while off-loading the
CPU to save power consumption. It is embedded H/W video decoder to deliver high-quality video playback in different
formats, like H.264 / MPEG-4 / H.263.
The N3291xUxDN is built on the ARM926EJ-S CPU core and integrated with video encoder, JPEG codec, CMOS
image sensor interface, Sound Processing Unit (SPU), ADC, DAC, and TV encoder for meeting various kinds of
application needs while saving the BOM cost. The combination of ARM926 @ 300MHz, DDR2, H/W video decoder,
and USB2.0 HS Device makes the N3291xU1DN the best choice for high performance media processing devices.
The N3291xU1DN also integrates an AES cipher/de-cipher cryptography engine for stream protection considerations.
The stream stored in SD card, SPI NOR Flash, or NAND Flash is encrypted. It is decrypted when the stream is read
back and decrypted for playback.
The N32916UxDN is ported with Linux OS to leverage the driver availability of emerging functionalities, like Wi-Fi
connectivity. On the other hand, the open source code environment also gives the product development more
flexibility. Moreover, hybrid platform is introduced to best utilize the performance advantage at native C programming
while enjoying the inherent benefit at application firmware/software development.
Maximum resolution for the N3291xUxDN is D1 (720x480) @ TV output and 1,024x768 @ TFT LCD panel. With
increasing popularity of the application image resolution, the N3291xUxDN is the best fit for the application that
requires fast turn-around time of development. The N3291xUxDN is well-positioned in the cost effective & high
performance media player market where video streams are extensively used.
To reduce system complexity while cutting the BOM cost, the N3291xUxDN is particularly designed with the 128-pin
SLQFP MCP (Multi-Chip Package). For N3291xUxDN, the 32Mbitx16 DDR2 chip is stacked inside the MCP to ensure
higher performance, lower power consumption and to minimize the system design efforts, like EMI and noise coupling.
The N3291xUxDN is incorporated with a reliable Linux OS kernel and Board Support Package (BSP) to help
customers shorten the design cycle time. The fast booting time (under 3 seconds), from power on to application
running, is another extra feature to help eliminate power consumption.
1.1 Applications
e-Reader for kids
ELA (Educational Learning Aid)
TV game
HMI
Home Applicance
Advertisement
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Release Date: Jun. 2013
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N3291xUxDN Data Sheet
2. FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 16KB I-Cache & 16KB D-Cache.
Frequency up to 300MHz (worse case).
JTAG interface supported for development and debugging.
Internal SRAM & ROM
8KB internal SRAM and 16KB IBR (Internal Booting ROM) supported.
IBR booting messages displayed by UART console for debugging.
Different system booting modes supported:
Memory card
SD card
SD-to-NAND flash bridge
NAND Interface
Raw NAND Flash
OTP ROM (N23512T / N231GT)
SPI Flash
USB
Memory Controller
SDRAM Interface
SDR, DDR, LPDDR & DDR2 type SDRAM supported.
Frequency up to 150MHz.
16-bit data bus width supported.
2 external SDRAM banks (2 chip select pins) supported.
Total memory size up to 256MB (128MB x 2).
EDMA (Enhanced DMA)
Totally 6 DMA channels supported
4 peripheral DMA channels for transfer between memory and on-chip peripherals,
such as ADC, UART and SPI.
Two dedicated channels for memory-to-memory transfer.
Byte, half-word and word data width types supported.
Single and burst transfer modes supported.
Block transfer supported in memory-to-memory transfer channel.
Color format transformation supported in memory-to-memory transfer channel.
Source color format could be RGB555, RGB565 and YCbCr422.
Destination color format could be RGB555, RGB565 and YCbCr422.
Auto reload supported for continuous data transfer.
Interrupt generation supported in the half-of-transfer or end-of-transfer.
Capture (CMOS Image Sensor I/F)
CCIR601 and CCIR656 interfaces supported for connection to CMOS image sensor.
Resolution up to 2M pixels.
YUV422 and RGB565 color format supported for data-in from CMOS sensor.
YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system
memory.
Planar and packet data formats supported for data storing to system memory.
Image cropping supported with the cropping window up to 4096x2048.
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Release Date: Jun. 2013
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N3291xUxDN Data Sheet
Image scaling-down supported.
Vertical and horizontal scaling-down for preview mode supported.
The scaling factor is N/M.
Two pairs of configurable 8-bit N and 8-bit M for vertical and horizontal scaling-
down.
The value of N has to equal to or less than M.
Frame rate control supported.
Combines two interlace fields to a single frame supported for data in from TV-decoder
3 Kinds of color processing effects:
Negative picture
Sepia picture
Posterization
JPEG Codec
Baseline Sequential mode JPEG codec function compliant with ISO/IEC 10918-1
international JPEG standard supported.
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format
image.
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)
format image.
Support to decode YCbCr 4:2:2 transpose format.
Support arbitrary width and height image encode and decode.
Support three programmable quantization-tables.
Support standard default Huffman-table and programmable Huffman-table for decode.
Support arbitrarily 1X~8X image up-scaling function for encode mode.
Support down-scaling function for encode and decode modes.
Support specified window decode mode.
Support quantization-table adjustment for bit-rate and quality control in encode
mode.
Support rotate function in encode mode.
Support on-the-Fly interface with video data processor.
Packet Format
Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and
4:2:0 format.
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image.
Support decoded output image RGB555, RGB565 and RGB888 formats.
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards.
Support arbitrary width and height image encode and decode.
Support three programmable quantization-tables.
Support standard default Huffman-table and programmable Huffman-table for decode.
Support arbitrarily 1X~8X image up-scaling function for encode mode.
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for
decode mode.
Support specified window decode mode.
Support quantization-table adjustment for bit-rate and quality control in encode
mode.
Support on-the-Fly interface with video data processor.
Support Scatter-Gather mode for output frame buffer.
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Release Date: Jun. 2013
Revision A3
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N3291xUxDN Data Sheet
Video Decoder
Support H.264 AVC baseline profile level-3 and compliant with ISO/IEC 14496-10 visual
standard, SVGA (800x600) @ 30fps.
Support MPEG-4 part-II simple profile level-3 decoder and compliant with ISO/IEC 14496-
2 visual standard, SVGA (800x600) @ 30fps.
Support H.263 P3 decoder, SVGA (800x600) @ 30fps.
Support Sorenson Spark decoder, D1 (720x480) @ 30fps.
Support real-time 30fps video decompression and resolution can up to 720×480.
Error resilience: Slice Resynchronization, Data Partitioning and Reversible VLC.
VPOST
8/16/18/24-bit SYNC type and 8/9/16/18/24-bit MPU type TFT LCD supported.
Color format supported:
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data in.
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data out.
XGA (1024x768), SVGA (800x600), WVGA (800x480), D1 (720X480), VGA (640x480),
WQVGA (480x272), QVGA (320x240) and HVGA (320x480) resolution supported.
The maximum resolution is up to D1 (720X480) for TV output.
The maximum resolution is up to 1024X768 for TFT LCD panel.
Display scaler – to fit different size of LCD panels.
Horizontal: At most 4.0x scale.
Vertical: At most 3.0x scale.
For SYNC type LCD:
For 8-bit bus
CCIR601 YCbCr422 packet mode (NTSC/PAL) supported.
CCIR601 RGB Dummy mode (NTSC/PAL) supported.
CCIR656 interface supported.
RGB Through mode supported.
For 16/18/24-bit bus
Parallel pixel data output mode (1-pixel/1-clock).
NTSC/PAL interlace & non-interlace output supported.
Color format transform supported:
Color format transform between YCbCr422 and RGB565.
Color format transform from YCbCr422 to RGB888.
TV encoder supported.
Dual screen, outputs to TV and LCDwith same content, supported.
LCD panel should be 320X240 MPU-type, or 8-bit SYNC-type LCD panel with TV
timing
Notch filter for NTSC supported to remove the rainbow color effect.
Support OSD function to overlap system information like battery life, brightness tuning,
volume tuning or muting, etc.
SPU (Sound Processing Unit)
7-bit volume control supported.
5-bit pan control supported.
10-band equalizer supported.
13-bit DFA supported for source sampling rate control.
Audio DAC
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Release Date: Jun. 2013
Revision A3
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N3291xUxDN Data Sheet
16-bit stereo DAC supported with headphone driver output.
H/W volume control supported.
Built-in PLL for supporting various sampling rate.
I2S Controller
I2S interface supported to connect external audio codec.
16/18/20/24-bit data format supported.
Storage Interface Controller
Interface to NAND Flash:
8-bit data bus width supported.
SLC and MLC type NAND Flash supported.
512B, 2KB, 4KB, and 8KB page size NAND Flash supported.
ECC4, ECC8, ECC12, ECC15 and ECC24 algorithm supported for ECC generation,
error detection and error correction.
Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported.
SD-to-NAND flash bridge supported.
DMA function supported to accelerate the data transfer between system memory and
NAND Flash or SD/MMC/SDIO/SDHC/micro-SD.
USB Device Controller
USB2.0 HS (High-Speed) x 1 port.
6 configurable endpoints supported.
Control, Bulk, Interrupt and Isochronous transfers supported.
Suspend and remote wakeup supported.
USB Host Controller
USB1.1 Host x 2 ports.
Fully compliant with USB Revision 1.1 specification.
Open Host Controller Interface (OHCI) Revision 1.0 compatible.
Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported.
Control, Bulk, Interrupt and Isochronous transfers supported.
Timer & Watch-Dog Timer
Two 32-bit with 8-bit pre-scalar timers supported.
One programmable 24-bit Watch-Dog Timer supported.
PWM
4 PWM channel outputs supported.
16-bit counter supported for each PWM channel.
Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels.
Two clock-dividers supported and each divider shared by two PWM channels.
Two Dead-Zone generators supported and each generator shared by two PWM channels.
Auto reloaded mode and one-shot pulse mode supported.
Capture function supported.
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Release Date: Jun. 2013
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N3291xUxDN Data Sheet
UART
A high speed UART supported:
Baud rate is up to 1M bps.
4 signals TX, RX, CTS and RTS supported.
A normal UART supported:
Baud rate is up to 115.2K bps.
2 signals TX and RX supported only.
SPI
Two SPI interfaces are supported.
Both master and slave mode are supported in SPI interface 0.
Only master mode is supported in SPI interface 1.
Byte transfer with configurable stop interval supported.
I2C
One I2C channel supported.
Compatible with Philips’s I2C standard and only master mode supported.
Multi-master operation supported.
Advanced Interrupt Controller
Total 32 interrupt source supported.
Configurable interrupt type:
Low-active level triggered interrupt.
High-active level triggered interrupt.
Low-active edge (falling edge) triggered interrupt.
High-active edge (rising edge) triggered interrupt.
Individual interrupt mask bit for each interrupt source.
8 different priority levels supported.
Daisy-chain priority mechanism supported for interrupts with same priority level.
Low priority interrupt automatic masking supported for interrupt nesting.
RTC
Independent power plane supported
Dual clock source are supported, accurate 32.768 KHz crystal oscillation circuit and built-
in coarse 32KHz RC-oscillator.
Time counter (second, minute, hour) and Calendar counter (day, month, year) supported.
Alarm supported (second, minute, hour, day, month and year).
12/24-hour mode and Leap year supported.
Alarm to wake chip up from Standby mode or from Power-down mode supported.
Wake chip up from Power-down mode by input pin supported.
Power-off chip by register setting supported.
Power-on timeout is supported for low battery protection.
GPIO
88 programmable general purpose I/Os supported and separated into 5 groups.
Individual configuration supported for each I/O signal.
Configurable interrupt control functions supported.
Configurable de-bounce circuit supported for interrupt function.
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Release Date: Jun. 2013
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N3291xUxDN Data Sheet
General-purpose ADC
Multi-channel, 10-bit ADC supported
2 channels dedicated for 4-wire resistive touch sensor inputs.
3 channels reserved for various purposes, like LVD (Low Voltage Detection), keypad
input, and light sensor.
Input voltage range from 0V ~ 3.3V supported.
Maximum 25MHz input clock supported.
Maximum 150K/s conversion rate supported.
LVR (Low Voltage Reset) supported.
Microphone ADC
Built-in Programmable Gain Control (PGC) circuit
Built-in Bias circuit
10-bit ADC supported
Keypad Interface (KPI)
Matrix Key Pad Interface Supported.
Maximum 8x8 and minimum 3x3 keypad matrix supported.
Configurable key de-bounce supported.
Low power wakeup mode supported.
Configurable three-key reset supported.
AES (Advance Encryption Standard) Engine
Support both encryption and decryption.
Support only CBC (Cipher Block Chaining) mode.
All three kinds of key length: 128, 192, 256 bits are supported.
Built-in DMA supported.
Power Management
Advanced power management including Power Down, Deep Standby, CPU Standby, and
Normal Operating modes.
Normal Operating Mode
Core power is 1.2V and chip is in normal operation.
CPU Standby Mode
Core power is 1.2V and only ARM CPU clock is turned OFF.
Deep Standby Mode
Core power is 1.2V and all IP clocks are turned OFF.
Power Down Mode
Only the RTC power is ON. Other 3.3V and 1.2V power are OFF.
Software Support
Development Tools
Bootloader / Diagnostic Program / NAND Writer Program: ADS 1.2 or RVDS 2.x or 3.x
Linux Kernel (2.6.17.14) / System Manager: GCC 4.2
TurboWriter / Sync Tool: Microsoft VC 6.0
NAND Flash File System
FAT12, FAT16 and FAT32 with long filename are supported.
Hidden disk is supported.
RAM disk is supported.
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N3291xUxDN Data Sheet
S/W audio Library
Decoders with ADPCM / MP3 / ACC / OGG / WMA format support.
32-polyphony Wavetable MIDI synthesizer.
Programmable sampling rate and target bit rate.
USB Driver
MS (Mass Storage) Class
HID (Human Interface Device) Class
Fast Booting Time (From power-on to application running)
Within 3 seconds
Operating Voltage
I/O: 3.3V
Core: 1.2V for 300MHz.
Package
LQFP-128 (MCP, stacked with 32Mbx16 DDR2 @ 1.8V)
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Release Date: Jun. 2013
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N3291xUxDN Data Sheet
3. PIN DIAGRAM
3.1 N3291xUxDN (LQFP-128)
1
9
P
F
1
ADAC_HPVDD33
ADAC_HPOUT_L
ADAC_HPOUT_R
ADAC_VSS33
GPD[12] / SPI0_CLK
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
N
2
GPE[6] /
GPE[7] /
SDCMD
SDCLK
Q
L
ADAC_VMID
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
ADAC_AVDD33
TVDAC_AVDD33
N
3
90
80
70
GPB[12] /LVDATA[23]
GPB[11] /LVDATA[22]
/ SPI1_DO/
/ SPI1_CLK / GPG[2] / ISCK
SPDATA[7]
TVDAC_TVOUT / I2S_DOUT
TVDAC_COMP / I2S_WS
/ SPI1_DI/ SPDATA[6]
D
x
/ GPG[4]
/ GPG[5]
/ GPG[3]
/ SPI1_DI
/ ISDA
VDD12
MVDDQ18
MVDDQ18
VDD12
10
TVDAC_VREF
TVDAC_REXT
/ I2S_MCLK / SPI1_DO
/ I2S_BCLK
/ SPI1_CS0_
/ GPH[5]
/ LVD_OUT
DIVIDER_FB
MVDD18
MVDD18
VDD12
8
U
x
SPDATA[5]
GPB[10] /LVDATA[21]/SPI1_CS0_/
GPB[9] /LVDATA[20] / SPI1_CLK/
GPB[8] /LVDATA[19] /
SPDATA[4]
SPDATA[3]
SPDATA[2]
SPDATA[1]
SPDATA[0]
2
-
RTC_XOUT
RTC_XIN
/ GPG[1]
/ GPG[0]
GPB[7] /LVDATA[18] /
/ I2S_DIN/
/I2S_DOUT/
GPB[6]
RTC_RWAKE_
1
GPB[5] / SDDAT1[2]
GPB[4] / SDDAT1[3]
GPB[3] / SDCMD1
RTC_RPWR
RTC_VDD33
ADC_VDD33
20
/
I2S_WS/
/ I2S_BCLK/
/ I2S_MCLK/
SFIELD
SVSYNC
SHSYNC
SPCLK
/ SDCLK1
GPB[2]
ADC_VSS33
GPB[1] / SDDAT1[0] / UHL_DM1 /
GPB[0] / SDDAT1[1] / UHL_DP1 /
ADC_AIN[3]
ADC_AIN[2]
ADC_TP_YP / ISCK
ADC_TP_XP
/ GPG[7]
/ GPG[8]
SCLKO
XIN
/ GPG[12]
/ SPI1_CLK
/ SPI1_CS0_
XOUT
/ GPG[13]
VDD33
/ SPI1_DI
/ GPG[14]
/ GPG[15]
ADC_TP_XM
/ ISDA / SPI1_DO
UD_VDD12
UD_DM
UD_DP
ADC_TP_YM
/ GPG[11]
MIC_BIAS
/ I2S_BCLK
/ MIC_N
/ MIC_P
/ I2S_DI
/ GPG[9]
ADC_AIN[1]
ADC_AIN[0]
30
/ GPG[10]
/ I2S_WS
/ I2S_MCLK
UD_VDD33
UD_REXT
/ GPH[0]
PGC_VREF
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N3291xUxDN Data Sheet
4. PIN DESCRIPTION
4.1 Pin Description
I/O
PIN NAME
DESCRIPTION
TYPE
Clock & Reset
XIN
I
27MHz/12MHz Crystal Input
27MHz/12MHz Crystal Output
XOUT
RST_
O
IOSU System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
JTAG Interface
TCK
IOD
IOU
JTAG Interface Test Clock, Input
SPI1_CS1_
PWM0
SPI Port 1 Device Select 1, Output, Low Active
PWM Channel 0
GPD[0]
TMS
GPIO Port D Bit 0
JTAG Interface Test Mode Select, Input
High-Speed UART TX Data, Output
PWM Channel 1
HUR_TXD
PWM1
S2PCLK
GPD[1]
TDI
CMOS Camera Module Port 2 PCLK Signal
GPIO Port D Bit 1
IOU
JTAG Interface Test Data In, Input
High-Speed UART RX Data, Input
PWM Channel 2
HUR_RXD
PWM2
S2CLKO
GPD[2]
TDO
CMOS Camera Module Port 2 MCLK Signal
GPIO Port D Bit 2
IOU
JTAG Interface Test Data Out, Output
High-Speed UART Clear-To-Send, Input, Low Active
PWM Channel 3
HUR_CTS
PWM3
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N3291xUxDN Data Sheet
I/O
PIN NAME
LVD_OUT
DESCRIPTION
TYPE
Low Voltage Dection Indicator
S2VSYNC
UHL_DP0
GPD[3]
The 2nd CMOS Camera Module VSYNC Signal
USB 1.1 Host Like Port 0 D+ Signal
GPIO Port D Bit 3
TRST_
IOU
JTAG Interface Test Reset, Input, Low Active
High-Speed UART Reset-To-Send, Output, Low Active
SPI Port 0 Device Select 1, Output, Low Active
USB 1.1 Host like Port 0 D- Signal
HUR_RTS
SPI0_CS1_
UHL_DM0
S2HSYNC
GPD[4]
The 2nd CMOS Camera Module HSYNC Signal
GPIO Port D Bit 4
NAND Interface
NCS0_
IOU
IOU
IOU
NAND Interface Chip Select 0, Output, Low Active
GPIO Port E Bit 8
GPE[8]
NCS1_
NAND Interface Chip Select 1, Output, Low Active
GPIO Port E Bit 9
GPE[9]
NALE
NAND Interface Address-Latch-Enable, Output, High Active
SDDAT2[0]
GPE[10]
NCLE
SD Port 2 Data Bit 0
GPIO Port E Bit 10
IOU
IOU
NAND Interface Command-Latch-Enable, Output, High Active
SD Port 2 Data Bit 1
SDDAT2[1]
GPE[11]
NBUSY0_
SDDAT2[2]
GPD[5]
GPIO Port E Bit 11
NAND Interface Busy 0, Input, Low Active
SD Port 2 Data Bit 2
GPIO Port D Bit 5
NBUSY1_
GPD[6]
IOU
IOU
NAND Interface Busy 1, Input, Low Active
GPIO Port D Bit 6
NRE_
NAND Interface Read Enable, Output, Low Active
SD Port 2 Clock, Output
SDCLK2
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N3291xUxDN Data Sheet
I/O
PIN NAME
GPD[7]
NWR_
DESCRIPTION
TYPE
GPIO Port D Bit 7
IOU
IOU
IOU
IOU
NAND Interface Write Enable, Output, Low Active
SD Port 2 Command/Response
GPIO Port D Bit 8
SDCMD2
GPD[8]
ND[7]
NAND Interface Data Bit 7
SPI Port 0 CS0, Active Low
GPIO Port A Bit 15
SPI0_CS0_
GPA[15]
ND[6]
NAND Interface Data Bit 6
SPI Port 0 Serial Clock Signal
GPIO Port A Bit 14
SPI0_CLK
GPA[14]
ND[5]
NAND Interface Data Bit 5
SPI Port 0 Serial Data Input
USB 1.1 Host Like Port 0 D- Signal
GPIO Port A Bit 13
SPI0_DI
UHL_DM0
GPA[13]
ND[4]
IOU
IOU
NAND Interface Data Bit 4
SPI Port 0 Serial Data Output
USB 1.1 Host Like Port 0 D+ Signal
GPIO Port A Bit 12
SPI0_DO
UHL_DP0
GPA[12]
ND[3]
SDDAT2[3]
NAND Interface Data Bit 3
SD Port 3 Data Bit 3
ND[2]
IOU
IOU
IOU
NAND Interface Data Bit 2
NAND Interface Data Bit 1
NAND Interface Data Bit 0
ND[1]
ND[0]
Sensor/Video-In Interface
SCLKO
IOU
Clock to Sensor Module, Output
USB Host Like Interface, DP
SD Port 1 Data Bit 1
UHL_DP1
SDDAT1[1]
GPB[0]
GPIO Port B Bit 0
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N3291xUxDN Data Sheet
I/O
TYPE
IOU
PIN NAME
DESCRIPTION
Sensor Interface Pixel Clock, Input
SPCLK
UHL_DM1
USB Host Like Interface, DM
SD Port 1 Data Bit 0
SDDAT1[0]
GPB[1]
GPIO Port B Bit 1
SHSYNC
I2S_MCLK
SDCLK1
IOU
IOU
IOU
IOU
Sensor Interface HSYNC, Input
Clock to I2S Codec, Output
SD Port 1 Clock, Output
GPIO Port B Bit 2
GPB[2]
SVSYNC
I2S_BCLK
SDCMD1
GPB[3]
Sensor Interface VSYNC, Input
I2S Interface Clock, Input
SD Port 1 Command/Response
GPIO Port B Bit 3
SFIELD
Sensor Interface Even/ODD Field Indicator, Input
I2S Interface Word Select, Output
SD Port 1 Data Bit 3
I2S_WS
SDDAT1[3]
GPB[4]
GPIO Port B Bit 4
SPDATA[0]
I2S_DOUT
SDDAT1[2]
GPB[5]
Sensor Interface Data Bit 0, Input
I2S Interface Data Output
SD Port 1 Data Bit 2
GPIO Port B Bit 5
SPDATA[1]
I2S_DIN
IOU
IOU
IOU
Sensor Interface Data Bit 1, Input
I2S Interface Data Input
GPB[6]
GPIO Port B Bit 6
SPDATA[2]
LVDATA[18]
GPB[7]
Sensor Interface Data Bit 2, Input
LCD Interface Data Bit 18
GPIO Port B Bit 7
SPDATA[3]
LVDATA[19]
Sensor Interface Data Bit 3, Input
LCD Interface Data Bit 19
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 16 -
N3291xUxDN Data Sheet
I/O
PIN NAME
GPB[8]
DESCRIPTION
TYPE
GPIO Port B Bit 8
SPDATA[4]
SPI1_CLK
IOU
Sensor Interface Data Bit 4, Input
SPI Port 1 Clock
Output in Master Mode
Input in Slave Mode
LVDATA[20]
GPB[9]
LCD Interface Data Bit 20
GPIO Port B Bit 9
SPDATA[5]
SPI1_CS0_
IOU
Sensor Interface Data Bit 5, Input
SPI Port 1 Select 0, Low Active
Output in Master Mode
Input in Slave Mode
LVDATA[21]
GPB[10]
LCD Interface Data Bit 21
GPIO Port B Bit 10
SPDATA[6]
SPI1_DI
IOU
IOU
Sensor Interface Data Bit 6, Input
SPI Port 1 Data Input
LVDATA[22]
GPB[11]
LCD Interface Data Bit 22
GPIO Port B Bit 11
SPDATA[7]
SPI1_DO
LVDATA[23]
GPB[12]
Sensor Interface Data Bit 7, Input
SPI Port 1 Data Output
LCD Interface Data Bit 23
GPIO Port B Bit 12
I2C Interface
ISCK
IOU
IOU
I2C Interface Clock, Output
GPIO Port B Bit 13
GPB[13]
ISDA
I2C Interface Data
LMVSYNC
GPB[14]
MPU Mode VSYNC, Output
GPIO Port B Bit 14
LCD/Display Interface
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 17 -
N3291xUxDN Data Sheet
I/O
TYPE
IOU
PIN NAME
DESCRIPTION
LCD Interface Pixel Clock, Output
LPCLK
GPB[15]
GPIO Port B Bit 15
LHSYNC
GPD[9]
IOU
IOU
IOU
IOU
LCD Interface HSYNC, Output, High Active
GPIO Port D Bit 9
LVSYNC
GPD[10]
LVDE
LCD Interface VSYNC, Output, High Active
GPIO Port D Bit 10
LCD Interface Data Enable, Output, High Active
GPIO Port D Bit 11
GPD[11]
LVDATA[0]
KPI_SO[0]
GPC[0]
LCD Interface Data Bit 0
KPI Scan Out Bit 0
GPIO Port C Bit 0
LVDATA[1]
KPI_SO[1]
GPC[1]
IOU
IOU
IOU
IOU
IOU
IOU
LCD Interface Data Bit 1
KPI Scan Out Bit 1
GPIO Port C Bit 1
LVDATA[2]
KPI_SO[2]
GPC[2]
LCD Interface Data Bit 2
KPI Scan Out Bit 2
GPIO Port C Bit 2
LVDATA[3]
KPI_SO[3]
GPC[3]
LCD Interface Data Bit 3
KPI Scan Out Bit 3
GPIO Port C Bit 3
LVDATA[4]
KPI_SO[4]
GPC[4]
LCD Interface Data Bit 4
KPI Scan Out Bit 4
GPIO Port C Bit 4
LVDATA[5]
KPI_SO[5]
GPC[5]
LCD Interface Data Bit 5
KPI Scan Out Bit 5
GPIO Port C Bit 5
LVDATA[6]
KPI_SO[6]
LCD Interface Data Bit 6
KPI Scan Out Bit 6
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 18 -
N3291xUxDN Data Sheet
I/O
PIN NAME
GPC[6]
DESCRIPTION
TYPE
GPIO Port C Bit 6
LVDATA[7]
KPI_SO[7]
GPC[7]
IOU
IOU
LCD Interface Data Bit 7
KPI Scan Out Bit 7
GPIO Port C Bit 7
LVDATA[8]
KPI_SO[8]
SPDATA[0]
GPC[8]
LCD Interface Data Bit 8
KPI Scan Out Bit 8
Sensor Interface Data Bit 0, Input
GPIO Port C Bit 8
LVDATA[9]
KPI_SO[9]
SPDATA[1]
GPC[9]
IOU
IOU
IOU
IOU
IOU
LCD Interface Data Bit 9
KPI Scan Out Bit 9
Sensor Interface Data Bit 1, Input
GPIO Port C Bit 9
LVDATA[10]
KPI_SO[10]
SPDATA[2]
GPC[10]
LCD Interface Data Bit 10
KPI Scan Out Bit 10
Sensor Interface Data Bit 2, Input
GPIO Port C Bit 10
LVDATA[11]
KPI_SO[11]
SPDATA[3]
GPC[11]
LCD Interface Data Bit 11
KPI Scan Out Bit 11
Sensor Interface Data Bit 3, Input
GPIO Port C Bit 11
LVDATA[12]
KPI_SO[12]
SPDATA[4]
GPC[12]
LCD Interface Data Bit 12
KPI Scan Out Bit 12
Sensor Interface Data Bit 4, Input
GPIO Port C Bit 12
LVDATA[13]
KPI_SO[13]
SPDATA[5]
GPC[13]
LCD Interface Data Bit 13
KPI Scan Out Bit 13
Sensor Interface Data Bit 5, Input
GPIO Port C Bit 13
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 19 -
N3291xUxDN Data Sheet
I/O
TYPE
IOU
PIN NAME
LVDATA[14]
DESCRIPTION
LCD Interface Data Bit 14
KPI Scan Out Bit 14
KPI_SO[14]
SPDATA[6]
GPC[14]
Sensor Interface Data Bit 6, Input
GPIO Port C Bit 14
LVDATA[15]
KPI_SO[15]
SPDATA[7]
GPC[15]
IOU
LCD Interface Data Bit 15
KPI Scan Out Bit 15
Sensor Interface Data Bit 7, Input
GPIO Port C Bit 15
LVDATA[16]
SHSYNC
IOU
IOU
LCD Interface Data Bit 16
Sensor Interface HSYNC, Input
GPIO Port E Bit 0
GPE[0]
LVDATA[17]
SVSYNC
LCD Interface Data Bit 17
Sensor Interface VSYNC, Input
Low Voltage Detect Output
GPIO Port E Bit 1
LVD_OUT
GPE[1]
UART Interface
URTXD
IOU
UART TX Data, Output
SPI1_CS1_
UHL_DP1
ISCK
SPI Port 1 Device Select 1, Output, Low Active
USB 1.1 Host Lite Port 1, D+
I2C Serial Clock
GPA[10]
GPIO Port A Bit 10
URRXD
IOU
UART RX Data, Input
LMVSYNC
S2FIELD
UHL_DM1
ISDA
MPU Mode VSYNC, Output
CMOS Image Sensor Field Indicator
USB 1.1 Host Lite Port 1, D-
I2C Serial Data
GPA[11]
GPIO Port A Bit 11
SPI 0 Interface
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 20 -
N3291xUxDN Data Sheet
I/O
TYPE
IOU
PIN NAME
SPI0_CLK
DESCRIPTION
SPI Port 0 Clock
Output in Master Mode
Input in Slave Mode
GPIO Port D Bit 12
GPD[12]
SPI0_CS0_
IOU
SPI Port 0 Device Select 0, Low Active
Output in Master Mode
Input in Slave Mode
GPD[13]
SPI0_DI
GPIO Port D Bit 13
IOU
IOU
SPI Port 0 Data Input
UHL_DP0
GPD[14]
USB 1.1 Host Lite Port 0, D+
GPIO Port D Bit 14
SPI0_DO
UHL_DM0
LVD_OUT
GPD[15]
SPI Port 0 Data Output
USB 1.1 Host Lite Port 0, D-
Low Voltage Detect Output
GPIO Port D Bit 15
SD Card Interface
SDCLK
IOU
IOU
IOU
IOU
IOU
IOU
SD Port 0 Clock, Output
GPIO Port E Bit 7
GPE[7]
SDCMD
SD Port 0 Command/Response
GPIO Port E Bit 6
GPE[6]
SDDAT[0]
GPE[2]
SD Port 0 Data Bit 0
GPIO Port E Bit 2
SDDAT[1]
GPE[3]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
SDDAT[2]
GPE[4]
SD Port 0 Data Bit 2
GPIO Port E Bit 4
SDDAT[3]
GPE[5]
SD Port 0 Data Bit 3
GPIO Port E Bit 5
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 21 -
N3291xUxDN Data Sheet
I/O
PIN NAME
DESCRIPTION
TYPE
GPIO A
GPA[0]
IOU
IOU
GPIO Port A Bit 0
S2PCLK
CMOS Image Sensor PCLK
GPIO Port A Bit 1
GPA[1]
S2CLKO
CMOS Image Sensor MCLK
SD_CD_
GPA[3]
KPI_SI[0]
GPA[4]
SD Card Detect, Input, Low Active
GPIO Port A Bit 3
IOU
IOU
KPI Scan In Bit 0
GPIO Port A Bit 4
SPI0_CS1_
KPI_SI[1]
SPI Port 0 Chip Select 1
KPI Scan Out Bit 2
GPA[5]
IOU
IOU
GPIO Port A Bit 5
UHL_DP0
KPI_SI[2]
USB Host 1.1 Lite Port 0, D+
KPI Scan In Bit 2
GPA[6]
GPIO Port A Bit 6
UHL_DM0
KPI_SI[3]
USB Host 1.1 Lite Port 0, D-
KPI Scan In Bit 3
RTC (Real Time Clock)
RTC_XIN (32768Hz)
RTC_XOUT (32768Hz)
RTC_RWAKE_
RTC_RPWR
I
O
32768Hz Crystal Input
32768Hz Crystal Output
I
Wakeup Enable, Input, Low Active
Power Enable, Open-Drain
OD
USB 2.0 Device Interface
UD_CDET
I
USB Device Connect Detect, Input, High Active
USB 2.0 Device D+
UD_DP
IO
IO
IO
UD_DM
USB 2.0 Device D-
UD_REXT
External Resistor Connect
Recommend to connect 12.1KΩ resistor to ground for USB 2.0 PHY
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 22 -
N3291xUxDN Data Sheet
I/O
PIN NAME
DESCRIPTION
TYPE
TV Out
TVDAC_TVOUT
O
Composite/Chroma Output
Connect an external 75Ω resistor to ground of TVDAC as TV terminal
impedence
SPI1_CLK
I2S_DOUT
ISCK
O
O
SPI Port 1 Serial Clock
I2S Serial Data Output
I2C Serial Clock
IO
IO
GPG[2]
GPIO Port G bit 2
TVDAC_REXT
IO
External Resistor Connection
Recommend to connect 160Ω resistor to ground of TVDAC
SPI Port 1 Chip Select
SPI1_CS0_
I2S_BCLK
O
I
I2S Bit Clock
GPG[3]
IO
O
GPIO Port G bit 3
TVDAC_COMP
External Capacitor Connection
Connect 0.1uF capacitor to VDD33 of TVDAC
SPI Port 1 Serial Data Input
SPI1_DI
I2S_WS
I
O
IO
O
I2S Interface Word Select, Output
GPG[4]
GPIO Port G bit 4
TVDAC_VREF
Reference Voltage Output
Connect 0.1uF capacitor to ground of TVDAC
SPI Port 1 Serial Data Output
SPI1_DO
I2S_MCLK
ISDA
O
O
I2S Master Clock
I2C Serial Data
GPIO Port G bit 5
IO
IO
GPG[5]
ADC & Touch Panel
MIC_BIAS
I
I
I
MIC ADC Bias Voltage
I2S Bit Clock
I2S_BCLK
GPG[11]
GPIO Port G bit 11
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 23 -
N3291xUxDN Data Sheet
I/O
TYPE
I
PIN NAME
PGC_VREF
DESCRIPTION
PGC Voltage Reference
I2S Master Clock
I2S_MCLK
GPH[0]
O
IO
I
GPIO Port H bit 0
ADC_AIN[3]
ADC_AIN[2]
ADC_AIN[1]
MIC_N
ADC Analog Input Channel 3
ADC Analog Input Channel 2
ADC Analog Input Channel 1
Microphone Negative Input
I2S Serial Data Input
I
I
I
I2S_DI
I
GPG[9]
I
GPIO Port G bit 9
ADC_AIN[0]
MIC_P
I
ADC Analog Input Channel 0
Microphone Positive Input
I
I2S_WS
O
IO
I2S Interface Word Select, Output
GPIO Port G bit 10
GPG[10]
ADC_TP_YP
SPI1_CLK
ISCK
I
Touch Panel YP
O
SPI Port 1 Serial Clock
I2C Serial Clock
IO
IO
GPG[12]
GPIO Port G bit 12
ADC_TP_XP
SPI1_CS0_
GPG[13]
I
O
IO
I
Touch Panel XP
SPI Port 1 Chip Select
GPIO Port G bit 13
Touch Panel XM
ADC_TP_XM
SPI1_DI
I
SPI Port 1 Serial Data Input
GPIO Port G bit 14
Touch Panel YM
GPG[14]
IO
I
ADC_TP_YM
SPI1_DO
ISDA
O
IO
IO
SPI Port 1 Serial Data Output
I2C Serial Data
GPG[15]
GPIO Port G bit 15
Audio DAC
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 24 -
N3291xUxDN Data Sheet
I/O
TYPE
O
PIN NAME
DESCRIPTION
Audio Headphone Right Channel Output
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_VREF
O
O
Audio Headphone Left Channel Output
Audio DAC Reference Voltage Output
Recommend to connect 1uF capacitor to ground of Audio DAC
Power/Ground
MVDD18
P
P
P
P
P
P
P
G
P
G
P
G
P
P
G
SDRAM I/F Power (1.8V)
SDRAM I/F Power (1.8V)
RTC Core, I/F & 32768Hz Crystal Power
USB 2.0 PHY Power (3.3V)
USB 2.0 PHY Power (1.8V)
TV DAC Power (3.3V)
MVDDQ18
RTC_VDD33
UD_VDD33
UD_VDD12
TVDAC_VDD33
ADC_VDD33
ADC_VSS33
ADAC_HPVDD33
ADAC_HPVSS33
ADAC_AVDD33
ADAC_VSS33
VDD33
ADC Power (3.3V)
ADC Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio DAC Headphone Driver Ground (0V)
Audio DAC Power (3.3V)
Audio DAC Ground (0V)
I/O Power (3.3V)
VDD18
Core Logic Power (1.8V)
Ground (0V)
VSS
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 25 -
N3291xUxDN Data Sheet
4.2 Pin Type Description
TYPE
I
DESCRIPTION
Input
O
Output
OD
IO
Open Drain output
Input / Output
IOD
IOU
IOSU
P
Input with pull-Down / Output
Input with pull-Up / Output
Input with Schmitt trigger & pull-Up/ Output
Power
G
Ground
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 26 -
N3291xUxDN Data Sheet
5. ELECTRICAL SPECIFICATION
5.1 Absolute Maximum Rating
PARAMETERS
VALUES
Ambient Temperature
-20 °C ~ 85 °C
-40 °C ~ 125 °C
-0.3V ~ 3.6V
-0.5V ~ 1.8V
-0.5V ~ 4.6V
100mA
Storage Temperature
Voltage On Any Pin
Power Supply Voltage (Core Logic)
Power Supply Voltage (I/O Buffer)
Injection Current (Latch-Up Testing)
Crystal Frequency
2MHz ~ 27MHz
5.2 DC Characteristics (Normal I/O)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
VDD33
I/O Buffer Post-Driver
Voltage
3.0
3.3
3.6
V
Core
and
Logic
I/O
Buffer
Driver
Voltage
Pre-
VDD12
300MHz
1.08
1.7
1.2
1.32
1.9
V
1.8
MVDD18
RTC_VDD
IRTC_VDD
VIH
DRAM Power Voltage
RTC Power Supply
RTC Supply Current
Input High Voltage
Input Low Voltage
V
V
-
2.0
3.6
-
-
4
uA
V
-
2.0
VDD33+0.3
0.8
-
VIL
-0.3
V
Schmitt Trigger Low to
High Threshold Point
VT+
VT-
1.5
0.9
1.7
1.9
1.2
V
V
Schmitt Trigger High to
Low Threshold Point
1.1
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 27 -
N3291xUxDN Data Sheet
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
FCPU = 300MHz,
MCLK = 150MHz,
VDD12 = 1.2V
Core Power Supply
Current
ICC
-
-
mA
TBD
-
IL
Input Leakage Current
20
mA
uA
Tri-State
Output
TBD
IOZ
Leakage Current
RPU
RPD
VOL
VOH
IOL
Pull-Up Resistor
61
76
112
156
kΩ
kΩ
V
Pull-Down Resistor
Output Low Voltage
Output High Voltage
Low Level Output Current
57
80
-
-
0.4
-
-
2.4
4.2
8.4
4.7
9.4
V
4W I/O, VOL = 0.4V
8W I/O, VOL = 0.4V
6.5
13.0
9.6
8
mA
mA
mA
mA
16.0
14.9
29.8
IOH
High Level Output Current 4W I/O, VOH = 2.4V
8W I/O, VOH = 2.4V
19.2
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 28 -
N3291xUxDN Data Sheet
5.3 Audio DAC Characteristics
Conditions: AVDD:3.3V, VDD:1.2V, TA:25℃, Fsignal:1KHz, Fsampling:48KHz, MCLK:256xFsampling
PARAMETER
Operating Voltage AVDD
MIN
TYP
3.3
MAX
UNIT
3.0
3.6
V
V
V
1.08
1.34
Operating Voltage VDD
Reference Voltage
1.2
-
-
AVDD/2
Line Output
-
-
Resolution
16
-90
Bit
dB
-
-
-76
L-Channel Total Harmonic Distortion (THD)
R-Channel Total Harmonic Distortion (THD)
Dynamic Range (-60dB input, A-weighted)
SNR (A-weighted)
-76
-90
dB
90
90
-
-
-
-
-
-
101.6
101.6
100
0.2
dB
dB
Channel Separation
dB
-
Channel Matching
dB
-
Full Scale output voltage
Load Resistor
AVDD(3.3)
-
Vrms
Kohm
pF
10
-
-
50
-
-
Load Capacitor
-
100
Analog Mute
dB
Headphone Output
-
-
-
Maximum Output Power (Po) @ 32ohm load
Maximum Output Power (Po) @ 16ohm load
L-Channel SNR (A-weighted)
31
mW
mW
dB
-
90
90
-
62
-
96
96
-
R-Channel SNR (A-weighted)
dB
-70
-70
L-Channel THD @ 32ohm load, Po=10mW
R-Channel THD @ 32ohm load, Po=10mW
-76
-76
dB
-
dB
Power Supply Current in Normal Mode (including PLL, no loading)
-
-
-
-
AVDD(3.3V)
VDD (1.2V)
8.7
0.7
mW
mW
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 29 -
N3291xUxDN Data Sheet
5.4 ADC Characteristics
PARAMETER
MIN.
TYP.
MAX.
UNIT
SAR ADC Input Voltage Range
Resolution of ADC
3.0
-
-
-
3.6
10
V
bit
Signal-to-Noise Plus Distortion of ADC from
Line In
-
-60
-
dB
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
No Missing Code
-
-
-
-
±2.0
±0.8
10
-
LSB
LSB
bit
-
-
AD Conversion Rate=ADCCLK/16
-
150
KHz
5.5 AC Characteristics (Digital Interface)
5.5.1 Clock Input Characteristics
TXIN
XIN
TXINWH
T
XINWL
F
XIN = 1 / TXIN
XINDUTY = TXINWH / ( TXINWH + TXINWL
)
SYMBOL
FXIN
PARAMETER
Clock Input Frequency
Clock Input Duty Cycle
MIN.
-
TYP.
12 / 27
50
MAX. UNIT
-
MHz
%
XINDUTY
45
55
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 30 -
N3291xUxDN Data Sheet
5.6 Thermal characteristics of SLQFP-128 Package
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 31 -
N3291xUxDN Data Sheet
6. ORDERING INFORMATION
PART NO.
PACKAGE TYPE
DESCRIPTION
Cost-effective package with 32Mbx16 DDR2 inside,
without OVG accelerator.
N32916U1DN
LQFP-128, MCP
Cost-effective package with 32Mbx16 DDR2 inside and
OVG accelerator.
N32916U2DN
N32915U3DN
N32915U4DN
LQFP-128, MCP
LQFP-128, MCP
LQFP-128, MCP
Cost-effective package with 16Mbx16 DDR2 inside,
without OVG accelerator.
Cost-effective package with 16Mbx16 DDR2 inside and
OVG accelerator.
6.1 Part Number Definition
6.2 Difference between N3291xU1(3)DN and N3291xU2(4)DN
N3291xU1DN/N3291xU3DN
-
N3291xU2DN/N3291xU4DN
OpenVG(OVG) Accelerator
V
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 32 -
N3291xUxDN Data Sheet
7. PACKAGE OUTLINE
7.1 128L LQFP (14X14X1.4mm body, 0.4mm pitch)
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 33 -
N3291xUxDN Data Sheet
8. REVISION HISTORY
Version
Date
Description
Initial release.
A0
Aug. 1, 2012
Change Operation Temperature Range
Add N32916U2DN ordering information.
A1
A2
A3
Oct. 1, 2012
Oct. 25, 2012
Jun. 1, 2013
Add Part Number Definition
Add N32915UxDN Parts Information
Add MVDD18 Votage Range
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or
failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are
deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control
instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems
designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications
intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton
as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred
by Nuvoton.
Nuvoton Technology Corp.
http://www.nuvoton.com/
Release Date: Jun. 2013
Revision A3
- 34 -
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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