N32914R1DN [NUVOTON]
ARM926-based Media Processor;
| 型号： | N32914R1DN |
| 厂家： | 
NUVOTON |
| 描述： | ARM926-based Media Processor |
| 文件： | 总47页 (文件大小：1659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N3290x
Data Sheet
ARM926-based Media Processor
Nuvoton Technology Corp.
http://www.nuvoton.com/
1
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
The information in this document is subject to change without notice.
The Nuvoton Technology Corp. shall not be liable for technical or editorial errors or omissions
contained herein; nor for incidental or consequential damages resulting from the furnishing,
performance, or use of this material.
This documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or
reduced to any electronic medium or machine readable form without prior consent, in writing, from the
Nuvoton Technology Corp.
Nuvoton Technology Corp. All rights reserved.
Nuvoton Technology Corp.
http://www.nuvoton.com/
2
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
N3290x
ARM926-based Media Processor
Table of Contents
1.
GENERAL DESCRIPTION...................................................................................................................................5
1.1 Applications..............................................................................................................................................5
2.
3.
FEATURES...........................................................................................................................................................6
PIN DIAGRAM....................................................................................................................................................12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
N32901U1DN (LQFP-128).....................................................................................................................12
N32901U2DN (LQFP-128).....................................................................................................................13
N32903U1DN (LQFP-128).....................................................................................................................14
N32905U1DN (LQFP-128).....................................................................................................................15
N32905U2DN (LQFP-128).....................................................................................................................16
N32903R1DN (TQFP-64).......................................................................................................................17
N32901R1DN (LQFP-64).......................................................................................................................18
4.
5.
PIN DESCRIPTION............................................................................................................................................19
4.1
4.2
Pin Description & Cross Reference........................................................................................................19
Pin Type Description ..............................................................................................................................28
ELECTRICAL SPECIFICATION.........................................................................................................................29
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Absolute Maximum Rating .....................................................................................................................29
DC Characteristics (Normal I/O) ............................................................................................................29
Audio DAC Characteristics.....................................................................................................................30
ADC Characteristics..................................................................................................................................31
AC Characteristics (Digital Interface) .........................................................................................................31
Power-on Sequence...............................................................................................................................40
Thermal characteristics of LQFP-128 Package .....................................................................................40
6.
7.
ORDERING INFORMATION..............................................................................................................................41
6.1
6.2
Part Number Definition...........................................................................................................................41
Difference between N32901U1DN, N32903U1DN, N32905U1DN and N32905U2DN..........................41
PACKAGE OUTLINE..........................................................................................................................................42
Nuvoton Technology Corp.
http://www.nuvoton.com/
3
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
7.1
7.2
7.3
LQFP-128 (14X14X1.4mm body, 0.4mm pitch).....................................................................................42
TQFP-64 (10X10X1.0mm body, 0.5mm pitch).......................................................................................43
LQFP-64 (10X10X1.4mm body, 0.5mm pitch).......................................................................................46
8.
REVISION HISTORY..........................................................................................................................................47
Nuvoton Technology Corp.
http://www.nuvoton.com/
4
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
1. GENERAL DESCRIPTION
The N3290xUxDN is built on the ARM926EJ-S CPU core and integrated with JPEG codec, CMOS sensor interface,
32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application needs while saving the
BOM cost. The combination of ARM926 @ 200MHz, synchronous DRAM, 2D BitBLT accelerator, CMOS image
sensor interface, LCD panel interface, USB 1.1 Host & USB2.0 HS Device makes the N3290xUxDN the best choice
for LCD ELA devices.
Maximum resolution for the N3290xUxDN is XVGA (1,024x768) @ TFT LCD panel. The 2D BitBLT accelerator
accelerates the graphic compution to make the rendering smooth and off-load CPU to save power consumption.
The N3290xUxDN is well-positioned in terms of cost/performance for the applications which bitmap graphics is
extensively used or CMOS Image Sensor (CIS) interface is required.
The N3290xUxDN is for application under Linux OS and leverage the driver availability of emerging functionalities like
Wi-Fi, browser, etc. On the other hand, the open source code environment also give the product development more
flexible.
To meet the different requirement of the overall system BOM cost, the different size of DRAM is stacked with N3290x
main SoC into one package, that is, multi-chip package (MCP). The N32901U1DN is particularly designed with the
128-pin LQFP package and the 1Mbitx16 SDRAM is stacked inside the MCP. The N32903U1DN is particularly
designed with the 128-pin LQFP package and the 4Mbitx16 SDRAM is stacked inside the MCP. The 16Mbitx16
SDRAM is stacked inside the N32905UxDN MCP to ensure higher performance and minimize the system design
efforts, like EMI & noise coupling. Total BOM cost could be reduced by employing 2-layer PCB along with the
elimination of damping resistors, EMI prevention components, etc. Advantages including, but not limited to, less PCB
space, shorter lead time, and higher / reliable production yield.
1.1 Applications
ELA (Educational Learning Aid)
HMI
Security
Home Appliance
Advertisement
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
2. FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
Frequency up to 200MHz@1.8V core power operation voltage
JTAG interface supported for development and debugging
Internal SRAM & ROM
8KB internal SRAM and 16KB IBR internal booting ROM supported
IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
Memory card
SD card
SD-to-NAND flash bridge
Raw NAND Flash
SPI Flash
USB
EDMA (Enhanced DMA)
Totally 5 DMA channels supported
4 peripheral DMA channels for transfer between memory and on-chip peripherals,
such as ADC, UART and SPI
One dedicated channel for memory-to-memory transfer
Byte, half-word and word data width types supported
Single and burst transfer modes supported
Block transfer supported in memory-to-memory transfer channel
Color format transformation supported in memory-to-memory transfer channel
Source color format could be RGB555, RGB565 and YCbCr422
Destination color format could be RGB555, RGB565 and YCbCr422
Auto reload supported for continuous data transfer
Interrupt generation supported in the half-of-transfer or end-of-transfer
Capture (CMOS Sensor I/F)
CCIR601 & CCIR656 interfaces supported for connection to CMOS image sensor
Resolution up to 2M pixel for Still Image Capture, 640x480 (VGA) resolution for MJPEG
Video Streaming
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system
memory
Planar and packet data formats supported for data storing to system memory
Image cropping supported with the cropping window up to 4096x2048
Image scaling-down supported
Vertical and horizontal scaling-down for preview mode supported
The scaling factor is N/M
Two pairs of configurable 8-bit N and 8-bit M for vertical and horizontal scaling-
down
The value of N has to equal to or less than M
Frame rate control supported
Combines two interlace fields to a single frame supported for data in from TV-decoder
JPEG Codec
Baseline Sequential mode JPEG codec function compliant with ISO/IEC 10918-1
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
international JPEG standard supported.
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format
image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)
format image
Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode
mode
Support rotate function in encode mode
Packet Format
Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and
4:2:0 format
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image RGB555, RGB565 and RGB888 formats.
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for
decode mode
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode
mode
2D Accelerator
BitBLT operation
2x2 transform matrix with effects:
Scale
Translate
Rotate
Shear
Fill
Alpha blending and color transformation supported
Source format for operations: supported color format of source bitmap
Rectangle Fill with single color – ARGB8888
Fill with blending effect supported
Supported color formats
Source
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
1 bit/pixel, 2 bits/pixel, 4 bits/pixel, 8 bits/pixel with RGB color palette
Destination
16 bits/pixel – RGB565
32 bits/pixel – ARGB8888
Nuvoton Technology Corp.
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7
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
VPOST
8/16/18/24-bit SYNC type and 8/9/16/18/24-bit MPU type TFT LCD supported
Color format supported:
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data in
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data out
XGA (1024x768), SVGA (800x600), WVGA (800x480), D1 (720X480), VGA (640x480),
WQVGA (480x272), QVGA (320x240) and HVGA (640x240) resolution supported
The maximum resolution is up to D1 (720X480) for TV output
The maximum resolution is up to 1024X768 for TFT LCD panel for still image
displaying
The maximum resolution is up to 480x272 for TFT LCD panel for MJPEG video
displaying up to 25fps.
Display scaler – to fit different size of LCD panels
Horizontal: At most 4.0x scale
Vertical: At most 3.0x scale
For SYNC type LCD:
For 8-bit bus
CCIR601 YCbCr422 packet mode (NTSC/PAL) supported
CCIR601 RGB Dummy mode (NTSC/PAL) supported
CCIR656 interface supported
RGB Through mode supported
For 16/18/24-bit bus
Parallel pixel data output mode (1-pixel/1-clock)
NTSC/PAL interlace & non-interlace output supported
Color format transform supported:
Color format transform between YCbCr422 and RGB565
Color format transform from YCbCr422 to RGB888
TV encoder supported
Dual screen, outputs to TV and LCD simultaneously with same content, supported
LCD panel should be 320X240 MPU-type, or 8-bit SYNC-type LCD panel with TV
timing
Notch filter for NTSC supported to remove the rainbow color effect
Support OSD function to overlap system information like battery life, brightness tuning,
volume tuning or muting, etc.
Frame Switch Controller
Frame relation controlled between VPOST and Capture supported
2 modes supported to switch Frame Buffer Base
Frame Ratio Mode (16 selectable ratio)
Frame sync mode
Double/triple buffers supported
SPU (Sound Processing Unit)
32 stereo channels supported
PCM8/PCM16/4-bit MDPCM/TONE source format supported
7-bit volume control supported for each of 32 channels
5-bit pan control supported for each L/R of 32 channels
10-band equalizer supported
Special code supported for loop playing and event detection
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
Audio DAC
16-bit stereo DAC supported with headphone driver output
H/W volume control supported
I2S Controller
I2S interface supported to connect external audio codec
16/18/20/24-bit data format supported
Storage Interface Controller
Interface to NAND Flash:
8-bit data bus width supported
SLC and MLC type NAND Flash supported
512B, 2KB, 4KB, and 8KB page size NAND Flash supported
ECC4, ECC8, ECC12 and ECC15 algorithm supported for ECC generation, error
detection and error correction
PBA-NAND flash supported
Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported
SD-to-NAND flash bridge supported
DMA function supported to accelerate the data transfer between system memory and
NAND Flash or SD/MMC/SDIO/SDHC/micro-SD
USB Device Controller
USB2.0 HS (High-Speed) x 1 port
6 configurable endpoints supported
Control, Bulk, Interrupt and Isochronous transfers supported
Suspend and remote wakeup supported
USB Host Controller
USB1.1 Host one H/W Engine, two pin locations.
Fully compliant with USB Revision 1.1 specification
Open Host Controller Interface (OHCI) Revision 1.0 compatible
Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices supported
Control, Bulk, Interrupt and Isochronous transfers supported
Timer & Watch-Dog Timer
Two 32-bit with 8-bit pre-scalar timers supported
One programmable 24-bit Watch-Dog Timer supported
PWM
4 PWM channel outputs supported
16-bit counter supported for each PWM channel
Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels
Two clock-dividers supported and each divider shared by two PWM channels
Two Dead-Zone generators supported and each generator shared by two PWM channels
Auto reloaded mode and one-shot pulse mode supported
Capture function supported
UART
A high speed UART supported:
Baud rate is up to 1M bps
4 signals TX, RX, CTS and RTS supported
Nuvoton Technology Corp.
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9
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
A normal UART supported:
Baud rate is up to 115.2K bps
2 signals TX and RX supported only
SPI
One SPI controller is supported
Both master and slave mode are supported in SPI interface
Two chip selection signals for two SPI devices
I2C
One I2C channel supported
Compatible with Philips’s I2C standard and only master mode supported
Multi-master operation supported
Advanced Interrupt Controller
Total 32 interrupt source supported
Configurable interrupt type:
Low-active level triggered interrupt
High-active level triggered interrupt
Low-active edge (falling edge) triggered interrupt
High-active edge (rising edge) triggered interrupt
Individual interrupt mask bit for each interrupt source
8 different priority levels supported
Daisy-chain priority mechanism supported for interrupts with same priority level
Low priority interrupt automatic masking supported for interrupt nesting
RTC
Independent power plane supported
32.768 KHz crystal oscillation circuit supported
Time counter (second, minute, hour) and Calendar counter (day, month, year) supported
Alarm supported (second, minute, hour, day, month and year)
12/24-hour mode and Leap year supported
Alarm to wake chip up from Standby mode or from Power-down mode supported
Wake chip up from Power-down mode by input pin supported
Power-off chip by register setting supported
Power-on timeout is supported for low battery protection
GPIO
80 programmable general purpose I/Os supported and separated into 5 groups
Individual configuration supported for each I/O signal
Configurable interrupt control functions supported
Configurable de-bounce circuit supported for interrupt function
ADC
Multi-channel, 10-bit ADC supported
2 channels dedicated for 4-wire resistive touch sensor inputs
2 channels dedicated for Audio ADC with Microphone pre-Amp & AGC
3 channels reserved for various purposes, like LVD (Low Voltage Detection), keypad
input, and light sensor
Input voltage range from 0V ~ 3.3V supported
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
Maximum 25MHz input clock supported
Maximum 400K/s conversion rate supported
LVR (Low Voltage Reset) supported
Power Management
Advanced power management including Power Down, Deep Standby, CPU Standby, and
Normal Operating modes
Normal Operating Mode
Core power is 1.8V and chip is in normal operation
CPU Standby Mode
Core power is 1.8V and only ARM CPU clock is turned OFF
Deep Standby Mode
Core power is 1.8V and all IP clocks are turned OFF
Power Down Mode
Only the RTC power is ON. Other 3.3V and 1.8V power are OFF
Software Support
Development Tools
Bootloader / Diagnostic Program / NAND Writer Program: ADS 1.2 or RVDS 2.x or 3.x
Linux Kernel (2.6.17.14) / System Manager: GCC 4.2
TurboWriter / Sync Tool: Microsoft VC 6.0
NAND Flash File System
FAT12, FAT16 and FAT32 with long filename are supported
Hidden disk is supported
RAM disk is supported
S/W audio Library
Decoders with ADPCM / MP3 / ACC / OGG / WMA format support
32-polyphony Wavetable MIDI synthesizer
Programmable sampling rate and target bit rate
USB Driver
MS (Mass Storage) Class
HID (Human Interface Device) Class
Operating Voltage
I/O: 3.3V
Core: 1.8V for 200MHz
Package
LQFP-128 (MCP, stacked with DDR @ 1.8V and SDR @ 1.8V)
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3. PIN DIAGRAM
3.1 N32901U1DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSSQ
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDDQ
MVDDQ
MVSSQ
MVREF
MVSS
GPD[12]/
GPD[13]/
GPD[14]/
GPD[15]/
SPI0_CLK
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
TRST_/
10
/
GPE[6]
HUR_RTS
/SPI0_CS1_/
GPD[4]
GPE[7]/
SDCLK
TDO
TDI
HUR_CTS
PWM3
/
/
/
/
/
/
/
/
/
/
/
GPE[2]/ SDDAT[0]
GPE[3]
GPD[3]
GPD[2]
SDDAT[1]
XIN
/
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSSQ
MVDDQ
MVSSQ
MVDDQ
MVDD
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
MVREF
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD
30
RTC_XOUT
ADC_AIN[3]
MVSS
VSS
/LVDATA[17]
/
GPE[1] SVSYNC
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.2 N32901U2DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSSQ
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDDQ (3.3V)
MVDDQ (3.3V)
MVSSQ
NC
GPD[12]/
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CLK
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
90
80
70
GPE[4]/
GPE[5]/
MVSS
VDD18
UD_CDET
TRST_/
10
/
GPE[6]
HUR_RTS
/SPI0_CS1_/
GPD[4]
GPE[7]/
SDCLK
TDO
TDI
HUR_CTS
PWM3
/
/
/
/
/
/
/
/
/
/
/
GPE[2]/ SDDAT[0]
GPE[3]
GPD[3]
GPD[2]
SDDAT[1]
XIN
/
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSSQ
GPA[0]
GPA[1]
MVDDQ(3.3V)
MVSSQ
MVDDQ(3.3V)
MVDD(3.3V)
NC
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD
30
RTC_XOUT
ADC_AIN[3]
MVSS
VSS
/LVDATA[17]
/
GPE[1] SVSYNC
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.3 N32903U1DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSSQ
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDDQ
MVDDQ
MVSSQ
MVREF
MVSS
GPD[12]/
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CLK
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
TRST_/
10
/
GPE[6]
HUR_RTS
/SPI0_CS1_/
GPD[4]
GPE[7]/
SDCLK
TDO
TDI
HUR_CTS
PWM3
/
/
/
/
/
/
/
/
/
/
/
GPE[2]/ SDDAT[0]
GPE[3]
GPD[3]
GPD[2]
SDDAT[1]
XIN
/
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSSQ
MVDDQ
MVSSQ
MVDDQ
MVDD
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
MVREF
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD
30
RTC_XOUT
ADC_AIN[3]
MVSS
VSS
/LVDATA[17]
/
GPE[1] SVSYNC
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.4 N32905U1DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSSQ
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDDQ
MVDDQ
MVSSQ
MVREF
MVSS
GPD[12]/
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CLK
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
TRST_/
10
/
GPE[6]
HUR_RTS
/SPI0_CS1_/
GPD[4]
GPE[7]/
SDCLK
TDO
TDI
HUR_CTS
PWM3
/
/
/
/
/
/
/
/
/
/
/
GPE[2]/ SDDAT[0]
GPE[3]
GPD[3]
GPD[2]
SDDAT[1]
XIN
/
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSSQ
MVDDQ
MVSSQ
MVDDQ
MVDD
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
MVREF
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD
30
RTC_XOUT
ADC_AIN[3]
MVSS
VSS
/LVDATA[17]
/
GPE[1] SVSYNC
Nuvoton Technology Corp.
http://www.nuvoton.com/
15
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.5 N32905U2DN (LQFP-128)
/
SDDAT1[0]
SDDAT1[1]/
GPB[14]/
UHL_DM1
UHL_DP1
LMVSYNC
GPB[1]
/
/
/
SPCLK
SCLKO
MVSSQ
ADAC_HPOUT_L
ADAC_HPVDD33
1
GPB[0]/
_
ISDA
ISCK
/
/
GPB[13] WDT_RST_ /
ADAC_HPVSS33
MVDDQ
MVDDQ
MVSSQ
MVREF
MVSS
GPD[12]/
GPD[13] /
GPD[14]/
GPD[15]/
SPI0_CLK
SPI0_CS0_
SPI0_DI
SPI0_DO
SDDAT[2]
SDDAT[3]
SDCMD
90
80
70
GPE[4]/
GPE[5]/
VDD18
UD_CDET
TRST_/
10
/
GPE[6]
HUR_RTS
/SPI0_CS1_/
GPD[4]
GPE[7]/
SDCLK
TDO
TDI
HUR_CTS
PWM3
/
/
/
/
/
/
/
/
/
/
/
GPE[2]/ SDDAT[0]
GPE[3]
GPD[3]
GPD[2]
SDDAT[1]
XIN
/
HUR_RXD
HUR_TXD
/
SPI1_CS1_ PWM0
PWM2
PWM1
TMS
TCK
RST_
GPD[1]
GPD[0]
XOUT
VDD18
MVSSQ
MVDDQ
MVSSQ
MVDDQ
MVDD
GPA[0]
GPA[1]
/
SD_CD_
LMVSYNC
UHL_DP1
/UHL_DM1
20
GPA[2]/
GPA[3]/
GPA[4]
/
GPA[5] SPI0_CS1_
GPA[6]/SPI1_CS1_
VDD33
MVREF
UD_VDD18
UD_VSS
UD_DM
RTC_VDD
RTC_RPWR
RTC_RWAKE_
RTC_XIN
UD_DP
UD_VDD33
UD_REXT
MVDD
30
RTC_XOUT
ADC_AIN[3]
MVSS
VSS
/LVDATA[17]
/
GPE[1] SVSYNC
Nuvoton Technology Corp.
http://www.nuvoton.com/
16
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.6 N32903R1DN (TQFP-64)
GPD[13]
/
1
5
SPI0_CS0_
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_HPVDD33
ADAC_HPVSS33
GPD[14]/
GPD[15]/
SPI0_DI
SPI0_DO
45
40
35
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
MVDD18
MVREF
VDD18
GPE[6] /
GPE[7] /
SDCMD
SDCLK
UD_CDET
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
HUR_RXD / PWM2 / GPD[2]
HUR_TXD / PWM1 / GPD[1]
10
15
XIN
XOUT
RST_
GPA[1]/
SD_CD
MVREF
PLL_VDD18
UD_DM
GPA[3]/
UHL_DP1
/UHL_DM1
/SPI0_CS1_
GPA[4]
GPA[5]
UD_DP
ADC_AIN[2]
UD_VDD33
Nuvoton Technology Corp.
http://www.nuvoton.com/
17
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
3.7 N32901R1DN (LQFP-64)
GPD[13]
/
1
5
SPI0_CS0_
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_HPVDD33
ADAC_HPVSS33
GPD[14]/
GPD[15]/
SPI0_DI
SPI0_DO
45
40
35
GPE[4] / SDDAT[2]
GPE[5] / SDDAT[3]
MVDD33
VSS
GPE[6] /
GPE[7] /
SDCMD
SDCLK
VDD18
UD_CDET
GPE[2] / SDDAT[0]
GPE[3] / SDDAT[1]
HUR_RXD / PWM2 / GPD[2]
HUR_TXD / PWM1 / GPD[1]
10
15
XIN
XOUT
RST_
GPA[1]/
SD_CD
VSS
PLL_VDD18
UD_DM
GPA[3]/
UHL_DP1
/UHL_DM1
/SPI0_CS1_
GPA[4]
GPA[5]
UD_DP
ADC_AIN[2]
UD_VDD33
Nuvoton Technology Corp.
http://www.nuvoton.com/
18
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
4. PIN DESCRIPTION
4.1 Pin Description & Cross Reference
I/O
Pin Name
Description
Type
Clock & Reset
XIN
I
27MHz/12MHz Crystal Input
27MHz/12MHz Crystal Output
●
●
●
●
●
●
●
●
●
●
●
●
●
●
XOUT
O
RST_
IOSU System Reset, Input, Low Active
Watch-Dog Reset, Output, Low Active
●
●
●
●
●
●
●
JTAG Interface
TCK
IOD
JTAG Interface Test Clock, Input
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low
Active
●
●
●
●
●
PWM0
GPD[0]
TMS
PWM Channel 0
GPIO Port D Bit 0
IOU
IOU
IOU
JTAG Interface Test Mode Select, Input
High-Speed UART TX Data, Output
PWM Channel 1
HUR_TXD
PWM1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPD[1]
TDI
GPIO Port D Bit 1
JTAG Interface Test Data In, Input
High-Speed UART RX Data, Input
PWM Channel 2
HUR_RXD
PWM2
GPD[2]
TDO
GPIO Port D Bit 2
JTAG Interface Test Data Out, Output
HUR_CTS
High-Speed UART Clear-To-Send, Input,
Low Active
●
●
●
●
●
PWM3
GPD[3]
TRST_
PWM Channel 3
GPIO Port D Bit 3
IOU
JTAG Interface Test Reset, Input, Low
Active
HUR_RTS
SPI0_CS1_
GPD[4]
High-Speed UART Reset-To-Send, Output,
Low Active
●
●
●
●
●
SPI Port 0 Device Select 1, Output, Low
Active
GPIO Port D Bit 4
Nuvoton Technology Corp.
http://www.nuvoton.com/
19
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
NAND Interface
NCS0_
IOU
IOU
NAND Interface Chip Select 0, Output, Low
Active
●
●
●
●
●
●
●
●
●
●
SDDAT2[1]
GPE[8]
SD Port 2 Data Bit 1
GPIO Port E Bit 8
NCS1_
NAND Interface Chip Select 1, Output, Low
Active
SDDAT2[0]
GPE[9]
SD Port 2 Data Bit 0
GPIO Port E Bit 9
NALE
IOU
IOU
IOU
NAND
Output, High Active
Interface
Address-Latch-Enable,
●
●
●
●
●
●
●
●
●
●
GPE[10]
NCLE
GPIO Port E Bit 10
NAND Interface Command-Latch-Enable,
Output, High Active
GPE[11]
NBUSY0_
SDDAT2[3]
GPD[5]
GPIO Port E Bit 11
NAND Interface Busy 0, Input, Low Active
SD Port 2 Data Bit 3
●
●
●
●
●
●
●
●
●
●
GPIO Port D Bit 5
NBUSY1_
SDDAT2[2]
GPD[6]
IOU
IOU
NAND Interface Busy 1, Input, Low Active
SD Port 2 Data Bit 2
GPIO Port D Bit 6
NRE_
NAND Interface Read Enable, Output, Low
Active
●
●
●
●
●
SDCLK2
GPD[7]
NWR_
SD Port 2 Clock, Output
GPIO Port D Bit 7
IOU
IOU
NAND Interface Write Enable, Output, Low
Active
●
●
●
●
●
●
●
●
●
●
SDCMD2
GPD[8]
SD Port 2 Command/Response
GPIO Port D Bit 8
ND[7:0]
NAND Interface Data Bit [7:0]
CHIPCFG[7:0]
Chip Power-On Configuration Bit [7:0],
Input
Sensor/Video-In Interface
Nuvoton Technology Corp.
http://www.nuvoton.com/
20
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
SCLKO
IOU
IOU
IOU
IOU
Clock to Sensor Module, Output
USB Host Like Interface, DP
SD Port 1 Data Bit 1
UHL_DP1
SDDAT1[1]
GPB[0]
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPIO Port B Bit 0
SPCLK
Sensor Interface Pixel Clock, Input
USB Host Like Interface, DM
SD Port 1 Data Bit 0
UHL_DM1
SDDAT1[0]
GPB[1]
GPIO Port B Bit 1
SVSYNC
Sensor Interface VSYNC, Input
I2S Interface Clock, Input
SD Port 1 Command/Response
GPIO Port B Bit 3
I2S_BCLK
SDCMD1
GPB[3]
SFIELD
Sensor Interface Even/ODD Field Indicator,
Input
I2S_WS
SDDAT1[3]
GPB[4]
I2S Interface Word Select, Output
SD Port 1 Data Bit 3
●
●
●
●
●
GPIO Port B Bit 4
SPDATA[0]
I2S_DOUT
SDDAT1[2]
GPB[5]
IOU
IOU
Sensor Interface Data Bit 0, Input
I2S Interface Data Output
SD Port 1 Data Bit 2
●
●
●
●
●
●
●
●
●
●
GPIO Port B Bit 5
SPDATA[1]
I2S_DIN
GPB[6]
Sensor Interface Data Bit 1, Input
I2S Interface Data Input
GPIO Port B Bit 6
I2C Interface
ISCK
IOU
IOU
I2C Interface Clock, Output
GPIO Port B Bit 13
●
●
●
●
●
●
●
●
●
●
GPB[13]
ISDA
I2C Interface Data
LMVSYNC
LFMARK
MPU Mode VSYNC, Output
Frame Mark, Input
GPB[14]
GPIO Port B Bit 14
Nuvoton Technology Corp.
http://www.nuvoton.com/
21
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
LCD/Display Interface
LPCLK
GPB[15]
IOU
LCD Interface Pixel Clock, Output
GPIO Port B Bit 15
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
LHSYNC
GPD[9]
LVSYNC
GPD[10]
LVDE
IOU
IOU
IOU
LCD Interface HSYNC, Output, High Active
GPIO Port D Bit 9
LCD Interface VSYNC, Output, High Active
GPIO Port D Bit 10
LCD Interface Data Enable, Output, High
Active
●
●
●
●
●
GPD[11]
LVDATA[0]
GPC[0]
GPIO Port D Bit 11
IOU
IOU
IOU
IOU
IOU
LCD Interface Data Bit 0
GPIO Port C Bit 0
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
LVDATA[1]
GPC[1]
LCD Interface Data Bit 1
GPIO Port C Bit 1
LVDATA[2]
GPC[2]
LCD Interface Data Bit 2
GPIO Port C Bit 2
LVDATA[3]
GPC[3]
LCD Interface Data Bit 3
GPIO Port C Bit 3
LVDATA[4]
GPC[4]
LCD Interface Data Bit 4
GPIO Port C Bit 4
●
●
●
●
●
●
●
●
●
●
CHIPCFG[8]
LVDATA[5]
GPC[5]
Chip Power-On Configuration Bit [8], Input
LCD Interface Data Bit 5
GPIO Port C Bit 5
IOU
IOU
CHIPCFG[9]
LVDATA[6]
GPC[6]
Chip Power-On Configuration Bit [9], Input
LCD Interface Data Bit 6
GPIO Port C Bit 6
●
●
●
●
●
CHIPCFG[10]
Chip Power-On Configuration Bit [10],
Input
LVDATA[7]
GPC[7]
IOU
IOU
LCD Interface Data Bit 7
GPIO Port C Bit 7
●
●
●
●
●
●
●
●
●
●
LVDATA[8]
LCD Interface Data Bit 8
●
●
Nuvoton Technology Corp.
http://www.nuvoton.com/
22
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
KPI_SI[0]
SPDATA[0]
GPC[8]
KPI Scan In Bit 0
Sensor Interface Data Bit 0, Input
GPIO Port C Bit 8
LVDATA[9]
KPI_SI[1]
SPDATA[1]
GPC[9]
IOU
IOU
IOU
IOU
IOU
IOU
IOU
LCD Interface Data Bit 9
KPI Scan In Bit 1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Sensor Interface Data Bit 1, Input
GPIO Port C Bit 9
LVDATA[10]
KPI_SI[2]
SPDATA[2]
GPC[10]
LCD Interface Data Bit 10
KPI Scan In Bit 2
Sensor Interface Data Bit 2, Input
GPIO Port C Bit 10
LVDATA[11]
KPI_SI[3]
SPDATA[3]
GPC[11]
LCD Interface Data Bit 11
KPI Scan In Bit 3
Sensor Interface Data Bit 3, Input
GPIO Port C Bit 11
LVDATA[12]
KPI_SI[4]
SPDATA[4]
GPC[12]
LCD Interface Data Bit 12
KPI Scan In Bit 4
Sensor Interface Data Bit 4, Input
GPIO Port C Bit 12
LVDATA[13]
KPI_SI[5]
SPDATA[5]
GPC[13]
LCD Interface Data Bit 13
KPI Scan In Bit 5
Sensor Interface Data Bit 5, Input
GPIO Port C Bit 13
LVDATA[14]
KPI_SI[6]
SPDATA[6]
GPC[14]
LCD Interface Data Bit 14
KPI Scan In Bit 6
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Sensor Interface Data Bit 6, Input
GPIO Port C Bit 14
LVDATA[15]
KPI_SI[7]
SPDATA[7]
LCD Interface Data Bit 15
KPI Scan In Bit 7
Sensor Interface Data Bit 7, Input
Nuvoton Technology Corp.
http://www.nuvoton.com/
23
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
GPC[15]
LVDATA[16]
SHSYNC
GPIO Port C Bit 15
IOU
IOU
LCD Interface Data Bit 16
Sensor Interface HSYNC, Input
GPIO Port E Bit 0
●
●
●
●
●
●
●
●
●
●
GPE[0]
LVDATA[17]
SVSYNC
LCD Interface Data Bit 17
Sensor Interface VSYNC, Input
GPIO Port E Bit 1
GPE[1]
UART Interface
URTXD
IOU
IOU
UART TX Data, Output
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low
Active
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPA[10]
URRXD
GPIO Port A Bit 10
UART RX Data, Input
MPU Mode VSYNC, Output
Frame Mark, Input
GPIO Port A Bit 11
LMVSYNC
LFMARK
GPA[11]
SPI 0 Interface
SPI0_CLK
IOU
IOU
SPI Port 0 Clock
Output in Master Mode
Input in Slave Mode
GPIO Port D Bit 12
●
●
●
●
●
●
●
●
●
●
GPD[12]
SPI0_CS0_
SPI Port 0 Device Select 0, Low Active
Output in Master Mode
Input in Slave Mode
●
●
GPD[13]
SPI0_DI
GPIO Port D Bit 13
IOU
IOU
SPI Port 0 Data Input
GPIO Port D Bit 14
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPD[14]
SPI0_DO
SPI Port 0 Data Output
GPIO Port D Bit 15
GPD[15]
SD Card Interface
SDCLK
IOU
SD Port 0 Clock, Output
●
●
●
●
●
●
●
Nuvoton Technology Corp.
http://www.nuvoton.com/
24
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
GPE[7]
SDCMD
GPIO Port E Bit 7
IOU
IOU
IOU
IOU
IOU
SD Port 0 Command/Response
GPIO Port E Bit 6
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPE[6]
SDDAT[0]
GPE[2]
SD Port 0 Data Bit 0
GPIO Port E Bit 2
SDDAT[1]
GPE[3]
SD Port 0 Data Bit 1
GPIO Port E Bit 3
SDDAT[2]
GPE[4]
SD Port 0 Data Bit 2
GPIO Port E Bit 4
SDDAT[3]
GPE[5]
SD Port 0 Data Bit 3
GPIO Port E Bit 5
GPIO A
GPA[0]
IOU
IOU
GPIO Port A Bit 0
●
●
●
●
●
●
●
●
●
●
GPA[1]
GPIO Port A Bit 1
●
●
SD_CD_
GPA[2]
SD Card Detect, Input, Low Active
GPIO Port A Bit 2
IOU
LMVSYNC
LFMARK
KPI_SO[0]
GPA[3]
MPU Mode VSYNC, Output
Frame Mark, Input
●
●
●
●
●
KPI Scan Out Bit 0
IOU
IOU
IOU
GPIO Port A Bit 3
UHL_DP1
KPI_SO[1]
GPA[4]
USB Host 1.0 Lite Port 1, D+
KPI Scan Out Bit 1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
GPIO Port A Bit 4
UHL_DM1
KPI_SO[2]
GPA[5]
USB Host 1.0 Lite Port 1, D-
KPI Scan Out Bit 2
GPIO Port A Bit 5
SPI0_CS1_
SPI Port 0 Device Select 1, Output, Low
Active
●
●
●
●
●
●
●
●
●
●
●
●
KPI_SO[3]
GPA[6]
KPI Scan Out Bit 3
IOU
GPIO Port A Bit 6
SPI1_CS1_
SPI Port 1 Device Select 1, Output, Low
Nuvoton Technology Corp.
http://www.nuvoton.com/
25
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
Active
KPI_SO[4]
KPI Scan Out Bit 4
GPIO Port A Bit 7
KPI Scan Out Bit 5
GPA[7]
KPI_SO[5]
IOU
●
●
●
●
●
●
●
RTC (Real Time Clock)
RTC_XIN
(32768Hz)
I
32768Hz Crystal Input
32768Hz Crystal Output
●
●
●
●
●
●
●
●
●
●
RTC_XOUT
(32768Hz)
O
RTC_RWAKE_
RTC_RPWR
I
Wakeup Enable, Input, Low Active
Power Enable, Open-Drain
●
●
●
●
●
●
●
●
●
●
OD
USB 2.0 Device Interface
UD_CDET
I
USB Device Connect Detect, Input, High
Active
●
●
●
●
●
●
●
UD_DP
IO
IO
IO
USB 2.0 Device D+
●
●
●
●
●
●
●
●
●
●
●
●
●
●
UD_DM
UD_REXT
USB 2.0 Device D-
External Resistor Connect
●
●
●
●
●
●
●
Recommend to connect 12.1KΩ resistor to
ground for USB 2.0 PHY
TV Out
TVDAC_TVOUT
O
Composite/Chroma Output
●
●
Connect an external 75Ω resistor to ground
of TVDAC as TV terminal impedence
TVDAC_REXT
IO
External Resistor Connection
●
●
●
●
●
●
Recommend to connect 160Ω resistor to
ground of TVDAC
TVDAC_COMP
TVDAC_VREF
O
O
External Capacitor Connection
Connect 0.1uF capacitor to VDD33 of TVDAC
Reference Voltage Output
Connect 0.1uF capacitor to ground of
TVDAC
ADC & Touch Panel
ADC_AIN[3]
I
I
ADC Analog Input Channel 3
ADC Analog Input Channel 2
●
●
●
●
●
●
●
●
●
●
ADC_AIN[2]
●
●
Nuvoton Technology Corp.
http://www.nuvoton.com/
26
Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
ADC_AIN[1]
MIC_IN_M
I
I
I
I
I
I
I
I
ADC Analog Input Channel 1
Microphone Negative Input
ADC Analog Input Channel 0
Microphone Positive Input
Touch Panel YP
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ADC_AIN[0]
MIC_IN_P
ADC_TP_YP
ADC_TP_XP
ADC_TP_XM
ADC_TP_YM
Audio DAC
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Touch Panel XP
Touch Panel XM
Touch Panel YM
ADAC_HPOUT_R
ADAC_HPOUT_L
ADAC_VREF
O
O
O
Audio Headphone Right Channel Output
Audio Headphone Left Channel Output
Audio DAC Reference Voltage Output
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Recommend to connect 1uF capacitor to
ground of Audio DAC
Power/Ground
MVREF
P
Reference Voltage for SDRAM I/F
Useless if SDR SDRAM used.
●
●
●
●
●
●
●
●
●
●
It should be MVDD/2 if DDR/DDR2/LPDDR
SDRAM used
MVREF_GND_SHI
ELDING
G
Ground Shielding for Reference Voltage
●
●
●
●
MVDD18
P
P
G
P
G
P
P
G
P
G
P
SDRAM I/F Power (1.8V)
SDRAM I/F Power (3.3V)
SDRAM I/F Ground (0V)
SDRAM I/F Power (1.8V)
SDRAM I/F Ground (0V)
RTC Core, I/F & 32768Hz Crystal Power
USB 2.0 PHY Power (3.3V)
USB 2.0 PHY Ground (0V)
USB 2.0 PHY Power (1.8V)
USB 2.0 PHY Ground (0V)
TV DAC Power (3.3V)
MVDD33
●
●
●
●
●
●
●
●
●
●
●
●
●
●
MVSS
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
MVDDQ
MVSSQ
RTC_VDD
UD_VDD33
UD_VSS33
UD_VDD18
UD_VSS18
TVDAC_VDD33
●
●
●
●
●
●
●
●
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
I/O
Pin Name
Description
Type
TVDAC_VSS33
ADC_VDD33
ADC_VSS33
ADAC_HPVDD33
ADAC_HPVSS33
ADAC_AVDD33
ADAC_AVSS33
VDD33
G
P
G
P
G
P
G
P
P
G
TV DAC Ground (0V)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ADC Power (3.3V)
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
ADC Ground (0V)
Audio DAC Headphone Driver Power (3.3V)
Audio DAC Headphone Driver Ground (0V)
Audio DAC Power (3.3V)
Audio DAC Ground (0V)
I/O Power (3.3V)
VDD18
Core Logic Power (1.8V)
Ground (0V)
VSS
4.2 Pin Type Description
Type
Description
I
O
Input
Output
OD
IO
Open Drain output
Input / Output
IOD
IOU
IOSU
P
Input with pull-Down / Output
Input with pull-Up / Output
Input with Schmitt trigger & pull-Up/ Output
Power
G
Ground
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5. ELECTRICAL SPECIFICATION
5.1 Absolute Maximum Rating
Parameters
Values
Ambient Temperature
-20 °C ~ 85 °C
-40 °C ~ 125 °C
-0.3V ~ 3.6V
-0.5V ~ 2.5V
-0.5V ~ 4.6V
100mA
Storage Temperature
Voltage On Any Pin
Power Supply Voltage (Core Logic)
Power Supply Voltage (I/O Buffer)
Injection Current (Latch-Up Testing)
Crystal Frequency
2MHz ~ 27MHz
5.2 DC Characteristics (Normal I/O)
Symbol
Parameter
Condition
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
V
VDD33
I/O Buffer Post-Driver Voltage
MVDD33 SDRAM Operation Voltage
Core Logic and I/O 200MHz
3.0
3.3
3.6
V
VDD18
Buffer
Pre-Driver
1.62
1.8
1.98
V
Voltage
DDR Operation
Voltage
100MHz
100MHz
MVDD18
1.7
1.7
1.8
1.8
1.9
1.9
V
V
MVDDQ/ DDR Operation
Voltage
MVDD
RTC_VDD
IRTC_VDD
VIH
RTC Power Supply
RTC Supply Current
Input High Voltage
Input Low Voltage
Threshold Point
-
1.2
-
1.8
-
V
uA
V
RTC_VDD<VDD18
4
-
-
2.0
-0.3
1.45
5.5
0.8
1.74
VIL
V
VT
1.58
V
Schmitt Trigger Low to High
Threshold Point
VT+
VT-
1.44
0.89
1.42
1.06
1.56
0.99
V
V
Schmitt Trigger High to Low
Threshold Point
FCPU = 200MHz,
MCLK = 100MHz,
VDD18 = 1.8V
-
160
-
ICC
Core Power Supply Current
Input Leakage Current
-
mA
uA
IL
-10
10
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Tri-State
Current
Output
Leakage
-
IOZ
-10
10
uA
RPU
RPD
VOL
VOH
Pull-Up Resistor
39
40
-
65
56
-
116
108
0.4
-
kΩ
kΩ
V
Pull-Down Resistor
Output Low Voltage
Output High Voltage
2.4
V
-
Low Level Output 4mA I/O
Current
VOL = 0.4V
VOH = 2.4V
-
-
-
-
IOL
IOH
4.0
5.9
mA
mA
High Level Output 4mA I/O
Current
5.3 Audio DAC Characteristics
Test conditions: RL = 10K / 50pF, BW = 20Hz ~ 20KHz, Freq.= 1KHz, Sample Rate = 48KHz.
Parameter
Operating Voltage
Min
Typ
Max
Unit
3.0
3.3
3.6
V
V
Reference Voltage
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DAC_VDD/2
0.1
-
-
Reference Capacitor
uF
Full Scale output voltage
Maximum Output Power
1.32
Vrms
mW
mW
mW
dBV
dBV
dB
-
52
46
41
-
Maximum Output Power @ 32ohm load
Maximum Output Power @ 16ohm load
L-Channel SNR
-
-
86
85
-64
-64
-63
-63
-62
-62
-
-
-
-
-
-
-
-
R-Channel SNR
L-Channel THD+N
R-Channel THD+N
dB
L-Channel THD+N @ 32ohm load
R-Channel THD+N @ 32ohm load
L-Channel THD+N @ 16ohm load
R-Channel THD+N @ 16ohm load
dB
dB
dB
dB
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.4 ADC Characteristics
Parameter
Min.
Typ.
Max.
Unit
SAR ADC Input Voltage Range
Resolution of ADC
3.0
-
-
-
3.6
10
V
bit
Signal-to-Noise Plus Distortion of ADC
from Line In
-
TBD
-
dB
Integral Non-Linearity of ADC
Differential Non-Linearity of ADC
No Missing Code
-
-
-
-
±2.0
±0.8
10
-
-
-
LSB
LSB
bit
AD Conversion Rate=ADCCLK/16
-
400
KHz
5.5 AC Characteristics (Digital Interface)
5.5.1 Clock Input Characteristics
T
XIN
XIN
T
XINWH
T
XINWL
FXIN = 1 / TXIN
XINDUTY = TXINWH / ( TXINWH + TXINWL
)
Symbol
Parameter
Clock Input Frequency
Clock Input Duty Cycle
Min.
-
Typ.
Max.
Unit
MHz
%
FXIN
12 / 27
50
-
XINDUTY
45
55
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.2 SDRAM Interface
T
MCLK
MCLK
T
MWL
T
MWH
Command Out
MCS_
MRAS_
MCAS_
MWE_
MA
T
MODLY
T
MOH
MBA
MDQS0
MDQS1
T
MDQSH
T
MDQSL
TMDSU
T
MDH
Data Output
MD[15:0]
Symbol
Parameter
Min.
6
Typ.
Max.
12
Unit
ns
TMCLK
TMWL
TSWH
MCLK Clock Cycle Time
MCLK Clock Low Time
MCLK Clock High Time
-
-
-
0.45
0.45
0.55
0.55
TMCLK
TMCLK
ns
Command and Address Output
Delay Time
TMODLY
-
-
-
2
-
Command and Address Output
Hold Time
ns
TMOH
2
TMDQSH
TMDQSL
TMDSU
TMDH
MDQS0/MDQS1 High Time
MDQS0/MDQS1 Low Time
MD to MDQS0/MDQS1 Setup Time
MD to MDQS0/MDQS1 Hold Time
IO reference voltage
0.4
0.4
-
-
-
-
-
0.6
0.6
-
TMCLK
TMCLK
ns
0.6
0.6
-
ns
VREF
0.49
0.51
VDD
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.3 Sensor/Video-In Interface
FSPCLK
T
SWL
T
SWH
SPCLK
T
SISU
T
SIH
SHSYNC
SVSYNC
SFIELD
SPDATA[7:0]
Symbol
FSPCLK
TSWL
Parameter
Min.
-
Typ.
Max.
Unit
MHz
ns
50
-
SPCLK Clock Frequency
SPCLK Clock Low Time
SPCLK Clock High Time
-
-
-
10
10
TSWH
-
ns
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Setup Time
ns
1.0
1.0
TSISU
-
-
-
-
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Hold Time
ns
TSIH
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.4 I2S Interface
F
ABCLK
T
AWL
T
AWH
I2S_BCLK
T
AISU
T
AIH
Input Mode
I2S_DIN
Output Mode
I2S_WS
I2S_DOUT
T
AODLY
T
AOH
Symbol
FABCLK
TAWL
Parameter
Min.
Typ.
Max.
Unit
MHz
ns
I2S_BCLK Clock Frequency
I2S_BCLK Clock Low Time
I2S_BCLK Clock High Time
I2S_DIN Setup Time
-
-
-
-
-
-
16
-
31.25
31.25
10
TAWH
-
ns
TAISU
-
ns
TAIH
I2S_DIN Hold Time
10
-
ns
I2S_DOUT
Time
Output
Delay
ns
TAODLY
TAOH
-
-
-
0.5
-
I2S_DOUT Output Hold Time
0.1
ns
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.5 LCD/Display Interface
SYNC Type LCD
FLPCLK
T
LWL
T
LWH
LPCLK
LHSYNC
LVSYNC
LVDE
LVDATA[15:0]
TLODLY
T
LOH
Symbol
Parameter
Min.
-
Typ.
Max.
Unit
MHz
ns
FLPCLK
TLWL
LPCLK Clock Frequency
LPCLK Clock Low Time
LPCLK Clock High Time
-
-
-
27
-
18.5
18.5
TLWH
-
ns
LHSYNC, LVSYNC, LVDE and
LVDATA Output Delay Time
ns
TLODLY
-
-
-
1.3
-
LHSYNC, LVSYNC, LVDE and
LVDATA Output Hold Time
ns
TLOH
0.67
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
MPU Type LCD
LPCLK (CS_)
TLAS
T
LAH
LVDE (RS)
TLCSS
T
LCSH
T
LWR
80 Mode:
LHSYNC (WR_)
TLDODLY
TLDOH
LVDATA[15:0]
T
LEN
68 Mode:
LVSYNC (EN)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
TLCSS
TLCSH
TLAS
CS_ to WR_ Setup Time
CS_ to WR_ Hold Time
RS to WR_ Setup Time
RS to WR_ Hold Time
2
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
TLAH
TLDODLY
TLDOH
TLWR
LVDATA Output Delay Time
LVDATA Output Hold Time
WR_ Pulse Width
1
1
1
80 Mode
68 Mode
TLEN
EN Pulse Width
Note: PCLK is the period of one APB bus clock.
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.6 SPI Interface
FSPCLK
T
SPWL
T
SPWH
SPI0_CLK
T
SPISU
T
SPIH
Input Mode
SPI0_DI
Output Mode
SPI0_DO
T
SPODLY
TSPOH
Symbol
FSPCLK
TSPWL
Parameter
Min.
-
Typ.
Max.
Unit
MHz
ns
SPI0_CLK Clock Frequency
SPI0_CLK Clock Low Time
SPI0_CLK Clock High Time
SPI0_DI Setup Time
-
-
-
-
-
-
-
25
-
20
20
10
10
-
TSPWH
TSPISU
TSPIH
-
ns
-
ns
SPI0_DI Hold Time
-
ns
TSPODLY
TSPOH
SPI0_DO Output Delay Time
SPI0_DO Output Hold Time
1
-
ns
0.2
ns
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.7 NAND Interface
NCS0_
NCS1_
NALE
NCLE
T
NWL
T
NWH
NWR_
T
NODLY
T
NOH
ND[7:0]
(write)
NRE_
T
NISU
T
NIH
ND[7:0]
(Read)
Symbol
Parameter
Min.
10
10
-
Typ.
Max.
Unit
ns
TNWL
TNWH
TNODLY
TNOH
TNISU
TNIH
Write Pulse Low Width
NWR_ High Hold Time
-
-
-
-
-
-
-
-
ns
ND[7:0] Output Delay Time
ND[7:0] Output Hold Time
2.5
-
ns
10
3.2
1
ns
ND[7:0] Data in Setup Time
ND[7:0] Data in hold time
-
ns
-
ns
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.5.8 SD Card Interface
FSDCLK
TSDWL
TSDWH
SDCLK
T
SDISU
TSDIH
Input Mode
SDCMD,
SDDAT[3:0]
Output Mode
SDCMD,
SDDAT[3:0]
T
SDODLY
TSDOH
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock SDCLK
Clock
FSDCLK
Frequency
Transfer Mode
in
Data
-
-
-
24
MHz
KHz
Clock
Frequency
in
FSDCLK
100
400
Identification Mode
Clock Low Time
Clock High Time
TSDWL
TSDWH
10
10
-
-
-
-
ns
ns
Input SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDISU
TSDIH
Input Setup Time
Input Hold Time
6
2
-
-
-
-
ns
ns
Output SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDODLY
TSDOH
Output Delay Time
Output Hold Time
-
-
-
14
-
ns
ns
2.5
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
5.6 Power-on Sequence
5.7 Thermal characteristics of LQFP-128 Package
Thermal Performance of LQFP-128 under Forced Convection
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
6. ORDERING INFORMATION
PART NO.
PACKAGE TYPE
DESCRIPTION
N32901U1DN LQFP-128, MCP1
Stacked 1Mbit x16 SDR MCP with LCD, CIS and I2S interface.
Stacked 4Mbit x 16 DDR MCP with CIS, SDHC and I2S interface
Stacked 4Mbit x16 DDR MCP with LCD,CIS and I2S interface.
Stacked 16Mbit x16 DDR MCP with LCD, CIS and I2S interface.
Stacked 16Mbit x16 DDR MCP with LCD,CIS interface & TV output.
N32903R1DN
N32903U1DN
N32905U1DN
N32905U2DN
TQFP-64, MCP
LQFP-128, MCP
LQFP-128, MCP
LQFP-128, MCP
6.1
Part Number Definition
6.2
Difference between N32901U1DN, N32903U1DN, N32905U1DN and N32905U2DN
MCPed SDRAM
Type/Capacity
SDR/2MBytes
SDR/2MBytes
DDR/8MBytes
DDR/32MBytes
DDR/32MBytes
Analog Composite TV Output
I2S Interface
N32901U1DN
N32901U2DN
N32903U1DN
N32905U1DN
N32905U2DN
-
V
-
V
-
V
V
-
-
V
1
MCP stands for Multi-Chip Package.
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
7. PACKAGE OUTLINE
7.1
LQFP-128 (14X14X1.4mm body, 0.4mm pitch)
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
7.2 TQFP-64 (10X10X1.0mm body, 0.5mm pitch)
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
7.3 LQFP-64 (10X10X1.4mm body, 0.5mm pitch)
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.063
Max
1.60
A
1
A
2
A
b
c
0.002
0.05
0.15
1.45
0.27
0.20
0.006
0.053 0.055 0.057 1.35
1.40
0.20
0.007
0.004
0.17
0.09
0.008 0.011
0.008
10.00
10.00
0.50
0.393
D
E
e
0.393
0.020
D
H
HE
L
L
y
12.00
12.00
0.472
0.472
0.030
7
0.024
0.039
0.75
7
0.45 0.60
1.00
0.018
0
1
0.10
0.004
3.5
3.5
0
0
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Release Date: May. 2013
Rev. A5.1
N3290X DATASHEET
8. REVISION HISTORY
VERSION
DATE
PAGE
ALL
36
DESCRIPTION
A0
Jul. 25, 2012
Aug. 1, 2012
Initial release.
A1
Add stacked DRAM size into order Information
Add N32901U1DN Information
A2
Aug. 30, 2012
Sept. 17, 2012
ALL
22
Correct the N32905U2DN Pin Diagram
1Mx16 MVDD and MVDDQ are changed from 3.3V to
A2.1
1.8V for consistence with N32905 and N32903
Extend Operation Temperature Range
Add Parts Feature Difference Table
Add Part Number Definition
A3
Oct. 15, 2012
Oct. 26, 2012
23,35
35
A3.1
Add CCIR Still Image and Video Recommanded
Resolutions.
Add LCD Display for Still Image and Video
Recommanded Resolutions.
A3.2
Nov. 8, 2012
6,7,8,9
Modify One SPI H/W Engine to Support Two SPI Devices
by Two Chip Selection Signals when SPI0 is in Master
Mode. For LQFP128 package, only SPI0 is active.
Add USB 1.1 Host One H/W Controller, Three Different
Pin Locations Information.
A3.3
A3.4
A4.0
Nov. 10, 2012
Jan. 21, 2013
Mar. 15, 2013
35
4, 5, 10, 23
ALL
Remove Adobe Flash Feature from Comparision Table.
Update the AC characteristics.
Add N32903R1DN
Add N32901R1DN Information.
A5.0
A5.1
May. 1, 2013
May. 3,2013
ALL
28
Add N32901U2DN Information.
Add SDRAM and DDR Operation Voltage Spec
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or
failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are
deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control
instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems
designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications
intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton
as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred
by Nuvoton.
Nuvoton Technology Corp.
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Release Date: May. 2013
Rev. A5.1
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