N682387MG [NUVOTON]
Dual Programmable Extended Codec/SLCC SLFC;
| 型号： | N682387MG |
| 厂家： | 
NUVOTON |
| 描述： | Dual Programmable Extended Codec/SLCC SLFC 电信 电信集成电路 |
| 文件： | 总160页 (文件大小：2020K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
1. DESCRIPTION
The N682386/87, implements a dual channel FXS telephone line interface optimized for short loop applications. It
integrates SLCC (Subscriber Line Control Circuit) functionality with a dual programmable CODEC and a dual DC/DC
controller. The SLCC supports internal ringing up to 90 VPK (5 REN at 4k ft) ideal for Customer Premise Equipment
(CPE). The CODEC can be configured for μ-law, A-law or 16-bit linear PCM encoding. It also supports a
comprehensive set of signaling capabilities required to supervise and control the telephone lines. These include tone
generation, ring tones, DTMF detection/ generation as well as FSK generation. An on-chip Pulse Width Modulation
(PWM) driver allows control of an inductor based DC/DC converter. Programmable impedance and trans-hybrid
balancing allow for worldwide deployment.
¡
¡
Wideband and Narrowband codec (N682387)
2. FEATURES
Optional integrated (N681622) or discrete
Subscriber Line Feed Circuit
¡
¡
Complete BORSCHT functions
APPLICATIONS
Internal balanced and unbalanced ringing up to 90
VPK (5 REN up to 4k ft)
¡
¡
Integrated Power Management Options
¡
¡
¡
¡
¡
¡
¡
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Residential VoIP Gateways / Routers/ IP-PBX
Integrated DC/DC controller regulates battery
voltage to minimize power dissipation in all
operating modes
Fiber to the Premise/Home (FTTP/H)
Wireless Local Loop
Optical Network Terminals (ONT)
Analog Telephone Adapter (ATA)
Voice enabled DSL/Cable Modems
Integrated Access Devices
Set Top Boxes
Programmable external battery switching
Programmable linefeed characteristics
Ringing Frequency, Amplitude, and Cadence
Trapezoidal and Sinusoidal waveforms
Two wire AC impedance, and trans-hybrid
balance
Ordering Information
Constant Current feed (20 to 41) mA
Ring Trip and Loop Closure Thresholds
Ground Key Detection
Temp
Part Number
Package
Material
Package
64-TQFP
Range (oC)
¡
¡
Programmable signal generation and detection
N682386MG
-40 to 85
Pb-Free
DTMF generation/ detection and Tone
generation
N682387MG
N682386YG
-40 to 85
Frequency Shift Keying (FSK) Enhanced Caller
ID generation (Type I and Type II)
64-QFN..
20-QFN
Pb-Free
Pb-Free
N682387YG
Loop test and diagnostics support
N681622YG
-40 to 85
Integrated loopback modes
Real-time linefeed monitoring
On-chip temperature sensor
Line Card Diagnostics Support
U.S. Patent # 7260212 B1
! WARNING !
HIGH VOLTAGE WARNING USE EXTREME CAUTION
¡
Digital interfaces
PCM: G.711 μ-Law, A-Law and 16-bit linear
GCI and SPI bus
High voltage sources could cause serious injury or
death if not used in accordance with design and/or user
specifications, if they are used by untrained or
unqualified personnel. Before testing Nuvoton’s products
read and understand all instructions, and safety
procedures as in industry standard safe practices.
Programmable audio path gains
¡
¡
Both PCM Master and Slave modes supported
On-chip PLL for flexible clocking options including
1.0 MHz and 2.0 MHz BCLK operation
¡
¡
Operating voltage: 3.3V
Narrowband Codec (N682386)
Revision 1.3
Page 1 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
3. PIN CONFIGURATION
Figure 1: Pin Configuration
Figure 2: N6816Subscriber Lie Feed Circut (SLFC) Pin Configuration
*Note: Heat sink metal paddle under device soulbe connected to VBAT plane on PCB for heat dissipation
as it is internally connected to Vbat pin.
Revision 1.3
Page 2 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
4. PIN DESCRIPTION
4.1. N682386/87 Pin Description
Pin
Type
Pin Name Pin No.
Functionality
A/D
VDD2
RIP2
1
2
Line-driver 3.3 V supply
A
A
A
A
A
A
A
A
A
A
A
D
A
P2
I/O2
O2
O2
G2
O2
I2
Positive RING Driver current source & Voltage sense
Negative RING Driver current source
Positive TIP Driver Base Voltage Control
Line-driver ground supply
RIN2
TVB2
GND2
RVB2
RAC2
TAC2
CR2
3
4
5
6
Positive RING Driver Base Voltage Control
RING Voice Band Input
7
8
TIP Voice Band Input
I2
9
External Capacitor RING
I/O2
I/O2
G4
P4
CT2
10
11
12
External Capacitor TIP
GND4
VDD4
Line-driver ground supply
Line-driver 3.3 V supply
I/O2
VREF2
13
Precision Reference Voltage
IREF
DCL2
DCH2
14
15
16
17
Current Reference
A
A
A
D
I/O
I2
DC/DC Converter Current Sense LOWER input Voltage
DC/DC Converter Current Sense HIGHER input Voltage
Interrupt. Mask able interrupt. Open drain output for wired-or operation
I2
O
INT
CS
Chip Select. When inactive, SCLK and SDI are ignored and SDO is high
impedance. When active, serial port is operational
18
D
I
SCLK
SDI
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Serial port bit clock. Controls serial data on SDO and latches data on SDI
Serial port data in. Serial port control data
Serial port data out. Serial port control data
DC/DC converter Control for external NPN BJT
DC/DC Converter Control for external PNP BJT
Logic I/O ground supply
D
D
D
D
D
D
D
D
D
D
D
D
D
D
I
I
SDO
O
DCN2
DCP2
GND5
VDD5
DCN1
DCP1
PCMT
FS
O2
O2
G5
P5
O1
O1
O
3.3 V Logic I/O supply
DC/DC converter Control for external NPN BJT
DC/DC Converter Control for external PNP BJT
Serial PCM Transmit data
8 or 16 kHz Frame Sync
I/O
I
BCLK
PCMR
DSY
PCM Bit Clock. Also used as internal PLL reference clock
Serial PCM Receive data
I
SPI Daisy Chain Enable
I
Reset. Active Low. Hardware reset used to place all control registers in
default state.
33
D
I
RESET
DCH1
DCL1
34
35
36
DC/DC Converter Current Sense Higher input Voltage
DC/DC Converter Current Sense Lower input Voltage
Half Supply Reference Voltage to VDD
A
A
A
I1
I1
P
VREF1
Revision 1.3
Page 3 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Pin
Type
Pin Name Pin No.
Functionality
A/D
A
3.3 V Analog AC path and reference Supply Voltage
VDD3
37
P3
GND3
CT1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Analog AC path and reference Supply ground
External Capacitor TIP
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
G3
I/O
I/O
I1
CR1
External Capacitor RING
TAC1
RAC1
RVB1
GND1
TVB1
RIN1
RIP1
TIP Voice Band Input
RING Voice Band Input
I1
Positive RING Driver Base Voltage Control
Line-driver ground supply
O1
G1
O1
O1
I/O1
P1
I/O1
O1
I1
Positive TIP Driver Base Voltage Control
Negative RING Driver current source
Positive RING Driver current source & Voltage sense
Line-driver 3.3 V supply
VDD1
TPP1
TIN1
Positive TIP Driver current source & Voltage sense
Negative TIP Driver current source
RVE1
BAT1
TVE1
SDB1
SCM1
SDA1
SDA2
SCM2
SDB2
TVE2
BAT2
RVE2
TIN2
RING line-driver emitter voltage sense
Battery voltage monitoring
I1
TIP line-driver emitter voltage sense
I1
Subscriber Loop Differential sense signal B from linefeed circuit
Subscriber Common Mode sense signal from linefeed circuit
Subscriber Loop Differential sense signal A from linefeed circuit
Subscriber Loop Differential sense signal A from linefeed circuit
Subscriber Common Mode sense signal from linefeed circuit
Subscriber Loop Differential sense signal B from linefeed circuit
TIP line-driver emitter voltage sense
I1
I1
I1
I2
I2
I2
I2
Battery voltage monitoring
I2
RING line-driver emitter voltage sense
Negative TIP Driver current source
I2
O2
I/O3
TPP2
Positive TIP Driver current source & Voltage sense
Table 1: Pin Description
A
D
G
Analog
Digital
O
I
Output
Input
Ground
P
Power
Revision 1.3
Page 4 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
4.2. N681622 Pin Description
Pin Name
Pin No.
1
Functionality
Ring Driver Pull up Current from 34.8 Ohm resistor
Tip Pull-Up Driver control voltage
Tip Driver Pull up Current from 34.8 Ohm resistor
Ring Pull-Up Driver control voltage
Supply ground (0V)
Type
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
HV
Pin Type
RIP
TVB
TPP
RVB
GND
VDD
SDB
SDA
TIN
I/O
I
2
3
I/O
I
4
5
G
P
6
3.3V Supply
7
Subscriber differential signal B
Subscriber differential signal A
Tip DC Pull-Down current
Ring DC Pull-Down current
Subscriber differential Ring input
Not connected
O
O
I
8
9
RIN
10
11
12
13
14
15
16
17
18
19
20
I
SDR
NC
I/O
NC
Not connected
NC
Not connected
VBAT
RING
NC
Battery Supply Voltage
HV
HV
P
Ring terminal
O
Not connected
TIP
Tip terminal
HV
HV
O
NC
Not connected
SDT
Subscriber differential Tip input
I/O
*Note: Heat sink metal paddle under device should be connected to VBAT plane for heat dissipation as it is internally
connected to Vbat as shown in Figure 2.
Table 2: N681622 Pin Description
LV
HV
G
Low Voltage
High Voltage
Ground
O
I
Output
Input
P
Power
Revision 1.3
Page 5 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
5. BLOCK DIAGRAM
Figure 3: Block Diagram
Revision 1.3
Page 6 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
6. TABLE OF CONTENTS
1.
DESCRIPTION...........................................................................................................................................1
FEATURES ................................................................................................................................................1
PIN CONFIGURATION ..............................................................................................................................2
PIN DESCRIPTION....................................................................................................................................3
N682386/87 PIN DESCRIPTION ...............................................................................................................3
N681622 PIN DESCRIPTION ....................................................................................................................5
BLOCK DIAGRAM......................................................................................................................................6
TABLE OF CONTENTS .............................................................................................................................7
LIST OF FIGURES...................................................................................................................................14
LIST OF TABLES .....................................................................................................................................16
ABSOLUTE MAXIMUM RATINGS ...........................................................................................................17
DUAL PROGRAMMABLE EXTENDED CODEC/SLCC (N682386/87).....................................................17
N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC) ...........................................................................17
OPERATING CONDITIONS.....................................................................................................................18
SINGLE PROGRAMMABLE EXTENDED CODEC/SLCC (N682386/87).................................................18
SUBSCRIBER LINE FEED CIRCUIT (N681622) .....................................................................................18
ELECTRICAL CHARACTERISTICS.........................................................................................................19
GENERAL PARAMETERS (N682386/87)................................................................................................19
SUPPLY PARAMETERS DISCRETE SOLUTION (N682386/87 AND DISCRETE LINE DRIVER) .........19
SUPPLY PARAMETERS SLFC SOLUTION (N682386/87 AND N681622) .............................................20
MONITORING A/D PARAMETERS..........................................................................................................21
ANALOG SIGNAL LEVEL AND GAIN PARAMETERS ............................................................................21
2-WIRE TO 4-WIRE CONVERSION PARAMETERS...............................................................................22
2-WIRE PARAMETERS ...........................................................................................................................22
LINEFEED CHARACTERISTICS .............................................................................................................22
ANALOG DISTORTION AND NOISE PARAMETERS .............................................................................23
FUNCTIONAL DESCRIPTION.................................................................................................................24
BORSCHT FUNCTIONALITY ..................................................................................................................25
BATTERY FEED ......................................................................................................................................25
LINEFEED STATES OF OPERATION.....................................................................................................27
2.
3.
4.
4.1.
4.2.
5.
6.
7.
8.
9.
9.1.
9.2.
10.
10.1.
10.2.
11.
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
11.8.
11.9.
12.
12.1.
12.1.1.
12.1.1.1.
12.1.1.1.1. OPEN STATE...........................................................................................................................................27
12.1.1.1.2. ACTIVE, IDLE AND ON-HOOK TRANSMISSION STATES.....................................................................27
12.1.1.1.3. TIP OPEN STATE ....................................................................................................................................27
12.1.1.1.4. RING OPEN STATE.................................................................................................................................28
12.1.1.1.5. RINGING STATE......................................................................................................................................28
12.1.1.1.6. CALIBRATION STATE.............................................................................................................................28
Revision 1.3
Page 7 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.1.1.2.
12.1.1.3.
OPERATION MODES ..............................................................................................................................28
AUTOMATIC TRANSITIONS ...................................................................................................................28
12.1.1.3.1. POWER ALARM AUTOMATIC REACT ...................................................................................................28
12.1.1.3.2. SETTING RING AUTOMATIC..................................................................................................................28
12.1.1.3.3. SETTING LOOP CLOSURE DETECT AUTOMATIC REACT ..................................................................29
12.1.1.4.
POLARITY REVERSAL............................................................................................................................31
12.1.1.4.1. HARD POLARITY REVERSAL ................................................................................................................31
12.1.1.4.2. SOFT POLARITY REVERSAL.................................................................................................................31
12.1.1.5.
12.1.2.
WINK FUNCTION POLARITY REVERSAL..............................................................................................32
OVER-VOLTAGE PROTECTION.............................................................................................................32
THERMAL OVERLOAD ...........................................................................................................................33
TEMPERATURE MONITOR ....................................................................................................................34
RINGING..................................................................................................................................................35
TONE GENERATION...............................................................................................................................35
RING SIGNAL GENERATION..................................................................................................................38
12.1.2.1.
12.1.2.2.
12.1.3.
12.1.3.1.
12.1.3.2.
12.1.3.2.1. SINUSOIDAL RINGING ...........................................................................................................................40
12.1.3.2.2. TRAPEZOIDAL RINGING ........................................................................................................................41
12.1.3.2.3. RINGING DC OFFSET AND COMMON MODE BIAS..............................................................................42
12.1.3.2.4. LINEFEED CONSIDERATIONS DURING RINGING ...............................................................................43
12.1.3.3.
12.1.3.4.
12.1.4.
INTERNAL UNBALANCED RINGING......................................................................................................43
RING TRIP DETECTION..........................................................................................................................44
SUPERVISION (SIGNALING)..................................................................................................................46
LOOP CLOSURE DETECTION................................................................................................................46
GROUND KEY DETECTION....................................................................................................................48
CALLER ID AND FSK GENERATION......................................................................................................49
DTMF GENERATOR................................................................................................................................50
DTMF DETECTION..................................................................................................................................52
CODEC ....................................................................................................................................................53
HYBRID....................................................................................................................................................53
AC PATH..................................................................................................................................................53
12.1.4.1.
12.1.4.2.
12.1.4.3.
12.1.4.4.
12.1.4.5.
12.1.5.
12.1.6.
12.1.6.1.
12.1.6.1.1. NARROWBAND TRANSMIT PATH .........................................................................................................53
12.1.6.1.2. NARROWBAND RECEIVE PATH............................................................................................................53
12.1.6.1.3. ANALOG TRANSHYBRID BALANCING ..................................................................................................54
12.1.6.1.4. IMPEDANCE MATCHING........................................................................................................................55
12.1.6.1.1. DAC/ADC AUTOMUTE ............................................................................................................................56
12.1.7.
TESTING..................................................................................................................................................57
LOOP BACK TESTS ................................................................................................................................57
DIAGNOSTICS SUPPORT ......................................................................................................................58
12.1.7.1.
12.1.7.2.
Revision 1.3
Page 8 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.1.8.
POWER INTERFACE...............................................................................................................................58
DC/DC CONVERSION (INDUCTOR).......................................................................................................59
EXTERNAL BATTERY SWITCHING........................................................................................................61
DIGITAL INTERFACE ..............................................................................................................................62
CLOCK GENERATION ............................................................................................................................62
PCM INTERFACE ....................................................................................................................................63
WIDEBAND AND NARROWBAND OPERATION ....................................................................................64
TOGGLING BETWEEN WIDEBAND AND NARROWBAND....................................................................65
PCM INTERFACE IN WIDEBAND OPERATION .....................................................................................65
12.1.8.1.
12.1.8.2.
12.2.
12.2.1.
12.2.2.
12.2.2.1.
12.2.2.2.
12.2.2.3.
12.2.2.3.1. PCM INTERFACE 8KHZ FRAME SYNC..................................................................................................65
12.2.2.3.2. PCM INTERFACE 16KHZ FRAME SYNC................................................................................................66
12.2.2.4.
12.2.3.
12.2.4.
12.2.5.
12.2.6.
12.2.7.
12.2.7.1.
12.3.
PLL & PRESCALER IN WIDEBAND OPERATION..................................................................................66
SERIAL PERIPHERAL INTERFACE (SPI)...............................................................................................67
READ/WRITE SEQUENCE (8-BIT OR 16-BIT)........................................................................................68
SPI DAISY CHAIN....................................................................................................................................70
SPI BURST MODE...................................................................................................................................71
SPECIAL READ SEQUENCE FOR 12-BIT WIDE REGISTER ................................................................72
12-BIT READ SEQUENCE.......................................................................................................................72
POWER-ON RESET ................................................................................................................................73
INTERRUPT HANDLING .........................................................................................................................74
GENERAL DESCRIPTION FOR N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC) .......................75
FUNCTIONAL DESCRIPTION FOR N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC) .................75
REGISTER DESCRIPTION......................................................................................................................76
PCM CONTROL REGISTERS .................................................................................................................81
PCM CONTROL REGISTER....................................................................................................................81
RECEIVE/TRANSMIT TIMESLOT (WIDEBAND AND NARROWBAND) .................................................81
PLL STATUS REGISTER.........................................................................................................................82
PCM FREQUENCY SETTING REGISTER ..............................................................................................83
SILICON REVISION ID REGISTER (READ ONLY) .................................................................................84
DEVICE VERSION ID REGISTER (READ ONLY)...................................................................................84
TIMESLOT (WIDEBAND).........................................................................................................................84
FSK REGISTERS.....................................................................................................................................85
FSK CONTROL REGISTER.....................................................................................................................85
FSK TRANSMIT REGISTER....................................................................................................................85
FSK STATUS REGISTER (READ ONLY)................................................................................................86
FSK LCR REGISTER...............................................................................................................................86
FSK TCR REGISTER...............................................................................................................................87
DIAGNOSTIC REGISTERS .....................................................................................................................88
12.4.
13.
13.1.
14.
14.1.
14.1.1.
14.1.2.
14.1.3.
14.1.4.
14.1.5.
14.1.6.
14.1.7.
14.2.
14.2.1.
14.2.2.
14.2.3.
14.2.4.
14.2.5.
14.3.
Revision 1.3
Page 9 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.3.1.
14.3.2.
14.3.3.
14.3.4.
14.3.5.
14.3.6.
14.4.
DIAGNOSTIC CONTROL 0......................................................................................................................88
DIAGNOSTIC CONTROL 1......................................................................................................................88
DIAGNOSTIC CONTROL 2, 3, 4, AND 5 .................................................................................................89
DIAGNOSTIC CONTROL 6 AND 7 (READ ONLY) ..................................................................................90
DIAGNOSTIC CONTROL 8 (READ ONLY)..............................................................................................91
DIAGNOSTIC FIFO 0 AND FIFO1 (READ ONLY) ...................................................................................91
SYSTEM REGISTERS.............................................................................................................................92
PCM HPF (HIGH PASS FILTER) .............................................................................................................92
LOOP BACK CONTROL REGISTER.......................................................................................................92
POWER ON .............................................................................................................................................93
LINEFEED TRIM ......................................................................................................................................94
INTERRUPT REGISTERS .......................................................................................................................95
INTERRUPT VECTOR LOW (READ ONLY)............................................................................................95
INTERRUPT STATUS REGISTER 1........................................................................................................95
INTERRUPT ENABLE REGISTER 1........................................................................................................96
INTERRUPT STATUS REGISTER 2........................................................................................................96
INTERRUPT ENABLE REGISTER 2........................................................................................................97
INTERRUPT STATUS REGISTER 3........................................................................................................97
INTERRUPT ENABLE REGISTER 3........................................................................................................98
DTMF DETECTION REGISTER...............................................................................................................99
DTMF CONTROL 1..................................................................................................................................99
DTMF CONTROL 2................................................................................................................................100
DTMF STATUS (READ ONLY) ..............................................................................................................101
DTMF THRESHOLD ..............................................................................................................................101
DTMF PRESENT DETECT TIME...........................................................................................................101
DTMF ABSENT DETECT TIME .............................................................................................................102
DTMF ACCEPT TIME ............................................................................................................................102
DTMF RECEIVE DATA STATUS ...........................................................................................................103
DTMF ROW FREQUENCY ....................................................................................................................103
14/15 DTMF COLUMN FREQUENCY....................................................................................................104
LINE REGISTERS..................................................................................................................................105
AC PATH GAIN......................................................................................................................................105
HYBRID BALANCE ................................................................................................................................105
COMMON RINGING BIAS ADJUST DURING RINGING......................................................................106
LINE AUTOMATIC MANUAL CONTROL...............................................................................................106
LINEFEED STATUS...............................................................................................................................107
LOOP CURRENT LIMIT.........................................................................................................................107
RING TRIP DETECT STATUS/ LOOP CLOSURE STATUS..................................................................108
14.4.1.
14.4.2.
14.4.3.
14.4.4.
14.5.
14.5.1.
14.5.2.
14.5.3.
14.5.4.
14.5.5.
14.5.6.
14.5.7.
14.6.
14.6.1.
14.6.2.
14.6.3.
14.6.4.
14.6.5.
14.6.6.
14.6.7.
14.6.8.
14.6.9.
14.6.10.
14.7.
14.7.1.
14.7.2.
14.7.3.
14.7.4.
14.7.5.
14.7.6.
14.7.7.
Revision 1.3
Page 10 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.8.
14.7.9.
14.7.10.
14.7.11.
14.7.12.
14.7.13.
14.7.14.
14.7.15.
14.7.16.
14.7.17.
14.7.18.
14.7.19.
14.7.20.
14.7.21.
14.8.
LOOP CLOSURE DEBOUNCE..............................................................................................................109
RING TRIP DEBOUNCE INTERVAL......................................................................................................109
PWM PERIOD........................................................................................................................................109
DC/DC CONTROLLER CONTROL........................................................................................................110
ON-HOOK VOLTAGE ............................................................................................................................110
GROUND MARGIN VOLTAGE ..............................................................................................................111
HIGH BATTERY VOLTAGE...................................................................................................................111
LOW BATTERY VOLTAGE....................................................................................................................111
LOOP CLOSURE DETECT/RING TRIP DETECT COEFFICIENT.........................................................112
LOOP CLOSURE DETECT THRESHOLD WITHOUT / WITH HYSTERESIS .......................................112
RING TRIP DETECT THRESHOLD.......................................................................................................113
OFFSET VOLTAGE ...............................................................................................................................113
DC/DC TIME ON ....................................................................................................................................113
AUTOMUTE FUNCTION........................................................................................................................114
GROUND KEY DETECTION..................................................................................................................115
LINEFEED CONTROL ...........................................................................................................................115
GROUND KEY DETECT HIGH/LOW THRESHOLD..............................................................................115
GROUND KEY DETECT DEBOUNCE TIME .........................................................................................116
GROUND KEY DETECT FILTER COEFFICIENT LOW/ HIGH..............................................................116
DC RING TRIP DEBOUNCE FILTER COEFFICIENT LOW...................................................................116
DC RING TRIP CURRENT THRESHOLD..............................................................................................117
DC RING TRIP DEBOUNCE TIME ........................................................................................................117
EXTERNAL BATTERY SWITCH OUTPUT CONFIGURATION 1 ..........................................................117
DC/DC HEAVY CURRENT CONVERTER.............................................................................................118
DC/DC TARGET VOLTAGE...................................................................................................................118
MONITORING REGISTERS ..................................................................................................................119
MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE...........................................................119
MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE...........................................................119
LINE CONTROL REGISTERS ...............................................................................................................120
VOLTAGE REGISTERS.........................................................................................................................120
14.8.1.
14.8.2.
14.8.3.
14.8.4.
14.8.5.
14.8.6.
14.8.7.
14.8.8.
14.8.9.
14.8.10.
14.9.
14.9.1.
14.9.2.
14.10.
14.10.1.
14.10.1.1. BATTERY VOLTAGE SENSE (READ ONLY)........................................................................................120
14.10.1.2. TIP/RING TRANSISTOR 3 EMITTER VOLTAGE SENSE (READ ONLY) .............................................120
14.10.1.3. TIP/RING TRANSISTOR 3 EMITTER VOLTAGE SENSE (READ ONLY) .............................................120
14.11.
TRANSISTOR CURRENT REGISTERS ................................................................................................121
TIP/RING TRANSISTOR 1/2/3 CURRENT SENSE (READ ONLY) .......................................................121
LOOP SUPERVISION............................................................................................................................122
LONGITUDINAL CURRENT (READ ONLY) ..........................................................................................122
LOOP VOLTAGE SENSE (READ ONLY) ..............................................................................................122
14.11.1.
14.12.
14.12.1.
14.12.2.
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Dual Programmable Extended Codec/SLCC + SLFC
14.12.3.
14.12.4.
14.12.5.
14.12.6.
14.12.7.
14.12.8.
14.12.9.
TIP, RING, AND LOOP CURRENT (READ ONLY)................................................................................123
POLARITY..............................................................................................................................................123
COMMON MODE VOLTAGE.................................................................................................................124
TIP EMITTER VOLTAGE FOR TRANSISTORS QT1 SENSE (READ ONLY) .......................................124
TIP VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) ..........................................................124
RING EMITTER VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY) ......................................125
RING VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY).......................................................125
14.12.10. TEMPERATURE SENSE (READ ONLY) ...............................................................................................125
14.12.11. BAND GAP VOLTAGES.........................................................................................................................125
14.12.12. PEAK TO PEAK LOOP VOLTAGE.........................................................................................................126
14.12.13. PEAK TO PEAK LOOP CURRENT (READ ONLY)................................................................................126
14.13.
POWER ALARM LPF POLE REGISTERS.............................................................................................127
POWER ALARM COUNTER (READ ONLY)..........................................................................................127
POWER ALARM LOW PASS FILTER POLE FOR TRANSISTORS 1/2/3 ............................................127
POWER ALARM THRESHOLD FOR TRANSISTOR 1-3.......................................................................128
IMPEDANCE MATCHING 1/2................................................................................................................128
TEMPERATURE ALARM THRESHOLD................................................................................................129
LOOP CLOSURE MASK COUNT ..........................................................................................................129
COARSE CALIBRATION INTERNAL RESISTOR .................................................................................129
OSCILLATOR 2 RINGING PHASE DELAY............................................................................................129
CALIBRATION .......................................................................................................................................130
DC OFFSET REGISTERS .....................................................................................................................131
DC OFFSET (RING, TIP, AND VBAT) ...................................................................................................131
PWM COUNT.........................................................................................................................................131
TONE GENERATION REGISTERS .......................................................................................................132
OSCILLATOR CONTROL ......................................................................................................................132
RING CONTROL....................................................................................................................................132
OSCILLATOR 1 AND 2 INITIAL CONDITION LOW/HIGH.....................................................................132
OSCILLATOR 1 AND 2 COEFFICIENT LOW/HIGH ..............................................................................133
OSCILLATOR 1 AND 2 ACTIVE/ INACTIVE TIME LOW/HIGH .............................................................133
GENERAL TONE GENERATION...........................................................................................................134
RING OFFSET .......................................................................................................................................134
ADC/DAC DIGITAL GAIN.......................................................................................................................134
PWM DC/DC FINE TUNING ..................................................................................................................135
PWM DC/DC FINE TUNING SKIP PERIOD...........................................................................................135
PWM DC/DC FINE TUNING ..................................................................................................................136
IMPEDANCE MATCH REGISTER.........................................................................................................137
14.13.1.
14.13.2.
14.13.3.
14.14.
14.14.1.
14.14.2.
14.14.3.
14.14.4.
14.15.
14.16.
14.16.1.
14.16.2.
14.17.
14.17.1.
14.17.2.
14.17.3.
14.17.4.
14.18.
14.19.
14.19.1.
14.19.2.
14.19.3.
14.19.4.
14.19.5.
14.19.6.
14.19.6.1. IMPEDENCE MATCHING COEFFICIENT RAM ....................................................................................137
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Dual Programmable Extended Codec/SLCC + SLFC
14.19.6.2. IMPEDANCE MATCHING DELAY COUNT............................................................................................137
14.19.6.3. IMPEDANCE MATCHING COEFFICIENT RAM CONTROL..................................................................137
14.19.6.4. RESERVED REGISTERS......................................................................................................................138
14.19.6.5. FILTER BYPASS....................................................................................................................................138
15.
TIMING DIAGRAM .................................................................................................................................139
PCM TIMING DIAGRAM FOR NON-GCI ...............................................................................................139
PCM TIMING DIAGRAM FOR GCI ........................................................................................................140
SPI TIMING DIAGRAM ..........................................................................................................................142
DIGITAL I/O............................................................................................................................................148
µ-LAW ENCODE DECODE CHARACTERISTICS.................................................................................148
A-LAW ENCODE DECODE CHARACTERISTICS.................................................................................149
µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE......................................................................149
µ-LAW / A-LAW CODES FOR 0DBM0 OUTPUT (DIGITAL MILLIWATT)..............................................150
16-BIT LINEAR PCM CODES FOR ZERO AND FULL SCALE..............................................................150
16-BIT LINEAR PCM CODES FOR 1 KHZ DIGITAL MILLIWATT..........................................................150
TYPICAL APPLICATION CIRCUITS......................................................................................................151
N682386/7..............................................................................................................................................151
LINE DRIVER.........................................................................................................................................152
N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC) FOR CHANNEL 1............................................152
DISCRETE LINE FEED CIRCUIT FOR CHANNEL 1.............................................................................153
CHANNEL 1 DC-DC...............................................................................................................................154
TRIPLE BATTERY SWITCH APPLICATION..........................................................................................155
PACKAGE SPECIFICATION..................................................................................................................156
TQFP64L (10X10X1.4MM FOOTPRINT 2.0MM) ...................................................................................156
QFN 64L 9X9 MM^2, THICKNESS :1.0 MM (PUNCH TYPE) ................................................................157
QFN 20L 4X4 MM2, PITCH:0.50 MM......................................................................................................158
ORDERING INFORMATION..................................................................................................................159
VERSION HISTORY ..............................................................................................................................160
15.1.
15.2.
15.3.
16.
16.1.1.
16.2.
16.3.
16.3.1.
16.4.
16.5.
17.
17.1.
17.2.
17.2.1.
17.2.2.
17.3.
17.4.
18.
18.1.
18.2.
18.3.
19.
20.
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
7. LIST OF FIGURES
Figure 1: Pin Configuration ............................................................................................................................................2
Figure 2: N681622 Subscriber Line Feed Circuit (SLFC) Pin Configuration ..................................................................2
Figure 3: Block Diagram.................................................................................................................................................6
Figure 4: AC signal Path ..............................................................................................................................................24
Figure 5: DC Feed Regions .........................................................................................................................................25
Figure 6: Line Loop Control..........................................................................................................................................26
Figure 7: Example State Diagram ................................................................................................................................29
Figure 8: Block Diagram Oscillator 1............................................................................................................................37
Figure 9: Zero Crossing for Tone Generation ..............................................................................................................38
Figure 10: Trapezoidal Ringing ....................................................................................................................................41
Figure 11: Positive DC offset for Trapezoidal Ringing..................................................................................................42
Figure 12: Programming VCMR voltage for Trapezoidal Ringing ...................................................................................42
Figure 13: Unbalanced Ringing on TIP ........................................................................................................................43
Figure 14: RING Trip Detection Mechanism ................................................................................................................44
Figure 15: Loop Closure Detector Block Diagram........................................................................................................46
Figure 16: Ground Key Detection Circuitry...................................................................................................................48
Figure 17: The Architecture of Linear FSK Waveform Generator.................................................................................49
Figure 18: DTMF Detector - Functional Block Diagram................................................................................................52
Figure 19: Characteristic Line Impedance....................................................................................................................55
Figure 20: Diagnostics Support Block Diagram............................................................................................................58
Figure 21: Voltage Tracking in Forward Active State ...................................................................................................60
Figure 22: Dynamic Battery Target ..............................................................................................................................60
Figure 23: Three Voltage External Battery switching ...................................................................................................61
Figure 24: Two Battery Supply Control Circuit .............................................................................................................61
Figure 25: Wideband 8kHz Frame Sync PCM interface...............................................................................................65
Figure 26: Wideband 16kHz Frame Sync PCM interface.............................................................................................66
Figure 27: Register write operation through a 8-bit SPI port ........................................................................................69
Figure 28: Register read operation through a 8-bit SPI port.........................................................................................69
Figure 29: Register write operation through a 16-bit SPI port ......................................................................................69
Figure 30: Register read operation through a 16-bit SPI port.......................................................................................69
Figure 31: Three Chip Daisy Chain connection............................................................................................................70
Figure 32: Device/Register Address for Three Device Daisy Chain application...........................................................70
Figure 33: DATA for Three Device Daisy Chain application.........................................................................................71
Figure 34: Burst mode operation (BST=1) ...................................................................................................................71
Figure 35: SPI 12-bits Read sequence ........................................................................................................................73
Figure 36: N681622 Equivalent Internal diagram.........................................................................................................75
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Dual Programmable Extended Codec/SLCC + SLFC
Figure 37: PCM Timing for Non-GCI..........................................................................................................................139
Figure 38: GCI PCM Timing.......................................................................................................................................140
Figure 39: SPI Timing (Non-Daisy Chain Mode) ........................................................................................................142
Figure 40: In-band Transmit Frequency Response....................................................................................................143
Figure 41: In-band Receive Frequency Response.....................................................................................................143
Figure 42: Transmit Group Delay Distortion...............................................................................................................144
Figure 43: Receive Group Delay Distortion................................................................................................................144
Figure 44: 2-Wire to PCM Signal to Distortion Mask (A-Law) ...................................................................................145
Figure 45: 2-Wire to PCM Signal to Distortion Mask (µ-Law)....................................................................................145
Figure 46: Wideband In-band Transmit Frequency Response...................................................................................146
Figure 47: Wideband Transmit Group Delay Distortion..............................................................................................146
Figure 48: Wideband Receive Group Delay Distortion...............................................................................................147
Figure 49: Typical Application Circuit for N682386/7 ................................................................................................151
Figure 50: N681622 Subscriber Line Feed Circuit (SLFC) for Channel 1 ..................................................................152
Figure 51: Line-driver circuit for Channel1 ................................................................................................................153
Figure 52: Inductor based circuit for Channel 1.........................................................................................................154
Figure 53: Triple Battery based Switch 1 ..................................................................................................................155
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
8. LIST OF TABLES
Table 1: Pin Description.................................................................................................................................................4
Table 2: N681622 Pin Description..................................................................................................................................5
Table 3: Programmable Ranges for DC Line Feed ......................................................................................................25
Table 4: Linefeed States ..............................................................................................................................................27
Table 5: Operation Modes............................................................................................................................................28
Table 6: Associated Registers for Linefeed Control .....................................................................................................29
Table 7: TIP and RING Voltage Targets ......................................................................................................................30
Table 8: Registers Associated with Line Monitoring – Measured.................................................................................30
Table 9: Registers Associated with Line Monitoring – Calculated................................................................................30
Table 10: Registers for Polarity Reversal.....................................................................................................................32
Table 11: PWM DC/DC Power Alarm Counter.............................................................................................................33
Table 12: Registers Associated with Thermal Overload...............................................................................................33
Table 13: Associated Registers for Oscillator Control (Oscillator 1 Example)..............................................................35
Table 14: Example Register settings for Oscillator m...................................................................................................36
Table 15: Registers for RING Generation ....................................................................................................................39
Table 16: Example Ringer Register settings................................................................................................................40
Table 17: Registers for RING Trip Detection................................................................................................................45
Table 18: Recommended RING Trip Values for Ringing..............................................................................................45
Table 19: Loop Closure Detection Registers................................................................................................................47
Table 20: Ground Key Detection Registers..................................................................................................................49
Table 21: Registers for FSK Generation ......................................................................................................................50
Table 22: DTMF frequency mapping............................................................................................................................50
Table 23: Digital Gain Adjust Coefficients and Attenuation weightings ........................................................................54
Table 24: Examples of Resistive Impedance Matching................................................................................................55
Table 25: Example of Impedance Matching Programming...........................................................................................55
Table 26: Registers for Automute.................................................................................................................................56
Table 27: Registers associated with DC/DC Conversion .............................................................................................59
Table 28: Example Standard Interface modes.............................................................................................................63
Table 29: Wideband or Narrowband Hardware Selection ............................................................................................64
Table 30: PLL and Prescaler in Wideband...................................................................................................................66
Table 31: Device Address Bit pattern...........................................................................................................................67
Table 32: 12-bit byte Selection.....................................................................................................................................68
Table 33: Interrupt Registers.......................................................................................................................................74
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
9. ABSOLUTE MAXIMUM RATINGS
9.1. Dual Programmable Extended Codec/SLCC (N682386/87)
SYMBOL
PARAMETER
Junction temperature
VALUE
UNITS
0C
150
Storage temperature range
TQFP-64 Thermal Resistance, typical
QFN-64 Thermal Resistance, typical
Voltage applied to any pin
Input current applied to any digital input pin
ESD (Human Body Model)
VDD - VSS
-65 to +150
0C
oC/W
oC/W
V
θJA
θJA
76
17
(VSS - 0.3V) to (VDD + 0.3V)
+/- 10
2000
mA
V
-0.5 to +3.63
0.7
V
Power Dissipation
W
CAUTION: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
9.2. N681622 Subscriber Line Feed Circuit (SLFC)
SYMBOL
PARAMETER
VDD Supply Voltage
VALUE
UNIT
VDD
VBAT
VINHV
VINLV
-0.5 to +5.0
-104
V
V
VBAT Supply Voltage
Input Voltage HV IO
Input Voltage LV IO
ESD, HBM
(VBAT - 0.3) to (VDD + 0.3)
-0.3 to (VDD+0.3)
JESD22 Class 1C
-40 to +100
-40 to +150
45
V
V
V
TA
TS
Operating Temperature **
Storage Temperature
Thermal Resistance QFN20
Power Dissipation
C
C
θJA
C/W
W
PMAX
0.9
** If the dice temperature reaches over 130C, the device reliability may be adversely affected.
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
10. OPERATING CONDITIONS
10.1. Single Programmable Extended Codec/SLCC (N682386/87)
SYMBOL
PARAMETER
Industrial operating temperature
Supply voltage
MIN
-40
TYP
MAX UNIT
TA
+85
C
V
V
VDD
VSS
3.13
3.47
Ground voltage
0
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and
reliability of the device.
10.2. Subscriber Line Feed Circuit (N681622)
SYMBOL
TA
PARAMETER
MIN
-40
TYP
MAX
85
UNIT
Industrial operating temperature
C
V
V
VDD
Supply voltage (VDD
)
3.13
-100
3.3
-
3.47
-9
VBAT
VBAT Supply Voltage
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
11. ELECTRICAL CHARACTERISTICS
11.1. GENERAL PARAMETERS (N682386/87)
V
DD=3.13 V to 3.47 V; VSS=0 V; TA = -400C to +850C;
SYMBOL
VIL
PARAMETERS
Logic Input LOW Voltage
Logic Input HIGH Voltage
Threshold point
CONDITIONS
MIN
-0.3
2
TYP1 MAX2 UNIT
--
--
0.8
3.6
V
V
V
V
VIH
VT
1.41
--
INTB,FS,PCMT,SDO: IOL = 4 mA
DCP, DCN: IOL = 16 mA (24mA)
VOL
Logic Output LOW Voltage
--
2.4
--
0.4
FS,PCMT,SDO: IOH = 4mA
VOH
IIL
Logic Output HIGH Voltage
--
--
--
V
DCP, DCN: IOH = 16 mA (24mA)
V
SS<VIN<VDD
No pull-up or pull-down
SS<VO<VDD
Input HIGH & LOW Leakage
Current
uA
uA
+/-10
+/-10
V
IOZ
Tri-state Leakage Current
--
High Z State
CIN
Digital Input Capacitance
Digital Output Capacitance
--
--
3
3
--
--
pF
pF
COUT
VO High Z
1. Typical values: TA = 25°C , VDD = 3.3 V
2. All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are
100 percent tested.
11.2. SUPPLY PARAMETERS DISCRETE SOLUTION (N682386/87 AND DISCRETE LINE DRIVER)
VDD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C;
SYMBOL
IPD
PARAMETERS
CONDITIONS
MIN
TYP1 MAX2 UNIT
RESETb = 0V, VDD1, VDD2,
VDD3, VDD4, and VDD5
FS=BCLK=0V
Total Power Down Supply
Current
100
25
12.5
8
uA
RESETb = VDD, VDD1, VDD2,
VDD3, VDD4, and VDD5
Total Standby Supply
Current
ISB
mA
FS=BCLK=0V, Line state Open
42
62
40
18
48
Open (ADC and DAC disabled)
mA
mA
mA
mA
mA
Forward/Reverse Active ILIM=20
mA
Total Supply Current for all
supplies @3.3V
Forward/Reverse ON-HOOK
Transmission
IVDD
Forward/Reverse Idle (ADC and
DAC disabled)
TIP/RING Open
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
SYMBOL
PARAMETERS
CONDITIONS
MIN
TYP1 MAX2 UNIT
Ringing, Sine wave, REN=1,
VPK=56 V
30
0.007
31
mA
mA
mA
Open, VBAT = 72V
Forward/Reverse Active ILIM=20
mA,
Forward/Reverse ON-HOOK
Transmission, XBTA:XTBOT=0,
VBAT = 54V
14
mA
IVBAT
Total Battery Supply Current
1.5
0.007
8
Forward/Reverse Idle, VBAT = 54V
mA
mA
mA
TIP/RING Open, VBAT = 54V
Ringing, Sine wave, REN=1,
VPK=71V
1. Typical values: TA = 25°C , VDD = 3.3 V
2. All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are
n00 percent tested.
3. The supply current for the DC/DC converter can be calculated by : IDC/DC=IVBAT*VBAT/(efficiency*VDC/DC)
4. Ch1 and Ch2 have identical configuration for all the above current measurement. IVDD and IVBAT are per channel
current measurement
11.3. SUPPLY PARAMETERS SLFC SOLUTION (N682386/87 AND N681622)
SYMBOL
IDDO
PARAMETER
CONDITION
MIN
TYP
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MAX
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Open State
IDDI
Low Power Idle State, VBAT=-50V
Active State
IDDA
VDD Supply Current
IDDR
Ringing, 1REN, 40Vrms
On-Hook Transmit
Tip/Ring Open
IDDOT
IDDTRO
IBATO
IBATI
Open State
Low Power Idle State, VBAT=-50V
Active State
-
1.2
IBATA
VBAT Supply Current
IBATR
IBATOT
IBATTRO
Ringing, 1REN, 40Vrms
On-Hook Transmit
Tip/Ring Open
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
11.4. MONITORING A/D PARAMETERS
VDD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C
SYMBOL
INL
PARAMETER
CONDITION
UNIT
LSB
LSB
MIN.
--
TYP
+/-0.5
+/-0.5
MAX.
Integral Nonlinearity (8-bit resolution)
Differential Nonlinearity (8-bit
resolution)
DNL
--
Gain Error (Current)
Gain Error (Voltage)
Sample Rate per channel
Number of channels
--
--
--
--
20
10
800
--
%
%
--
Hz
32
Typically at 12-bit the INL and DNL is 2 LSB.
11.5. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
V
DD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C; Loading 600 Ω
TRANSMIT (A/D)
RECEIVE (D/A)
TYP
SYMB
OL
PARAMETER
CONDITION
UNIT
VPK
MIN
TYP
MAX
MIN
---
MAX
---
0 dBm0 = 0 dBm @
LABS
Absolute Level
---
1.0954
---
1.0954
600Ω
3.17 dBm0 for u-Law
3.14 dBm0 for A-Law(1)
---
---
1.5779
1.5725
---
---
---
---
1.5779
1.5725
---
---
VPK
VPK
TXMAX
Max. Transmit Level
0 dBm0 @ 1020 Hz, VDD
=3.3V; TA=+25°C;
assuming ideal line
impedance matching
Absolute Gain (0 dBm0
@ 1020 Hz; TA=+25°C)
GABS
-0.40
0
+0.40
-0.40
0
+0.40
dB
TA= 0°C to+70°C
TA=-40°C to+85°C
-0.10
-0.20
+0.10
+0.20
-0.10
-0.20
+0.10
+0.20
Absolute Gain variation
with Temperature
GABST
0
0
0
0
dB
dB
VDD=3.13 V – 3.47 V;
Absolute Gain variation
with Supply Voltage
GABSS
GRTV
0dBm0 @ 1020 Hz;
TA=+25°C
-0.10
+0.10
-0.10
+0.10
Frequency Response
See Figures 40, 41, and 46
Gain Variation vs. Level
Tone
(1020 Hz relative to –10
dBm0)
+3 to –40 dBm0
-40 to –50 dBm0
-50 to –60 dBm0
-0.3
-0.6
-1.6
---
---
---
+0.3
+0.6
+1.6
-0.3
-0.6
-1.6
---
---
---
+0.3
+0.6
+1.6
GLT
dB
+/-
0.025
+/-
0.025
GST
Gain Step Variation
-6 dB to 6 dB
1200 Hz
-
-
dB
TABS
Absolute Group Delay
---
540
---
---
280
---
usec
Group Delay Distortion
(relative to group delay
@ 1200 Hz)
TD
See Figures 42, 43, 47, and 48
1. at Default Gain Setting
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
11.6. 2-WIRE TO 4-WIRE CONVERSION PARAMETERS
VDD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C; Loading 600 Ω
SYMBOL
PARAMETER
Return Loss
Trans hybrid Balance
CONDITION
MIN.
26
TYP.
40
MAX.
---
UNIT
dB
RL
200 Hz to 3.4 kHz, 600 Ohm
HB
200 Hz to 3.4 kHz, 600 Ohm
40
50
---
dB
11.7. 2-WIRE PARAMETERS
VDD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C; Loading 600 Ω
SYMBOL
LCL
PARAMETER
CONDITION
300 Hz to 3.4 kHz
MIN
46
TYP
MAX
---
UNIT
dB
Longitudinal Conversion Loss
LML
300 Hz to 600 Hz
600 Hz to 3.4 kHz,
300 Hz to 3.4 kHz
40
52
55
18
---
dB
Longitudinal to Metallic or
PCM Balance
LMH
46
---
dB
LZ
Longitudinal Impedance
Longitudinal Current
---
---
Ohms
Active OFF-HOOK; 300 Hz to
3.4 kHz
LI
---
6.5
---
mA
11.8. LINEFEED CHARACTERISTICS
VDD=3.13 V to 3.47 V; VSS=0 V; TA=-400C to +850C; Loading 600 Ω
SYMBOL
PARAMETER
CONDITION
MIN
44
TYP
45
MAX
---
UNIT
VRMS
5 REN load; sine wave;
LOOP =160 Ohm;
RING amplitude
VTR
R
VBAT = –75 V
Loop closure / Ground start
threshold accuracy
ILt
IIT = 11.43 mA
IRT = 40.64 mA
---
---
---
---
+/-20
+/-20
%
%
RING trip threshold accuracy
IRT
Trapezoidal RING crest factor
accuracy
+/-
0.05
Crest factor = 1.3
---
1.35
---
---
---
---
Sinusoidal RING crest factor
Ringing frequency accuracy
RCF
1.45
+/-3
F = 20 Hz
%
ms
%
V
Ringing cadence accuracy
DC Loop Current Accuracy
Accuracy of on/off time
ILIM = 18 mA
---
---
---
---
---
+/-50
+/-10
+/-4
DC Open Circuit Voltage
Accuracy
Power alarm threshold
accuracy
Active Mode; VOH = 48 V, VTIP
– VRING
Power Threshold = 300 mW
---
+/-25
%
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
11.9. ANALOG DISTORTION AND NOISE PARAMETERS
VDD=3.13 V – 3.47 V; VSS=0 V; TA=-400C to +850C; Loading 600 Ω
TRANSMIT (A/D)
MIN TYP MAX
RECEIVE (D/A)
MIN TYP MAX
SYMBOL
PARAMETER
CONDITION
UNIT
dB
Total Distortion vs. Level
Tone u-Law
1020 Hz, C-Message
Weighted
DLTU
See Figure 45
See Figure 44
Total Distortion vs. Level
Tone, A-Law
1020 Hz, Psophometric
Weighting
dB
dB
DLTA
0 dBm0, Active OFF-
HOOK and OHT, ideal
impedance matching
Audio Tone Generator
Signal-to-Distortion Ratio
DLTT
45
---
---
45
---
---
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8400 Hz to 100000 Hz
---
---
---
-70
-70
-65
-30
-40
-30
Spurious Out-Of-Band
(300 Hz to 3400 Hz @
0dBm0)
DSPO
NA
---
NA
---
NA
-47
dB
dB
-47
Spurious In-Band (700 Hz
to 1100 Hz @ 0dBm0)
DSPI
300 to 3200 Hz
Two tones
---
---
Intermodulation Distortion
(300 Hz to 3400 Hz
–4 to –21 dBm0)
DIM
---
---
-45
---
---
-45
dB
u-Law; C-message
A-Law; Psophometric
16-bit Linear
---
---
---
---
---
---
13
18
1
14
dBrnc0
dBm0p
NIDL
Idle Channel Noise
-74
-69
-90
-76
PSRRA
PSRRB
Power Supply Rejection
Power Supply Rejection
VDDA; DC to 3.4 kHz
VBAT; DC to 3.4 kHz
40
40
---
---
---
---
40
40
---
---
---
---
dB
dB
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Dual Programmable Extended Codec/SLCC + SLFC
12. FUNCTIONAL DESCRIPTION
x T F I M P C
R x a f c r e t e n M C I P
Figure 4: AC signal Path
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
12.1. BORSCHT FUNCTIONALITY
The N682386/87 connects to the TIP and RING (POTS - Plain Old Telephone Service) interface and performs the so-
called BORSCHT and AC transmission functions. Following are the BORSCHT functions:
¡
¡
¡
¡
¡
¡
¡
Battery Feed
Over-Voltage Protection
Ringing (Balanced / Unbalanced)
Supervision (Signaling)
Coding
Hybrid (2 / 4-wire conversion)
Testing
12.1.1. BATTERY FEED
The N682386/87, has two DC feed regions; a constant voltage region and a constant current region. As illustrated in
Figure 4 the current limit ILIM determines the constant current region. The ON-HOOK voltage, VOH, determines the
constant voltage region. The device has an inherent output resistance of typically 50ꢀ in non-ringing states. The
Ground Margin Voltage, VGM, determines the offset of the most positive terminal (TIP in Forward polarity state and
RING in Reverse polarity state) with respect to ground ILIM, VOH, and VGM are programmable as shown in Table 2.
|VTIP-VRING
|
ΔV
ΔI
=50ꢀ typical
(Volt)
VOH
ΔV
ΔI
>10kꢀ typical
ILIM
ILOOP (mA)
DCFeed
Figure 5: DC Feed Regions
Register
LCL
Address
0x45
Parameter
ILIM
Programmable Range
20 – 41
Step Size
3
Default Value
20
Unit
mA
V
OHV
0x4C
VOH
0 to –93.5
1.484
1.484
-47.488
-2.968
GMV
0x4D
VGM
0 to –93.5
V
Table 3: Programmable Ranges for DC Line Feed
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
The control circuit for TIP or RING is illustrated in Figure below. N682386/87 utilizes a three transistor discrete
Linefeed circuit. Transistors Q1 and Q2 drive the voltages on the subscriber loop while transistor Q3 provides
additional isolation. The Line Driver DC feedback loop is completed via DC isolation resistors RVBAT and RVE to the
chip. TIP and RING signals are derived from the common mode and differential mode signal block. This information
is, in turn, used to exercise control over the external transistors. Voice band signals are passed over a decoupling
capacitor in the AC feedback loop.
TIP or RING
VDD
Discrete
Linefeed
Sigma/Delta
DAC
Q1
-
Sigma/Delta
ADC
+
Q3
+
IOUT
OTA
Q2
+
RQE
RB3
AC Loop
DC Loop
VBAT
LineFeed
ADC
RVBAT
RVE
Common Mode
LineFeed
DAC
Differential Mode
Signals
Mux
On-chip
LLC-v1
Figure 6: Line Loop Control
Control and monitoring of these transistors is done both individually and in groups. For example, TIP and RING
Linefeed circuits each have a Q1 transistor. Both share the same register to set their Power Alarm Threshold values.
But each TIP and RING transistor has a separate Power Alarm Interrupt bit in the interrupt register. The control
circuit for TIP and RING when N681622 is utilized follows the same general principles.
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Dual Programmable Extended Codec/SLCC + SLFC
12.1.1.1.
LINEFEED STATES OF OPERATION
The N682386/87 can operate in eleven states, as shown below. .
LS Settings
State
Description
MSB
0
LSB
0
Open
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
TIP and RING tri-state
VTIP > VRING
Forward Active
Forward ON-HOOK Transmission
TIP Open
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
1
0
VTIP > VRING; audio signal paths powered on
TIP tri-stated, RING active; used for ground start
Ringing waveform applied to TIP and RING
VRING > VTIP
Ringing
Reverse Active
Reverse ON-HOOK Transmission
RING Open
VRING > VTIP; audio signal paths powered on
RING tri-stated, TIP active
Forward Idle
VTIP > VRING
Reverse Idle
VRING > VTIP
Calibration
VTIP = VRING~Vbat+2
Table 4: Linefeed States
12.1.1.1.1.
OPEN STATE
Current to the external linefeed circuitry is shut off, effectively making TIP and RING tri-stated and it can also be used
for fault condition detection. DC output impedance is 150K ohm.
12.1.1.1.2.
ACTIVE, IDLE AND ON-HOOK TRANSMISSION STATES
¡
¡
¡
¡
¡
¡
Active, Idle and ON-HOOK Transmission states all have both Forward and Reverse incarnations
In Forward state TIP is the more positive lead
In Reverse state RING is the more positive lead
In Idle states the external linefeed circuitry is ON but the audio signal paths are not powered up.
In both Active states the external linefeed circuitry is ON and the audio signal paths are powered up.
In both ON-HOOK Transmission states audio signal paths are powered up to allow ON-HOOK transmission.
The Forward and Reverse incarnations of the Active, Idle and ON-HOOK Transmission states are determined solely
by setting the LS register. For automatic transitions Forward and Reverse incarnations are determined by the VOH
polarity in OHV:SBCn[6] address location (0x4C).
12.1.1.1.3.
TIP OPEN STATE
¡
¡
All control currents to the external circuitry associated with TIP are shut off.
Linefeed is provided to RING.
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.1.1.1.4.
All control currents to the external circuitry associated with RING are shut off and keeps TIP active.
12.1.1.1.5. RINGING STATE
Drives the ringing waveforms onto the loop
12.1.1.1.6. CALIBRATION STATE
RING OPEN STATE
¡
¡
Calibration state is used to compensate or correct for external component imperfections. It should be performed
following the system power up. This state is enabled by setting LS:LSCn[3:0] address (0x44) to ‘1110’. The line
should be on-hook during calibration. RING or TIP must not be connected to ground during the calibration. All
automatic linefeed transitions should be disabled when performing calibration. After calibration is completed, the
Linefeed state should be reset to a normal operating state and the automatic Linefeed transitions can be enabled
again. For a more detailed explanation, please refer to the Calibration Application note.
Please note that Calibration state is not applicable to Subscriber Line Feed Circuit (SLFC).
12.1.1.2.
OPERATION MODES
The N682386/87 can operate under two battery supply operation modes. The modes are selected as illustrated
below.
Per Channel
DC/DC
VBAT Switch [DCN/DCP Line
state dependent Control]
Operation Mode
Condition
Figure 52: Inductor based
circuit for Channel 1
On-Chip DC/DC Controller
External Battery Supplies
On
Off
Off
On
DCL1 & DCL2 to VDD
DCH1 & DCH2 to VSS
Table 5: Operation Modes
12.1.1.3.
AUTOMATIC TRANSITIONS
In addition, some automatic state transitions may also be enabled:
12.1.1.3.1. POWER ALARM AUTOMATIC REACT
¡
Setting LAMC:PAACn[2] address (0x43) bit will make the channel automatically enter the Open state upon the
occurrence of a power alarm.
12.1.1.3.2.
SETTING RING AUTOMATIC
¡
Setting LAMC:RGACn[1] address (0x43) bit makes the channel automatically enter the Active state from the
Ringing State upon RING Trip Detect
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.1.1.3.3.
SETTING LOOP CLOSURE DETECT AUTOMATIC REACT
Setting LAMC:LCDACn[0] address (0x43) bit makes the channel automatically enter the Active state from the ON-
HOOK Transmission, Idle, TIP Open, and RING Open states upon Loop Closure Detect. Furthermore, the channel
will transition from Active to Idle state if the Loop Closure Detect circuitry indicates a loop closure is no longer
present, and back to Active state upon a reoccurrence of Loop Closure Detect.
When the above automatic transitions do occur, LS:LSCn[3:0] address (0x44) will be updated automatically to reflect
the newly entered state. In all cases the shadow linefeed status bits, LS:SLSCn[3:0] address (0x44) reflect the actual
linefeed status. This includes switching between ‘Ringing’ during the ring burst and ‘ON-HOOK Transmission’ during
the cadence. This RING/cadence transition is not considered an automatic transition and LS:LSCn[3:0] address
(0x44) will continue to reflect Ringing state. The following example state diagram illustrates LS:SLSCn[3:0] address
(0x44) states including automatic transitions, RING/Cadence transition and several possible transitions solely
governed by software.
PA_Auto
SW
Open
Open
Any State
Any State
Any State
SW
Idle
SW
SW
LC_Auto
! LC_Auto
(F/R)
LC_Auto
On Hook
Transmission
(F/R)
Active
(F/R)
SW
SW
LC_Auto
TIP Open
Ring Cadence
&
SW
LC_Auto
LS[3:0] = Ringing
Ring Burst
&
LS[3:0] = Ringing
SW
RT_Auto
SW
SW
RING Open
Calibration
Any State
Any State
Ringing
LC_Auto = RTLC:LCD = 1 & LAMC:LCDA= 1
!
LC_Auto = RTLC:LCD= 0 & LAMC:LCDA= 1
RT_Auto = RTLC:RTD = 1 & LAMC:RGA= 1
PA_Auto = Power Alarm Event& LAMC:PAA = 1
F/R = Forward / Reverse
n = 1, 2
LFSDS
Figure 7: Example State Diagram
Register
LS
Bit(s)
Address
0x44
Parameter
Description / Range
LSCn[3:0]
SLSCn[7:4]
PAACn[2]
RGACn[1]
LCDACn[0]
Programmed Linefeed Status
Shadow Linefeed Status
Eleven states
0x44
0x43
0x43
0x43
Reflects actual state
Enable/Disable
Enable/Disable
Enable/Disable
Power Alarm Automatic React
RING Automatic
LAMC
Loop Closure Detect Automatic React
Table 6: Associated Registers for Linefeed Control
The device continuously monitors voltages on the line driver, driving them to target voltages appropriate to the actual
linefeed state as summarized below.
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Linefeed State
TIP Target
High Z
RING Target
High Z
Open
Forward Active
VTIP > VRING
VTIP > VRING
Forward ON-HOOK Transmission
TIP Open
High Z
Active
Ringing
RING Signal
RING Signal
Reverse Active
VTIP < VRING
Reverse ON-HOOK Transmission
RING Open
VTIP < VRING
Active
High Z
Forward Idle
VTIP > VRING
VTIP < VRING
Reverse Idle
Table 7: TIP and RING Voltage Targets
The device monitors the currents in the external transistors and makes these values available in registers. These
registers and the internal A/D are updated at a rate of 800 Hz or every 1.25 msec. Other useful voltages and currents
are calculated internally and made available in registers
Register
BATV
SCM
Bits(s)
Address
0x80
0x92
0x83
0x84
0x85
0x86
Parameter
Battery Voltage
Description / Range
0V to -94.6 in 371 mV steps
VBCn[7:0]
SCMCn[7:0]
QT3VCn[7:0]
QR3VCn[7:0]
QT3ICn[7:0]
QR3ICn[7:0]
Common Mode Voltage
+95.88V to -95.88V in 23.4uV steps
0V to -94.6V in 371 mV steps
0V to -94.6V in 371 mV steps
0A to 78.54 mA in 19.2 µA steps
0A to 78.54 mA in 19.2 μA steps
QT3V
QR3V
QT3I
Transistor QT3 Emitter Voltage
Transistor QR3 Emitter Voltage
Transistor QT3 Current
QR3I
Transistor QR3 Current
Table 8: Registers Associated with Line Monitoring – Measured
Register
LPV
Bit(s)
Address
0x8D
0x87
0x88
0x89
0x8A
0x8C
0x8E
0x8F
0x90
Parameter
Loop Voltage
Description / Range
+93.5V to -93.5V in 23 mV steps
0A to 78.54 mA in 19.2 μA steps
0A to 9.95 mA in 2.5 μA steps
0A to 78.54 mA in 19.2 μA steps
0A to 9.95 mA in 2.5 μA steps
+77.62 mA to –77.62 mA in 19uA
+77.62 mA to –77.62 mA in 19uA
+77.62 mA to –77.62 mA in 19uA
+77.62 mA to –77.62 mA in 19uA
VLPCn[11:0]
QT1ICn[11:0]
QT2ICn[11:0]
QR1ICn[11:0]
QR2ICn[11:0]
ILGCn[11:0]
ITLPCn[11:0]
IRLPCn[11:0]
ILPCn[11:0]
QT1I
QT2I
QR1I
QR2I
LGI
Transistor QT1 Current
Transistor QT2 Current
Transistor QR1 Current
Transistor QR2 Current
Longitudinal Current
TIP Current
TIPI
RINGI
LPI
RING Current
Loop Current
Table 9: Registers Associated with Line Monitoring – Calculated
In addition the following loop voltages and currents are derived from the above measurements and reported
separately.
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.1.1.4.
POLARITY REVERSAL
The Linefeed states which have Forward or Reverse incarnation (Active, Idle and ON-HOOK Transmission states)
can have the polarity reversed two different ways. In addition, the line (TIP or RING) which is at VOH can be
collapsed towards ground by using the wink function.
¡
¡
Hard polarity reversal
Soft polarity reversal
12.1.1.4.1.
HARD POLARITY REVERSAL
Hard polarity is achieved by abruptly reversing the voltage between TIP and RING without any ramp-rate control. This
is achieved by simply changing the linefeed register from Forward to Reverse incarnation or vice versa. A Hard
polarity reversal will be performed provided that soft polarity reversal is not enabled APG:PRENCn[6] address (0x40)
bit to 0. The sign bit (OHV:SBCn[6]) is used to determine the polarity of the line when going from Idle to Active
States. If the new polarity is to be retained in future Idle to Active transitions, it is recommended that this bit be also
changed appropriately when polarity is reversed.
12.1.1.4.2.
SOFT POLARITY REVERSAL
Soft polarity is achieved by reversing the voltage between TIP and RING with ramp-rate control. Soft polarity reversal
is enabled by setting APG:PRENCn[6] = “1” address (0x40). The ramp rate at which the reversal will occur is
selected in APG:RAMPCn[8] address (0x40). The Ramp is triggered by toggling WINK bit APG:PRENCn[6] = “1”
address (0x40). Soft polarity reversal is typically used in idle states and can be used in active states. The table
below illustrates the sequence of events for a Forward to Reverse soft polarity reversal. For Reverse to Forward
Polarity Reversal step 2 would involve TIP and step 4 would involve RING.
Step(s) Register Name Bit(s)
Bit State
Step Description
1
2
3
4
5
APG
APG
PRECn[6]
1
1
Enables soft polarity reversal
Wink line (RING towards 0V)
VOHZCn[5]
Use Line state register to reverse the line from Forward to Reverse
APG
APG
VOHZCn[5]
PRECn[6]
0
0
Un-wink line (TIP side towards VOH)
Disable soft polarity reversal
Note that the negative going ramp rate can be limited by the settling speed of the DCDC converter. Setting the
minimum on time (0x57) to 0x0B before the ramp and back to the initialization value after the ramp will prevent this
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x40
APG
RAMPCn PRENCn VOHZCn
RES
ARXCn
ATXCn
The sign bit OHV:SBCn[6] is used to determine the polarity of the line during an automatic transition into idle, Active,
and On-Hook transition states. If the new polarity is to be retained in future automatic transitions, it is recommended
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
that OHV:SBCn[6] be also changed appropriately when polarity is reversed. The ramp rate for steps 2 and 4 above is
determined by the Ramp Rate bit APG:RAMPCn[7].
12.1.1.5.
WINK FUNCTION POLARITY REVERSAL
A Wink function is used for the ‘message waiting’ lamp in telephone sets. For this function to take place no Linefeed
state change is necessary. The Wink function is a variation of Soft Polarity Reversal but without any Linefeed state
change. In this case Soft Polarity reversal is enabled as before APG:PRENCn[6] address (0x40) bit to “1”, with
APG:RAMPCn[7] address (0x40) selecting the ramp rate. Now the OHV:VOHZCn[5] address (0x4C) bit can be used
to directly ramp the RING line towards 0V or back to VRING. For example, in Forward Idle mode VTIP is at VGM and
VRING is VGM+VOH. If VOHZCn bit is set to “1” the Ring Voltage will ramp towards 0V. If the bit is toggled it will
eventually return to the nominal VRING setting. The user has full control of the Wink function cadence.
Register
APG
Bit(s)
Address
0x40
Parameter
Programmable Range
0 = Return to previous VOH
1 = Ramp to 0V
VOHZCn[5]
Wink Function (Smooth transition to VOH=0V)
0 = Disabled
1 = Enabled
0 = 1.5 V/125 µs
1 = 3.0 V/125 µs
APG
APG
LS
PRECn[6]
RAMPCn[7]
LSCn[3:0]
SBCn[6]
0x40
0x40
0x44
0x4C
Soft Polarity Reversal Enable
Soft Polarity Reversal Ramp Rate
Linefeed Status
0 = Forward
1 = Reverse
OHV
Polarity Reversal Status (Sign)
Table 10: Registers for Polarity Reversal
12.1.2. OVER-VOLTAGE PROTECTION
It is a common requirement for electronic circuits to have to withstand some degree of over-voltage and/or reverse
voltage on the power-supply lines. Integrated circuits are designed to operate from a nominal 3.3V power supply.
Some kind of protection circuit is therefore needed to prevent voltages greater than the maximum allowable from
being applied to the IC pins. The N682386/87 device needs to be protected from surges and AC power shorts. This
should be implemented using external components and a variety of commercial approaches are typically employed.
However, N682386/87 device has on-chip voltage and line monitoring capabilities which allow the system to report
line faults, crossovers, and other line conditions in order to facilitate remote service. It also has sense inputs can be
configured such that blown fuse can be detected. The on-chip DC/DC controller is equipped with three protection
shutdown mechanisms. It detects
a) DCDC output voltage (VBAT) 10% above full scale or
b) DCDC supply voltage (VDDC) too low or
c) DCDC supply current (IVDDC) too high;
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Dual Programmable Extended Codec/SLCC + SLFC
A counter is tracking the three cases of DC/DC power alarm. The counter will automatically reset upon being read,
allowing the user to monitor the number of power alarms within a specific time period. This register is a read ONLY
register resets upon a read command.
Register
APG
Bit(s)
Address
0x9F
Parameter
Programmable Range
Increment on every rising edge of LOW
VDC or HIGH IDC; clip at 255;
PALCNTCn[7:0]
Power Alarm Counter
Table 11: PWM DC/DC Power Alarm Counter
12.1.2.1.
THERMAL OVERLOAD
In addition to voltage and current monitoring described in the “Linefeed States of Operation” section, N682386/87
continuously monitors the power dissipation of each external transistor in the Linefeed circuitry. After Low Pass
Filtering, the power dissipation is compared against thresholds which are listed in Table 10. The threshold and the
Low Pass Filter pole are both programmable and should be set according to the characteristics of the individual
transistor as follows. The Low Pass Filter pole for QT1 and QR1 is given by the equation:
⎛
⎜
⎞
⎟
1
Q1C[12: 0]
=
1 −
×213
⎜
⎟
⎜
⎝
⎟
⎠
800 × TTC
Where TTC is the thermal time constant of the external transistor. The threshold should be programmed according to
the maximum power dissipation of the external transistor. If the threshold is exceeded a power alarm event is
deemed to have occurred. An associated interrupt may be enabled. An automatic state transition into Open state
may be enabled by setting Power Alarm Automatic React (LAMC:PAACn[2]) address (0x43)).
Register
PALPQ1
PALPQH1
PALPQH2
PALPQ2
PALPQH1
PALPQH2
PALPQ3
PALPQH2
PALPQH2
Bit(s)
Address
Parameter
Description / Range
Q1C[7:0]
Q1C[11:8]
Q1C[12]
Q2C[7:0]
Q2C[11:8]
Q2C[12]
Q2C[7:0]
Q3C[11:8]
Q3C[12]
0xA1
0xA3
0xA4
0xA0
0xA3
0xA4
0xA2
0xA3
0xA4
PA Low Pass Filter Pole for
QT1 and QR1
See Register Description
PA Low Pass Filter Pole for QT2
and QR2
See Register Description
See Register Description
PA Low Pass Filter Pole for QT3
and QR3
PATHQ1
PATHQ2
PATHQ3
INT1
Q1TH[7:0]
Q2TH[7:0]
Q3TH[7:0]
0xA6
0xA5
0xA7
0x26
PA Threshold for QT1 and QR1
PA Threshold for QT2 and QR2
PA Threshold for QT3 and QR3
Power Alarm Interrupt
0 to 7.7 W in 30.4 mW steps
0 to 0.97 W in 3.8 mW steps
0 to 7.7 W in 30.4 mW steps
No INT / INT
IE1
LAMC
0x27
0x43
Power Alarm Interrupt Enable
Power Alarm Automatic React
Masked / Enabled
Enable/Disable
PAACn[2]
Table 12: Registers Associated with Thermal Overload
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
12.1.2.2.
TEMPERATURE MONITOR
The device contains an on-chip temperature sensor that senses the temperature of the die. This temperature is read
through the TEMP:TS[7:0] register (0x99). TEMP:TS[7:0] address (0x99) is READ ONLY register. The die
temperature is given in °C (degree Celsius) as follows
Die Temperature = TS [7 : 0] − 67
(Decimal)
Example1: If register TEMP:TS[7:0] reads 0x23 (35 decimal) then the die temperature is -32°C.
Example2: If register TEMP:TS[7:0] reads 0xCD (205 decimal) then the die temperature is 138°C.
The die temperature alarm threshold is set using the register THAT:THAT[7:0] address (0xAA). The die temperature
alarm threshold (TTH) is given in °C (degree Celsius) as follows
TTH = THAT
[
7 : 0
]
− 67
(Decimal )
If the die temperature reaches the threshold temperature than an interrupt will be generated if this interrupt is
enabled. The interrupt is enabled by setting IE3:TMPE[0] address (0x2B). This facilitates control of the temperature
should the device get close to the junction temperature. Note that there is no filtering associated with this
temperature alarm since the package has an intrinsic thermal time constant. It is recommended that the temperature
alarm threshold be set to 125°C. The die temperature can be estimated by the following equation.
⎛
⎜
⎞
⎟
Die temperature = T
+
R
× P
J
A
⎜
⎜
⎟
⎟
⎝
⎠
TA – Ambient Temperature
RJ – Thermal Resistance
P – Power Dissipation
For example, the maximum power dissipation for the QFN device is 0.7 W. The thermal resistance of the 64-pin QFN
package is 17°C/W. So at TA=85°C, the estimated internal temperature would be:
ο
Die Temperature = 85 + 17 * 0.7 = 96.9 C
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Dual Programmable Extended Codec/SLCC + SLFC
12.1.3. RINGING
N682386/87 has a built-in Ring generator that can generate both balanced sinusoidal or trapezoidal Ringing without
the need for external components. The choice of sinusoidal or trapezoidal will depend on requirements of the end
user; sinusoids are required in many parts of the world to minimize cross talk between the many tip/ring pairs in a
typical wiring bundle from the central office, whereas a trapezoid will deliver more power to the phone due to its low
crest factor. The Frequency, Amplitude, DC offset and Ringing cadence of the ringing signal are programmable. In
the case of trapezoidal waveforms, the crest factor is also programmable. As Ringing utilizes the Tone Generation
block, we will first examine this function.
12.1.3.1.
TONE GENERATION
N682386/87 has two-tone generators Oscillator1 (OS1), and Oscillator2 (OS2). These can be used to generate
signals such as dial tone, busy tone, and various test tones which can be sent either on the transmit or receive paths.
Each tone generator has a similar architecture and contains a two-pole oscillator circuit with a sample rate of 16 kHz.
Register
OS1ICL
Bit(s)
Address
Parameter
Description / Range
Sets Amplitude
Sets Frequency
0 to 8 sec
0xC2
0xC3
0xC6
0xC7
0xCA
0xCB
0xCE
0xCF
O1ICCn[15:0]
O1CCn[15:0]
O1ONCn[15:0]
Oscillator 1 Amplitude Coefficient
Oscillator 1 Frequency Coefficient
Oscillator 1 Active Timer
OS1ICH
OS1CL
OS1CH
OS1ATL
OS1ATH
OS1ITL
OS1ITH
O1OFF[15:0]
TORCn[3]
Oscillator 1 Inactive Timer
Tone Route
0 to 8 sec
RMPC
OSN
0xC1
Towards D/A or A/D
O1ECn[0]
O2ECn[1]
0xC0
0xC0
0x29
Oscillator Control
O1AECn[0]
0x29
O1IECn[1]
O2AECn[2]
O2IECn[3]
IE2
Interrupt Mask / Enable
Control
Status
0x29
0x29
INTV
IINT2
0x24
0x28
Interrupt Vector Low Register
Interrupt Status
Table 13: Associated Registers for Oscillator Control (Oscillator 1 Example)
For a desired frequency, ft, the oscillator coefficient for oscillator m, OmCCn[15:0], can be calculated with the
following equations for both Narrowband and Wideband. The resulting hexadecimal coefficients are inputs to
registers OSmCH and OSmCL.
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⎡
⎢
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎥
⎡
⎢
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎥
2 * π * f
2 * π * f
t
t
O1CCn [15: 0] = COS
* 215
O2CCn [17 : 0] = COS
* 217
16 kHz
16 kHz
⎢
⎣
⎥
⎦
⎢
⎣
⎥
⎦
The initial condition for Oscillator m, OSmICL[15:0], can be calculated using the following equation for both
Narrowband and Wideband.
⎡
⎢
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎥
2 * π * f
t
OmICCn [15:0] = A * sin
* 215
(m: 1 , 2
n: 1, 2)
16 kHz
⎢
⎣
⎥
⎦
“A” is calculated as the ratio of desired peak amplitude, APK, with a peak D/A output of 1.5779 VPK. APK cannot
exceed 1.2 VPK. The resulting hexadecimal coefficient is input to registers OSmICH and OSmICL.
APK
A =
1.5779
Frequency
(Hz)
APK
(Volts)
Frequency
(Hz)
APK
(Volts)
O1CCn[15:0]
O1ICCn[15:0]
O2CCn[17:0]
O2ICCn[15:0]
697
770
0x7B3C
0x7A37
0x78E7
0x775C
0x71D8
0x6EC9
0x6B11
0x6692
0.31
0.31
0.31
0.31
0.55
0.55
0.55
0.55
0x06C5
0x0775
0x0839
0x090B
0x145B
0x164E
0x1868
0x1AA4
697
770
0.31
0.31
0.31
0.31
0.55
0.55
0.55
0.55
0x06C5
0x0775
0x0839
0x090B
0x145B
0x164E
0x1868
0x1AA4
1ECF0
1E8C5
1E39B
1DD70
1C75E
1BB22
1AC43
19A48
852
852
941
941
1209
1336
1477
1633
1209
1336
1477
1633
Table 14: Example Register settings for Oscillator m
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Figure 8: Block Diagram Oscillator 1
Each tone generator contains two timers, one for setting the active period and the other for the inactive period. Each
period can be programmed between 0 seconds (timer disabled) to 8 seconds in 125µs increments. In addition,
interrupts can be enabled on the expiration of either timer. The device has programmable cadence where the signal
is generated during the active period and suspended during the inactive period.
One-shot control of the oscillation can be achieved by controlling OSN:O1ECn[0] and OSN:O2ECn[1] address (0xC0)
together with the active timer and the interrupt for durations up to 8 seconds. For longer durations or for direct
software control of the oscillation, enabling the active timer by setting it to any non-zero value while simultaneously
disabling the inactive timer completely will put the oscillator under direct control of the OSN:O1ECn[2] and
OSN:O2ECn[3] bits. Zero crossing detect can be enabled by setting the OSN:OmZCCn bit for the corresponding
tone generator. Setting this bit will ensure that each oscillator pulse will end without a DC component as illustrated
below.
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cadence
cadence
tone
tone
Figure 9: Zero Crossing for Tone Generation
Oscillator 2 is also specifically used to generate the Ringing signal and is unavailable for other functions during
ringing. FSK generation does not utilize either one of the tone generation oscillators.
12.1.3.2.
RING SIGNAL GENERATION
The N682386/87 supports balanced and unbalanced Ringing up to 90 VPK (typically 5 REN up to 4 kft). Oscillator 2
from the Tone Generation block is used to generate the Ringing waveform. However, programming the waveform,
sinusoidal or trapezoidal, involves some slight modifications to the procedures described for Tone Generation. The
active and inactive timers of oscillator 2 can be programmed between 0 seconds (timer disabled) and 8secs in 125us
increments. A Ring phase delay can also be programmed in the OS2RPD:O2RPDCn[7:0] address (0xAD).
All other oscillator operations are standard and follow the description in the tone generation section. Interrupts can
be enabled on the expiration of either timer, so that, for instance, Caller ID can be inserted between tones. Cadence
is activated when a non-zero value is programmed into both the active and inactive timers. In this case, these timers
effectively govern the transitions in and out of the Ringing state as described in Linefeed States of Operation Section.
When the Ring Automatic bit LAMC:RGACn[1] address (0x43) is set, the oscillator is automatically enabled when the
Ringing state is entered and disabled when exited. If the Ring Automatic bit is enabled the transition from Ringing to
Active state (Forward or Reverse) occurs automatically upon Ring Trip Detect. The oscillator enable and ring enable
bits are automatically updated accordingly OSN:O2ECn[1] address (0xC0) and RMPC:R1ENCn[5] address (0xC1).
One-shot control of the oscillation can be achieved by controlling OSN:O2ECn[1] address (0xC0) together with the
active timer and the active timer interrupt for durations up to 8 seconds. For longer durations or for direct software
control of the oscillation, enabling the active timer by setting it to any non-zero value, while simultaneously disabling
the inactive timer completely, will put the oscillator under complete direct control of the OSN:O2ECn[1] address
(0xC0) bit. Zero crossing detect can be enabled by setting the OSN:O2ZCCn[3] address (0xC0). Setting this bit will
ensure that the RING signal will end without a DC component. It is recommended that settings be reprogrammed
only when the oscillator is disabled.
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Register Name
RMPC
Register Name
TRAP[7]
Address
0xC1
Parameter
Ringing Waveform
Description / Range
Sine/Trapezoid
0xC8
0xC9
0xDC
0xC4
0xC5
OS2CL
OS2CH
15 to 100 Hz for Sine Trapezoid
Ramp Slope
O2CCn[17:0]
Ringing Frequency
OS2ICL
OS2ICH
O2ICCn[15:0]
OS2RPDCn[7:0]
O2ECn[1]
Ringing Amplitude
0 to 93.5 V Trapezoid tRISE / tPEAK
0 to 31.8 ms @ 125us
Enable/Disable
OS2RPD
OSN
0xAD
0xC0
Ringing Phase Delay
Ringing Oscillator Enable
Ringing Oscillator Active Timer
OS2ATL
OS2ATH
OS2ITL
OS2ITH
0xCC
0xCD
0xD0
0xD1
O2ON[15:0]
O2OFF[15:0]
O2ZCCn[3]
0V to 8 seconds
Ringing Oscillator Inactive Timer 0V to 8 seconds
Ringing Oscillator Zero Cross
Enable/Disable
OSN
LS
0xC0
0x44
0x4E
0x42
0xDC
0x29
Enable
Linefeed Status Control (Initiates
Ringing State)
LSCn[3:0]
Ringing State = 0100b
VBHV
VCMR
ROFFS
IE2
VBATHCn[5:0]
VCMRCn[5:0]
ROSCn[5:0]
VBATH High Battery Voltage /2
0V to -93.5V in 1.484V steps
0V to -93.5V in 1.484V steps
0V to +47.488 V in 1.484V steps
Controls
VCMR Common Ringing Bias
Adjust During Ringing
Ringing DC voltage offset
Interrupt Enable
INTV
INT2
0x24
0x28
Interrupt
Status
Table 15: Registers for RING Generation
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12.1.3.2.1.
SINUSOIDAL RINGING
Sinusoidal Ringing is selected by setting RMPC:TRAP[7] address (0xC1) to LOW. For a desired frequency fR is
calculated and programmed as before (see section Tone Generation). The oscillator initial condition for oscillator 2 is
set in register O2ICn[17:0] address (0xC4 – 0xC5) according to the following equation.
Description
Desired frequency ft
Equation
⎡
⎢
⎢
⎤
2 * π * f
⎥
⎥
17
t
O2CCn[17 : 0] = cos
* 2
(n: 1, 2)
(n: 1, 2)
The resulting hexadecimal coefficient is input to registers
OS2CH and OS2C and ROFFS
⎢
⎣
⎥
⎦
8 kHz
⎡
⎢
⎢
⎢
⎣
⎤
⎥
Oscillator initial condition for oscillator 2
2* π * f
15
* 2
R
O2ICCn[15 : 0] = A * sin
⎥
⎥
⎦
The resulting hexadecimal coefficient is input to registers
OS2ICH and OS2ICL
8 kHz
A
A is calculated from the desired peak amplitude,
APK, in volts
PK
A
=
96
Note that A is calculated differently for Tone Generation. Finally the precise phase position where the sinusoidal
ringing signal begins transmitting can be controlled by programming a transmission or phase delay of up to 31.8 ms
into OS2RPD:O2RPDCn[7:0] address (0xAD). If the zero-crossing feature is enabled signal transmission will end at
the equivalent phase position.
Target
Frequency
(Hz)
Frequency with
Dual Pro–X (Hz)
O2CCn[17:0]
10
11
12
13
14
15
16
17
18
19
20
25
50
11.12
11.12
12.18
13.15
14.07
15.73
16.49
17.22
18.60
19.27
20.51
25.37
50.26
1FFFB
1FFFB
1FFFA
1FFF9
1FFF8
1FFF6
1FFF5
1FFF4
1FFF2
1FFF1
1FFEF
1FFE6
1FF9A
Table 16: Example Ringer Register settings
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12.1.3.2.2.
TRAPEZOIDAL RINGING
Trapezoidal Ringing is selected by writing RMPC:TRAP[7] = 1 address (0xC1). Three parameters are required to
specify a Trapezoidal RING Signal and they as follows:
•
•
•
Desired frequency ft (period T)
Desired amplitude APK
Crest factor, CF
Three values are programmed across O2CCn[17:0] and O2ICn[15:0] to describe the waveform.
V
TIP-RING
tPK
APK
Time
tRISE
T = 1/fT
TR_v1
Figure 10: Trapezoidal Ringing
Description
Equation
⎛
⎞
⎟
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
⎜
t
= 0.375 * T * 1−
Calculated rise time (tRISE
)
RISE
⎜
⎝
⎟
⎠
2
CF
The rise time, expressed as an integer number of periods of 8 kHz,
OS2ICL
O2ICCn[7: 0] = t
* 8 kHz
RISE
The resulting hexadecimal coefficient is input to registers OS2ICL
t
=
0.5 * T
)
−
2 * t
Calculated peak time (tPK
)
PK
RISE
The peak time, expressed as an integer number of periods of 8
kHz, OS2ICH
O2ICCn[15: 8] = t
* 8 kHz
(n: 1, 2)
(n: 1, 2)
PK
The resulting hexadecimal coefficient is input to registers OS2ICH
⎡ A
⎤
Calculated ramp rate is specified in O2CCn[15:0]
15
PK
⎢
⎢
⎥⎥ *2
96
⎢
⎣
⎥
⎦
O2CCn[15:0]=
Oscillator 2 has 18-bit register. The resulting hexadecimal coefficient is
written to registers ROFFS:O2C[7:6], OS2CL and OS2CH
t
*8 kHz
RISE
Precise position where the trapezoidal signal begins transmitting. If
the zero-crossing feature is enabled signal transmission will end at
the equivalent phase position.
OS2RPD = transmission or phase delay of up
to 32 ms
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12.1.3.2.3.
RINGING DC OFFSET AND COMMON MODE BIAS
A Ringing DC offset voltage VROFF can be defined by setting ROFFS:ROS[5:0]
V
⎛
⎞
6
ROFF
96
⎜
⎜
⎟
⎟
ROS[5 : 0] =
* 2
⎝
⎠
Ringing DC Offset is enabled when ROFFS:ROS[5:0] contains a non-zero value. VROFF is added to, or subtracted
from, the AC ringing signal depending on the setting.
time
0V
V
TIP
V
TIP
APEAK
APEAK
VROFF
VBATH/2
VROFF
APEAK
V
V
RING
RING
VBATH
Volts
VROFF = 0
RG
VROFF > 0
Figure 11: Positive DC offset for Trapezoidal Ringing
Similarly a Common Ringing Bias voltage VCMR can be defined by setting the VCMR Register.
0V
time
V
TIP
V
TIP
APEAK
VBATH/2
VCMR
APEAK
V
V
RING
RING
VBATH
Volts
CMR
VCMR = 0
VCMR > 0
Figure 12: Programming VCMR voltage for Trapezoidal Ringing
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12.1.3.2.4.
LINEFEED CONSIDERATIONS DURING RINGING
To maintain proper biasing of the external bipolar transistors the generated Ringing signal should stay between the
Ringing voltage rails (GNDA and VBATH). If the ringing signal approaches the rails the signal will distort. Furthermore
excessive power dissipation in the external transistors will also occur. This can be prevented if VBATH is programmed
such that:
⎛
⎜
⎞
⎟
V
> 2 ×
+
+ V
CMR
A
V
ROFF
PEAK
BATH
⎜
⎜
⎟
⎟
⎝
⎠
12.1.3.3.
INTERNAL UNBALANCED RINGING
An unbalanced ringing waveform can be generated by the N682386/87. This feature is enabled by setting
GMV:UBRCn[7] address (0x4D) to “1”. The Ringing signal is only applied to the RING lead and the TIP lead remains
at the programmed VGM voltage. The Ringing signal is programmed as described in Ring Signal Generator section.
A DC offset can be used to provide DC current for Ring Trip Detection. Positive VROFF values will cause the DC offset
point to move closer to ground. The internal unbalanced Ringing waveform is shown below.
Figure 13: Unbalanced Ringing on TIP
The DC offset value should be set to less than half the ringing amplitude or the ringing signal will be clipped. Reverse
unbalanced Ringing waveform can be achieved by setting the GMV:UBRCn[7] address (0x4D) bit to 1 (the TIP lead
oscillates while the RING lead stays constant). In this mode, the polarity of VROFF must also be reversed.
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12.1.3.4.
RING TRIP DETECTION
The Ring Trip Detection mechanism is used to recognize an off-hook event during Ringing. The N682386/87
monitors the Loop current through the Loop current circuitry (available at LPI:ILPCn[11:0] address (0x90)). If the
shadow Linefeed state LS:SLSCn[7:4] address (0x44)indicates a Ringing state the loop current can used to evaluate
whether a Ring Trip event has occurred under two alternative methods - AC path or DC path.
Figure 14: RING Trip Detection Mechanism
For the AC path the AC component of the loop current is determined by passing it first through a full-wave rectifier to
remove the DC component and then through a Low Pass Filter for smoothing. The resulting value is compared to the
AC path Ring Trip Threshold in register RTTA:ARTT[5:0] address (0x55). A subsequent debounce filter is
programmed with an AC Path debounce interval from register RTDBA:ARTDI[7:0] address (0x48). If this interval is
satisfied, a valid Ring Trip is judged to have occurred. However, RTLC:RTDUACn[3] address (0x46) bit records the
unfiltered status of the AC path Ring Trip Detect without regard to the debounce interval.
For the DC path the DC component of the loop current is determined by passing it first through a Low Pass Filter to
remove the AC component and then though a rectifier to ensure a positive value. The resulting value then compared
against the DC path Ring Trip Threshold in register RTTD:DRTT[5:0] address (0x67) and tested against the DC path
debounce interval from register RTDBD:DRTDI[7:0] address (0x68). If this interval is satisfied, a valid Ring Trip is
judged to have occurred. However, RTLC:RTDUDCn[4] address (0x46) bit records the unfiltered status of the DC
path Ring Trip Detect without regard to the debounce interval.
If a RingTrip is judged to have occurred either on the AC path or on the DC path RTLC:RTDCn[1] address (0x46) bit
is set. If enabled, a Ring Trip Interrupt will occur. If LAMC:RGACn[1] address (0x43) is set the channel will
automatically transition into the Active state (Forward or Reverse) upon a valid Ring Trip Detect.
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In general, only one detection path should be utilized at one time by maximizing the Ring Trip Threshold value of the
unwanted path.
Register
Bit(s)
ARTT[5:0]
DRTT[5:0]
ARTDI[7:0]
DRTDI[7:0]
Address
Parameter
Description / Range
RTTA
RTTD
0x55
0x67
0x48
0x68
0x51
0x52
0x65
0x66
RING Trip Threshold AC & DC
0 to 80 mA in 1.27 mA steps
RTDBA
RTDBD
RING Trip Detect Debounce Interval
RING Trip Filter Coefficient
0 to 159 milliseconds
For Digital LPF
RTDFCLD ARTDFC[7:0]
DCHA
RTDFCLD
DCHD
ARTDFC[11:8]
DRTDFC[7:0]
DRTDFC[11:8]
INT1
IE1
RTCn[0]
0x26
0x27
0x46
0x44
0x43
RING Trip Interrupt Pending
RING Trip Interrupt Enable
Status
RTECn[0]
RTDCn[1]
SLSCn[3:0]
RGACn[1]
Enable/Mask
RTLC
LS
RING Trip Loop Closure Detect Status Status
Linefeed Status Control
Ringing Shadow Status
Control
Enable Oscillators and Transitions
automatically
LAMC
Table 17: Registers for RING Trip Detection
The cutoff frequency, fLP, of the Digital LPF is programmed in the Ring Trip Filter coefficient RTDFCA[11:0] and
RTDFCD[11:0]:
⎛
⎞
⎟
⎛
⎞
⎟
f
f
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎜
⎜
12
12
LP
800Hz
LP
800Hz
RTDFCD[11 : 0] = 1 - 2 * π *
* 2
RTDFCA[11 : 0] = 1 - 2 * π *
* 2
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
⎝
⎠
⎝
⎠
Values for RTDFCA, RTDFCD, RTTA, RTTD, RTDBD and RTDBA vary according to the programmed ringing
frequency. The following table can be used for reference.
Ringing
Frequency
RTDFCD[11:0]
RTDFCA[11:0]
RTTA
RTTD
RTDBD
RTDBA
Hz
Decimal
Hex
Decimal
Hex
Decimal
Hex
16.667
20
3561
3453
3132
0x0DE9
0x0D7D
0x0C3C
34 mA
34 mA
34 mA
3600
3600
3600
15 ms
12.5 ms
8.75 ms
0x0C
0x0A
0x07
30
40
50
60
2810
2489
2167
0x0AFA
0x09B9
0x0877
34 mA
34 mA
34 mA
3600
3600
3600
7.5 ms
5 ms
0x06
0x04
0x04
5 ms
Table 18: Recommended RING Trip Values for Ringing
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Dual Programmable Extended Codec/SLCC + SLFC
12.1.4. SUPERVISION (SIGNALING)
12.1.4.1. LOOP CLOSURE DETECTION
The recognition of an off-hook event outside Ringing is controlled by the Loop Closure Detect mechanism. Figure
below shows the functional block.
Figure 15: Lp Closure Detector Block Diagram
Loop current monitoring circuitry provides a Loop Current value which can be read at LPI:ILPCn[11:0] address (0x90)
register. If the shadow linefeed state LS:SLSCn[7:4] address (0x44) indicates any state other than Open or Ringing
state, the Loop Current value is fed to a digital Low Pass Filter to remove unwanted AC components. The cutoff
frequency, fLP, of the Digital LPF is programmed in the Loop Closure Detect Filter coefficient LCDCL:LCDC[11:0]
address (0x50).
⎛
⎞
⎟
f
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎜
12
LP
800Hz
LCDC[11 : 0] = 1- 2 * π *
* 2
⎜
⎜
⎟
⎟
⎝
⎠
The resulting value is compared to a Loop Current Detect Threshold value in register LCT[5:0] address (0x53).
However if the transition is an off-hook to an on-hook transition with hysteresis is enabled LCTHY:LCHYEN[6]=1
address (0x54), the threshold value in LCTHY:LCTOFF[5:0] address (0x54) is used in the comparison. A subsequent
debounce filter is programmed with a debounce interval from register LCDB:LCDI[7:0] address (0x47). In addition, a
special mask counter LCMCNT:LCMCNT[7:0] address (0xAB) can be enabled using RTLC:LCMCn[6] address (0x46)
to guard against detects due to transients on the line, which can occur with reactive ringers. The RTLC:LCDU[2]
address (0x46) bit records the unfiltered status of Loop Closure Detect without regard to the debounce interval or the
Mask count. If the interval is satisfied a valid Loop Closure is judged to have occurred and the RTLC:LCDCn[0]
address (0x46) bit is set. An interrupt can be enabled when the Loop Closure Interrupt occurred.
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Register
LCT
Bit(s)
Address
0x53
Parameter
Description / Range
Current Based: 0-80 mA @ 1.27 mA
Voltage based: 0-93.5V @ 1.484V
Current Based: 0-78.74 mA @ 1.25
mA
LCT[5:0]
Loop Closure Threshold
Loop Closure
LPI
ILPCn[11:0]
LCHYEN[6]
0x90
0x54
LCTHY
Enable Hysteresis
When hysteresis enabled only
Loop Closure Threshold Off-Hook to
ON-HOOK state Enable Hysteresis
opposite transition governed by LCT.
Current Based: 0-80 mA @ 1.27 mA
Voltage based: 0-93.5V @ 1.484V
LCTHY
LCDB
LCTOFF[5:0]
LCDI[7:0]
0x54
0x47
Loop Closure Detect Debounce
Interval
0 to 159 milliseconds
For Digital LPF
Status
LCDCL
DCH
LCDC[7:0]
LCDC[11:8]
0x50
0x52
Loop Closure Filter Coefficient
Loop Closure Interrupt Pending
Loop Closure Interrupt Enable
Loop Closure Detect Status
INT1
IE1
LCCn[1]
0x26
0x27
0x46
0xAB
0x43
LCECn[1]
LCD[0]
Enable/Mask
Status / Enable Voltage-based
Loop Closure
RTLC
LCMC
LAMC
LCMCNT[7:0]
LCDACn[0]
Loop Closure Detect Mask Counter
Enable Automatic Transitions
0 to 319 ms in 1.25 ms steps
Control
Table 19: Loop Closure Detection Registers
If LAMC:LCDACn[1] address (0x43) is set the channel will automatically transition from the Idle (Forward or Reverse),
ON-HOOK Transmission (Forward or Reverse) as well as TIP Open or RING Open into the Active (Forward or
Reverse) state upon a valid Loop Closure Detect.
Voltage based Loop Closure Detect can also be enabled by setting bit RTLC:VBLCCn[5] address (0x46). In this case
the input signal is the Loop Voltage and the thresholds are interpreted as voltages. All other functionality is the same.
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12.1.4.2.
GROUND KEY DETECTION
Ground Key Detect (GKD) senses a DC current imbalance between the TIP and RING terminals when the RING
terminal is connected to ground. This feature is commonly associated with PBX signaling. The feature is enabled in
all states except Ringing. Figure below shows the functional blocks for ground key detector.
Figure 16: Ground Key Detection Circuitry
Ground Key Detection is enabled by setting the GKDFCH:GKDEN[7] address (0x64). The input to the GKD circuitry
is the longitudinal current, which is available in register LGI:ILGCn[11:0] address (0x8C). If the shadow linefeed state
LS:SLSCn[7:4] address (0x44) indicates a non-Ringing state, the longitudinal current is fed to a programmable Digital
Low Pass Filter to remove any unwanted AC components. If fLP is the desired cutoff frequency LPF the Low Pass
Filter Coefficient GFDFC:FCGKD[11:0] address (0x63) is calculated using the following equation:
⎛
⎜
⎞
⎞
⎛
⎜
f
12
LP
800Hz
⎟
⎟
GKDFC : FCGKD[11 : 0]
=
1
2 *
π
*
*
2
⎜
⎝
⎜
⎝
⎟ ⎟
⎠
⎠
A typical value of 10 (GKDFC:FCGKD[11:0] = 00A) is sufficient to filter out any unwanted ac artifacts while allowing
the dc information to pass through the filter.
Register
Bit(s)
Addr
Parameter
Range
Increment Resolution
INT3
IE3
GKDECn[3]
GKDIECn[3]
0x2A Ground Key Interrupt Pending
0x2B Ground Key Interrupt Enable
Yes/No
Yes/No
N/A
N/A
N/A
N/A
Ground Key Detect Debounce
Interval
GKDDT
DTGKD[7:0]
0x62
0 to 320ms
1.25ms
1.25ms
8-bits
12-bits
77.62 mA
77.62 mA
0 to 80 mA
303 uA
18.95 uA
1.27mA
Longitudinal
Current
LGI
ILGCn[11:0]
HGKD[5:0]
0x8C
0x60
GKDH
Ground Key Threshold (enabled)
1.27mA
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Register
Bit(s)
Addr
Parameter
Range
Increment Resolution
GKDL
LGKD[5:0]
0x61 Ground Key Threshold (released)
0x63 Ground Key Filter Coefficient
0 to 80 mA
0 to 4000h
1.27mA
N/A
1.27mA
N/A
GKDFC
FCGKD[11:0]
Table 20: Ground Key Detection Registers
The resulting value from the Low Pass Filter is compared to a Ground Key Detect High Threshold GKDH:HGKD[7:0]
address (0x60) value. Hysteresis is enabled automatically by programming a second threshold GKDL:LGKD[7:0]
address (0x61) to detect when the Ground Key is released. The output of the comparator is connected to a
programmable debounce filter. It can be programmed with a debounce interval GKDDT address (0x62).
12.1.4.3.
CALLER ID AND FSK GENERATION
The N682386/87 provides an optimized Frequency-shift keying (FSK) generator for sending Caller ID information.
Both Bell 202 and ITU-T V.23 standard FSK are supported. The FSK generation supports both Type I and Type II
Caller ID with ability to generate CPE Alerting Signals (CAS tones) of 2130 Hz and 2750 Hz. The linear FSK
waveform generator provides a mechanism to generate the linear code of FSK with continuous phase.
Figure 17: The Architecture of Linear FSK Waveform Generator
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As Figure above illustrates, an 8-byte FIFO substantially reduces CPU intervention in generating FSK. Transmitted
FSK data is placed in the FIFO by writing to the FSKTD:FSK[7:0] address (0x11) register. The writing process can
be controlled by the status bits in the FSKS address (0x12) register which inform on the FIFO’s current status.
FSK transmission is initiated by asserting FSKC:TX[3] address (0x10). The FSK transmit data is clocked out of the
FIFO one byte at a time beginning with the LSB. If package mode is enabled a ‘start bit’ (Space) will automatically be
amended to the head of the FSK transmit data. Furthermore, one or two ‘stop bits’ (Mark) are added to the end of the
FSK transmit data, depending on the setting of FSKC:STOP[2] address (0x10). If package mode is not enabled the
FSK transmit data is transmitted as it appears in the FSK FIFO.
There is one FSK generation engine available inside the N682386/87. An FSK interrupt is generated if the FIFO is
empty. The gain of the FSK signal can also be adjusted using FSKLCR:GAIN[3:0] address (0x13) register.
Register
FSKC
Bit(s)
Address
0x10
Parameter
FSK Control Register
FSK Transmit Data
Description / Range
Control
FSKTD
FSK[7:0]
0x11
Binary signal to be transmitted
FIFO and Shift Register Status
FF[2]
FEP[0]
FSKS
0x12
FSK Status Register
FSKLCR
FSKTCR
INT2
GAIN[3:0]
FSKR[3]
0x13
0x14
0x28
0x29
FSK Gain
See Register Description
Route FSK Data
Status
FSK Route
FSKICn[7]
FSKIECn[7]
Interrupt Status Registers
Interrupt Enable Register
IE2
Enable/Mask
Table 21: Registers for FSK Generation
12.1.4.4.
DTMF GENERATOR
In Dual Tone Multi Frequency (DTMF) two tones are used to generate a DTMF digit. One tone is chosen from four
possible row tones, and one tone is chosen from four possible column tones. The sum of these two tones constitutes
one of 16 possible DTMF digits.
Column frequency
Hz
1209
1336
1477
1633
A
B
C
D
697
770
852
941
1
4
7
*
2
5
8
0
3
6
9
#
Table 22: DTMF frequency mapping
DTMF tone generation can be achieved by using both oscillator 1 and oscillator 2. The table below illustrates the
oscillator coefficient and initial condition which are required for the standard DTMF tone frequencies. For timing
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integrity both oscillators should be enabled simultaneously. Tones can be directed either towards the line or the PCM
interface by programming the RMPC:TRAP[7] bit address (0xC1).
O1CCn[15:0] or O2CCn[17:2]
OmIC[15:0]
Frequency
(Hz)
APK (Volts)
Decimal
Hex
Decimal
Hex
697
770
0.31
0.31
0.31
0.31
0.55
0.55
0.55
0.55
31548
31281
30951
30556
29144
28361
27409
26258
7B3C
7A31
78E7
775C
71D8
6EC9
6B11
6692
1733
1909
2105
2315
2930
3211
3513
3834
06C5
0775
0839
090B
0B72
0C8B
0DB9
0EFA
852
941
1209
1336
1477
1633
Table 22: DTMF frequency settings (APK values for line impedance =600 ꢀ)
For a desired frequency fD the oscillator coefficient for Oscillator m, O1CCn[15:0] or O2CCn[17:2], can be calculated
with the following equation. The following equations can be used for both Narrowband and Wideband. The resulting
hexadecimal coefficients are register data of OSmCH and OSmCL.
⎡
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎡
⎢
⎢
⎢
⎤
⎥
⎥
⎥
2*π*f
2*π*f
D
17
*2
D
15
*2
O2CCn[17 : 0] = cos
O1CCn[15 : 0] = cos
⎢
⎣
⎥
⎦
⎢
⎣
⎥
⎦
16kHz
16kHz
The initial condition for Oscillator m, OSmICL[15:0], can be calculated using the following equation. The following
equations can be used for both Narrowband and Wideband.
⎡
⎢
⎢
⎢
⎤
⎥
⎥
⎥
(m: 1 , 2)
2*π*f
D
15
*2
OmICCn[15 : 0] = A *sin
⎢
⎣
⎥
⎦
16 kHz
Where A is calculated from the desired peak amplitude, APK, in volts in the following equation
APK
A
=
1.5779
The resulting hexadecimal coefficient is input to registers OS2ICH and OS2ICL.
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12.1.4.5.
DTMF DETECTION
Dual Tone Multi Frequency (DTMF) tones consist of a low tone of 697Hz, 770Hz, 852Hz or 941Hz and high tone of
1209Hz, 1336Hz, 1477Hz or 1633Hz. The incoming signal is separated into high-group and low-group tones, and
detected by high-group and low-group tone detectors respectively. When valid data is detected the result is pushed
onto a FIFO which can be read by the host through the SPI interface.
When DTMF detection is enabled channel data is scanned for DTMF tones. Three critical time periods associated
with detection can be programmed. A signal must be present for a minimum of PDT (Present Detect Time) before
tone detection is triggered. Once valid tone is triggered, the tone must be present for ACCT seconds. Once this is
true, DTMF_RDY is active and the received data is pushed onto the FIFO. When the tone is removed, no detection
is triggered for ADT (Absent Detect Time) seconds. DTMFRDT:DTMFRDT[3:0] address (0x3A) is decoded from the
row and column frequency according to Table below. The sensitivity and precision of detection can also be
programmed.
When a DTMF tone is detected the N682386/87 can be configured to generate an interrupt to the host processor for
service.
Figure 18: DTMF Detector - Functional Block Diagram
Column frequency
1209 Hz
1336 Hz
1477 Hz
3
1633 Hz
A
1
2
697 Hz
770 Hz
852 Hz
941 Hz
0x01 hex
0x02 hex
0x03 hex 0x0D hex
4
5
6
B
0x04 hex
0x05 hex
0x06 hex 0x0E hex
7
8
0x08 hex
0
9
0x09 hex
#
C
0x0F hex
D
0x07 hex
*
0x0B hex 0x0A hex 0x0C hex 0x00 hex
Table 22b: DTMF Tone Decoding
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12.1.5. CODEC
The N682386/87 converts the analog transmit signal into a PCM code, either by using µ-Law, A-Law or linear PCM,
and vice versa. A-Law, µ-Law and PCM encoding and decoding is performed according to the recommendations in
the ITU-T G.711 specification. In the linear PCM mode a 16-bit 2s complement data format is used. Details of the
Decode and Encode Characteristics are to be found in Section 11.
12.1.6. HYBRID
12.1.6.1.
AC PATH
The N682386/87 is used for digitizing and reconstructing the human voice. To digitize intelligible voice requires a
signal to distortion ratio (S/D) of about 30 dB over a dynamic range of about 40 dB. N682386/87 meets this
requirement by a large margin. The complete AC signal path block diagram is shown in Figure 3.
12.1.6.1.1.
NARROWBAND TRANSMIT PATH
The gain of this amplifier can be set by programming in APG:ATX[1:0] so that the signal takes advantage of the full
range of the A/D. An anti-aliasing filter also precedes the A/D. The A/D produces a 16-bit linear PCM data stream
sampled at 8 kHz. The A/D not only exceeds ITU G.712 and G.711 but also expands the voice-band cut-off
frequency from a standard 3.4 kHz to 3.6 kHz for enhanced voice quality. High pass filter HXP implements the high-
pass attenuation requirements for signals below 65 Hz. The linear PCM data stream is then amplified by the A/D
digital gain amplifier, programmable from –inf dB to 6 dB and allowing fine gain adjustments down to a resolution of
0.1 dB. When enabled, the DTMF decoder can access this data stream at this point. Finally, if companding is
selected, A-law or μ-law compression reduces the data stream to 8 bits wide. The timeslot on the PCM interface can
be configured with either 8-bit compressed or 16-bit uncompressed data in mind.
12.1.6.1.2.
NARROWBAND RECEIVE PATH
In the receive path, data taken from the PCM highway can be 16-bit uncompressed or A-law / μ-law 8-bit
compressed. In the latter case it is first expanded to 16-bit data. The linear PCM data stream is then amplified by the
D/A digital gain amplifier, programmable from –∞dB to 6 dB and allowing fine gain adjustments down to a resolution
of 0.1 dB. The data stream is then put through an optional high pass filter to filter out signals below 65 Hz and a low-
pass interpolation filter again with 3.6 KHz cutoff frequency for enhanced voice quality before being passed to the
D/A. Finally, the analog signal is amplified by the Analog Receive Amplifier. The gain of this amplifier can be set by
programming in APG:ARX[1:0] before the signal is output from the chip.
The 12-bit digital gain blocks in both the transmit and receive paths provide 11 bits (1024 steps) for fine tuning the
audio signals while the MSB can be used to invert the signal. To calculate the gain setting Y based on the desired dB
setting X, the equation is:
XdB
)
20
Y = 1024 × 10
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Conversely, to calculate the dB value of the gain based on known gain step values, the equation is:
X dB = 20 × log 10 Y
)
1024
The table below contains a sample of possible gain settings.
dB
-∞
-24
-12
-6
Gain
Off
Gain Setting (Y)
0x000
1 / 8
1 / 4
1 / 2
1
0x040
0x100
0x200
0
0x400
6
2
0x7FF
Table 23: Digital Gain Adjust Coefficients and Attenuation weightings
The device exceeds the maximum ITU requirements for frequency response, group delay distortion and signal to
distortion as can be verified from the diagrams in Section 11. Audio signals larger than 0dBm0 can be processed
without clipping in either compression scheme. The maximum PCM code generated for a sine wave is 3.17 dBm0 (μ-
law) or 3.14 dBm0 (A-law).
The N682386/87 overload clipping limits are driven by the PCM encoding process. The presence of a high-pass filter
transfer function ensures at least 30 dB of attenuation for signals below 65 Hz. The Low Pass Filter transfer function
which attenuates signals above 3.6 kHz has to exceed the requirements specified by ITU G.714 and it is
implemented as part of the A/D. The receive path transfer function requirement is very similar to the transmit path
transfer function. We have added the high-pass filter portion as a user controlled option. Pass-band has been defined
between 300 Hz to 3600 Hz. As the PCM data rate is 8 kHz, no frequencies greater than 4 kHz can be digitally
encoded in the data stream.
12.1.6.1.3.
ANALOG TRANSHYBRID BALANCING
The N682386/87 provides fully programmable hybrid balancing to cancel transmit and receive signal echo on the full-
duplex 2-wire pair. The hybrid balancing is performed at the internal 4-wire port. It is measured as the ratio of the
un-cancelled return signal to the reference signal (digital-to-digital gain). Although the ITU standard recommends a
hybrid balance below –18 dB within the voice band, care has been taken to reduce this further in order to avoid
unacceptable voice quality for packet based networks.
The Tran hybrid Balance is internally set to subtract a –6 dB level from the transmit path signal, corresponding to the
ideal case when the impedance matching perfectly matches the subscriber loop. This level can be adjusted from -
2.77 dB to +4.08 dB around this ideal setting by programming HB address (0x41). This register can also be used to
disable the Tran hybrid balancing completely. It should also be noted that Tran hybrid Balance adjustments are
independent of any other gain adjustment stages as the level shift occurs on the transmit path before any gain
stages, as can be seen on Figure 3.
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12.1.6.1.4.
IMPEDANCE MATCHING
The device provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire
return loss requirements.
R2
C
R1
Zline
Figure 19: Characteristic Line Impedance
Figure above illustrates the characteristic line impedance model implemented on-chip. Examples of the standard
impedances which the N682386/87 supports are shown below.
Requirement Impedance Element
(Unit)
R2(Ohm)
Open
Country
R1(Ohm)
600
C(Farad)
Short
US PBX, Korea, Taiwan
Standard
900
Open
Short
Table 24: Examples of Resistive Impedance Matching
Pure Resistive Impedance Settings (for example 600 Ohm and 900 Ohm) can be selected in IM1:ZR1[3:0]. Register
ILIM:ZCPEN[6] address (0x23) allows magnitude of the AC signal to be increased to compensate for the additional
loss at the high end of the audio frequency range. ILIM:ZCPEN[6] should be enabled for Pure Resistive Impedance
Matching cases.
Requirement Impedance Element
(Unit)
R2(Ohm)
Open
Country
R1(Ohm)
600
C(Farad)
1u
US PBX, Korea, Taiwan
Standard
2.2u
150n
100n
100n
100n
310n
115n
230n
120n
900
600
900
270
200
200
100
370
220
Open
Open
Open
750
Japan CO
Bellcore
CTR21
China CO
680
China PBX
560
Japan PBX
1000
620
India, New Zealand
Germany (Legacy)
820
Table 25: Example of Impedance Matching Programming
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For some of Complex Impedance cases where degraded subscriber loop conditions involving excessive line
capacitance leakage are present, this ILIM:ZCPEN[6] bit can also be used as a means for compensation.
12.1.6.1.1.
DAC/ADC AUTOMUTE
When the selected input data source is equal to zero for 1024 consecutive sample cycles, a mute signal is asserted
to the analog front end to mute the line output signal. The control output is de-asserted on the first non-zero sample.
Automute is enabled by setting AMT:AMTENCn[7] address (0x5E). Automute has the capability of selecting two
different options such as either DAC and ADC data or only DAC data by AMTSELCn[6] address (0x5E).
Register
AMT
Bit(s)
Address
0x5E
Parameter
Description / Range
0 = Automute disabled (default)
1 = Automute enabled
AMTENCn[7]
Automute Enable
0 = DAC data+ADC data (default)
1 = DAC data only
AMT
AMTSELCn[6]
0x5E
Automute Select
Table 26: Registers for Automute
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12.1.7. TESTING
The N682386/87 includes extensive test and diagnostics features. Real-time DC linefeed measurements are
available through the several voltages and current registers. GR-909 line test capabilities can also be supported. In
addition five loop back test options, three digital loop backs (DLP1, DLP2 and DLP3) and two analog loop backs
(ALP1, ALP2) are available. Figure 3, details the AC path architecture and also indicates the precise locations of the
test loop backs.
12.1.7.1.
LOOP BACK TESTS
The full analog loop back LB:ALP2Cn[4] address (0x21) allows the testing of almost all the circuitry of both transmit
and receive paths. The compressed 8-bit/16-bit linear transmit data stream is fed back serially to the input of the
receive path expander. The signal path starts with the analog signal at the input of the transmit path and ends with
an analog signal at the output of the receive path. LB:ALP1Cn[3] address (0x21) takes the digital stream at the
output of the A/D in the transmit path and feeds it back to the input of the D/A in the receive path. As with
LB:ALP2Cn[4] address (0x21) the signal path starts with the analog signal at the input of the transmit path and ends
with an analog signal at the output of the receive path.
Full digital loop back LB:DLP1Cn[0] address (0x21) tests practically all transmit and receive path circuitry. The
analog signal at the output of the receive path is fed back to the input of the transmit path by way of the Transhybrid
filter path. The Transhybrid balance may be set to unity gain so that the return signal is not attenuated. A switch in
the receive path is opened when this loop is selected so that no signal appears on the line during this loop back. The
signal path starts with 8-bit/16-bit PCM data input to the receive path and ends with 8-bit/16-bit PCM data at the
output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data.
LB:DLP2Cn[1] address (0x21) takes the digital stream at the input of the D/A in the receive path and feeds it back to
the output of the A/D in the transmit path. The signal path starts with 8-bit/16-bit PCM data input to the receive path
and ends with 8-bit/16-bit PCM data at the output of the transmit path. This loop back option allows the testing of the
digital signal processing circuitry of the N682386/87 independent of any analog signal processing activity. DLP3
loops the digital data stream just beyond the PCM interface, taking the 8-bit/16-bit output of the PCM receive
interface and looping directly to the input of the PCM transmit interface.
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12.1.7.2.
DIAGNOSTICS SUPPORT
The N682386/87 provides a variety of registers which proved both voltages and current values from the line which
are either measured or calculated (see tables 7 and 8). These registers are updated at a rate of 800 Hz or every 1.25
msec. Furthermore, the N682386/87 provides several mathematical and sampling resources to derive additional data
useful in diagnostics (see illustration below). For example, peak to peak measurement results of the loop current
and loop voltage is available in registers ILPP2P:LPIP2PCn[11:0] address (0x9C) and VLPP2P:LPVP2PCn[11:0]
address (0x9B). These measured calculated and derived register values can be used to do GR-909 diagnostic tests.
DCREN
Figure 20: Diagnostics Support Block Diagram
12.1.8. POWER INTERFACE
The N682386/87 utilizes low-cost external components for to perform the DC/DC conversion to the high voltages
required for the subscriber line interface (SLIC). The external discrete circuitry is controlled by on on-chip pulse width
modulation (PWM) driver.
The battery voltage circuit and PWM driver provide a closed loop system for battery voltage regulation. Battery
voltage, VBAT, is monitored and compared to an internal target and adjustments are made accordingly. The target
voltage will change, depending on different architectures and such factors as the linefeed state. As illustrated in
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Figure below for example, if the device is operating in the constant voltage region the VBAT target is a combination of
VOV, VOH and VGM. A combination of coarse and fine adjustments ensures rapid convergence on the target voltage.
Two different DC/DC conversion architectures are supported and described in the following sections. Two different
internal PLL master clocks (13.824 MHz, or 27.648 MHz) can be selected depending on the settings of
PON:CDCC[7] address (0x22) and PLLS:PLLCM address (0x04). The width of the pulse generated by the PWM is
programmed in PWMT:PT[7:0] address (0x49). A minimum off-time is programmable in the DDCC:DCOFF[7:0]
address (0x4A) to allow sufficient time for stored energy to be transferred to the output capacitor. For reference
monitoring the actual PWM pulse width can be checked in the read only PWCT:PWCTCn[7:0] address (0xB5)
register. For example, if the PWCT indicates a maximum pulse width consistently, this might indicate an overload
condition or a short circuit. The values for PWMT, DDCC and PWCT are based on multiples of the internal PLL
master clock period.
Register
PON
Bit(s)
CDCC[7]
Address
0x22
Parameter
Description / Range
Inductor Architecture
Sets PWM Pulse Width for
DC/DC converter
Sets PWM minimum Off time
for DC/DC convertor
Step size and initial value dependant on
internal PLL clock selection
Step size and initial value dependant on
internal PLL clock selection
PWMT
DDCC
PT[7:0]
0x49
0x4A
DCOFF[7:0]
PWCT
DCTR
OHV
PWCTCn[7:0]
VTR[7:0]
0xB5
0x77
0x4C
0x4D
PWM Count Register
DC/DC Target Voltage
VOH On-Hook Voltage
For Reference (Read only)
0V to -93.5V in 1.484V increments
0V to -93.5V in 1.484V increments
0V to -93.5V in 1.484V increments
VOHCn[5:0]
VMVCn[5:0]
GMV
VGM Ground Margin Voltage
VBATH High Battery Voltage
VBHV
VBLV
VBATHCn[5:0]
VBATLCn[5:0]
0x4E
0x4F
0V to -93.5V in 1.484V increments
VBATH Low Battery Voltage
VOV
VOVCn[3:0]
VBCn[7:0]
0x56
0x80
VOV Offset Voltage
0V to 24 V in 1.484 V increments
0V to –94.6V in 0.371 V increments
BATV
VBAT Battery Voltage
Table 27: Registers associated with DC/DC Conversion
12.1.8.1.
DC/DC CONVERSION (INDUCTOR)
A current sensing input for the DC/DC converter provided. The PWM pulse will be muted during each PWM cycle if
the current exceeds a predetermined threshold level. This prevents the external discrete transistors from damage
due to overload conditions. Similarly, the supply voltage is also monitored. The PWM pulse will be muted during
each PWM cycle if the supply voltage falls below a predetermined level. The PWM pulse will also be muted if the
battery voltage exceeds 10% of the maximum value. If this threshold is too high, an external clamp can be added in
the application. See application diagram.
The Figure below illustrates how voltage regulation occurs in the Forward Active state.
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VOH
ILIM
RLOOP
0V
VGM
VTIP
Constant V
Region
VOH
Constant I
Region
VBATL
|VTIP– VRING
|
VOV
VOV:TR=0
VRING
VBAT
VOV
V
CIVR-v4
Figure 21: Voltage Tracking in Forward Active State
The values for VGM, VOH and VOV are set in VCMR, OHV, and VOV registers respectively. When operating in the
constant voltage region the VBAT is simply the sum of these three settings (VGM + VOH + VOV). If the Loop current
attempts to exceed ILIM the constant current region is entered. In this case the values for VOV and VGM are maintained
but the VOH is adjusted to track the RLOOP, which adjusts VBAT accordingly. If tracking is enabled, VOV:TR=1, tracking
will continue below VBATL. Otherwise, tracking will stop and VBAT will not go lower than VBATL. A similar mechanism is
implemented in the Reverse Active state.
During the Ringing state, the VBAT must be increased to accommodate the ring signal. Conventionally VBAT is set to a
fixed value of VBATH. However, the discrete linefeed circuit dissipates significant power particularly when a large REN
load is applied. As an alternative the N682386/87 allows a dynamic battery target to be selected by setting the
LCTHY:DBTR[7] address (0x54) bit. In this case, VBAT will dynamically track the actual ring signal, minimizing the
power dissipation and improving efficiency during Ringing. Dynamic Battery Target is available only for DC/DC
conversion architecture.
time
0V
V
V
V
TIP
TIP
VBATH /2
V
RING
RING
VBATH
VBATH
Ring
DC
Volts
Figure 22: Dynamic Battery Target
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12.1.8.2.
EXTERNAL BATTERY SWITCHING
The N682386/87 device can also operate from two or three external battery supplies. The external battery supply
architecture can be enabled by connecting DCL1 & DCL2 to Vdd and DCH1 & DCH2 to Vss. This will also power
down the on-chip PWM controllers. In this case the N682386/87 utilizes the DCPn and the DCNn pins to control the
selection of externally supplied VBATR, VBATH and VBATL for VBAT by means of a external circuit such as the
one illustrated below.
V BAT
VBATL
VBATH
DCP
DC-to-DC
VBATR
Control
DCN
Figure 23: Three Voltage External Battery switching
The VBAT voltage selection is dependent on the linefeed state and the relationship is programmable. The mapping of
the DCNn pins output to the linefeed state can be uniquely programmed in the XBSDCN address (0x6A) register as
illustrated in the table shown under 0x6A and 0x6B register description page. The XBSDCP address (0x6B) register
serves the same purpose for the DCPn pins. The combination of DCNn, DCPn outputs and the external selection
circuitry allows either VBATR, VBATH or VBATL to be selected in any state.
When two external battery supplies are used (VBATH and VBATL) VBAT selection can be controlled by the one pin
alone. Therefore, DCNn should be used to control the external battery switching.
Figure 24: Two Battery Supply Control Circuit
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12.2. DIGITAL INTERFACE
12.2.1. CLOCK GENERATION
The N682386/87 will generate the necessary internal clock frequencies from the BCLK input. BCLK must be
synchronous to the 8 kHz frame sync clock and run at one of the following rates:
Binary Clock
256 kHz
Decimal Clock
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
512 kHz
768 kHz
1.024 MHz
1.152 MHz
1.536 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz.
The frame sync can either be supplied externally or it can be generated internally by the N682386/87, by setting the
PCMFS:FSS[2] address (0x05) bit to “1”. If frame sync is supplied externally (PCMFS:FSS=0), the ratio of the BCLK
rate to the frame sync rate is determined via a counter clocked by BCLK which can be read at the PLLS:BCFS[4:1]
address (0x04). This value is used to control the internal PLL, which multiplies BCLK appropriately to generate the
internal clock frequency required to run the internal circuitry.
If the frame sync is supplied internally (PCMFS:FSS=1), the user must set PCMFS:BF[3:0] to indicate BCLK so that
an appropriate multiple is calculated to generate the required internal frequency. If the frame sync is generated
internally its width can be selected by programming PCMFS:IFST[3] address (0x05).
¡
¡
1-bit clock long (for Short Frame Sync, GCI and IDL modes)
8-bit clocks long (for 8-bit Long Frame Sync mode)
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12.2.2. PCM INTERFACE
N682386/87 supports a flexible PCM interface structure which can be configured to perform multiple industry
standard PCM modes. Data is received serially through the PCMR pin and transmitted serially through the PCMT
pin.
Timeslots for data transmission and reception are independently configured using registers. Two registers, one for
each direction combination, control the selection of the start point for the data timeslot:
¡
¡
¡
TTS[9:0]: Transmit Timeslot Start
RTS[9:0]: Receive Timeslot Start
The start point is defined in terms of a particular the BCLK period within the frame. Once the start of the timeslot
is assigned the transfer will continue sequentially.
¡
¡
For an 8-bit transfer the timeslot will run from the start point to the start point + 7 BCLK cycles.
For a 16-bit transfer the timeslot will run from the start point to the start point + 15 BCLK cycles.
By setting the specific timeslot start points, the N682386/87 can be programmed to support many industry standard
PCM interfaces including many Long Frame Sync and Short Frame Sync variants, IDL2 8-bit, 10-bit, B1 and B2
channel timeslots. The table below illustrates this by showing how some standard interface modes may be
programmed.
TTS [7:0]
RTS [7:0]
BCLK PERIODS
PER DATA BIT
Clocking mode
Long Frame Mode
Short Frame Mode
GCI Mode
1
1
2
1
0x00000 (slot 1)
0x00001 (slot 1)
0x00000
IDL Mode
0x00001
Table 28: Example Standard Interface modes
However N682386/87 allows even more flexibility. It can support BCLK up to 8192 kHz, or up to 1024 BCLK periods
per 125usec frame. Therefore 10-bit timeslot assignment registers have sufficient flexibility to assign any timeslot
start point within the frame. Care should also be taken when dealing with a BCLK lower than 8192 kHz to ensure that
the timeslot start point is within the boundary of the frame, including sufficient headroom for the complete timeslot.
For example, if BCLK is 512 kHz there are 64 BCLK cycles within the frame. However, for all modes except Short
Frame Sync the highest valid start position for 8-bit PCM data would be 56, sufficient for the full byte to be
accommodated within the frame. For 16-bit data the highest start position would be 48. In Short Frame mode the
LSB can be located up to the first BCLK of the next frame so the highest valid position is 56 for 8-bit or 48 for 16-bit.
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The PCMT pin is high impedance except for the duration of the PCM transmit. PCMT will return to high impedance
either on the negative edge of BCLK during the LSB, or on the positive edge of BCLK following the LSB depending
on the setting of PCMC:TRICn[2] address (0x00). Tri-stating on the negative edge allows the transmission of data by
multiple sources in adjacent timeslots without the risk of driver contention.
12.2.2.1.
WIDEBAND AND NARROWBAND OPERATION
Nuvoton’s newest design in the Pro-X product line is a Narrowband and Wideband audio codec. The N682386 is
limited to Narrowband audio codec communication, meaning 8kHz sampling and 8kHz frame sync with frame sync
master mode capability. The Narrowband audio codec communication is compatible with the W681388, N681386, &
W684386. The user could write to a reserved register that is used for Wideband operation on N682386 without
effect.
The N682387 is capable of both Narrowband and Wideband audio communication by simply setting bits on the
register selected by PCMFS:WBENCn[1] address (0x05). Each channel has a unique wideband enable register,
such that the wideband & narrowband operation can be controlled independently for each channel. The Narrowband
mode is be limited to 8kHz sampling and 8kHz or 16kHz frame sync. The Wideband mode of operation is limited to
16kHz sampling and 8kHz or 16kHz frame sync.
The two different frame sync is selected by PLLS:FSRATE[5] address (0x04). 8kHz frame sync is selected by setting
PLLS:FSRATE[5]=0 and 16kHz is selected by setting PLLS:FSRATE[5] =1. There is no frame sync master mode
supported in wideband operation. The table below shows the modes of operation.
PCMFS:WBENCn[1]
Band of Operation
(0x05)
WBENC1
WBENC2
Channel 1 Channel 2
0
0
1
1
0
1
0
1
Narrow
Narrow
Wide
Narrow
Wide
Narrow
Wide
Wide
Table 29: Wideband or Narrowband Hardware Selection
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12.2.2.2.
TOGGLING BETWEEN WIDEBAND AND NARROWBAND
It is not recommended to toggle between Wideband and Narrowband when 16kHz frame sync is used, since it could
unlock the PLL. However, the architecture may allow it when the pin is toggled at the right time.
For Wideband, using 8kHz frame sync, the user can toggle PCMFS:WBENCn[1] address (0x05) register, while
keeping the frame sync and bit clock running as is. The internal filter and PCM interface of the N682387 will switch to
adjust to the Narrowband /Wideband mode of operation. This could lead to temporary glitches on the output while
switching the filter. One could briefly mute the DAC and ADC path through the firmware code to prevent the glitches
from being audible.
12.2.2.3.
PCM INTERFACE IN WIDEBAND OPERATION
PCM INTERFACE 8KHZ FRAME SYNC
12.2.2.3.1.
During Wideband operation and 8kHz frame sync the PCM data will be transmitted and received as two samples per
frame sync. The location of the MSB of each sample on the PCM bus with respect to the frame sync pulse is
programmable through two independent time slot registers. The time slots need to be programmed such that they
are 62.5usec apart. An internal data ready signal will be generated to synchronize with the filters to indicate the data
is ready and to synchronize the sample rate. The approximate timing diagram is shown below.
125usec
FS
BCLK
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
PCMT
PCMR
62.5usec
62.5usec
L
S
B
L
S
B
M
S
B
M
S
B
M
S
B
Data
Ready
TS1
TS2
approximate
Figure 25: Wideband 8kHz Frame Sync PCM interface
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12.2.2.3.2.
PCM INTERFACE 16KHZ FRAME SYNC
During Wideband operation and 16 kHz frame sync the PCM data will be transmitted and received as one sample per
frame sync. The location of the MSB of each sample on the PCM bus with respect to the frame sync pulse is
programmable through one time slot register. The second timeslot register is not used in this case. Below is shown
the approximate timing diagram for this case.
62.5usec
62.5usec
FS
BCLK
PCMT
PCMR
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
L
S
B
M
S
B
M
S
B
M
S
B
Data
Ready
TS1
TS1
approximate
Figure 26: Wideband 16kHz Frame Sync PCM interface
12.2.2.4.
PLL & PRESCALER IN WIDEBAND OPERATION
The prescaler determines the external bit clock frequency based on the ratio of the frame sync and bit clock
frequency. When the frame sync switches to 16kHz (Wideband) it needs a signal to indicate this change in order to
determine the correct bit clock frequency. In wideband and narrowband mode using 8kHz frame sync it doesn’t need
to adjust. Therefore, the PLL & prescaler operation can be summarized by the following truth table:
PLLWBANDEN
(switches prescaler)
WBENCn[1]
FSRATE[5]
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘1’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
‘0’
‘1’
0
0
0
0
0
0
0
1
Table 30: PLL and Prescaler in Wideband
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12.2.3. SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) is one of the widely accepted communication interfaces implemented in
Nuvoton’s Pro-X portfolio. SPI is a software protocol allowing operation on a simple 4-wire bus where the data is
transferred MSB first. The SPI interface consists of a clock (SCLK), chip select (CSb), serial data input (SDI), and
serial data output (SDO) to configure all the internal register contents. SCLK is static, allowing the user to stop the
clock and then start it again to resume operations where it left off. The SCLK can run any speed up to internal PLL
master clock (13.824 MHz, 24 MHz, or 27.648 MHz depending on selected architecture). In the case of a write,
DATA is sent by the micro-controller. In the case of a read, DATA is read by the micro-controller. To write data to
the chip the controller must follow the following sequence
There are two different Read/Write architecture
8-bits Data Read/Write
The 8-bits data Write consists of 8-bits of Device Address, 8-bits of Register Address, and 8-bits of DATA.
The 8-bits data Read consists of 8-bits of Device Address, 8-bits of Register Address, and 8-bits of DATA.
16-bits Data Read/Write
The 16-bits data Write consists of 8-bits of Device Address, 8-bits of Register Address, and 16-bits of DATA.
The 16-bits data Read consists of 8-bits of Device Address, 8-bits of Register Address, and 16-bits of DATA.
The first byte, Device Address, sent to the N682386/87 from the host controller, following a CSb going HIGH to LOW,
contains read/write bit, the Device type Identifier bits (wideband and narrowband selection information), and the burst
mode. The 8-bits of the Device Address are explained below.
Name
C7
C6
C5
C4
C3
C2
C1
C0
Device Address
RW
0
0
0
0
CH
XP
BST
Table 31: Device Address Bit pattern
Bit Value
Bit
Location
Bit
Name
Bit Description
0
1
Burst mode allows multiple consecutive registers to be written to or
0
1
read using in a single sequence. The complete register address BST
space (256 locations) can be read and written to using burst mode.
Disable
Enable
Control bit to select 12-Bits monitoring
XP
Bits[11-4]
Bits[3-0]
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Bit Value
Bit
Location
Bit
Name
Bit Description
This is a channel selection bit.
0
1
2
3 - 6
7
CH
-
0
1
These bits must be set to “0”
Read/Write control bit
-
-
RW
Write
Read
The CH[1:0] bits in the control byte is the selection of the 12-Bits monitoring extension.
CH1
XP
Channel
Command
0
0
1
1
0
1
0
1
1
1
2
2
Register Address (8-bits)
2nd byte of 12-Bits monitoring
Register Address (8-bits)
2nd byte of 12-Bits monitoring
Table 32: 12-bit byte Selection
12.2.4. READ/WRITE SEQUENCE (8-BIT OR 16-BIT)
The device is accessed via the SDI input with data clocked in on the rising edge of SCLK. DATA transfer is
synchronized to the SCLK input. DATA is clocked out onto SDO on the falling edges of SCLK. SCLK is the only
reference of SDI and SDO pins. The SDO pin will go tri-state when goes CSb HIGH.
The first two pictures below illustrate the Read/Write Sequence for an 8-bit architecture. Both Read/Write sequences
consist of three 8-bit transmissions of Device address, Register Address and DATA. Each 8-bit transmission starts
with the falling edge of the CSb line. At the end of every 8-bit transmission is complete the CSb transitions from LOW
back to HIGH. After a valid Device Address and Register Address for Read, 8-bit Data is shifted out on the SDO line.
The last two pictures below illustrate the Read/Write Sequence for a 16-bit architecture. Both Read/Write sequences
consist of two 16-bit transmissions, the first 16-bit transmission consisting of Device address and Register Address
bytes and the second 16-bit transmission consists of Data. Each 16-bit transmission starts with the falling edge of the
CSb line. At the end of every 16-bit transmission CSb transitions from LOW back to HIGH. After a valid Device
address and Register Address for Read, 16-bits of Data is shifted out on the SDO line. Since all the registers are 8-
bits long, the least significant byte of the 16-bit Data word should be ignored. If additional clocks are sent by the
master the device will provide the same data when BST is LOW.
The SPI state machine soft resets whenever CSb asserts during an operation on an SCLK cycle that is not a multiple
of eight, including burst mode. This is a mechanism for the controller to force the state machine to a known state
when the controller and the device are out of synchronization.
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CSb
DATA [7:0]
DEVICE ADDRESS
ADDRESS
SCLK
1
1
1
SDI
2
3
4
5
6
7
8
2
3
4
5
6
7
8
2
3
4
5
6
7
8
SDO
Hi-Z
Figure 27: Register write operation through a 8-bit SPI port
ADDRESS
CSb
DATA [7:0]
DEVICE ADDRESS
SCLK
1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
SDI
1
2
3
4
5
6
7
8
SDO
Figure 28: Register read operation through a 8-bit SPI port
Figure 29: Register write operation through a 16-bit SPI port
Figure 30: Register read operation through a 16-bit SPI port
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12.2.5. SPI DAISY CHAIN
When using multiple N682386/87 devices, SPI programming can be accomplished using a daisy chain architecture
which allows all chips to share one CSb and one SCLK. To enable the daisy chain configuration, the DSY pin should
be set HIGH. In this configuration the SDO pin will no longer tri-state in order to pass the serial data to the next
device in the chain. The daisy chain is facilitated by an internal 16-bit shift register in each device. After CSb goes
LOW, SDI is clocked into this shift register at each rising edge of SCLK. At each falling edge of SCLK the contents of
the shift register are shifted to SDO. SDO can then be connected to the SDI of the next chip in the daisy chain
sequence. Each device evaluates the data in the internal shift register at the rising edge of CSb. Figure 35 illustrates
a three-device daisy chain arrangement.
SDO
CSb
Micro-
Controller
SDI
SDO Chip1
SDI
SDO Chip2
SDI
SDO Chip3
SDI
SCLK
Figure 31: Three Chip Daisy Chain connection
For daisy chain operation, the length for Device address, Register Address and CSb should be 16xD bits, where D is
the total number of devices in the daisy chain. Figure below illustrates the Device address, and Register Address
structure for three-device daisy chain architecture. Three 16-bit Device address and Register Address words are
sent sequentially, the first word for the first device in the daisy chain, the second word for the second device, etc.
Device addressing is still enabled during daisy chain mode. Therefore, if a command needs to be ignored an
unmatched device address can be sent with the command. If a command needs to be ignored a NOP can be sent
with the command by sending a ‘1’ for any bit of C6 to C3.
CSb
SCLK
0
8
16
32
48
Chip 1
Device/Register Address
Chip 2
Device/Register Address
Chip 3
Device/Register Address
SDI
Figure 32: Device/Register Address for Three Device Daisy Chain application
Figure below illustrates the DATA structure for three-device daisy chain architecture. Three 8-bit DATA bytes are
sent sequentially, the first byte for the first device in the daisy chain, the second byte for the second device, etc.
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Figure 33: DATA for Three Device Daisy Chain application
12.2.6. SPI BURST MODE
The N682386/87 also supports a burst mode which allows multiple consecutive registers for the same channel to be
written to or read using a single Device address and Register address with BST=1. The complete channel register
address space (256 locations) can be read/ written to using burst mode.
16Bit
(8 Bit CMD+ 8 Bit Address)
CSb
8Bit
8Bit
8Bit
8Bit
8Bit
8Bit
BST=1
Figure 34: Burst mode operation (BST=1)
The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher address after each byte of data is shifted out. When the
highest address is reached, the address counter rolls over to address (0x00) on the same channel allowing the read
cycle to be continued indefinitely.
When the BST bit in Device address is set during a write operation the N682386/87 will accept multiple 8-bit DATA
blocks which will be written to sequential address locations beginning with the address specified in Register address.
The length of the burst is determined by the Chip Select (CSb). Note that if there is a location within the sequence
without a register assignment a dummy byte should be sent at the corresponding location in the DATA sequence.
Similarly during a burst read operation the device will output Data as long as CSb is LOW. The device will output a
dummy byte (0x00) when locations without register assignments are within the sequence. Register bits
PCMC:BDAEN[3] address (0x00) and PCMC:BCEN[1] address (0x00) is be used to determine the broadcasting
preferences. By default, after a reset, the device will accept all burst write commands without decoding bits C3 to C6
or channel. If this is not desired, the user can send a single command and data cycle to enable either or both the
channel and C3 to C6 decoding. Once the PCMC:BCEN[1] address (0x00) bit is set, the device will only accept burst
write data for the selected channel. Once the PCMC:BDAEN[3] address (0x00) bit is set, the device will only accept
burst write data when C3 to C6 are ‘0’. During burst mode read operation, the channel specific data registers will be
output for only the selected channel and with C3 to C6 all ‘0’.
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12.2.7. SPECIAL READ SEQUENCE FOR 12-BIT WIDE REGISTER
Although N682386/87 has 8-bit wide register map, it includes some special registers for ADC Monitoring for accurate
monitoring. N682386/87 includes a special SPI Read feature. This read feature allows the user to read the 12-bits
wide registers. It can be used in the 8-bits or 16-bits wide register data read mode. One important thing to remember
is that BURST Mode cannot be use for 12-bit register read.
12.2.7.1.
12-BIT READ SEQUENCE
Two separate read sequences are required to successfully read 12-bit register. Whether it is 8-bits or 16-bits wide
register data N682386/87 still requires two bye read sequence. Selection of the channel and the second byte read is
shown on the above table.
8-bits or 16-bits Data Read sequence for 12-bts ADC monitoring data
Sequence for Channel 1
1st byte Read
Device Address bits[2:1] – 00 binary
Register Address any of the ADC monitoring registers
The 8 bits[7:0] of the first read data are the bits[11:4] of the 12-bits register
2nd byte Read
Device Address bits[2:1] – 01 binary
Register Address any of the ADC monitoring registers
The 4 MSB bits[7:4] of the second read data are the bits[3:0] of the 12-bits register
Sequence for Channel 2
1st byte Read
Device Address bits[2:1] – 10 binary
Register Address any of the ADC monitoring registers
The 8 bits[7:0] of the first read data are the bits[11:4] of the 12-bits register
2nd byte Read
Device Address bits[2:1] – 11 binary
Register Address any of the ADC monitoring registers
The 4 MSB bits[7:4] of the second read data are the bits[3:0] of the 12-bits register
Revision 1.3
Page 72 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 35: SPI 12-bits Read sequence
12.3. POWER-ON RESET
The following Power-on Reset procedure is recommended for the N682386/87.
¡
The Reset pin (RESETb) should be held LOW as power is applied.
This allows logic levels to rise so that all output pins and all registers reach their default values while the system
is in reset mode. This process should take less than 100 μs if the external supply is settled.
¡
¡
¡
¡
Clocking should be applied (BCLK and, if necessary, FS)
Ensure CSb and SCLK are set HIGH before setting RESETb HIGH
Wait at least 400μs to ensure the PLL is locked. The status can be read in register PLLS:PL[0] address (0x04)
Initialize all appropriate country specific registers and mode registers according to specific operating mode
Revision 1.3
Page 73 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
12.4. INTERRUPT HANDLING
A number of events are capable of generating an interrupt. However, an interrupt signal is generated only if the bit
corresponding to that particular interrupt event is enabled in the Interrupt Enable Register. In that case the
corresponding bit is set in the Interrupt Status Register. An umbrella Interrupt Vector Register, INTV, indicates which
Interrupt Status Registers have bits currently set. This vectoring allows an interrupt service routine to quickly
determine which interrupt event has just occurred.
Once the interrupt has been serviced the Interrupt Status Register can be cleared by writing a one to that respective
bit. The Interrupt Vector Register INTV bits will be cleared when there are no pending interrupts in the corresponding
Interrupt Status Registers
Register
Name
Address
Parameter
Description / Range
Vectors the interrupt location
INTV
0x24
0x26
0x27
0x28
0x29
0x2A
0x2B
Interrupt Vector Register
Interrupt Status Register 1
Interrupt Enable Register 1
Interrupt Status Register 2
INT1
IE1
Power Alarms, RING Trip and Loop Closure Interrupts
Enables for Register 1 interrupts
INT2
IE2
FSK, DTMF, RING and Oscillator Interrupts
Interrupt Enable Register 2 for Enables for Register 2 interrupts
INT3
IE3
Interrupt Status Register 3
Interrupt Enable Register 3
Temperature Interrupts
Enables for Register 3 interrupts
Table 33: Interrupt Registers
Revision 1.3
Page 74 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
13. GENERAL DESCRIPTION FOR N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC)
The N681622 is the first supporting chip of its kind in the Nuvoton’s Pro-X line of products. It integrated the high
voltage linefeed circuit. It can be used with N681386, N681387, N682386 and N682387. N681622 is designed to
reduce substantial board space compared to the existing discrete implementation of the linefeed circuit. The
N681622 operates from a 3.3V supply voltages. A small QFN20 package with exposed pad for thermal
considerations allows for easy assembly and PCB design.
13.1. FUNCTIONAL DESCRIPTION FOR N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC)
The N681622 integrates the following six transistors of the discrete line driver: QT1, QT2, QT3, QR1, QR2, and QR3.
In the following register description there are some references to currents or voltages for these individual transistors.
For the N681622 the important transistors are QT1, QT3, QR1, QR3. The following diagram shows a virtual circuit
showing the equivalent positions of the these transistors inside the N681622.
Figure 36: N681622 Eqivalent Internal diagram
Revision 1.3
Page 75 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14. REGISTER DESCRIPTION
There are 2 distinct register sets, one for each channel in the N682386/87. Some of the registers are shared
between the two channels, some are specific to each channel, and address 0x00 (PCMC) of channel1 register set is
partially shared. Register set 2 is for channel 2 which consists of channel specific registers only. There are three
different types of registers in register set 1.
¡
¡
¡
Type 1, address 0x01 (TTLNB) exists in all two register sets because it is channel specific register.
Type 2, registers that are shared or common to both channels does not require channel information.
Type 3, is a partially shared register in channel1 register set.
For the purpose of this document all registers and register bits will be stated with The letters “Cn” where “n” can be
channel 1 or 2 and also follow the same register address definition. Please refer to the SPI command description on
how to address the various channels. For maximal forward compatibility, it is recommended that “0” be written to
reserved bits.
“RES” in the register map means Reserved.
ASYNC means the device does not require a clock to be able to read or write
12-Bits – specific register has 12-bits
Addr
(Dec)
Addr
(Hex)
Default
(Hex)
ASYNC
/12Bit
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
PCM CONTROL REGISTERS
GCLK BDAEN
TTSNBCn[7:0]
ASYNC
(D5-D0)
0
1
2
3
4
5
6
7
8
9
00
01
02
03
04
05
06
07
08
09
PCMC
TTLNB
RTLNB
TCH
CMS[1:0]
BM
TRICn
BCEN
ENCn
00
00
00
50
D9
00
00
C0
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R
ASYNC
ASYNC
ASYNC
RTSNBCn[7:0]
RTSWBCn[9:8]
TTSWBCn[9:8]
RTSNBCn[9:8]
TTSNBCn[9:8]
ASYNC
(D7,D5)
ASYNC
(D7-D1)
PLLS
PLLCM
CLK1544EN
FSRATE
BCFS[3:0] (RO)
IFST
PL (RO)
SRES
PCMFS
SIREV
DVID
BCF[3:0]
FSS
WBENCn
SIREV[7:0]
VER[7:0]
R
TTLWB
RTLWB
TTSWBCn[7:0]
RTSWBCn[7:0]
FSK REGISTERS
POL
R/W
R/W
ASYNC
ASYNC
16
17
18
19
20
10
11
12
13
14
FSKC
FSKTD
FSKS
PE
PEN
PTYP
RES
TX
STOP
FF
SPEC
EN
FEP
00
00
03
00
00
R/W
R/W
R
FSK[7:0]
RES
FSKLCR
FSKTCR
RES
RES
GAIN[3:0]
R/W
R/W
FSKR
RES
FMT
RES
Diagnostics
21
22
23
24
25
26
27
28
29
30
15
16
17
18
19
1A
1B
1C
1D
1E
DIAGCTRL0
DIAGCTRL1
DIAGCTRL2
DIAGCTRL3
DIAGCTRL4
DIAGCTRL5
DIAGCTRL6
DIAGCTRL7
DIAGCTRL8
DIAGFIFO0
FIFOIP
DCREN
DCRAC
ACLPFEN
DCLPFEN
FIFOEN
SIGNED
DIAGCH
DIAGEN
00
00
00
00
00
00
00
00
00
00
TRACNEG
ACSEL[2:0]
TRDCNEG
DCSEL[2:0]
VHI[7:0]
RES
SELT[2:0]
DCRRC
VHI[11:8]
VLO[7:0]
DCRDC
TMREN
RES
TIMER[7:0] (RO)
VOL[11:8]
RES
TIMER[12:8] (RO)
ACDP[11:0] (RO)
DCDP[11:0] (RO)
RO
RO
FIFO0[31:0] (RO)
Revision 1.3
Page 76 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Addr
(Dec)
Addr
(Hex)
Default
(Hex)
ASYNC
/12Bit
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
31
1F
DIAGFIFO1
FIFO1[31:0] (RO)
00
RO
SYSTEM REGISTERS
DACFFCn[1:0]
32
33
34
35
20
21
22
23
PHF
LB
RES
DACPOLCn
CDCC
DACSRCn
ADCFFCn[1:0]
ADCHPCn
DLP2Cn
DACHPCn
DLP1Cn
DCCCn
00
00
01
00
R/W
R/W
R/W
R/W
ADCPOLCn
RES
ALP2Cn
ALP1Cn
DLP3Cn
DACPPCn
ILMGAIN
PON
ILIM
RES
ADCPPCn
CALTR1
ZCPINV
ZCPEN
RNGGAIN
RIPS
TINS
CALTR0
INTERUPT REGISTERS
36
38
39
40
41
42
43
24
26
27
28
29
2A
2B
INTV
INT1
IE1
RES
IR3C2
IR2C2
PAT1Cn
PAT1ECn
RICn
IR1C2
PAR1Cn
PAR1ECn
RACn
RES
IR3C1
PAT2Cn
PAT2ECn
O2ACn
IR2C1
LCCn
IR1C1
RTCn
00
00
00
00
00
00
00
R/W
R/W
RO
PAT3Cn
PAT3ECn
FSKICn
FSKIECn
PAR3Cn
PAR2Cn
PAR2ECn
O2ICCn
PAR3ECn
DTMFICn
DTMFIECn
LCECn
O1ICCn
O1IECn
RTECn
O1ACn
O1AECn
TMP
INT2
IE2
R/W
R/W
R/W
R/W
RIECn
RAECn
O2IECn
O2AECn
INT3
IE3
RES
RES
GKDICn
GKDIECn
RES
RES
TMPE
DTMF REGISTERS
DTMFFDEV[1:0]
RES
RES
DTMFTHR[15:8]
48
49
51
52
53
54
55
56
58
59
60
61
62
30
31
33
34
35
36
37
38
3A
3B
3C
3D
3E
DTMFCTRL1
DTMFCTRL2
DTMFST
DTMFENCn
ADCOSELCn
DTMFTC[3:0]
00
00
01
01
00
00
00
00
00
00
00
00
00
R/W
R/W
RO
DTMFCLRCn
DTMFEMTCn
DTMFTHRH
DTMFTHRL
DTMFPDT
DTMFADT
DTMFACT
DTMFRDT
DTMFRFH
DTMFRFL
DTMFCFH
DTMFCFL
R/W
R/W
R/W
R/W
R/W
RO
DTMFTHR[7:0]
DTMFPDT[7:0]
DTMFADT[7:0]
DTMFACT[7:0]
DTMFRDYCn
DTMFSTCn
RES
DTMFRDTCn[3:0]
DTMFRF[15:8]
DTMFRF[7:0]
DTMFCF[15:8]
DTMFCF[7:0]
LINE REGISTERS
RES
RO
RO
RO
RO
64
65
66
67
68
69
70
71
72
73
74
76
77
78
79
80
81
82
83
84
85
86
87
94
40
41
42
43
44
45
46
47
48
49
4A
4C
4D
4E
4F
50
51
52
53
54
55
56
57
5E
APG
HB
RAMPCn
DACG
PRECn
ADCG
RES
VOHZCn
ARXCn[1:0]
ATXCn[1:0]
AHYBCn[2:0]
00
1B
00
07
00
00
00
00
00
FF
76
20
02
32
10
00
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
RO
RES
VCMR
LAMC
LS
VCMRCn[5:0]
PAACn
LSCn[3:0]
RES
RGACn
LCDACn
LCDCn
SLSCn[3:0]
LCL
LGCRTCn
LGCRRCn
LGCMCn[1:0]
VBLCCn
LGCRTCn
RTDUDCn
LCDI[7:0]
RES
RTDUACn
ILMCn[2:0]
RTDCn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RTLC
LCDB
RTDBA
PWMT
DDCC
OHV
RES
LCMCn
LCDUCn
ARTDI[7:0]
PT[7:0]
DCOFF[7:0]
RES
SBCn
RES
RES
VOHCn[5:0]
GMV
UBRCn
VGMCn[5:0]
VBATHCn[5:0]
VBATLCn[5:0]
VBHV
VBLV
LCDCL
RTDFCLD
DCHD
LCT
XBATRCn
RES
LCDC[7:0]
ARTDFC[7:0]
ARTDFC[11:8]
LCDC[11:8]
RW
RES
RES
LCT[5:0]
LCTOFF[5:0]
ARTT5:0]
RO
LCTHY
RTTA
VOV
DBTR
LCHYEN
R/W
R/W
R/W
R/W
R/W
RES
RES
TRCn
VOVCn[3:0]
TONDC[4:0]
AMTTHRCn[5:0]
DCTON
AMT
AMTENCn
AMTSELCn
GROUND KEY DETECTION REGISTERS
Revision 1.3
Page 77 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Addr
(Dec)
Addr
(Hex)
Default
(Hex)
ASYNC
/12Bit
Name
D7
D6
D5
D4
D3
XTBOTCn[1:0]
D2
D1
D0
XTBATCn[1:0]
R/W
95
96
5F
60
61
62
63
64
65
66
67
68
6A
6B
6E
77
XBTC
GKDH
RES
ASQHCn
CBPCn
XTBEN
00
R/W
RO
RES
RES
HGKD[5:0]
LGKD[5:0]
00
00
20
02
32
10
00
00
00
00
00
00
C8
97
GKDL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
98
GKDDT
GKDFCL
GKDFCH
RTDFCLD
DCHD
DTGKD[7:0]
99
FCGKD[7:0]
100
101
102
103
104
106
107
110
119
GKDEN
RES
FCGKD[11:8]
DRTDFC[7:0]
RES
DRTDFC[11:0]
RTTD
RES
XRTR
DRTT5:0]
RTDBD
XBSDCN
XBSDCP
LOAD
DRTDI[7:0]
DCNXB[7:0]
DCPXB[7:0]
RES
LOAD
DCTR
VTR[7:0]
MONITOR
120
121
122
123
124
125
126
127
78
79
7A
7B
7C
7D
7E
7F
RTMNT
LCMNT
MNT5
MNTRTCn[7:0]
MNTLCCn[7:0]
00
00
00
00
00
00
00
00
RO
RO
RO
RO
RO
RO
RO
RO
MNTQ1Cn[7:0]
(QT1)
MNT7
MNTQ2Cn[7:0]
MNTQ3Cn[7:0]
MNTQ4Cn[7:0]
MNTQ5Cn[7:0]
MNTQ6Cn[7:0]
(QR1)
(QR2)
(QT2)
(QR3)
(QT3)
MNT9
MNT11
MNT13
MNT15
LINE CONTROL REGISTERS
VOLTAGE REGISTERS
VBCn[7:0]
128
129
130
131
132
80
81
82
83
84
BATV
VTIP
02
000
000
02
RO
RO
RO
RO
RO
VTIP[11:0]
12-Bits
12-Bits
VRING
QT3V
QR3V
VRING[11:0]
QT3VCn[7:0] (VTVE) (VQT2)
QR3VCn[7:0] (VRVE) (VQR2)
TRANSISTOR CURRENT REGISTERS
QT3ICn[11:0]
02
133
134
135
136
137
138
85
86
87
88
89
8A
QT3I
QR3I
QT1I
QT2I
QR1I
QR2I
005
003
003
003
003
003
RO
RO
RO
RO
RO
RO
12-Bits
12-Bits
12-Bits
12-Bits
12-Bits
12-Bits
QR3ICn[11:0]
QT1ICn[11:0]
QT2ICn[11:0]
QR1ICn[11:0]
QR2ICn[11:0]
LOOP SUPERVISION
ILGCn[11:0]
140
141
142
143
144
145
146
147
148
149
150
153
154
155
156
8C
8D
8E
8F
90
91
92
93
94
95
96
99
9A
9B
9C
LGI
LPV
001
001
002
000
001
1A
RO
RO
RO
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
12-Bits
12-Bits
12-Bits
12-Bits
12-Bits
VLPCn[11:0]
TIPI
ITLPCn[11:0]
RINGI
LPI
IRLPCn[11:0]
ILPCn[11:0]
POL
RES
P2PENCn
ILGPCn
SCMCn[11:0]
ILPPCn
IRLPPCn
ITLPPCn
VLPPCn
SCM
02
12-Bits
VEQT1
VQT1
VEQR1
VQR1
TEMP
VBGAP
VLPP2P
ILPP2P
VEQT1Cn[7:0]
VQT1Cn[7:0]
VEQR1Cn[7:0]
VQR1Cn[7:0]
TS[7:0] (Vtemp)
VBG[7:0]
00
00
00
00
00
4A
LPVP2PCn[11:0]
LPIP2PCn[11:0]
000
000
12-Bits
12-Bits
POWER ALARM LPF POLE REGISTERS
Revision 1.3
Page 78 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Addr
(Dec)
Addr
(Hex)
Default
(Hex)
ASYNC
/12Bit
Name
D7
D6
D5
D4
PALCNTCn[7:0]
D3
D2
D1
D0
R/W
159
160
161
162
163
164
165
166
167
9F
A0
A1
A2
A3
A4
A5
A6
A7
PALCNT
PALPQ2
PALPQn
PALPQ3
PALPQHn
PALPQH2
PATHQ2
PATHQn
PATHQ3
00
RO
Q2C[7:0]
Q1C[7:0]
Q3C[7:0]
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Q1C[11:8]
Q2C[11:8]
Q3C[11:8]
RES
Q3C12
Q1C12
Q2C12
Q2TH[7:0]
Q1TH[7:0]
Q3TH[7:0]
IMPEDENCE MATCHING REGISTERS
168
169
170
171
172
173
A8
A9
AA
AB
AC
AD
IM1
IM2
ZCCn[3:0]
ZRnCn[3:0]
00
00
00
00
00
00
R/W
R/W
R/W
RO
RES
ZSWCn
ZCPCn[1:0]
ZR2CCn[3:0]
THAT
LCMCNT
CC
THAT[7:0]
LCMCNT[7:0]
CBGSW
RES
CTRIM[2:0]
RO
OS2RPD
O2RPDCn[7:0]
CALIBRATION REGISTERS
RO
175
176
177
AF
B0
B1
CAL1
CAL2
CAL3
SDATCn[3:0]
TVTE1Cn[3:0]
SCMTCn[3:0]
VBATTCn[3:0]
79
97
79
RO
RO
RO
SDBTCn[3:0]
RVTE1Cn[3:0]
DC OFFSET REGISTERS
DACSFC
180
181
B4
B5
IQTROS
PWCT
HISENSECn
BTVR
ILFDB
RES
00
00
R/W
RO
PWCTCn[7:0]
TONE GENERATION REGISTERS
O2ZCCn
192
193
C0
C1
OSN
RES
O1ZCCn
O2ECn
RES
O1ECn
08
00
R/W
R/W
RMPC
TRAP
LBACCn
R1ENCn
RES
TORCn
OSCILLATOR INITIAL CONDITION & COEFFICIENT REGISTERS
194
195
196
197
198
199
200
201
C2
C3
C4
C5
C6
C7
C8
C9
OS1ICL
OS1ICH
OS2ICL
OS2ICH
OS1CL
OS1CH
OS2CL
OS2CH
O1ICCn[7:0]
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
O1ICCn[15:8]
O2ICCn[7:0]
O2ICCn[15:8]
O1CCn[7:0]
O1CCn[15:8]
O2CCn[9:2]
O2CCn[17:10]
OSCILLATOR ACTIVE & INACTIVE TIME REGISTERS
202
203
204
205
206
207
208
209
CA
CB
CC
CD
CE
CF
D0
D1
OS1ATL
OS1ATH
OS2ATL
OS2ATH
OS1ITL
OS1ITH
OS2ITL
OS2ITH
O1ONCn[7:0]
O1ONCn[15:8]
00
00
00
00
00
00
00
00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
O2ONCn[7:0]
O2ONCn[15:8]
O1OFF[7:0]
O1OFF[15:8]
O2OFF[7:0]
O2OFF[15:8]
GENERAL TONE GENERATION REGISTERS
ROSCn[5:0]
220
221
222
223
DC
DD
DE
DF
ROFFS
ADCL
DACL
DGH
O2CCn[1:0]
00
00
00
44
R/W
R/W
R/W
R/W
ADCCn[7:0]
DACCn[7:0]
DACCn[11:8]
ADCCn[11:8]
DC-DC CONFIGURATION
224
225
226
227
E0
E1
E2
E3
ST0L0
ST1L0
ST2L0
ST0L1
RES
RES
ST0L0[3:0]
ST1L0[4:0]
ST2L0[4:0]
ST0L1[3:0]
02
04
06
08
R/W
R/W
R/W
R/W
RES
RES
Revision 1.3
Page 79 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Addr
(Dec)
Addr
(Hex)
Default
(Hex)
ASYNC
/12Bit
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
228
229
230
231
232
233
234
235
236
237
238
239
243
244
245
248
249
250
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F3
F4
F5
F8
F9
FA
ST1L1
ST2L1
SK0L0
SK1L0
SK2L0
SK0L1
SK1L1
SK2L1
WM0
RES
RES
ST1L1[4:0]
ST2L1[4:0]
10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
19
1F
04
02
1F
04
02
08
10
18
53
00
00
10
00
00
00
SK0L0[7:0]
SK0L1[7:0]
RES
RES
SK1L0[5:0]
SK2L0[4:0]
RES
SK1L1[5:0]
RES
RES
RES
RES
SK2L1[4:0]
WM0[4:0]
WM1[4:0]
WM2[4:0]
WM1
WM2
XSTEP
IMRAM
IMDEL
IMEN
PWMTC
XS[3:0]
IMDATA
IMHYBDCCn[3:0]
RES
IMB3PDCCn[3:0]
IMENCn IMR1MCn
IMRW
RES
IMPM
RES
RES
RES
W
W
ADCLPFBYP
Cn
HBLPFBYPC
n
251
FB
IMEN
RES
00
R/W
Decimal to Hex Conversion
To convert decimal value to hex value divide the decimal number by 16, and write the remainder on the side as the
least significant digit. This process is continued by dividing the quotient by 16 and writing the remainder until the
quotient is 0. When performing the division, the remainders which will represent the hex equivalent of the decimal
number are written beginning at the least significant digit (right) and each new digit is written to the next more
significant digit (the left) of the previous digit. Consider the number 175 decimal.
Division
175 / 16
Quotient
10 = A
Remainder
15 = F
Hex Number
AF
N682386/87 includes some bits that can be written without the PLL running while some bits requires the PLL running
for the write to be effective. Any register that states the ASYNC bits means that specific DO NOT require the PLL
running for the write to be effective.
Revision 1.3
Page 80 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.1. PCM CONTROL REGISTERS
14.1.1. PCM CONTROL REGISTER
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared (D0, D2)
Async (D0 - D5)
0x00
PCMC
CMS[1:0]
BM
GCLK
BDAEN
TRICn
BCEN
ENCn
The letters “Cn” stands for channel number 1 or 2. The following table explains the PCM control register bits.
Bit Value
Bit
Location
Bit
Name
Bit Description
0
1
0
1
PCM path including digital receive path
Burst Channel decode enable
ENCn
Disable
Enable
Single Channel
Both Channels In
Parallel
BCEN
2
3
4
5
Tri-state PCMT LSB
TRICn
BDAEN
GCLK
BM
Positive edge of BCLK Negative edge of BCLK
Burst Device Address decode enable
GCI Clock Format (per data bit)
Must be set appropriate to PCMC:CMS selection
All Devices in Parallel
1 BCLK
Single Device
2 BCLK
8-bit mode
16-bit mode
There are three different CODEC Modes to choose from and they are as follows:
CODEC MODE SELECTION
CMS1
CMS0
Mode
A-Law
0
0
1
1
0
1
0
1
u-Law
Linear
Reserved
14.1.2. RECEIVE/TRANSMIT TIMESLOT (WIDEBAND AND NARROWBAND)
Addr.
0x01
0x02
0x03
Name
TTLNB
RTLNB
TCH
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
TTSNBCn[7:0]
RTSNBCn[7:0]
Async
0x00
RTSWBCn[9:8]
TTSWBCn[9:8]
RTSNBCn[9:8]
TTSNBCn[9:8]
0x00
The letters “Cn” stands for channel number 1 or 2. Transmit and receive timeslot are expressed in number of BCLK
cycles in a 10-bit word. For Narrowband, Transmit Timeslot Start, TTSNBCn[9:0], determines the start point for the
timeslot on the PCM interface for data in the transmit direction and the Receive Timeslot Start, RTSNBCn[9:0],
determines the start point for the timeslot on the PCM interface for data in the receive direction. Timeslot Channel
High, TCH address (0x03) bits are the two most significant bits of the 10-bit word for both transmit and receive
timeslot, TCH:RTSWBCn[9:8] and TCH:TTSWBCn[9:8] for Wideband and TCH:RTSNB[9:8] and TCH:TTSNB[9:8] for
Narrowband.
Revision 1.3
Page 81 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.1.3. PLL STATUS REGISTER
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xD9
Shared
Async (D7, D5)
0x04
PLLS
PLLCM
CLK1544EN FSRATE
BCFS[3:0] (RO)
PL (RO)
PL[0] and BCFS[4:1] are status bits which means they are READ ONLY bits in this register. Any write to these bits
will be ignored. FSRATE[5], CLK1544EN[6], and PLLM[7] are READ/WRITE bits.
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
5
6
PLL Lock Status (RO)
Frame Sync Rate
PL
FSRATE
CLK1544EN Disabled
Not Locked Locked
8kHz
16kHz
Enable clock 1.544MHz
Enabled
With an external 8 kHz Frame Sync set (PCMFS:FSS=0), PLL Bit Clock Frequency Status, BCFS[3:0] bits will show
the value of BCLK according to the following table. Not all clocks are supported by 16KHz frame sync [ * ].
Bit Clock Frequency
DC/DC CLK Mode
DC-DC Clock
Type
PON:CDCC[7]
BCFS[3]
BCFS[2]
BCFS[1]
BCFS[0]
BCLK(Hz)
PLLCM[7]
(Addr – 0x22)
1
0
0
0
0
256
0
0
13.824MHz
0
0
0
0
0
1
1
0
512
768
0
1
1
0
1
27.648MHz
0
0
1
1
1
1
1000*
1024
1152
1536
0
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
1544*
2000
2048
4000
4096
8000
8192
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NA
Revision 1.3
Page 82 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.1.4. PCM FREQUENCY SETTING REGISTER
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared
Async (D7- D1)
0x05
PCMFS
BCF[3:0]
IFST
FSS
WBENCn
SRES
The following table explains the PCM Frequency Setting register bits.
Bit Value
Bit
Location
Bit Description
Soft Reset
Bit Name
0
1
0
SRES
WBENCn
FSS
Disable
Enable
FS = 8kHz
(Narrowband)
FS = 16kHz
(Wideband)
1
2
3
Band Select
Frame Sync Source
Internal Frame Sync Type
External
Internal
Short (fixed width Long (fixed width
1 BCLK) 8 BCLK)
IFST
When an internal 8 kHz Frame Sync is used (PCMFS:FSS=1) these bits should be programmed with the value of
BCLK Frequency, BCFS[3:0], according to the following table.
Bit Clock Frequency
BCF
[4]
BCF
[3]
BCF
[2]
BCF
[1]
BCLK
(Hz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
256
512
768
1000
1024
1152
1536
1544
2000
2048
4000
4096
8000
8192
NA
Revision 1.3
Page 83 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.1.5. SILICON REVISION ID REGISTER (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xEF
Shared
0x06
SIREV
SIREV[7:0]
Silicon revision ID Register is a READ ONLY register.
14.1.6. DEVICE VERSION ID REGISTER (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
NA
Shared
0x07
DVID
VER[7:0] (RO)
Device Version ID Register is a READ ONLY register.
Device
N682386
N682387
VER[7:0]
0x41
0x49
14.1.7. TIMESLOT (WIDEBAND)
Addr.
0x08
0x09
Name
TTLWB
RTLWB
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xC0
Shared
Async
TTSWBCn[7:0]
RTSWBCn[7:0]
0xC0
The letters “Cn” stands for channel number 1 or 2.
Transmit and receive timeslot are expressed in number of BCLK cycles in a 10-bit word. For Wideband, Transmit
Timeslot Start, TTSWBCn[9:0], determines the start point for the timeslot on the PCM interface for data in the
transmit direction and the Receive Timeslot Start, RTSWBCn[9:0], determines the start point for the timeslot on the
PCM interface for data in the receive direction. The two most significant bits of the 10-bit word are located on register
TCH address (0x03).
Revision 1.3
Page 84 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.2. FSK REGISTERS
14.2.1. FSK CONTROL REGISTER
Addr.
Name
D7
PE
D6
D5
D4
D3
TX
D2
D1
D0
EN
Default
0x00
Shared
PEN
PTYP
POL
0x10
FSKC
STOP
SPEC
The following table explains the FSK Control Register bits.
Bit
Location
Bit Value
Bit
Name
Bit Description
FSK Encoder
0
1
0
1
2
EN
Disable
Bell 202
1 Stop bit
Stop
Enable
FSK Specification
SPEC
STOP
ITU-T V.23
2 Stop bits
Start
Number of STOP bits
FSK Encoder start to transmit
data from FSK FIFO
3
TX
Transmission Transmission
4
5
6
7
FSK bit stream polarity
Parity Bit Type
POL
PTYP
PEN
PE
Non-inverted
Even parity
Disable
Inverted
Odd parity
Enable
Parity Bit Enable
FSK Package Format
Disable
Enable
FSK Package Format automatically amends a ‘start bit’ (Space) to the head of the FSK transmit data and one or two
‘stop bits’ (Mark) to the end, depending on programming of FSKC:STOP. “Res” in the register map means Reserved.
Bell 202
1200 Hz
2200 Hz
ITU-T V.23
1300 Hz
Mark ‘1’
Space ‘0’
2100 Hz
14.2.2. FSK TRANSMIT REGISTER
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared
0x11
FSKTD
FSK[7:0]
FSK Transmit Register, FSK[7:0], is a WRITE ONLY register. Data written to this register will be placed into the
Internal FIFO for transmission. Note: Reading this register will always give 0x00 as data.
Revision 1.3
Page 85 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.2.3. FSK STATUS REGISTER (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x03
Shared
FF
(RO)
FEP
(RO)
0x12
FSKS
RES
RES
“RES” in the register map means reserved bit(s).
FSK Status Register is a READ ONLY register. The following table explains the FSK Status Register bits.
Bit
Location
Bit Value
Bit
Name
Bit Description
0
1
FSK FIFO not empty (Last set of
bit stream finished transmitting)
0
2
FSK FIFO Empty Pending
FSK FIFO Full
FEP
FF
FSK FIFO is empty
FIFO Full
FSK FIFO not Full
14.2.4. FSK LCR REGISTER
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
Shared
0x00
0x13
FSKLCR
RES
GAIN[3:0]
“RES” in the register map means reserved bit(s).
The gain level is specified in linear values and referenced to the maximum linear PCM level (+3.14 dBm0). The
following table contains the adjusted levels and the attenuated value of the correspondent maximum PCM level.
FSK Encoder output signal level
Attenuation to max
PCM level
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-∞
-23.512
-17.499
-13.978
-11.48
-9.542
-7.956
-6.617
-5.458
-4.434
-3.52
-2.692
-1.937
-1.242
-0.599
0
Revision 1.3
Page 86 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.2.5. FSK TCR REGISTER
Addr.
0x14
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared
FSKTCR
RES
FSKR
RES
FMT
RES
“RES” in the register map means reserved bit(s).
The following table explains the FSK TCR Register bits.
Bit Value
Bit
Bit
Name
Bit Description
Location
0
1
1
3
Fast Mode
FSK Route
FMT
FSKR
Disabled
Enabled
Route
Channel1
Route
Channel2
Revision 1.3
Page 87 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.3. DIAGNOSTIC REGISTERS
14.3.1. DIAGNOSTIC CONTROL 0
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared
0x15
DIAGCTRL0
FIFOIP DCREN ACLPFEN DCLPFEN FIFOEN SIGNED DIAGCH DIAGEN
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
1
Enable Diagnostic Function
DIAGEN
DIAGCH
Disabled
Enabled
Enable
Channel1
Enable
Channel2
Enabled diagnostics
2
3
Converts unsigned Source Register data to signed data
Enable DIAGFIFO0 / DIAGFIFO1 FIFO Structure.
Enable Low pass filter in the DC path.
SIGNED
FIFOEN
Disabled
Disabled
Enabled
Enabled
4
The DC Path LPF utilizes the Loop Closure Detect LPF and is DCLPFEN
Disabled
Enabled
programmed in LCDCL: LCDC[11:0].
Enable Low pass filter in the AC path.
5
6
The AC Path LPF utilizes the AC Ring Trip Detect LPF and is ACLPFEN
programmed in RTDFCLD:ARTDFC[11:0].
Disabled
Disabled
Enabled
Enabled
Enable DC Removal function in the AC path
DCREN
Determines Data routed to DIAGFIFO0 / DIAGFIFO1 FIFO
Structure
DIAGCTRL0:DIAGEN must be set.
NOTE: DIAGCTRL0:FIFOEN will be turned on automatically if ADC
PCM Data is selected.
DC/AC
Diagnostics
Output
ADC PCM
data
7
FIFOIP
14.3.2. DIAGNOSTIC CONTROL 1
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
Shared
0x16
DIAGCTRL1
TRACNEG
ACSEL[2:0]
TRDCNEG
DCSEL[2:0]
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
VTIP, VRING and SCM are forced to negative values when selected
on the DC diagnostics path.
VTIP, VRING and SCM are forced to negative values when selected
on the AC diagnostics path.
3
7
TRDCNEG
TRACNEG
Disabled
Disabled
Enabled
Enabled
NOTE: Some diagnostic operations required signed operation, for example: DC removal.
ACSEL[6:4]: Select source register for the AC path diagnostics
DCSEL[2:0]: Select source register for the DC path diagnostics
Revision 1.3
Page 88 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Select AC/DC source for Diagnostics
ACSEL2
DCSEL2
ACSEL1
DCSEL1
ACSEL0
DCSEL0
Source
Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VTIP
VRING
LPV
SCM
TIPI
RINGI
LPI
LGI
14.3.3. DIAGNOSTIC CONTROL 2, 3, 4, AND 5
Addr.
0x17
0x18
0x19
0x1A
Name
D7
D6
D5
D4
D3
D2
D1
VHI[11:8]
VLO[11:8]
D0
Default
0x00
DIAGCTRL2
DIAGCTRL3
DIAGCTRL4
DIAGCTRL5
VHI[7:0]
Shared
Shared
Shared
Shared
0x00
RES
SELT[2:0]
DCRRC
0x00
VLO[7:0]
0x00
DCRDC
DCRAC
RES
Select source for timing measurement.
Source
Register
SELT2
SELT1
SELT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VTIP
VRING
LPV
SCM
TIPI
RINGI
LPI
LGI
VHI[11:0]: Determines VHI for DIACNTRL:TIMER[12:0] measurement.
Range, Step Size and number of valid bits same as Source Register determined by SELT.
VLO[11:0]: Determines VLO for DIACNTRL:TIMER[12:0] measurement.
Range, Step Size and number of valid bits same as Source Register determined by SELT.
Revision 1.3
Page 89 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Bit Value
Bit Name
Bit
Location
Bit Description
0
1
5
6
DC Removal RC Time Constant
DCRRC
DCRAC
1.25/64ms 1.25/32ms
DC Removal Accelerated Convergence.
Disable
Disable
Enable
Enable
Enable DC Removal output to DC Path LPF in addition to the
normal connection to the AC Path LPF
7
DCRDC
DIACNTRL0:DCREN must be set.
Notes:
-
When enabled DC Removal is able to estimate the DC level of a selected source data and pass an AC only
signal to the AC Path LPF.
-
When DC Removal is enabled both DIAGCTRL5:TRDCNEG and DIAGCTRL5:TRACNEG need to be turned
on if VTIP or VRING or SCM are selected as the source register.
14.3.4. DIAGNOSTIC CONTROL 6 AND 7 (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x1B
DIAGCTRL6
TIMER[7:0] (RO)
Shared
Shared
0x1C
DIAGCTRL7
TMREN
RES
TIMER[12:8] (RO)
TIMER[12:0] are status bits which means they are READ ONLY bits in this register. Any write to these bits will be
ignored. TMREN[5] is READ/WRITE bit.
Bit Value
Bit(s)
Location
Bit
Name
Bit Description
0
1
Reset Timer - It will increase
by at the rate of 800hz when
the monitored source is
The timer will accumulate the
time when the voltage of the
selected source (by SELT) falls
between VLO and VHI.
7
Capacitor Charging Timer
TMREN
between VLO and VHI.
Capacitor Charging Timer
TMREN[7] (0x1C)
Minimum
0 ms
Maximum
10.24 s
Increment
1.25 ms
Range
Revision 1.3
Page 90 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.3.5. DIAGNOSTIC CONTROL 8 (READ ONLY)
Name D7 D6 D5 D4
Addr.
D3
D2
D1
D0
Default
00
DCDP[7:0] (RO)
Shared
Shared
RES
RES
DCDP[11:8] (RO)
ACDP[11:8] (RO)
0x1D DIAGCTRL8
ACDP[7:0] (RO)
00
DCDP[11:0]: DC Diagnostic Path Output
ACDP[11:0]: AC Diagnostic Path Output
NOTE: This register is structured to be read in 4 byte burst
14.3.6. DIAGNOSTIC FIFO 0 AND FIFO1 (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
00
FIFO0[7:0] (RO)
FIFO0[15:8] (RO)
FIFO0[23:16] (RO)
FIFO0[31:24] (RO)
FIFO1[7:0] (RO)
Shared
Shared
Shared
Shared
0x1E DIAGFIFO0
0x1F DIAGFIFO1
00
00
00
FIFO1[15:8] (RO)
FIFO1[23:16] (RO)
FIFO1[31:24] (RO)
DIAGFIFO0 and DIAGFIFO1 are structured as Dual FIFO Structures. Each FIFO has 16 entries, each entry
structured as a 4 byte structure illustrated above. When one FIFO is full an interrupt is generated and diagnostic data
is collected in the alternative FIFO. In Diagnostic Mode (DIAGCTRL0:DIAGEN) DIAGFIFO0 uses the Ring Trip
Detect Interrupt mechanism and DIAGFIFO1 uses the Loop Closure Detect Interrupt mechanism.
When DIAGCTRL0:FOFIP[7] is set to 0, DIAGFIFO0 and DIAGFIFO1 are used to store DC Diagnostic Path and AC
Path Output Data
-
FIFOn[15:0], n=0,1 contains DCDP[11:0]: DC Diagnostic Path Output in the lower 12 bits
FIFOn[31:16], n=0,1 contains ACDP[11:0]: AC Diagnostic Path Output in the lower 12 bits
NOTE: DC Diagnostic Path and AC Path Data is input to each FIFO at 800 Hz.
-
When DIAGCTRL0:FOFIP[7] is enabled DIAGFIFO0 and DIAGFIFO1 are used to store ADC PCM Data
-
FIFOn[15:0], n=0,1 contains 16-bit ADC PCM data
FIFOn[31:16], n=0,1 is not output
In this case the Maximum burst read is 32 bytes per FIFO.
NOTE: PCM Data is input to each FIFO at the sampling frequency (Wideband or Narrowband).
-
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.4. SYSTEM REGISTERS
14.4.1. PCM HPF (HIGH PASS FILTER)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x20
PHF
RES
DACSRCn
DACFFCn
ADCFFCn
ADCHPCn DACHPCn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Bit Name
DACHPCn
0
1
0
1
6
PCM Transmit HPF (DAC)
PCM Receive HPF (ADC)
LPF for Wideband (DAC)
Enable
Enable
Enable
Disable
ADCHPCn
DACSRCn
Disable
Disable
High Pass Filter Select DAC
High Pass Filter Select ADC
ADC HPF
DAC HPF
DACFFCn[5] DACFFCn[4]
ADCFFCn[3] ADCFFCn[2]
Select (Hz)
Select (Hz)
0
0
1
1
0
1
0
1
20
40
80
0
0
1
1
0
1
0
1
20
40
80
160
160
High pass filter cutoff is only programmable in the Wideband mode. Bit-6 should only be used in Wideband mode but
disabled (set to 1) for Narrowband.
14.4.2. LOOP BACK CONTROL REGISTER
Addr. Name
0x21 LB
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
DACPOLCn ADCPOLCn RES ALP2Cn ALP1Cn DLP3Cn DLP2Cn DLP1Cn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
The following table explains the Loop Back Control Register bits.
Bit Value
Bit
Location
Bit Description
Digital loop back (D/A to A/D)
Bit Name
0
1
0
1
DLP1Cn
DLP2Cn
Disable
Enable
Digital loop back (LP interpolation filter to LP decimation
filter)
Disable
Enable
2
3
4
6
7
Digital loop back (A/u law expander to A/u law compander)
Analog Loop back 1
DLP3Cn
ALP1Cn
ALP2Cn
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Analog Loop back 2
Invert ADC input Polarity
ADCPOLCn Disable
DACPOLCn Disable
Invert DAC Output Polarity
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.4.3. POWER ON
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x01
0x22
PON
CDCC
RES
DACPPCn ADCPPCn DCCCn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s). The following
table explains the Loop Back Control Register bits.
Bit
Location
Bit Value
Bit Description
Bit Name
0
1
0
1
2
DC/DC Power Control Circuitry DCCCn
DCDC On
ADCPPCn Disable
DACPPCn Disable
DCDC OFF
Enable
A/D Power Path
DAC Power Path
Enable
DC/DC CLK Mode
DC-DC Clock Type
PLLS:PLLCM[7]
(Addr: 0x04)
CDCC[7]
1
0
0
13.824MHz
0
1
1
1
0
1
1
27.648MHz
This table gives the PLL Period.
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.4.4. LINEFEED TRIM
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x23
ILIM
ZCPINV
ZCPEN
RNGGAIN
RIPS
TINS
ILMGAIN
CALTR1
CALTR0
CALIBRATION STATE
CURRENT ADJUST
CALTR1
CALTR0
Current
0
0
1
1
0
1
0
1
20mA
19.6mA
19.4mA
20.4mA
Bit
Location
Bit Value
Bit Description
Bit Name
0
1
Ring Limiting Gain Adjust strength of Ring
limiting Impacts noise
2
3
ILIMGAIN
TINS
Default
2 x default
Idle State Battery Current Stops TIN in idle
for lower power
Default current
Low current
Idle State Battery Current Stops RIP in idle
for lower power
4
5
RIPS
Default current
Default
Low current
High gain
Increase Ring feedback gain in idle and
Ring state for more accuracy
RNGGAIN
6
7
Line Capacitor Compensation
Line Capacitor Compensation
ZCPEN
ZCPINV
Disabled
Subtract
Enabled
Add
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.5. INTERRUPT REGISTERS
14.5.1. INTERRUPT VECTOR LOW (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x24
INTV
RES
IR3C2
IR2C2
IR1C2
RES
IR3C1 IR2C1
IR1C1
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Interrupt Vector Register is a READ ONLY register. Each bit in this register will be cleared when there are no
pending interrupts reported in the corresponding interrupt status registers.
Bit Value
Bit
Location
Bit
Name
Bit Description
0
No INT
No INT
No INT
No INT
No INT
No INT
1
0
1
2
4
5
6
Interrupt Vector 1 Low channel 1
Interrupt Vector 2 Low channel 1
Interrupt Vector 3 Low channel 1
Interrupt Vector 1 Low channel 2
Interrupt Vector 2 Low channel 2
Interrupt Vector 3 Low channel 2
IR1C1
IR2C1
IR3C1
IR1C2
IR2C2
IR3C2
INT1
INT2
INT3
INT1
INT2
INT3
14.5.2. INTERRUPT STATUS REGISTER 1
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x26
INT1
PAT3Cn PAR3Cn PAT1Cn PAR1Cn PAR2Cn PAT2Cn
LCCn
RTCn
The letters “Cn” stands for channel number 1 or 2. This register displays all the Power Alarm and the Loop Closure
interrupt of the device. A pending interrupt is represented by a HIGH “1” in the respective bit. Writing 1 to that
respective bit clears the pending interrupt.
Bit
Location
Bit Value
Bit
Name
Bit Description
RING Trip
0
No INT
No INT
No INT
1
0
1
2
3
4
5
6
7
RTCn
INT
Loop Closure
LCCn
INT
INT
INT
INT
INT
INT
INT
Power Alarm QR2
Power Alarm QT2
Power Alarm QT1
Power Alarm QR1
Power Alarm QR3
Power Alarm QT3
PAT2Cn
PAR2Cn No INT
PAR1Cn No INT
PAT1Cn
PAR3Cn No INT
PAT3Cn
No INT
No INT
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.5.3. INTERRUPT ENABLE REGISTER 1
Addr Name
0x27 IE1
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
PAT3ECn PAR3ECn PAT1ECn PAR1ECn PAR2ECn
PAT2ECn
LCECn
RTECn
The letters “Cn” stands for channel number 1 or 2. This register enables all the Power Alarm and the Loop Closure
interrupt of the device. An interrupt can be enabled by writing a HIGH “1” in the respective interrupt bit.
Bit
Location
Bit Value
Bit Description
RING Trip
Bit Name
0
Masked
Masked
1
0
1
2
3
4
5
6
7
RTECn
LCECn
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Loop Closure
Power Alarm QR2
Power Alarm QT2
Power Alarm QT1
Power Alarm QR1
Power Alarm QR3
Power Alarm QT3
PAT2ECn Masked
PAR2ECn Masked
PAR1ECn Masked
PAT1ECn
Masked
PAR3ECn Masked
PAT3ECn Masked
14.5.4. INTERRUPT STATUS REGISTER 2
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x28
INT2
FSKICn DTMFICn
RICn
RACn
O2ICn
O2ACn
O1ICn
O1ACn
The letters “Cn” stands for channel number 1 or 2.
Bit
Location
Bit Value
Bit Description
Bit Name
0
1
0
1
2
3
4
5
6
Oscillator 1 Active Timer
Oscillator 1 Inactive Timer
Oscillator 2 Active Timer
Oscillator 2 Inactive Timer
Ringing Active Timer
Ringing Inactive Timer
DTMF Initialize
O1ACn
O1ICn
O2ACn
O2ICn
RACn
RICn
No INT
INT Pending
INT Pending
INT Pending
INT Pending
INT Pending
INT Pending
INT Pending
No INT
No INT
No INT
No INT
No INT
DTMFICn No INT
FSK Interrupt occurs when the
FSK FIFO is empty
7
FSKICn
No INT
INT Pending
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.5.5. INTERRUPT ENABLE REGISTER 2
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x29
IE2
FSKIECn
DTMFIECn RIECn RAECn O2IECn O2AECn O1IECn O1AECn
The letters “Cn” stands for channel number 1 or 2.
Bit Value
Bit
Bit Description
Location
Bit Name
0
Masked
Masked
Masked
Masked
Masked
Masked
1
0
1
2
3
4
5
6
7
Oscillator 1 Active Timer
Oscillator 1 Inactive Timer
Oscillator 2 Active Timer
Oscillator 2 Inactive Timer
Ringing Active Timer
Ringing Inactive Timer
DTMF Inactive Timer
FSK Enable
O1AECn
O1IECn
O2AECn
O2IECn
RAECn
RIECn
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
DTMFIECn Masked
FSKIECn
Masked
14.5.6. INTERRUPT STATUS REGISTER 3
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x2A
INT3
RES
GKDICn
RES
TMP
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
This register displays the status of the dice Temperature interrupt of the device. A pending interrupt is represented
by a HIGH “1” in the respective bit. Writing 1 to that respective bit clears the pending interrupt.
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
3
Die Temperature Interrupt
TMP
No INT
INT Pending
Ground Key Detection
Interrupt
GKDICn
No INT
INT Pending
Revision 1.3
Page 97 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.5.7. INTERRUPT ENABLE REGISTER 3
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x2B
IE3Cn
RES
GKDIECn
RES
TMPE
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
This register enables the dice Temperature interrupt of the device. An interrupt can be enabled by writing a HIGH “1”
in the respective interrupt bit. The following table explains the Interrupt Enable Register 1 bits.
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
3
Temperature Interrupt Enable
TMPE
Masked
Enabled
Ground Key Detection
Interrupt Enable
GKDIECn
Masked
Enabled
Revision 1.3
Page 98 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.6. DTMF DETECTION REGISTER
14.6.1. DTMF CONTROL 1
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x30
DTMFC1
DTMFENCn ADCOSELCn
DTMFFDEV
DTMFTC
0x00
The letters “Cn” stands for channel number 1 or 2. ADC output is the signal from ADC coming to DTMF decode.
Therefore, the ADC Select bit select either the ADC or PCM input to the DTMF decode. When DTMFTC[3:0] bits are
set to larger values, DTMF detector needs more time to decode the DTMF signal but the numerical precision is
greater.
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
ADC output comes from PCM.
(Transmit path)
ADC output comes from ADC.
(Receive path)
6
7
ADC Output Select
DTMF Enable
ADCOSELCn
DTMFENCn
Disabled
Enabled
DTMF Frequency Deviation
Deviation
(%)
DTMFFDEV[5]
DTMFFDEV[4]
0
0
1
1
0
1
0
1
1.5
2.5
3.0
3.5
Time constant used for DTMF frequency estimation
Time
Constant
DTMFTC3
DTMFTC2
DTMFTC1
DTMFTC0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Time constant used for DTMF frequency estimation
Time
Constant
DTMFTC3
DTMFTC2
DTMFTC1
DTMFTC0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
9
10
11
12
13
14
15
14.6.2. DTMF CONTROL 2
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x31
DTMFCTRL2
RES
DTMFCLRCn
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
DTMF Clear previous
received data.
DTMFCLRCn
0
Default
Clear
Revision 1.3
Page 100 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.6.3. DTMF STATUS (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
Shared
0x33 DTMFST
RES
DTMFEMTCn
0x01
“RES” in the register map means reserved bit(s). It is a Read ONLY bit
Bit Value
1
Bit
Location
Bit Description
Bit Name
0
0
DTMF buffer is empty DTMFEMTCn Pending Data Buffer is Empty
14.6.4. DTMF THRESHOLD
Name D7 D6
Addr.
D5
D4
D3
D2
D1
D0
Default
0x34 DTMFTHRH
0x35 DTMFTHRL
DTMFTHR[15:8]
DTMFTHR[7:0]
0x01
0x00
This is the signal level threshold which must be present to detect a DTMF tone.
14.6.5. DTMF PRESENT DETECT TIME
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x36 DTMFPDT
DTMFPDT[7:0]
0x00
DTMF PRESENT DETECT TIME
The time for which a tone must be present to be
qualified as a valid DTMF tone.
Minimum
0 ms
Maximum
127 ms
Increment
0.5 ms
Range
Revision 1.3
Page 101 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.6.6. DTMF ABSENT DETECT TIME
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x37 DTMFADT
DTMFADT[7:0]
0x00
DTMF ABSENT DETECT TIME
The time for which a tone must be absent before a
signal is considered a new DTMF tone
Minimum
0 ms
Maximum
127 ms
Increment
0.5 ms
Range
14.6.7. DTMF ACCEPT TIME
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x38 DTMFACT
DTMFACT[7:0]
0x00
DTMF ACCEPT TIME
The time for which a tone must be stable to be qualified as a
correct tone. This guard time improves detection performance
by rejecting detected signals with insufficient duration and by
masking momentary detection dropout.
Minimum
Maximum
Increment
Range
0 ms
127 ms
0.5 ms
Revision 1.3
Page 102 of 160
Sep 2010
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Dual Programmable Extended Codec/SLCC + SLFC
14.6.8. DTMF RECEIVE DATA STATUS
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x3A
DTMFRDT DTMFRDYCn
DTMFSTCn
RES
DTMFRDTCn[3:0]
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
DTMF Detector received data, DTMFRDT[3:0]. This data is valid when DTMF Ready, DTMFRDYCn[7], is active.
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
DTMF State (indicates whether a valid DTMF tone
is currently being detected and DTMF Present
Time DTMFPDTCn[7:0], is qualified.)
Data Not Data
Valid Valid
6
7
DTMFSTCn
DTMF Ready (indicates that a valid DTMF tone
has been present for required DTMF Hold Time
(ACCT).)
Data Not Data
Ready Ready
DTMFRDYCn
Column frequency
1209 Hz
1336 Hz
1477 Hz
3
1633 Hz
1
2
A
697 Hz
770 Hz
852 Hz
941 Hz
0x01 hex
0x02 hex
0x03 hex 0x0D hex
4
5
6
B
0x04 hex
0x05 hex
0x06 hex 0x0E hex
7
8
0x08 hex
0
9
0x09 hex
#
C
0x0F hex
D
0x07 hex
*
0x0B hex 0x0A hex 0x0C hex 0x00 hex
14.6.9. DTMF ROW FREQUENCY
Name D7 D6
Addr.
D5
D4
D3
D2
D1
D0
Default
0x3B DTMFRFH
0x3C DTMFRFL
DTMFRFCn[15:8]
DTMFRFCn[7:0]
0x00
0x00
The letters “Cn” stands for channel number 1 or 2. These two bytes are for debug mode, and display the DTMF Row
frequency directly.
•
•
DTMFRFCn[15:3] is the integer part of the DTMF Row frequency,
DTMFRFCn[2:0] is the decimal fraction part of the DTMF Row frequency (13.3 format).
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.6.10. 14/15 DTMF COLUMN FREQUENCY
Name D7 D6 D5
Addr.
D4
D3
D2
D1
D0
Default
0x3D DTMFCFH
0x3E DTMFCFL
DTMFCF[15:8]
DTMFCF[7:0]
0x00
0x00
These two bytes are for debug mode, and display the DTMF Column frequency directly.
•
•
DTMFCF[15:3] is the integer part of the DTMF Column frequency,
DTMFCF[2:0] is the decimal fraction part of the DTMF Column frequency (13.3 format).
Revision 1.3
Page 104 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7. LINE REGISTERS
14.7.1. AC PATH GAIN
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x40
APG
RAMPCn PRENCn VOHZCn
RES
ARXCn[1:0]
ATXCn[1:0]
Analog Receive Gain
Analog Transmit Gain
ARX1Cn
ARX0Cn
Gain (dB)
0
ATX1Cn
ATX0Cn
Gain (dB)
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
- 3.5
- 3.5
+ 3.5
Mute
+ 3.5
Mute
Bit Value
Bit
Location
Bit Description
Wink function
Bit Name
0
1
5
6
7
VOHZCn
PRENCn
RAMPCn
Return to nominal VRING Ramp towards 0 VRING
Soft Polarity Reversal
Disable
Enable
Soft Polarity Reversal ramp
1.484 V/125 µs
2.968 V/125 µs
14.7.2. HYBRID BALANCE
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x1B
0x41
HB
DACG
ADCG
RES
AHYBCn[2:0]
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
6
7
Analog ADC Path Gain
Analog DAC Path Gain
ADCG
DACG
-6 dB
0 dB
0 dB
6 dB
Audio Hybrid Balance Adjustment
AHYB2Cn AHYB1Cn AHYB0Cn Trans hybrid Gain
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+4.08
+2.50
+1.16
0
- 1.02
- 1.94
- 2.77
Disable
Revision 1.3
Page 105 of 160
Sep 2010
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Dual Programmable Extended Codec/SLCC + SLFC
14.7.3. COMMON RINGING BIAS ADJUST DURING RINGING
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x42
VCMR
RES
VCMRCn[5:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
The above register sets Common Ringing Bias Adjustment voltage during Ringing. To convert decimal value to hex
value please refer to the beginning of this section (Register Description).
COMMON RINGING BIAS ADJUST VOLTAGE
DURING RINGING
Minimum
Maximum
Increment
Range
0 V
–93.5 V
1.484 V
14.7.4. LINE AUTOMATIC MANUAL CONTROL
Addr.
Name
D7
D6
D5
RES
D4
D3
D2
D1
D0
Default
0x07
0x43
LAMC
PAACn RGACn LCDACn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Bit Name
LCDACn
0
1
0
1
2
Loop Closure Detect Automatic
Manual Mode
Automatic Control
Automatic RING
Control
RING Automatic
RGACn
PAACn
Manual Mode
Manual Mode
Power Alarm Automatic React
(Enters Open state automatically upon power
alarm regardless of current state)
Automatic Control
In RING Automatic, LAMC:RGACn[1] address (0x43), when entering Ringing state the RING Oscillator is
automatically enabled. Both OSN:O2ECn[1] address (0xC0) and RMPC:R1ENCn[5] address (0xC1) are set
automatically. Enter Active state from ringing state automatically upon RING Trip Detect. The RING Oscillators are
automatically disabled. Forward or Reverse states determined primarily by OHV:SBCn[6] address (0x4C) Upon
entering Loop Closure Detect Automatic LAMC:LCDACn[0] address (0x43) the device will enter the Active state from
Idle, TIP Open, RING Open and ON-HOOK Transmission states automatically upon Loop Closure Detect. Forward
or Reverse states determined primarily by OHV:SBCn[6] address (0x4C).
Revision 1.3
Page 106 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.5. LINEFEED STATUS
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x44
LS
SLSCn[3:0]
LSCn[3:0]
LineFeed Status
LS3Cn
LS2Cn LS1Cn LS0Cn
State
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
0
Open
Forward Active
Forward ON-HOOK Transmission
TIP Open
Ringing
Reverse Active
Reverse ON-HOOK Transmission
RING Open
Forward Idle
Reverse Idle
Calibration Mode
LS[3:0] is the Linefeed Status Register bits which reflects the programmed linefeed state, not necessarily the actual
linefeed state. See LS:SLSCn[3:0] definition. When automatic transitions occur LS[3:0] will also update accordingly.
SLS[3:0] is the Shadow Linefeed Status Register bits which reflects the actual real-time linefeed state. Automatic
operations may cause actual linefeed state to deviate from the state defined in LS:LS[3:0]. For example when
LS:LS[3:0] is programmed for ‘Ringing’ state, LS:SLSCn[3:0] will only indicate ‘Ringing’ during the actual RING burst.
During the RING cadence LS:SLSCn[3:0] will indicate ‘ON-HOOK Transmission’. This register has the same setting
as the Linefeed Status Register bits.
14.7.6. LOOP CURRENT LIMIT
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x45
LGCRTCn LGCRRCn
LGCMCn[1:0]
LCL
RES
ILMCn[2:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
To convert Current Limit decimal value to hex value please refer to the beginning of this section (Register
Description).
CURRENT LIMIT [ILMCn[2:0]]
Minimum
Maximum
Increment
3 mA
Range
20 mA [0x00]
41 mA [0x07]
Revision 1.3
Page 107 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Common Mode
Correction
LGCM1Cn
LGCM0Cn
0
0
1
0
1
0
Open (none)
Small (one)
Medium (two)
1
1
Large (three)
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
6
7
Series Resistor with CRn
Series Resistor with CTn
LGCRR
LGCRT
OFF
OFF
ON
ON
14.7.7. RING TRIP DETECT STATUS/ LOOP CLOSURE STATUS
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x46
RTLC
RES
LCMCn VBLCCn RTDUDCn RTDUACn LCDUCn RTDCn LCDCn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
RING Trip Detect Unfiltered Indicator (RTDUDCn) bit reflects the real-time output of RING trip detects circuit before
debounce. Loop Closure Detect Unfiltered Indicator (LCDUCn) bit reflects the real-time output of Loop Closure
Detect circuit before debounce. Bits of register RTLC[6:5] are READ/WRITE but the bits RTLC[4:0] are READ
ONLY
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
1
2
3
4
Loop Closure Detect (filtered output)
RING Trip Detect (filtered output)
Loop Closure Detect Unfiltered
RING Trip Detect Unfiltered AC
RING Trip Detect Unfiltered DC
LCDCn
LCD has not occurred
RTD has not occurred
Threshold not exceeded
Threshold not exceeded
Threshold not exceeded
LCD has occurred
RTD has occurred
Threshold exceeded
Threshold exceeded
Threshold exceeded
RTDCn
LCDUCn
RTDUACn
RTDUDCn
LC determined by loop
current
LC determined by Tip to
RING voltage
5
6
Voltage-Based Loop Closure
Loop Closure Mask Counter
VBLCCn
LCMCn
Disabled
Enabled
Revision 1.3
Page 108 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.8. LOOP CLOSURE DEBOUNCE
Addr.
0x47
Name
LCDB
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
LCDI[7:0]
Loop Closure Detect Debounce Interval LCDI[7:0] is an 8-bit register which sets time interval (decimal value) in digital
format. To convert decimal value to hex value please refer to the beginning of this section (Register Description).
LOOP CLOSURE DEBOUNCE INTERVAL
Minimum
0 msec
Maximum
159 msec
Increment
1.25 msec
Range
14.7.9. RING TRIP DEBOUNCE INTERVAL
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x48
RTDBA
ARTDI[7:0]
RING Trip Detect Debounce Interval ARTDI[6:0] is an 8-bit register which sets time interval (decimal value) in digital
format. To convert decimal value to hex value please refer to the beginning of this section (Register Description).
RING TRIP DEBOUNCE
Minimum
0 msec
Maximum
159 msec
Increment
1.25 msec
Range
14.7.10. PWM PERIOD
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xFF
Shared
0x49
PWMT
PT[7:0]
This register sets PWM period for the DC/DC converter. Use the following equation to calculate the period.
PWM Period = (PT[7:0] + 1) x PLL Period
The PWM period should be set to a value greater than the DC/DC Converter Minimum OFF Time
PWMT:PT[7:0] > DDCC:DCOFF[4:0]
The PLL Period (expressed in nsec) which is selected based on the setting of PON:CDCC[7] address (0x22) and
PLLS:PLLCM[7] address (0x04).
Revision 1.3
Page 109 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.11. DC/DC CONTROLLER CONTROL
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x76
0x4A
DDCC
DCOFF[7:0]
This register sets DC/DC Converter Minimum OFF Time. Use the following equation to calculate the period.
DCOFF[7:0] should be programmed to values ≥ 04 hex
TOFF = DCOFF[7:0] x PLL Period
The PLL Period (expressed in nsec) which is selected based on the setting of PON:CDCC[7] address (0x22) and
PLLS:PLLCM[7] address (0x04).
14.7.12. ON-HOOK VOLTAGE
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x20
0x4C
OHV
RES
SBCn
VOHCn[5:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
ON-HOOK VOLTAGE (VTIP – VRING) [VOH]
Minimum Maximum
0 V - 93.5 V
Increment
1.484 V
Default
Range
- 47.488 V
Bit Value
Bit
Location
Bit
Name
Bit Description
0
1
Determines polarity of Idle, Active, and On-hook
transition states after automatic transitions
6
SBCn
Forward
Reverse
Revision 1.3
Page 110 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.13. GROUND MARGIN VOLTAGE
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x02
0x4D
GMV
UBRCn
RES
VGMCn[5:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
GROUND MARGIN VOLTAGE [VGM]
Minimum Maximum
0 V - 93.5 V
Increment
1.484 V
Default
Range
-2.968 V
Bit Value
Bit
Location
Bit Description
Bit Name
UBRCn
0
1
7
Unbalanced Ringing
Balanced Ringing
Unbalanced Ringing
14.7.14. HIGH BATTERY VOLTAGE
Addr.
0x4E
Name
D7
XBATRCn
D6
D5
D4
D3
D2
D1
D0
Default
0x32
VBHV
RES
VBATHCn[5:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
HIGH BATTERY VOLTAGE [VBATHCn]
Minimum Maximum
Increment
1.484 V
Default
Range
0 V
- 93.5 V
- 74.2 V
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
7
External Battery Enable
XBATRCn
Disabled
Enabled
14.7.15. LOW BATTERY VOLTAGE
Addr.
0x4F
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x10
VBLV
RES
VBATLCn[5:0]
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
LOW BATTERY VOLTAGE [VBATLCn]
Minimum Maximum
Increment
1.484 V
Default
Range
0 V
- 93.5 V
- 23.744 V
Revision 1.3
Page 111 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.16. LOOP CLOSURE DETECT/RING TRIP DETECT COEFFICIENT
Addr.
0x50
0x51
0x52
Name
LCDCL
RTDFCLD
DCHD
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
LCDC[7:0]
ARTDFC[7:0]
0x00
ARTDFC[11:8]
LCDC[11:8]
0x00
Loop Closure Detect Coefficient LCDC[11:0] is governed by the cutoff frequency fLP
⎛
⎜
⎞
⎟
f
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
LP
800Hz
12
⎜
LCDC[11 :0] = ⎜1 - 2 * π *
⎟⎟ * 2
⎜
⎝
⎟
⎠
AC Ring Trip Detect Filter Coefficient ARTDFC[11:0] is governed by the cutoff frequency fLP
⎛
⎜
⎞
⎟
f
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
LP
800Hz
12
⎟⎟ *2
⎜
ARTDFC[11 :0] = ⎜1 - 2* π *
⎜
⎝
⎟
⎠
14.7.17. LOOP CLOSURE DETECT THRESHOLD WITHOUT / WITH HYSTERESIS
Addr.
0x53
0x54
Name
LCT
D7
D6
D5
D4
D3
LCT[5:0]
LCTOFF[5:0]
D2
D1
D0
Default
0x00
RES
LCTHY
DBTR
LCHYEN
0x00
“RES” in the register map means reserved bit(s).
Bit
Location
Bit Description
Condition
Bit Name
LCT
Range
Increment
Current Based
(RTLC:VBLC=0,)
0 to 80
mA
If hysteresis enabled
(LCTHY:LCHYEN=1) LCT[5:0] only
1.27 mA
1.484 V
1.27 mA
(0x53)
D0 - D5
Loop Closure
Detect Threshold used to determine transitions from
Voltage Based
(RTLC:VBLC=1,)
0 to 93.5
V
ON-HOOK to OFF-HOOK state
0 to 80
mA
Current Based
Only valid if hysteresis enabled
Loop Closure
(0x54)
D0 - D5
(LCTHY:LCHYEN=1) LCTOFF[5:0]
Detect Threshold
LCTOFF
only used to determine transitions
with hysteresis
Voltage Based
(LCDB:VBLC=1)
0 to 93.5
V
1.484 V
from OFF-HOOK to ON-HOOK state
Bit Value
Bit
Bit
Name
Bit Description
Location
0
1
6
7
Loop Closure Hysteresis
Dynamic Battery Target
LCHYEN Disable
DBTR Disable
Enable
Enable
Revision 1.3
Page 112 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.18. RING TRIP DETECT THRESHOLD
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x55
RTTA
RES
ARTT[5:0]
0x00
RING TRIP DETECT THRESHOLD [ARTT]
Minimum
Maximum
80 mA
Increment
1.27 mA
Range
0 A
14.7.19. OFFSET VOLTAGE
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x56
VOV
RES
TRCn
VOVCn[3:0]
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
The Tracking Mode is enabled by set TR bit HIGH and disabled by setting it LOW.
Offset Voltage between TIP and RING [VOVCn]
Minimum Maximum
0 V 24 V
Increment
1.484 V
Default
3.0 V
Range
Bit Value
Bit
Location
Bit Description
Bit Name
TRCn
0
1
|VBAT| will not go
below VBATL
VBAT tracks VRING in
4
Tracking Mode
constant current region
14.7.20. DC/DC TIME ON
Addr.
Name
D7
D6
RES
D5
D4
D3
D2
D1
D0
Default
0x57
DCTON
TONDC[5:0]
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Minimum time ON for DC/DC
Revision 1.3
Page 113 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.7.21. AUTOMUTE FUNCTION
Name D7 D6
Addr.
D5
D4
D3
D2
D1
D0
Default
0x5E
AMTTHRCn
AUTOMT AMTENCn AMTSELCn
0x00
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
6
7
Automute Select
Automute Enable
AMTSELCn DAC data + ADC data
AMTENCn Disabled
DAC data only
Enabled
Automute Threshold
AMTTHRCn
Value (dBFS)
5
0
0
4
0
0
3
0
0
2
0
0
1
0
1
0
1
0
-90.3
-84.3
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
: : : : : : : : : : : : : :
-60.8
0
1
1
1
1
0
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
: : : : : : : : : : : : : :
-54.5
1
1
1
1
1
1
1
1
1
1
0
1
-54.3
Revision 1.3
Page 114 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.8. GROUND KEY DETECTION
14.8.1. LINEFEED CONTROL
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x5F
XBTC
RES
ASQHCn
CBPCn
XBEN
XTBOT1Cn XTBOT0Cn
XTBATCn[1:0]
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
2
3
4
DC Bias Current OFF-Hook
DC Bias Current On-Hook TR
Ringer Bias Enable
XTBOT0Cn 8 mA
XTBOT1Cn 4 mA
4 mA
8 mA
XBEN
Disable
Enable
capacitors CP and
CM(C2) in circuit
Capacitors CT and CR
bypassed
5
6
Capacitor Bypass
Audio Mute
CBPCn
STIPAC and SRINGAC
pins are not muted
STIPAC and SRINGAC
pins are muted
ASQHCn
The DC bias current flows through external BJTs in the both On-Hook Transmission and in Active Off-Hook State.
Increasing this value (External Transistor Bias Levels) increases the TIP to RING peak of the differential AC current.
XTBAT1Cn XTBAT0Cn DC Bias Current
0
0
1
1
0
1
0
1
Nominal ILIM
+1 mA
+2 mA
-1 mA
14.8.2. GROUND KEY DETECT HIGH/LOW THRESHOLD
Addr.
0x60
0x61
Name
GKDH
GKDL
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
RES
RES
HGKD[5:0]
LGKD[5:0]
0x00
GKD HIGH/LOW THRESHOLD
Minimum
0 A
Maximum
80 mA
Increment
1.27 mA
Range
Revision 1.3
Page 115 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.8.3. GROUND KEY DETECT DEBOUNCE TIME
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x62
GKDDT
DTGKD[7:0]
GKD DEBOUNCE TIME
Minimum
0 msec
Maximum
320 msec
Increment
1.25 msec
Range
14.8.4. GROUND KEY DETECT FILTER COEFFICIENT LOW/ HIGH
Addr.
0x63
0x64
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
GKDFCL
GKDFCH
FCGKD[7:0]
0x00
0x00
GKDEN
RES
FCGKD[11:8]
Ground Key Detection Filter Coefficient governs the Ground Key Detect LPF cutoff frequency fLP
⎛
⎜
⎞
⎟
f
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
LP
800Hz
12
⎟⎟ * 2
⎜
FCGKD[11 :0] = ⎜1 - 2 * π *
⎜
⎝
⎟
⎠
Bit Value
Bit
Location
Bit Description
Bit Name
GKDEN
0
1
7
Enable Ground Key detection
Disable
Enable
14.8.5. DC RING TRIP DEBOUNCE FILTER COEFFICIENT LOW
Addr.
0x65
0x66
Name
RTDCDL
DCHD
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
DRTDFC[7:0]
RES
DRTDFC[11:8]
0x00
DC Ring Trip Coefficient is governed by the cutoff frequency fLP
⎡
⎤
⎥
⎥
1 − ( 2 * π * f
)
⎢
⎢
DRTFC[11: 0]
=
x
212
LP
800
⎢
⎣
⎥
⎦
Revision 1.3
Page 116 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.8.6. DC RING TRIP CURRENT THRESHOLD
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x67
RTTD
RES
XRTR
DRTT[5:0]
DC Ring Trip current Threshold in Internal Ringing Mode
RING TRIP DETECT THRESHOLD [DRTT]
Minimum
0 A
Maximum
80 mA
Increment
1.27 mA
Range
14.8.7. DC RING TRIP DEBOUNCE TIME
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x68
RTDBD
DRTD[7:0]
DC RING TRIP DEBOUNCE TIME
Minimum
0 msec
Maximum
159 msec
Increment
1.25 msec
Range
14.8.8. EXTERNAL BATTERY SWITCH OUTPUT CONFIGURATION 1
Addr.
0x6A
0x6B
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
XBSDCN
XBSDCP
DCNXB[7:0]
DCPXB[7:0]
0x00
0x00
External battery switch DCN pin and DCP output configuration for different line states
XBSDCN Register
XBSDCP Register
DCN output
DCP output
Linefeed State
Open
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
x
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
Open
Forward/Reverse Active
Forward/Reverse Active
Forward/Reverse ON-HOOK Transmission
Forward/Reverse ON-HOOK Transmission
TIP/RING Open
TIP/RING Open
Ringing
Ringing
Forward/Reverse Idle
Revision 1.3
Page 117 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
XBSDCN Register
XBSDCP Register
DCN output
DCP output
Linefeed State
Forward/Reverse Idle
x
x
x
x
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
HIGH
LOW
HIGH
Calibration Mode
Calibration Mode
14.8.9. DC/DC HEAVY CURRENT CONVERTER
Addr.
Name
D7
D6
D5
D4
RES
D3
D2
D1
D0
Default
0x00
0x6E
LOAD
LOAD
Bit Value
Bit
Location
Bit Description
Bit Name
LOAD
0
1
Heavy Current Load such as
Ringing for DC/DC converter
0
DC/DC Heavy Current Load
Light load
14.8.10. DC/DC TARGET VOLTAGE
Addr.
Name
D7
D6
D5
D4
D3
VTR[7:0]
D2
D1
D0
Default
0x77
DCTR
0XC8
In Inductor mode the Target Voltage for DC/DC Converter is a READ ONLY register.
DC/DC TARGET VOLTAGE [VTR]
Minimum Maximum
Increment
1.484 V
Default
3.0 V
Range
0 V
- 93.5 V
Revision 1.3
Page 118 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.9. MONITORING REGISTERS
14.9.1. MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE
Addr
(Hex)
Default
(Hex)
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
78
79
RTMNT
LCMNT
MNTRTCn[7:0]
MNTLCCn[7:0]
00
00
RO
RO
The letters “Cn” stands for channel number 1 or 2.
RING TRIP CURRENT MONITOR
LOOP CLOSURE CURRENT MONITOR
Minimum
0 A
Maximum
80 mA
Increment
0.317 mA
Range
14.9.2. MONITOR CURRENT FOR RING TRIP AND LOOP CLOSURE
Addr
(Hex)
Default
(Hex)
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
7A
7B
7C
7D
7E
7F
MNT5
MNT7
MNTQ1Cn[7:0]
MNTQ2Cn[7:0]
MNTQ3Cn[7:0]
MNTQ4Cn[7:0]
MNTQ5Cn[7:0]
MNTQ6Cn[7:0]
00
00
00
00
00
00
RO
RO
RO
RO
RO
RO
MNT9
MNT11
MNT13
MNT15
The letters “Cn” stands for channel number 1 or 2.
TRANSISTOR POWER DESSIPATION
TIP, RING, and LOOP CURRENT SENSE
DESCRIPTION
CONDITION
QT1 and QR1
QT2 and QR2
QT3 and QR3
Range
Minimum
0 W
Maximum
7.70 W
Stepsize
30.4 mW
3.80 mW
30.4 mW
PATHQ2
PATHQ1
PATHQ3
Dependent on the maximum
power dissipation rating of the
external transistors
0 W
0.97 W
0 W
7.70 W
Revision 1.3
Page 119 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.10. LINE CONTROL REGISTERS
14.10.1. VOLTAGE REGISTERS
14.10.1.1.
BATTERY VOLTAGE SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x80
BATV
VBCn[7:0] (RO)
0x02
The letters “Cn” stands for channel number 1 or 2. Battery Voltage VB[7:0] is a READ ONLY register.
BATTERY VOLTAGE SENSE [VBCn]
Minimum
0 V
Maximum
- 94.6V
Increment
0.371 V
Range
14.10.1.2.
TIP/RING TRANSISTOR 3 EMITTER VOLTAGE SENSE (READ ONLY)
D7 D6 D5 D4 D3 D2 D1
Addr.
Name
D0
Default
VTIP
VTIP[11:4] (RO)
0x81
0x00
VTRIP (XP)
VRING
VTIP[3:0] (RO)
RES
RES
VRING[11:4] (RO)
0x82
0x00
VRING (XP)
VRING[3:0] (RO)
“XP” stands for extra precision register. TIP and RING voltage is a READ ONLY register. The range value depends
on calibration. The values provided for range is without any calibration. Please refer to the SPI Peripheral Interface
section for details.
TIP AND RING VOLTAGE SENSE [VTIP, VRING]
Precision
Bits
Minimum
0 V
Maximum
-94.6 V
Increment
371 mV
8
Range
0 V
-94.6 V
23 mV
12
14.10.1.3.
TIP/RING TRANSISTOR 3 EMITTER VOLTAGE SENSE (READ ONLY)
D7 D6 D5 D4 D3 D2 D1
Addr.
0x83
0x84
Name
D0
Default
0x02
QT3VCn[7:0] (VTVE) (VQT2) (RO)
QR3VCn[7:0] (VRVE) (VQR2) (RO)
QT3V
QR3V
0x02
The letters “Cn” stands for channel number 1 or 2. Transistors QT3 / QR3 Emitter Voltage (QT3V, QR3V) is a READ
ONLY register. The range value depends on calibration. The values provided for range is without any calibration.
TRANSISTORS QT3VCn / QR3VCn
EMITTER VOLTAGE
Minimum
0 V
Maximum
- 94.6 V
Increment
371 mV
Range
Revision 1.3
Page 120 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.11.
TRANSISTOR CURRENT REGISTERS
14.11.1. TIP/RING TRANSISTOR 1/2/3 CURRENT SENSE (READ ONLY)
Addr.
0x85
Name
QT3I
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x05
QT3ICn[11:4] (RO)
QR3ICn[11:4] (RO)
QT1ICn[11:4] (RO)
QT2ICn[11:4] (RO)
QR1ICn[11:4] (RO)
QR2ICn[11:4] (RO)
QT3I (XP)
QR3I
QT3ICn[3:0] (RO)
QR3ICn[3:0] (RO)
QT1ICn[3:0] (RO)
QT2ICn[3:0] (RO)
QR1ICn[3:0] (RO)
QR2ICn[3:0] (RO)
RES
RES
RES
RES
RES
RES
0x86
0x87
0x88
0x89
0x8A
0x03
0x03
0x03
0x03
0x03
QR3I (XP)
QT1I
QT1I (XP)
QT2I
QT2I (XP)
QR1I
QR1I (XP)
QR2I
QR2I (XP)
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. TIP/RING Transistor
1/2/3 Current register is a READ ONLY. The range value depends on calibration. The values provided for Range is
without any calibration. Please refer to the SPI Peripheral Interface section for details.
REAL TIME CURRENT
Precision
Range
Bits
Minimum
0 A
Maximum
78.54 mA
Increment
308 μA
8
12
8
QT3ICn
QR3ICn
QT1ICn
QT2ICn
QR1ICn
QR2ICn
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0 A
0 A
78.54 mA
78.54 mA
78.54 mA
78.54 mA
78.54 mA
9.95 mA
9.95 mA
78.54 mA
78.54 mA
9.95 mA
9.95 mA
19.18 μA
308 μA
19.18 μA
308 μA
19.18 μA
39 μA
12
8
12
8
2.5 μA
12
8
308 μA
19.18 μA
39 μA
12
8
2.5 μA
12
Revision 1.3
Page 121 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.
LOOP SUPERVISION
14.12.1. LONGITUDINAL CURRENT (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
LGI
ILGCn[11:4] (RO)
0x8C
0x00
LGI (XP)
ILGCn[3:0] (RO)
RES
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. The range value depends
on calibration. The values provided for Range is without any calibration. Please refer to the SPI Peripheral Interface
section for details.
IQT1- IQT3 − IQR3 + IQR1
)
ILG =
2
LONGITUDINAL CURRENT
Precision
Bits
Minimum
Maximum
77.62 mA
77.62 mA
Increment
0 mA
0 mA
303 uA
8
Range
18.95 uA
12
14.12.2. LOOP VOLTAGE SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
LPV
VLPCn[11:4] (RO)
0x8D
00
LPV (XP)
VLPCn[3:0] (RO)
RES
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. Loop Voltage is a READ
ONLY register. The range value depends on calibration. The values provided for Range is without any calibration.
This is a 12-bit register. Please refer to the SPI Peripheral Interface section for details.
LOOP VOLTAGE
Precision
(VTIP – VRING
Maximum
)
Bits
Minimum
0 V
Increment
365 mV
- 93.5 V
- 93.5 V
8
Range
0 V
22.8 mV
12
Revision 1.3
Page 122 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.3. TIP, RING, AND LOOP CURRENT (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
NA
TIPI
TIPI (XP)
RINGI
ITLPCn[11:4] (RO)
IRLPCn[11:4] (RO)
ILPCn[11:4] (RO)
0x8E
ITLPCn[3:0] (RO)
IRLPCn[3:0] (RO)
ILPCn[3:0] (RO)
RES
RES
RES
0x8F
0x90
NA
NA
RINGI (XP)
LPI
LPI (XP)
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. The above registers are
READ ONLY. The range value depends on calibration. The values provided for Range is without any calibration.
Please refer to the SPI Peripheral Interface section for details.
TIP, RING, and LOOP CURRENT
Precision
Bits
Minimum
Maximum
77.62 mA
Increment
0 mA
0 mA
303 uA
8
Range
77.62 mA
18.95 uA
12
14.12.4. POLARITY
Addr.
Name
D7
RES
D6
D5
P2PENCn
D4
D3
D2
D1
D0
Default
0x91
POL
ILGPCn ILPPCn IRLPCn ITLPCn
VLPCn
NA
The letters “Cn” stands for channel number 1 or 2. Loop voltage, TIP Current, RING Current, Loop Current, and
Longitudinal Current all have Sign Bit associated with it. The Polarity register contains all the Sign or Polarity bits.
For these registers mentioned the range can also extend in the negative direction by setting the Sign or Polarity bit.
Bit Value
Bit
Location
Bit Description
Loop Voltage
Bit Name
0
1
0
1
2
Positive
Positive
Positive
Negative
Negative
Negative
VLPCn
ITLPCn
TIP Current
RING Current
IRLPCn
ILPPCn
ILGPCn
3
4
5
Loop Current
Positive
Positive
Negative
Negative
Longitudinal Current
Loop current PK-2-PK clear
Continuously updates
new peak values
P2PENCn
Clear value
When P2PENCn[5] is set from 0 to 1 the peak detector circuit register value is cleared. If P2PENCn[5] is set to HIGH
and it remain at HIGH than the peak detector circuit register value is continuously updated with new peak values.
Revision 1.3
Page 123 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.5. COMMON MODE VOLTAGE
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
SCM
SCMCn[11:4]
0x92
NA
SCM (XP)
SCMCn[3:0]
RES
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2.
The Common Mode Voltage is calculated using the equation below. Please refer to the SPI Peripheral Interface
section for details.
VTIP + VRING
)
2
14.12.6. TIP EMITTER VOLTAGE FOR TRANSISTORS QT1 SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x93
VEQT1
VEQT1Cn[7:0] (RO)
NA
The letters “Cn” stands for channel number 1 or 2. This is the emitter sense of the transistor QT1 which is used for
the power alarm computation. This register is a READ ONLY register. The range value depends on calibration. The
values provided for range is without any calibration.
TIP - TRANSISTOR QT1 EMITTER
VOLTAGE SENSE
Minimum
Maximum
Increment
Range
0 V
- 94.6 V
0.371 V
14.12.7. TIP VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x94
VQT1
VQT1Cn[7:0] (RO)
NA
The letters “Cn” stands for channel number 1 or 2. The value in this register is derived from TIP voltage and TIP
emitter voltage of the transistor. This is the emitter sense of the transistor QT1 which is used for the power alarm
computation. This register is a READ ONLY register. The range value depends on calibration. The values provided
for range is without any calibration.
TIP - TRANSISTOR QT1
VOLTAGE SENSE
Minimum
0 V
Maximum
Increment
Range
- 94.6 V
0.371V
Revision 1.3
Page 124 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.8. RING EMITTER VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x95
VEQR1
VEQR1Cn[7:0] (RO)
NA
The letters “Cn” stands for channel number 1 or 2.
This is the emitter sense of the transistor QR1 which is used for the power alarm computation. This register is a
READ ONLY register. The range value depends on calibration. The values provided for range is without any
calibration.
RING - TRANSISTOR QR1 EMITTER
VOLTAGE SENSE
Minimum
Maximum
Increment
Range
0 V
- 94.6 V
0.371V
14.12.9. RING VOLTAGE FOR TRANSISTOR QT1 SENSE (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x96
VQR1
VQR1Cn[7:0] (RO)
NA
The letters “Cn” stands for channel number 1 or 2.
The value in this register is derived from RING voltage and RING emitter voltage of the transistor. This is the emitter
sense of the transistor QR1 which is used for the power alarm computation. This register is a READ ONLY register.
The range value depends on calibration. The values provided for range is without any calibration.
RING - TRANSISTOR QR1
VOLTAGE SENSE
Minimum
Maximum
Increment
Range
0 V
- 94.6 V
0.371V
14.12.10.
TEMPERATURE SENSE (READ ONLY)
Addr.
Name
TEMP
D7
D6
D5
D4
D3
D2
D1
D0
Default
Shared
0x99
TS[7:0]
NA
Die Temperature Sense TS[7:0] is a READ ONLY register. The actual temperature T is given by:
T = TS[7:0] – 67
@ 1°C Increment
14.12.11.
BAND GAP VOLTAGES
Addr.
Name
VBGAP
D7
D6
D5
D4
D3
D2
D1
D0
Default
Shared
0x9A
VBG[7:0]
0x00
Bandgap Voltage Trim VBG[7:0] is a trim parameters which can be used during the calibration sequence.
Revision 1.3
Page 125 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.12.12.
Name
PEAK TO PEAK LOOP VOLTAGE
Addr.
D7
D6
D5
D4
D3
D2
D1
D0
Default
VLPP2P
LPVP2PCn[11:4]
0x9B
0x00
VLPP2P (XP)
LPVP2PCn[3:0]
RES
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. This read only register
captures the peak-to-peak loop voltage. The peak detector circuit clears this register value when POL:P2PEN[5]
address (0X91)is set from 0 to 1 and continuously updates new peak values when P2PEN[5] is HIGH. The final peak
value is held in VLPP2P:LPVP2P address (0X91) when P2PEN[5] is cleared to LOW until P2PEN[5] is set again.
The peak-to-peak loop voltage is measured as (max positive peak + max negative peak) / 2.
PEAK TO PEAK LOOP VOLTAGE
Precision
Bits
Minimum
0 V
Maximum
- 94.6 V
Increment
374 mV
8
Range
0 V
- 94.6 V
23mV
12
14.12.13.
Name
PEAK TO PEAK LOOP CURRENT (READ ONLY)
Addr.
D7
D6
D5
D4
D3
D2
D1
D0
Default
NA
ILPP2P
LPIP2P[11:4] (RO)
0x9C
ILPP2P (XP)
LPIP2P[3:0] (RO)
RES
“XP” stands for extra precision register. The letters “Cn” stands for channel number 1 or 2. This READ ONLY
register captures the peak-to-peak loop current. The peak detector circuit clears this register value when
POL:P2PEN[5] address (0X91)is set from 0 to 1 and continuously updates new peak values when P2PEN[5] is HIGH.
The final peak value is held in ILPP2P:LPIP2P address (0X91) when P2PEN[5] is cleared to LOW until P2PEN[5] is
set again. The peak-to-peak loop current is measured as (max positive peak + max negative peak) / 2.
PEAK TO PEAK LOOP CURRENT
Precision Bits
Minimum
Maximum
Increment
0 mA
-77.62 mA
303 uA
8
Range
0 mA
-77.62 mA
18.95 uA
12
Revision 1.3
Page 126 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.13.
POWER ALARM LPF POLE REGISTERS
14.13.1. POWER ALARM COUNTER (READ ONLY)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x9F
PALCNT
PALCNTCn[7:0] (RO)
0x00
The letters “Cn” stands for channel number 1 or 2.
The Power Alarm Counter indicates the number of rising edges of the LOWVDC or HIGHIDC flags. The value of this
register clips at 255. This counter is reset after every read command.
a) DCDC output voltage (VBAT) 10% above full scale or
b) DCDC supply voltage (VDDC) too low or
c) DCDC supply current (IVDDC) too high;
14.13.2. POWER ALARM LOW PASS FILTER POLE FOR TRANSISTORS 1/2/3
Addr.
0xA0
0xA1
0xA2
0xA3
0xA4
Name
D7
D6
D5
D4
Q2C[7:0]
Q1C[7:0]
Q3C[7:0]
D3
D2
D1
D0
Default
0x00
0x00
0x00
0x00
0x00
PALPQ2
PALPQ1
PALPQ3
PALPQHn
PALPQH2
Q1C[11:8]
Q2C[11:8]
Q3C[11:8]
LPFEN
Q3C12
Q1C12
Q2C12
The Power Alarm register are 13 bit registers. For example Q2 Power Alarm bits are located at address 0xA0, (D0 –
D7, Q2C[7:0]) first 8-bits. The next 4-bits are located at address 0xA3 (D0 – D3 bits, Q2C[11:8]) and the last bit out
of 13-bits is located at address 0xA4 (D4 – Q2C[12]). The other two transistor bits can be located the same way.
LPFEN enables the Low Pass Filter when set to 1.
POWER ALARM LOW PASS FILTER POLE FOR TRANSISTORS 1/2/3
Dependent on the thermal time constant of the external transistors
QT2 and QR2
PALPQ2
QT1 and QR1
PALPQ1
QT3 and QR3
PALPQ3
⎛
⎞
1
13
⎛
⎞
⎛
⎞
1
1
⎜
⎟
⎟
13
13
Q2C[12 : 0] = 1−
*2
⎜
⎟
⎟
⎜
⎟
⎟
⎜
⎝
Q1C[12 : 0] = 1−
*2
Q3C[12 : 0] = 1−
*2
800*TTC
⎜
⎝
⎜
⎝
⎠
800*TTC
800*TTC
⎠
⎠
Revision 1.3
Page 127 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.13.3. POWER ALARM THRESHOLD FOR TRANSISTOR 1-3
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0xA5
PATHQ2
PATHQ1
PATHQ3
Q2TH[7:0]
0xA6
0xA7
Q1TH[7:0]
Q3TH[7:0]
0x00
0x00
TIP, RING, and LOOP CURRENT
DESCRIPTION
CONDITION
QT1 and QR1
QT2 and QR2
QT3 and QR3
Range
Minimum Maximum
Increment
30.4 mW
3.8 mW
Dependent on the
maximum power
dissipation rating
of the external
transistors
PATHQ2
PATHQ1
PATHQ3
0 W
0 W
0 W
7.7 W
0.97 W
7.7 W
30.4 mW
14.14.
Addr.
IMPEDANCE MATCHING 1/2
Name
D7
D6
RES
ZSWCn
D5
D4
D3
D2
D1
D0
Default
0xA8
0xA9
IM1
IM2
ZR1Cn[3:0]
0x00
0x00
RES
RES
“RES” in the register map means reserved bit(s).
Impedance Matching/ R1 Element
ZR13Cn ZR12Cn ZR11Cn ZR10Cn R1 (Ohm)
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
0
1
0
1
x
600 ꢀ
900 ꢀ
600 ꢀ
900 ꢀ
270 ꢀ
200 ꢀ
200 ꢀ
100 ꢀ
370 ꢀ
220 ꢀ
320 ꢀ
220 ꢀ
Not Used
Bit Value
Bit
Location
Bit Description
Bit Name
ZSWCn
0
1
Disables impedance
matching feedback loop for
diagnostics testing
Impedance matching
Feedback loop Disable
6
Default, enabled
Revision 1.3
Page 128 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.14.1. TEMPERATURE ALARM THRESHOLD
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xAA
THAT
TATH[7:0]
0x00
TTH = TATH[7:0] – 67
@ Increment of 1°C
14.14.2. LOOP CLOSURE MASK COUNT
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xAB
LCMCNT
LCMCNT[7:0]
0x00
LOOP CLOSURE MASK COUNT
Minimum
0 ms
Maximum
319 ms
Increment
1.25 ms
Range
14.14.3. COARSE CALIBRATION INTERNAL RESISTOR
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xAC
CC
RES
CBGSW
CTRIM[2:0]
0x00
“RES” in the register map means reserved bit(s).Coarse Calibration CTRIM[2:0] and Internal Resistor CBGSW are a
trim parameters which can be used during the calibration sequence.
14.14.4. OSCILLATOR 2 RINGING PHASE DELAY
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0xAD
OS2RPD
O2RPDCn[7:0]
The letters “Cn” stands for channel number 1 or 2.
When Oscillator 2 is used for Tone Generation it is recommended this register be set to 0x00. If the ringing phase
delay in oscillator 2 (0xAD) is used , zero crossing function must be enabled OSN:O2ZCCn[3] address 0xC0.
OSCILLATOR 2 RINGING PHASE DELAY
Minimum
0 ms
Maximum
31.8 ms
Increment
125 us
Range
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.15.
Addr
CALIBRATION
Name D7
D6
D5
D4
D3
D2
D1
D0
Default
0X77
0xAF
0xB0
0xB1
CAL1
CAL2
CAL3
SDATCn[3:0]
TVTE1Cn[3:0]
SCMTCn[3:0]
VBATTCn[3:0]
SDBTCn[3:0]
RVTECn[3:0]
0X97
0X79
The letters “Cn” stands for channel number 1 or 2.
All values are trim parameters which can be used during the calibration sequence.
Bits
Trim
VBATTCn[3:0]
VBAT Trim
SDATCn[3:0]
SDBTCn[3:0]
TVTE1Cn[3:0]
RVTECn[3:0]
SCMTCn[3:0]
SDA Trim
SDB Trim
TVE1 Trim
RVE1 Trim
SCM Trim
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.16.
DC OFFSET REGISTERS
14.16.1. DC OFFSET (RING, TIP, AND VBAT)
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xB4
IQTROS
HISENSECn
BTVR
ILFDB
DACSFC
RES
0x00
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s). Where ‘n’
stands for channel 1, 2. All values are trim parameters which can be used during the calibration sequence.
Bit Value
Bit
Location
Bit Description
Smoothing Filter
Bit Name
DACSFC
ILFDB
0
1
4
5
Cutoff at 1xfc
Cutoff 2xfc
Bias varies with
coarse calibration
Line driver bias
Fixed Bias
Normal
6
7
DC/DC Range
BTVR
Low VBAT
Monitor DC Range
HISENSECn Normal line
Extended line
14.16.2. PWM COUNT
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
NA
0xB5
PWCT
PWCTCn[7:0]
The letters “Cn” stands for channel number 1 or 2.
This register is a READ ONLY. PWM Count Register can calculate DC/DC Converter Pulse Width TON with the
following equation.
TON = PWCTCn[7:0] * PLL Period
The TON Range is 0 ns to (PWM Period-TOFF) see PWMT and DDCC with a stepsize of PLL period. The PLL
Period (expressed in nsec) which is selected based on the setting of PON:CDCC[7] address (0x22) and
PLLS:PLLCM[7] address (0x04).
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.17.
TONE GENERATION REGISTERS
14.17.1. OSCILLATOR CONTROL
Addr.
Name
D7
D6
RES
D5
D4
D3
D2
D1
D0
Default
0x00
0xC0
OSN
O2ZCCn
O1ZCCn
O2ECn
O1ECn
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Oscillator 1
Bit Name
0
1
0
1
2
3
O1ECn
O2ECn
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Oscillator 2
Oscillator n Zero-Crossing
Oscillator 2 Zero-Crossing
O1ZCCn
O2ZCCn
14.17.2. RING CONTROL
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0xC1
RMPC TRAP LBACCn R1ENCn
RES
TORCn
RES
The letters “Cn” stands for channel number 1 or 2. “RES” in the register map means reserved bit(s).
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
Transmit direction
(towards DAC)
Receive direction
(towards ADC)
3
5
6
7
Tone Route
TORCn
R1ENCn
LBACCn
TRAP
Ringer 1
Disable
Enable
Sinusoidal RING
Waveform
Trapezoidal RING
Waveform
Ringing Waveform
Ringing Waveform Select
Disable
Enable
14.17.3. OSCILLATOR 1 AND 2 INITIAL CONDITION LOW/HIGH
Addr.
0xC2
0xC3
0xC4
0xC5
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x00
0x00
0x00
OS1ICL
OS1ICH
OS2ICL
OS2ICH
O1ICCn[7:0]
O1ICCn[15:8]
O2ICCn[7:0]
O2ICCn[15:8]
The letters “Cn” stands for channel number 1 or 2. Initial Condition for Oscillator m OmIC[15:0] m=1,and 2 can be
determined by formula. Refer to Tone Generation see Section for the formula.
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.17.4. OSCILLATOR 1 AND 2 COEFFICIENT LOW/HIGH
Addr.
0xC6
0xC7
0xC8
0xC9
Name
OS1CL
OS1CH
OS2CL
OS2CH
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x00
0x00
0x00
O1CCn[7:0]
O1CCn[15:8]
O2CCn[9:2]
O2CCn[17:10]
The letters “Cn” stands for channel number 1 or 2.
Coefficient for Oscillator m (OmC[15:0] m=1, and 2, refer to Tone Generation see section for the formula. OS2CL is
18-bits long word. First 16-bits are on address 0xC8 and 0xC9. The 2 most significant bits are located in register
address 0xDC (D6 –D7).
14.18.
Addr.
OSCILLATOR 1 AND 2 ACTIVE/ INACTIVE TIME LOW/HIGH
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
OS1ATL
OS1ATH
OS2ATL
OS2ATH
OS1ITL
OS1ITH
OS2ITL
OS2ITH
O1ONCn[7:0]
O1ONCn[15:8]
O2ONCn[7:0]
O2ONCn[15:8]
O1OFF[7:0]
O1OFF[15:8]
O2OFF[7:0]
O2OFF[15:8]
The letters “Cn” stands for channel number 1 or 2.
OSCILLATOR 1/2 ACTIVE/
INACTIVE TIME
Minimum
Maximum
Increment
O1ONCn
O2ONCn
O1OFF
Active/Inactive
Timer Oscillator m
Tone
Generation
Timer is disabled by
programming zero
0 s
0 s
8 s
125 us
125 us
O2OFF
Active/Inactive
Timer Oscillator 2
Timer is disabled by
programming zero
O2ONCn
O2OFF
Ringing only
8 s
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.19.
GENERAL TONE GENERATION
14.19.1. RING OFFSET
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0xDC
ROFFS
O2CCn[1:0]
ROSCn[5:0]
0x00
“RES” in the register map means reserved bit(s).
TIP to RING Offset for Ringing, Sets DC Offset component to the Ringing Waveform
RING OFFSET [ROSCn]
Minimum
0 V
Maximum
47.488 V
Increment
1.484 V
Range
14.19.2. ADC/DAC DIGITAL GAIN
Addr.
0xDD
0xDE
0xDF
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
ADCL
DACL
DGH
ADCCn[7:0]
DACCn[7:0]
0x00
0x00
0x44
DACCn[11:8]
ADCCn[11:8]
DIGITAL GAIN
Minimum
Maximum
ADC = 1024x10 (XdB/20)
DAC = 1024x10 (XdB/20)
ADCCn
DACCn
Digital Gain
–∞ dB
6 dB
ADCCn
DACCn
Gain
dB
0x000
0x040
Off
-∞
1 / 8
-24
0x100
0x200
0x400
0x7FF
1 / 4
1 / 2
1
-12
-6
0
2
6
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.19.3. PWM DC/DC FINE TUNING
Addr.
0xE0
Name
D7
D6
RES
D5
D4
D3
D2
D1
D0
Default
0x02
ST0L0
ST1L0
ST2L0
ST0L1
ST1L1
ST2L1
ST0L0[3:0]
0xE1
0xE2
0xE3
0xE4
0xE5
0x04
0x06
0x08
0x10
0x19
RES
RES
ST1L0[4:0]
ST2L0[4:0]
RES
ST0L1[3:0]
RES
RES
ST1L1[4:0]
ST2L1[4:0]
“RES” in the register map means reserved bit(s).
Name
Addr.
Symbol
STx
Description
Unit
Proportional to master clock period
x = 0, 1, 2
L0 - Non-RINGING
L1 - RINGING
Stepsize
Region
State
0xE0 – 0xE5
Ly
Addr.
Name
Recommendation
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0x02
0x02
0x02
0x08
0x08
0x08
ST0L0
ST1L0
ST2L0
ST0L1
ST1L1
ST2L1
14.19.4. PWM DC/DC FINE TUNING SKIP PERIOD
Addr.
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
Name
SK0L0
SK1L0
SK2L0
SK0L1
SK1L1
SK2L1
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x1F
0x04
0x02
0x1F
0x04
0x02
SK0L0[7:0]
RES
RES
SK1L0[5:0]
RES
RES
ST2L0[4:0]
SK0L1[7:0]
SK1L1[5:0]
SK2L1[4:0]
“RES” in the register map means reserved bit(s).
Addr.
Name
Recommendation
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
SK0L0
SK1L0
SK2L0
SK0L1
SK1L1
SK2L1
0x06
0x06
0x06
0x06
0x06
0x06
Addr.
Name
Name
SKx
Description
x = 0, 1, 2
Unit
# of PWM duty cycle
Skip Region
State
0xE6 – 0xEB
L0 - Non-RINGING
L1 - RINGING
Ly
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
14.19.5. PWM DC/DC FINE TUNING
Addr.
0xEC
0xED
0xEE
0xEF
Name
WM0
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x08
0x10
0x18
0x53
WM0[4:0]
WM1[4:0]
WM2[4:0]
RES
RES
RES
WM1
WM2
XSTEP
PWMTC
XS[3:0]
“RES” in the register map means reserved bit(s). “n” is the number written to the register in decimal
Name
Watermark
Addr.
Symbol
WMx
Description
x = 0, 1, 2
Unit
0xEC – 0xEE
n x 1.484V
n x 1.484V
0xEF
0xEF
Fine Adjust Region
XS
Time constant of VLoop
sensing filter for PWM
PWMTC
Addr.
Name
Recommendation
0xEC
0xED
0xEE
0xEF
WM0
WM1
WM2
0x01
0x02
0x02
0x60
XSTEP
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.19.6. IMPEDANCE MATCH REGISTER
14.19.6.1.
IMPEDENCE MATCHING COEFFICIENT RAM
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0xF3
IMRAM
IMDATA
Read and Write location for the Impedance Matching Coefficient RAM. Used in conjunction with Write Sequence
described in IMCTRL 0xF5.
14.19.6.2.
IMPEDANCE MATCHING DELAY COUNT
Addr.
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x00
0xF4
IMDEL
IMHYBDCCn[3:0]
IMB3PDCCn[3:0]
Programmed in conjunction with Impedance Matching Coefficient RAM.
Bit
Impedance Matching Delay Count
IMB3PDCCn[3:0]
Delay count of B3Parallel path - Default no delay
Delay count of Hybrid2 path - Default no delay
IMHYBDCCn[7:4]
14.19.6.3.
IMPEDANCE MATCHING COEFFICIENT RAM CONTROL
Addr.
Name
IMCTRL
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x10
0xF5
RES
IMRW
RES
IMEN
RES
IMPM
Bit Value
Bit
Location
Bit Description
Bit Name
0
1
0
2
4
Program Impedance Matching Coefficient RAM
Complex Impedance Matching enable
IMPM
IMEN
IMRW
Disable
Enable
Enable
Write
Disable
Read
Read/Write Impedance Matching Coefficient RAM
Bits 3, 5, 6, and 7 must be set to “0”. For Complex Impedance Matching Cases the appropriate set (288 Bytes)
should be loaded into the following sequence into the Coefficient RAM.
Write Step Sequence:
1. Set IMCTRL:IMRW[4] to 1
2. Set IMCTRL:IMPM[0] to 1
3. WRITE all 288 Bytes of Impedance Matching Coefficient set to Register IMRAM (Address 0xF3) in sequence
4. Set IMCTRL:IMPM[0] to 0
Read Step Sequence:
1. Set IMCTRL:IMRW[4] to 0
2. Set IMCTRL:IMPM[0] to 1
3. READ all 288 Bytes of Impedance Matching Coefficient set from Register IMRAM (Address 0xF3) in sequence
4. Set IMCTRL:IMRW[4] to 1 (to Restore Default Value)
5. Set IMCTRL:IMPM[0] to 0
Once the of Impedance Matching coefficients are loaded into the RAM, the Complex Impedance is enabled by setting
IMCTRL:IMEN[2]
Revision 1.3
Page 137 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
14.19.6.4.
Addr. Name D7
RESERVED REGISTERS
D6 D5 D4
D3
D2
D1
D0
Default
0x00
0xF8
0xF9
0xFA
RES
RES
RES
0x00
0x00
These three register must be set to 0x00 during a write operation
14.19.6.5.
FILTER BYPASS
D6 D5
Addr. Name
0xFB IMEN
D7
D4
D3
D2
D1
D0
Default
0x00
RES
ADCLPFBYPCn HBLPFBYPCn
Bit
HBLPFBYPCn[0]
PCM Scaling
Bypass the HB LPF. Default: 0(not bypass)
ADCLPFBYPCn[1] Bypass the ADC LPF. Default: 0(not bypass)
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
15. TIMING DIAGRAM
15.1. PCM TIMING DIAGRAM FOR NON-GCI
TBCK
TRISE
TFALL
BCLK
TFRS
TBCKH
TBCKL
TFFH
TFRH
TFS
TFSL
FS
TFDTD
TBDTD
THID
TBDTD
TFDTD
THID
PCMT
MSB
MSB
LSB
(MSB not starting at the
1st BCLK of a Frame)
(MSB starting at the 1st
BCLK of a Frame)
TDRS
PCMR
TDRH
MSB
LSB
Figure 37: PCM Timing for Non-GCI
SYMBOL
1/TFS
DESCRIPTION
MIN
TYP
MAX
UNIT
FS Frequency
---
8
---
kHz
sec
kHz
ns
TFSL
FS Minimum LOW Width
TBCK
256
50
1/TBCK
TBCKH
TBCKL
TFRH
BCLK, BCLK Frequency
---
---
---
---
---
---
8192
---
BCLK HIGH Pulse Width
ns
BCLK LOW Pulse Width
50
---
ns
BCLK Falling Edge to FS Rising Edge Hold Time
FS Rising Edge to BCLK Falling edge Setup Time
BCLK Falling Edge to FS Falling Edge Hold Time
20
---
TFRS
ns
25
---
TFFH
ns
20
---
The later of BCLK Rising Edge or FS Rising Edge to valid
PCMT Delay Time if MSB Starts from the 1st BCLK of a
Frame
TFDTD
TBDTD
THID
ns
ns
ns
---
---
10
---
---
---
20
20
50
BCLK Rising Edge to Valid PCMT Delay Time
Delay Time from BCLK Falling edge of the LSB or BCLK
Rising edge following the LSB (Depending on Register TRI)
to PCMT Output High Impedance
TDRS
TDRH
ns
ns
Valid PCMR to BCLK Falling Edge Setup Time
PCMR Hold Time from BCLK Falling Edge
25
20
---
---
---
---
Table 8.1: PCM Timing Parameters for Non-GCI
Revision 1.3
Page 139 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
15.2. PCM TIMING DIAGRAM FOR GCI
TBCK
TRISE
TFALL
BCLK
TFRS
TFRH
TBCKH
TBCKL
TFFH
TFS
TFSL
FS
TFDTD
THID
TBDTD
TBDTD
TFDTD
THID
PCMT
MSB
MSB
LSB
(MSB not starting from
the 1st BCLK of a Frame)
(MSB starting from the
1st BCLK of a Frame)
TDRS
PCMR
TDRH
Figure 38: GCI PCM Timing
MSB
LSB
SYMBOL
1/TFS
1/TBCK
TBCKH
TBCKL
TFRH
DESCRIPTION
MIN
---
TYP
8
MAX
---
UNIT
kHz
kHz
ns
FS Frequency
BCLK Frequency
512
50
---
---
---
---
---
---
8192
---
BCLK HIGH Pulse Width
BCLK LOW Pulse Width
50
---
ns
BCLK Falling Edge to FS Rising Edge Hold Time
FS Rising Edge to BCLK Falling edge Setup Time
BCLK Falling Edge to FS Falling Edge Hold Time
20
---
ns
TFRS
50
---
ns
TFFH
20
---
ns
The later of BCLK or FS Rising Edge to Valid PCMT Delay
Time if MSB Starts from the 1st BCLK of a Frame
TFDTD
TBDTD
10
10
---
---
50
50
ns
ns
BCLK Rising Edge to Valid PCMT Delay Time
Delay Time from the Second BCLK Falling Edge of the LSB
or the BCLK Rising Edge following LSB (Depending on
Register TRI setting) to the PCMT Output High Impedance
THID
10
---
50
ns
TDRS
TDRH
Valid PCMR to BCLK Rising Edge Setup Time
PCMR Hold Time from BCLK Rising Edge
20
50
---
---
---
---
ns
ns
Table 8.2: GCI Timing Parameters
Revision 1.3
Page 140 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
SYMBOL
1/TBCK
Tjitter
DESCRIPTION
MIN
TYP
0.256
0.512
0.768
1.000
1.024
1.152
1.536
1.544(2)
2.000
2.048
4.000
4.096
8.000
8.192
---
MAX
UNIT
MHz
ns
BLCK Clock Frequency
---
---
BLCK Period Jitter Tolerance(1)
-120
40%
120
TBCKH / TBCK BCLK Duty Cycle for 256 kHz Operation
50%
60%
Minimum Pulse Width HIGH for BCLK(512 kHz or
Higher)
TBCKH
50
50
---
---
---
---
ns
ns
Minimum Pulse Width LOW for BCLK (512 kHz or
Higher)
TBCKL
TFRH
TFRS
TRISE
TFALL
BCLK falling Edge to FS Rising Edge Hold Time
FS Rising Edge to BCLK Falling edge Setup Time
Rise Time for All Digital Signals
50
50
---
---
---
---
---
---
---
---
25
25
ns
ns
ns
ns
Fall Time for All Digital Signals
Table 8.3: General PCM Timing Parameters
1
At 512 kHz BCLK
2. This clock is not a multiple of 256kHz or 1.000MHz. Therefore, it uses a non-integer divider.
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
15.3. SPI TIMING DIAGRAM
\CS
TCSHI
TCSS
TCSH
TSCK
TRISE
TFALL
SCLK
SDI
TSCKH
TSDIH
TSCKL
TSDIS
TSDOD
TSDOT
SDO
TSDOA
Figure 39: SPI Timing (Non-Daisy Chain Mode)
SYMBOL
TSCK
DESCRIPTION
MIN
90
TYP
---
MAX
---
UNIT
ns
SCLK Cycle Time
TSCKH
TSCKL
TRISE
TFALL
TCSS
SCLK High Pulse Width
SCLK Low Pulse Width
45
45
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
25
25
---
---
---
---
---
20
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rise Time for All Digital Signals
Fall Time for All Digital Signals
---
CSb Falling Edge to 1st SCLK Falling Edge Setup Time
Last SCLK Rising Edge to \CS Rising Edge Hold Time
CSb High, Delay Time between Chip Selects
SDI to SCLK Rising Edge Setup Time
45
45
200
20
20
---
TCSH
TCSHI
TSDIS
TSDIH
TSDOD
TSDOT
TSDOA
SCLK Rising Edge to SDI Hold Time
Delay Time from SCLK Falling Edge to SDO Data
Delay Time from CSb Rising Edge to SDO Tri-State
Delay Time from CSb Falling Edge to SDO Active
---
---
Table 8.4: General SPI Timing Parameters
Revision 1.3
Page 142 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 40: In-band Transmit Frequency Response
Figure 41: In-band Receive Frequency Response
Revision 1.3
Page 143 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 42: Transmit Group Delay Distortion
Figure 43: Receive Group Delay Distortion
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 44: 2-Wire to PCM Signal to Distortion Mask (A-Law)
Figure 45: 2-Wire to PCM Signal to Distortion Mask (µ-Law)
Revision 1.3
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Dual Programmable Extended Codec/SLCC + SLFC
Figure 46: Wideband In-band Transmit Frequency Response
Figure 47: Wideband Transmit Group Delay Distortion
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
Figure 48: Wideband Receive Group Delay Distortion
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
16. DIGITAL I/O
16.1.1. µ-LAW ENCODE DECODE CHARACTERISTICS
Digital Code
D4
Normalized Encode
Decision Levels
Normalized
Decode Levels
D7
D6
D5
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step Step Step
8159
7903
:
4319
4063
:
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
8031
:
4191
:
2143
2015
:
1055
991
:
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
2079
:
1023
:
495
:
231
:
511
479
:
239
223
:
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
99
:
103
95
33
:
:
35
31
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
3
1
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
16.2. A-LAW ENCODE DECODE CHARACTERISTICS
Normalized
Digital Code
Normalized
Decode
Levels
Encode
Decision
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
4096
3968
:
1
0
1
0
1
0
1
0
4032
:
2176
2048
:
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
2112
:
1056
1088
1024
:
544
512
:
272
256
:
136
128
:
:
528
:
1
0
0
0
0
1
0
1
1
1
1
0
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
264
:
132
:
66
:
68
64
1
1
0
1
0
1
0
1
1
:
2
0
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
16.3. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE
µ-Law
A-Law
Level
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
+ Full Scale
+ Zero
1
1
0
0
000
111
111
000
0000
1111
1111
0000
1
1
0
0
010
101
101
010
1010
0101
0101
1010
- Zero
- Full Scale
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
16.3.1. µ-LAW / A-LAW CODES FOR 0DBM0 OUTPUT (DIGITAL MILLIWATT)
µ-Law
A-Law
Chord bits
Sample
Sign bit
(D7)
Chord bits
(D6,D5,D4)
Step bits
(D3,D2,D1,D0)
Sign bit
(D7)
Step bits
(D3,D2,D1,D0)
(D6,D5,D4)
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
001
000
000
001
001
000
000
001
1110
1011
1011
1110
1110
1011
1011
1110
0
0
0
0
1
1
1
1
011
0100
0001
0001
0100
0100
0001
0001
0100
010
010
011
011
010
010
011
16.4. 16-BIT LINEAR PCM CODES FOR ZERO AND FULL SCALE
Level
Sign bit
Magnitude Bits
+ Full Scale
+ One Step
Zero
0
0
0
1
1
111.1111 1111 1111
000 0000 0000 0001
000 0000 0000 0000
111 1111 1111 1111
000 0000 0000 0000
- One Step
- Full Scale
16.5. 16-BIT LINEAR PCM CODES FOR 1 KHZ DIGITAL MILLIWATT
Phase
Sign bit
Magnitude Bits
π / 8
0
0
0
0
1
1
1
1
010 0001 1110 0011
101 0001 1101 0000
101 0001 1101 0000
010 0001 1110 0011
101 1110 0001 1100
010 1110 0010 1111
010 1110 0010 1111
101 1110 0001 1100
3 π / 8
5 π / 8
7 π / 8
9 π / 8
11 π / 8
13 π / 8
15 π / 8
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
17. TYPICAL APPLICATION CIRCUITS
17.1. N682386/7
Figure 49: Typical Application Circuit for N682386/7
Note: Please contact local sales/FAEs for latest reference design package
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
17.2. LINE DRIVER
17.2.1. N681622 SUBSCRIBER LINE FEED CIRCUIT (SLFC) FOR CHANNEL 1
Figure 50: N681622 Subscriber Line Feed Circuit (SLFC) for Channel 1
Note: Please contact local sales/FAEs for latest reference design package
Revision 1.3
Page 152 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
17.2.2. DISCRETE LINE FEED CIRCUIT FOR CHANNEL 1
Figure 51: Line-driver circuit for Channel1
Note: Please contact local sales/FAEs for latest reference design package
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
17.3. CHANNEL 1 DC-DC
Figure 52: Inductor based circuit for Channel 1
Note: Please contact local sales/FAEs for latest reference design package
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
17.4. TRIPLE BATTERY SWITCH APPLICATION
2
3
2
4
3
2
1
4
2
3
2
3
Figure 53: Triple Battery based Switch 1
Note: Please contact local sales/FAEs for latest reference design package
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
18. PACKAGE SPECIFICATION
18.1. TQFP64L (10X10X1.4MM FOOTPRINT 2.0MM)
Revision 1.3
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
18.2. QFN 64L 9X9 MM^2, THICKNESS :1.0 MM (PUNCH TYPE)
Revision 1.3
Page 157 of 160
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N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
18.3. QFN 20L 4X4 mm2, PITCH:0.50 mm
Revision 1.3
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Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
19. ORDERING INFORMATION
Nuvoton Part Number Description
N682386/87_ _
Product Family
Package Material:
Pb-free Package
G
=
Package Type:
M
Y
=
=
TQFP-64
QFN-64
When ordering N682386/87 series devices, please refer to the following part numbers:
Temp
Package
Material
Part Number
Package
64-TQFP
Range (oC)
N682386MG
N682387MG
-40 to 85
-40 to 85
Pb-Free
Pb-Free
N682386YG
N682387YG
64-QFN
N681622_ _
Package Material:
Product Family
G
=
Pb-free Package
Package Type:
QFN-20
Y
=
When ordering N681622 series devices, please refer to the following part numbers:
Temp
Package
Material
Part Number
N681622YG
Package
20-QFN
Range (oC)
-40 to 85
Pb-Free
Revision 1.3
Page 159 of 160
Sep 2010
N682386/87 + N681622
Dual Programmable Extended Codec/SLCC + SLFC
20. VERSION HISTORY
VERSION
1.0
DATE
PAGE
NA
DESCRIPTION
March 2010
151-154
2, 5, 152
77, 108
84
Reference schematic updates
1.1
March 25, 2010
April 6, 2010
N681622 pin diagram, description, and Reference Schematic updates for
pin 13 and pin 14 – not connected on Rev. BB
Updated Register RTLC(0X46):[7] as RESERVED BIT
1.2
Device ID is added to DVID register (0x07) for N682387 (WB) and
N682386 (NB)
April 14, 2010
April 22, 2010
159
Package type change: DG to MG (TQFP) on N682386/7
Update ILIM(0x23):TINS[3] description - Idle State Battery Current Stops
TIN in idle for lower power
94
April 27, 2010
June 3, 2010
July 12, 2010
3, 7, 67, 80 Description changes from N681386 to N682386
61
Description updates for 0x6A and 0x6B table location
1.3
Sampling rate for tone generation changed to 16KHz for two-pole oscillator
circuit. Block diagram is updated on Figure 8.
35, 37
Sep. 1, 2010
Sep. 8, 2010
Description improvement regarding ringing distance over REN (12.1.3.2)
and Hybrid Balance performance (12.1.6.1.3)
38, 54
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or
equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for
applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.
Revision 1.3
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Sep 2010
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