N9H26 [NUVOTON]
ARM® ARM926EJ-S Based 32-bit Microprocessor;
| 型号： | N9H26 |
| 厂家： | 
NUVOTON |
| 描述： | ARM® ARM926EJ-S Based 32-bit Microprocessor |
| 文件： | 总63页 (文件大小：2038K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N9H26
ARM® ARM926EJ-S Based
32-bit Microprocessor
N9H26 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ARM926EJ-S based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Oct. 16, 2019
Page 1 of 63
Rev 1.10
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TABLE OF CONTENTS
*
LIST OF FIGURES............................................................................................... 5
LIST OF TABLES ................................................................................................ 6
1 GENERAL DESCRIPTION.............................................................................. 7
1.1 Applications.....................................................................................................................7
2 FEATURES...................................................................................................... 8
3 PARTS INFORMATION LIST AND PIN CONFIGURATION..........................14
3.1 N9H26 Series Part Number Naming Guide.............................................................14
3.2 N9H26 Series Part Selection Guide..........................................................................15
3.3 Pin Configuration..........................................................................................................16
3.3.1 N9H26 Series Pin Diagram .......................................................................................... 16
3.4 Pin Description .............................................................................................................17
4 BLOCK DIAGRAM.........................................................................................31
4.1 N9H26 Series Block Diagram ....................................................................................31
5 FUNCTIONAL DESCRIPTION .......................................................................32
5.1 ARM® ARM926EJ-S CPU Core.................................................................................32
5.1.1 Overview ......................................................................................................................... 32
5.2 System Manager..........................................................................................................33
5.2.1 Overview ......................................................................................................................... 33
5.3 Clock Controller (CLK_CTL) ......................................................................................33
5.3.1 Overview ......................................................................................................................... 33
5.4 SDRAM Interface Controller (SDIC) .........................................................................33
5.4.1 Overview ......................................................................................................................... 33
5.5 2D Blitting Accelerator.................................................................................................33
5.5.1 Overview ......................................................................................................................... 33
5.6 VPE Video Data Processing Engine.........................................................................34
5.6.1 Overview ......................................................................................................................... 34
5.7 JPEG Codec (JPEG)...................................................................................................34
5.7.1 Overview ......................................................................................................................... 34
5.8 CAPTURE Engine........................................................................................................34
5.8.1 Overview ......................................................................................................................... 34
5.9 H.264 Video Codec......................................................................................................34
5.9.1 Overview ......................................................................................................................... 34
5.10 LCD Display Interface Controller (VPOST)........................................................34
5.10.1Overview ......................................................................................................................... 34
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5.11 Sound Processing Unit (SPU)..............................................................................34
5.11.1Overview ......................................................................................................................... 35
5.12 I2S Controller (I2S)..................................................................................................35
5.12.1Overview ......................................................................................................................... 35
5.13 Storage Interface Controller .................................................................................35
5.13.1Overview ......................................................................................................................... 35
5.14 USB 2.0 Device Controller (USBD).....................................................................35
5.14.1Overview ......................................................................................................................... 35
5.15 USB Host Controller (USBH)................................................................................35
5.15.1Overview ......................................................................................................................... 35
5.16 Enhanced DMA Controller ....................................................................................36
5.16.1Overview ......................................................................................................................... 36
5.17 Advanced Interrupt Controller (AIC)....................................................................36
5.17.1Overview ......................................................................................................................... 36
5.18 General Purpose I/O (GPIO)................................................................................36
5.18.1Overview ......................................................................................................................... 36
5.19 Timer Controller (TMR) .........................................................................................36
5.19.1Overview ......................................................................................................................... 36
5.20 Watchdog Timer (WDT).........................................................................................37
5.20.1Overview ......................................................................................................................... 37
5.21 Real Time Clock (RTC) .........................................................................................37
5.21.1Overview ......................................................................................................................... 37
5.22 I2C Synchronous Serial Interface Controller (I2C).............................................37
5.22.1Overview ......................................................................................................................... 37
5.23 Pulse Width Modulation (PWM)...........................................................................37
5.23.1Overview ......................................................................................................................... 37
5.24 UART Interface Controller (UART)......................................................................37
5.24.1Overview ......................................................................................................................... 37
5.25 SPI Interface Controller (SPI Master/Slaver).....................................................38
5.25.1Overview ......................................................................................................................... 38
5.26 Analog to Digital Converter (ADC) ......................................................................38
5.26.1Overview ......................................................................................................................... 38
5.27 Keypad Interface (KPI)..........................................................................................38
5.27.1Overview ......................................................................................................................... 38
5.28 Ethernet MAC Controller.......................................................................................38
5.28.1Overview ......................................................................................................................... 38
5.29 Audio Record Control............................................................................................38
5.29.1Overview ......................................................................................................................... 38
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5.30 AAC IMDCT/MDCT Engine ..................................................................................39
5.30.1Overview ......................................................................................................................... 39
5.31 Secure-Digital Input / Output Controller..............................................................39
5.31.1Overview ......................................................................................................................... 39
6 ELECTRICAL CHARACTERISTICS..............................................................40
6.1 Absolute Maximum Ratings........................................................................................40
6.2 DC Electrical Characteristics......................................................................................41
6.2.1 N9H26 Series DC Electrical Characteristics.............................................................. 41
6.3 AC Electrical Characteristics......................................................................................43
6.3.1 External 12 MHz Crystal ............................................................................................... 43
6.3.2 Power-on Sequence & RESET.................................................................................... 44
6.3.3 Sensor/Video-In Interface............................................................................................. 45
6.3.4 I2C Interface ................................................................................................................... 46
6.3.5 I2S Interface ................................................................................................................... 47
6.3.6 LCD/Display Interface ................................................................................................... 48
6.3.7 SPI Interface................................................................................................................... 50
6.3.8 NAND Interface .............................................................................................................. 51
6.3.9 SD Card Interface .......................................................................................................... 52
6.3.10USB PHY Specifications............................................................................................... 53
6.3.11Ethernet Interface Timing.............................................................................................. 54
6.3.12Specifications of 12-bit SARADC ................................................................................ 56
6.3.13Specifications of 24-bit Delta-Sigma CODEC............................................................ 57
6.3.14Specification of Low Voltage Reset............................................................................. 58
6.3.15Specifications of Power-on Reset (3.3V).................................................................... 58
6.4 Thermal Characteristics of N9H26 Package ...........................................................58
7 PACKAGE DIMENSIONS ..............................................................................59
7.1 128L LQFP (14x14x1.4mm footprint)........................................................................59
7.2 PCB Reflow Profile Suggestion .................................................................................60
7.2.1 Profile Setting Consideration........................................................................................ 60
7.2.2 Profile Suggestion for N9H26 series........................................................................... 61
8 REVISION HISTORY......................................................................................62
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LIST OF FIGURES
Figure 3-1 N9H26 Series Part Number Naming Guide ..................................................................14
Figure 3.3-1 N9H26 LQFP 128 Pin Diagram..................................................................................16
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LIST OF TABLES
No table of figures entries found.
Oct. 16, 2019
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1
GENERAL DESCRIPTION
The N9H26 series is built on the ARM926EJ-S CPU core and integrated with USB2.0 HS Host/Device,
NAND/eMMC/SD/SDIO/SPI host controller, video codec (H.264), JPEG codec, 32-channel SPU
(Sound Processing Unit), ADC, DAC and AAC accelerator for saving the BOM cost in various kinds of
application needs to be the best choice.
The N9H26 series could also be ported under Linux OS to leverage the driver availability of emerging
functionalities such as Wi-Fi, etc., maximum resolutions for N9H26 is1024x768 @ TFT LCD panel. On
the other hand, the open source code environment provides the product development more flexibility
and Nuvoton’s continuous optimizations in Linux provide customers with a cost-effective solution.
Moreover, the 3rd parties USB and SDIO Wi-Fi modules are introduced to best utilize Wi-Fi streaming
application.
To reduce system complexity while cutting the BOM cost, the N9H26 series provides MCP (Multi-Chip
Package) to ensure higher performance and to minimize the system design efforts.Total BOM cost
could be cut by employing 2-layer PCB along with the elimination of external parts, EMI prevention
components and saving board space.
1.1
Applications
HMI
Home Appliance
Advertisement
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2
FEATURES
CPU
ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache
CPU 240MHz is for typical operation and the speed could be up to 264MHz if function
without USB Host
JTAG interface supported for development and debugging
Internal SRAM & ROM
16KB IBR internal booting ROM supported
IBR booting messages displayed by UART console for debugging supported
Different system booting modes supported:
Memory Card
SD card
SD-to-NAND flash bridge
NAND Interface
Raw NAND Flash
SPI Flash
USB Mass Storage
SDRAM MCP
16Mbx16 DDR2 MCP for N9H26K51N
EDMA (Enhanced DMA)
Totally 11 DMA channels supported
8 peripheral DMA channels for transfer between memory and on-chip peripherals,
such as ADC, UART and SPI
3 dedicated channels for memory-to-memory transfer
Byte, half-word and word data width types supported
Single and burst transfer modes supported
Block transfer supported in memory-to-memory transfer channel
Color format transformation supported in memory-to-memory transfer channel
Source color format could be RGB555, RGB565 and YCbCr422
Destination color format could be RGB555, RGB565 and YCbCr422
Auto reload supported for continuous data transfer
Interrupt generation supported in the half-of-transfer or end-of-transfer
Capture (CMOS Image Sensor I/F)
CCIR601 & CCIR656 interfaces supported for connection to CMOS image sensor
Resolution up to 3M pixels
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color format supported for data storing to system
memory
Planar and packet data formats supported for data storing to system memory
Image cropping supported with the cropping window up to 4096x2048
Image scaling-down supported
Vertical and horizontal scaling-down for preview mode supported
The scaling factor is N/M
Two pairs of configurable 16-bit N and 16-bit M for vertical and horizontal scaling-
down
The value of N has to equal to or less than M
Frame rate control supported
Combines two interlace fields to a single frame supported for data in from TV-decoder
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Supports 1280x1024@15fps CIS (PCLK up to 48MHz)
Supports 1280x720@30fps CIS (PCLK up to 67.5MHz)
Supports 640x480@60fps CIS (PCLK up to 48MHz)
JPEG Codec
Baseline sequential mode JPEG codec function compliant with ISO/IEC 10918-1
international JPEG standard supported.
Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)
format image
Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
Support rotate function in encode mode
Packet Format
Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and
4:2:0 format
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image RGB555, RGB565 and RGB888 formats.
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for
decode mode
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
H.264 Codec
Supports ITU-T Recommendation H.264|ISO/IEC 14496-10 Advance Video Coding(AVC)
Standard (MPEG-4 part 10) baseline profile Level 3.1 standard
Supports up to the 720p @25fps video resolution
Supports YUV 4:2:0 video input format (MB base)
Hardware block-base rate-control (CBR/VBR)
Pure hardware engine
Video Data Processor(VPE)
Video Data Processor
Image/Video data format conversion
Source
-
-
Planar: YUV/YCbCr 444/422/420
Packet: YUV 422
Destination
-
Packet: YUV 422, RGB 555/565/888
Image/video 2-D rotation and coordinate transforming
Left/Right with 90/180 degrees, mirror, up-side-down, and flip/flop.
Arbitrary scaling up/down with the bilinear filter
Supports MMU DMA
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CRC Generator/Checking Hardware Engine
CRC16: x^16+x^15+x^2+1 or x^16+x^15+x^5+1 (CRC-CCITT)
CRC32: x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
VPOST
8/16/18/24-bit SYNC type and 8/9/16/18/24-bit MPU type TFT LCD supported
Color format supported:
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data in
YCbCr422, RGB565, RGB555, and RGB888 color formats supported for data out
SVGA (800x600), WVGA (800x480), D1 (720X480), VGA (640x480), WQVGA (480x272),
QVGA (320x240) and HVGA (640x240) resolution supported
The maximum resolution is up to 1024x768 for TFT LCD panel
Display scaling to fit different size of LCD panels
Horizontal: At most 4.0x scale
Vertical: At most 3.0x scale
For SYNC type LCD:
For 8-bit bus
CCIR601 YCbCr422 packet mode (NTSC/PAL) supported
CCIR601 RGB Dummy mode (NTSC/PAL) supported
CCIR656 interface supported
RGB Through mode supported
For 16/18/24-bit bus
Parallel pixel data output mode (1-pixel/1-clock)
Color format transform supported:
Color format transform between YCbCr422 and RGB565
Color format transform from YCbCr422 to RGB888
Support OSD functions to overlap system information like battery life, brightness tuning,
volume tuning or muting, etc.
SPU (Sound Processing Unit)
7-bit volume control supported for each of 32 channels
5-bit pan control supported for each L/R of 32 channels
10-band equalizer supported
Special code supported for loop playing and event detection
AAC accelerator
MDCT/IMDCT engine
I2S Controller
I2S interface supported to connect external audio codec
16/18/20/24-bit data format supported
Storage Interface Controller
Interface to NAND Flash:
8-bit data bus width supported
SLC and MLC type NAND Flash supported
512B, 2KB, 4KB, and 8KB page size NAND Flash supported
ECC24 algorithm supported for ECC generation, error detection and error correction
PBA-NAND flash supported
Interface to SD/MMC/SDIO/SDHC/micro-SD cards supported
SD-to-NAND flash bridge supported
DMA function supported to accelerate the data transfer between system memory and
NAND Flash or SD/MMC/SDIO/SDHC/micro-SD
USB Device Controller
USB2.0 HS (High-Speed) x 1 port
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6 configurable endpoints supported
Control, Bulk, Interrupt and Isochronous transfers supported
Suspend and remote wakeup supported
USB Host Controllers
One USB 1.1 Host port (lite)
One USB 2.0 Host port
Over Current detection required
Fully compliant with USB Revision 1.1 and 2.0 specifications
Open Host Controller Interface (OHCI) Revision 1.0 compatible
High-speed (480Mbps), Full-speed (12Mbps) and low-speed (1.5Mbps) USB devices
supported
Control, Bulk, Interrupt and Isochronous transfers supported
Ethernet MAC Controller
Supports IEEE Std. 802.3 CSMA/CD protocol.
Supports both half and full duplex for 10M/100M bps operation.
Supports RMII interface.
Supports MII Management function.
Supports pause and remote pause function for flow control.
Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes)
reception.
Supports 16 entries CAM function for Ethernet MAC address recognition.
Supports internal loop back mode for diagnostic.
Supports 256 bytes embedded transmit and receive FIFO.
Supports DMA function.
Timer & Watch-Dog Timer
Four 32-bit with 8-bit pre-scalar timers supported
One programmable 24-bit Watch-Dog Timer supported
PWM
4 PWM channel outputs supported
16-bit counter supported for each PWM channel
Two 8-bit pre-scalars supported and each pre-scalar shared by two PWM channels
Two clock-dividers supported and each divider shared by two PWM channels
Two Dead-Zone generators supported and each generator shared by two PWM channels
Auto reloaded mode and one-shot pulse mode supported
Capture function supported
UART
A high speed UART supported:
Baud rate is up to 1M bps
4 signals TX, RX, CTS and RTS supported
A normal UART supported:
Baud rate is up to 115.2K bps
2 signals TX and RX supported only
SPI
Two SPI interfaces are supported
Both master and slave mode are supported in SPI interface 0
Only master mode is supported in SPI interface 1
Byte transfer with configurable stop interval supported
Supports 1/2/4 bit SPI NOR Flash interface timing specification
I2C
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One I2C channel supported
Compatible with Philips’s I2C standard and only master mode supported
Multi-master operation supported
Advanced Interrupt Controller
Total 32 interrupt source supported
Configurable interrupt type:
Low-active level triggered interrupt
High-active level triggered interrupt
Low-active edge (falling edge) triggered interrupt
High-active edge (rising edge) triggered interrupt
Individual interrupt mask bit for each interrupt source
8 different priority levels supported
Low priority interrupt automatic masking supported for interrupt nesting
Internal SRAM
8KB embedded SRAM
Co-work with Fast Booting (<3 seconds) for reducing system power consumption.
RTC
Independent power plane supported
32.768 KHz crystal oscillation circuit supported
Build-in 32KHz RC oscillator
Time counter (second, minute, hour) and Calendar counter (day, month, year) supported
Alarm supported (second, minute, hour, day, month and year)
12/24-hour mode and Leap year supported
Alarm to wake chip up from Standby mode or from Power-down mode supported
Wake chip up from Power-down mode by input pin supported
Power-off chip by register setting supported
Power-on timeout is supported for low battery protection
GPIO
80 programmable general purpose I/Os supported and separated into 5 groups
Individual configuration supported for each I/O signal
Configurable interrupt control functions supported
Configurable de-bounce circuit supported for interrupt function
Audio DAC
16-bit stereo DAC supported with headphone driver output
H/W volume control supported
Audio ADC
16-bit Sigma-Delta ADC supported
General-Purpose ADC (SAR ADC)
Multi-channel, 12-bit ADC supported
4 channels dedicated for 4-wire resistive touch sensor inputs
3 channels reserved for various purposes, like LVD (Low Voltage Detection), keypad
input, and light sensor
5-wire resistive touch sensor interface is also supported
Input voltage range from 0V ~ 3.3V supported
Maximum 16MHz input clock supported
Maximum 200K/s conversion rate supported
One high-speed channel for 1M SPS sampling rate
LVR (Low Voltage Reset) supported
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Power Management
Advanced power management including Power Down, Deep Standby, CPU Standby, and
Normal Operating modes
Normal Operating Mode
Core power is 1.2V and chip is in normal operation
CPU Standby Mode
Core power is 1.2V and only ARM CPU clock is turned OFF
Deep Standby Mode
Core power is 1.2V and all IP clocks are turned OFF
Power Down Mode
Only the RTC power is ON. Other 3.3V and 1.2V power are OFF
Operating Voltage
I/O: 3.3V
Core: 1.2V
DDR2: 1.8V
Package
LQFP-128
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3
PARTS INFORMATION LIST AND PIN CONFIGURATION
N9H26 Series Part Number Naming Guide
3.1
Figure 3-1 N9H26 Series Part Number Naming Guide
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3.2
N9H26 Series Part Selection Guide
N9H26K Series
Operting
Temperature
Core
Memory
USB
H/W Accelerator
LCD
Analog
Peripheral
Power
PKG
Part No.
H.264,
JPEG 24 XGA
Codec
LQFP-
128
(MCP)
32MB
DDR2
N9H26K51N
264 926
8
8
8
√
24
3
1
1
HS
√
√
√
√
√
4/5W 24
√
√
√
80
2
1
1/2/4bit
2
√
4
√
1.2 1.8 3.3
-20 to +85
UD
5 Resoltion: XGA (1024 x 768).
6 Status: MP - Mass Production, ES - Engineering Sample, UD - Under Development
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3.3
Pin Configuration
3.3.1
N9H26 Series Pin Diagram
Figure 3.3-1 N9H26 Series LQFP 128 Pin Diagram
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3.4
Pin Description
Name
Pin No
Type
I/O
O
Group
SD0
Description
SD0_D[2]
TRST_b
GPE[4]
SD Interface Port 0 Data Bit 2.
JTAG
GPIOE
SYSTEM
SD0
Alternative JTAG Interface Test Reset, Low Active.
GPIO Port E Bit 4.
1
I/O
O
LVD_O
Low Voltage Detect Indicator, Low Active.
SD Interface Port 0 Data Bit 3.
GPIO Port E Bit 5.
SD0_D[3]
GPE[5]
I/O
I/O
O
2
3
4
5
6
GPIOE
SYSTEM
SD0
POR_O
Power On Reset, Low Active.
SD Interface Port 0 Command.
Alternative JTAG Interface Test Mode Select.
GPIO Port E Bit 6.
SD0_CMD
TMS_b
I/O
O
JTAG
GPIOE
SD0
GPE[6]
I/O
I/O
O
SD0_CLK
TCK_b
SD Interface Port 0 Clock.
JTAG
GPIOE
SD0
Alternative JTAG Interface Test Clock.
GPIO Port E Bit 7.
GPE[7]
I/O
I/O
I
SD0_D[0]
TDI_b
SD Interface Port 0 Data Bit 0.
Alternative JTAG Interface Test Data In.
GPIO Port E Bit 2.
JTAG
GPIOE
SD0
GPE[2]
I/O
I/O
O
SD0_D[1]
TDO_b
SD Interface Port 0 Data Bit 1.
Alternative JTAG Interface Test Data Out.
GPIO Port E Bit 3.
JTAG
GPIOE
SPI1
GPE[3]
I/O
O
SPI1_DO_a
LVDATA[23]
GPB[12]
SP_D[7]
SPI1_DI_a
LVDATA[22]
GPB[11]
SP_D[6]
UD_CDET
Alternative SPI Interface Port 1 Data Out.
LCD Interface Data Bit 23.
O
LCM
7
I/O
I
GPIOB
CMOS
SPI1
GPIO Port B Bit 12.
Sensor Interface1st Port, Data Bit 7.
Alternative SPI Interface Port 1 Data In.
LCD Interface Data Bit 22.
I
O
LCM
8
9
I/O
I
GPIOB
CMOS
USBD20
GPIO Port B Bit 11.
Sensor Interface 1st Port, Data Bit 6.
USB Device Connect Detect, High Active.
I
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10
11
12
VDD12
MVDD
MVDD
P
P
P
VDD12
MVDD
MVDD
Core Logic Power.
SDRAM I/F Power.
SDRAM I/F Power.
Alternative SPI Interface Port 1 Device Select 0, Low
Active.
SPI1_CS0_a
O
SPI1
LVDATA[21]
GPB[10]
O
I/O
I
LCM
LCD Interface Data Bit 21.
13
14
GPIOB
CMOS
SPI1
GPIO Port B Bit 10.
SP_D[5]
Sensor Interface 1st Port, Data Bit 5.
Alternative SPI Interface Port 1 Clock.
LCD Interface Data Bit 20.
SPI1_CLK_a
LVDATA[20]
GPB[9]
O
O
I/O
I
LCM
GPIOB
CMOS
LCM
GPIO Port B Bit 9.
SP_D[4]
Sensor Interface 1st Port, Data Bit 4.
LCD Interface Data Bit 19.
LVDATA[19]
GPB[8]
O
I/O
I
15
16
17
GPIOB
CMOS
LCM
GPIO Port B Bit 8.
SP_D[3]
Sensor Interface 1st Port, Data Bit 3.
LCD Interface Data Bit 18.
LVDATA[18]
GPB[7]
O
I/O
I
GPIOB
CMOS
I2S
GPIO Port B Bit 7.
SP_D[2]
Sensor Interface 1st Port, Data Bit 2.
Alternative I2S Interface Data Input.
GPIO Port B Bit 6.
I2S_DIN_a
GPB[6]
I
I/O
I
GPIOB
CMOS
I2S
SP_D[1]
Sensor Interface 1st Port, Data Bit 1.
Alternative I2S Interface Data Output.
SD Interface Port 1 Data Bit 2.
GPIO Port B Bit 5.
I2S_DOUT_a
SD1_D[2]
GPB[5]
O
I/O
I/O
I
SD1
18
GPIOB
CMOS
I2S
SP_D[0]
Sensor Interface 1st Port, Data Bit 0.
Alternative I2S Interface Left/Right Channel Clock.
SD Interface Port 1 Data Bit 3.
GPIO Port B Bit 4.
I2S_WS_a
SD1_D[3]
GPB[4]
O
I/O
I/O
SD1
19
20
GPIOB
Sensor Interface 1st Port, Even/Odd Field Indicator,
high Active.
SP_FIELD
I
CMOS
I2S
I2S_BCLK_a
O
Alternative I2S Interface Bit Clock.
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SD1_CMD
GPB[3]
I/O
I/O
I
SD1
SD Interface Port 1 Command.
GPIO Port B Bit 3.
GPIOB
CMOS
I2S
SP_VSYNC
I2S_MCLK_a
SD1_CLK
GPB[2]
Sensor Interface 1st Port, Vertical Sync., High Active.
Alternative I2S Interface Master Clock.
SD Interface Port 1 Clock.
O
I/O
I/O
I
SD1
21
GPIOB
CMOS
SD1
GPIO Port B Bit 2.
SP_HSYNC
SD1_D[0]
GPB[1]
Sensor Interface 1st Port, Horizontal Sync., High Active.
SD Interface Port 1 Data Bit 0.
GPIO Port B Bit 1.
I/O
I/O
I
22
23
GPIOB
CMOS
SD1
SP_PCLK
SD1_D[1]
GPB[0]
Sensor Interface 1st Port, Pixel Clock Input.
SD Interface Port 1 Data Bit 1.
GPIO Port B Bit 0.
I/O
I/O
O
GPIOB
CMOS
SYSTEM
SYSTEM
VDD33
VDD12
SYSTEM
USBD20
USBD20
USBD20
USBD20
SP_CLKO
XOUT
Sensor Interface 1st Port, System Clock Output.
12MHz Crystal Output.
24
25
26
27
28
29
30
31
32
33
O
XIN
I
12MHz Crystal In.
VDD33
P
I/O Power.
VDD12
P
Core Logic Power.
UD_PLL_VDD12
UD_DM
P
PLL and USB Core Power.
I/O
I/O
P
USB 2.0 Device D-.
UD_DP
USB 2.0 Device D+.
UD_VDD33
UD_REXT
ADC_VDD33
ADC_TP_XM
SPI1_DI_b
SDIO_D[2]_b
GPG[14]
USB 2.0 PHY Power.
I
External Resister 12.1K Resistor Connected to Ground.
AP
AI
I
SAR_ADC SAR-ADC Power.
SAR_ADC Touch Panel XM.
SPI1
Alternative SPI Interface Port 1 Data In.
34
35
I/O
I/O
AI
O
SDIO
GPIOG
Alternative SDIO Interface Data Bit 2.
GPIO Port G Bit 14.
ADC_TP_YM
SPI1_DO_b
SDIO_D[3]_b
SAR_ADC Touch Panel YM.
SPI1
Alternative SPI Interface Port 1 Data Out.
Alternative SDIO Interface Data Bit 3.
I/O
SDIO
Oct. 16, 2019
Page 19 of 63
Rev 1.10
N9H26
GPG[15]
I/O
AI
GPIOG
GPIO Port G Bit 15.
ADC_TP_XP
SAR_ADC Touch Panel XP.
Alternative SPI Interface Port 1 Device Select 0, Low
Active.
SPI1_CS0_b
O
SPI1
36
SDIO_D[1]_b
GPG[13]
I/O
I/O
AI
O
SDIO
Alternative SDIO Interface Data Bit 1.
GPIO Port G Bit 13.
GPIOG
ADC_TP_YP
SPI1_CLK_b
SDIO_D[0]_b
GPG[12]
SAR_ADC Touch Panel YP.
SPI1
Alternative SPI Interface Port 1 Clock.
37
38
I/O
I/O
AI
AI
I
SDIO
GPIOG
Alternative SDIO Interface Data Bit 0.
GPIO Port G Bit 12.
ADC_VSENSE
ADC_AIN[3]
KPI_SI[0]_a
GPG[7]
SAR_ADC 5W Touch Panel Input Detection.
SAR_ADC ADC Analog Input Channel 3.
KPI_SI
GPIOG
Alternative KPI Scan In Bit 0.
GPIO Port G Bit 7.
I/O
AI
AI
I
ADC_AHS
ADC_AIN[1]
I2S_DI_b
SAR_ADC ADC Analog High Speed Input Channel.
SAR_ADC ADC Analog Input Channel 1.
39
40
I2S
Alternative I2S Interface Data Input.
Alternative KPI Scan In Bit 1.
GPIO Port G Bit 9.
KPI_SI[1]_a
GPG[9]
I
KPI_SI
GPIOG
I/O
AI
I/O
AP
ADC_AIN[2]
GPG[8]
SAR_ADC ADC Analog Input Channel 2.
GPIOG GPIO Port G Bit 8.
SAR_ADC SAR-ADC Ground.
41
42
ADC_VSS33
External Resistor12.1K Resistor connected to Ground
UH_REXT
I
USBH20
For USB 2.0 Host PHY.
USB 2.0 Host PHY Power.
USB 2.0 Host D+.
43
44
45
46
UH_VDD33
UH_DP
AP
I/O
I/O
AP
O
USBH20
USBH20
USBH20
USBH20
I2C
UH_DM
USB 2.0 Host D-.
UH_VDD12
ISCK_a
USB 2.0 Host Core Logic Power.
Alternative I2C Interface Clock.
GPIO Port B Bit 13.
47
48
GPB[13]
ISDA_a
I/O
I/O
GPIOB
I2C
Alternative I2C Interface Data.
Oct. 16, 2019
Page 20 of 63
Rev 1.10
N9H26
GPB[14]
I/O
I/O
O
GPIOB
SPI0
GPIO Port B Bit 14.
SPI0_D[3]_c
LVSYNC
SD0_CD_
GPA[1]
Alternative SPI Interface Port 0 Data Bit 3.
LCD Interface Vertical SYNC., High Active.
SD Interface Card 0 Insert Detect, Low Active.
GPIO Port A Bit 1.
LCM
I
SD0
49
I/O
I
GPIOA
SD1
SD1_CD_
SP2_PCLK_a
SPI0_D[2]_c
LVDEN
SD Interface Crad 1 Insert Detect, Low Active.
Alternative Sensor Interface 2nd Port, Pixel Clock.
Alternative SPI Interface Port 0 Data Bit 2.
LCD Interface Data Enable, High Active.
SD Interface 0 Write Protect Indicator, Low Active.
GPIO Port A Bit 0.
I
CMOS2
SPI0
I/O
O
LCM
SD0_WP_
GPA[0]
I
SD0
50
I/O
I/O
O
GPIOA
SD1
SD1_WP_
SP2_CLKO_a
RST_
SD Interface 1 Write Protect Indicator, Low Active.
CMOS2
SYSTEM
SYSTEM
SYSTEM
KPI_SI
GPIOA
LCM
Alternative Sensor Interface 2nd Port, System Clock.
System Reset, Low Active.
Power On Reset, Low Active.
Low Voltage Reset Indicator, Low Active.
Alternative KPI Scan In Bit 0.
GPIO Port A Bit 3.
I
51
52
53
POR_O
O
LVR_O
O
KPI_SI[0]_c
GPA[3]
I
I/O
O
LVDATA[0]
GPC[0]
LCD Interface Data Bit 0.
GPIO Port C Bit 0.
I/O
O
GPIOC
KPI_SO
LCM
KPI_SO[0]
LVDATA[1]
GPC[1]
KPI Scan Out Bit 0.
O
LCD Interface Data Bit 1.
GPIO Port C Bit 1.
54
55
56
I/O
O
GPIOC
KPI_SO
LCM
KPI_SO[1]
LVDATA[2]
GPC[2]
KPI Scan Out Bit 1.
O
LCD Interface Data Bit 2.
GPIO Port C Bit 2.
I/O
O
GPIOC
KPI_SO
LCM
KPI_SO[2]
LVDATA[3]
GPC[3]
KPI Scan Out Bit 2.
O
LCD Interface Data Bit 3.
GPIO Port C Bit 3.
I/O
O
GPIOC
KPI_SO
KPI_SO[3]
KPI Scan Out Bit 3.
Oct. 16, 2019
Page 21 of 63
Rev 1.10
N9H26
LVDATA[4]
GPC[4]
O
I/O
I
LCM
LCD Interface Data Bit 4.
GPIOC
ChipCFG
KPI_SO
LCM
GPIO Port C Bit 4.
57
58
59
60
CHIPCFG[8]
KPI_SO[4]
LVDATA[5]
GPC[5]
Chip Power On Configuration Data Bit 8.
KPI Scan Out Bit 4.
O
O
I/O
I
LCD Interface Data Bit 5.
GPIOC
ChipCFG
KPI_SO
LCM
GPIO Port C Bit 5.
CHIPCFG[9]
KPI_SO[5]
LVDATA[6]
GPC[6]
Chip Power On Configuration Data Bit 9.
KPI Scan Out Bit 5.
O
O
I/O
I
LCD Interface Data Bit 6.
GPIOC
ChipCFG
KPI_SO
LCM
GPIO Port C Bit 6.
CHIPCFG[10]
KPI_SO[6]
LVDATA[7]
GPC[7]
Chip Power On Configuration Data Bit 10.
KPI Scan Out Bit 6.
O
O
I/O
I
LCD Interface Data Bit 7.
GPIOC
ChipCFG
KPI_SO
LCM
GPIO Port C Bit 7.
CHIPCFG[11]
KPI_SO[7]
LVDATA[8]
SDIO_D[0]_a
REFCLK_a
GPC[8]
Chip Power On Configuration Data Bit 11.
KPI Scan Out Bit 7.
O
O
I/O
I
LCD Interface Data Bit 8.
SDIO
Alternative SDIO Interface Data Bit 0.
Alternative LAN RMII Interface, REFCLK input.
GPIO Port C Bit 8.
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
LCM
61
I/O
I
SP2_D[0]_a
KPI_SO[8]
KPI_SO[0]
LVDATA[9]
SDIO_D[1]_a
MDC_a
Alternative Sensor Interface 2nd Port, Data Bit 0.
KPI Scan Out Bit 8.
O
O
O
I/O
O
I/O
I
KPI Scan Out Bit 0.
LCD Interface Data Bit 9.
SDIO
Alternative SDIO Interface Data Bit 1.
Alternative LAN RMII Interface, MDC.
GPIO Port C Bit 9.
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
62
GPC[9]
SP2_D[1]_a
KPI_SO[9]
KPI_SO[1]
Alternative Sensor Interface Port 2nd Data Bit 1.
KPI Scan Out Bit 9.
O
O
KPI Scan Out Bit 1.
Oct. 16, 2019
Page 22 of 63
Rev 1.10
N9H26
LVDATA[10]
SDIO_D[2]_a
MDIO_a
O
LCM
LCD Interface Data Bit 10.
Alternative SDIO Interface Data Bit 2.
Alternative LAN RMII Interface, MDIO.
GPIO Port C Bit 10.
I/O
I/O
I/O
I
SDIO
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
VSS
63
GPC[10]
SP2_D[2]_a
KPI_SO[10]
KPI_SO[2]
VSS
Alternative Sensor Interface 2nd Port, Data Bit 2.
KPI Scan Out Bit 10.
O
O
KPI Scan Out Bit 2.
64
65
P
Ground
VDD33
P
VDD33
LCM
I/O Power.
LVDATA[11]
SDIO_D[3]_a
TXD0_a
O
LCD Interface Data Bit 11.
Alternative SDIO Interface Data Bit 3.
Alternative LAN RMII Interface TXD0.
GPIO Port C Bit 11.
I/O
O
SDIO
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
LCM
66
67
68
GPC[11]
I/O
I
SP2_D[3]_a
KPI_SO[11]
KPI_SO[3]
LVDATA[12]
SDIO_CMD_a
TXD1_a
Alternative Sensor Interface 2nd Port, Data Bit 3.
KPI Scan Out Bit 11.
O
O
KPI Scan Out Bit 3.
O
LCD Interface Data Bit 12.
Alternative SDIO Interface Command.
Alternative LAN RMII Interface TXD1.
GPIO Port C Bit 12.
I/O
I/O
I/O
I
SDIO
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
LCM
GPC[12]
SP2_D[4]_a
KPI_SO[12]
KPI_SO[4]
LVDATA[13]
SDIO_CLK_a
TXEN_a
Alternative Sensor Interface 2nd Port, Data Bit 4.
KPI Scan Out Bit 12.
O
O
KPI Scan Out Bit 4.
O
LCD Interface Data Bit 13.
Alternative SDIO Interface Clock.
Alternative LAN RMII Interface, TXEN.
GPIO Port C Bit 13.
O
SDIO
O
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
GPC[13]
I/O
I
SP2_D[5]_a
KPI_SO[13]
KPI_SO[5]
Alternative Sensor Interface 2nd Port, Data Bit 5.
KPI Scan Out Bit 13.
O
O
KPI Scan Out Bit 5.
Oct. 16, 2019
Page 23 of 63
Rev 1.10
N9H26
LVDATA[14]
SDIO_CD_a
O
I
LCM
LCD Interface Data Bit 14.
Alternative SDIO Interface Card Detect Indicator, Low
Active.
SDIO
Alternative LAN RMII Interface, carrier sense / receive
data valid
CRSDV_a
I/O
EMAC
69
GPC[14]
I/O
I
GPIOC
CMOS2
KPI_SO
KPI_SO
LCM
GPIO Port C Bit 14.
SP2_D[6]_a
KPI_SO[14]
KPI_SO[6]
LVDATA[15]
RXD0_a
Alternative Sensor Interface 2nd Port, Data Bit 6.
KPI Scan Out Bit 14.
O
O
O
I
KPI Scan Out Bit 6.
LCD Interface Data Bit 15.
EMAC
GPIOC
CMOS2
KPI_SO
KPI_SO
LCM
Alternative LAN RMII Interface, RXD0.
GPIO Port C Bit 15.
GPC[15]
I/O
I
70
SP2_D[7]_a
KPI_SO[15]
KPI_SO[7]
LVDATA[16]
SPI0_D[2]_b
RXD1_a
Alternative Sensor Interface 2nd Port, Data Bit 7.
KPI Scan Out Bit 15.
O
O
O
I/O
I
KPI Scan Out Bit 7.
LCD Interface Data Bit 16.
SPI0
Alternative SPI Interface Port 0 Data Bit 2.
Alternative LAN RMII Interface, RXD1.
GPIO Port E Bit 0.
EMAC
GPIOE
71
GPE[0]
I/O
Alternative Sensor Interface 2nd Port, Horizontal Sync.,
High Active.
SP2_HSYNC_a
I
CMOS2
LVDATA[17]
SPI0_D[3]_b
RXERR_a
GPE[1]
O
LCM
LCD Interface Data Bit 17.
I/O
I
SPI0
Alternative SPI Interface Port 0 Data Bit 3.
Alternative LAN RMII Interface, RXERR.
GPIO Port E Bit 1.
EMAC
GPIOE
72
I/O
Alternative Sensor Interface 2nd Port, Vertical Sync.,
High Active.
SP2_VSYNC_a
I
CMOS2
LVDEN
O
I
LCM
LCD Interface Data Enable, High Active.
Alternative LAN RMII Interface, REFCLK.
GPIO Port D Bit 11.
REFCLK_b
GPD[11]
EMAC
GPIOD
CMOS2
LCM
73
74
I/O
I
SP2_D[0]_b
LVSYNC
Alternative Sensor Interface 2nd Port, Data Bit 0.
LCD Interface Vertical SYNC., High Active.
O
Oct. 16, 2019
Page 24 of 63
Rev 1.10
N9H26
MDC_b
O
EMAC
GPIOD
CMOS2
LCM
Alternative LAN RMII Interface, MDC.
GPIO Port D Bit 10.
GPD[10]
SP2_D[1]_b
LHSYNC
GPD[9]
I/O
I
Alternative Sensor Interface 2nd Port, Data Bit 1.
LCD Interface Horizontal SYNC., High Active.
GPIO Port D Bit 9.
O
75
76
I/O
O
GPIOD
LCM
LPCLK
LCD Interface Pixel Clock.
GPB[15]
TRST_a
I/O
O
GPIOB
JTAG
GPIO Port B Bit 15.
Alternative JTAG Interface Test Reset, Low Active.
High Speed UART Request To Send.
HUR_RTS
SPI0_CS1_
UHL0_DM_a
GPD[4]
O
HUART
SPI0
O
SPI Interface Port 0 Device Select 1.
77
I/O
I/O
USBH11_0 Alternative USB 1.1 Host Lite Port 0 D-.
GPIOD
GPIO Port D Bit 4.
Alternative Sensor Interface 2nd Port, Horizontal
SYNC., High Active.
SP2_HSYNC_b
I
CMOS2
TDO_a
O
JTAG
HUART
PWM
Alternative JTAG Interface Test Data Out.
High Speed UART Clear to Send.
PWM Output Channel 3.
HUR_CTS
PWM3
I
O
UHL0_DP_a
LVD_O
I/O
O
USBH11_0 Alternative USB 1.1 Host Lite Port 0 D+.
78
SYSTEM
EMAC
Low Voltage Detect Output, Low Active.
Alternative LAN RMII Interface, MDIO.
GPIO Port D Bit 3.
MDIO_b
GPD3
I/O
I/O
GPIOD
Alternative Sensor Interface 2nd Port Vertical SYNC.,
High Active.
SP2_VSYNC_b
I
CMOS2
TDI_a
I
JTAG
Alternative JTAG Interface Test Data In.
High Speed UART RX Data.
PWM Output Channel 2.
HUR_RXD
PWM2
I
HUART
PWM
O
O
I/O
79
80
TXD0_b
GPD[2]
EMAC
GPIOD
Alternative LAN RMII Interface, TXD0.
GPIO Port D Bit 2.
Alternative Sensor Interface 2nd Port, System Clock
Output.
SP2_CLKO_b
O
CMOS2
TMS_a
O
O
JTAG
Alternative JTAG Interface Test Mode Select.
High Speed UART TX Data.
HUR_TXD
HUART
Oct. 16, 2019
Page 25 of 63
Rev 1.10
N9H26
PWM1_a
TXD1_b
GPD[1]
O
O
I/O
I
PWM
Alternative PWM Output Channel 1.
Alternative LAN RMII Interface, TXD1.
GPIO Port D Bit 1.
EMAC
GPIOD
CMOS2
JTAG
SP2_D[2]_b
TCK_a
Alternative Sensor Interface 2nd Port, Data Bit 2.
Alternative JTAG Interface Test Clock.
O
Alternative SPI Interface Port 1 Device Select 1, Low
Active.
SPI1_CS1_a
O
SPI1
PWM0_a
TXEN_b
GPD[0]
O
O
I/O
I
PWM
Alternative PWM Output Channel 0.
Alternative LAN RMII Interface, TXEN.
GPIO Port D Bit 0.
81
EMAC
GPIOD
CMOS2
VDD12
MVDD
MVDD
SP2_D[3]_b
VDD12
Alternative Sensor Interface 2nd port, Data Bit 3.
Core Logic Power.
82
83
84
P
MVDD
P
SDRAM I/F Power.
MVDD
P
SDRAM I/F Power.
External Resistor Connection, cnnect a 270 Ohm to
Ground.
TVDAC_REXT
I2S_BCLK_b
SPI1_CS0_c
SDIO_CLK_b
CRSDV_b
I
TV
O
O
O
I
I2S
Alternative I2S Interface Bit Clock.
Alternative SPI Interface Port 1 Device Select 0, Low
Active.
SPI1
SDIO
EMAC
85
Alternative SDIO Interface Clock.
Alternative LAN RMII Interface, carrier sense / receive
data valid.
GPG[3]
I/O
GPIOG
CMOS2
TV
GPIO Port G Bit 3.
SP2_D[6]_b
TVDAC_VREF
I2S_MCLK_b
ISDA_b
I
Alternative Sensor Interface 2nd Port, Data Bit 6.
TV DAC Reference Voltage Output.
Alternative I2S Interface Master Clock.
Alternative I2C Interface Data.
I
O
I/O
O
I
I2S
I2C
86
87
SPI1_DO_c
RXD0_b
SPI1
Alternative SPI Interface Port 1 Data Out.
Alternative LAN RMII Interface, RXD0.
GPIO Port G Bit 5.
EMAC
GPIOG
CMOS2
TV
GPG[5]
I/O
I
SP2_D[4]_b
TVDAC_COMP
Alternative Sensor Interface 2nd Port, Data Bit 4.
External Capacitor Connection.
I
Oct. 16, 2019
Page 26 of 63
Rev 1.10
N9H26
I2S_WS_b
SPI1_DI_c
O
I
I2S
Alternative I2S Interface Left/Right Channel Clock.
SPI1
Alternative SPI Interface Port 1 Data In.
Alternative SDIO Interface Card Detect Indicator, Low
Active.
SDIO_CD_b
I
SDIO
RXD1_b
I
EMAC
GPIOG
CMOS2
TV
Alternative LAN RMII Interface, RXD1.
GPIO Port G Bit 4.
GPG[4]
I/O
I
SP2_D[5]_b
TVDAC_TVOUT
I2S_DOUT_b
ISCK_b
Alternative Sensor Interface 2nd Port, Data Bit 5.
TV DAC Output.
O
O
O
O
I/O
I
I2S
Alternative I2S Interface Data Output.
Alternative I2C Interface Clock.
Alternative SPI Interface Port 1 Clock.
Alternative SDIO Interface Command.
Alternative LAN RMII Interface, RXERR.
GPIO Port G Bit 2.
I2C
SPI1_CLK_c
SDIO_CMD_b
RXERR_b
SPI1
SDIO
EMAC
GPIOG
CMOS2
TV
88
GPG[2]
I/O
I
SP2_D[7]_b
TVDAC_VDD33
RTC_VDD
Alternative Sensor Interface 2nd Port, Data Bit 7.
TV DAC Analog Power.
89
90
91
92
93
94
AP
P
O
I
RTC
RTC Power.
RTC_RPWR
RTC_RWAKE_
RTC_XIN
RTC
Power Enable, High Active.
RTC
Wakeup Enable, Low Active.
32.768KHZ Crystal Input.
I
RTC
RTC_XOUT
O
RTC
32.768KHZ Crystal Output.
Microphone Bias Power Supply output. (MIC_BIAS=0.75
* ADAC_AVDD33)
MIC_BIAS
Line_In
VMID
AP
AI
I
AUDIO
AUDIO
AUDIO
95
Analog Audio Input.
Mid-Rail Reference, connect 1uF to ADAC_VSS33. (1/2
* ADAC_VDD33).
96
97
MIC_IN_P
AI
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
Microphone Positive Input.
98
MIC_IN_M
AI
Microphone Negative Input.
99
ADAC_AVDD33
AP
Audio DAC Analog Power.
100
101
102
ADAC_HPVSS33 AP
ADAC_HPOUT_R O
Audio DAC and Headphone Analog Ground.
Headphone Right Output Channel.
Headphone Left Output Channel.
ADAC_HPOUT_L
O
Oct. 16, 2019
Page 27 of 63
Rev 1.10
N9H26
103
104
ADAC_HPVDD33 AP
AUDIO
UART
Headphone Analog Power.
UART TX Data.
UR_TXD
UHL1_DP
ISCK_c
O
I/O
O
USBH11_1 USB 1.1 Host Lite Port 1 D+.
I2C
Alternative I2C Interface Clock.
Alternative SPI Interface Port 1 Device Select 1, Low
Active.
SPI1_CS1_b
O
SPI1
GPA[10]
UR_RXD
UHL1_DM
ISDA_c
I/O
I
GPIOA
UART
GPIO Port A Bit 10.
UART RX Data.
I/O
I/O
I/O
I/O
USBH11_1 USB 1.1 Host Lite Port 1 D-.
I2C
Alternative I2C Interface Data.
105
LMVSYNC
GPA[11]
LCM
GPIOA
LCD Interface MPU Mode Vertical SYNC., High Active.
GPIO Port A Bit 11.
Alternative Sensor Interface 2nd Port, Even/Odd Field
Indicator.
SP2_FIELD_b
I
CMOS2
106
107
VDD12
P
VDD12
NAND
Core Logic Power.
ND[0]
I/O
I
NAND Interface Data Bit 0.
CHIPCFG[0]
ND[1]
ChipCFG
NAND
Chip Power On Configuration Data Bit 0.
NAND Interface Data Bit 1.
I/O
I
108
109
CHIPCFG[1]
ND[2]
ChipCFG
NAND
Chip Power On Configuration Data Bit 1.
NAND Interface Data Bit 2.
I/O
I
CHIPCFG[2]
ND[3]
ChipCFG
NAND
Chip Power On Configuration Data Bit 2.
NAND Interface Data Bit 3.
I/O
I/O
I
110
111
SD2_D[3]
CHIPCFG[3]
ND[4]
SD2
SD Interface Port 2 Data Bit 3.
Chip Power On Configuration Data Bit 3.
NAND Interface Data Bit 4.
ChipCFG
NAND
I/O
I/O
I
GPA[12]
CHIPCFG[4]
ND[5]
GPIOA
ChipCFG
NAND
GPIO Port A Bit 12.
Chip Power On Configuration Data Bit 4.
NAND Interface Data Bit 5.
I/O
I/O
I
112
113
GPA[13]
CHIPCFG[5]
ND[6]
GPIOA
ChipCFG
NAND
GPIO Port A Bit 13.
Chip Power On Configuration Data Bit 5.
NAND Interface Data Bit 6.
I/O
Oct. 16, 2019
Page 28 of 63
Rev 1.10
N9H26
GPA[14]
CHIPCFG[6]
ND[7]
I/O
I
GPIOA
ChipCFG
NAND
GPIOA
ChipCFG
NAND
SD2
GPIO Port A Bit 14.
Chip Power On Configuration Data Bit 6.
NAND Interface Data Bit 7.
I/O
I/O
I
114
115
GPA[15]
CHIPCFG[7]
NBUSY1_
SD2_CD_
OV_FLAG
GPD[6]
GPIO Port A Bit 15.
Chip Power On Configuration Data Bit 7.
NAND Interface Busy Indicator 1, Low Active.
I
I
SD Interface Port 2, Card Insert Detect, Low Active.
USB HOS Power Over Current Occurrence Flag.
GPIO Port D Bit 6.
I
USBH20
GPIOD
CMOS2
NAND
SD2
I/O
I
SP2_PCLK_b
NBUSY0_
SD2_D[2]
GPD[5]
Alternative Sensor Interface 2nd Port, Pixel Clock Input.
NAND Interface Busy Indicator 0, Low Active.
SD Interface Port 2 Data Bit 2.
I
116
117
118
119
120
I/O
I/O
O
GPIOD
NAND
SD2
GPIO Port D Bit 5.
NWR_
NAND Interface Write Enable, Low Active.
SD Interface Port 2 Command.
SD2_CMD
GPD[8]
I/O
I/O
O
GPIOD
NAND
SD2
GPIO Port D Bit 8.
NRE_
NAND Interface Read Enable, Low Active
SD Interface Port 2 Clock.
SD2_CLK
GPD[7]
O
I/O
O
GPIOD
NAND
SD2
GPIO Port D Bit 7.
NCLE
NAND Interface Command Latch Enable, Low Active
SD Interface Port 2 Data Bit 1.
SD2_D[1]
GPE[11]
NALE
I/O
I/O
O
GPIOE
NAND
SD2
GPIO Port E Bit 11.
NAND Interface Address Latch Enable, Low Active
SD Interface Port 2 Data Bit 0.
SD2_D[0]
GPE[10]
NCS1_
I/O
I/O
O
GPIOE
NAND
SPI0
GPIO Port E Bit 10.
NAND Interface Device Select 1, Low Active.
Alternative SPI Interface Port 0 Data Bit 3.
USB HOST Power Output Control.
GPIO Port E Bit 9.
SPI0_D[3]_a
USB_PWEN
GPE[9]
I/O
O
121
122
USBH20
GPIOE
NAND
I/O
O
NCS0_
NAND Interface Device Select 0, Low Active
Oct. 16, 2019
Page 29 of 63
Rev 1.10
N9H26
SPI0_D[2]_a
GPE[8]
I/O
I/O
P
SPI0
Alternative SPI Interface Port 0 Data Bit 2.
GPIO Port E Bit 8.
GPIOE
VDD33
SPI0
123
124
VDD33
I/O Power.
SPI0_DI
I
SPI Interface Port 0 Data In.
UHL0_DP_b
KPI_SI[0]_b
DM_DIN
I/O
I
USBH11_0 Alternative USB 1.1 Host Lite Port 0 D+.
KPI_SI
DIG_MIC
GPIOD
SPI0
Alternative KPI Scan In Bit 0.
Digital Microphone Data Input.
GPIO Port D Bit 14.
I
GPD[14]
I/O
O
SPI0_CS0_
PWM1_b
GPD[13]
SPI Interface Port 0 Device Select 0.
Alternative PWM Output Channel 1.
GPIO Port D Bit 13.
125
126
O
PWM
I/O
O
GPIOD
SPI0
SPI0_DO
UHL0_DM_b
KPI_SI[1]_b
LVR_O
SPI Interface Port 0 Data Out.
I/O
I
USBH11_0 Alternative USB 1.1 Host Lite Port 0 D-.
KPI_SI
SYSTEM
GPIOD
SPI0
Alternative KPI Scan In Bit 1.
Low Voltage Reset Indicator, Low Active.
GPIO Port D Bit 15.
O
GPD[15]
I/O
O
SPI0_CLK
PWM0_b
DM_CLK
GPD[12]
SPI Interface Port 0 Clock.
Alternative PWM Output Channel 0.
Digital Microphone Clock.
GPIO Port D Bit 12.
O
PWM
127
O
DIG_MIC
GPIOD
VSS
I/O
P
128
VSS
Ground
Note:
TYPE
I
DESCRIPTION
Input
O
Output
I/O
P
Input / Output
Digital Power or Digital GND
Analog Power or Analog GND
Analog Input
AP
AI
Oct. 16, 2019
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N9H26
4
BLOCK DIAGRAM
4.1
N9H26 Series Block Diagram
ICE_CTRL
Bus service priority in SDIC
AHB4 > AHB3 > AHB1 > AXI > AHB5
MMU, I/D
Cache
ARM926EJ-S
M
DDR
DLL
GCR
S
PLLX3
CLKGEN
S
CRC X 2
S
TIC
M
8KB/8KB
AHB – 1
M
S
S
S
S
BLT
Capture1
AAC
EDMA/
APB Bridge
SDR/DDR/
DDR2 SDRAM
Controller
ROM
(16KB)
AHB Bridge
M
SRAM Controller
(8KB)
M
S
M
S
M
S
M
S
S
S
S
S
S
AHB – 4
AHB – 2
M
S
M
S
M
S
M
S
UEHCI 2.0
IIS
Controller
UOHCI 2.0
SPU
M
S
VPOST
AHB – 3
AHB – 5
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
IPSEC
AES
SD
SDIO
VPE
EMAC
JPEG
SIC
UHC
UDC 2.0
M
S
M
S
M
S
S
M
Rotation
Engine
(32KB)
FTMCP210
H.264
Encoder
FTMCP220
H.264
Decoder
Timer/
WDT
Capture0
RF_Codec
RS_Codec
KPI
S
AIC
S
RTC
S
S
S
APB
S
S
S
S
S
GPIO
S
PWM X 4
Audio
DAC
Video
DAC
USB 2.0 PHY
ADC
UART X 2
SPI X 2
I2C
USB 2.0 PHY
Figure 4.1 N9H26 Series Block Diagram
Oct. 16, 2019
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5
FUNCTIONAL DESCRIPTION
ARM® ARM926EJ-S CPU Core
5.1
5.1.1
Overview
The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose
microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full
memory management, high performance, and low power are all important.
The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling
the user to choose between high performance and high code density. The ARM926EJ-S CPU
core includes features for efficient execution of Java byte codes, providing Java performance
similar to JIT, but without the associated code overhead.
The ARM926EJ-S processor provides support for external coprocessor enabling floating-point or
other application-specific hardware acceleration to be added. The ARM926EJ-S CPU core
implements ARM architecture version 5TEJ.
The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-
performance processor subsystem, including:
An ARM9EJ-S integer core.
A Memory Management Unit (MMU).
Separate instruction and data cache.
Separate instruction and data AMBA AHB bus interfaces.
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5.2
System Manager
Overview
5.2.1
The system management describes following information and functions.
System Memory Map
Power-On Setting
Bus Arbitration Mode
Power Management
IBR (Internal Boot ROM) Sequence
System management registers for product ID, functional reset and multi-function pin
control.
5.3
5.3.1
Clock Controller (CLK_CTL)
Overview
The clock controller generates the clocks for the whole chip, it include all of IPs on AHB, APB and
engine clock like USB, UART and so on. There are three PLLs in this chip, and the PLL clock source is
from the external crystal input. It also implements the power control function, include the individually
clock on or off control register, clock source selector and divider. These functions minimize the extra
power consumption and the chip run on the only just condition. On the power down mode the controller
turn off the crystal oscillator to minimize the chip power consumption.
5.4
SDRAM Interface Controller (SDIC)
Overview
5.4.1
The SDRAM Controller support Low-Power DDR and DDR2 type SDRAM. The memory device size
type can be from 64M bit and up to 512M bits. Only 16-bit data bus width is supported. The total
system memory size can be from 8M-byte and up to 64M-byte for different SDRAM configuration.
5.5
2D Blitting Accelerator
Overview
5.5.1
The 2D blitting accelerator features are built on top of the FlashLite Bitmap rendering feature. It
improves rendering performance of bitmap objects (source image) onto the frame buffer (destination
image).
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5.6
VPE Video Data Processing Engine
Overview
5.6.1
Video Data Processing Engine (VPE) contains the acceleration engines for still images and video
movies.
The first function is for the image/video data format conversion and the second function is for the
image/video 2D rotation or the coordinate transformation.
5.7
JPEG Codec (JPEG)
Overview
5.7.1
The JPEG Codec supports Baseline Sequential Mode JPEG still image compression and
decompression that is fully compliant with ISO/IEC International Standard 10918-1 (T.81).
5.8
CAPTURE Engine
Overview
5.8.1
CAPTURE engine is designed to capture image data from sensor or TV decoder. After capturing or
fetching image data, capture engine processes the image data, and then FIFO output them into frame
buffer.
5.9
H.264 Video Codec
Overview
5.9.1
H.264 DEC is a video decoder, which supports the H.264 standard baseline profile. H.264 DEC is
compliant with the ITU-T Recommendation H.264|ISO/IEC 14496-10 Advanced Video Coding
Standard (MPEG 4 Part 10). This decoder is capable of decoding the video streams with a resolution
of up to 720 x 480 at a frame rate of up to 60 frames per second or decoding the video streams with a
resolution of up to 2048 x 1024 at a frame rate of up to 10 frames per second.
5.10 LCD Display Interface Controller (VPOST)
5.10.1 Overview
The main purpose of Display Controller is used to display the video/image data to LCD device or
connect with external TV-encoder. The video/image data source may come from the H.264 video
codec, JPEG decoder and the OSD pattern which have been stored in system memory (SDRAM). The
input data format of the display controller can be packet YUV422, packet YUV444, packet RGB444,
packet RGB565, packet RGB666, and packet RGB888. The OSD (On Screen Display) function
supports packet YUV422 and 8/16/24-bit direct-color mode. The LCD controller supports both sync-
type and MPU-type LCDM. This LCD Controller is a bus master and can transfer display data from
system memory (SDRAM) without CPU intervention.
5.11 Sound Processing Unit (SPU)
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5.11.1 Overview
The SPU performs 32 channels audio input and 16-bit stereo output to DAC and I2S. SPU support 3
data-types (E-MDPCM (4bit), PCM16, LP8) with event and raw PCM16 mono/stereo and Tone.
5.12 I2S Controller (I2S)
5.12.1 Overview
The audio controller consists of I2S protocols to interface with external audio CODEC. The I2S
interface supports 16, 18, 20 and 24-bit left/right precision in record and playback. When operating in
18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each left/right-channel
sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding zeros. When operating
in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and left-channel sample is
stored in LSB of a 32-bit word.
5.13 Storage Interface Controller
5.13.1 Overview
The Storage Interface Controller (SIC) has DMAC unit and FMI unit. The DMAC unit provides a DMA
(Direct Memory Access) function for FMI to exchange data between system memory and shared buffer
(128 bytes). The FMI control the interface of SD/SDHC/SDIO/MMC or NAND/SM. The storage
interface controller can support SD/SDHC/SDIO/MMC card and NAND-type flash and the FMI is
cooperated with DMAC to provide a fast data transfer between system memory and cards.
5.14 USB 2.0 Device Controller (USBD)
5.14.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains four configurable endpoints in addition to control
endpoint.These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device
controller has a built-in DMA to relieve the load of CPU.
5.15 USB Host Controller (USBH)
5.15.1 Overview
The Universal Serial Bus (USB) is a fast, bi-directional, isochronous, low-cost, dynamically attachable
serial interface standard intended for modem, scanners, PDAs, keyboards, mice, and digital imaging
devices. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host
Controller and a network of peripheral devices. The attached peripherals share USB bandwidth
through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and
detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is
supported).
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N9H26
5.16 Enhanced DMA Controller
5.16.1 Overview
The N9H26 series contains an enhanced direct memory access (EDMA) controller that transfers data
to and from memory or transfer data to and from APB. The EDMA controller has 6-channel DMA that
include 2 channel VDMA (Video-DMA, Memory-to-Memory) and four channels PDMA (Peripheral-to-
Memory or Memory-to-Peripheral). For channel0/5 VDMA mode, it also support color format transform
and stripe mode transfer. For PDMA channel (EDMA CH1~CH4), it can transfer data between the
Peripherals APB IP (ex: UART, SPI, ADC….) and Memory.
5.17 Advanced Interrupt Controller (AIC)
5.17.1 Overview
An interrupt temporarily changes the execution sequence of a program to react to a particular event
such as power failure, watchdog timer timeout, engines complete, system events, external event
trigger and so on. The ARM9 processor provides two modes of interrupts, the Fast Interrupt (FIQ)
mode for critical session and the Interrupt (IRQ) mode for general purpose. The IRQ exception is
occurred when the nIRQ input is asserted. Similarly, the FIQ exception is occurred when the nFIQ
input is asserted. The FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible
to ignore the FIQ and the IRQ by setting the F-bit and I-bit in the current program status register
(CPSR).
5.18 General Purpose I/O (GPIO)
5.18.1 Overview
80 pins of General Purpose I/O are shared with special feature functions.
Supported Features of these I/O are: input or output facilities, pull-up resistors.
All these general purpose I/O functions are achieved by software programming setting and I/O cells
selected from SMIC universal standard I/O Cell Library. And the following figures illustrate the control
mechanism to achieve the GPIO functions.
5.19 Timer Controller (TMR)
5.19.1 Overview
The timer module includes four channels, TIMER0~TIMER3, which allow you to easily implement a
counting scheme for use. The timer can perform functions like frequency measurement, event
counting, interval measurement, clock generation, delay timing, and so on. The timer possesses
features such as adjustable resolution, programmable counting period, and detailed information. The
timer can generate an interrupt signal upon timeout, or provide the current value of count during
operation.
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5.20 Watchdog Timer (WDT)
5.20.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
5.21 Real Time Clock (RTC)
5.21.1 Overview
Real Time Clock (RTC) block can be operated by independent power supply while the system power is
off. The RTC uses a 32.768 KHz external crystal or internal oscillator. It can transmit data to CPU with
BCD values. The data includes the time by (second, minute and hour), the day by (day, month and
year). In addition, to achieve better frequency accuracy, the RTC counter can be adjusted by software.
5.22 I2C Synchronous Serial Interface Controller (I2C)
5.22.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
5.23 Pulse Width Modulation (PWM)
5.23.1 Overview
There are 4 PWM-Timers. The 4 PWM-Timers has 2 Pre-scale, 2 clock divider, 4 clock selectors, 4 16-
bit counters, 4 16-bit comparators, 2 Dead-Zone generators. They are all driven by Crystal or system
clock. Each can be used as a timer and issues interrupt independently.
5.24 UART Interface Controller (UART)
5.24.1 Overview
The N9H26 series provides two channels of Universal Asynchronous Receiver/Transmitters (UART).
UART0 supports High Speed UART and UART1 perform Normal Speed UART, besides, only UART0
support flow control function.
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N9H26
5.25 SPI Interface Controller (SPI Master/Slaver)
5.25.1 Overview
The MICROWIRE/SPI Synchronous Serial Interface performs a serial-to-parallel conversion on data
characters received from the peripheral, and a parallel-to-serial conversion on data characters
received from CPU. This interface can drive up to 2 external peripherals and is seen as the master or
can be driven as the slave.
5.26 Analog to Digital Converter (ADC)
5.26.1 Overview
The N9H26 series contains one 12-bit Successive Approximation Register analog-to-digital converter
(SAR A/D converter) with eight input channels. The A/D converter supports two operation modes: 4-
wire or 5-wire mode. The ADC is especially suitable to act as touch screen controller. Battery voltage
detection could be easily accomplished by the SAR ADC. It has keypad interrupt signal generator.
5.27 Keypad Interface (KPI)
5.27.1 Overview
The Keypad Interface (KPI) is an APB slave with configurable minimum 2-row up to 16-row scan
output and minimum 1-column up to 4-column scan input. Any keys in the array pressed or released
are de-bounced and generate an interrupt.
5.28 Ethernet MAC Controller
5.28.1 Overview
The N3292x provides an Ethernet MAC Controller (EMC) for WAN/LAN application. This EMC has its
DMA controller, transmit FIFO, and receive FIFO.
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM
function for Ethernet MAC address recognition, Transmit-FIFO, Receive-FIFO, TX/RX state machine
controller and status controller. The EMC only supports RMII (Reduced MII) interface to connect with
PHY operating on 50MHz REF_CLK.
5.29 Audio Record Control
5.29.1 Overview
The Audio Record control has two parts. One is the analog IP (sigma-delta ADC), and the other is
digital audio record control.
The analog IP interface is I2C and I2S. I2C is for command, and I2S is for audio data.
Digital part includes three blocks, AGC and NG block, I2C wrapper, and Register. The Register block
is to handshake with APB bus. AGC and NG are to control the gain automatically. I2C wrapper is for
transferring the command to the ADC.
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Rev 1.10
N9H26
5.30 AAC IMDCT/MDCT Engine
5.30.1 Overview
AAC IMDCT/MDCT engine is designed to calculate the data for the AAC decoder or encoder.
5.31 Secure-Digital Input / Output Controller
5.31.1 Overview
The Secure-Digital Input/ Output Controller (SDIO) has DMAC unit and SD unit. The DMAC unit
provides a DMA (Direct Memory Access) function for SD to exchange data between system memory
and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC/SDIO/MMC. The
SDIO controller can support SD/SDHC/SDIO/MMC card and the FMI is cooperated with DMAC to
provide a fast data transfer between system memory and cards.
Oct. 16, 2019
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Rev 1.10
N9H26
6
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
6.1
Parameters
Values
Ambient Temperature
-20 °C ~ 85 °C
-40 °C ~ 125 °C
-0.3V ~ 3.6V
-0.5V ~ 1.5V
-0.5V ~ 4.6V
100mA
Storage Temperature
Voltage On Any Pin
Power Supply Voltage (Core Logic)
Power Supply Voltage (I/O Buffer)
Injection Current (Latch-Up Testing)
Crystal Frequency
1MHz ~ 20MHz
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of
the device.
Oct. 16, 2019
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Rev 1.10
N9H26
6.2
DC Electrical Characteristics
6.2.1
N9H26 Series DC Electrical Characteristics
(VDD-VSS=3.3 V, TA = 25C, FOSC = 12 MHz unless otherwise specified.)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD33
I/O Buffer Post-
Driver Voltage
2.97
3.30
3.63
V
V
VDD12
MVDD
Core
Logic
264MHz *. USB HOST must be disable
240MHz
1.14
1.20
1.80
1.3
Voltage
SDRAM
Voltage
396MHz MPLL_CLK@396MHz
360MHz MPLL_CLK@360MHz
1.75
2.0
1.9
3.6
V
RTC_VDD RTC Power Supply
V
IRTC_VDD
VIH
RTC Supply Current
Input High Voltage
10
uA
V
2.0
VDD33
+0.3
VIL
VT
Input Low Voltage
Threshold Point
0.8
V
V
V
1.65
VT+
Schmitt Trigger Low
to High Threshold
Point
Schmitt Trigger
High to Low
1.7
1.96
1.11
VT-
0.87
V
Threshold Point
Supply Current 1
(Core@1.2V)
ICC1
CPU@264MHz_MPLL_CLK@396MHz
for H.264 ENC/DEC running
(all Engines ON)
CPU@240MHz_MPLL_CLK@360MHz
for H.264 ENC/DEC running
(all Engines ON)
330
300
mA
ICC2
Supply Current 2
(Core@1.2V)
CPU@264MHz_MPLL_CLK@396MHz
for memory R/W test
CPU@240MHz_MPLL_CLK@360MHz
for memory R/W test
CPU@264MHz_MPLL_CLK@396MHz
for H.264 ENC/DEC running
(all Engines ON)
200
182
56
mA
mA
IMVDD
DRAM Supply
Current
CPU@240MHz_MPLL_CLK@360MHz
for memory R/W test
40
IL
Input Leakage
Current
Tri-State Output
Leakage Current
Pull-Up Resistor
-10
-10
10
10
uA
uA
IOZ
RPU
RPD
VOL
VOH
53
37
66
50
120
120
0.4
kohm
kohm
V
Pull-Down Resistor
Output Low Voltage
Output High Voltage
2.4
V
Oct. 16, 2019
Page 41 of 63
Rev 1.10
N9H26
IOL
Low
Level
Output
Current
High
Level
Output
Current
4mA I/O VOL = 0.4V
8mA I/O VOL = 0.4V
4.2
8.4
6.5
13
8
mA
16
mA
IOH
4mA I/O VOH = 2.4V
8mA I/O VOH = 2.4V
4.7
9.4
9.6
14.9
29.8
mA
mA
19.2
Note. Because USB HOST PHY CLK divider has limitation when CPU@264MHZ (i.e. UPLL_CLK=264MHZ) , the USB
HOST could not be used in this condition. Therefore, if USB HOST is MUST for application please change the CPU
CLK to 240MHz.
Oct. 16, 2019
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Rev 1.10
N9H26
6.3
AC Electrical Characteristics
External 12 MHz Crystal
6.3.1
t
CLCL
t
t
CLCH
CLCX
t
t
CHCL
CHCX
Note: Duty cycle is 50%.
PARAMETER
Clock High Time
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITION
tCHCX
tCLCX
tCLCH
tCHCL
20
20
-
-
-
-
-
125
125
10
nS
nS
nS
nS
Clock Low Time
Clock Rise Time
Clock Fall Time
-
10
Oct. 16, 2019
Page 43 of 63
Rev 1.10
N9H26
6.3.2
Power-on Sequence & RESET
6.3.2.1 Power up Sequence
Higher Voltage (3.3V) First
Sequence: T33 ≥ T18 ≥ T12, (The time of delay gap between < 500uS is prefer)
6.3.2.2 Power down Sequence,
The lower voltage (1.2V) should be powered down first
Sequence: T12 ≥ T18 ≥ T33
Note.
-
T12 represents 1.2V powered time for Core power
T18 represents 1.8V powered time for MVDD power
T33 represents 3.3V powered time for I/O power
-
-
Oct. 16, 2019
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Rev 1.10
N9H26
6.3.3
Sensor/Video-In Interface
FSPCLK
TSWL
TSWH
SPCLK
TSISU
TSIH
SHSYNC
SVSYNC
SFIELD
SPDATA[7:0]
Symbol
FSPCLK
TSWL
Parameter
Condition
Min.
-
Typ.
Max.
Unit
MHz
ns
SPCLK Clock Frequency
SPCLK Clock Low Time
SPCLK Clock High Time
-
-
-
-
72M
10
10
1.0
-
-
-
TSWH
ns
TSISU
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Setup Time
ns
TSIH
SHSYNC, SVSYNC, SFIELD,
SPDATA[7:0] Hold Time
1.0
-
-
ns
Oct. 16, 2019
Page 45 of 63
Rev 1.10
N9H26
6.3.4
I2C Interface
Oct. 16, 2019
Page 46 of 63
Rev 1.10
N9H26
6.3.5
I2S Interface
FABCLK
TAWL
TAWH
I2S_BCLK
TAISU
TAIH
Input Mode
I2S_DIN
Output Mode
I2S_WS
I2S_DOUT
TAODLY
TAOH
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
FABCLK
I2S_BCLK Clock
Frequency
-
-
16
MHz
TAWL
I2S_BCLK Clock Low
Time
31.25
31.25
-
-
-
-
ns
ns
TAWH
I2S_BCLK Clock High
Time
TAISU
TAIH
I2S_DIN Setup Time
I2S_DIN Hold Time
10
10
-
-
-
-
-
-
ns
ns
ns
TAODLY
I2S_DOUT Output Delay
Time
0.5
TAOH
I2S_DOUT Output Hold
Time
0.1
-
-
ns
Oct. 16, 2019
Page 47 of 63
Rev 1.10
N9H26
6.3.6
LCD/Display Interface
SYNC Type LCD
FLPCLK
TLWL
TLWH
LPCLK
LHSYNC
LVSYNC
LVDE
LVDATA[15:0]
TLODLY
TLOH
Symbol
Parameter
Condition
Min.
Typ.
Max.
120
-
Unit
MHz
ns
FLPCLK
TLWL
LPCLK Clock Frequency
LPCLK Clock Low Time
LPCLK Clock High Time
-
-
-
-
-
18.5
18.5
-
TLWH
-
ns
TLODLY
LHSYNC, LVSYNC,
LVDE and LVDATA
Output Delay Time
1.3
ns
TLOH
LHSYNC, LVSYNC,
LVDE and LVDATA
Output Hold Time
0.67
-
-
ns
Oct. 16, 2019
Page 48 of 63
Rev 1.10
N9H26
MPU Type LCD
LPCLK (CS_)
TLAS
TLAH
LVDE (RS)
TLCSS
TLCSH
TLWR
80 Mode:
LHSYNC (WR_)
TLDODLY
TLDOH
LVDATA[15:0]
TLEN
68 Mode:
LVSYNC (EN)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
TLCSS
TLCSH
TLAS
CS_ to WR_ Setup Time
CS_ to WR_ Hold Time
RS to WR_ Setup Time
RS to WR_ Hold Time
LVDATA Output Delay Time
LVDATA Output Hold Time
WR_ Pulse Width
2
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
TLAH
TLDODLY
TLDOH
TLWR
TLEN
1
1
1
80 Mode
68 Mode
EN Pulse Width
Note: Where PCLK is APB bus clock.
Oct. 16, 2019
Page 49 of 63
Rev 1.10
N9H26
6.3.7
SPI Interface
FSPCLK
TSPWL
TSPWH
SPI0_CLK
TSPISU
TSPIH
Input Mode
SPI0_DI
Output Mode
SPI0_DO
TSPODLY
TSPOH
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
FSPCLK
SPI0_CLK Clock
Frequency
-
-
-
-
25
MHz
TSPWL
SPI0_CLK Clock Low
Time
20
20
-
-
ns
ns
TSPWH
SPI0_CLK Clock High
Time
TSPISU
TSPIH
SPI0_DI Setup Time
SPI0_DI Hold Time
10
10
-
-
-
-
-
-
ns
ns
ns
TSPODLY
SPI0_DO Output Delay
Time
1
TSPOH
SPI0_DO Output Hold
Time
0.2
-
-
ns
Oct. 16, 2019
Page 50 of 63
Rev 1.10
N9H26
6.3.8
NAND Interface
NCS0_
NCS1_
NALE
NCLE
TNWL
TNWH
NWR_
TNODLY
TNOH
ND[7:0]
(write)
NRE_
TNISU
TNIH
ND[7:0]
(Read)
Symbol
TNWL
Parameter
Condition
Min.
10
10
-
Typ.
Max.
Unit
ns
Write Pulse Low Width
NWR_ High Hold Time
-
-
-
-
-
-
-
TNWH
TNODLY
TNOH
-
2.5
-
ns
ND[7:0] Output Delay Time
ND[7:0] Output Hold Time
ND[7:0] Data in Setup Time
ND[7:0] Data in hold time
ns
10
3.2
1
ns
TNISU
TNIH
-
ns
-
ns
Oct. 16, 2019
Page 51 of 63
Rev 1.10
N9H26
6.3.9
SD Card Interface
FSDCLK
TSDWL
TSDWH
SDCLK
TSDISU
TSDIH
Input Mode
SDCMD,
SDDAT[3:0]
Output Mode
SDCMD,
SDDAT[3:0]
TSDODLY
TSDOH
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Clock SDCLK
FSDCLK Clock Frequency in Data
-
-
-
50
MHz
KHz
Transfer Mode
FSDCLK
Clock Frequency in
Identification Mode
100
400
TSDWL
TSDWH
Clock Low Time
Clock High Time
10
10
-
-
-
-
ns
ns
Input SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDISU
TSDIH
Input Setup Time
Input Hold Time
6
2
-
-
-
-
ns
ns
Output SDCMD, SDDAT[3:0] (referenced to SDCLK)
TSDODLY
TSDOH
Output Delay Time
Output Hold Time
-
-
-
14
-
ns
ns
2.5
Oct. 16, 2019
Page 52 of 63
Rev 1.10
N9H26
6.3.10 USB PHY Specifications
6.3.10.1 USB DC Electrical Characteristics
Symbol
VIH
Parameter
Input high (driven)
Conditions
Min.
2.0
-
Typ
Max.
Unit
V
-
-
-
-
0.8
-
Input low
V
VIL
VDI
Differential input sensitivity
|PADP-PADM|
0.2
V
Differential
Includes VDI range
0.8
-
2.5
V
VCM
VSE
common-mode range
Single-ended receiver threshold
Receiver hysteresis
Output low (driven)
0.8
-
-
2.0
-
V
mV
V
400
0
-
-
-
-
-
0.3
VOL
Output high (driven)
Output signal cross voltage
Pull-up resistor
2.8
1.3
1.425
14.25
3.6
V
VOH
VCRS
RPU
2.0
V
1.575
15.75
kΩ
kΩ
Pull-down resistor
VTRM
Termination Voltage for upstream port
pull up (RPU)
3.0
-
3.6
V
ZDRV
Driver output resistance
Transceiver capacitance
Steady state drive*
Pin to VSS
28
-
-
-
49.5
20
Ω
CIN
VIH
pF
Note: Driver output resistance does not include series resistor resistance.
6.3.10.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ
Max.
Unit
Rising time
Falling time
CL = 50p
CL = 50p
4
4
-
-
20
20
ns
ns
TFR
TFF
6.3.10.3 USB High-Speed Driver Electrical Characteristics
Symbol
Parameter
Rising time
Falling time
Conditions
CL = 5p
Min.
500
500
Typ
Max.
Unit
ns
TFR
TFF
CL = 5p
ns
Oct. 16, 2019
Page 53 of 63
Rev 1.10
N9H26
6.3.11 Ethernet Interface Timing
6.3.11.1 RMII Interface Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
20.0 +/- 50
TP_RMII_REFCLK
RMII_REFCLK Period
-
-
ns
-
ppm
TH_RMII_REFCLK
TL_RMII_REFCLK
RMII_REFCLK High Time
8.0
8.0
10.0
10.0
12.0
12.0
ns
ns
-
-
RMII_REFCLK Low Time
RMII_REFCLK Rising to Valid
RMII_TXEN, RMII_TXDATA0 and
RMII_TXDATA1 Delay
TDLY_RMII_TX
TSU_RMII_RX
THD_RMII_RX
-
-
-
-
10
-
ns
ns
ns
-
-
-
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Setup Time to
RMII_REFCLK Rising
5
2
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Hold Time
from RMII_REFCLK Rising
-
TP_RMII_REFCLK
TH_RMII_REFCLK TL_RMII_REFCLK
RMIIx_REFCLK
RMIIx_TXEN
RMIIx_TXDATA0
RMIIx_TXDATA1
TDLY_RMII_TX
RMIIx_CRSDV
RMIIx_RXDATA0
RMIIx_RXDATA1
TSU_RMII_RX
THD_RMII_RX
RMII Interface Timing Diagram
Oct. 16, 2019
Page 54 of 63
Rev 1.10
N9H26
6.3.11.2 Ethernet PHY Management Interface Timing
Symbol
TP_RMII_MDC
TH_RMII_MDC
TL_RMII_MDC
Parameter
Min
400
200
200
Typ
Max
Unit
ns
Test Condition
RMII_MDC Period
RMII_MDC High Time
RMII_MDC Low Time
-
-
-
-
-
-
-
-
-
ns
ns
RMII_MDC Falling to Valid
RMII_MDIO Delay
TDLY_RMII_MDIOWR
TSU_RMII_MDIORD
THD_RMII_MDIORD
-
-
-
-
10
-
ns
ns
ns
-
-
-
RMII_MDIO Setup Time to
RMII_MDC Rising
10
10
RMII_MDIO Hold Time from
RMII_MDC Rising
-
TP_RMII_MDC
TH_RMII_MDC
TL_RMII_MDC
RMIIx_MDC
RMIIx_MDIO
(Write)
TDLY_RMII_MDIOWR
RMIIx_MDIO
(Read)
TSU_RMII_MDIORD
THD_RMII_MDIORD
Ethernet PHY Management Interface Timing Diagram
Oct. 16, 2019
Page 55 of 63
Rev 1.10
N9H26
6.3.12 Specifications of 12-bit SARADC
SPECIFICATIONS
PARAMETER
SYM
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Operating Voltage
AVDD_ADC
2.7
3.3
3.6
V
Resolution
RADC
VREF
VIN
-
12
-
-
bit
V
Reference Voltage
ADC input Voltage
2
0
AVDD
VREF
-
V
ADC Clock = 16MHz
Free Running Conversion
Sampling Rate
FSPS
-
-
1M
Hz
Integral Non-linearity Error (INL)
INL
DNL
-
±3
-
-
LSB
LSB
Differential Non-linearity Error
(DNL)
-1
+1.5
±3
Offset Error
SNR
EOFFSET
±1
62
LSB
dB
-
Note: The performance measurement is in ADC only condition (all other IPs are in reset statue).
Oct. 16, 2019
Page 56 of 63
Rev 1.10
N9H26
6.3.13 Specifications of 24-bit Delta-Sigma CODEC
Specifications
Parameter
Sym
Test Conditions
Min.
Typ
Max.
Unit
Reference
VMID
-
0.5*AVDD_CODEC
-
V
Microphone Bias
Bias Voltage
-
-
-
0.75*AVDD_CODEC
-
V
Maximum Output Current
Capacitive Load
Line Input
-
-
3
mA
pF
50
Resolution
-
-
24
-
Bit
dB
Total Harmonic Distortion
THD
DR
-80
-70
-60dB input,
Dynamic Range
80
90
-
dB
A-Weighted
S/N
SNR
80
-
90
100
0.2
-
-
-
dB
dB
dB
Channel Separation
Channel Matching
-
0.93*
Full Scale Output Voltage
VFS
-
-
dB
AVDD_CODEC/3.3
Input Impedance
Input Capacitor
10
-
-
-
-
kΩ
10
pF
Headphone Output
RL = 0 Ohm,
Po = 10mW
Total Harmonic Distortion
THD
-
-80
-
dB
RL = 32Ohm,
Po = 10mW
Total Harmonic Distortion
S/N
THD
SNR
-
-60
93
-
-
dB
dB
90
A-Weighted
Power Supply Current (No PLL, No Loading)
AVDD_CODEC
AVDD_HP
-
-
8
4
-
-
mA
mA
Note: The performance measurement is in CODEC only condition (All other IPs are in reset statue).
Oct. 16, 2019
Page 57 of 63
Rev 1.10
N9H26
6.3.14 Specification of Low Voltage Reset
Parameter
Operation voltage
Conditions
Min.
Typ
Max.
Unit
-40℃ ~ 85℃
2
3.3
3.6
V
LVD_SEL = 0
VDD rises
2.34
2.295
2.52
2.6
2.55
2.8
2.86
2.805
3.08
V
V
V
V
LVD_SEL = 0
VDD falls
LVD Detect Levels
LVD_SEL = 1
VDD rises
LVD_SEL = 1
VDD falls
2.475
2.75
3.025
VDD rises
VDD falls
2.16
2.4
2.64
V
V
LVR Detect Levels
2.115
2.35
2.585
6.3.15 Specifications of Power-on Reset (3.3V)
Parameter
Min.
-20
Typ
25
Max.
85
Unit
℃
Temperature
Reset voltage
1.05
1.57
1.99
V
6.4
Thermal Characteristics of N9H26 Package
Oct. 16, 2019
Page 58 of 63
Rev 1.10
N9H26
7
PACKAGE DIMENSIONS
7.1
128L LQFP (14x14x1.4mm footprint)
Oct. 16, 2019
Page 59 of 63
Rev 1.10
N9H26
7.2
PCB Reflow Profile Suggestion
Profile Setting Consideration
7.2.1
Oct. 16, 2019
Page 60 of 63
Rev 1.10
N9H26
7.2.2
Profile Suggestion for N9H26 series
Oct. 16, 2019
Page 61 of 63
Rev 1.10
N9H26
8
REVISION HISTORY
Date
Revision
Description
2018, 04, 19
2018, 09, 10
1.00
1.
1.
Preliminary version.
Added notice for CPU at 264MHz limitation in
chapter 2
1.01
1.10
2.
1.
Added CPU at 240MHz DC specification in
chapter 6.2
Supported CMOS Image Sensor and EMAC
functions for N9H26 series in chapter 2
2019, 10, 16
Oct. 16, 2019
Page 62 of 63
Rev 1.10
N9H26
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Oct. 16, 2019
Page 63 of 63
Rev 1.10
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