NANO103-LB1AE [NUVOTON]
ARM® Cortex®-M 32-bit Microcontroller;
| 型号： | NANO103-LB1AE |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总87页 (文件大小：2111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nano103
ARM® Cortex® -M
32-bit Microcontroller
NuMicro® Family
Nano103 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact:Nuvoton Technology Corporation.
www.nuvoton.com
May. 02, 2018
Page 1 of 87
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Table of Contents
1
GENERAL DESCRIPTION .......................................................................7
Connectivity Support Table........................................................................... 7
FEATURES .........................................................................................8
ABBREVIATIONS................................................................................14
PARTS INFORMATION LIST AND PIN CONFIGURATION ..............................16
NuMicro® Nano103 Series Selection Code.......................................................16
NuMicro® Nano103 Products Selection Guide ...................................................17
1.1
2
3
4
4.1
4.2
4.2.1
NuMicro® Nano103 Base Line Selection Guide..........................................................17
Pin Configuration......................................................................................18
NuMicro® Nano103 Pin Diagrams..........................................................................18
Pin Description ........................................................................................21
NuMicro® Nano103 Pin Description........................................................................21
4.3
4.3.1
4.4
4.4.1
5
6
BLOCK DIAGRAM ...............................................................................29
Nano103 Block Diagram.............................................................................29
FUNCTIONAL DESCRIPTION.................................................................30
ARM® Cortex® -M0 Core..............................................................................30
System Manager......................................................................................32
5.1
6.1
6.2
6.2.1
6.2.2
Overview .......................................................................................................32
Features........................................................................................................32
Clock Controller .......................................................................................33
Overview .......................................................................................................33
Features........................................................................................................33
Flash Memory Controller (FMC)....................................................................34
Overview .......................................................................................................34
Features........................................................................................................34
General Purpose I/O Controller.....................................................................35
Overview .......................................................................................................35
Features........................................................................................................35
PDMA Controller (PDMA) ...........................................................................36
Overview .......................................................................................................36
Features........................................................................................................36
Timer Controller.......................................................................................38
Overview .......................................................................................................38
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
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6.7.2
Features........................................................................................................38
PWM Generator and Capture Timer (PWM) .....................................................39
Overview .......................................................................................................39
Features........................................................................................................39
Watchdog Timer Controller..........................................................................41
Overview .......................................................................................................41
Features........................................................................................................41
Window Watchdog Timer Controller ...............................................................42
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1 Overview .......................................................................................................42
6.10.2 Features........................................................................................................42
6.11
Real Time Clock (RTC) ..............................................................................43
6.11.1 Overview .......................................................................................................43
6.11.2 Features........................................................................................................43
6.12
UART Controller ......................................................................................44
6.12.1 Overview .......................................................................................................44
6.12.2 Features........................................................................................................44
6.13
Smart Card Host Interface (SC) ....................................................................45
6.13.1 Overview .......................................................................................................45
6.13.2 Features........................................................................................................45
6.14
I2C Serial Interface Controller (I2C) ................................................................46
6.14.1 Overview .......................................................................................................46
6.14.2 Features........................................................................................................46
6.15
SPI ......................................................................................................47
6.15.1 Overview .......................................................................................................47
6.15.2 Features........................................................................................................47
6.16
Analog to Digital Converter (ADC) .................................................................48
6.16.1 Overview .......................................................................................................48
6.16.2 Features........................................................................................................48
6.17
Analog Comparator Controller (ACMP0)..........................................................49
6.17.1 Overview .......................................................................................................49
6.17.2 Features........................................................................................................49
7
8
9
APPLICATION CIRCUIT........................................................................50
Power COMSUMPTION ........................................................................51
ELECTRICAL CHARACTERISTICS ..........................................................53
9.1
Absolute Maximum Ratings .........................................................................53
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9.2
9.3
Nano103 DC Electrical Characteristics............................................................54
AC Electrical Characteristics........................................................................72
External Input Clock ..........................................................................................72
External 4~24 MHz XTAL Oscillator .......................................................................72
External 32.768 kHz Crystal ................................................................................73
Internal 36 MHz Oscillator...................................................................................74
Internal 12 MHz Oscillator...................................................................................74
Internal 4 MHz Oscillator ....................................................................................75
Internal 10 kHz Oscillator....................................................................................76
Analog Characteristics ...............................................................................77
12-bit ADC .....................................................................................................77
Brown-out Detector...........................................................................................78
Power-on Reset...............................................................................................79
Low-Voltage Reset ...........................................................................................79
Temperature Sensor .........................................................................................79
Internal Voltage Reference..................................................................................80
Comparator ....................................................................................................80
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
10 PACKAGE DIMENSIONS ......................................................................81
10.1
10.2
10.3
64S LQFP (7x7x1.4 mm footprint 2.0 mm) .......................................................81
48L LQFP (7x7x1.4 mm footprint 2.0 mm)........................................................83
33L QFN (5x5x1.4 mm footprint 2.0 mm) .........................................................84
11 REVISION HISTORY............................................................................86
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LIST OF FIGURES
Figure 4.1-1 NuMicro® Nano103 Series Selection Code
Figure 4.3-1 NuMicro® Nano103 LQFP 64-pin Diagram
Figure 4.3-2 NuMicro® Nano103 LQFP 48-pin Diagram
Figure 4.3-3 NuMicro® Nano103 QFN32-pin Diagram
Figure 5.1-1 NuMicro® Nano103 Block Diagram
Figure 6.1-1 Functional Block Diagram
16
18
19
20
29
30
73
Figure 9‑1 Typical Crystal Application Circuit
Figure 9‑2 Typical Crystal Application Circuit
73
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LIST OF TABLES
Table 1.1-1 Connectivity Support Table........................................................................................... 7
Table 1.1-1 List of Abbreviations.................................................................................................... 15
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1 GENERAL DESCRIPTION
The Nano103 series ultra-low-power 32-bit microcontroller embeded with ARM® Cortex® -M0 core
operates at low voltage ranged from 2.2V to 3.6V and runs up to 36 MHz frequency with 64
Kbytes embedded Flash (APROM) and 16 Kbytes embedded SRAM and 4 Kbytes Flash loader
memory (LDROM) for In-System Programming (ISP).
The Nano103 series integrates RTC with independent VBAT pin, 12-bit SAR ADC, comparator and
provides high performance connectivity peripheral interfaces such as UART, SPI, I2C, GPIOs, and
ISO-7816-3 for Smart card.
The Nano103 series supports main power off with only VBAT and RTC on less than 1.0 uA and
Deep Power-down mode with RAM retention is less than 1.6 uA and fast wake-up via many
peripheral interfaces.
The Nano103 series provides low voltage, low operating power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost
32-bit microcontrollers. The Nano103 series is suitable for a wide range of battery device
applications such as:
Hand-Held Medical Device
Wearable Device & Smart Watch
Wireless Gaming Control, Thermostats, Sensors Node Device (WSND)
Wireless Auto Meter Reading (AMR)
RFID Reader
Portable Wireless Data Collector
Mobile Payment Smart Card Reader
Security Alarm System
Smart Home Appliance
Smart Water, Gas, Heat Meters
1.1 Connectivity Support Table
Product Line
Nano103
UART
SPI
I2C
ADC
ACMP
RTC/Vbat
SC
Timer
●
●
●
●
●
●
●
●
Table 1.1-1 Connectivity Support Table
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2 FEATURES
Low Supply Voltage Range: 2.2V to 3.6V
Operating Temperature: -40℃~105℃
Four power modes
Normal mode
Idle mode
Power-down mode with RTC on and RAM retention
RTC domain only
Wake-up sources
RTC, WDT, I²C, Timer, UART, SPI, BOD, GPIO
Fast wake-up from power-down mode: less than 3.5 μs when using HIRC0
Brown-out
Built-in 1.7~3.1V BOD for wide operating voltage range operation
Built-in low power 2.0/2.5V BOD
Core
ARM® Cortex® -M0 core running up to 36 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Flash EPROM Memory
64 Kbytes application program memory (APROM)
4 Kbytes in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on-chip Flash
EPROM
SRAM Memory
16 Kbytes embedded SRAM
Supports DMA mode
DMA: Supports Five channels includingfour PDMA channels and one CRC channel
PDMA
Three modes: peripheral-to-memory, memory-to-peripheral, and memory-
to-memory transfer
Source address and destination address must be word alignment in all
modes.
Memory-to-memory mode: transfer length must be word alignment.
Peripheral-to-memory and memory-to-peripheral mode: transfer length
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could be word/half-word/byte alignment.
Peripheral-to-memory and memory-to-peripheral mode: transfer data width
could be word/half-word/byte alignment
Supports source and destination address direction: increment, fixed, and
wrap around
CRC
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
Clock Control
Built-in 12/16MHz OSC (HIRC0) has 2 % deviation within all temperarure range.
Deviation could be reduced to 1% if turning on auto-trim function.
Built-in 36MHz OSC(HIRC1)
Built-in 4MHz OSC(MIRC)
Supports one PLL, up to 36 MHz, for high performance system operation
External 4~24 MHz(HXT) crystal input for precise timing operation
Low power 10 kHz OSC(LIRC) for watchdog and low power system operation
External 32.768 kHz(LXT) crystal input for RTC and low power system operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports input 5V tolerance, except
PA.0 ~ PA.7 (sharing pin with ADC),
PA.12~ PA.13 (sharing pin with comparator),
PF.0~ PF.1 and PF.6 ~ PF.7(sharing pin with HXT and LXT)
PA.8, PB.4 and PB.5
Timer
Supports 4 sets of 32-bit timers, each timer with 24-bit up-counting timer and
one 8-bit pre-scale counter
Each timer could have independent clock source selection
Supports one-shot,periodic, output toggle and continuous operation modes
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Internal trigger event to ADC and PDMA
Supports PDMA mode
Wake system up from Power-down mode
Watchdog Timer
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable when watchdog time-out
Wakes system up from Power-down mode
Window Watchdog Timer(WWDT)
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC
Supports software compensation by setting frequency compensate register
(FREQADJ)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down mode
Supports 20 bytes spare registers and a tamper pin to clear the content of these
spare registers
Supports 1 Hz clock output
Support independent VBAT power domain to provide for PF.6~PF.7 (sharing pin
with LXT) and tamper pins (LQFP64: PB.13/LQFP48: PA.9/QFN32: PB.8)
PWM/Capture
Supports one PWM module to provides 6 output channels
Supports independent mode for PWM output/Capture input channe
Supports complementary mode for 3 complementary paired PWM output
channel
Supports 16-bit resolution PWM counter, each module provides 3 PWM counters
Supports PWM triggerADC function
Supports up to 12 capture input channels with 16-bit resolution
UART
Supports up to two sets of UART
Up to 1 Mbit/s baud rate
Support 9600 baud rate at 32.768 kHz
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Up to two 16-byte FIFO UART controllers
UART ports with flow control (TX, RX, nCTS and nRTS)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control.
Programmable baud rate generator
Supports PDMA mode
Supports wake-up function (nCTS, incoming RX data, RS-485 AAD mode
address matched or received FIFO is equal to the RFITL)
SPI
I2C
Up to two sets of SPI controllers
Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation
Supports 1 bit and 2 bit transfer mode
Support Dual IO transfer mode
Configurable bit length of a transaction from 8 to 32-bit
Supports MSB first or LSB first transfer sequence
Two slave select lines supported in Master mode
Configurable byte or word suspend mode
Supports byte re-ordering function
Supports variable serial clock in Master mode
Provide separate 8-level depth transmit and receive FIFO buffer
Supports wake-up function(SPI clock toggle in Power-down mode)
Supports PDMA transfer
Supports 3-wires, no slave select signal, bi-direction interface
Up to two sets of I2C device
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
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Supports multiple address recognition (four slave addresses with mask option)
Wake system up(address match) from Power-down mode
ADC
12-bit SAR ADC
Up to 12 channels: 8 external channel(PA.0 ~ PA.6 and PC.7) and 4 internal
channels.
Four internal channels: internal reference voltage (Int_VREF), Temperature
sensor, AVDD, and AVSS.
Supports three reference voltage sources: VREF pin, internal reference voltage
(Int_VREF: 2.5V/1.8V/1.5V), and AVDD.
Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
Each channel with individual result register
Threshold voltage detection (comparator function)
Conversion started by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to two ISO-7816-3 ports
Separates receive/transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
A 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and
waiting times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART mode (full–duplex)
ACMP
Supports one comparator
Analog input voltage range: 0~AVDD
Supports Hysteresis function
96-bit unique ID
128-bit unique customer ID
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Packages:
All Green package (RoHS)
LQFP 64-pin(7x7)
LQFP 48-pin(7x7)
QFN 33-pin(5x5)
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3 ABBREVIATIONS
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
Advanced High-Performance Bus
Brown-out Detection
BOD
CAN
DAP
Controller Area Network
Debug Access Port
DES
Data Encryption Standard
EBI
External Bus Interface
EPWM
FIFO
FMC
FPU
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12/16 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NTC
Negative Temperature Coefficient
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
NVIC
PCLK
PDMA
PLL
PTC
Positive Temperature Coefficient
Thermal Resistance
PT1000
PWM
Pulse Width Modulation
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QEI
Quadrature Encoder Interface
Secure Digital Input/Output
Serial Peripheral Interface
Samples per Second
SDIO
SPI
SPS
TDES
TMR
UART
UCID
USB
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 1.1-1 List of Abbreviations
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4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® Nano103 Series Selection Code
NANO 1 0
A E
3 - X X
X
Temperature
Ultra-low Power M0
E :- 40℃ ~ +105℃
Version
A : Version
Product Line Function
1 : Base Line
SRAM Size
1 : 4KB
Package Type
Z : QFN 33 (5x5mm.0.5mm pitch)
L : LQFP 48 (7x7mm,0.5mm pitch)
S : LQFP 64 (7x7mm,0.4mm pitch)
2 : 8KB
3 : 16KB
Flash ROM
B: 16KB
C: 32KB
D: 64KB
Figure 4.1-1 NuMicro® Nano103 Series Selection Code
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4.2 NuMicro® Nano103 Products Selection Guide
4.2.1
NuMicro® Nano103 Base Line Selection Guide
Connectivity
Part No.
NANO103ZD3AE
NANO103LD3AE
NANO103SD3AE
64
64
64
16
16
16
Configurable
Configurable
Configurable
4
4
4
26
39
53
4x32-bit
4x32-bit
4x32-bit
2+2
2+2
2+2
4
4
4
2
2
2
-
-
-
2
6
6
6
8
8
1
1
1
V
V
V
V
V
V
4
4
4
2
2
2
V
V
V
QFN33
LQFP48
LQFP64
*Marked in the table (2+2) means 2 UART + 2 ISO-7816 UART
*ISO-7816 UART supports UART full duplex mode
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4.3 Pin Configuration
4.3.1
NuMicro® Nano103 Pin Diagrams
4.3.1.1 NuMicro® Nano103 LQFP 64-pin
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PA.5
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PD.15
PD.14
PD.7
PD.6
PB.3
PB.2
PB.1
PB.0
50
PA.6
51
VREF
52
AVDD
53
PC.7
54
PC.6
55
PC.15
56
PC.14
LQFP64
57
PB.15
58
PF.3
59
PF.2
60
nRESET
61
VSS
62
VDD
63
PVSS
64
PB.8
Figure 4.3-1 NuMicro® Nano103 LQFP 64-pin Diagram
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4.3.1.2 NuMicro® Nano103 LQFP 48-pin
37
24
23
22
21
20
19
18
17
16
15
14
13
PA.5
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
38
PA.6
39
VREF
40
AVDD
41
PC.7
42
PC.6
LQFP48
43
44
45
46
47
48
PB.15
PF.3
PF.2
nRESET
PVSS
PB.8
Figure 4.3-2 NuMicro® Nano103 LQFP 48-pin Diagram
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4.3.1.3 NuMicro® Nano103 QFN33-pin
25
16
15
14
13
12
11
10
9
PA.5
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
26
PA.6
27
AVDD
28
PF.3
QFN33
29
PF.2
30
nRESET
31
VBAT
32
PF.6
Figure 4.3-3 NuMicro® Nano103 QFN32-pin Diagram
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4.4 Pin Description
4.4.1
NuMicro® Nano103 Pin Description
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
PB.14
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 External interrupt0 input pin.
INT0
1
-
-
SPI2_MOSI1
SPI2_SS1
PB.13
I/O
I/O
I/O
I/O
I
MFP3 SPI2 2nd MOSI (Master Out, Slave In) pin.
MFP4 SPI2 2nd slave select pin.
MFP0 General purpose digital I/O pin.
MFP3 SPI2 2nd MISO (Master In, Slave Out) pin.
MFP7 Snooper pin.
2
3
-
-
SPI2_MISO1
SNOOPER
VBAT
P
MFP0 Power supply for tamper pin (LQFP64:
PB.13/LQFP48: PA.9/QFN32: PB.8) and
RTC.
1
31
PF.6
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 I2C1 data input/output pin.
I2C1_SDA
X32_OUT
4
5
2
3
32
MFP7 External 32.768 kHz crystal output
pin(default).
PF.7
I/O
MFP0 General purpose digital I/O pin.
MFP1 I2C1 clock pin.
I2C1_SCL
SC0_CD
X32_IN
I/O
1
I
I
MFP3 SmartCard0 card detect pin.
MFP7 External 32.768 kHz crystal input
pin(default).
PA.9
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C0 clock pin.
I2C0_SCL
TM1_CNT
SC0_DAT
SPI2_CLK
TM1_OUT
UART1_nRTS
SNOOPER
PA.11
MFP2 Timer1 event counter input.
MFP3 SmartCard0 data pin.
I/O
I/O
O
-
-
2
MFP4 SPI2 serial clock pin.
MFP5 Timer1 toggle output.
O
MFP6 UART1 Request to Send output pin.
MFP7 Snooper pin.
I
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C1 clock pin.
I2C1_SCL
TM3_CNT
SC0_RST
SPI2_MOSI0
TM3_OUT
MFP2 Timer3 event counter input.
MFP3 SmartCard0 reset pin.
MFP4 SPI2 1st MOSI (Master Out, Slave In) pin.
MFP5 Timer3 toggle output.
6
4
-
O
I/O
O
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Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
PA.10
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C1 data input/output pin.
MFP2 Timer2 event counter input.
MFP3 SmartCard0 power pin.
I2C1_SDA
TM2_CNT
SC0_PWR
SPI2_MISO0
TM2_OUT
PA.9
7
5
-
O
I/O
O
MFP4 SPI2 1st MISO (Master In, Slave Out) pin.
MFP5 Timer2 toggle output.
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C0 clock pin.
I2C0_SCL
TM1_CNT
SC0_DAT
SPI2_CLK
TM1_OUT
UART1_nRTS
SNOOPER
PA.8
MFP2 Timer1 event counter input.
MFP3 SmartCard0 data pin.
I/O
I/O
O
8
6
-
MFP4 SPI2 serial clock pin.
MFP5 Timer1 toggle output.
O
MFP6 UART1 Request to Send output pin.
MFP7 Snooper pin.
I
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 I2C0 data input/output pin.
MFP2 Timer0 event counter input.
MFP3 SmartCard0 clock pin.
I2C0_SDA
TM0_CNT
SC0_CLK
SPI2_SS0
TM0_OUT
UART1_nCTS
PB.4
9
7
3
O
I/O
O
MFP4 SPI2 1st slave select pin.
MFP5 Timer0 toggle output.
I
MFP6 UART1 Clear to Send input pin.
MFP0 General purpose digital I/O pin.
MFP1 Data receiver input pin for UART1.
MFP3 SmartCard0 card detect pin.
MFP4 SPI2 1st slave select pin.
MFP6 RTC 1Hz output.
I/O
I
UART1_RXD
SC0_CD
10
8
4
I
SPI2_SS0
RTC_HZ
I/O
O
PB.5
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 Data transmitter output pin for UART1.
MFP3 SmartCard0 reset pin.
UART1_TXD
SC0_RST
SPI2_CLK
PB.6
11
12
9
5
O
I/O
I/O
O
MFP4 SPI2 serial clock pin.
MFP0 General purpose digital I/O pin.
MFP1 UART1 Request to Send output pin.
MFP4 SPI2 1st MISO (Master In, Slave Out) pin.
-
-
UART1_RSTn
SPI2_MISO0
I/O
May. 02, 2018
Page 22 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
PB.7
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 UART1 Clear to Send input pin.
MFP4 SPI21stMOSI (Master Out, Slave In) pin.
MFP0 LDO output pin.
13
-
-
UART1_nCTS
SPI2_MOSI0
LDO_CAP
VDD
I/O
AO
P
14
15
16
10
11
12
6
7
8
MFP0 Power supply for I/O ports and LDO
source for internal PLL and digital function.
VSS
G
I/O
I
MFP0 Ground pin for digital circuit.
PB.0
MFP0 General purpose digital I/O pin.
MFP1 Data receiver input pin for UART0.
MFP3 SPI11stMOSI (Master Out, Slave In) pin.
MFP0 General purpose digital I/O pin.
MFP1 Data transmitter output pin for UART0.
MFP3 SPI11st MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP1 UART0 Request to Send output pin.
MFP3 SPI1 serial clock pin.
17
18
13
14
9
UART0_RXD
SPI1_MOSI0
PB.1
I/O
I/O
O
10
UART0_TXD
SPI1_MISO0
PB.2
I/O
I/O
O
UART0_nRTS
SPI1_CLK
CLKO
19
15
11
I/O
O
MFP4 Frequency Divider output pin.
MFP0 General purpose digital I/O pin.
MFP1 UART0 Clear to Send input pin.
MFP3 SPI1 1st slave select pin.
PB.3
I/O
I
UART0_nCTS
SPI1_SS0
SC1_CD
PD.6
20
21
16
12
I/O
I
MFP4 SmartCard1 card detect pin.
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP3 SPI1 2nd MOSI (Master Out, Slave In) pin.
MFP4 SmartCard1 reset pin.
-
-
SPI1_MOSI1
SC1_RST
PD.7
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP3 SPI1 2nd MISO (Master In, Slave Out) pin.
MFP4 SmartCard1 power pin.
22
23
-
-
-
-
SPI1_MISO1
SC1_PWR
PD.14
I/O
I/O
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 SPI0 2nd MOSI (Master Out, Slave In) pin.
MFP4 SmartCard1 data pin.
SPI0_MOSI1
SC1_DAT
PD.15
MFP0 General purpose digital I/O pin.
MFP1 SPI0 2nd MISO (Master In, Slave Out) pin.
MFP4 SmartCard1 clock pin.
24
25
-
-
SPI0_MISO1
SC1_CLK
PC.3
17
13
I/O
MFP0 General purpose digital I/O pin.
May. 02, 2018
Page 23 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
SPI0_MOSI0
SC1_RST
PWM0_BRAKE0
PC.2
I/O
O
MFP1 SPI0 1stMOSI (Master Out, Slave In) pin.
MFP4 SmartCard1 reset pin.
I
MFP5 PWM0 Brake0 input pin .
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 SPI0 1st MISO (Master In, Slave Out) pin.
MFP4 SmartCard1 power pin.
SPI0_MISO0
SC1_PWR
PWM0_BRAKE1
PC.1
26
27
18
19
14
15
I
MFP5 PWM0 Brake1 input pin.
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 SPI0 serial clock pin.
SPI0_CLK
SC1_DAT
PWM0_BRAKE0
PC.0
MFP4 SmartCard1 data pin.
MFP5 PWM0 Brake0 input pin.
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 SPI0 1st slave select pin.
SPI0_SS0
SC1_CLK
PWM0_BRAKE1
PE.5
28
29
20
21
16
MFP4 SmartCard1 clock pin.
I
MFP5 PWM0 Brake1 input pin..
I/O
I/O
O
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel5 output/capture input.
MFP6 RTC 1Hz output.
-
PWM0_CH5
RTC_HZ
PB.11
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel4 output/capture input.
MFP2 Timer3 event counter input.
MFP4 Timer3 toggle output.
PWM0_CH4
TM3_CNT
TM3_OUT
SPI0_MISO0
PB.10
30
31
32
22
23
24
-
-
-
O
I/O
I/O
I/O
I
MFP5 SPI0 1st MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP1 SPI0 1stMOSI (Master Out, Slave In) pin.
MFP2 Timer2 event counter input.
MFP4 Timer2 toggle output.
SPI0_MOSI0
TM2_CNT
TM2_OUT
SPI0_SS1
PB.9
O
I/O
I/O
I/O
I
MFP5 SPI0 2nd slave select pin.
MFP0 General purpose digital I/O pin.
MFP1 SPI1 1st slave select pin.
SPI1_SS1
TM1_CNT
TM1_OUT
INT0
MFP2 Timer1 event counter input.
MFP4 Timer1 toggle output.
O
I
MFP5 External interrupt0 input pin.
May. 02, 2018
Page 24 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
PC.11
I/O
I/O
O
MFP0 General purpose digital I/O pin.
33
34
35
36
-
-
-
-
-
-
-
-
SPI1_MOSI0
UART1_TXD
PC.10
MFP1 SPI1 1st MOSI (Master Out, Slave In) pin.
MFP5 Data transmitter output pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 SPI1 1st MISO (Master In, Slave Out) pin.
MFP5 Data receiver input pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 SPI1 serial clock pin.
I/O
I/O
I
SPI1_MISO0
UART1_RXD
PC.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SPI1_CLK
I2C1_SCL
PC.8
MFP5 I2C1 clock pin.
MFP0 General purpose digital I/O pin.
MFP1 SPI1 1st slave select pin.
SPI1_SS0
I2C1_SDA
PA.15
MFP5 I2C1 data input/output pin.
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel3 output/capture input.
MFP2 I2C1 clock pin.
PWM0_CH3
I2C1_SCL
TM3_EXT
SC0_PWR
TM3_CNT
UART0_TXD
TM3_OUT
PA.14
MFP3 Timer3 external capture input.
MFP4 SmartCard0 power pin.
37
25
17
O
I
MFP5 Timer3 event counter input.
MFP6 Data transmitter output pin for UART0.
MFP7 Timer3 toggle output.
O
O
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel2 output/capture input.
MFP2 I2C1 data input/output pin.
PWM0_CH2
I2C1_SDA
TM2_EXT
TM2_CNT
UART0_RXD
TM2_OUT
PA.13
38
26
18
MFP3 Timer2 external capture input.
MFP5 Timer2 event counter input.
MFP6 Data receiver input pin for UART0.
MFP7 Timer2 toggle output.
I
I
O
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel1 output/capture input.
MFP3 Timer1 external capture input.
MFP5 I2C0 clock pin.
PWM0_CH1
TM1_EXT
I2C0_SCL
PA.12
39
40
27
28
-
-
I/O
I/O
I/O
MFP0 General purpose digital I/O pin.
MFP1 PWM0 channel0 output/capture input.
PWM0_CH0
May. 02, 2018
Page 25 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
TM0_EXT
I2C0_SDA
PF.0
I
MFP3 Timer0 external capture input.
MFP5 I2C0 data input/output pin.
I/O
I/O
I
MFP0 General purpose digital I/O pin.
MFP5 External interrupt0 input pin.
MFP7 Serial wired debugger data pin
MFP0 General purpose digital I/O pin.
MFP4 Frequency Divider output pin.
MFP5 External interrupt1 input pin.
MFP7 Serial wired debugger clock pin.
MFP0 Ground pin for analog circuit.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input0.
41
29
19
INT0
ICE_DAT
PF.1
I/O
I/O
O
CLKO
42
43
30
31
20
-
INT1
I
ICE_CLK
AVSS
I
G
PA.0
I/O
AI
AI
I
ADC_CH0
ACMP0_P
TM2_EXT
PWM0_CH2
SPI3_MOSI1
PA.1
MFP2 Comparator0 P-end input.
44
32
21
MFP3 Timer2 external capture input.
MFP5 PWM0 channel2 output/capture input.
I/O
I/O
I/O
AI
AI
I/O
I/O
AI
I
MFP6 SPI3 2ndMOSI (Master Out, Slave In) pin.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input1.
ADC_CH1
ACMP0_N
SPI3_MISO1
PA.2
45
46
47
33
34
35
-
MFP2 Comparator0 N-end input.
MFP6 SPI3 2nd MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input2.
22
23
ADC_CH2
UART1_RXD
PA.3
MFP5 Data receiver input pin for UART1.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input3.
I/O
AI
O
ADC_CH3
UART1_TXD
SPI3_MOSI0
PA.4
MFP5 Data transmitter output pin for UART1.
MFP6 SPI3 1st MOSI (Master Out, Slave In) pin.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input4.
I/O
I/O
AI
I/O
I/O
I/O
AI
ADC_CH4
I2C0_SDA
SPI3_MISO0
PA.5
48
49
36
37
24
25
MFP5 I2C0 data input/output pin.
MFP6 SPI3 1st MISO (Master In, Slave Out) pin.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input5.
ADC_CH5
May. 02, 2018
Page 26 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
I2C0_SCL
SPI3_SCLK
PA.6
I/O
I/O
I/O
AI
O
I
MFP5 I2C0 clock pin.
MFP6 SPI3 serial clock pin.
MFP0 General purpose digital I/O pin.
MFP1 ADC analog input6.
ADC_CH6
ACMP0_O
TM3_EXT
TM3_CNT
PWM0_CH3
SPI3_SS0
TM3_OUT
VREF
MFP2 Comparator0 output.
MFP3 Timer3 external capture input.
MFP4 Timer3 event counter input.
MFP5 PWM0 channel3 output/capture input.
MFP6 SPI3 1st slave select pin.
50
38
26
I
I/O
I/O
O
I
MFP7 Timer3 toggle output.
51
52
39
40
-
MFP0 Voltage reference input for ADC.
MFP0 Power supply for internal analog circuit.
MFP0 General purpose digital I/O pin.
MFP1 Data transmitter output pin for UART1.
MFP2 ADC analog input7.
27
AVDD
AP
I/O
O
AI
I
PC.7
UART1_TXD
ADC_CH7
TM1_EXT
PWM0_CH1
PC.6
53
41
-
MFP3 Timer1 external capture input.
MFP5 PWM0 channel1 output/capture input.
MFP0 General purpose digital I/O pin.
MFP1 Data receiver input pin for UART1.
MFP3 Timer0 external capture input.
MFP4 SmartCard1 card detect pin.
MFP5 PWM0 channel0 output/capture input.
MFP0 General purpose digital I/O pin.
MFP1 UART1 Request to Send output pin.
MFP3 Timer0 external capture input.
MFP0 General purpose digital I/O pin.
MFP1 UART1 Clear to Send input pin.
MFP0 General purpose digital I/O pin.
MFP1 External interrupt1 input pin.
MFP3 Snooper pin.
I/O
I/O
I
UART1_RXD
TM0_EXT
SC1_CD
PWM0_CH0
PC.15
54
42
-
I
I
I/O
I/O
O
I
55
56
-
-
-
-
UART1_nRTS
TM0_EXT
PC.14
I/O
I
UART1_nCTS
PB.15
I/O
I
INT1
57
58
43
44
-
SNOOPER
SC1_CD
PF.3
I
I
MFP4 SmartCard1 card detect pin.
MFP0 General purpose digital I/O pin.
I/O
I
28
XT1_IN
MFP7 External 4~24 MHz (high speed) crystal
input pin.
May. 02, 2018
Page 27 of 87
Rev 1.01
Nano103
Pin No.
Pin Name
Pin Type MFP*
Description
64-pin 48-pin 32-pin
PF.2
I/O
O
MFP0 General purpose digital I/O pin.
59
60
45
46
29
30
XT1_OUT
MFP7 External 4~24 MHz (high speed) crystal
output pin.
nRESET
I
MFP0 External reset input: active LOW, with an
internal pull-up. Set this pin low reset to
initial state.
61
62
63
-
-
-
-
-
VSS
VDD
G
P
MFP0 Ground pin for digital circuit.
MFP0 Power supply for I/O ports and LDO
source for internal PLL and digital function.
47
VSS
G
MFP0 Ground pin for digital circuit.
MFP0 General purpose digital I/O pin.
MFP1 ADC external trigger input.
MFP2 Timer0 event counter input.
MFP3 External interrupt0 input pin.
MFP4 Timer0 toggle output.
PB.8
I/O
STADC
TM0_CNT
INT0
I
I
64
48
-
I
TM0_OUT
SNOOPER
O
I
MFP7 Snooper pin.
Note:Pin Type: I = Digital Input, O=Digital Output; AI = Analog Input; AO = Analog Output; P = Power
Pin; AP = Analog Power.
May. 02, 2018
Page 28 of 87
Rev 1.01
Nano103
5 BLOCK DIAGRAM
5.1 Nano103 Block Diagram
Memory
RTC / PWM / Timer
RTC (VBAT
Analog Interface
12-bit ADC x 8
)
APROM
64 KB
LDROM
4 KB
32-bit Timer x 4
Watchdog Timer
ARM
Cortex-M0
36 MHz
PDMA x 5
Analog
Comparator x 1
DataFlash
SRAM
16 KB
Window
Watchdog Timer
Configurable
PWM/Capture
Timer x 6
Bridge
AHB Bus
APB Bus
Power Control
LDO
Connectivity
Clock Control
PLL
I/O Ports
UART x 4
(2 from ISO-7816-3)
General Purpose
I/O x 53
1.8V/1.6V/1.2V
High Speed
Oscillator(HIRC1)
36 MHz
High Speed
Crystal Osc.(HXT)
4 ~ 24 MHz
External
Interrupt x 32
SPI x 4
I2C x 2
Power On Reset
Medium Speed
Oscillator(MIRC)
4 MHz
High Speed
Oscillator(HIRC0)
12/16 MHz
Reset Pin x 1
BOD
LVR
Low Speed
Oscillator(LIRC)
10 kHz
Low Speed
Crystal Osc.(LXT)
32.768 kHz
ISO-7816-3 x 2
Figure 5.1-1 NuMicro® Nano103 Block Diagram
May. 02, 2018
Page 29 of 87
Rev 1.01
Nano103
6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes –Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The Figure 6.1-1shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use of
pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
32 external interrupt inputs, each with four levels of priority
May. 02, 2018
Page 30 of 87
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Nano103
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Debug support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
May. 02, 2018
Page 31 of 87
Rev 1.01
Nano103
6.2 System Manager
6.2.1
Overview
The system manager provides the functions of power modes, wake-up sources, power
architecture, reset sources, scalable LDO, system memory map, product ID and multi-function pin
control.
6.2.2
Features
Power modes and wake-up sources
System power architecture
Reset sources
Scalable LDO
HIRC0, HIRC1, and MIRC Auto-trim
System memory map
System manager Control registers map
System timer (SysTick)
System control register
Nested vectored interrupt controller (NVIC)
May. 02, 2018
Page 32 of 87
Rev 1.01
Nano103
6.3 Clock Controller
6.3.1
Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[6]) and
Cortex® -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~24 MHz external high speed crystal (HXT), 12~16 MHz internal
high speed RC oscillator (HIRC0), 36 MHz internal high speed RC oscillator (HIRC1), and 4 MHz
internal medium speed RC oscillator (MIRC) to reduce the overall system power consumption.
The following figure shows the clock generator and the overview of the clock source control.
The clock controller consists of 7 sources as listed below:
32768 Hz external low speedcrystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
12~16 MHz internal high speed RC oscillator (HIRC0)
36 MHz internal high speed RC oscillator (HIRC1)
4 MHz internal medium speed RC oscillator (MIRC)
One programmable PLL FOUT (PLL source can be selected from HXT, HIRC0,HIRC1
or MIRC)
10 kHz internal low speed RC oscillator (LIRC)
6.3.2
Features
Generates clocks for system clocks and all peripheral module clocks.
Each peripheral module clock can be turned on/off.
In Power-down mode, the clock controller turns off the external high speed crystal
(HXT) and internal high speed RC oscillator (HIRC0,HIRC1 and MIRC) to reduce the
overall system power consumption.
May. 02, 2018
Page 33 of 87
Rev 1.01
Nano103
6.4 Flash Memory Controller (FMC)
6.4.1
Overview
The Nano103 series is equipped with 32/64 Kbytes on-chip embedded flash for application and
Data Flash to store some application dependent data. A User Configuration block provides for
system initiation. A 4K bytes loader ROM (LDROM) is used for In-System-Programming (ISP)
function. This chip also supports In-Application-Programming (IAP) function, user switches the
code executing without the chip reset after the embedded flash updated.
6.4.2
Features
Supports 32/64 Kbytesapplication ROM (APROM).
Supports 4 Kbytesloader ROM (LDROM).
Supports Data Flash with configurable memory size.
Supports 12 bytes User Configuration block to control system initiation.
Supports 512 bytes page erase for all embedded flash.
Supports fast flash programming verification function.
Supports CRC-32 checksum calculation function.
Supports Flash All-One verification function.
Supports In-System-Programming (ISP) /In-Application-Programming (IAP)to update
embedded flash memory.
Supports cache memory to improve flash access performance and reduce power
consumption.
May. 02, 2018
Page 34 of 87
Rev 1.01
Nano103
6.5 General Purpose I/O Controller
6.5.1
Overview
The Nano103 series hasup to 53 General Purpose I/O pins to be shared with other function pins
depending on the chip configuration. These 53 pins are arranged in 6 ports named as PA, PB,
PC, PD, PE and PF.The PA, PB, PC, PD and PE have 16 pins on port, and the PF has 8 pins on
port. Each of the 53 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each I/O pin can be configured by software individually as Input, Push-pull output,
and Open-drain output. Each I/O pin has a very weak individual pull-up resistor which is about
110 k~40 k and VDD is from 2.2 V to 3.6 V.
6.5.2
Features
Three I/O modes:
Schmitt triggerInput-only with high impendence
Push-Pull Output mode
Open-Drain Output mode
I/O pin can be configured as interrupt source with edge/level setting
Enabling the pin interrupt function will also enable the wake-up function
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6.6 PDMA Controller (PDMA)
6.6.1
Overview
The peripheral direct memory access (PDMA) controllerin the Nano103 series contains a four-channel
DMA controller and a cyclic redundancy check (CRC) generator.
The PDMA controller is used to provide high-speed data transfer. The PDMA controller can transfer
data from one address to another without CPU intervention. This has the benefit of reducing the
workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a
total of 4 channels and each channel can perform transfer between memory and peripherals or
between memory and memory.
The PDMA controller also contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU mode and DMA
transfer mode.
6.6.2
Features
Supports 4 independently configurable channels and 1 CRC channel
Supports hardware round robin priority scheme. PDMA channel 1 has the highest
priority and channel 4 has the lowest priority
PDMA
Supports transfer data width of 8, 16, or 32 bits
Supports software and SPI, UART, TIMER and ADC request
Supports source and destination address increment size can be byte, half-word,
word, no increment or wrap around
Supports periodic transfer count interrupt
Supports time-out function for each channel
Cyclic Redundancy Check (CRC)
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8:X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 +
X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC
checksum
Supports CPU mode or DMA transfer mode
Supports transfer data width of 8, 16, or 32 bits in CRC CPU mode
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
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Supports transfer data width of 8 bits in CRC DMA mode
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6.7 Timer Controller
6.7.1
Overview
The timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.7.2
Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent Clock Source for each Timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function to count input event from pin TMx_CNT (x = 0~3)
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports event capture from external pin TMx_EXT (x = 0~3) for interval
measurement
Supports event capture from external pin TMx_EXT (x = 0~3) to reset 24-bit up
counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Supports time-out interrupt or capture interrupt to trigger ADC, PDMA and PWM.
Supports Inter-Timer trigger that Timer 0 can trigger Timer 1 and Timer 2 can trigger
Timer 3
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6.8 PWM Generator and Capture Timer (PWM)
6.8.1
Overview
The Nano103 provides one PWM generator － PWM0. The PWM0 supports 6 channels for
PWM0 output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
PWM0 counter with 16-bit comparator. The PWM0 counter supports up, down and up-down
counter types and uses a comparator compared with counter to generate events. These events
are used to generate PWM0 pulse, interrupt and trigger signal for ADC to start conversion.
The PWM0 generator supports two standard PWM0 output modes: Independent mode and
Complementary mode, which have different architecture. In Complementary mode, there are two
comparators that generate various PWM0 pulse with 12-bit dead-time generator. The PWM0
output control unit supports polarity output, independent pin mask, tri-state output enable and
brake functions.
The PWM0 generator also supports input capture function. It supports latch PWM0 counter value
to a corresponding register when input channel has a rising transition, falling transition or both
transitions.
6.8.2
Features
6.8.2.1 PWM0 function features
Supports one PWM0 module to provides 6 output channels
Supports independent mode for PWM0 output/Capture input channel
Supports complementary mode for 3 complementary paired PWM0 output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM0 counter, each module provides 3 PWM0 counters
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM0 pin
Supports brake function
Brake source from pin and system safety events (Brown-out detection and CPU
lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM0 counter match zero, period value or compared value
Brake condition happened
Supports trigger ADCon the following events:
PWM0 counter match zero, period value or compared value
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6.8.2.2 Capture Function Features
Supportsup to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.9 Watchdog Timer Controller
6.9.1
Overview
The Watchdog Timer (WDT) is used to perform a system reset after system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up CPU from Power-down mode. The watchdog timer
includes an 18-bit free running up counter with programmable time-out intervals.
6.9.2
Features
18-bit free running up counter for Watchdog timer time-out interval.
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s (if
WDT_CLK = 10 kHz).
System kept in reset state for a period of (1 / WDT_CLK) * 63.
Supports selectable WDT reset delay period, including 1026 、 130 、 18 or 3
WDT_CLK reset delay period.
Supports to force WDT enabled after chip powered on or reset by setting
CWDT_EN[2:0] in Config0 register.
Supports WDT time-out wake-up function only if WDT clock source is selected as
LIRC or LXT.
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6.10 Window Watchdog Timer Controller
6.10.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition. The WWDT
down counter value will stop to update when chip is in Idle or Power-down mode.
6.10.2 Features
6-bit down counter (WWDT_CNT) and 6-bit compare value (WINCMP) to make the
WWDT time-out window period flexible
Supports 4-bit value (PERIODSEL) to programmable maximum 11-bit prescale
counter period of WWDT counter
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6.11 Real Time Clock (RTC)
6.11.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick andalarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
The RTC controller also offers 80 bytes spare registers to store user’s important information. The
spare registers content is cleared when specified event on tamper pin is detected.
6.11.2 Features
Supportsreal time counterin RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year,month, day) for RTC time and calendar check
Supportsalarm time (hour, minute, second) and calendar (year,month, day) settings in
RTC_TALM and RTC_CALM
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in
RTC_TAMSK and RTC_CAMSK
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counterin RTC_WEEKDAY register
Frequency of RTC clock source compensateby RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
Supports 20 bytes spare registers and a snoop pin detection to clear the content of these
spare registers
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6.12 UART Controller
6.12.1 Overview
The UART Controller provides up to two channels of Universal Asynchronous
Receiver/Transmitter (UART). The UART Controller performs Normal Speed UART and supports
flow control function. In addtion, the UART Controller performs a serial-to-parallel conversion on
data received from the peripheral and a parallel-to-serial conversion on data transmitted from the
CPU. Each UART Controller channel supports ten types of interrupts. The UART controller also
supports IrDA SIR, LIN Master/Slave, RS-485 and auto-baud rate measuring function.
6.12.2 Features
Full duplex asynchronous communications.
Separate receiving and transmitting 16/16 bytes entry FIFO for data payloads.
Supports hardware auto-flow control
Supports programmable receiver buffer trigger level.
Supports programmable baud rate generator for each channel individually.
Supports nCTS, incoming RX data, RS-485 AAD mode address matched or received
FIFO is equal to the RFITL to wake-up function.
Supports 9-bit receiver buffer time-out detection function.
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
All UART Controller can be served by the PDMA.
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6.13 Smart Card Host Interface (SC)
6.13.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also can be set as UART mode to communicate with other
device.
6.13.2 Features
ISO-7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Up to two ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error number limitation function
Supports hardware activation sequence process ,and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Provides card insert/removal status
Supports UART mode
Full duplex, asynchronous communications
Separates receiving / transmitting 4 bytes entry FIFO for data payloads
Supports programmable baud rate generator for each channel
Supports programmable receiver buffer trigger level
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SC_EGTR register
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
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6.14 I2C Serial Interface Controller (I2C)
6.14.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.14.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( two slave address with mask option)
Supports Power-down wake-up function
Supports two-level buffer
Supports data transmit or receive directly mode.
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6.15 SPI
6.15.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. It is used to perform a serial-to-parallel conversion on data received from a
peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device.
The SPI controller can be configured as a master or a slave device.
The SPI controller supports wake-up function. When this chip stays in Power-down mode, it can
be woken up by off-chip device.
The SPI controller supports 2-bit transfer mode to connect 2 off-chip slave devices and then
perform full-duplex 2-bit data transfer. It also supports PDMA function to access the data buffer.
6.15.2 Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 1 bit and 2 bit transfer mode
Supports Dual I/O transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Supports MSB first or LSB first transfer sequence
Two slave select lines supported in Master mode
Configurable byte or word suspend mode
Supports byte re-ordering function
Provide separate 8-level depth transmit and receive FIFO buffer
Supports wake-up function
Supports PDMA transfer
Supports 3-wires, no slave select signal, bi-direction interface
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6.16 Analog to Digital Converter (ADC)
6.16.1 Overview
The Nano103 series contains one 12-bit successive approximation analog-to-digital converter (SAR
A/D converter) with 8 external input channels and 6 internal channels. The A/D converter supports
three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started by
software, external STADC(PB.8) pin, timer event trigger and PWM trigger.
Note that the I/O pins used as ADC analog input pins must configure the Pin Function
(SYS_GPA_MFPL/SYS_GPC_MFPL) to ADC input and off digital input path disable control
(Px_DINOFF) should be turned on before ADC function is enabled.
6.16.2 Features
Analog input voltage range: 0~VREF (Max to AVDD).
Selectable 12-bit, 10-bit, 8-bit and 6-bit resolution.
Supports sampling time settings for channel 0~7 individually and channel 12~17 share the same
one sampling time setting.
Supports two power saving modes:
Power-down mode.
Standby mode.
Up to 8 external analog input channels (channel0 ~ channel7), and 6 internal channels
(channel12 - channel17) converting six voltage sources (internal band-gap voltage, internal
reference voltage, internal temperature sensor output, battery voltage, AVDD, and AVSS).
Maximum ADC clock frequency is 36 MHz and each conversion needs 19 clocks and sampling
time depending on the input resistance (Rin).
Three operating modes:
Single mode: A/D conversion is performed one time on a specified channel.
Single-cycle Scan mode: A/D conversion is performed one cycle on all specified channels
with the sequence from the lowest numbered channel to the highest numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle scan mode until
software stops A/D conversion.
An A/D conversion can be started by:
Software write 1 to SWTRG (ADC_CTL[11]) bit.
External pin STADC.
PWM trigger.
Selects one of four timer events to trigger ADC and transfer A/D results by PDMA.
Each conversion result is held in data registers for each channel with valid and overrun
indicators.
Conversion results can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Supports calibration and load calibration words capability.
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Nano103
6.17 Analog Comparator Controller (ACMP0)
6.17.1 Overview
The Nano103 series contains one comparator. The comparator output is logic 1 when positive
input is greater than negative input; otherwise, the output is 0. The comparator can be configured
to generate an interrupt when the comparator output value changes.
6.17.2 Features
Analog input voltage range: 0 ~ AVDD(voltage of AVDD pin)
Supports hysteresis function
Supports wake-up function
Selectableinput sources of negative input
Comparator ACMP supports
1 positive source
PA.0(ACMP0_P)
4 negative sources
PA.1(ACMP0_N)
Comparator Reference Voltage (CRV)
Int_VREF
AGND
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Nano103
7 APPLICATION CIRCUIT
Power
DVCC
[1]
AVDD
AVDD
1uF//10nF
SPISS
SPICLK
MISO
CS
CLK
MISO
MOSI
VDD
SPI Device
In Case
VREF = AVDD
VREF
VREF
VSS
MOSI
1uF//10nF
AVSS
AVSS
DVCC
4.7K
DVCC
VDD
VDD
VBAT
VBAT
4.7K
CLK
DIO
SCL
SDA
VDD
I2C Device
LDO
VSS
VSS
20p
X32_IN
LDO_CAP
32.768 KHz
crystal
1uF
Crystal
Crystal
20p
20p
20p
Nano103AE
X32_OUT
XT1_IN
VDD
4~24 MHz
crystal
ICE_DAT
ICE_CLK
/RESET
VSS
SWD
Interface
XT1_OUT
RS232 Transceiver
ROUT RIN
PC COM Port
RXD
TXD
DVDD
UART
TIN
TOUT
10K
nRESET
Reset
Circuit
10uF/25V
Note: For the SPI device, the Nano103 chip supply
voltage must be equal to SPI device working voltage.
For example, when the SPI Flash working voltage is 3.3
V, the Nano103 chip supply voltage must also be 3.3V.
May. 02, 2018
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8 POWER COMSUMPTION
Part No
Test Condition
VDD
3.6V
CPU clock
36 MHz
Current
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 36MHz (from PLL and its clock source is 12 MHz
Crystal Oscillator)
6.7mA
186uA/MHz
Disable all peripheral
Set LDO output = 1.8V
Idle Mode:
CPU stop
Clock = 36MHz (from PLL and its clock source is 12 MHz
Crystal Oscillator)
2.2mA
61uA/MHz
3.6V
36 MHz
Disable all peripheral
Set LDO output = 1.8V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 36MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.8V
Idle Mode:
6.7mA
186uA/MHz
3.6V
3.6V
3.6V
3.6V
3.6V
3.6V
36 MHz
36 MHz
16 MHz
16 MHz
16 MHz
16 MHz
CPU stop
1.9mA
53uA/MHz
Clock = 36MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.8V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 16MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
2.9mA
181uA/MHz
Nano103
series
CPU stop
1.2mA
75uA/MHz
Clock = 16MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.6V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 36MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
2.8mA
175uA/MHz
CPU stop
1.1mA
69uA/MHz
Clock = 36MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
2.2mA
183uA/MHz
3.6V
3.6V
12 MHz
12 MHz
900uA
75uA/MHz
CPU stop
Clock = 12MHz Crystal Oscillator
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Disable all peripheral
Set LDO output = 1.6V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
2.2mA
183uA/MHz
3.6V
3.6V
3.6V
3.6V
3.6V
3.6V
3.6V
12 MHz
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
Stop
CPU stop
900uA
75uA/MHz
Clock = 12MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 4MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.2V
Idle Mode:
CPU stop
Clock = 4MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.2V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 4MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.2V
Idle Mode:
600uA
150uA/MHz
500uA
125uA/MHz
900uA
225uA/MHz
CPU stop
Clock = 4MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.2V
RTC Mode: (RAM retention)
(Main power off and only VBAT and RTC on)
CPU stop
500uA
125uA/MHz
1uA
Clock = 32.768KHz Crystal Oscillator
Disable all peripheral except RTC circuit
RTC Mode: (RAM retention)
(Power down with LXT enable)
CPU stop
Clock = 32.768KHz Crystal Oscillator
Disable all peripheral except RTC circuit
Set LDO output = 1.2V
Power Down Mode: (RAM retention)
CPU and all clocks stop
Set LDO output = 1.2V
3.6V
3.6V
Stop
Stop
2.1uA
1.6uA
May. 02, 2018
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Nano103
9 ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
PARAMETER
VDD-VSS
MIN
-0.3
MAX
+3.6
+3.6
5.5
UNIT
V
V
V
Battery Power Supply
VBAT-VSS
VIN
-0.3
Input Voltage on 5V Tolerance Pin
VSS -0.3
Input Voltage on Any Other Pin without 5V
Tolerance Pin
VIN
VSS -0.3
VDD +0.3
V
Oscillator Frequency
1/tCLCL
TA
4
24
+105
+150
150
150
25
MHz
C
Operating Temperature
-40
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
Maximum Current Sunk by Total I/O Pins
Maximum Current Sourced by Total I/O Pins
25
100
100
Note: Output voltage for ADC/ACMP/HXT/LXT/PA.8/PB.4/PB.5 shared pins cannot be higher than VDD because these pins
are without 5V tolerance.
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Nano103
9.2 Nano103 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 36 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Operation Voltage
Power Ground
VDD
2.2
-
3.6
-
V
V
V
V
V
VDD = 2.2V up to 36 MHz
VSS
-0.3
1.62
1.44
1.08
-
AVSS
MCU operating in Run, Idle or Power-down
mode
1.8
1.6
1.2
1.98
1.76
1.32
VLDO
Set LDO_LEVEL(LDO_CTL[3:2]) = 0x1
Set LDO_LEVEL(LDO_CTL[3:2]) = 0x0
LDO Output Voltage
CLDO
AVDD
1
-
-
1
-
uF Connect to LDO_CAP pin
V
Analog Operating
Voltage
VDD
Battery Operating
Voltage
VBAT
-
-
VDD
14
-
-
V
All digital
module
VDD
HXT
HIRC0
X
PLL
V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
IDD1
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD10
IDD11
IDD12
IDD13
-
-
-
-
-
-
-
-
-
-
-
6.9
13.1
6.7
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
13.7
6.7
12.9
6.6
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
13.6
6.4
4 MHz
12.8
6.3
4 MHz
VLDO=1.8 V
4 MHz
All digital
module
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
VDD
HXT
X
HIRC1
36 MHz
36 MHz
PLL
X
IDD14
-
-
13.6
6.7
-
-
mA
mA
3.6 V
V
X
IDD15
3.6 V
X
X
May. 02, 2018
Page 54 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.8 V
36 MHz
IDD16
IDD17
-
-
12.8
6.3
-
-
mA
mA
2.2 V
2.2 V
X
X
X
X
V
X
36 MHz
All digital
module
VDD
HXT
X
HIRC0
16 MHz
16 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
IDD18
-
14.5
-
mA
3.6 V
V
X
V
X
V
X
V
X
IDD19
IDD20
IDD21
IDD22
IDD23
IDD24
IDD25
-
-
-
-
-
-
-
6.7
13.6
6.5
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
V
V
V
V
V
V
V
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
14.5
6.7
13.6
6.6
VLDO=1.8 V
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =36 MHz
while(1){}executed
from flash
IDD26
-
13.3
-
mA
3.6 V
V
X
V
X
IDD27
IDD28
IDD29
-
-
-
6.4
12.6
6.3
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
V
V
V
4 MHz
4 MHz
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD30
-
7.3
-
mA
3.6 V
18 MHz
V
X
V
X
V
X
V
X
V
X
V
X
V
X
V
IDD31
IDD32
IDD33
IDD34
IDD35
IDD36
IDD37
IDD38
IDD39
IDD40
IDD41
IDD42
IDD43
IDD44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.8
7.1
3.7
7.5
3.9
7.3
3.8
7.3
3.7
7.1
3.7
7.1
3.5
6.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
18 MHz
18 MHz
18 MHz
16 MHz
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =18 MHz
4 MHz
4 MHz
while(1){}executed
May. 02, 2018
Page 55 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
IDD45
TEST CONDITIONS
MIN. TYP. MAX. UNIT
from flash
2.2 V
-
3.5
-
mA
VLDO=1.8 V
4 MHz
X
V
X
All digital
module
VDD
HXT
X
HIRC0
16 MHz
16 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD46
-
7.9
-
mA
3.6 V
V
X
V
X
V
X
V
X
IDD47
IDD48
IDD49
IDD50
IDD51
IDD52
IDD53
-
-
-
-
-
-
-
3.7
7.7
3.7
7.7
3.7
7.5
3.6
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
V
V
V
V
V
V
V
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO1=1.8 V
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD54
-
6.9
-
mA
3.6 V
V
X
V
X
IDD55
IDD56
IDD57
-
-
-
3.4
6.8
3.4
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
V
V
V
4 MHz
4 MHz
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD58
-
6.5
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
IDD59
IDD60
IDD61
IDD62
IDD63
IDD64
IDD65
IDD66
IDD67
IDD68
IDD69
-
-
-
-
-
-
-
-
-
-
-
3.3
6.3
3.3
6.5
3.4
6.4
3.4
6.3
3.1
6.3
3.1
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
VLDO1=1.8 V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
4 MHz
4 MHz
VLDO1=1.8 V
4 MHz
All digital
module
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
VDD
HXT
X
HIRC0
PLL
X
IDD70
-
6.8
-
mA
3.6 V
16 MHz
V
X
V
IDD71
IDD72
-
-
3.1
6.7
-
-
mA
mA
3.6 V
2.2 V
X
X
16 MHz
16 MHz
X
X
VLDO=1.8 V
May. 02, 2018
Page 56 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
IDD73
IDD74
IDD75
IDD76
IDD77
-
-
-
-
-
3.1
7
-
-
-
-
-
mA
mA
mA
mA
mA
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
V
V
V
V
X
V
X
V
X
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
3.3
6.8
3.2
VLDO1=1.8 V
All digital
module
VDD
HXT
X
MIRC
PLL
V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD78
-
6.2
-
mA
3.6 V
4 MHz
V
X
V
X
IDD79
IDD80
IDD81
-
-
-
3.1
6.1
3.1
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD82
-
4.9
-
mA
3.6 V
12 MHz
V
X
V
X
V
X
V
X
IDD83
IDD84
IDD85
IDD86
IDD87
IDD88
IDD89
-
-
-
-
-
-
-
2.5
4.8
2.5
4.9
2.5
4.8
2.5
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
12 MHz
12 MHz
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
V
V
V
V
VLDO=1.8 V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC0
PLL
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD90
-
5.3
-
mA
3.6 V
12 MHz
V
X
V
X
IDD91
IDD92
IDD93
-
-
-
2.5
5.2
2.5
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
12 MHz
12 MHz
12 MHz
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
MIRC
PLL
V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD94
-
4.8
-
mA
3.6 V
4 MHz
V
X
V
X
IDD95
IDD96
IDD97
-
-
-
2.4
4.7
2.4
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
VLDO=1.8 V
All digital
module
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
VDD
HXT
MIRC
X
PLL
X
IDD98
-
-
1.1
0.7
-
-
mA
mA
3.6 V
4 MHz
V
X
IDD99
3.6 V
4 MHz
X
X
May. 02, 2018
Page 57 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.8 V
IDD100
IDD101
IDD102
IDD103
IDD104
IDD105
-
-
-
-
-
-
1.1
0.7
1.7
1
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
4 MHz
X
X
X
X
X
X
X
V
X
V
X
V
X
4 MHz
X
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
X
X
X
X
4 MHz
4 MHz
4 MHz
4 MHz
1.7
0.9
VLDO=1.8 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IDD106
-
148
-
uA
3.6 V
32.768 kHz
V
X
V
X
V
X
V
X
IDD107
IDD108
IDD109
IDD110
IDD111
IDD112
IDD113
-
-
-
-
-
-
-
130
126
120
128
126
118
116
-
-
-
-
-
-
-
uA
uA
uA
uA
uA
uA
uA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
32.768 kHz
X
X
X
X
X
X
X
X
32.768 kHz
X
VLDO=1.8 V
32.768 kHz
X
Operating Current
Normal Run Mode
HCLK =10 kHz
while(1){}executed
from flash
X
X
X
X
10 kHz
10 kHz
10 kHz
10 kHz
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC0
PLL
X
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD114
-
6.5
-
mA
3.6 V
18 MHz
X
X
V
X
V
X
V
X
V
X
V
X
V
X
V
X
V
X
X
IDD115
IDD116
IDD117
IDD118
IDD119
IDD120
IDD121
IDD122
IDD123
IDD124
IDD125
IDD126
IDD127
IDD128
IDD129
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.4
6.4
3.3
6.6
3.5
6.6
3.4
6.5
3.3
6.4
3.3
6.2
3.1
6.2
3.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
18 MHz
18 MHz
18 MHz
16 MHz
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
V
VLDO=1.6 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO=1.6 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO=1.6 V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
4 MHz
4 MHz
VLDO=1.6 V
4 MHz
May. 02, 2018
Page 58 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
All digital
module
VDD
HXT
X
HIRC0
16 MHz
16 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD130
-
7
-
mA
3.6 V
V
IDD131
IDD132
IDD133
IDD134
IDD135
IDD136
IDD137
-
-
-
-
-
-
-
3.3
7
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
V
V
V
V
V
V
V
X
V
X
V
X
V
X
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
VLDO=1.6 V
3.3
6.9
3.3
6.8
3.3
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
VLDO1=1.6 V
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =18 MHz
while(1){}executed
from flash
IDD138
-
6.2
-
mA
3.6 V
V
X
V
X
IDD139
IDD140
IDD141
-
-
-
3.1
6.1
3
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
V
V
V
4 MHz
4 MHz
VLDO=1.6 V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD142
-
5.7
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
IDD143
IDD144
IDD145
IDD146
IDD147
IDD148
IDD149
IDD150
IDD151
IDD152
IDD153
-
-
-
-
-
-
-
-
-
-
-
2.9
5.7
2.9
5.8
3
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
VLDO=1.6 V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
5.7
3
VLDO1=1.6 V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
5.6
2.8
5.6
2.8
4 MHz
4 MHz
VLDO1=1.6 V
4 MHz
All digital
module
VDD
HXT
X
HIRC0
PLL
X
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD154
-
6
-
mA
3.6 V
16 MHz
V
X
V
X
IDD155
IDD156
IDD157
-
-
-
2.8
5.9
2.8
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
16 MHz
16 MHz
16 MHz
X
X
X
VLDO=1.6 V
May. 02, 2018
Page 59 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
3.6 V
3.6 V
2.2 V
2.2 V
12 MHz
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD158
IDD159
IDD160
IDD161
-
-
-
-
6.2
3
-
-
-
-
mA
mA
mA
mA
X
X
X
X
V
V
V
V
V
X
V
X
12 MHz
12 MHz
12 MHz
6.2
3
VLDO1=1.6 V
All digital
module
VDD
HXT
X
MIRC
PLL
V
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD162
-
5.5
-
mA
3.6 V
4 MHz
V
X
V
X
IDD163
IDD164
IDD165
-
-
-
2.8
5.5
2.8
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
VLDO=1.6 V
All digital
module
VDD
HXT
HIRC0
PLL
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD166
-
4.3
-
mA
3.6 V
12 MHz
X
X
V
X
V
X
V
X
V
X
X
IDD167
IDD168
IDD169
IDD170
IDD171
IDD172
IDD173
-
-
-
-
-
-
-
2.2
4.3
2.2
4.3
2.3
4.3
2.3
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
12 MHz
12 MHz
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
V
V
V
VLDO=1.6 V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
VLDO=1.6 V
All digital
module
VDD
HXT
X
HIRC0
12 MHz
12 MHz
PLL
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD174
-
4.7
-
mA
3.6 V
V
X
V
X
IDD175
IDD176
IDD177
-
-
-
2.2
4.7
2.2
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
12 MHz
12 MHz
VLDO=1.6 V
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
V
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD178
-
4.3
-
mA
3.6 V
V
X
V
X
IDD179
IDD180
IDD181
-
-
-
2.2
4.2
2.2
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
V
V
V
4 MHz
4 MHz
VLDO=1.6 V
All digital
module
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
VDD
HXT
HIRC0
PLL
X
IDD182
-
1
-
mA
3.6 V
4 MHz
X
X
V
X
V
IDD183
IDD184
-
-
0.6
1
-
-
mA
mA
3.6 V
2.2 V
4 MHz
4 MHz
X
X
VLDO=1.6 V
X
May. 02, 2018
Page 60 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
IDD185
IDD186
TEST CONDITIONS
MIN. TYP. MAX. UNIT
2.2 V
X
-
0.6
-
mA
4 MHz
X
X
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
X
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
-
1.6
-
mA
3.6 V
V
X
V
X
IDD187
IDD188
IDD189
-
-
-
0.9
1.5
0.9
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
4 MHz
4 MHz
VLDO=1.6 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IDD190
-
147
-
uA
3.6 V
32.768 kHz
V
X
V
X
V
X
V
X
IDD191
IDD192
IDD193
IDD194
IDD195
IDD196
IDD197
-
-
-
-
-
-
-
141
124
119
139
137
117
115
-
-
-
-
-
-
-
uA
uA
uA
uA
uA
uA
uA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
32.768 kHz
X
X
X
X
X
X
X
X
32.768 kHz
X
VLDO=1.6 V
32.768 kHz
X
Operating Current
Normal Run Mode
HCLK =10 kHz
while(1){}executed
from flash
X
X
X
X
10 kHz
10 kHz
10 kHz
10 kHz
VLDO=1.6 V
All digital
module
VDD
HXT
MIRC
X
PLL
X
IDD198
-
0.9
-
mA
Operating Current
Normal Run Mode
HCLK =2 MHz
while(1){}executed from
flash
3.6 V
4 MHz
4 MHz
V
X
V
X
IDD199
IDD200
IDD4
-
-
-
0.6
0.9
0.6
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
4 MHz
4 MHz
VLDO=1.2 V
All digital
module
VDD
HXT
X
MIRC
4 MHz
4 MHz
PLL
X
IDD201
-
0.8
-
mA
Operating Current
Normal Run Mode
HCLK =2 MHz
while(1){}executed from
flash
3.6 V
V
X
V
X
IDD202
IDD203
IDD204
-
-
-
0.5
0.8
0.5
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
4 MHz
4 MHz
VLDO=1.2 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
IDD205
-
218
-
uA
Operating Current
Normal Run Mode
HCLK =32 kHz
while(1){}executed from
flash
3.6 V
32.768 kHz
32.768 kHz
V
X
V
X
IDD206
IDD207
IDD208
-
-
-
225
206
202
-
-
-
uA
uA
uA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
32.768 kHz
32.768 kHz
VLDO=1.2 V
All digital
module
Operating Current
Normal Run Mode
HCLK =10 kHz
VDD
LXT
X
MIRC
PLL
X
IDD209
-
122
-
uA
3.6 V
10 kHz
V
May. 02, 2018
Page 61 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
while(1){}executed from
flash
10 kHz
IDD210
IDD211
IDD212
-
-
-
121
112
111
-
-
-
uA
uA
uA
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
V
X
10 kHz
10 kHz
VLDO=1.2 V
All digital
module
VDD
HXT
HIRC0
X
PLL
V
IIDLE1
-
9.5
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
IIDLE11
IIDLE12
-
-
-
-
-
-
-
-
-
-
-
2.4
9.1
2.4
9.3
2.2
9
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
2.2
9.1
2
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
4 MHz
8.8
2
4 MHz
4 MHz
All digital
module
VDD
HXT
X
HIRC1
PLL
X
IIDLE13
-
9
-
mA
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
3.6 V
36 MHz
V
X
V
X
IIDLE14
IIDLE15
IIDLE16
-
-
-
1.9
8.8
1.9
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
36 MHz
36 MHz
36 MHz
X
X
X
All digital
module
VDD
HXT
X
HIRC0
PLL
V
IIDLE17
-
10.1
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
IIDLE18
IIDLE19
IIDLE20
IIDLE21
IIDLE22
IIDLE23
IIDLE24
-
-
-
-
-
-
-
2.3
9.7
2.2
10
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
V
V
V
V
V
V
V
Operating Current
Idle Mode
HCLK =36 MHz
VLDO=1.8 V
2.2
9.6
2.2
All digital
module
Operating Current
Idle Mode
HCLK =36 MHz
VDD
HXT
X
MIRC
PLL
V
IIDLE25
-
9
-
mA
3.6 V
4 MHz
V
May. 02, 2018
Page 62 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.8 V
IIDLE26
IIDLE27
IIDLE28
-
-
-
6.3
8.7
6.2
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
X
V
X
All digital
module
VDD
HXT
HIRC0
X
PLL
X
IIDLE29
-
5
-
mA
3.6 V
18 MHz
V
X
V
X
V
X
V
X
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
IIDLE30
IIDLE31
IIDLE32
IIDLE33
IIDLE34
IIDLE35
IIDLE36
IIDLE37
IIDLE38
IIDLE39
IIDLE40
IIDLE41
IIDLE42
IIDLE43
IIDLE44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
18 MHz
18 MHz
18 MHz
16 MHz
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
V
1.5
5.2
1.7
5.1
1.6
5.1
1.5
5.
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
1.5
4.8
1.3
4.8
1.2
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
4 MHz
4 MHz
4 MHz
All digital
module
VDD
HXT
X
HIRC0
PLL
V
IIDLE45
-
5.6
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
IIDLE46
IIDLE47
IIDLE48
IIDLE49
IIDLE50
IIDLE51
IIDLE52
-
-
-
-
-
-
-
1.5
5.6
1.5
5.5
3.7
5.4
3.6
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
V
V
V
V
V
V
V
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.8 V
VDD
HXT
X
MIRC
PLL
V
IIDLE53
-
-
4.7
1.2
-
-
mA
mA
3.6 V
4 MHz
V
X
IIDLE54
3.6 V
X
4 MHz
V
May. 02, 2018
Page 63 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
2.2 V
2.2 V
IIDLE55
IIDLE56
-
-
4.7
1.2
-
-
mA
mA
X
X
4 MHz
4 MHz
V
V
V
X
All digital
module
VDD
HXT
HIRC0
X
PLL
X
IIDLE57
-
4.5
-
mA
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
IIDLE58
IIDLE59
IIDLE60
IIDLE61
IIDLE62
IIDLE63
IIDLE64
IIDLE65
IIDLE66
IIDLE67
IIDLE68
-
-
-
-
-
-
-
-
-
-
-
1.3
4.4
1.3
4.6
1.4
4.5
1.4
4.3
1.2
4.3
1.2
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
4 MHz
4 MHz
4 MHz
All digital
module
VDD
HXT
X
HIRC0
PLL
X
IIDLE69
-
4.9
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
IIDLE70
IIDLE71
IIDLE72
IIDLE73
IIDLE74
IIDLE75
IIDLE76
-
-
-
-
-
-
-
1.2
4.8
1.2
5
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
V
V
V
V
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
1.4
5
1.4
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE77
-
4.3
-
mA
3.6 V
4 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.8 V
IIDLE78
IIDLE79
IIDLE80
-
-
-
1.1
4.2
1.1
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
All digital
module
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.8 V
VDD
HXT
HIRC0
X
PLL
X
IIDLE81
-
-
3.4
1
-
-
mA
mA
3.6 V
12 MHz
V
X
IIDLE82
3.6 V
12 MHz
X
X
May. 02, 2018
Page 64 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
IIDLE83
IIDLE84
IIDLE85
IIDLE86
IIDLE87
IIDLE88
-
-
-
-
-
-
3.3
1
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
12 MHz
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
X
V
V
V
V
V
X
V
X
V
X
3.4
1
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.8 V
3.3
1
All digital
module
VDD
HXT
X
HIRC0
PLL
X
IIDLE89
-
3.8
-
mA
3.6 V
12 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.8 V
IIDLE90
IIDLE91
IIDLE92
-
-
-
1
3.7
1
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
12 MHz
12 MHz
12 MHz
X
X
X
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE93
-
3.3
-
mA
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.8 V
3.6 V
4 MHz
V
X
V
X
IIDLE94
IIDLE95
IIDLE96
-
-
-
1
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
3.3
0.9
All digital
module
VDD
HXT
MIRC
X
PLL
X
IIDLE97
-
0.9
-
mA
3.6 V
4 MHz
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =4 MHz
VLDO=1.8 V
IIDLE98
IIDLE99
-
-
-
-
-
-
-
0.5
0.9
0.4
1.2
0.5
1.2
0.4
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
4 MHz
X
X
X
X
X
X
X
X
4 MHz
X
IIDLE100
IIDLE101
IIDLE102
IIDLE103
IIDLE104
4 MHz
X
X
X
X
X
4 MHz
4 MHz
4 MHz
4 MHz
Operating Current
Idle Mode
HCLK =4 MHz
VLDO=1.8 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
IIDLE105
-
132
-
uA
3.6 V
32.768 kHz
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =32.768 kHz
VLDO=1.8 V
IIDLE106
IIDLE107
IIDLE108
IIDLE109
IIDLE110
-
-
-
-
-
126
122
116
127
125
-
-
-
-
-
uA
uA
uA
uA
uA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
32.768 kHz
X
X
X
X
X
X
X
32.768 kHz
32.768 kHz
X
Operating Current
Operating Current
Idle Mode
X
X
10 kHz
10 kHz
May. 02, 2018
Page 65 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
HCLK =10 kHz
VLDO=1.8 V
2.2 V
2.2 V
IIDLE111
IIDLE112
-
-
116
114
-
-
uA
uA
X
X
10 kHz
10 kHz
X
X
V
X
All digital
module
VDD
HXT
HIRC0
X
PLL
X
IIDLE113
-
4.5
-
mA
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
3.6 V
18 MHz
V
X
V
X
V
X
V
X
V
X
V
X
V
X
V
X
IIDLE114
IIDLE115
IIDLE116
IIDLE117
IIDLE118
IIDLE119
IIDLE120
IIDLE121
IIDLE122
IIDLE123
IIDLE124
IIDLE125
IIDLE126
IIDLE127
IIDLE128
-
-
-
-
1.3
4.4
1.3
4.6
1.5
4.6
1.4
4.5
1.4
4.4
1.3
4.3
1.1
4.2
1.1
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
18 MHz
18 MHz
18 MHz
16 MHz
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
V
V
V
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
-
-
-
-
-
-
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
-
-
-
-
-
-
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
4 MHz
-
-
-
-
4 MHz
4 MHz
All digital
module
VDD
HXT
X
HIRC0
PLL
V
IIDLE129
-
5
-
mA
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
3.6 V
16 MHz
V
X
V
X
V
X
V
X
IIDLE130
IIDLE131
IIDLE132
IIDLE133
IIDLE134
IIDLE135
IIDLE136
-
-
-
-
1.4
5
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
V
V
V
V
V
V
V
1.3
4.9
3.3
4.8
3.3
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
-
-
-
-
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE137
-
4.2
-
mA
Operating Current
Idle Mode
HCLK =18 MHz
VLDO=1.6 V
3.6 V
4 MHz
V
X
V
IIDLE138
IIDLE139
-
-
1.1
4.2
-
-
mA
mA
3.6 V
2.2 V
X
X
4 MHz
4 MHz
V
V
May. 02, 2018
Page 66 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
IIDLE140
IIDLE141
TEST CONDITIONS
MIN. TYP. MAX. UNIT
2.2 V
-
1.1
-
mA
X
4 MHz
V
X
All digital
module
VDD
HXT
HIRC0
X
PLL
X
-
3.9
-
mA
3.6 V
16 MHz
V
X
V
X
V
X
V
X
V
X
V
X
Operating Current
Idle Mode
IIDLE142
IIDLE143
IIDLE144
IIDLE145
IIDLE146
IIDLE147
IIDLE148
IIDLE149
IIDLE150
IIDLE151
IIDLE152
-
-
-
-
-
-
-
-
-
-
-
1.2
3.9
1.1
4.1
1.3
4
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
HCLK =16 MHz
VLDO=1.6 V
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.6 V
1.3
3.9
1.1
3.8
1
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.6 V
4 MHz
4 MHz
4 MHz
All digital
module
VDD
HXT
X
HIRC0
PLL
X
IIDLE153
-
4.3
-
mA
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.6 V
3.6 V
16 MHz
V
X
V
X
V
X
V
X
IIDLE154
IIDLE155
IIDLE156
IIDLE157
IIDLE158
IIDLE159
IIDLE160
-
-
-
-
-
-
-
1.1
4.3
1
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
X
X
X
X
X
X
X
16 MHz
16 MHz
16 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
V
V
V
V
4.4
1.3
4.4
1.2
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.6 V
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE161
-
3.8
-
mA
3.6 V
4 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =16 MHz
VLDO=1.6 V
IIDLE162
IIDLE163
IIDLE164
-
-
-
1
3.8
1
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
IIDLE165
-
3
-
mA
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.6 V
3.6 V
12 MHz
V
X
V
IIDLE166
IIDLE167
-
-
0.9
3
-
-
mA
mA
3.6 V
2.2 V
12 MHz
12 MHz
X
X
X
X
May. 02, 2018
Page 67 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
IIDLE168
IIDLE169
IIDLE170
IIDLE171
IIDLE172
-
-
-
-
-
0.9
3
-
-
-
-
-
mA
mA
mA
mA
mA
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
V
V
V
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.6 V
0.9
3
0.9
All digital
module
VDD
HXT
X
HIRC0
PLL
X
IIDLE173
-
3.4
-
mA
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.6 V
3.6 V
12 MHz
V
X
V
X
IIDLE174
IIDLE175
IIDLE176
-
-
-
0.9
3.3
0.9
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
12 MHz
12 MHz
12 MHz
X
X
X
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE177
-
3
-
mA
3.6 V
4 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =12 MHz
VLDO=1.6 V
IIDLE178
IIDLE179
IIDLE180
-
-
-
0.9
2.9
0.9
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
All digital
module
VDD
HXT
HIRC0
X
PLL
X
IIDLE181
-
0.8
-
mA
Operating Current
Idle Mode
HCLK =4 MHz
VLDO=1.6 V
3.6 V
4 MHz
V
X
V
X
IIDLE182
IIDLE183
IIDLE184
-
-
-
0.4
0.8
0.4
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
All digital
module
VDD
HXT
X
MIRC
PLL
V
IIDLE185
-
1.1
-
mA
3.6 V
4 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =4 MHz
VLDO=1.6 V
IIDLE186
IIDLE187
IIDLE188
-
-
-
0.4
1.1
0.4
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
V
V
V
All digital
module
VDD
LXT
LIRC
X
PLL
X
IIDLE189
-
143
-
uA
3.6 V
32.768 kHz
V
X
V
X
V
X
Operating Current
Idle Mode
HCLK =32.768 kHz
VLDO=1.6 V
IIDLE190
IIDLE191
IIDLE192
IIDLE193
IIDLE194
-
-
-
-
-
138
120
115
138
136
-
-
-
-
-
uA
uA
uA
uA
uA
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
32.768 kHz
X
X
X
X
X
X
X
32.768 kHz
32.768 kHz
X
Operating Current
Idle Mode
HCLK =10 kHz
X
X
10 kHz
10 kHz
May. 02, 2018
Page 68 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.6 V
2.2 V
2.2 V
IIDLE195
IIDLE196
-
-
116
114
-
-
uA
uA
X
X
10 kHz
10 kHz
X
X
V
X
All digital
module
VDD
HXT
MIRC
X
PLL
X
IIDLE197
-
0.7
-
mA
Operating Current
Idle Mode
HCLK =2 MHz
VLDO=1.2 V
3.6 V
4 MHz
V
X
V
X
IIDLE198
IIDLE199
IIDLE200
-
-
-
0.4
0.7
0.4
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
All digital
module
VDD
HXT
X
MIRC
PLL
X
IIDLE201
-
0.7
-
mA
3.6 V
4 MHz
V
X
V
X
Operating Current
Idle Mode
HCLK =2 MHz
VLDO=1.2 V
IIDLE202
IIDLE203
IIDLE204
-
-
-
0.3
0.7
0.3
-
-
-
mA
mA
mA
3.6 V
2.2 V
2.2 V
X
X
X
4 MHz
4 MHz
4 MHz
X
X
X
All digital
module
VDD
LXT
LIRC
X
PLL
X
IIDLE205
-
215
-
uA
Operating Current
Idle Mode
HCLK =32.768 kHz
VLDO=1.2 V
3.6 V
32.768 kHz
V
X
V
X
IIDLE206
IIDLE207
IIDLE208
-
-
-
211
204
200
-
-
-
uA
uA
uA
3.6 V
2.2 V
2.2 V
32.768 kHz
32.768 kHz
32.768 kHz
X
X
X
X
X
X
All digital
module
VDD
LXT
X
LIRC
PLL
X
IIDLE209
-
122
-
uA
3.6 V
10 kHz
V
X
V
X
Operating Current
Idle Mode
HCLK =10 kHz
VLDO=1.2 V
IIDLE210
IIDLE211
IIDLE212
-
-
-
132
112
111
-
-
-
uA
uA
uA
3.6 V
2.2 V
2.2 V
X
X
X
10 kHz
10 kHz
10 kHz
X
X
X
RAM
retention
VDD HXT/HIRC/PLL LXT(kHz) RTC
IPWD1
-
1.7
-
uA
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
3.6 V
2.2 V
2.2 V
3.6 V
X
X
X
X
X
X
X
X
X
X
32.768
X
X
V
X
V
X
V
X
V
X
V
V
V
V
V
V
V
V
V
Standby Current
Power-down Mode
VLDO=1.8 V
IPWD2
IPWD3
IPWD4
IPWD5
IPWD6
IPWD7
IPWD8
IPWD9
-
-
-
-
-
-
-
-
2.3
1.6
2.2
1.6
2.2
1.5
2.1
1.6
-
-
-
-
-
-
-
-
uA
uA
uA
uA
uA
uA
uA
uA
32.768
X
Standby Current
Power-down Mode
VLDO=1.6 V
32.768
X
32.768
X
Standby Current
May. 02, 2018
Page 69 of 87
Rev 1.01
Nano103
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Power-down Mode
VLDO=1.2 V
3.6 V
2.2 V
2.2 V
IPWD10
IPWD11
IPWD12
-
-
-
2.1
1.4
2.0
-
-
-
uA
uA
uA
X
X
X
32.768
X
V
X
V
V
V
V
32.768
Input Pull Up Resistor
PA, PB, PC, PD, PE,
PF
42
KΩ
VDD = 3.3V
VDD = 2.2V
-
-
-
-
RIN
106
-
KΩ
Input Leakage Current
PA, PB, PC, PD, PE,
PF
ILK
-1
-
1
VDD = 3.3V, 0<VIN<VDD
A
Input Low Voltage PA,
PB, PC, PD, PE, PF
VIL1
-
0.3*VDD
V
(Schmitt input)
Input High Voltage PA,
PB, PC, PD, PE, PF
ADC/ACMP/HXT/LXT shared pins and
PA.8/PB.4/PB.5 pins without Input 5V
tolerance.
VIH1 0.7*VDD
V
V
-
-
-
(Schmitt input)
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
0.4*VDD
-
-
Negative going
threshold
VILS
0.3*VDD
V
V
VDD = 3.3V
VDD = 3.3V
-
-
(Schmitt input),
/RESET
Positive going
threshold
VIHS 0.7*VDD
-
(Schmitt Input),
/RESET
VDD = 3.3V,
VS = 2.4V
ISR21
ISR22
ISK21
ISK22
-
-
-
-
-18
-2.5
12
-
-
-
-
mA
mA
mA
mA
Source Current PA,
PB, PC, PD, PE, PF
VDD = 2.2V,
VS = 1.6V
(Push-pull Mode)
VDD = 3.3V,
VS = 0.45V
Sink Current PA, PB,
PC, PD, PE, PF
VDD = 2.2V,
VS = 0.45V
(Push-pull Mode)
6
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin and the closest VSS pin
of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
May. 02, 2018
Page 70 of 87
Rev 1.01
Nano103
5. All peripherals’ clock source is from HXT (12 MHz), except SPI from HCLK.
6. The Operating Current (Normal Run Mode and Idle Mode) test condition is enable LVR and Clock filter.
May. 02, 2018
Page 71 of 87
Rev 1.01
Nano103
9.3 AC Electrical Characteristics
9.3.1 External Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
tCLCH
tCHCL
10
10
2
-
-
-
-
nS
nS
nS
nS
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
15
15
tCLCL
2
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
9.3.2 External 4~24 MHz XTAL Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Oscillator frequency
Temperature
fHXT
THXT
IHXT
4
-40
-
12
-
24
+105
-
MHz
C
VDD = 2.2V ~ 3.6V
Operating current
450
uA
VDD = 3.3V
9.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
20pF
C2
R1
4MHz ~ 24 MHz
20pF
without
May. 02, 2018
Page 72 of 87
Rev 1.01
Nano103
XT1_OUT
XT1_IN
R1
C1
C2
Figure 9‑1 Typical Crystal Application Circuit
9.3.3 External 32.768 kHz Crystal
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Oscillator frequency
Temperature
fLXT
-
32.768
-
-
kHz
VDD = 2.2V ~ 3.6V
TLXT
-40
+105 C
Operating current
VDD = 3.3V,
Testing crystal ESR = 50kΩ
ILXT
-
1.42
-
A
Note: The 32.768 kHz crystal must fit the specifications for working in any situation normally.
1. Equivalent series resistance (ESR) of crystal should be less than 50 kΩ (max. 50 kΩ).
2. The load capacitance should be 12.5 pF.
3. The specifications based on crystal “XD36RU000032C9” from vendor Aurumtec.
9.3.3.1 Typical Crystal Application Circuits
CRYSTAL
C3
C4
R2
32.768 kHz
20pF
20pF
without
X32O
X32I
R2
C3
C4
Figure 9‑2 Typical Crystal Application Circuit
May. 02, 2018
Page 73 of 87
Rev 1.01
Nano103
9.3.4 Internal 36 MHz Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Supply voltage[1]
VHRC
-
1.5
36
-
V
35.64
36.36 MHz
36.72 MHz
25C, VDD = 3.3V
-40C ~ +105C,
35.28
36
VDD = 2.2V~3.6V
Calibrated Internal
Oscillator Frequency
FHRC
-40C ~ +105 C,
VDD = 2.2V~3.6V
35.64
-
36
85
35.36 MHz
Enable 32.768K crystal
oscillator and set
TRIM_SEL[1:0]=”10”
Operating current
IHRC
-
A
9.3.5 Internal 12 MHz Oscillator
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Supply voltage[1]
VHRC
-
1.8
12
-
V
11.88
12.12 MHz
12.24 MHz
25C, VDD = 3.3V
-40C ~ +105C,
11.76
12
VDD = 2.2V~3.6V
Calibrated Internal
Oscillator Frequency
FHRC
-40C ~ +105 C,
VDD = 2.2V~3.6V
11.88
-
12
12.12 MHz
Enable 32.768K crystal
oscillator and set
TRIM_SEL[1:0]=”10”
Operating current
IHRC
210
-
A
Note: Internal oscillator operation voltage comes from LDO.
May. 02, 2018
Page 74 of 87
Rev 1.01
Nano103
9.3.6 Internal 4 MHz Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Supply voltage[1]
VHRC
-
1.5
4
-
V
3.96
4.04 MHz
4.08 MHz
25C, VDD = 3.3V
-40C ~ +105C,
3.88
4
VDD = 2.2V~3.6V
Calibrated Internal
Oscillator Frequency
FHRC
-40C ~ +105 C,
VDD = 2.2V~3.6V
3.92
-
4
4.04 MHz
Enable 32.768K crystal
oscillator and set
TRIM_SEL[1:0]=”10”
Operating current
IHRC
20
-
A
May. 02, 2018
Page 75 of 87
Rev 1.01
Nano103
9.3.7 Internal 10 kHz Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Supply voltage[1]
VLRC
-
1.8
10
-
V
7
13
kHz
25C, VDD = 3.3V
Center Frequency
FLRC
-40C ~+105 C,
5
-
10
15
-
kHz
VDD = 2.2V~3.6V
Operating current
ILRC
0.5
VDD = 3.3V
A
Note: Internal oscillator operation voltage comes from LDO.
May. 02, 2018
Page 76 of 87
Rev 1.01
Nano103
9.4 Analog Characteristics
9.4.1 12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Operating voltage
AVDD
2.2
3.6
V
AVDD = VDD
-
AVDD = VDD = 3.6V
ADC_VREF = AVDD
IADC32
125
-
-
A
Operating current (AVDD
current)
ADC Clock Rate = 36 MHz
(Enable ADC and disable all
other analog modules)
AVDD = VDD = 3.6V
ADC_VREF = AVDD
ADC Clock Rate = 6 MHz
IADC2
20
-
-
A
Resolution
RADC
VREF
12
Bit
V
-
-
Reference voltage
2.2
AVDD
-
Reference input current (Avg.) IREF
1
-
-
A
V
ADC input voltage
Conversion time
Conversion Rate
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
VIN
TCONV
FSPS
INL
0
VREF
-
1
-
-
S
1.8M
Hz VDD = 3.6V
-
-
±1
LSB VREF is external Vref pin
-
-
-
DNL
EG
±0.8
LSB VREF is external Vref pin
-
±2
LSB VREF is external Vref pin
-
-
Offset error
EOFFSET
EABS
FADC
ADCYC
CIN
±1.5
LSB VREF is external Vref pin
-
-
-
Absolute error
-
±6
36
-
LSB VREF is external Vref pin
ADC Clock frequency
Clock cycle
0.25
20
-
MHz
Cycle
pF
-
-
Internal Capacitance
Monotonic
5
-
-
Guaranteed
-
May. 02, 2018
Page 77 of 87
Rev 1.01
Nano103
9.4.2 Brown-out Detector
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
3.6
Unit
V
Test Condition
-
℃
-40
25
105
-
IBOD
Quiescent Current
Quiescent Current
-
40
μA
μA
V
AVDD = 3.6V
-
ILPBOD
-
0.5
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
AVDD = 3.6V
-
1.75
1.84
1.94
2.04
2.14
2.23
2.33
2.43
2.53
2.62
2.72
2.82
2.92
3.02
2.01
1.79
1.89
1.99
2.09
2.19
2.29
2.39
2.49
2.59
2.69
2.79
2.89
2.99
3.09
2.07
BODCTL[15:12] = 0001
BODCTL[15:12] = 0010
BODCTL[15:12] = 0011
BODCTL[15:12] = 0100
BODCTL[15:12] = 0101
BODCTL[15:12] = 0110
BODCTL[15:12] = 0111
BODCTL[15:12] = 1000
BODCTL[15:12] = 1001
BODCTL[15:12] = 1010
BODCTL[15:12] = 1011
BODCTL[15:12] = 1100
BODCTL[15:12] = 1101
BODCTL[15:12] = 1110
BODCTL[9] = 0
V
V
V
V
V
V
Brown-out Voltage
VBOD
25℃
V
V
V
V
V
V
3.1
2.0
V
Low Power Mode
Brown-out Voltage
25℃
V
VLPBOD
2.42
2.5
2.79
V
BODCTL[9] = 1
May. 02, 2018
Page 78 of 87
Rev 1.01
Nano103
9.4.3 Power-on Reset
Symbol
TA
Parameter
Min
-40
-
Typ
25
Max
105
-
Unit
℃
Test Condition
Temperature
-
-
VPOR
Threshold Voltage
1.5
V
9.4.4 Low-Voltage Reset
Symbol
TA
Parameter
Temperature
Min
-40
-
Typ
25
Max
105
-
Unit
℃
Test Condition
-
-
VPOR
Threshold Voltage
1.68
V
9.4.5 Temperature Sensor
SPECIFICATIONS
TEST CONDITION
(supply voltage = 3V)
PARAMETER
SYM.
MIN. TYP. MAX. UNIT
Detection Temperature
Operating current
Gain
TDET
ITEMP
VTG
-40
-
+105
-
oC
5
A
-1.64
735
-1.70
745
-1.76 mV/ oC
mV Temperature at 0 oC
Offset
VTO
755
Note: Internal operation voltage comes from LDO.
May. 02, 2018
Page 79 of 87
Rev 1.01
Nano103
9.4.6 Internal Voltage Reference
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Operating voltage
1.5V voltage reference
1.8V voltage reference
2.5V voltage reference
Stable Time
AVDD
VREF1
VREF2
VREF3
TREFTAB
IVREF1
IVREF2
IVREF3
2.2
-
3.6
V
V
V
V
1.43
1.5
1.8
2.5
1
1.58
AVDD ≥ 2.2V (-40C ~105C)
AVDD ≥ 2.2V (-40C ~105C)
AVDD ≥ 2.8V (-40C ~105C)
1.71
1.89
2.37
2.63
-
-
-
-
-
-
-
-
ms ILOAD=1mA, C=1uF
1.5V operating current
1.8V operating current
2.5V operating current
125
130
140
AVDD = 3.3V
AVDD = 3.3V
AVDD = 3.3V
A
A
A
9.4.7 Comparator
Symbol
VCMP
TA
Parameter
Supply Voltage
Temperature
Min
2.2
-40
-
Typ
Max
3.6
Unit Test Condition
V
-
25
40
10
-
℃
105
-
-
ICMP
Operation Current
Input Offset Voltage
Output Swing
μA AVDD = 3.3 V
VOFF
VSW
TBD
mV
V
-
-
-
-
-
0.1
0.1
40
-
AVDD - 0.1
VCOM
-
Input Common Mode Range
DC Gain
-
AVDD – 0.1
V
70
280
440
±60
1
-
dB
TPGD1
TPGD2
VHYS
TSTB
Propagation Delay(HYS=0)
Propagation Delay(HYS=1)
Hysteresis
TBD
TBD
-
ns VDIFF = 100mV,
-
us VDIFF = 100mV
-
mV
Stable time
-
TBD
μs
May. 02, 2018
Page 80 of 87
Rev 1.01
Nano103
10 PACKAGE DIMENSIONS
10.1 64S LQFP (7x7x1.4 mm footprint 2.0 mm)
May. 02, 2018
Page 81 of 87
Rev 1.01
Nano103
May. 02, 2018
Page 82 of 87
Rev 1.01
Nano103
10.2
48L LQFP (7x7x1.4 mm footprint 2.0 mm)
May. 02, 2018
Page 83 of 87
Rev 1.01
Nano103
10.3
33L QFN (5x5x1.4 mm footprint 2.0 mm)
May. 02, 2018
Page 84 of 87
Rev 1.01
Nano103
May. 02, 2018
Page 85 of 87
Rev 1.01
Nano103
11 REVISION HISTORY
Date
Revision
Description
2016.07.01
1.00
Initial version
1. Revised Temperature Selection Code in section 4.1.
2. Revised UART channel number in section 4.2.
3. Revised I/O ports number in section 5.1.
4. Revised Supply Voltage Range in chapter 1, chapter 2, section 6.5 and chapter 9.
5. Removed invalid cross-references in section 6.8.1.
2018.05.02
1.01
6. Revised external 32.768 kHz crystal characteristics in section 9.3.3.
7. Removed SPROM and KPROM discription in chapter 1, chapter 2, section 5.1 and section
6.4.
May. 02, 2018
Page 86 of 87
Rev 1.01
Nano103
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
May. 02, 2018
Page 87 of 87
Rev 1.01
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