NANO506LA2AN [NUVOTON]
ARM® Cortex®-M 32-bit Microcontroller;
| 型号： | NANO506LA2AN |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总95页 (文件大小：2021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nano100(A)
ARM® Cortex® -M
32-bit Microcontroller
NuMicro™ Family
Nano100(A) Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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Table of Contents
1
2
GENERAL DESCRIPTION ..................................................................................................... 7
FEATURES ............................................................................................................................. 9
2.1
2.2
Nano100 Features – Base Line ................................................................................... 9
Nano120 Features – USB Connectivity Line.............................................................. 14
3
PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 19
3.1
3.2
NuMicro Nano100 Series Selection Code............................................................... 19
NuMicro Nano100 Products Selection Guide.......................................................... 20
3.2.1 NuMicro Nano100 Base Line Selection Guide.............................................................20
3.2.2 NuMicro Nano120 USB Connectivity Line Selection Guide.........................................20
Pin Configuration........................................................................................................ 21
3.3
3.4
3.3.1 NuMicro Nano100 Pin Diagram...................................................................................21
3.3.2 NuMicro Nano120 Pin Diagram...................................................................................25
Pin Description ........................................................................................................... 29
3.4.1 NuMicro Nano100 Pin Description...............................................................................29
3.4.2 NuMicro Nano120 Pin Description...............................................................................40
4
5
BLOCK DIAGRAM ................................................................................................................ 51
4.1
4.2
Nano100 Block Diagram ............................................................................................ 51
Nano120 Block Diagram ............................................................................................ 52
FUNCTIONAL DESCRIPTION.............................................................................................. 53
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
ARM® Cortex™-M0 Core ........................................................................................... 53
5.1.1 Overview ........................................................................................................................53
5.1.2 Features .........................................................................................................................53
Memory Organization................................................................................................. 55
5.2.1 Overview ........................................................................................................................55
5.2.2 Memory Map ..................................................................................................................55
Nested Vectored Interrupt Controller (NVIC) ............................................................. 57
5.3.1 Overview ........................................................................................................................57
5.3.2 Features .........................................................................................................................57
System Manager ........................................................................................................ 58
5.4.1 Overview ........................................................................................................................58
5.4.2 Features .........................................................................................................................58
Clock Controller.......................................................................................................... 59
5.5.1 Overview ........................................................................................................................59
5.5.2 Features .........................................................................................................................59
FLASH Memory Controller (FMC).............................................................................. 60
5.6.1 Overview ........................................................................................................................60
5.6.2 Features .........................................................................................................................60
External Bus Interface................................................................................................ 61
5.7.1 Overview ........................................................................................................................61
5.7.2 Features .........................................................................................................................61
General Purpose I/O Controller.................................................................................. 61
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5.8.1 Overview ........................................................................................................................61
5.8.2 Features .........................................................................................................................61
DMA Controller........................................................................................................... 62
5.9
5.9.1 Overview ........................................................................................................................62
5.9.2 Features .........................................................................................................................62
5.10 Timer Controller.......................................................................................................... 63
5.10.1 Overview ......................................................................................................................63
5.10.2 Features .......................................................................................................................63
5.11 Pulse Width Modulation (PWM) ................................................................................. 63
5.11.1 Overview ......................................................................................................................63
5.11.2 Features .......................................................................................................................64
5.12 Watchdog Timer Controller ........................................................................................ 66
5.12.1 Overview ......................................................................................................................66
5.12.2 Features .......................................................................................................................66
5.13 RTC ............................................................................................................................ 67
5.13.1 Overview ......................................................................................................................67
5.13.2 Features .......................................................................................................................67
5.14 UART Controller......................................................................................................... 68
5.14.1 Overview ......................................................................................................................68
5.14.2 Features .......................................................................................................................68
5.15 Smart Card Host Interface (SC) ................................................................................. 69
5.15.1 Overview ......................................................................................................................69
5.15.2 Features .......................................................................................................................69
5.16 I2C............................................................................................................................... 69
5.16.1 Overview ......................................................................................................................69
5.16.2 Features .......................................................................................................................71
5.17 SPI.............................................................................................................................. 72
5.17.1 Overview ......................................................................................................................72
5.17.2 Features .......................................................................................................................72
5.18 I2S............................................................................................................................... 73
5.18.1 Overview ......................................................................................................................73
5.18.2 Features .......................................................................................................................73
5.19 USB ............................................................................................................................ 74
5.19.1 Overview ......................................................................................................................74
5.19.2 Features .......................................................................................................................74
5.20 Analog to Digital Converter (ADC) ............................................................................. 75
5.20.1 Overview ......................................................................................................................75
5.20.2 Features .......................................................................................................................75
APPLICATION CIRCUIT....................................................................................................... 76
ELECTRICAL CHARACTERISTIC ....................................................................................... 77
6
7
7.1
7.2
7.3
Absolute Maximum Ratings........................................................................................ 77
DC Electrical Characteristics...................................................................................... 78
AC Electrical Characteristics...................................................................................... 82
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7.3.1 External Input Clock .......................................................................................................82
7.3.2 External 4~24 MHz XTAL Oscillator...............................................................................82
7.3.3 External 32.768 kHz Crystal...........................................................................................83
7.3.4 Internal 12 MHz Oscillator ..............................................................................................83
7.3.5 Internal 10 kHz Oscillator ...............................................................................................83
Analog Characteristics ............................................................................................... 83
7.4
7.4.1 12-bit ADC......................................................................................................................83
7.4.2 Brown-out Detector.........................................................................................................84
7.4.3 Power-On Reset.............................................................................................................85
7.4.4 Temperature Sensor.......................................................................................................85
7.4.5 Internal Voltage Reference.............................................................................................85
7.4.6 USB PHY Specifications.................................................................................................85
8
9
PACKAGE DIMENSIONS..................................................................................................... 87
8.1
8.2
8.3
8.4
LQFP100 (14x14x1.4 mm footprint 2.0 mm).............................................................. 87
LQFP64 (7x7x1.4 mm footprint 2.0 mm).................................................................... 88
LQFP48 (7x7x1.4 mm footprint 2.0 mm).................................................................... 90
QFN33 (5x5x0.8 mm footprint 0.5 mm)...................................................................... 91
REVISION HISTORY............................................................................................................ 93
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List of Figures
Figure 3-1 NuMicroTM Nano100 Series Selection Code................................................................. 19
Figure 3-2 NuMicroTM Nano100 LQFP 100-pin Assignment.......................................................... 21
Figure 3-3 NuMicroTM Nano100 LQFP 64-pin Assignment............................................................ 22
Figure 3-4 NuMicroTM Nano100 LQFP 48-pin Assignment ............................................................ 23
Figure 3-5 NuMicroTM Nano100 QFN 33-pin Assignment.............................................................. 24
Figure 3-6 NuMicroTM Nano120 LQFP 100-pin Assignment .......................................................... 25
Figure 3-7 NuMicroTM Nano120 LQFP 64-pin Assignment ............................................................ 26
Figure 3-8 NuMicroTM Nano120 LQFP 48-pin Assignment ............................................................ 27
Figure 3-9 NuMicroTM Nano120 QFN 33-pin Assignment.............................................................. 28
Figure 4-1 NuMicroTM Nano100 Block Diagram ............................................................................. 51
Figure 4-2 NuMicroTM Nano120 Block Diagram ............................................................................. 52
Figure 6-1 M0 Functional Block ..................................................................................................... 53
Figure 8-1 Typical Crystal Application Circuit ................................................................................ 83
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List of Tables
Table 1-1 Connectivity Support Table.............................................................................................. 8
Table 3-1 Nano100 Base Line Selection Table ............................................................................. 20
Table 3-2 Nano120 USB Connectivity Line Selection Table ......................................................... 20
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1
GENERAL DESCRIPTION
The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM® Cortex™-M0
core operated at a wide voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with
32K/64K-byte embedded Flash and 8K/16K-byte embedded SRAM. Integrating USB 2.0 full-
speed function, RTC, 12-bit SAR ADC, and provides high performance connectivity peripheral
interfaces such as UART, SPI, I2C, I2S, GPIOs, EBI (External Bus Interface) for external
memory-mapped device access and ISO-7816-3 for Smart card, the Nano100 series supports
Brown-Out Detector, Power-down mode with RAM retention and fast wake-up via many
peripheral interfaces.
The Nano100 series provides low power voltage, low power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and lowest cost 32-
bit microcontrollers. The Nano100 series is suitable for a wide range of battery device applications
such as:
Portable Data Collector
Portable Medical Monitor
Portable RFID Reader
Portable Barcode Scanner
Security Alarm System
System Supervisors
Power Metering
USB Accessories
Smart Card Reader
Wireless Game Control Device
IPTV Remote Smart Keyboard
Wireless Sensors Node Device (WSN)
Wireless RF4CE Remote Control
Wireless Audio
Wireless Automatic Meter Reader (AMR)
Electronic Toll Collection(ETC)
The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM®
Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 32 MHz
frequency with 32K/64K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates
RTC, 8- channels 12-bit SAR ADC, and provides high performance connectivity peripheral
interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external
memory-mapped device access and 2xISO-7816-3 for Smart card. The Nano100 Base line
supports Brown-Out Detector, Power-down mode with RAM retention and fast wake-up via many
peripheral interfaces.
The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded
ARM® Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 32
MHz frequency with 32K/64K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates USB 2.0 full-speed device function, RTC, 8-channels 12-bit SAR ADC, and provides
high performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs,
EBI (External Bus Interface) for external memory-mapped device access and 2xISO-7816-3 for
Smart card. The Nano120 USB Connectivity line supports Brown-Out Detector, Power-down
mode with RAM retention and fast wake-up via many peripheral interfaces.
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Product Line
Nano100
UART
SPI
●
I2C
●
I2S
●
USB
ADC
●
RTC
●
EBI
●
SC
●
Timer
●
●
●
●
Nano120
●
●
●
●
●
●
●
●
Table 1-1 Connectivity Support Table
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2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 Nano100 Features – Base Line
Core
ARM® Cortex™-M0 core running up to 32 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 32 MHz with zero wait state for discontinuous address read access
64K/32K bytes application program memory (APROM)
4 KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on-chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports DMA mode
DMA: Supports 5 channels: one VDMA channel and 4 PDMA channels
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
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Clock Control
Flexible selection for different applications
Built-in 12 MHz OSC (Trimmed to 1%) for system operation, and low power 10
kHz OSC for watchdog and wake-up idle operation
Low power 10 kHz OSC for watchdog and low power system operation
Supports one PLL, up to 96 MHz, for high performance system operation (32
MHz) and USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports High Driver and High Sink I/O mode
Supports input 5V tolerance (except ADC shared pins PC.6 and PC.7)
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit
pre-scale counter
Independent Clock Source for each timer
Provides one-shot, output toggle and periodic operation modes
Internal trigger event to ADC module
Supports PDMA mode
Timer can wake system up from power down or idle mode
Watchdog Timer
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable when watchdog time-out
Wake system up from Power-down or Idle mode
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
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Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down or Idle mode
Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM modules, each has two 16-bit PWM generators
Provides eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM
Up to eight 16-bit digital Capture timers (shared with PWM timers), and provides
eight capture inputs (rising, falling, or both)
Supports One-shot and Continuous mode
Supports Capture interrupt
UART
Up to two 16-byte FIFO UART controllers
SPI
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control.
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down or Idle mode
Up to three sets of SPI controller
Master up to 16 MHz, and Slave up to 6 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is used as the master, and 1
slave/device select line when SPI controller is used as the slave
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire mode, no slave select signal, bi-direction interface
Wake system up from Power-down or Idle mode
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I2C
Up to two sets of I2C device
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC
Up to 8-ch single-ended input from external pin
One internal channel from AVDD, AVSS, Temp sensor, and internal reference
voltage
Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion started by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TRM0_CH0, TMR0_CH1, TMR1_CH0
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and TMR1_CH1) to enable ADC
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to two ISO-7816-3 ports
Separates receive/transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
A 24-bit and two 8 bit time out counters for Answer to Request (ATR) and
waiting times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
EBI (External bus interface) support
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8bit/16bit data width
Supports byte write in 16-bit Data Width mode
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 100-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 33-pin(5x5)
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2.2 Nano120 Features – USB Connectivity Line
Core
ARM® Cortex™-M0 core running up to 32 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 32 MHz with zero wait state for discontinuous address read access.
64K/32K bytes application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Support PDMA mode
DMA: Support 5 channels: one VDMA channel and 4 PDMA channels
VDMA
Memory-to-memory transfer
Support block transfer with stride
Support word/half-word/byte boundary address
Support address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Support word boundary address
Support word alignment transfer length in memory-to-memory mode
Support word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Support word/half-word/byte transfer data width from/to peripheral
Support address: increment, fixed, and wrap around
Clock Control
Flexible selection for different applications
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Built-in 12MHz OSC (Trimmed to 1%) for system operation, and low power 10
kHz OSC for watchdog and wake-up operation
Low power 10 kHz OSC for watchdog and low power system operation
Support one PLL, up to 96 MHz, for high performance system operation
(32MHz) and USB application (48MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin can be configured as interrupt source with edge/level setting
High driver and high sink IO mode support
Support input 5V tolerance (except ADC shared pins PC.6 and PC.7)
Timer
Support 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-scale
counter
Independent Clock Source for each timer
Provides one-shot, output toggle and periodic operation modes
Internal trigger event to ADC module
Support PDMA mode
Wake system up from Power-down or Idle mode
Watchdog Timer
Clock Source from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable on watchdog time-out
Wake system up from Power-down or Idle mode
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
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1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down or Idle mode
Support 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Support 2 PWM module, each has two 16-bit PWM generators
Provide eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler , two
clock selectors, and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight
rising/falling capture inputs
Support one shot and continuous mode
Support Capture interrupt
UART
Up to two 16-byte FIFO UART controllers
SPI
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control. (Low Density Only)
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down or Idle mode
Up to three sets of SPI controller
Master up to 16 MHz, and Slave up to 6 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire, no slave select signal, bi-direction interface
Wake system up from Power-down or Idle mode
I2C
Up to two sets of I2C device
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Master/Slave up to 1Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption
of serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend
and resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus
hangs up and timer-out counter overflows
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask
option)
I2S
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC with 800K SPS
Up to 8-ch single-end input from external pin.
One internal channel from AVDD, AVSS, Temp sensor, and internal reference
voltage.
Supports single scan, single cycle scan, and continuous scan modes
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion start by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2, TMR3) to
enable ADC
SmartCard (SC)
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Compliant to ISO-7816-3 T=0, T=1
Supports up to two ISO-7816-3 ports
Separates receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
A 24-bit and two 8 bit time out counter for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
USB 2.0 Full-Speed Device
One set of USB 2.0 FS Device 12Mbps
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provide 6 programmable endpoints
Include 512 Bytes internal SRAM as USB buffer
Provide remote wake-up capability
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 100-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 33-pin(5x5)
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3
PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro Nano100 Series Selection Code
Figure 3-1 NuMicroTM Nano100 Series Selection Code
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Revision V1.00
Nano100(A)
3.2 NuMicro Nano100 Products Selection Guide
3.2.1 NuMicro Nano100 Base Line Selection Guide
ISP
ROM
(Kbytes)
IRC
ICP
ISP
IAP
Connectivity
Flash
(Kbytes) (Kbytes)
SRAM
Timer
(32-bit)
12-bit
ADC
ISO-
7816-3
I2S
Part No.
Data Flash
I/O
PWM
RTC
EBI
10KHz PDMA
12MHz
Package
I2C
2
UART SPI
USB
NANO100ZC2AN
NANO100ZD2AN
NANO100ZD3AN
NANO100LC2AN
NANO100LD2AN
NANO100LD3AN
NANO100SD2AN
NANO100SD3AN
32K
64K
64K
32K
64K
64K
64K
64K
8K
8K
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4K
4K
4K
4K
4K
4K
4K
4K
up to 26
up to 26
up to 26
up to 37
up to 37
up to 37
up to 51
up to 51
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
-
-
-
-
-
-
-
-
-
-
2
2
2
4
4
4
8
8
5
5
5
8
8
8
8
8
V
V
V
V
V
V
V
V
-
-
V
V
V
V
V
V
V
V
4
4
4
4
4
4
4
4
-
-
V
V
V
V
V
V
V
V
QFN33
QFN33
2
16K
8K
2
-
-
-
QFN33
2
1
1
1
1
1
-
2
2
2
2
2
LQFP48
LQFP48
LQFP48
LQFP64*
LQFP64*
8K
2
-
16K
8K
2
-
2
V
V
16K
2
QFN33: 5x5mm ; LQFP48: 7x7mm ; LQFP64*: 7x7mm
Table 3-1 Nano100 Base Line Selection Table
3.2.2 NuMicro Nano120 USB Connectivity Line Selection Guide
ISP
ROM
(Kbytes)
IRC
ICP
ISP
IAP
Connectivity
Flash
(Kbytes) (Kbytes)
SRAM
Timer
(32-bit)
12-bit
ADC
ISO-
7816-3
I2S
Part No.
Data Flash
I/O
PWM
RTC
EBI
10KHz PDMA
12MHz
Package
I2C
2
UART SPI
USB
NANO120ZC2AN
NANO120ZD2AN
NANO120ZD3AN
NANO120LC2AN
NANO120LD2AN
NANO120LD3AN
NANO120SD2AN
NANO120SD3AN
32K
64K
64K
32K
64K
64K
64K
64K
8K
8K
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4K
4K
4K
4K
4K
4K
4K
4K
up to 22
up to 22
up to 22
up to 33
up to 33
up to 33
up to 47
up to 47
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
1
1
1
1
1
1
1
1
-
-
2
2
2
4
4
4
8
8
5
5
5
8
8
8
8
8
-
-
-
-
V
V
V
V
V
V
V
V
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
V
V
V
V
V
V
V
V
QFN33
QFN33
2
16K
8K
2
-
-
-
QFN33
2
1
1
1
1
1
V
V
V
V
V
-
LQFP48
LQFP48
LQFP48
LQFP64*
LQFP64*
8K
2
-
16K
8K
2
-
2
V
V
16K
2
QFN33: 5x5mm ; LQFP48: 7x7mm ; LQFP64*: 7x7mm
Table 3-2 Nano120 USB Connectivity Line Selection Table
Mar 31, 2015
Page 20 of 95
Revision V1.00
Nano100(A)
3.3 Pin Configuration
3.3.1 NuMicro Nano100 Pin Diagram
3.3.1.1 NuMicro Nano100 LQFP 100-pin
PA.5
PA.6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9
PB.10
PB.11
PE.5
PE.6
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.15
PD.14
PD.7
PD.6
PB.3
PB.2
PB.1
PB.0
PE.7
PE.8
PE.9
PE.10
PE.11
PE.12
PA.7
Vref
AVDD
PD.0
PD.1
PD.2
PD.3
PD.4
PD.5
PC.7
NANO100
LQFP 100-pin
PC.6
PC.15
PC.14
PB.15
XT1_Out
XT1_In
/RESET
VSS
VDD
PF.4
PF.5
PVSS
PB.8
Figure 3-2 NuMicroTM Nano100 LQFP 100-pin Assignment
Mar 31, 2015
Page 21 of 95
Revision V1.00
Nano100(A)
3.3.1.2 NuMicro Nano100 LQFP 64-pin
PA.5
PA.6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PD.15
PD.14
PD.7
PD.6
PB.3
PB.2
PB.1
PB.0
PA.7
AVDD
PC.7
PC.6
PC.15
PC.14
PB.15
XT1_Out
XT1_In
/RESET
VSS
NANO100
LQFP 64-pin
VDD
PVSS
PB.8
Figure 3-3 NuMicroTM Nano100 LQFP 64-pin Assignment
Mar 31, 2015
Page 22 of 95
Revision V1.00
Nano100(A)
3.3.1.3 NuMicro Nano100 LQFP 48-pin
PA.5
PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
PA.7
AVDD
PC.7
PC.6
NANO100
LQFP 48-pin
PB.15
XT1_Out
XT1_In
/RESET
PVSS
PB.8
Figure 3-4 NuMicroTM Nano100 LQFP 48-pin Assignment
Mar 31, 2015
Page 23 of 95
Revision V1.00
Nano100(A)
3.3.1.4 NuMicro Nano100 QFN 33-pin
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
PA.5
AVDD
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
PC.6
NANO100
QFN 33-pin
PB.15
XT1_OUT
XT1_IN
/RESET
X32O
33 VSS
9
Figure 3-5 NuMicroTM Nano100 QFN 33-pin Assignment
Mar 31, 2015
Page 24 of 95
Revision V1.00
Nano100(A)
3.3.2 NuMicro Nano120 Pin Diagram
3.3.2.1 NuMicro Nano120 LQFP 100-pin
PA.5
PA.6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9
PB.10
PB.11
PE.5
PA.7
Vref
AVDD
PD.0
PE.6
PC.0
PD.1
PC.1
PD.2
PC.2
PD.3
PC.3
PD.4
PC.4
PD.5
PC.5
PC.7
PD.15
PD.14
PD.7
Nano120
LQFP 100-pin
PC.6
PC.15
PC.14
PB.15
XT1_Out
XT1_In
/RESET
VSS
PD.6
PB.3
PB.2
PB.1
PB.0
USB_DP
USB_DM
VDD33
VBUS
PE.7
VDD
PF.4
PF.5
PVSS
PB.8
PE.8
Figure 3-6 NuMicroTM Nano120 LQFP 100-pin Assignment
Mar 31, 2015
Page 25 of 95
Revision V1.00
Nano100(A)
3.3.2.2 NuMicro Nano120 LQFP 64-pin
PA.5
PA.6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
D+
PA.7
AVDD
PC.7
PC.6
PC.15
PC.14
PB.15
XT1_Out
XT1_In
/RESET
VSS
NANO120
LQFP 64-pin
VDD
D-
PVSS
PB.8
VDD33
VBUS
Figure 3-7 NuMicroTM Nano120 LQFP 64-pin Assignment
Mar 31, 2015
Page 26 of 95
Revision V1.00
Nano100(A)
3.3.2.3 NuMicro Nano120 LQFP 48-pin
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
D+
PA.5
PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PA.7
AVDD
PC.7
PC.6
NANO120
LQFP 48-pin
PB.15
XT1_Out
XT1_In
/RESET
PVSS
PB.8
D-
VDD33
VBUS
Figure 3-8 NuMicroTM Nano120 LQFP 48-pin Assignment
Mar 31, 2015
Page 27 of 95
Revision V1.00
Nano100(A)
3.3.2.4 NuMicro Nano120 QFN 33-pin
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
PA.5
AVDD
PC.0
PC.1
PC.2
PC.3
D+
PC.6
NANO120
QFN 33-pin
PB.15
XT1_OUT
XT1_IN
/RESET
PVSS
D-
VDD33
VBUS
33 VSS
9
Figure 3-9 NuMicroTM Nano120 QFN 33-pin Assignment
Mar 31, 2015
Page 28 of 95
Revision V1.00
Nano100(A)
3.4 Pin Description
3.4.1 NuMicro Nano100 Pin Description
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
Digital GPIO pin
1
PE.15
PE.14
PE.13
PB.14
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
2
3
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP48
package.
4
1
SPISS21
nINT0
O
I
SPI2 2nd slave select pin
External interrupt0 input pin
Digital GPIO pin
PB.13
I/O
User program must enable pull-up resistor in LQFP48
package.
5
6
2
3
AD1
I/O
I/O
I/O
O
EBI Address/Data bus bit1
Digital GPIO pin
PB.12
AD0
1
EBI Address/Data bus bit0
Frequency Divider output pin
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
Digital GPIO pin
CLKO
X32O
7
8
4
5
2
3
32
1
O
X32I
I
PA.11
I2C1SCK
nRD
I/O
I/O
O
I2C1 clock pin
9
6
4
2
EBI read enable output pin
SmartCard0 RST pin
SC0RST
MOSI20
PA.10
I2C1SDA
nWR
O
I/O
I/O
I/O
O
SPI2 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
I2C1 data I/O pin
10
11
7
8
5
6
3
4
EBI write enable output pin
SmartCard0 Power pin
SC0PWR
MISO20
PA.9
O
I/O
I/O
SPI2 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
Mar 31, 2015
Page 29 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
I2C0SCL
SC0DAT
SPICLK2
PA.8
I/O
I/O
O
I2C0 clock pin
SmartCard0 DATA pin
SPI2 serial clock pin
Digital GPIO pin
I/O
I/O
O
I2C0SDA
SC0CLK
SPISS20
I2C0 data I/O pin
12
9
7
5
SmartCard0 clock pin
SPI2 1st slave select pin
Digital GPIO pin
O
13
14
15
16
17
PD.8
I/O
I/O
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
PD.9
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
PD.10
PD.11
PD.12
PD.13
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
18
19
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
PB.4
I/O
I
Digital GPIO pin
10
8
RX1
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
Digital GPIO pin
SC0CD
SPISS20
PB.5
I
O
I/O
O
O
20
21
11
12
9
TX1
UART1 Data transmitter output pin
SPI2 serial clock pin
SPICLK2
Digital GPIO pin
PB.6
I/O
User program must enable pull-up resistor in LQFP48
package.
RTSn1
ALE
O
O
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 2nd MISO (Master In, Slave Out) pin
MISO20
I/O
Mar 31, 2015
Page 30 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
Digital GPIO pin
PB.7
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
22
13
CTSn1
nCS
I
O
I/O
P
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
LDO output pin
MOSI20
LDO
23
24
25
14
15
16
10
11
12
6
7
8
VDD
P
Power supply for I/O ports and LDO source
Ground
VSS
P
Digital GPIO pin
26
27
28
29
30
31
PE.12
PE.11
PE.10
PE.9
I/O
I/O
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
PE.8
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Digital GPIO pin
PE.7
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
PB.0
I/O
I
Digital GPIO pin
32
33
17
18
13
14
9
RX0
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
MOSI10
PB.1
I/O
I/O
O
10
TX0
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
MISO10
PB.2
I/O
I/O
O
RTSn0
nWRL
SPICLK1
PB.3
UART0 Request to Send output pin
EBI low byte write enable output pin
SPI1 serial clock pin
34
35
19
20
15
16
11
12
O
O
I/O
Digital GPIO pin
Mar 31, 2015
Page 31 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
CTSn0
nWRH
I
UART0 Clear to Send input pin
O
O
EBI high byte write enable output pin
SPI1 1st slave select pin
Digital GPIO pin
SPISS10
36
37
38
39
21
22
23
24
PD.6
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
PD.7
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
PD.14
PD.15
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
PC.5
I/O
O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
40
41
MOSI01
PC.4
SPI0 2nd MOSI (Master Out, Slave In) pin
Digital GPIO pin
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
MISO01
PC.3
I
SPI0 2nd MISO (Master In, Slave Out) pin
Digital GPIO pin
I/O
O
MOSI00
I2SDO
SPI0 1st MOSI (Master Out, Slave In) pin
I2S data output
42
43
25
26
17
18
13
14
O
SC1RST
PC.2
O
SmartCard1 RST pin
Digital GPIO pin
I/O
I
MISO00
I2SDI
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
I
SC1PWR
PC.1
O
SmartCard1 PWR pin
Digital GPIO pin
I/O
I/O
I/O
I/O
I/O
I/O
SPICLK0
I2SBCLK
SC1DAT
PC.0
SPI0 serial clock pin
44
45
27
28
19
20
15
16
I2S bit clock pin
SmartCard1 DATA pin
Digital GPIO pin
SPISS00
SPI0 1st slave select pin
Mar 31, 2015
Page 32 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
I2SLRCLK
SC1CLK
I/O
O
I2S left right channel clock
SmartCard1 clock pin
Digital GPIO pin
46
PE.6
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
PE.5
I/O
I/O
I/O
I/O
O
Digital GPIO pin
47
48
29
30
21
22
PWM1CH1
PB.11
PWM1 Channel1 output
Digital GPIO pin
PWM1CH0
TMR3
PWM1 Channel0 output
Timer3 external counter input
SPI0 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
MISO00
PB.10
I/O
I/O
I/O
O
SPISS01
TMR2
SPI0 2nd slave select pin
Timer2 external counter input
SPI0 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
49
50
31
32
23
24
MOSI00
PB.9
I/O
I/O
I/O
O
SPISS11
TMR1
SPI1 2nd slave select pin
Timer1 external counter input
External interrupt0 input pin
Digital GPIO pin
nINT0
I
PE.4
I/O
I/O
I/O
I/O
I/O
O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
51
52
53
MOSI00
PE.3
SPI0 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
MISO00
PE.2
SPI0 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
SPICLK0
PE.1
SPI0 serial clock pin
Digital GPIO pin
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
54
PWM1CH3
SPISS00
I/O
O
PWM1 Channel3 output
SPI0 1st slave select pin
Mar 31, 2015
Page 33 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
Digital GPIO pin
PE.0
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
55
PWM1CH2
I2SMCLK
I/O
O
PWM1 Channel2 output
I2S master clock output pin
Digital GPIO pin
PC.13
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
MOSI11
O
O
I
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
Snooper pin
56
PWM1CH!
SNOOPER
nINT0
I
External interrupt 0
I2C0SCK
O
I2C0 clock pin
Digital GPIO pin
PC.12
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
MISO11
PWM1CH0
nINT0
I
O
I
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel0 output
External interrupt0 input pin
I2C0 data I/O pin
57
I2C0SDA
I/O
Digital GPIO pin
PC.11
I/O
User program must enable pull-up resistor in LQFP48
package.
58
59
33
34
MOSI10
TX1
O
O
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
Digital GPIO pin
PC.10
I/O
User program must enable pull-up resistor in LQFP48
package.
MISO10
RX1
I
I
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
Digital GPIO pin
PC.9
I/O
User program must enable pull-up resistor in LQFP48
package.
60
61
35
36
SPICLK1
I2C1SCK
I/O
I/O
SPI1 serial clock pin
I2C1 clock pin
Digital GPIO pin
PC.8
I/O
User program must enable pull-up resistor in LQFP48
package.
Mar 31, 2015
Page 34 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
SPISS10
MCLK
I/O
O
SPI1 1st slave select pin
EBI external clock output pin
I2C1 data I/O pin
I2C1SDA
PA.15
I/O
I/O
I/O
O
Digital GPIO pin
PWM0CH3
I2SMCLK
TC3
PWM0 Channel3 output
I2S master clock output pin
Timer3 capture input
62
63
64
65
37
38
39
40
25
26
27
28
17
I
TX0
O
UART0 Data transmitter output pin
Digital GPIO pin
PA.14
I/O
I/O
I/O
I
PWM0CH2
AD15
PWM0 Channel2 output
EBI Address/Data bus bit15
Timer 2 capture input
UART0 Data receiver input pin
Digital GPIO pin
18
TC2
RX0
I
PA.13
I/O
I/O
I/O
I
PWM0CH1
AD14
PWM0 Channel1 output
EBI Address/Data bus bit14
Timer1 capture input
TC1
I2C0SCK
PA.12
I/O
I/O
I/O
I/O
I
I2C0 clock pin
Digital GPIO pin
PWM0CH0
AD13
PWM0 Channel0 output
EBI Address/Data bus bit13
Timer 0 capture input
I2C0 data I/O pin
TC0
I2C0SDA
ICE_DAT
PF.0
I/O
I/O
I/O
I
Serial Wired Debugger Data pin
Digital GPIO pin
66
67
41
42
29
30
19
20
nINT0
External interrupt0 input pin
Serial Wired Debugger Clock pin
Digital GPIO pin
ICE_CK
PF.1
I
I/O
O
CLKO
Frequency Divider output pin
External interrupt1 input pin
nINT1
I
Power supply for I/O ports and LDO source for internal PLL
and digital circuit
68
69
VDD
VSS
P
P
33
Ground
Mar 31, 2015
Page 35 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
70
71
43
44
31
32
AVSS
PA.0
AP
I/O
AI
Ground Pin for analog circuit
Digital GPIO pin
21
ADC0
PA.1
ADC analog input0
I/O
AI
Digital GPIO pin
72
73
45
46
33
34
ADC1
AD12
PA.2
ADC analog input1
I/O
I/O
AI
EBI Address/Data bus bit12
Digital GPIO pin
ADC2
AD11
RX1
ADC analog input2
22
23
24
25
I/O
I
EBI Address/Data bus bit11
UART1 Data receiver input pin
Digital GPIO pin
PA.3
I/O
AI
ADC3
AD10
TX1
ADC analog input3
74
75
76
47
48
49
35
36
37
I/O
O
EBI Address/Data bus bit10
UART1 Data transmitter output pin
Digital GPIO pin
PA.4
I/O
AI
ADC4
AD9
ADC analog input4
I/O
I/O
I/O
AI
EBI Address/Data bus bit9
I2C0 data I/O pin
I2C0SDA
PA.5
Digital GPIO pin
ADC5
AD8
ADC analog input5
I/O
I/O
I/O
AI
EBI Address/Data bus bit8
I2C0 clock pin
I2C0SCK
PA.6
Digital GPIO pin
ADC6
AD7
ADC analog input6
77
50
38
I/O
I
EBI Address/Data bus bit7
Timer3 capture input
PWM0 Channel3 output
Digital GPIO pin
TC3
PWM0CH3
PA.7
O
I/O
AI
ADC7
AD6
ADC analog input7
78
51
39
I/O
I
EBI Address/Data bus bit6
Timer2 capture input
PWM0 Channel2 output
TC2
PWM0CH2
O
Mar 31, 2015
Page 36 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
79
Vref
AP
AP
Voltage reference input for ADC
80
81
52
40
26
AVDD
Power supply for internal analog circuit
Digital GPIO pin
PD.0
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
RX1
I
UART1 Data receiver input pin
SPI2 2nd slave select pin
SmartCard1 clock pin
Digital GPIO pin
SPISS20
SC1CLK
I/O
O
PD.1
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
82
TX1
O
UART1 Data transmitter output pin
SPI2 serial clock pin
SPICLK2
SC1DAT
I/O
I/O
SmartCard1 DATA pin.
Digital GPIO pin
PD.2
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
RTSn1
O
I/O
I
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
83
I2SLRCLK
MISO20
SC1PWR
O
Digital GPIO pin
PD.3
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
CTSn1
I
UART1 Clear to Send input pin
I2S bit clock pin
84
I2SBCLK
MOSI20
SC1RST
I/O
O
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
O
Digital GPIO pin
PD.4
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
85
86
I2SDI
I
I
I
I2S data input
MISO21
SC1CD
SPI2 2nd MISO (Master In, Slave Out) pin
SmartCard1 card detect
Digital GPIO pin
PD.5
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Mar 31, 2015
Page 37 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
I2SDO
MOSI21
PC.7
O
O
I2S data output
SPI2 2nd MOSI (Master Out, Slave In) pin
Digital GPIO pin
I/O
I/O
I
AD5
EBI Address/Data bus bit5
Timer1 capture input
87
53
41
TC1
PWM0CH1
PC.6
O
PWM1 Channel1 output
Digital GPIO pin
I/O
I/O
I
AD4
EBI Address/Data bus bit4
Timer 0 capture input
SmartCard1 card detect pin
PWM0 Channel0 output
Digital GPIO pin
88
54
42
27
TC0
SC1CD
PWM0CH0
I
O
PC.15
I/O
User program must enable pull-up resistor in LQFP48
package.
89
55
AD3
I/O
I
EBI Address/Data bus bit3
Timer0 capture input
PWM1 Channel1 output
Digital GPIO pin
TC0
PWM1CH2
O
PC.14
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
90
91
56
57
AD2
I/O
I/O
I/O
I
EBI Address/Data bus bit2
PWM1 Channel3 output
Digital GPIO pin
PWM1CH3
PB.15
43
28
nINT1
External interrupt1 input pin
Snooper pin
SNOOPER
I
92
93
58
59
44
45
29
30
XT1_OUT
XT1_IN
O
I
External 4~24 MHz crystal output pin
External 4~24 MHz crystal input pin
External reset input: Low active, set this pin low reset chip
to initial state. With internal pull-up.
94
95
96
60
61
62
46
31
nRESET
VSS
I
P
P
Ground
Power supply for I/O ports and LDO source for internal PLL
and digital circuit
VDD
Digital GPIO pin
97
PF.4
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Mar 31, 2015
Page 38 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
I2C0SDA
PF.5
I/O
I/O
I2C0 data I/O pin
Digital GPIO pin
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
98
I2C0SCK
PVSS
I/O
I2C0 clock pin
99
63
64
47
48
P
PLL Ground
PB.8
I/O
Digital GPIO pin
ADCTRG
TMR0
I
I
I
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
100
nINT0
Note: Pin Type: I = Digital Input; O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog
Power
Mar 31, 2015
Page 39 of 95
Revision V1.00
Nano100(A)
3.4.2 NuMicro Nano120 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
1
PE.15
PE.14
PE.13
PB.14
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
2
3
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP48
package.
4
1
nINT0
I
External interrupt0 input pin
SPI2 2nd slave select pin
Digital GPIO pin
SPISS21
O
PB.13
I/O
User program must enable pull-up resistor in LQFP48
package.
5
6
2
3
AD1
I/O
I/O
I/O
O
EBI Address/Data bus bit1
Digital GPIO pin
PB.12
AD0
1
EBI Address/Data bus bit0
Frequency Divider output pin
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
Digital GPIO pin
CLKO
X32O
7
8
4
5
2
3
O
X32I
I
PA.11
I2C1SCK
nRD
I/O
I/O
O
I2C1 clock pin
9
6
4
1
2
EBI read enable output pin
SmartCard0 RST pin
SC0RST
MOSI20
PA.10
I2C1SDA
nWR
O
I/O
I/O
I/O
O
SPI2 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
I2C1 data I/O pin
10
11
7
8
5
6
EBI write enable output pin
SmartCard0 Power pin
SPI2 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
SC0PWR
MISO20
PA.9
O
I/O
I/O
I/O
3
I2C0SCL
I2C0 clock pin
Mar 31, 2015
Page 40 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
SC0DAT
SPICLK2
PA.8
I/O
O
SmartCard0 DATA pin
SPI2 serial clock pin
Digital GPIO pin
I/O
I/O
O
I2C0SDA
SC0CLK
SPISS20
I2C0 data I/O pin
12
9
7
4
SmartCard0 clock pin
SPI2 1st slave select pin
Digital GPIO pin
O
13
14
15
16
17
18
PD.8
I/O
I/O
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
PD.9
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
PD.10
PD.11
PD.12
PD.13
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
PB.4
I/O
I
Digital GPIO pin
RX1
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
Digital GPIO pin
19
20
10
11
8
9
5
SC0CD
SPISS20
PB.5
I
O
I/O
O
O
TX1
UART1 Data transmitter output pin
SPI2 serial clock pin
SPICLK2
Digital GPIO pin
PB.6
I/O
User program must enable pull-up resistor in LQFP48
package.
21
12
RTSn1
ALE
O
O
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 2nd MISO (Master In, Slave Out) pin
MISO20
I/O
Mar 31, 2015
Page 41 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
PB.7
I/O
User program must enable pull-up resistor in LQFP48
package.
22
13
CTSn1
nCS
I
O
I/O
P
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
LDO output pin
MOSI20
LDO
23
24
25
14
15
16
10
11
12
6
7
8
VDD
P
Power supply for I/O ports and LDO source
Ground
VSS
P
Digital GPIO pin
26
27
PE.8
PE.7
I/O
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
28
29
30
31
17
18
19
20
13
14
15
16
9
VBUS
VDD33
D-
USB POWER SUPPLY: From USB Host or HUB.
USB Internal Power Regulator Output 3.3V Decoupling Pin
USB USB Differential Signal D-
10
11
12
D+
USB USB Differential Signal D+
PB.0
I/O
I
Digital GPIO pin
32
33
21
22
17
18
RX0
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
MOSI10
PB.1
I/O
I/O
O
TX0
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
MISO10
PB.2
I/O
I/O
O
RTSn0
nWRL
SPICLK1
PB.3
UART0 Request to Send output pin
EBI low byte write enable output pin
SPI1 serial clock pin
34
35
23
24
19
20
O
O
I/O
I
Digital GPIO pin
CTSn0
nWRH
SPISS10
UART0 Clear to Send input pin
EBI high byte write enable output pin
SPI1 1st slave select pin
O
O
Mar 31, 2015
Page 42 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
36
PD.6
I/O
I/O
I/O
I/O
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
37
38
39
PD.7
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
PD.14
PD.15
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
User program must enable pull-up resistor in LQFP48
package.
Digital GPIO pin
PC.5
I/O
O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
40
41
MOSI01
PC.4
SPI0 2nd MOSI (Master Out, Slave In) pin
Digital GPIO pin
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
MISO01
PC.3
I
SPI0 2nd MISO (Master In, Slave Out) pin
Digital GPIO pin
I/O
O
MOSI00
I2SDO
SPI0 1st MOSI (Master Out, Slave In) pin
I2S data output
42
43
44
45
25
26
27
28
21
22
23
24
13
14
O
SC1RST
PC.2
O
SmartCard1 RST pin
I/O
I
Digital GPIO pin
MISO00
I2SDI
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
I
SC1PWR
PC.1
O
SmartCard1 PWR pin
Digital GPIO pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SPICLK0
I2SBCLK
SC1DAT
PC.0
SPI0 serial clock pin
15
16
I2S bit clock pin
SmartCard1 DATA pin
Digital GPIO pin
SPISS00
I2SLRCLK
SC1CLK
SPI0 1st slave select pin
I2S left right channel clock
SmartCard1 clock pin
Mar 31, 2015
Page 43 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
46
PE.6
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
PE.5
I/O
I/O
I/O
O
Digital GPIO pin
47
48
29
30
PWM1CH1
PB.11
PWM1 Channel1 output
Digital GPIO pin
TMR3
Timer3 external counter input
PWM1 Channel0 output
SPI0 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
PWM1CH0
MISO00
PB.10
I/O
I/O
I/O
I/O
O
SPISS01
TMR2
SPI0 2nd slave select pin
Timer2 external counter input
SPI0 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
49
50
31
32
MOSI00
PB.9
I/O
I/O
I/O
O
SPISS11
TMR1
SPI1 2nd slave select pin
Timer1 external counter input
External interrupt0 input pin
Digital GPIO pin
nINT0
I
PE.4
I/O
I/O
I/O
I/O
I/O
O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
51
52
53
MOSI00
PE.3
SPI0 1st MOSI (Master Out, Slave In) pin
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
MISO00
PE.2
SPI0 1st MISO (Master In, Slave Out) pin
Digital GPIO pin
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
SPICLK0
PE.1
SPI0 serial clock pin
Digital GPIO pin
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
54
55
PWM1CH3
SPISS00
I/O
O
PWM1 Channel3 output
SPI0 1st slave select pin
Digital GPIO pin
PE.0
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
Mar 31, 2015
Page 44 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
PWM1CH2
I2SMCLK
I/O
O
PWM1 Channel2 output
I2S master clock output pin
Digital GPIO pin
PC.13
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
MOSI11
O
O
I
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
Snooper pin
56
PWM1CH!
SNOOPER
nINT0
I
External interrupt 0 input pin
I2C0 clock pin
I2C0SCK
O
Digital GPIO pin
PC.12
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
MISO11
PWM1CH0
nINT0
I
O
I
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel 0 output
External interrupt 0 input pin
I2C0 data I/O pin
57
I2C0SDA
I/O
Digital GPIO pin
PC.11
I/O
User program must enable pull-up resistor in LQFP48
package.
58
59
60
61
33
34
35
36
MOSI10
TX1
O
O
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
Digital GPIO pin
PC.10
I/O
User program must enable pull-up resistor in LQFP48
package.
MISO10
RX1
I
I
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
Digital GPIO pin
PC.9
I/O
User program must enable pull-up resistor in LQFP48
package.
SPICLK1
I2C1SCK
I/O
I/O
SPI1 serial clock pin
I2C1 clock pin
Digital GPIO pin
PC.8
I/O
User program must enable pull-up resistor in LQFP48
package.
SPISS10
MCLK
I/O
O
SPI1 1st slave select pin
EBI external clock output pin
Mar 31, 2015
Page 45 of 95
Revision V1.00
Nano100(A)
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
I2C1SDA
PA.15
I/O
I/O
I/O
O
I2C1 data I/O pin
Digital GPIO pin
PWM0CH3
I2SMCLK
TC3
PWM0 Channel3 output
I2S master clock output pin
Timer3 capture input
62
37
25
17
18
I
TX0
O
UART0 Data transmitter output pin
Digital GPIO pin
PA.14
I/O
I/O
I/O
I
PWM0CH2
AD15
PWM0 Channel2 output
EBI Address/Data bus bit15
Timer 2 capture input
UART0 Data receiver input pin
Digital GPIO pin
63
38
39
40
26
27
28
TC2
RX0
I
PA.13
I/O
I/O
I/O
I
PWM0CH1
AD14
PWM0 Channel1 output
EBI Address/Data bus bit14
Timer1 capture input
64
TC1
I2C0SCK
PA.12
I/O
I/O
I/O
I/O
I
I2C0 clock pin
Digital GPIO pin
PWM0CH0
AD13
PWM0 Channel0 output
EBI Address/Data bus bit13
Timer 0 capture input
I2C0 data I/O pin
65
66
TC0
I2C0SDA
ICE_DAT
PF.0
I/O
I/O
I/O
I
Serial Wired Debugger Data pin
Digital GPIO pin
41
42
29
30
19
20
nINT0
External interrupt0 input pin
Serial Wired Debugger Clock pin
Digital GPIO pin
ICE_CK
PF.1
I
I/O
O
67
68
CLKO
Frequency Divider output pin
External interrupt1 input pin
nINT1
I
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
VDD
P
69
70
71
33
21
VSS
P
Ground
43
44
31
32
AVSS
PA.0
AP
I/O
Ground Pin for analog circuit
Digital GPIO pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
ADC0
PA.1
AI
I/O
AI
ADC analog input0
Digital GPIO pin
72
45
33
ADC1
AD12
PA.2
ADC analog input1
I/O
I/O
AI
EBI Address/Data bus bit12
Digital GPIO pin
ADC2
AD11
RX1
ADC analog input2
73
74
75
76
46
47
48
49
34
35
36
37
22
23
24
25
I/O
I
EBI Address/Data bus bit11
UART1 Data receiver input pin
Digital GPIO pin
PA.3
I/O
AI
ADC3
AD10
TX1
ADC analog input3
I/O
O
EBI Address/Data bus bit10
UART1 Data transmitter output pin
Digital GPIO pin
PA.4
I/O
AI
ADC4
AD9
ADC analog input4
I/O
I/O
I/O
AI
EBI Address/Data bus bit9
I2C0 data I/O pin
I2C0SDA
PA.5
Digital GPIO pin
ADC5
AD8
ADC analog input5
I/O
I/O
I/O
AI
EBI Address/Data bus bit8
I2C0 clock pin
I2C0SCK
PA.6
Digital GPIO pin
ADC6
AD7
ADC analog input6
77
50
38
I/O
I
EBI Address/Data bus bit7
Timer3 capture input
PWM0 Channel3 output
Digital GPIO pin
TC3
PWM0CH3
PA.7
O
I/O
AI
ADC7
AD6
ADC analog input7
78
51
52
39
40
I/O
I
EBI Address/Data bus bit6
Timer2 capture input
PWM0 Channel2 output
Voltage reference input for ADC
Power supply for internal analog circuit
TC2
PWM0CH2
Vref
O
79
80
AP
AP
26
AVDD
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
PD.0
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
81
RX1
I
UART1 Data receiver input pin
SPI2 2nd slave select pin
SmartCard1 clock pin
Digital GPIO pin
SPISS20
SC1CLK
I/O
O
PD.1
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
82
TX1
O
UART1 Data transmitter output pin
SPI2 serial clock pin
SPICLK2
SC1DAT
I/O
I/O
SmartCard1 DATA pin.
Digital GPIO pin
PD.2
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
RTSn1
O
I/O
I
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
83
I2SLRCLK
MISO20
SC1PWR
O
Digital GPIO pin
PD.3
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
CTSn1
I
UART1 Clear to Send input pin
I2S bit clock pin
84
I2SBCLK
MOSI20
SC1RST
I/O
O
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
O
Digital GPIO pin
PD.4
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
85
I2SDI
I
I
I
I2S data input
MISO21
SC1CD
SPI2 2nd MISO (Master In, Slave Out) pin
SmartCard1 card detect
Digital GPIO pin
PD.5
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
86
I2SDO
O
O
I2S data output
MOSI21
SPI2 2nd MOSI (Master Out, Slave In) pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
PC.7
I/O
I/O
I
Digital GPIO pin
AD5
EBI Address/Data bus bit5
Timer1 capture input
PWM1 Channel1 output
Digital GPIO pin
87
53
41
TC1
PWM0CH1
PC.6
O
I/O
I/O
I
AD4
EBI Address/Data bus bit4
Timer 0 capture input
SmartCard1 card detect pin
PWM0 Channel0 output
Digital GPIO pin
88
54
42
27
TC0
SC1CD
PWM0CH0
O
PC.15
I/O
User program must enable pull-up resistor in LQFP48
package.
89
55
AD3
I/O
I
EBI Address/Data bus bit3
Timer0 capture input
PWM1 Channel1 output
Digital GPIO pin
TC0
PWM1CH2
O
PC.14
I/O
User program must enable pull-up resistor in LQFP48
package.
90
91
56
57
AD2
I/O
I/O
I/O
I
EBI Address/Data bus bit2
PWM1 Channel3 output
Digital GPIO pin
PWM1CH3
PB.15
28
43
nINT1
External interrupt1 input pin
Snooper pin
SNOOPER
XT1_OUT
I
29
30
92
93
58
59
44
45
O
External 4~24 MHz crystal output pin
XT1_IN
I
External 4~24 MHz crystal input pin
External reset input: Low active, set this pin low reset
chip to initial state. With internal pull-up.
94
95
96
60
61
62
46
31
nRESET
VSS
I
P
P
Ground
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
VDD
Digital GPIO pin
PF.4
I/O
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
97
I2C0SDA
I2C0 data I/O pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
QFN
33
100
64
48
Digital GPIO pin
PF.5
I/O
User program must enable pull-up resistor in LQFP64
and LQFP48 package.
98
I2C0SCK
PVSS
I/O
I2C0 clock pin
99
63
64
47
48
32
P
PLL Ground
PB.8
I/O
Digital GPIO pin
ADCTRG
TMR0
I
I
I
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
100
nINT0
Note: Pin Type I=Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power
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4
BLOCK DIAGRAM
4.1 Nano100 Block Diagram
LXT
LIRC
P
L
L
FLASH
EBI
Cortex-M0
32MHz
DMA
CLK_CTL
HXT
64/32KB
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR(1.8V)
BOD(1.7/2.0/2.5 V)
SRAM
16/8KB
ISP 4KB
GPIO
A,B,C,D,E,F
10-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
PWM 0
1.5/2.5V REF
TEMP sensor
Timer 0/1
UART 0
SPI 0
I2S
SPI 2
SC 0
SC 1
RTC
WDT
Peripherals with PDMA
Peripherals with wakeup
NOTE: BOD can wakeup system.
External interrupts, included in GPIO, can wakeup system, too.
Figure 4-1 NuMicroTM Nano100 Block Diagram
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4.2 Nano120 Block Diagram
LXT
LIRC
P
L
L
FLASH
EBI
Cortex-M0
32MHz
DMA
CLK_CTL
HXT
64/32KB
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR(1.8V)
BOD(1.7/2.0/2.5 V)
ISP 4KB
GPIO
SRAM
A,B,C,D,E,F
16/8KB
12-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
12-b DAC
PWM 0
1.5/2.5V REF
Timer 0/1
UART 0
SPI 0
Touch key
USB -512B
TEMP sensor
USB PHY
I2S
SPI 2
SC 0
SC 1
RTC
WDT
Peripherals with PDMA
Peripherals with wakeup
NOTE: BOD can wakeup system.
External interrupts, included in GPIO, can wakeup system, too.
Figure 4-2 NuMicroTM Nano120 Block Diagram
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5
FUNCTIONAL DESCRIPTION
5.1 ARM® Cortex™-M0 Core
5.1.1 Overview
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The following figure shows the functional controller of processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
interface
BusMatrix
(DAP)
AHB- Lite
interface
Serial Wire or
JTAG debug port
Figure 5-1 M0 Functional Block
5.1.2 Features
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
Supports little-endian data accesses
Capable of deterministic, fixed-latency, interrupt handling
Load/store-multiples and multi-cycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
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(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-Maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Wake-up Interrupt Controller (WIC), providing Ultra-low Power Sleep mode
support
Debug support:
Four hardware breakpoints
Two watch points
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to
all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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5.2 Memory Organization
5.2.1 Overview
Nano100 provides 4G-byte addressing space. The memory locations assigned to each on-chip
modules are shown in following. The detailed register definition, memory space, and
programming detailed will be described in the following sections for each on-chip module.
Nano100 series only supports little-endian data format.
5.2.2 Memory Map
The memory locations assigned to each on-chip controllers are shown in the following table.
Address Space
Token
Modules
Flash & SRAM Memory Space
0x0000_0000 – 0x0000_FFFF
0x2000_0000 – 0x2000_3FFF
0x6000_0000 --- 0x6001_FFFF
FLASH_BA
SRAM_BA
FLASH Memory Space (64KB)
SRAM Memory Space (16KB)
External Memory Space(128KB)
EXTMEM_BA
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
GCR_BA
CLK_BA
INT_BA
System Management Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
DMA_BA
FMC_BA
EBI_BA
DMA Control Registers
Flash Memory Control Registers
External Bus Interface Control Registers
APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x400A_0000 – 0x400A_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_3FFF
WDT_BA
RTC_BA
Watch-Dog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer 0 and Timer 1 Control Registers
I2C 0 Interface Control Registers
TMR01_BA
I2C0_BA
SPI0_BA
SPI 0 with Master/Slave function Control Registers
PWM 0 Control Registers
PWM0_BA
UART0_BA
USBD_BA
Reserved
SPI2_BA
UART 0 Control Registers
USB FS device Controller Registers
Reserved
SPI 2 with Master/Slave function Control Registers
12-bit Analog-Digital-Converter (ADC10) Control Registers
ADC10_BA
APB2 Modules Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
TMR23_BA
I2C1_BA
Timer 2 and Timer 3 Control Registers
I2C 1 Interface Control Registers
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0x4013_0000 – 0x4013_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x4019_0000 – 0x4019_3FFF
0x401A_0000 – 0x401A_3FFF
0x401B_0000 – 0x401B_3FFF
SPI1_BA
PWM1_BA
UART1_BA
SC0_BA
I2S_BA
SPI 1 with Master/Slave function Control Registers
PWM 1 Control Registers
UART1 Control Registers
Smart Card 0 Control Registers
I2S Control Registers
SC1_BA
Smart Card 1 Control Registers
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
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5.3 Nested Vectored Interrupt Controller (NVIC)
5.3.1 Overview
Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and
provides following features:
5.3.2 Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority changing
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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5.4 System Manager
5.4.1 Overview
System manager mainly controls the power modes, wake-up source, system resets and system
memory map. It also provides information about product ID, chip reset, IP reset, and multi-function pin
control.
5.4.2 Features
Power modes and wake-up sources
System resets
System Memory Map
System manager registers for :
Product ID
Chip and IP reset
Multi-functional pin control
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5.5 Clock Controller
5.5.1 Overview
The clock controller generates clocks for the whole chip, including system clocks (CPU clock,
HCLKx, and PCLKx) and all peripheral engine clocks. HCLKx means AHB bus clock for
peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. The clock
controller also implements the power control function with the individually clock ON/OFF control,
clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until
CPU sets the power down enable bit (PD_EN(PWRCTL[6])) and CPU executes the WFI
instruction. In the Power-down mode, clock controller turns off the external high frequency crystal,
internal high frequency oscillator, and system clocks (CPU clock, HCLKx, and PCLKx) to reduce
the power consumption to minimum.
5.5.2 Features
Generates clocks for system clocks and all peripheral engine clocks
Each peripheral engine clock can be turned on/off.
High frequency crystal, internal high frequency oscillator, and system clocks will be
turned off when chip is in Power-down mode.
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5.6 FLASH Memory Controller (FMC)
5.6.1 Overview
This chip is equipped with 32KB/64KB on-chip embedded Flash EPROM for application program
memory (APROM) that can be updated through ISP procedure. In System Programming (ISP)
function enables user to update program memory when chip is soldered on PCB. After chip power
on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in
Config0. By the way, this chip also provides DATA Flash Region, the data flash is shared with
original program memory and its start address is configurable and defined by user in Config1. The
data flash size is defined by user application request.
5.6.2 Features
AHB interface compatible
Run up to 32 MHz with zero wait state for discontinuous address read access
32KB/64KB application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page erase
unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
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5.7 External Bus Interface
5.7.1 Overview
This chip is equipped with an external bus interface (EBI) to access external device. To save the
connections between external device and this chip, EBI support address bus and data bus
multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the address and
data cycle.
5.7.2 Features
External devices with max. 64 Kbytes size (8-bit data width)/128 Kbytes (16-bit data
width) supported
Supports variable external bus base clock (MCLK)
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Address bus and data bus multiplex mode supported to save the address pins
Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R), Read-to-Write (R2W)
Supports PDMA and VDMA transfer
5.8 General Purpose I/O Controller
5.8.1 Overview
The NuMicroTM Nano100 series have up to 51 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 51 pins are arranged in 6 ports named
with GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. Each one of the 51 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be independently software configured as input, output, and
open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110
K~300 K for VDD from 1.8 V to 3.6 V.
5.8.2 Features
Three I/O modes:
Schmitt trigger Input-only with high impendence
Push-pull output
Open-drain output
I/O pin configured as interrupt source with edge/level setting
Enabling the pin interrupt function will also enable the pin wake-up function
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5.9 DMA Controller
5.9.1 Overview
The DMA controller contains a four-channel peripheral direct memory access (PDMA) controller
and a one-channel video direct memory access (VDMA) controller that transfers data to and from
memory or transfer data to and from peripherals.For VDMA channel (DMA CH0), it only supports
block transfer from memory to memory. For PDMA channel (DMA CH1~CH4), there is one-word
buffer as transfer buffer between the Peripherals APB devices and Memory. And for VDMA
channel (DMA CH0), there is a two-word buffer.
User can stop the PDMA or VDMA operation by disable PDMACEN (PDMA_CSRx[0]) or
VDMACEN(VDMA_CSR[0]), respectively.
User can polling TD_IS (PDMA_ISRx[1] or
VDMA_ISRx[1]) or enable TD_IE (PDMA_IERx[1] or VDMA_IERx[1]) and wait interrupt to check
DMA transfer complete. The DMA controller can increase source or destination address, fixed or
wrap around them as well.
5.9.2 Features
Five channels: 1 VDMA channel and 4 PDMA channels. Each channel can support a
unidirectional transfer.
VDMA
Supports Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Supports Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-memory
and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
AMBA AHB Master/Slave interface compatible, for data transfer and register
read/write.
Hardware round robin priority scheme.
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5.10 Timer Controller
5.10.1 Overview
This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3
(TIMER0/1 is at APB1 and TIMER2/3 is at APB2), which allow user to easily implement a
counting scheme or timing control for applications. The timer can perform functions like frequency
measurement, event counting, interval measurement, clock generation, delay timing, and so on.
The timer can generate an interrupt signal upon timeout, or provide the current value of count
during operation.
5.10.2 Features
Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3)
Time out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / 25 MHz) * (2^8) * (2^24), if TCLK = 25 MHz
Internal 8-bit pre-scale counter
Internal 24-bit up counter is readable through TDR (Timer Data Register)
Supports One-shot, Periodic and Output Toggle Operation mode
Supports external pin capture for interval measurement
Supports external pin capture for timer counter reset
Supports Inter-Timer trigger
Supports Internal trigger event to ADC and PDMA
5.11 Pulse Width Modulation (PWM)
5.11.1 Overview
This chip has two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3,
or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone
generators.
Each of the two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock
divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent
16-bit PWM down-count counter for PWM period control, and 16-bit comparators for PWM duty
control. Each dead-zone generator has two outputs. The first dead-zone generator output is CH0
and CH1, and for the second dead-zone generator, the output is CH2 and CH3. The 2 sets of
PWM controller total provide eight independent PWM interrupt flags which are set by hardware
when the corresponding PWM period down counter reaches 0. PWM interrupt will be asserted
when both PWM interrupt source and its corresponding enable bit are active. Each PWM output
can be configured as one-shot mode to produce only one PWM cycle signal or continuous mode
to output PWM waveform continuously.
When DZEN01 (PWMx_CTL[4]) (x=0,1) is set, CH0 and CH1 perform complementary PWM
paired function; the paired PWM timing, period, duty and dead-time are determined by PWM
channel 0 timer and Dead-zone generator 0. Similarly, When DZEN23 (PWMx_CTL[5]) is set the
complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
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PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM output
is set as continuous mode, when the down counter reaches 0, it is reloaded with CN of
PWMx_DUTYy (y=0~3) Register automatically then start decreases, repeatedly. If the PWM
output is set as one-shot mode, the down counter will stop and generate one interrupt request
when it reaches 0.
The value of PWM counter comparator is used for pulse width modulation. The counter control
logic changes the output level when down-counter value matches the value of compare register.
The alternate feature of the PWM is digital input capture function. If capture function is enabled
the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share
one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user
must setup the PWM timer before enabling capture feature. After capture feature of channel 0 is
enabled, the capture always latches PWM CH0 timer value to Capture Rising Latch Register CRL
(PWMx_CRL0[15:0]) when input channel has a rising transition and latches PWM CH0 timer
value to Capture Falling Latch Register CFL (PWMx_CFL0[15:0]) when input channel has a
falling transition. Capture channel
0 interrupt is programmable by setting CRL_IE0
(PWMx_CAPINTEN[0]) for rising transition or CFL_IE0 (PWMx_CAPINTEN[1]) for falling
transition. Whenever Capture rising event latched for channel 0, the PWM CH0 timer will be
reload at this moment if the corresponding reload enable bit CAPRELOADREN0
(PWMx_CAPCTL[6]) is set.
The maximum captured frequency that PWM can capture is dominated by the capture interrupt
latency. When capture interrupt occurs, software will do at least three steps, they are:
Read PWMx_INTSTS to get interrupt source and Read PWMx_CRLy/PWMx_CFLy(y=0~3) to get
capture value and finally write 1 to clear PWMx_INTSTS. If interrupt latency will take time T0 to
finish, the capture signal mustn’t transient during this interval. In this case, the maximum capture
frequency will be 1/T0.
5.11.2 Features
5.11.2.1 PWM function:
Two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3, or
as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable
dead-zone generators.
Up to 8 PWM channels or 4 PWM paired channels.
Up to 16 bits PWM counter width.
PWM Interrupt request synchronous with PWM period.
One-shot or Continuous mode.
Four Dead-Zone generators
5.11.2.2 Capture Function:
Timing control logic shared with PWM timer.
8 Capture input channels shared with 8 PWM output channels.
Each channel supports one rising latch register CRL (PWMx_CRL0[15:0]), one falling
latch register CFL (PWMx_CFL0[15:0]) and Capture interrupt flag CAPIF0
(PWMx_CAPINTSTS[0]) .
Eight 16-bit counters for eight capture channels or four 32-bit counter for four capture
channels when cascade is enabled:when CH01CASKEN (PWMx_CAPCTL[13]) is
set ,the original 16-bit counter of channel 1 will combine with channel 0’s 16-bit
counter for channel 0 input capture counting and so does CH23CASKEN
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(PWMx_CAPCTL[29]) for channel 2,3
Supports PDMA transfer function for PWMx channel 0, 2
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5.12 Watchdog Timer Controller
5.12.1 Overview
The purpose of Watchdog Timer is to perform a system reset after the software running into a
problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up CPU from power-down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals.
5.12.2 Features
18-bit free running WDT counter for Watchdog timer time-out interval.
Selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.316
s (if WDT_CLK = 10 kHz).
Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz.
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5.13 RTC
5.13.1 Overview
Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source
of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference to pin
Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit
provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as
calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is
expressed in BCD format. This unit offers alarm function that user can preset the alarm time in
Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR).
The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has
8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR
(TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and
CAR, the alarm interrupt flag (AIS(RTC_RIIR[0])) is set and the alarm interrupt is requested if the
alarm interrupt is enabled (AIER(RTC_RIER[0])=1). The RTC Time Tick (if wake-up CPU function
is enabled, (TWKE(RTC_TTR[3])) high)) and Alarm Match can cause CPU wake-up from idle or
Power-down mode.
5.13.2 Features
There is a time counter (second, minute, hour) and calendar counter (day, month,
year) for user to check the time.
Alarm register (second, minute, hour, day, month, year).
12-hour or 24-hour mode is selectable.
Leap year compensation automatically.
Day of week counter.
Frequency compensate register (FCR).
All time and calendar message is expressed in BCD code.
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm Match interrupt
Supports wake-up CPU from power-down mode.
Supports 80 bytes spare registers and a snoop pin to clear the content of these spare
registers.
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5.14 UART Controller
5.14.1 Overview
The UART Controller provides up to two channels of Universal Asynchronous
Receiver/Transmitter (UART) modules and performs Normal Speed UART, and supports flow
control function. The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-
parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on
data transmitted from the CPU.
The UART controller also supports IrDA (SIR), LIN Master/Slave and RS-485 function modes.
5.14.2 Features
Full duplex, asynchronous communications.
Separate receiving / transmitting 16 bytes entry FIFO for data payloads.
Supports hardware auto-flow control function (CTSn, RTSn) and programmable
(CTSn, RTSn) flow control trigger level.
Supports programmable baud rate generator for each channel.
Supports auto-baud rate detect function.
Supports programmable receiver buffer trigger level.
Supports incoming data or CTSn to wake-up function.
Supports 9 bit receiver buffer time-out detection function.
All UART channels can be served by the PDMA controller.
Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting DLY(UART_TMCTL[23:16]) register.
Supports IrDA SIR function mode
Supports LIN function mode.
Supports RS-485 function mode.
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5.15 Smart Card Host Interface (SC)
5.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.15.2 Features
ISO-7816-3 T = 0, T = 1 compliant.
EMV2000 compliant
Up to two ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads.
Programmable transmission clock frequency.
Programmable receiver buffer trigger level.
Programmable guard time selection (11 ETU ~ 267 ETU).
A 24-bit and two 8 bit timers for Answer to Request (ATR) and waiting times
processing.
Supports auto inverse convention function.
Supports transmitter and receiver error retry and error number limitation function.
Supports hardware activation sequence process.
Supports hardware warm reset sequence process.
Supports hardware deactivation sequence process.
Supports hardware auto deactivation sequence when detected the card removal.
Supports UART mode
Half duplex, asynchronous communications.
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
Supports programmable baud rate generator for each channel.
Supports programmable receiver buffer trigger level.
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SC_EGTR register.
Programmable even, odd or no parity bit generation and detection.
Programmable stop bit, 1 or 2 stop bit generation.
5.16 I2C
5.16.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
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byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte.
A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL.
The controller’s on-chip I2C logic provides the serial interface that meets the I2C bus standard
mode specification. The I2C controller handles byte transfers autonomously. Pull up resistor is
needed for I2C operation as these are open drain pins.
The I2C controller is equipped with two slave address registers. The contents of the registers are
irrelevant when I2C is in Master mode. In the Slave mode, the seven most significant bits must be
loaded with the user’s own slave address. The I2C hardware will react if the contents of I2CADDR
are matched with the received slave address.
This controller supports the “General Call (GC)” function. If the GCALL (I2CSADDR[0]) bit is set
this controller will respond to General Call address (00H). Clear GC bit to disable general call
function. When GCALL bit is set and the I2C is in Slave mode, it can receive the general call
address which is equal to 00H after master sends general call address to the I2C bus, then it will
follow status of GC mode. If it is in Master mode, the ACK bit must be cleared when it sends
general call address of 00H to the I2C bus.
The I2C-bus controller supports multiple address recognition with two address mask register.
When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to 0, that means the received corresponding register bit
should be exact the same as address register.
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5.16.2 Features
Supports two I2C channels and both of them can acts as Master or Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
One built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
Programmable clock divider allows versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( Two slave addresses with mask option)
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5.17 SPI
5.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol.
Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to
perform a serial-to-parallel conversion on data received from a peripheral device, and a parallel-
to-serial conversion on data transmitted to a peripheral device. The SPI controller can be
configured as a master or a slave device.
The SPI controller supports wake-up function. When this chip stays in power-down mode, it can
be waked up chip by off-chip device.
This controller supports variable serial clock for special application and 2 data channel transfer
mode to connect 2 off-chip slave devices. The SPI controller also supports PDMA function to
access the data buffer.
5.17.2 Features
Up to two sets of SPI controllers
Supports Master (max. 16 MHz) or Slave (max. 6 MHz) mode operation
Supports 1 bit data channel and 2 bit data channel transfer mode
Configurable bit length of a transaction from 8 to 32 bits and configurable transaction
number up to 2 of a transfer in burst mode, so the maximum bit length is 64 bits for
each data transfer in burst mode
Supports MSB first or LSB first transfer sequence
Two slave select lines supported in Master mode
Configurable byte or word suspend mode
Supports byte re-ordering function
Supports variable serial clock in Master mode
Provide Dual FIFO buffers
Supports wake-up function
Supports PDMA transfer
Supports 3-wires, no slave select signal, bi-direction interface
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5.18 I2S
5.18.1 Overview
The audio controller consists of I2S protocol to interface with external audio CODEC. Two 8 word
deep FIFO for receiving path and transmitting path respectively and is capable of handling 8-, 16-,
24-, 32-bit word sizes. PDMA controller handles the data movement between FIFO and memory.
5.18.2 Features
Support Master mode and Slave mode
Capable of handling 8-, 16-, 24- or 32-bit word sizes
Supports monaural and stereo audio data
Supports I2S and MSB justified data format
Provides two 8-level FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Support PDMA transfer
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5.19 USB
5.19.1 Overview
The USB controller is a USB 2.0 full-speed device controller. It is compliant with USB 2.0 full
speed device specification and supports control/bulk/interrupt/isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There is an internal 512-byte SRAM as data buffer in this controller. For IN token or OUT token
transfer, it is necessary to write data to SRAM or read data from SRAM through the APB
interface. Users need to allocate the effective starting address of SRAM for each endpoint buffer
through “buffer segmentation register (BUFSEG)”.
This device controller contains 6 configurable endpoints. Each endpoint can be configured as IN
or OUT endpoint. The function address of the device and endpoint number in each endpoint shall
be configured properly in advance for receiving or transmitting a data packet correctly. The
transmitting/receiving length in each endpoint is defined in maximum payload register (MXPLD)
and the handshakes between Host and Device are also handled by it.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of events
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables the DRVSE0 bit (USB_DRVSE0), the
USB controller will force USB_DP and USB_DM to level low and USB device function is disabled
(disconnected). After disable the DRVSE0 bit, host will enumerate the USB device again.
Reference: Universal Serial Bus Specification Revision 2.0
5.19.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
Compliant with USB 2.0 Full-Speed specification.
Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS).
Supports Control/Bulk/Interrupt/Isochronous transfer type.
Supports suspend function when no bus activity existing for 3 ms.
Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
512-byte SRAM buffer inside
Provide remote wake-up capability.
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5.20 Analog to Digital Converter (ADC)
5.20.1 Overview
The Nano100 series contains one 12-bit successive approximation analog-to-digital converters (SAR
A/D converter) with 8 external input channels and 1 internal channel. The A/D converter supports
three operation modes: single, single-cycle scan and continuous scan mode, and can be started by
software, external STADC/PB.8 pin, timer event start.
Note that the I/O pins used as ADC analog input pins must configure the Pin Function (PA_L_MFP) to
ADC input and off digital function (GPIOA_OFFD) should be turned on before ADC function is
enabled.
5.20.2 Features
Analog input voltage range: 0~Vref (Max to 3.6V).
12-bit resolution and 8-bits accuracy is guaranteed.
Up to 8 external analog input channels (channel0 ~ channel7), and 1 internal channel
(channel10) converting four voltage sources (internal band-gap voltage, internal temperature
sensor output, AVDD, and AVSS).
Maximum ADC clock frequency is 16 MHz and each conversion is 21 clocks.
Three operating modes
Single mode: A/D conversion is performed one time on a specified channel.
Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels
with the sequence from the lowest numbered channel to the highest numbered channel.
Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until
software stops A/D conversion.
An A/D conversion can be started by
Software write 1 to ADST bit
External pin STADC
Selects one from four timer events (TMR0, TMR1, TMR2 and TMR3) that enable ADC and
transfer AD results by PDMA
Conversion results are held in data registers for each channel
Supports data registers to hold conversion results for each channel.
Supports A/D conversion End interrupt to indicate the end of A/D conversion.
Supports two digital comparators to compare conversion result with a specified value.
Supports digital comparator interrupt to indicate that conversion result meets setting condition.
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6
APPLICATION CIRCUIT
DVCC
[1]
CS
CLK
MISO
MOSI
Power
SPISS
SPICLK
MISO
AVDD
VDD
VSS
AVCC
1uF//10nF
SPI Device
In Case
VREF = AVDD
MOSI
VREF
AVSS
VREF
1uF//10nF
DVCC
4.7K
DVCC
AVSS
VDD
VSS
VCC
4.7K
CLK
DIO
SCL
SDA
VDD
I2C Device
VDD
VSS
ICE_DAT
ICE_CLK
SWD
Interface
/RESET
VSS
20p
20p
XT1_IN
Nano100AN
Crystal
4~24 MHz
crystal
XT1_OUT
DVCC
10K
Reset
Circuit
RS232 Transceiver
ROUT RIN
PC COM Port
nRESET
RX
TX
10uF/25V
UART
TIN
TOUT
LDO_CAP
1uF
LDO
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7
ELECTRICAL CHARACTERISTIC
7.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
-0.3
MAX
+3.6
5.5
UNIT
V
DC Power Supply
VDD
SS
Input Voltage on five-volt tolerance pin
VIN
VIN
VSS -0.3
V
Input Voltage on any other pin without five-volt
tolerance pin
VSS -0.3
VDD +0.3
V
Oscillator Frequency
1/tCLCL
TA
4
24
+85
+150
150
150
25
MHz
C
Operating Temperature
-40
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
25
100
100
Note: GPIO supports input 5V tolerance except ADC shared pins, PC.6 and PC.7.
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7.2 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
Operation voltage
Power Ground
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
1.8
-
3.6
V
VDD =1.8V up to 32 MHz
VSS
-0.3
-
V
V
V
V
AVSS
VLDO1
VLDO2
AVDD
1.62
1.8
1.66
VDD
1.98
MCU operating in run or Idle mode
MCU operating in Power-down mode
LDO Output Voltage
Analog Operating Voltage
VDD = 3.6V@32MHz,
enable all IP and PLL
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
14
7.5
12
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 3.6V@32MHz
Operating Current
Run Mode
disable all IP and enable PLL
@ XTAL 12MHz,
HCLK = 32 MHz
VDD = 1.8V@32MHz
enable all IP and PLL
VDD = 1.8V@32MHz
disable all IP and enable PLL
VDD = 3.6V@12MHz,
5
enable all IP and disable PLL
VDD = 3.6V@12MHz,
Operating Current
Run Mode
2.5
4
disable all IP and disable PLL
@ XTAL 12MHz,
HCLK = 12MHz
VDD = 1.8V@12MHz,
enable all IP and disable PLL
VDD = 1.8V@12MHz,
2
disable all IP and disable PLL
VDD = 3.6V@12MHz,
6
enable all IP and disable PLL
VDD = 3.6V@12MHz,
Operating Current
Run Mode
2.3
5.7
2.2
disable all IP and disable PLL
@ IRC 12MHz,
HCLK = 12MHz
VDD = 1.8V@12MHz,
enable all IP and disable PLL
VDD = 1.8V@12MHz,
disable all IP and disable PLL
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 3.6V@4MHz,
IDD13
IDD14
IDD15
2.2
mA
enable all IP and disable PLL
VDD = 3.6V@4MHz,
Operating Current
Run Mode
1.1
2
mA
mA
disable all IP and disable PLL
@ XTAL 4MHz,
HCLK = 4MHz
VDD = 1.8V@4MHz,
enable all IP and disable PLL
VDD = 1.8V@4MHz,
IDD16
1
mA
disable all IP and disable PLL
VDD = 3.6V@32.768 kHz
IDD17
IDD18
IDD19
IDD20
IDD21
IDD22
IDD23
IDD24
IIDLE1
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
90
80
75
72
80
75
67
65
10.5
4.2
9
uA
uA
enable all IP and disable PLL,
VDD = 3.6V@32.768 kHz
Operating Current
Run Mode
disable all IP and disable PLL
@ XTAL 32.768 kHz,
HCLK = 32.768 kHz
VDD = 1.8V@32.768 kHz
uA
enable all IP and disable PLL
VDD = 1.8V@32.768kHz
uA
disable all IP and disable PLL
VDD = 3.6V@10kHz
uA
enable all IP and disable PLL
VDD = 3.6V@10kHz
Operating Current
Run Mode
uA
disable all IP and disable PLL
@ IRC 10kHz,
HCLK = 10kHz
VDD = 1.8V@10kHz
uA
enable all IP and disable PLL
VDD = 1.8V@10kHz
uA
disable all IP and disable PLL
VDD= 3.6V@32MHz
mA
mA
mA
mA
mA
mA
mA
enable all IP and PLL,
VDD=3.6V@32MHz
Operating Current
Idle Mode
disable all IP and enable PLL
@ XTAL 12MHz,
HCLK = 32MHz
VDD = 1.8V@32MHz
enable all IP and PLL
VDD = 1.8V@32MHz
4
disable all IP and enable PLL
VDD = 3.6V@12MHz,
3.3
0.7
3
enable all IP and disable PLL
Operating Current
Idle Mode
VDD = 3.6V@12MHz,
@ XTAL 12MHz,
HCLK = 12MHz
disable all IP and disable PLL
VDD = 1.8V@12MHz,
enable all IP and disable PLL
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 1.8V@12MHz,
IIDLE8
0.7
mA
disable all IP and disable PLL
VDD = 3.6V@12MHz,
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
4.5
0.7
4.2
0.7
1.7
0.6
1
mA
mA
mA
mA
mA
mA
mA
enable all IP and disable PLL
VDD = 3.6V@12MHz,
Operating Current
Idle Mode
disable all IP and disable PLL
@ IRC 12MHz,
HCLK = 12MHz
VDD = 1.8V@12MHz,
enable all IP and disable PLL
VDD = 1.8V@12MHz,
disable all IP and disable PLL
VDD = 3.6V@4MHz,
enable all IP and disable PLL
VDD = 3.6V@4MHz,
Operating Current
Idle Mode
disable all IP and disable PLL
@ XTAL 4MHz,
HCLK = 4MHz
VDD = 1.8V@4MHz,
enable all IP and disable PLL
VDD = 1.8V@4MHz,
IIDLE16
0.5
mA
disable all IP and disable PLL
VDD = 3.6V@ 32.768kHz
IIDLE17
IIDLE18
IIDLE19
85
75
70
uA
uA
uA
enable all IP and disable PLL
VDD = 3.6V@ 32.768kHz
Operating Current
Idle Mode
disable all IP and disable PLL
@ XTAL 32.768kHz,
HCLK = 32.768kHz
VDD = 1.8V@ 32.768kHz
enable all IP and disable PLL
VDD = 1.8V@ 32.768kHz
IIDLE20
65
uA
disable all IP and disable PLL
VDD = 3.6V@ 10kHz
IIDLE21
IIDLE22
IIDLE23
IIDLE24
IPWD1
80
75
65
63
1.5
uA
uA
uA
uA
A
enable all IP and disable PLL
VDD = 3.6V@ 10kHz
Operating Current
Idle Mode
disable all IP and disable PLL
@ IRC 10kHz,
HCLK = 10kHz
VDD = 1.8V@ 10kHz
enable all IP and disable PLL
VDD = 1.8V@ 10kHz
disable all IP and disable PLL
Standby Current
VDD = 3.6V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
Power-down Mode
Mar 31, 2015
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 1.8V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
IPWD2
1.0
A
VDD = 3.6V, RTC ON, all clock stop except
32.768kHz
IPWD3
3
A
A
With RAM Retenstion, IO no loading
VDD = 1.8V, RTC ON, all clock stop except
32.768kHz
IPWD4
2.5
With RAM Retenstion, IO no loading
40
98
KΩ VDD = 3.3V
KΩ VDD = 1.8V
Input Pull Up Resistor PA,
PB, PC, PD, PE, PF
RIN
Input Leakage Current PA,
PB, PC, PD, PE, PF
ILK
-0.1
-
-
+0.1
VDD = 3.3V, 0<VIN<VDD
A
Input Low Voltage PA, PB,
PC, PD, PE, PF
VIL1
0.4VDD
V
(Schmitt input)
Input High Voltage PA, PB,
PC, PD, PE, PF
ADC shared pins, PC.6 and PC.7 without Input
5V tolerance.
VIH1
0.6VDD
5.5
V
V
(Schmitt input)
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
0.2VDD
Input Low Voltage XT1[*2]
Input High Voltage XT1[*2]
Input Low Voltage X32I[*2]
Input High Voltage X32I[*2]
VIL2
VIH2
VIL4
VIH4
0
-
-
-
-
0.4
VDD +0.2
0.3
VDD = 3.3V
VDD = 3.3V
2.4
0
V
V
V
1.5
1.98
Negative going threshold
(Schmitt input), /RESET
VILS
VIHS
ISR21
ISR22
ISK1
1.28
1.75
-10
1.33
1.98
-14
1.37
V
VDD = 3.3V
VDD = 3.3V
Positive going threshold
(Schmitt input), /RESET
2.25
V
VDD = 3.3V,
-
-
-
-
mA
mA
mA
mA
Source Current PA, PB,
PC, PD, PE, PF
VS = Vdd-0.7V
VDD = 1.8V,
(Push-pull Mode)
-4.06
16
-6.5
19
VS = Vdd-0.45V
VDD = 3.3V,
VS = 0.7V
Sink Current PA, PB, PC,
PD, PE, PF
VDD = 1.8V,
VS = 0.45V
(Push-pull Mode)
ISK1
4.14
6.97
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
Mar 31, 2015
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3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin and the closest VSS pin
of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise
7.3 AC Electrical Characteristics
7.3.1 External Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
10
10
2
TYP.
MAX.
UNIT
nS
Clock High Time
tCHCX
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
tCLCX
tCLCH
tCHCL
nS
15
15
nS
2
nS
t
CLCL
t
t
CLCH
CLCX
t
t
CHCL
CHCX
7.3.2 External 4~24 MHz XTAL Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
4
TYP.
12
MAX.
24
UNIT
MHz
oC
Oscillator frequency
fHXTAL
THXTAL
IHXTAL
VDD = 1.8V ~ 3.6V
Temperature
-40
-
+85
Operating current
0.3
mA
VDD = 3.0V
7.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4MHz ~ 24 MHz
Optional(Depend on crystal specification)
without
XT1_OUT
XT1_IN
R1
C1
C2
Mar 31, 2015
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Nano100(A)
Figure 7-1 Typical Crystal Application Circuit
7.3.3 External 32.768 kHz Crystal
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
32.768
-
MAX.
UNIT
kHz
oC
Oscillator frequency
fLXTAL
TLXTAL
IHXTAL
VDD = 1.8V ~ 3.6V
Temperature
-40
+85
Operating current
1.2
VDD = 3.0V
A
7.3.4 Internal 12 MHz Oscillator
SPECIFICATIONS
PARAMETER
Supply voltage[1]
SYM.
TEST CONDITIONS
MIN.
TYP.
1.8
12
MAX.
UNIT
VHRC
V
11.88
10.8
12.12
13.2
MHz 25oC, VDD = 3V
12
MHz -40oC~+85 oC, VDD = 1.8V~3.6V
-40oC~+85 oC, VDD = 1.8V~3.6V
Calibrated
Frequency
Internal
Oscillator
FHRC
11.88
12
12.12
MHz
Enable 32.768K crystal oscillator and set
TRIM_SEL[1:0]=”10”
Operating current
IHRC
TBD
mA
Note: Internal oscillator operation voltage comes from LDO.
7.3.5 Internal 10 kHz Oscillator
SPECIFICATION
PARAMETER
Supply voltage[1]
SYM.
VLRC
FLRC
ILRC
TEST CONDITIONS
MIN.
TYP.
1.8
10
MAX.
UNIT
V
7
5
13
15
kHz 25oC, VDD = 3V
Center Frequency
10
kHz -40oC~+85 oC, VDD = 1.8V~3.6V
Operating current
0.7
VDD = 3V
A
Note: Internal oscillator operation voltage comes from LDO.
7.4 Analog Characteristics
7.4.1 12-bit ADC
SPECIFICATIONS
TYP. MAX.
PARAMETER
SYM.
TEST CONDITIONS
MIN.
UNIT
Mar 31, 2015
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Nano100(A)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Operating voltage
AVDD
IADC
2.0
3.6
V
AVDD = VDD
Operating current
Resolution
TBD
mA AVDD = VDD = 3.0V
RADC
VREF
IREF
12
Bit
Reference voltage
Reference input current (Avg.)
ADC input voltage
Conversion time
Sampling Rate
1.5
AVDD
V
320
A
VIN
0
VREF
V
TCONV
FSPS
INL
1.25
S
800K
±8
Hz VDD = 3V
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
±4
-1~+4
±16
±4
LSB
LSB
LSB
LSB
LSB
MHz
Cycle
pF
DNL
EG
-1~+8
Offset error
EOFFSET
EABS
FADC
ADCYC
CIN
Absolute error
-
±16
16
ADC Clock frequency
Clock cycle
0.25
21
-
Internal Capacitance
Internal Resistance
Monotonic
3.2
200
-
-
Ω
RIN
-
-
Guaranteed
-
7.4.2 Brown-out Detector
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
Operating voltage
Quiescent current
VBOD
IBOD
1.8
3.6
1
AVDD = 3.0V, BOD enabled
A
V
VB17dt1
VB17dt2
VB20dt1
VB20dt2
VB25dt1
VB25dt2
1.6
1.5
1.9
1.8
2.4
2.2
1.7
1.7
2.0
2.0
2.5
2.5
1.8
1.9
2.1
2.2
2.6
2.8
25oC
BOD17 detection level
BOD20 detection level
BOD25 detection level
V
-40~85oC
25oC
V
V
-40~85oC
25oC
V
V
-40~85oC
Mar 31, 2015
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Nano100(A)
7.4.3 Power-On Reset
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
1.6
1
MAX.
UNIT
V
Reset voltage
VPOR
IPOR
-
-
-
-
Quiescent current
nA
LDO output > Reset voltage
7.4.4 Temperature Sensor
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
oC
Detection Temperature
Operating current
Gain
TDET
ITEMP
VTG
-40
+125
-
-
-
5
-
-
-
A
-1.64
750
mV/ oC
Offset
VTO
mV Tempeature at 0 oC
Note: Internal operation voltage comes form LDO.
7.4.5 Internal Voltage Reference
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
-
MAX.
UNIT
Operating voltage
AVDD
VREF1
VREF2
TREFTAB
IVREF
1.8
3.6
V
V
1.5V voltage reference
2.5V voltage reference
Stable Time
-
-
-
-
1.5
2.5
1
-
-
-
-
AVDD >= 1.8V
AVDD >= 2.8V
V
ms
A
Operating current
30
AVDD = 3V
7.4.6 USB PHY Specifications
7.4.6.1 USB PHY DC Electrical Characteristics
SYMBOL
VIH
PARAMETER
Input high (driven)
Input low
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.0
-
-
-
V
V
V
VIL
0.8
VDI
Differential input sensitivity
|PADP-PADM|
0.2
0.8
0.8
Differential
VCM
VSE
Includes VDI range
-
2.5
2.0
V
common-mode range
Single-ended receiver threshold
Receiver hysteresis
-
V
200
mV
Mar 31, 2015
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Nano100(A)
VOL
VOH
VCRS
RPU
RPD
Output low (driven)
Output high (driven)
Output signal cross voltage
Pull-up resistor
0
-
-
-
-
-
0.3
3.6
V
V
2.8
1.3
2.0
V
1.425
14.25
1.575
15.75
kΩ
kΩ
Pull-down resistor
Termination Voltage for upstream port
pull up (RPU)
VTRM
3.0
-
3.6
V
ZDRV
CIN
Driver output resistance
Transceiver capacitance
Steady state drive*
Pin to GND
10
-
Ω
20
pF
*Driver output resistance doesn’t include series resistor resistance.
7.4.6.2 USB PHY Full-Speed Driver Elevtrical Characteristics
SYMBOL
TFR
PARAMETER
Rise Time
CONDITIONS
CL=50p
MIN.
4
TYP.
MAX.
20
UNIT
ns
-
-
-
TFF
Fall Time
CL=50p
4
20
ns
TFRFF
Rise and fall time matching
TFRFF=TFR/TFF
90
111.11
%
7.4.6.3 USB PHY Power Dissipation
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IVDDREG
VDDD and VDDREG Supply Current
(Steady State)
Standby
50
uA
(Full Speed)
7.4.6.4 USB LDO DC Electrical Characteristics
SYMBOL
VBUS
V33
PARAMETER
CONDITIONS
MIN.
TYP.
5
MAX.
UNIT
V
Output voltage
3.3
100
V
Iop
Operation Current
uA
Mar 31, 2015
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Nano100(A)
8
PACKAGE DIMENSIONS
8.1 LQFP100 (14x14x1.4 mm footprint 2.0 mm)
H
D
D
A
A2
7
A1
51
7
50
H
E E
100
26
L1
L
1
25
c
e
b
Y
Controlling Dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
A
Min Nom
Max
Min Nom
Max
1.60
0.063
A1
A
0.002
0.05
1.45
0.27
0.053 0.055 0.057
1.35
0.17
0.10
1.40
0.22
b
0.011
0.008
0.009
0.006
0.007
0.004
0.547
0.547
c
0.15
0.20
D
E
14.00
0.551
0.551
0.020
14.10
13.90
13.90
0.556
0.556
14.00 14.10
0.50
e
H D
16.00
16.20
16.20
16.00
15.80
15.80
0.45
0.622
0.638
0.638
0.030
0.630
H E
L
0.622 0.630
0.60
1.00
0.75
0.024
0.039
0.018
L1
y
0.10
7
0.004
7
0
0
Mar 31, 2015
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Nano100(A)
8.2 LQFP64 (7x7x1.4 mm footprint 2.0 mm)
Mar 31, 2015
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Nano100(A)
Mar 31, 2015
Page 89 of 95
Revision V1.00
Nano100(A)
8.3 LQFP48 (7x7x1.4 mm footprint 2.0 mm)
Mar 31, 2015
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Nano100(A)
8.4 QFN33 (5x5x0.8 mm footprint 0.5 mm)
Mar 31, 2015
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Mar 31, 2015
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Nano100(A)
9
REVISION HISTORY
Date
Revision Description
2011.05.31
2011.08.22
0.001
0.002
Initial release
Modified the Electrical Characteristics section
1. Changed the max SPI speed to 16 MHz
2. ADC pin without 5V tolerance
3. Modified the Electrical Characteristics section
4. Removed XT1_IN and XT1_OUT GPIO (PF.2/PF.3) shared
function
2011.10.31
0.003
5. Modified pin diagram and pin description
6. Removed timer continuous operation mode and UART
wakeup function
7. Revised the product selection table
8. Fixed typos.
1. Updated pin diagram and pin description
2011.12.31
2012.04.09
0.004
0.005
2. Updated the DC Electrical Characteristics section
1. Removed UART1 shared function from pin-26 to pin-29 in
NANO100 LQFP100 package
2. Added detailed description of “I2CINTSTS” register (I2Cx_BA
+ 0x04)
1. Removed NANO110/NANO130 series information.
2. Updated Nano100 series selection code in section 3.1.
3. Updated Nano100 product selection guide in section 3.2.
2013.06.27
2013.07.30
0.006
4. Removed GPIOF[2] and GPIOF[3] of Multiple Function Port F
in section 5.4.5.
5. Added a note “For GPIOF_PUEN, bits [15:6] and [3:2] are
reserved” in section 5.8.6.
1. Updated Nano100 product selection guide in section 3.2.
0.007
0.008
2. Added Nano100 QFN33 pin diagram and description in
section 3.3.1.4 and 3.4.1.
1. Updated Nano100 product selection guide in section 3.2.
2. Changed Timer0/1 Ch0/1 to Timer x (x=0, 1, 2, 3) in the Timer
2014.12.29
Mar 31, 2015
Page 93 of 95
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Nano100(A)
Controller section.
1. Updated Electrical Characteristics TBD items in chapter 7.
2. Added Application Circuit in chapter 6.
3. Added a noto that “GPIO supports input 5V tolerance except
ADC shared pins, PC.6 and PC.7” in section 7.1.
4. Updated the value of capacitor connected with LDO pin to be
1uF in section 7.2.
2015.03.31
1.00
5. Updated external 4~24 MHz XTAL application circuit in
section 7.3.4.
6. Updated 12-bit ADC characteristics in section 7.4.1.
7. Added Brown-out Detector characteristics in a full operating
temperature range in section 7.4.2.
Mar 31, 2015
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Nano100(A)
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Mar 31, 2015
Page 95 of 95
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