NANO536-SE0AN [NUVOTON]
ARM® Cortex®-M 32-bit Microcontroller;
| 型号： | NANO536-SE0AN |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总160页 (文件大小：3346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUMICRO® NANO100 (B) DATASHEET
ARM® Cortex® -M
32-bit Microcontroller
NuMicro® Family
Nano100 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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Table of Contents
LIST OF FIGURES........................................................................................................................... 6
LIST OF TABLES............................................................................................................................. 7
1
2
GENERAL DESCRIPTION ..................................................................................................... 8
FEATURES ........................................................................................................................... 10
2.1
2.2
2.3
2.4
Nano100 Features – Base Line ................................................................................. 10
Nano110 Features – LCD Line .................................................................................. 16
Nano120 Features – USB Connectivity Line.............................................................. 22
Nano130 Features – Advanced Line.......................................................................... 28
3
PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 34
3.1
3.2
NuMicro® Nano100 Series Selection Code................................................................ 34
NuMicro® Nano100 Products Selection Guide........................................................... 35
3.2.1 NuMicro® Nano100 Base Line Selection Guide..............................................................35
3.2.2 NuMicro® Nano110 LCD Line Selection Guide...............................................................35
3.2.3 NuMicro® Nano120 USB Connectivity Line Selection Guide ..........................................35
3.2.4 NuMicro® Nano130 Advanced Line Selection Guide......................................................36
Pin Configuration........................................................................................................ 37
3.3.1 NuMicro® Nano100 Pin Diagrams ..................................................................................37
3.3.2 NuMicro® Nano110 Pin Diagrams ..................................................................................40
3.3.3 NuMicro® Nano120 Pin Diagrams ..................................................................................42
3.3.4 NuMicro® Nano130 Pin Diagrams ..................................................................................45
Pin Description ........................................................................................................... 47
3.3
3.4
3.4.1 NuMicro® Nano100 Pin Description................................................................................47
3.4.2 NuMicro® Nano110 Pin Description................................................................................58
3.4.3 NuMicro® Nano120 Pin Description................................................................................72
3.4.4 NuMicro® Nano130 Pin Description................................................................................83
4
5
BLOCK DIAGRAM ................................................................................................................ 97
4.1
4.2
4.3
4.4
Nano100 Block Diagram ............................................................................................ 97
Nano110 Block Diagram ............................................................................................ 98
Nano120 Block Diagram ............................................................................................ 99
Nano130 Block Diagram .......................................................................................... 100
FUNCTIONAL DESCRIPTION............................................................................................ 101
5.1
5.2
5.3
5.4
Memory Organization............................................................................................... 101
5.1.1 Overview ......................................................................................................................101
5.1.2 Memory Map ................................................................................................................101
Nested Vectored Interrupt Controller (NVIC) ........................................................... 103
5.2.1 Overview ......................................................................................................................103
5.2.2 Features .......................................................................................................................103
System Manager ...................................................................................................... 104
5.3.1 Overview ......................................................................................................................104
5.3.2 Features .......................................................................................................................104
Clock Controller........................................................................................................ 105
5.4.1 Overview ......................................................................................................................105
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5.4.2 Features .......................................................................................................................105
Analog to Digital Converter (ADC) ........................................................................... 106
5.5
5.6
5.7
5.8
5.9
5.5.1 Overview ......................................................................................................................106
5.5.2 Features .......................................................................................................................106
Digital to Analog Converter (DAC) ........................................................................... 107
5.6.1 Overview ......................................................................................................................107
5.6.2 Features .......................................................................................................................107
DMA Controller......................................................................................................... 108
5.7.1 Overview ......................................................................................................................108
5.7.2 Features .......................................................................................................................108
External Bus Interface.............................................................................................. 110
5.8.1 Overview ......................................................................................................................110
5.8.2 Features .......................................................................................................................110
FLASH Memory Controller (FMC)............................................................................ 111
5.9.1 Overview ......................................................................................................................111
5.9.2 Features .......................................................................................................................111
5.10 General Purpose I/O Controller................................................................................ 112
5.10.1 Overview ....................................................................................................................112
5.10.2 Features .....................................................................................................................112
5.11 I2C............................................................................................................................. 113
5.11.1 Overview ....................................................................................................................113
5.11.2 Features .....................................................................................................................114
5.12 I2S............................................................................................................................. 115
5.12.1 Overview ....................................................................................................................115
5.12.2 Features .....................................................................................................................115
5.13 LCD Display Driver................................................................................................... 116
5.13.1 Overview ....................................................................................................................116
5.13.2 Features .....................................................................................................................116
5.14 Pulse Width Modulation (PWM) ............................................................................... 117
5.14.1 Overview ....................................................................................................................117
5.14.2 Features .....................................................................................................................118
5.15 RTC .......................................................................................................................... 119
5.15.1 Overview ....................................................................................................................119
5.15.2 Features .....................................................................................................................119
5.16 Smart Card Host Interface (SC) ............................................................................... 119
5.16.1 Overview ....................................................................................................................119
5.16.2 Features .....................................................................................................................119
5.17 SPI............................................................................................................................ 121
5.17.1 Overview ....................................................................................................................121
5.17.2 Features .....................................................................................................................121
5.18 Timer Controller........................................................................................................ 122
5.18.1 Overview ....................................................................................................................122
5.18.2 Features .....................................................................................................................122
5.19 UART Controller....................................................................................................... 123
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5.19.1 Overview ....................................................................................................................123
5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In LIN
mode, one start bit and 8-bit data format with 1-bit stop bit are required in accordance with the
LIN standard. Features..............................................................................................................124
5.20 USB .......................................................................................................................... 126
5.20.1 Overview ....................................................................................................................126
5.20.2 Features .....................................................................................................................126
5.21 Watchdog Timer Controller ...................................................................................... 127
5.21.1 Overview ....................................................................................................................127
5.21.2 Features .....................................................................................................................127
5.22 Window Watchdog Timer Controller ........................................................................ 128
5.22.1 Overview ....................................................................................................................128
5.22.2 Features .....................................................................................................................128
ARM® CORTEX™-M0 CORE ............................................................................................. 129
6
7
6.1
6.2
Overview................................................................................................................... 129
Features ................................................................................................................... 129
APPLICATION CIRCUIT..................................................................................................... 131
7.1
LCD Charge Pump................................................................................................... 131
7.1.1 C-type 1/3 Bias.............................................................................................................131
7.1.2 C-type 1/2 Bias.............................................................................................................131
7.1.3 Internal R-type..............................................................................................................131
7.1.4 External R-type.............................................................................................................132
ADC Application Circuit............................................................................................ 133
7.2
7.3
7.4
7.2.1 Voltage Reference Source ...........................................................................................133
DAC Application Circuit............................................................................................ 135
7.3.1 Voltage Reference Source ...........................................................................................135
Whole Chip Application Circuit................................................................................. 137
8
9
POWER COMSUMPTION .................................................................................................. 138
ELECTRICAL CHARACTERISTIC ..................................................................................... 139
9.1
9.2
9.3
Absolute Maximum Ratings...................................................................................... 139
Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics..................... 139
AC Electrical Characteristics.................................................................................... 145
9.3.1 External Input Clock .....................................................................................................145
9.3.2 External 4~24 MHz XTAL Oscillator.............................................................................145
9.3.3 External 32.768 kHz Crystal.........................................................................................146
9.3.4 Internal 12 MHz Oscillator ............................................................................................146
9.3.5 Internal 10 kHz Oscillator .............................................................................................146
Analog Characteristics ............................................................................................. 146
9.4
9.4.1 12-bit ADC....................................................................................................................146
9.4.2 Brown-out Detector.......................................................................................................147
9.4.3 Power-on Reset............................................................................................................148
9.4.4 Temperature Sensor.....................................................................................................148
9.4.5 12-bit DAC....................................................................................................................148
9.4.6 LCD ..............................................................................................................................149
9.4.7 Internal Voltage Reference...........................................................................................149
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9.4.8 USB PHY Specifications...............................................................................................149
Flash DC Electrical Characteristics.......................................................................... 151
9.5
10 PACKAGE DIMENSIONS................................................................................................... 152
10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm)............................................................ 152
10.2 LQFP64 (10x10x1.4 mm footprint 2.0 mm).............................................................. 153
10.3 LQFP64 (7x7x1.4 mm footprint 2.0 mm).................................................................. 154
10.4 LQFP48 (7x7x1.4 mm footprint 2.0 mm).................................................................. 156
10.5 QFN48 (7x7x0.85 mm)............................................................................................. 157
11 REVISION HISTORY.......................................................................................................... 158
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LIST OF FIGURES
Figure 3‑1 NuMicro® Nano100 Series Selection Code.................................................................. 34
Figure 3‑2 NuMicro® Nano100 LQFP 128-pin Diagram ................................................................ 37
Figure 3‑3 NuMicro® Nano100 LQFP 64-pin Diagram .................................................................. 38
Figure 3‑4 NuMicro® Nano100 LQFP 48-pin Diagram................................................................... 39
Figure 3‑5 NuMicro® Nano110 LQFP 128-pin Diagram................................................................. 40
Figure 3‑6 NuMicro® Nano110 LQFP 64-pin Diagram................................................................... 41
Figure 3‑7 NuMicro® Nano120 LQFP 128-pin Diagram................................................................. 42
Figure 3‑8 NuMicro® Nano120 LQFP 64-pin Diagram................................................................... 43
Figure 3‑9 NuMicro® Nano120 LQFP 48-pin Diagram................................................................... 44
Figure 3‑10 NuMicro® Nano130 LQFP 128-pin Diagram............................................................... 45
Figure 3‑11 NuMicro® Nano130 LQFP 64-pin Diagram................................................................. 46
Figure 4‑1 NuMicro® Nano100 Block Diagram .............................................................................. 97
Figure 4‑2 NuMicro® Nano110 Block Diagram .............................................................................. 98
Figure 4‑3 NuMicro® Nano120 Block Diagram .............................................................................. 99
Figure 4‑4 NuMicro® Nano130 Block Diagram ............................................................................ 100
Figure 6‑1 M0 Functional Block................................................................................................... 129
Figure 9‑1 Typical Crystal Application Circuit.............................................................................. 145
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LIST OF TABLES
Table 1‑1 Connectivity Support Table ............................................................................................. 9
Table 3‑1 Nano100 Base Line Selection Table............................................................................. 35
Table 3‑2 Nano110 LCD Line Selection Table.............................................................................. 35
Table 3‑3 Nano120 USB Connectivity Line Selection Table......................................................... 35
Table 3‑4 Nano130 Advanced Line Selection Table..................................................................... 36
Table 5‑12 UART Baud Rate Equation ....................................................................................... 123
Table 5‑13 UART Baud Rate Setting .......................................................................................... 124
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1
GENERAL DESCRIPTION
The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM® Cortex™-M0
core operated at a wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with
32K/64K/128K bytes embedded Flash and 8K/16K-byte embedded SRAM. Integrating LCD 4x40
or 6x38 (COM/Segment), USB 2.0 full-speed function, RTC, 12-bit SAR ADC, 12-bit DAC and
provides high performance connectivity peripheral interfaces such as UART, SPI, I2C, I2S, GPIOs,
EBI (External Bus Interface) for external memory-mapped device access and ISO-7816-3 for
Smart card, the Nano100 series supports Brown-out Detector, Power-down mode with RAM
retention and fast wake-up via many peripheral interfaces.
The Nano100 series provides low power voltage, low power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost
32-bit microcontrollers. The Nano100 series is suitable for a wide range of battery device
applications such as:
Portable Data Collector
Portable Medical Monitor
Portable RFID Reader
Portable Barcode Scanner
Security Alarm System
System Supervisors
Power Metering
USB Accessories
Smart Card Reader
Wireless Game Control Device
IPTV Remote Smart Keyboard
Wireless Sensors Node Device (WSN)
Wireless RF4CE Remote Control
Wireless Audio
Wireless Automatic Meter Reader (AMR)
Electronic Toll Collection (ETC)
The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM®
Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz
frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates RTC, 12- channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high
performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI
(External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart
card. The Nano100 Base line supports Brown-out Detector, Power-down mode with RAM
retention and fast wake-up via many peripheral interfaces.
The Nano110 LCD line, an ultra-low power 32-bit microcontroller with the embedded ARM®
Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz
frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates LCD 4x40 or 6x38 (COM/Segment). RTC, 12-channels 12-bit SAR ADC, 2-channels
12-bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART,
2xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and 3xISO-7816-3 for Smart card. The Nano110 LCD line supports Brown-out Detector,
Power-down mode with RAM retention and fast wake-up via many peripheral interfaces.
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The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded
ARM® Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42
MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates USB 2.0 full-speed device function, RTC, 12-channels12-bit SAR ADC, 2-channels 12-
bit DAC and provides high performance connectivity peripheral interfaces such as 2xUART,
3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and 3xISO-7816-3 for Smart card. The Nano120 USB Connectivity line supports Brown-
out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral
interfaces.
The Nano130 Advanced line, an ultra-low power 32-bit microcontroller with the embedded ARM®
Cortex™-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz
frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrated LCD 4x40 or 6x38 (COM/Segment), USB 2.0 full-speed device function, RTC, 8-
channels 12-bit SAR ADC, 2-channels 12-bit DAC and provides high performance connectivity
peripheral interfaces such as 2xUART, 2xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for
external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano130
Advanced line supports Brown-out Detector, Power-down mode with RAM retention and fast
wake-up via many peripheral interfaces.
Product Line UART SPI I2C I2S USB LCD ADC DAC RTC EBI SC Timer
Nano100
Nano110
Nano120
Nano130
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Table 1‑1 Connectivity Support Table
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2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 Nano100 Features – Base Line
Core
ARM® Cortex™-M0 core running up to 42 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access
64K/32K/123K bytes application program memory (APROM)
4 KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on-chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports DMA mode
DMA: Supports 8 channels: one VDMA channel, 6 PDMA channels and one CRC
channel
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
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Supports address direction: increment, fixed, and wrap around
CRC
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
Clock Control
Flexible selection for different applications
Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all
temperarure range.
Low power 10 kHz OSC for watchdog and low power system operation
Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports High Driver and High Sink I/O mode
Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~ PC.7
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit
pre-scale counter
Independent Clock Source for each timer
Provides one-shot,periodic, output toggle and continuous operation modes
Internal trigger event to ADC, DAC and PDMA
Supports PDMA mode
Wake system up from Power-down mode
Watchdog Timer
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
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Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable when watchdog time-out
Wake system up from Power-down mode
Window Watchdog Timer(WWDT)
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down mode
Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM modules, each has two 16-bit PWM generators
Provides eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM
(Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
Supports One-shot and Continuous mode
Supports Capture interrupt
UART
SPI
Up to two 16-byte FIFO UART controllers
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control.
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down mode
Up to three sets of SPI controller
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Master up to 32 MHz, and Slave up to 16 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is used as the master, and 1
slave/device select line when SPI controller is used as the slave
I2C
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire mode, no slave select signal, bi-direction interface
Wake system up from Power-down mode
Up to two sets of I2C device
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
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12-bit SAR ADC up to 2Msps conversion rate
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3)
Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
Temperature sensor, AVDD, and AVSS.
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion started by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
DAC
12-bit monotonic output with 400K conversion rate
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Synchronized update capability for two DACs (group function)
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3),
software or PDMA to trigger DAC to conversion
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separates receive/transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit time-out counters for Answer to Reset (ATR) and waiting
times processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART mode (Half Duplex)
EBI (External bus interface) support
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Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8bit/16bit data width
Supports byte write in 16-bit Data Width mode
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
128-bit unique customer ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 48-pin(7x7)
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2.2 Nano110 Features – LCD Line
Core
ARM® Cortex™-M0 core running up to 42 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access.
64K/32K/123K bytes application program memory (APROM)
4 KB In System Programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports DMA mode
DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
channel
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
CRC
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
Clock Control
Flexible selection for different applications
Built-in 12 MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all
temperarure range.
Low power 10 kHz OSC for watchdog and low power system operation
Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports High Driver and High Sink I/O mode
Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~
PC.7)
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-
scale counter
Independent Clock Source for each timer
Provides one-shot,periodic, output toggle and continuous operation modes
Internal trigger event to ADC, DAC and PDMA module
Supports PDMA mode
Wake system up from Power-down mode
Watchdog Timer
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable when watchdog time-out
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NUMICRO® NANO100 (B) DATASHEET
Wake system up from Power-down mode
Window Watchdog Timer(WWDT)
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down mode
Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM modules, each has two 16-bit PWM generators
Provides eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM
(Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
Supports Capture interrupt
UART
SPI
Up to two 16-byte FIFO UART controllers
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control (Low Density Only)
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down mode
Up to three sets of SPI controller
Master up to 32 MHz, and Slave up to 16 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
I2C
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire mode, no slave select signal, bi-direction interface
Wake system up from Power-down mode
Up to two sets of I2C device
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requestING the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address with mask option)
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC up to 2Msps conversion rate
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3)
Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
Temperature sensor, AVDD, and AVSS
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion start by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2, and TMR3) to
enable ADC
DAC
12-bit monotonic output with 400K conversion rate
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Synchronized update capability for two DACs (group function)
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3),
software or PDMA to trigger DAC to conversion
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separates receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting
times processing
LCD
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART mode (Half Duplex)
LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
Supports Static,1/2 bias and 1/3 bias voltage
Four display modes; Static, 1/2 duty, 1/3 duty,1/4 duty, 1/5 duty and 1/6 duty.
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
Selectable LCD frequency by frequency divider
Configurable frame frequency
Internal Charge pump, adjustable contrast adjustment
Configurable Charge pump frequency
Blinking capability
Supports R-type/C-type method
LCD frame interrupt
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
128-bit unique customer ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 128-pin(14x14) / 64-pin(10x10) / 64-pin(7x7)
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
2.3 Nano120 Features – USB Connectivity Line
Core
ARM® Cortex™-M0 core running up to 42 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access.
64K/32K/123K bytes application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports PDMA mode
DMA: Support 8 channels: one VDMA channel, 6 PDMA channels, and one CRC
channel
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address: increment, fixed, and wrap around
CRC
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
Clock Control
Flexible selection for different applications
Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all
temperarure range
Low power 10 kHz OSC for watchdog and low power system operatin
Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin can be configured as interrupt source with edge/level setting
High driver and high sink IO mode support
Supports input 5V tolerance (except ADC and DAC shared pins)
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-
scale counter
Independent Clock Source for each timer
Provides one-shot,periodic, output toggle and continuous operation modes
Internal trigger event to ADC, DAC and PDMA module
Supports PDMA mode
Wake system up from Power-down mode
Watchdog Timer
Clock Source from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable on watchdog time-out
Wake system up from Power-down mode
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Window Watchdog Timer(WWDT)
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down or Idle mode
Support 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM module, each has two 16-bit PWM generators
Provide eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-Zone generator for complementary paired PWM
(Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
Supports one shot and continuous mode
Supports Capture interrupt
UART
SPI
Up to two 16-byte FIFO UART controllers
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control. (Low Density Only)
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down mode
Up to three sets of SPI controller
Master up to 32 MHz, and Slave up to 16 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
I2C
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire, no slave select signal, bi-direction interface
Wake system up from Power-down mode
Up to two sets of I2C device
Master/Slave up to 1Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC up to 2Msps conversion rate
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~
PD.3).
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
Temperature sensor, AVDD, and AVSS.
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD
Supports single scan, single cycle scan, and continuous scan modes
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion start by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
DAC
12-bit monotonic output with 400K conversion rate
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Synchronized update capability for two DACs (group function)
Supports up to four timer time-out event (TMR0, TMR1, TMR2 and TMR3),
software or PDMA to trigger DAC to conversion
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separates receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting
times processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART mode (Half Duplex)
USB 2.0 Full-Speed Device
One set of USB 2.0 FS Device 12 Mbps
On-chip USB Transceiver
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
EBI (External bus interface) support
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8bit/16bit data width
Supports byte write in 16-bit Data Width mode
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
128-bit unique customer ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7)
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
2.4 Nano130 Features – Advanced Line
Core
ARM® Cortex™-M0 core running up to 42 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access.
64K/32K/123K bytes application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports DMA mode
DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
egiste
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-
memory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
CRC
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
Clock Control
Flexible selection for different applications
Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12 MHz OSC has 2 % deviation within all
temperarure range.
Low power 10 kHz OSC for watchdog and low power system operation
Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports High Driver and High Sink I/O mode
Supports input 5V tolerance (except ADC and DAC shared pins)
Timer
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale
counter
Independent Clock Source for each timer
Provides one-shot,periodic, output toggle and continuous operation modes
Supports internal trigger event to ADC, DAC and PDMA module
Wake system up from Power-down mode
Watchdog Timer
Clock Source is from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6ms ~ 26sec (depends on clock source)
Interrupt or reset selectable on watchdog time-out
WDT can wake system up from Power-down mode
Window Watchdog Timer(WWDT)
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC
Supports software compensation by setting frequency compensate register
(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down or Idle mode
Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM module, each with two 16-bit PWM generators
Provides eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-Zone generator for complementary paired PWM
(Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
Supports Capture interrupt
UART
Up to two 16-byte FIFO UART controllers
SPI
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control (Low Density Only)
Programmable baud rate generator
Supports PDMA mode
Wake system up from Power-down or Idle mode
Up to 3 sets of SPI controller
Master up to 32 MHz, and Slave up to 16 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when used as the master, and 1 slave/device
select line when used as the slave
I2C
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA request, one for transmit and another for receive
Supports three wire, no slave select signal, bi-direction interface
Wake system up from Power-down or Idle mode
Up to two sets of I2C device
Master/Slave up to 1Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus
Serial clock synchronization can be used as a handshake mechanism to
suspend and resume serial transfer
Built-in 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
I2S
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
Generates interrupt requests when buffer levels cross a programmable
boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC up to 2Msps conversion rate
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3)
Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
Temperature sensor, AVDD, and AVSS.
Supports three reference voltage sources from VREF pin, internal reference
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
voltage (Int_VREF), and AVDD
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection (comparator function)
Conversion start by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
DAC
12-bit monotonic output with 400K conversion rate
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Synchronized update capability for two DACs (group function)
Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3),
software or PDMA to trigger DAC to conversion
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separates receive/transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit time-out counter for Answer to Reset (ATR) and waiting
times processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card is
removed
Support UART mode (Half Duplex)
LCD
LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
Supports Static,1/2 bias and 1/3 bias voltage
Four display modes: Static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty.
Selectable LCD frequency by frequency divider
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Configurable frame frequency
Internal Charge pump, adjustable contrast adjustment
Configurable Charge pump frequency
Blinking capability
Supports R-type/C-type method
LCD frame interrupt
USB 2.0 Full-speed Device
One set of USB 2.0 FS Device 12 Mbps
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
EBI (External bus interface)
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8bit/16bit data width
Supports byte write in 16-bit data width mode
One built-in temperature sensor with 1℃ resolution
96-bit unique ID
128-bit unique customer ID
Operating Temperature: -40℃~85℃
Packages:
All Green package (RoHS)
LQFP 128-pin(14x14) / 64-pin (7x7)
May 31, 2016
Page 33 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3
PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro® Nano100 Series Selection Code
NANO 1 X X - X X X B N
Ultra-Low Power MCU
CPU core
Temperature
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
1: Cortex-M0
5/7: ARM7
9: ARM9
Version
A : Version
B : Version
Product Line Function
SRAM Size
0 : 2KB
1 : 4KB
2 : 8KB
3 : 16KB
0: Base Line
1: LCD Line
2: USB Connectivity Line
3: LCD + USB Connectivity Line
Flash ROM
A: 8KB
B: 16KB
C: 32KB
D: 64KB
E: 128KB
Reserved
0 ~ 9 Sub Product Line
Package Type
N : QFN48 (7x7 mm)
L : LQFP 48 (7x7 mm)
R : LQFP 64 (10x10 mm)
S : LQFP 64 (7x7 mm)
K : LQFP 128 (14x14 mm)
Figure 3‑1 NuMicro® Nano100 Series Selection Code
May 31, 2016
Page 34 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.2 NuMicro® Nano100 Products Selection Guide
3.2.1 NuMicro® Nano100 Base Line Selection Guide
Connectivity
ISP
ROM
(Kbytes)
ICP
IRC
Operating
Temp.
Range (°C )
Flash
(Kbytes) (Kbytes)
SRAM
Data Flash
(Kbytes)
Timer
(32-bit)
PWM
S
(16-bit) (12-bit)
ADC
DAC
(12-bit)
I2
Part No.
I/O
RTC EBI PDMA
LCD
ISO-7816-3* ISP 10KHz Package
IAP 12MHz
I2
C
UART* SPI
USB
NANO100NC2BN
NANO100ND2BN
NANO100ND3BN
NANO100NE3BN
NANO100LC2BN
NANO100LD2BN
NANO100LD3BN
NANO100LE3BN
NANO100SC2BN
NANO100SD2BN
NANO100SD3BN
NANO100SE3BN
NANO100KD3BN
NANO100KE3BN
32
64
64
128
32
64
64
128
32
64
64
8
8
16
16
8
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4
4
4
4
4
4
4
4
4
4
4
4
4
4
38
38
38
38
38
38
38
38
52
52
52
52
86
86
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2+2
2+2
2+2
2+2
2+2
2+2
2+2
2+2
2+3
2+3
2+3
2+3
2+3
2+3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
6
6
6
6
6
6
6
6
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
7
7
7
12
12
√
√
√
√
√
√
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
-
-
-
-
-
√
√
8
8
8
8
8
8
8
8
8
8
8
8
8
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
QFN48
QFN48
QFN48
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
QFN48
LQFP48
LQFP48
LQFP48
LQFP48
LQFP64*
LQFP64*
LQFP64*
LQFP64*
8
16
16
8
8
16
16
16
16
128
64
128
LQFP128 -40 to +85
LQFP128 -40 to +85
*Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART.
*ISO-7816 UART supports half duplex mode.
LQFP64*:7X7mm
Table 3‑1 Nano100 Base Line Selection Table
3.2.2 NuMicro® Nano110 LCD Line Selection Guide
Connectivity
(32-bit) UART* SPI
ISP
ROM
(Kbytes)
ICP
IRC
Operating
Temp.
Range (°C )
Flash
(Kbytes) (Kbytes)
SRAM
Data Flash
(Kbytes)
Timer
PWM
S
(16-bit) (12-bit)
ADC
DAC
(12-bit)
I2
Part No.
I/O
RTC EBI PDMA
LCD
ISO-7816-3* ISP 10KHz Package
IAP 12MHz
I2
C
USB
NANO110SC2BN
NANO110SD2BN
NANO110SD3BN
NANO110SE3BN
NANO110RC2BN
NANO110RD2BN
NANO110RD3BN
NANO110RE3BN
NANO110KC2BN
NANO110KD2BN
NANO110KD3BN
NANO110KE3BN
32
64
64
128
32
64
64
128
32
64
64
8
8
16
16
8
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4
4
4
4
4
4
4
4
4
4
4
4
51
51
51
51
51
51
51
51
86
86
86
86
4
4
4
4
4
4
4
4
4
4
4
4
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
3
3
3
3
3
3
3
3
3
3
3
3
2
-
-
-
-
-
-
-
-
-
-
-
-
1
7
7
7
7
7
7
7
7
8
8
8
8
7
7
7
7
7
7
7
7
12
12
12
12
√
√
√
√
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
-
√
√
√
√
8
8
8
8
8
8
8
8
8
8
8
8
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x40, 6x38
4x40, 6x38
4x40, 6x38
4x40, 6x38
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP64*
LQFP64*
LQFP64*
LQFP64*
LQFP64
LQFP64
LQFP64
LQFP64
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
8
16
16
8
8
16
16
128
*Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART.
*ISO-7816 UART supports half duplex mode.
LQFP64*:7X7mm
Table 3‑2 Nano110 LCD Line Selection Table
3.2.3 NuMicro® Nano120 USB Connectivity Line Selection Guide
Connectivity
(32-bit) UART* SPI
ISP
ROM
(Kbytes)
ICP
IRC
Operating
Temp.
Range (°C )
Flash
(Kbytes) (Kbytes)
SRAM
Data Flash
(Kbytes)
Timer
PWM
S
(16-bit) (12-bit)
ADC
DAC
(12-bit)
I2
Part No.
I/O
RTC EBI PDMA
LCD
ISO-7816-3* ISP 10KHz Package
IAP 12MHz
I2
C
USB
NANO120LC2BN
NANO120LD2BN
NANO120LD3BN
NANO120LE3BN
NANO120SC2BN
NANO120SD2BN
NANO120SD3BN
NANO120SE3BN
NANO120KD3BN
NANO120KE3BN
32
64
64
128
32
64
64
128
64
8
8
16
16
8
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4
4
4
4
4
4
4
4
4
4
34
34
34
34
48
48
48
48
86
86
4
4
4
4
4
4
4
4
4
4
2+2
2+2
2+2
2+2
2+3
2+3
2+3
2+3
2+3
2+3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
8
8
8
8
8
8
7
7
7
7
7
7
7
7
8
8
√
√
√
√
√
√
√
√
√
√
-
-
-
-
-
-
-
-
√
√
8
8
8
8
8
8
8
8
8
8
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP48
LQFP48
LQFP48
LQFP48
LQFP64*
LQFP64*
LQFP64*
LQFP64*
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
8
16
16
16
16
LQFP128 -40 to +85
LQFP128 -40 to +85
128
*Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART.
*ISO-7816 UART supports half duplex mode.
LQFP64*:7X7mm
Table 3‑3 Nano120 USB Connectivity Line Selection Table
May 31, 2016
Page 35 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.2.4 NuMicro® Nano130 Advanced Line Selection Guide
Connectivity
(32-bit) UART* SPI
ISP
ROM
(Kbytes)
ICP
IRC
Operating
Temp.
Range (°C )
Flash
(Kbytes) (Kbytes)
SRAM
Data Flash
(Kbytes)
Timer
PWM
S
(16-bit) (12-bit)
ADC
DAC
(12-bit)
I2
Part No.
I/O
RTC EBI PDMA
LCD
ISO-7816-3* ISP 10KHz Package
IAP 12MHz
I2
C
USB
NANO130SC2BN
NANO130SD2BN
NANO130SD3BN
NANO130SE3BN
NANO130KC2BN
NANO130KD2BN
NANO130KD3BN
NANO130KE3BN
32
64
64
128
32
64
8
8
16
16
8
8
16
16
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
Configurable
4
4
4
4
4
4
4
4
47
47
47
47
86
86
86
86
4
4
4
4
4
4
4
4
2+3
2+3
2+3
2+3
2+3
2+3
2+3
2+3
3
3
3
3
3
3
3
3
2
1
1
1
1
1
1
1
1
1
7
7
7
7
8
8
8
8
7
7
7
7
8
8
8
8
√
√
√
√
√
√
√
√
-
-
-
8
8
8
8
8
8
8
8
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x31, 6x29
4x40, 6x38
4x40, 6x38
4x40, 6x38
4x40, 6x38
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP64*
LQFP64*
LQFP64*
LQFP64*
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2
2
2
2
2
2
2
1
1
1
1
1
1
1
-
√
√
√
√
64
128
*Marked in the table (2+3) means 2 UART+ 3 ISO-7816 UART.
*ISO-7816 UART supports half duplex mode.
LQFP64*:7X7mm
Table 3‑4 Nano130 Advanced Line Selection Table
May 31, 2016
Page 36 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3 Pin Configuration
3.3.1 NuMicro® Nano100 Pin Diagrams
3.3.1.1 NuMicro® Nano100 LQFP 128-pin
97
98
99
VREF
NC
64
63
62
61
60
59
58
PB.9
PB.10
PB.11
PE.5
NC
AVDD
AD8/PD.0
AD9/PD.1
AD10/PD.2
AD11/PD.3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
PE.6
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PD.15
PD.14
PD.7
PD.6
PB.3
PB.2
PB.1
PB.0
NC
PD.4
PD.5
PC.7
PC.6
PC.15
PC.14
PB.15
NC
NANO100
LQFP 128-pin
XT1_IN
XT1_OUT
NC
nRESET
VSS
VSS
NC
NC
VDD
NC
NC
NC
PF.4
NC
PF.5
PE.7
PE.8
PE.9
PE.10
PE.11
PE.12
VSS
PVSS
PB.8
PE.15
PE.14
Figure 3‑2 NuMicro® Nano100 LQFP 128-pin Diagram
May 31, 2016
Page 37 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.1.2 NuMicro® Nano100 LQFP 64-pin
AD5/PA.5
AD6/PA.6
VREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PD.15
PD.14
PD.7
PD.6
PB.3
PB.2
PB.1
PB.0
AVDD
PC.7
PC.6
PC.15
PC.14
PB.15
XT1_IN
XT1_OUT
nRESET
VSS
NANO100
LQFP 64-pin
VDD
PVSS
PB.8
Figure 3‑3 NuMicro® Nano100 LQFP 64-pin Diagram
May 31, 2016
Page 38 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.1.3 NuMicro® Nano100 LQFP/QFN 48-pin
AD5/PA.5
AD6/PA.6
VREF
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PB.9
PB.10
PB.11
PE.5
PC.0
PC.1
PC.2
PC.3
PB.3
PB.2
PB.1
PB.0
AVDD
PC.7
PC.6
NANO100
LQFP/QFN 48-pin
PB.15
XT1_IN
XT1_OUT
nRESET
PVSS
PB.8
Figure 3‑4 NuMicro® Nano100 LQFP 48-pin Diagram
May 31, 2016
Page 39 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.2 NuMicro® Nano110 Pin Diagrams
3.3.2.1 NuMicro® Nano110 LQFP 128-pin
97
98
99
VREF
64
63
62
61
60
59
58
PB.9/LCD_V3
PB.10/LCD_V2
PB.11/LCD_V1
PE.5
NC
AVDD
AD8/PD.0
AD9/PD.1
AD10/PD.2
AD11/PD.3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
VLCD
PE.6
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC.0/LCD_DH1
PC.1/LCD_DH2
PC.2/LCD_COM0
PC.3/LCD_COM1
PC.4/LCD_COM2
PC.5/LCD_COM3
PD.15/LCD_SEG0(COM4)
PD.14/LCD_SEG1(COM5)
PD.7/LCD_SEG2
PD.6/LCD_SEG3
PB.3/LCD_SEG4
PB.2/LCD_SEG5
PB.1/LCD_SEG6
PB.0/LCD_SEG7
NC
LCD_SEG35/PD.4
LCD_SEG34/PD.5
PC.7
PC.6
LCD_SEG33/PC.15
LCD_SEG32/PC.14
LCD_SEG31/PB.15
NC
NANO110
LQFP 128-pin
XT1_IN
XT1_OUT
NC
nRESET
VSS
VSS
NC
NC
VDD
NC
NC
NC
PF.4
NC
PF.5
PE.7/LCD_SEG8
PE.8/LCD_SEG9
PE.9
VSS
PVSS
LCD_SEG30/PB.8
LCD_SEG29/PE.15
LCD_SEG28/PE.14
PE.10
PE.11
PE.12
Figure 3‑5 NuMicro® Nano110 LQFP 128-pin Diagram
May 31, 2016
Page 40 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.2.2 NuMicro® Nano110 LQFP 64-pin
LCD_SEG20/AD5/PA.5
LCD_SEG19/AD6/PA.6
VREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/LCD_V3
PB.10/LCD_V2
PB.11/LCD_V1
LCD_VLCD
AVDD
LCD_SEG17/PC.7
PC.6
PC.0/LCD_DH1
PC.1/LCD_DH2
PC.2/LCD_COM0
PC.3/LCD_COM1
PD.15
LCD_SEG16/PC.15
LCD_SEG15/PC.14
LCD_SEG14/PB.15
XT1_IN
Nano110
LQFP 64-pin
PD.14
XT1_OUT
PD.7
nRESET
PD.6
VSS
PB.3/LCD_COM2
PB.2/LCD_COM3
PB.1/LCD_SEG0(COM4)
PB.0/LCD_SEG1(COM5)
VDD
PVSS
LCD_SEG13/PB.8
Figure 3‑6 NuMicro® Nano110 LQFP 64-pin Diagram
May 31, 2016
Page 41 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.3 NuMicro® Nano120 Pin Diagrams
3.3.3.1 NuMicro® Nano120 LQFP 128-pin
97
98
99
VREF
NC
64
63
62
61
60
59
58
PB.9
PB.10
PB.11
PE.5
NC
AVDD
PD.0
PD.1
PD.2
PD.3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
PE.6
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC.0
PD.4
PD.5
PC.7
PC.6
PC.15
PC.14
PB.15
NC
PC.1
PC.2
PC.3
PC.4
PC.5
PD.15
PD.14
PD.7
NANO120
LQFP 128-pin
XT1_IN
XT1_OUT
NC
PD.6
PB.3
PB.2
nRESET
VSS
PB.1
PB.0
VSS
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS
NC
NC
VDD
NC
PF.4
PF.5
PE.7
VSS
PE.8
PVSS
PB.8
PE.9
PE.10
PE.11
PE.12
PE.15
PE.14
Figure 3‑7 NuMicro® Nano120 LQFP 128-pin Diagram
May 31, 2016
Page 42 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.3.2 NuMicro® Nano120 LQFP 64-pin
PA.5
PA.6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9
PB.10
VREF
AVDD
PC.7
PB.11
PE.5
PC.0
PC.6
PC.1
PC.15
PC.14
PB.15
XT1_IN
XT1_OUT
nRESET
VSS
PC.2
PC.3
NANO120
LQFP 64-pin
PB.3
PB.2
PB.1
PB.0
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS
VDD
PVSS
PB.8
Figure 3‑8 NuMicro® Nano120 LQFP 64-pin Diagram
May 31, 2016
Page 43 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.3.3 NuMicro® Nano120 LQFP 48-pin
PC.0
PA.5
PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.1
PC.2
VREF
PC.3
AVDD
PC.7
PB.3
PB.2
PC.6
NANO120
LQFP 48-pin
PB.1
PB.15
XT1_IN
XT1_OUT
nRESET
PVSS
PB.0
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS
PB.8
Figure 3‑9 NuMicro® Nano120 LQFP 48-pin Diagram
May 31, 2016
Page 44 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.4 NuMicro® Nano130 Pin Diagrams
3.3.4.1 NuMicro® Nano130 LQFP 128-pin
97
98
99
VREF
64
63
62
61
60
59
58
PB.9/LCD_V3
PB.10/LCD_V2
PB.11/LCD_V1
PE.5
NC
AVDD
AD8/PD.0
AD9/PD.1
AD10/PD.2
AD11/PD.3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
VLCD
PE.6
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC.0/LCD_DH1
PC.1/LCD_DH2
PC.2/LCD_COM0
PC.3/LCD_COM1
PC.4/LCD_COM2
PC.5/LCD_COM3
PD.15/LCD_SEG0(COM4)
PD.14/LCD_SEG1(COM5)
PD.7/LCD_SEG2
PD.6/LCD_SEG3
PB.3/LCD_SEG4
PB.2/LCD_SEG5
PB.1/LCD_SEG6
PB.0/LCD_SEG7
USB_D+
LCD_SEG35/PD.4
LCD_SEG34/PD.5
PC.7
PC.6
LCD_SEG33/PC.15
LCD_SEG32/PC.14
LCD_SEG31/PB.15
NC
NANO130
LQFP 128-pin
XT1_IN
XT1_OUT
NC
nRESET
VSS
VSS
NC
USB_D-
VDD
USB_VDD33_CAP
USB_VBUS
NC
PF.4
NC
PF.5
PE.7/LCD_SEG8
PE.8/LCD_SEG9
PE.9
VSS
PVSS
LCD_SEG30/PB.8
LCD_SEG29/PE.15
LCD_SEG28/PE.14
PE.10
PE.11
PE.12
Figure 3‑10 NuMicro® Nano130 LQFP 128-pin Diagram
May 31, 2016
Page 45 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.3.4.2 NuMicro® Nano130 LQFP 64-pin
LCD_SEG20/AD5/PA.5
LCD_SEG19/AD6/PA.6
VREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/LCD_V3
PB.10/LCD_V2
PB.11/LCD_V1
VLCD
AVDD
LCD_SEG17/PC.7
PC.6
PC.0/LCD_DH1
PC.1/LCD_DH2
PC.2/LCD_COM0
PC.3/LCD_COM1
PB.3/LCD_COM2
PB.2/LCD_COM3
PB.1/LCD_SEG0(COM4)
PB.0/LCD_SEG1(COM5)
USB_D+
LCD_SEG16/PC.15
LCD_SEG15/PC.14
LCD_SEG14/PB.15
XT1_IN
Nano130
LQFP 64-pin
XT1_OUT
nRESET
VSS
VDD
USB_D-
PVSS
USB_VDD33_CAP
USB_VBUS
LCD_SEG13/PB.8
Figure 3‑11 NuMicro® Nano130 LQFP 64-pin Diagram
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.4 Pin Description
3.4.1 NuMicro® Nano100 Pin Description
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I/O
I/O
I
1
PE.13
General purpose digital I/O pin
General purpose digital I/O pin
External interrupt0 input pin
SmartCard2 card detect pin
SPI2 2nd slave select pin
General purpose digital I/O pin
EBI Address/Data bus bit1
General purpose digital I/O pin
EBI Address/Data bus bit0
Frequency Divider output pin
NC
PB.14
INT0
2
1
I
SC2_CD
SPI2_SS1
PB.13
I/O
I/O
I/O
I/O
I/O
O
3
4
2
3
EBI_AD1
PB.12
1
EBI_AD0
FCLKO
5
6
7
8
O
I
4
5
2
3
X32O
X32I
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
NC
I/O
I/O
O
PA.11
General purpose digital I/O pin
I2C1 clock pin
I2C1_SCL
EBI_nRD
SC0_RST
SPI2_MOSI0
PA.10
9
6
4
EBI read enable output pin
SmartCard0 RST pin
O
SPI2 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
I2C1 data I/O pin
I/O
I/O
I/O
O
I2C1_SDA
EBI_nWR
SC0_PWR
SPI2_MISO0
PA.9
10
7
8
5
6
EBI write enable output pin
SmartCard0 Power pin
O
SPI2 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
I2C0 clock pin
I/O
I/O
I/O
I/O
I/O
I2C0_SCL
SC0_DAT
SPI2_CLK
11
SmartCard0 DATA pin(SC0_UART_RXD)
SPI2 serial clock pin
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I/O
I/O
O
PA.8
General purpose digital I/O pin
I2C0 data I/O pin
I2C0_SDA
SC0_CLK
SPI2_SS0
PD.8
12
9
7
SmartCard0 clock pin(SC0_UART_TXD)
SPI2 1st slave select pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
13
14
15
16
17
18
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
UART1_RXD
SC0_CD
SPI2_SS0
PB.5
19
20
21
22
10
11
12
8
9
I
I/O
I/O
O
General purpose digital I/O pin
UART1 Data transmitter output pin
SmartCard0 RST pin
UART1_TXD
SC0_RST
SPI2_CLK
PB.6
O
I/O
I/O
O
SPI2 serial clock pin
General purpose digital I/O pin
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
NC
UART1_RTSn
EBI_ALE
SPI2_MISO0
PB.7
O
I/O
I/O
I
UART1_CTSn
EBI_nCS
SPI2_MOSI0
13
14
O
I/O
23
24
25
26
P
10
LDO_CAP
LDO output pin
NC
NC
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
P
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
15
16
11
VDD
Power supply for I/O ports and LDO source
NC
P
12
VSS
Ground
P
VSS
Ground
P
VSS
Ground
P
VSS
Ground
I/O
I/O
I/O
I/O
I/O
I/O
PE.12
PE.11
PE.10
PE.9
PE.8
PE.7
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
NC
NC
NC
NC
NC
I/O
I
PB.0
General purpose digital I/O pin
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
UART0 Request to Send output pin
EBI low byte write enable output pin
SPI1 serial clock pin
44
45
17
18
13
14
UART0_RXD
SPI1_MOSI0
PB.1
I/O
I/O
O
UART0_TXD
SPI1_MISO0
PB.2
I/O
I/O
O
UART0_RTSn
EBI_nWRL
SPI1_CLK
PB.3
46
19
20
15
16
O
I/O
I/O
I
General purpose digital I/O pin
UART0 Clear to Send input pin
EBI high byte write enable output pin
47
UART0_CTSn
EBI_nWRH
O
May 31, 2016
Page 49 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
SPI1_SS0
PD.6
SPI1 1st slave select pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
48
49
50
51
21
22
23
24
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
SPI0 2nd MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
SPI0 2nd MISO (Master In, Slave Out) pin
General purpose digital I/O pin
SPI0 1st MOSI (Master Out, Slave In) pin
I2S data output
PD.7
PD.14
PD.15
PC.5
52
53
SPI0_MOSI1
PC.4
SPI0_MISO1
PC.3
SPI0_MOSI0
I2S_DO
SC1_RST
PC.2
54
55
56
25
26
27
17
18
19
O
SmartCard1 RST pin
I/O
I/O
I
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
SPI0_MISO0
I2S_DI
O
SC1_PWR
PC.1
SmartCard1 PWR pin
I/O
I/O
I/O
I/O
General purpose digital I/O pin
SPI0 serial clock pin
SPI0_CLK
I2S_BCLK
SC1_DAT
I2S bit clock pin
SmartCard1 DATA pin(SC1_UART_RXD)
General purpose digital I/O pin / Module
clock output pin
I/O
PC.0 / MCLKO
I/O
I/O
O
SPI0_SS0
I2S_LRCLK
SC1_CLK
PE.6
SPI0 1st slave select pin
I2S left right channel clock
SmartCard1 clock pin(SC1_UART_TXD)
General purpose digital I/O pin
NC
57
28
20
I/O
58
59
60
NC
I/O
I/O
PE.5
General purpose digital I/O pin
PWM1 Channel1 output
61
29
21
PWM1_CH1
May 31, 2016
Page 50 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I/O
I/O
O
PB.11
General purpose digital I/O pin
PWM1 Channel0 output
PWM1_CH0
TM3
62
63
64
30
31
32
22
Timer3 external counter input
SmartCard2 DATA pin(SC2_UART_RXD)
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
SPI0 2nd slave select pin
I/O
I/O
I/O
I/O
O
SC2_DAT
SPI0_MISO0
PB.10
SPI0_SS1
TM2
23
Timer2 external counter input
SmartCard2 clock pin(SC2_UART_TXD)
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
SPI1 2nd slave select pin
O
SC2_CLK
SPI0_MOSI0
PB.9
I/O
I/O
I/O
O
SPI1_SS1
TM1
24
Timer1 external counter input
SmartCard2 RST pin
O
SC2_RST
INT0
I
External interrupt0 input pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PE.4
General purpose digital I/O pin
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
SPI0 serial clock pin
65
66
67
SPI0_MOSI0
PE.3
SPI0_MISO0
PE.2
SPI0_CLK
PE.1
General purpose digital I/O pin.
PWM1 Channel3 output
68
69
70
PWM1_CH3
SPI0_SS0
PE.0
SPI0 1st slave select pin
General purpose digital I/O pin
PWM1 Channel2 output
PWM1_CH2
I2S_MCLK
PC.13
I2S master clock output pin
I/O
I/O
O
General purpose digital I/O pin
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
SPI1_MOSI1
PWM1_CH1
May 31, 2016
Page 51 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I
SNOOPER
INT1
Snooper pin
I
External interrupt 1
O
I2C0_SCL
PC.12
I2C0 clock pin
I/O
I/O
O
General purpose digital I/O pin
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel0 output
SPI1_MISO1
PWM1_CH0
INT0
71
I
External interrupt0 input pin
I2C0 data I/O pin
I/O
I/O
I/O
O
I2C0_SDA
PC.11
General purpose digital I/O pin
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
General purpose digital I/O pin
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
General purpose digital I/O pin
SPI1 serial clock pin
72
73
74
33
34
35
SPI1_MOSI0
UART1_TXD
PC.10
I/O
I/O
I
SPI1_MISO0
UART1_RXD
PC.9
I/O
I/O
I/O
I/O
I/O
O
SPI1_CLK
I2C1_SCL
PC.8
I2C1 clock pin
General purpose digital I/O pin
SPI1 1st slave select pin
SPI1_SS0
EBI_MCLK
I2C1_SDA
PA.15
75
36
EBI external clock output pin
I2C1 data I/O pin
I/O
I/O
I/O
O
General purpose digital I/O pin
PWM0 Channel3 output
PWM0_CH3
I2S_MCLK
TC3
I2S master clock output pin
Timer3 capture input
76
37
38
25
26
I
O
SC0_PWR
UART0_TXD
PA.14
SmartCard0 Power pin
O
UART0 Data transmitter output pin
General purpose digital I/O pin
PWM0 Channel2 output
I/O
I/O
I/O
77
PWM0_CH2
EBI_AD15
EBI Address/Data bus bit15
May 31, 2016
Page 52 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I
TC2
Timer2 capture input
I
UART0_RXD
PA.13
UART0 Data receiver input pin
General purpose digital I/O pin
PWM0 Channel1 output
EBI Address/Data bus bit14
Timer1 capture input
I/O
I/O
I/O
I
PWM0_CH1
EBI_AD14
TC1
78
39
27
I/O
I/O
I/O
I/O
I
I2C0_SCL
PA.12
I2C0 clock pin
General purpose digital I/O pin
PWM0 Channel0 output
EBI Address/Data bus bit13
Timer0 capture input
PWM0_CH0
EBI_AD13
TC0
79
40
28
I/O
I/O
I/O
I
I2C0_SDA
ICE_DAT
PF.0
I2C0 data I/O pin
Serial Wired Debugger Data pin
General purpose digital I/O pin
External interrupt0 input pin
Serial Wired Debugger Clock pin
General purpose digital I/O pin
Frequency Divider output pin
External interrupt1 input pin
NC
80
81
41
42
29
30
INT0
I
ICE_CLK
PF.1
I/O
O
FCLKO
INT1
I
82
83
Power supply for I/O ports and LDO source
for internal PLL and digital circuit
P
VDD
84
85
86
87
88
NC
P
P
VSS
Ground
VSS
Ground
AP
AP
I/O
AI
I
43
31
AVSS
AVSS
PA.0
Ground Pin for analog circuit
Ground Pin for analog circuit
General purpose digital I/O pin
ADC analog input0
SmartCard2 card detect
General purpose digital I/O pin
89
44
45
32
33
AD0
SC2_CD
PA.1
I/O
90
May 31, 2016
Page 53 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
AI
I/O
I/O
AI
I/O
I
AD1
ADC analog input1
EBI_AD12
PA.2
EBI Address/Data bus bit12
General purpose digital I/O pin
ADC analog input2
AD2
91
92
46
47
34
35
EBI_AD11
UART1_RXD
PA.3
EBI Address/Data bus bit11
UART1 Data receiver input pin
General purpose digital I/O pin
ADC analog input3
I/O
AI
I/O
O
AD3
EBI_AD10
UART1_TXD
PA.4
EBI Address/Data bus bit10
UART1 Data transmitter output pin
General purpose digital I/O pin
ADC analog input4
I/O
AI
I/O
O
AD4
93
48
36
EBI_AD9
SC2_PWR
I2C0_SDA
PA.5
EBI Address/Data bus bit9
SmartCard2 Power pin
I2C0 data I/O pin
I/O
I/O
AI
I/O
O
General purpose digital I/O pin
ADC analog input5
AD5
94
49
37
EBI_AD8
SC2_RST
I2C0_SCL
PA.6
EBI Address/Data bus bit8
SmartCard2 RST pin
I2C0 clock pin
I/O
I/O
AI
I/O
I
General purpose digital I/O pin
ADC analog input6
AD6
EBI_AD7
TC3
EBI Address/Data bus bit7
Timer3 capture input
95
50
38
O
SC2_CLK
PWM0_CH3
PA.7
SmartCard2 clock pin(SC2_UART_TXD)
PWM0 Channel3 output
General purpose digital I/O pin
ADC analog input7
O
I/O
AI
I/O
I
AD7
96
EBI_AD6
TC2
EBI Address/Data bus bit6
Timer2 capture input
May 31, 2016
Page 54 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I/O
O
SC2_DAT
PWM0_CH2
VREF
SmartCard2 DATA pin(SC2_UART_RXD)
PWM0 Channel2 output
AP
97
98
99
51
52
39
40
Voltage reference input for ADC
NC
AP
I/O
I
AVDD
Power supply for internal analog circuit
General purpose digital I/O pin
UART1 Data receiver input pin
SPI2 1st slave select pin
PD.0
UART1_RXD
SPI2_SS0
SC1_CLK
AD8
I/O
O
100
SmartCard1 clock pin(SC1_UART_TXD)
ADC analog input8
AI
I/O
O
PD.1
General purpose digital I/O pin
UART1 Data transmitter output pin
SPI2 serial clock pin
UART1_TXD
SPI2_CLK
SC1_DAT
AD9
I/O
I/O
AI
I/O
O
101
SmartCard1 DATA pin(SC1_UART_RXD).
ADC analog input9
PD.2
General purpose digital I/O pin
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
UART1_RTSn
I2S_LRCLK
SPI2_MISO0
SC1_PWR
AD10
I/O
I/O
O
102
AI
I/O
I
ADC analog input10
PD.3
General purpose digital I/O pin
UART1 Clear to Send input pin
I2S bit clock pin
UART1_CTSn
I2S_BCLK
SPI2_MOSI0
SC1_RST
AD11
I/O
I/O
O
103
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
AI
ADC analog input11
104
105
NC
I/O
I
PD.4
General purpose digital I/O pin
I2S data input
I2S_DI
May 31, 2016
Page 55 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
SPI2 2nd MISO (Master In, Slave Out) pin
I/O
SPI2_MISO1
SC1_CD
PD.5
I
I/O
O
SmartCard1 card detect
General purpose digital I/O pin
I2S data output
106
I2S_DO
SPI2_MOSI1
PC.7
SPI2 2nd MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
DAC 1 output
I/O
I/O
AO
I/O
I
DA1_OUT
EBI_AD5
TC1
107
53
41
EBI Address/Data bus bit5
Timer1 capture input
O
PWM0_CH1
PC.6
PWM1 Channel1 output
General purpose digital I/O pin
DAC0 output
I/O
I
DA0_OUT
EBI_AD4
TC0
I/O
I
EBI Address/Data bus bit4
Timer0 capture input
108
54
42
I
SC1_CD
PWM0_CH0
PC.15
SmartCard1 card detect pin
PWM0 Channel0 output
General purpose digital I/O pin
EBI Address/Data bus bit3
Timer0 capture input
O
I/O
I/O
I
EBI_AD3
TC0
109
110
111
55
56
57
O
PWM1_CH2
PC.14
PWM1 Channel1 output
General purpose digital I/O pin
EBI Address/Data bus bit2
PWM1 Channel3 output
General purpose digital I/O pin
External interrupt1 input pin
Snooper pin
I/O
I/O
I/O
I/O
I
EBI_AD2
PWM1_CH3
PB.15
INT1
43
44
I
SNOOPER
SC1_CD
I
SmartCard1 card detect
NC
112
113
O
XT1_IN
PF.3
External 4~24 MHz crystal output pin
General purpose digital I/O pin
58
I/O
May 31, 2016
Page 56 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Pin Name
Description
Type
LQFP LQFP LQFP/QFN
128-pin 64-pin
48-pin
I
XT1_OUT
PF.2
External 4~24 MHz crystal input pin
General purpose digital I/O pin
NC
114
115
116
59
45
I/O
External reset input: Low active, set this pin
low reset chip to initial state. With internal
pull-up.
I
60
61
46
nRESET
P
P
117
118
119
VSS
VSS
Ground
Ground
NC
Power supply for I/O ports and LDO source
for internal PLL and digital circuit
P
120
121
62
VDD
NC
I/O
I/O
I/O
I/O
P
PF.4
General purpose digital I/O pin
I2C0 data I/O pin
122
123
I2C0_SDA
PF.5
General purpose digital I/O pin
I2C0 clock pin
I2C0_SCL
VSS
124
125
Ground
P
63
64
47
48
PVSS
PLL Ground
I/O
I
PB.8
General purpose digital I/O pin
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
SmartCard2 Power pin
General purpose digital I/O pin
General purpose digital I/O pin
STADC
TM0
I
126
I
INT0
O
SC2_PWR
PE.15
PE.14
I/O
I/O
127
128
Note:
Pin Type: I = Digital Input, O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog Power.
May 31, 2016
Page 57 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.4.2 NuMicro® Nano110 Pin Description
Pin No.
Pin Name
Pin Type
Description
LQFP
LQFP
LQFP
128-pin 64-pin
48-pin
I/O
O
PE.13
General purpose digital I/O pin
LCD segment output 27 at LQFP128
General purpose digital I/O pin
External interrupt0 input pin
SmartCard2 card detect
1
LCD_SEG27
PB.14
I/O
I
INT0
I
SC2_CD
SPI2_SS1
LCD_SEG12
LCD_SEG26
PB.13
2
1
SPI2 2nd slave select pin
I/O
O
LCD segment output 12 at LQFP64
LCD segment output 26 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit1
LCD segment output 11 at LQFP64
LCD segment output 25 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit0
Frequency Divider output pin
LCD segment output 10 at LQFP64
LCD segment output 24 at LQFP128
NC
O
I/O
I/O
O
EBI_AD1
LCD_SEG11
LCD_SEG25
PB.12
3
4
2
3
O
I/O
I/O
O
EBI_AD0
FCLKO
O
LCD_SEG10
LCD_SEG24
O
5
6
7
8
O
I
4
5
X32O
X32I
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
NC
I/O
I/O
O
PA.11
General purpose digital I/O pin
I2C1 clock pin
I2C1_SCL
EBI_nRD
SC0_RST
SPI2_MOSI0
LCD_SEG9
LCD_SEG23
PA.10
EBI read enable output pin
SmartCard0 RST pin
O
9
6
7
SPI2 1st MOSI (Master Out, Slave In) pin
LCD segment output 9 at LQFP64
LCD segment output 23 at LQFP128
General purpose digital I/O pin
I2C1 data I/O pin
I/O
O
O
I/O
I/O
10
I2C1_SDA
May 31, 2016
Page 58 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
O
O
EBI_nWR
SC0_PWR
SPI2_MISO0
LCD_SEG8
LCD_SEG22
PA.9
EBI write enable output pin
SmartCard0 Power pin
SPI2 1st MISO (Master In, Slave Out) pin
LCD segment output 8 at LQFP64
LCD segment output 22 at LQFP128
General purpose digital I/O pin
I2C0 clock pin
I/O
O
O
I/O
I/O
I/O
I/O
O
I2C0_SCL
SC0_DAT
SPI2_CLK
LCD_SEG7
LCD_SEG21
PA.8
SmartCard0 DATA pin(SC0_UART_RXD)
SPI2 serial clock pin
11
8
LCD segment output 7 at LQFP64
LCD segment output 21 at LQFP128
General purpose digital I/O pin
I2C0 data I/O pin
O
I/O
I/O
O
I2C0_SDA
SC0_CLK
SPI2_SS0
LCD_SEG6
LCD_SEG20
PD.8
SmartCard0 clock pin(SC0_UART_TXD)
SPI2 1st slave select pin
12
9
I/O
O
LCD segment output 6 at LQFP64
LCD segment output 20 at LQFP128
General purpose digital I/O pin
LCD segment output 19 at LQFP128
General purpose digital I/O pin
LCD segment output 18 at LQFP128
General purpose digital I/O pin
LCD segment output 17 at LQFP128
General purpose digital I/O pin
LCD segment output 16 at LQFP128
General purpose digital I/O pin
LCD segment output 15 at LQFP128
General purpose digital I/O pin
LCD segment output 14 at LQFP128
General purpose digital I/O pin
O
I/O
O
13
14
15
16
17
LCD_SEG19
PD.9
I/O
O
LCD_SEG18
PD.10
I/O
O
LCD_SEG17
PD.11
I/O
O
LCD_SEG16
PD.12
I/O
O
LCD_SEG15
PD.13
I/O
O
18
19
LCD_SEG14
PB.4
I/O
10
May 31, 2016
Page 59 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
I
UART1_RXD
SC0_CD
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
I
I/O
O
SPI2_SS0
LCD_SEG5
LCD_SEG13
PB.5
LCD segment output 5 at LQFP64
LCD segment output 13 at LQFP128
General purpose digital I/O pin
UART1 Data transmitter output pin
SmartCard0 RST pin
O
I/O
O
UART1_TXD
SC0_RST
SPI2_CLK
LCD_SEG4
LCD_SEG12
PB.6
O
20
21
22
11
I/O
O
SPI2 serial clock pin
LCD segment output 4 at LQFP64
LCD segment output 12 at LQFP128
General purpose digital I/O pin
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 1st MISO (Master In, Slave Out) pin
LCD segment output 3 at LQFP64
LCD segment output 11 at LQFP128
General purpose digital I/O pin
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
LCD segment output 2 at LQFP64
LCD segment output 10 at LQFP128
NC
O
I/O
O
UART1_RTSn
EBI_ALE
O
12
I/O
O
SPI2_MISO0
LCD_SEG3
LCD_SEG11
PB.7
O
I/O
I
UART1_CTSn
EBI_nCS
O
13
14
I/O
O
SPI2_MOSI0
LCD_SEG2
LCD_SEG10
O
23
24
25
26
27
28
29
P
LDO_CAP
LDO output pin
NC
NC
P
P
15
16
VDD
VSS
Power supply for I/O ports and LDO source
NC
Ground
May 31, 2016
Page 60 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
P
P
30
31
32
VSS
Ground
Ground
Ground
VSS
P
VSS
I/O
I
PE.12
General purpose digital I/O pin
UART1 Clear to Send input pin
General purpose digital I/O pin
UART1 Request to Send output pin
General purpose digital I/O pin
UART1 Data transmitter output pin
General purpose digital I/O pin
UART1 Data receiver input pin
General purpose digital I/O pin
LCD segment output 9 at LQFP128
General purpose digital I/O pin
LCD segment output 8 at LQFP128
NC
33
34
35
36
37
38
UART1_CTSn
PE.11
I/O
O
UART1_RTSn
PE.10
I/O
O
UART1_TXD
PE.9
I/O
I
UART1_RXD
PE.8
I/O
O
LCD_SEG9
PE.7
I/O
O
LCD_SEG8
39
40
41
42
43
NC
NC
NC
NC
I/O
I
PB.0
General purpose digital I/O pin
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
UART0_RXD
SPI1_MOSI0
I/O
44
17
LCD segment output 1 at LQFP64 (or as
LD_COM5)
O
LCD_SEG1
O
I/O
O
LCD_SEG7
PB.1
LCD segment output 7 at LQFP128
General purpose digital I/O pin
UART0_TXD
SPI1_MISO0
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
45
18
I/O
LCD segment output 0 at LQFP64 (or as
LCD_COM4)
O
LCD_SEG0
May 31, 2016
Page 61 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
O
I/O
O
LCD_SEG6
PB.2
LCD segment output 6 at LQFP128
General purpose digital I/O pin
UART0 Request to Send output pin
EBI low byte write enable output pin
SPI1 serial clock pin
UART0_RTSn
EBI_nWRL
SPI1_CLK
LCD_COM3
LCD_SEG5
PB.3
O
46
19
I/O
O
LCD common output 3 at LQFP64
LCD segment output 5 at LQFP128
General purpose digital I/O pin
UART0 Clear to Send input pin
EBI high byte write enable output pin
SPI1 1st slave select pin
O
I/O
I
UART0_CTSn
EBI_nWRH
SPI1_SS0
LCD_COM2
LCD_SEG4
PD.6
O
47
20
I/O
O
LCD common output 2 at LQFP64
LCD segment output 4 at LQFP128
General purpose digital I/O pin
LCD segment output 3 at LQFP128
General purpose digital I/O pin
LCD segment output 2 at LQFP128
General purpose digital I/O pin
O
I/O
O
48
49
21
22
LCD_SEG3
PD.7
I/O
O
LCD_SEG2
PD.14
I/O
50
51
23
24
LCD segment output 1 at LQFP128 (or as
LCD_COM5)
O
I/O
O
LCD_SEG1
PD.15
General purpose digital I/O pin
LCD segment output 0 at LQFP128 (or as
LCD_COM4)
LCD_SEG0
I/O
I/O
O
PC.5
General purpose digital I/O pin
52
SPI0_MOSI1
LCD_COM3
PC.4
SPI0 2nd MOSI (Master Out, Slave In) pin
LCD common output 3 at LQFP128
General purpose digital I/O pin
I/O
I/O
O
53
54
SPI0_MISO1
LCD_COM2
PC.3
SPI0 2nd MISO (Master In, Slave Out) pin
LCD common output 2 at LQFP128
General purpose digital I/O pin
I/O
I/O
25
SPI0_MOSI0
SPI0 1st MOSI (Master Out, Slave In) pin
May 31, 2016
Page 62 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
I2S data output
O
O
I2S_DO
SC1_RST
LCD_COM1
LCD_COM1
PC.2
SmartCard1 RST pin
O
LCD common output 1 at LQFP64
LCD common output 1 at LQFP128
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
O
I/O
I/O
I
SPI0_MISO0
I2S_DI
55
26
O
SC1_PWR
LCD_COM0
LCD_COM0
PC.1
SmartCard1 PWR pin
O
LCD common output 0 at LQFP64
LCD common output 0 at LQFP128
General purpose digital I/O pin
SPI0 serial clock pin
O
I/O
I/O
I/O
I/O
SPI0_CLK
I2S_BCLK
SC1_DAT
I2S bit clock pin
SmartCard1 DATA pin(SC1_UART_RXD)
56
27
LCD externl capacitor pin of charge pump
circuit at LQFP64
O
O
LCD_DH2
LCD externl capacitor pin of charge pump
circuit at LQFP128
LCD_DH2
General purpose digital I/O pin / Module
clock output pin
I/O
PC.0 / MCLKO
I/O
I/O
O
SPI0_SS0
I2S_LRCLK
SC1_CLK
SPI0 1st slave select pin
I2S left right channel clock
57
28
SmartCard1 clock pin(SC1_UART_TXD)
LCD externl capacitor pin of charge pump
circuit at LQFP64
O
O
LCD_DH1
LCD_DH1
LCD externl capacitor pin of charge pump
circuit at LQFP128
I/O
58
59
60
61
PE.6
General purpose digital I/O pin
LCD power supply pin
NC
AO
29
30
LCD_VLCD
I/O
I/O
I/O
PE.5
General purpose digital I/O pin
General purpose digital I/O pin
PWM1 Channel0 output
PB.11
62
PWM1_CH0
May 31, 2016
Page 63 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
O
TM3
Timer3 external counter input
I/O
I/O
SC2_DAT
SPI0_MISO0
SmartCard2 DATA pin(SC2_UART_RXD)
SPI0 1st MISO (Master In, Slave Out) pin
Unit voltage for LCD charge pump circuit at
LQFP64
O
O
LCD_V1
LCD_V1
LCD Unit voltage for LCD charge pump
circuit at LQFP128
I/O
I/O
O
PB.10
General purpose digital I/O pin
SPI0 2nd slave select pin
SPI0_SS1
TM2
Timer2 external counter input
SmartCard2 clock pin(SC2_UART_TXD)
SPI0 1st MOSI (Master Out, Slave In) pin
LCD driver biasing voltage at LQFP64
LCD driver biasing voltage at LQFP128
General purpose digital I/O pin
SPI1 2nd slave select pin
O
63
31
SC2_CLK
SPI0_MOSI0
LCD_V2
LCD_V2
PB.9
I/O
O
O
I/O
I/O
O
SPI1_SS1
TM1
Timer1 external counter input
SmartCard2 RST pin
O
64
32
SC2_RST
INT0
I
External interrupt0 input pin
O
LCD_V3
LCD_V3
PE.4
LCD driver biasing voltage at LQFP64
LCD driver biasing voltage at LQFP128
General purpose digital I/O pin
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
SPI0 serial clock pin
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
65
66
67
SPI0_MOSI0
PE.3
SPI0_MISO0
PE.2
SPI0_CLK
PE.1
General purpose digital I/O pin
PWM1 Channel3 output
68
69
PWM1_CH3
SPI0_SS0
PE.0
SPI0 1st slave select pin
General purpose digital I/O pin
May 31, 2016
Page 64 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
I/O
O
PWM1_CH2
I2S_MCLK
PC.13
PWM1 Channel2 output
I2S master clock output pin
General purpose digital I/O pin
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
I/O
I/O
O
SPI1_MOSI1
PWM1_CH1
SNOOPER
INT1
70
I
Snooper pin
I
External interrupt 1
I2C0_SCL
PC.12
I2C0 clock pin
O
I/O
I/O
O
General purpose digital I/O pin
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel0 output
SPI1_MISO1
PWM1_CH0
INT0
71
I
External interrupt0 input pin
I2C0 data I/O pin
I/O
I/O
I/O
O
I2C0_SDA
PC.11
General purpose digital I/O pin
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
LCD segment output 31 at LQFP64
General purpose digital I/O pin
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
LCD segment output 30 at LQFP64
General purpose digital I/O pin
SPI1 serial clock pin
SPI1_MOSI0
UART1_TXD
LCD_SEG31
PC.10
72
73
74
33
34
35
O
I/O
I/O
I
SPI1_MISO0
UART1_RXD
LCD_SEG30
PC.9
O
I/O
I/O
I/O
O
SPI1_CLK
I2C1_SCL
LCD_SEG29
PC.8
I2C1 clock pin
LCD segment output 29 at LQFP64
General purpose digital I/O pin
SPI1 1st slave select pin
I/O
I/O
O
SPI1_SS0
EBI_MCLK
I2C1_SDA
LCD_SEG28
75
36
EBI external clock output pin
I2C1 data I/O pin
I/O
O
LCD segment output 28 at LQFP64
May 31, 2016
Page 65 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
I/O
I/O
O
PA.15
General purpose digital I/O pin
PWM0 Channel3 output
PWM0_CH3
I2S_MCLK
TC3
I2S master clock output pin
Timer3 capture input
I
76
37
O
SC0_PWR
UART0_TXD
LCD_SEG27
PA.14
SmartCard0 Power pin
O
UART0 Data transmitter output pin
LCD segment output 27 at LQFP64
General purpose digital I/O pin
PWM0 Channel2 output
O
I/O
I/O
I/O
I
PWM0_CH2
EBI_AD15
TC2
EBI Address/Data bus bit15
Timer2 capture input
77
78
79
38
39
40
I
UART0_RXD
LCD_SEG26
PA.13
UART0 Data receiver input pin
LCD segment output 26 at LQFP64
General purpose digital I/O pin
PWM0 Channel1 output
O
I/O
I/O
I/O
I
PWM0_CH1
EBI_AD14
TC1
EBI Address/Data bus bit14
Timer1 capture input
I2C0_SCL
LCD_SEG25
PA.12
I2C0 clock pin
I/O
O
LCD segment output 25 at LQFP64
General purpose digital I/O pin
PWM0 Channel0 output
I/O
I/O
I/O
I
PWM0_CH0
EBI_AD13
TC0
EBI Address/Data bus bit13
Timer0 capture input
I2C0 data I/O pin
I/O
O
I2C0_SDA
LCD_SEG24
ICE_DAT
PF.0
LCD segment output 24 at LQFP64
Serial Wired Debugger Data pin
General purpose digital I/O pin
External interrupt0 input pin
Serial Wired Debugger Clock pin
General purpose digital I/O pin
I/O
I/O
I
80
81
41
42
INT0
I
ICE_CLK
PF.1
I/O
May 31, 2016
Page 66 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
O
I
FCLKO
INT1
Frequency Divider output pin
External interrupt1 input pin
NC
82
83
Power supply for I/O ports and LDO source
for internal PLL and digital circuit
P
VDD
84
85
86
NC
P
P
VSS
Ground
VSS
Ground
AP
AP
I/O
AI
87
88
43
44
45
AVSS
Ground Pin for analog circuit
Ground Pin for analog circuit
General purpose digital I/O pin
ADC analog input0
AVSS
PA.0
89
90
AD0
I
SC2_CD
PA.1
SmartCard2 card detect
General purpose digital I/O pin
ADC analog input1
I/O
AI
AD1
I/O
I/O
AI
EBI_AD12
PA.2
EBI Address/Data bus bit12
General purpose digital I/O pin
ADC analog input2
AD2
I/O
I
91
46
47
48
EBI_AD11
UART1_RXD
LCD_SEG23*
PA.3
EBI Address/Data bus bit11
UART1 Data receiver input pin
LCD segment output 23 at LQFP64
General purpose digital I/O pin
ADC analog input3
AO
I/O
AI
AD3
I/O
O
92
EBI_AD10
UART1_TXD
LCD_SEG22*
PA.4
EBI Address/Data bus bit10
UART1 Data transmitter output pin
LCD segment output 22 at LQFP64
General purpose digital I/O pin
ADC analog input4
AO
I/O
AI
AD4
I/O
O
93
EBI_AD9
SC2_PWR
I2C0_SDA
EBI Address/Data bus bit9
SmartCard2 Power pin
I2C0 data I/O pin
I/O
May 31, 2016
Page 67 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
AO
AO
I/O
AI
LCD_SEG21*
LCD_SEG39*
PA.5
LCD segment output 21 at LQFP64
LCD segment output 39 at LQFP128
General purpose digital I/O pin
ADC analog input5
AD5
I/O
O
EBI_AD8
SC2_RST
I2C0_SCL
LCD_SEG20*
LCD_SEG38*
PA.6
EBI Address/Data bus bit8
SmartCard2 RST pin
94
95
96
49
I2C0 clock pin
I/O
AO
AO
I/O
AI
LCD segment output 19 at LQFP64
LCD segment output 37 at LQFP128
General purpose digital I/O pin
ADC analog input6
AD6
I/O
I
EBI_AD7
TC3
EBI Address/Data bus bit7
Timer3 capture input
50
O
SC2_CLK
PWM0_CH3
LCD_SEG19*
LCD_SEG37*
PA.7
SmartCard2 clock pin(SC2_UART_TXD)
PWM0 Channel3 output
O
AO
AO
I/O
AI
LCD segment output 19 at LQFP64
LCD segment output 37 at LQFP128
General purpose digital I/O pin
ADC analog input7
AD7
I/O
I
EBI_AD6
TC2
EBI Address/Data bus bit6
Timer2 capture input
I/O
O
SC2_DAT
PWM0_CH2
LCD_SEG36*
VREF
SmartCard2 DATA pin(SC2_UART_RXD)
PWM0 Channel2 output
AO
AP
LCD segment output 36 output at LQFP128
Voltage reference input for ADC
NC
97
98
99
51
52
AP
I/O
I
AVDD
Power supply for internal analog circuit
General purpose digital I/O pin
UART1 Data receiver input pin
SPI2 1st slave select pin
PD.0
100
UART1_RXD
SPI2_SS0
I/O
May 31, 2016
Page 68 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
O
AI
SC1_CLK
AD8
SmartCard1 clock pin(SC1_UART_TXD)
ADC analog input8
I/O
O
PD.1
General purpose digital I/O pin
UART1 Data transmitter output pin
SPI2 serial clock pin
UART1_TXD
SPI2_CLK
SC1_DAT
AD9
I/O
I/O
AI
101
SmartCard1 DATA pin(SC1_UART_RXD)
ADC analog input9
I/O
PD.2
General purpose digital I/O pin
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
UART1_RTSn
I2S_LRCLK
SPI2_MISO0
SC1_PWR
AD10
I/O
I/O
O
102
AI
ADC analog input10
I/O
PD.3
General purpose digital I/O pin
UART1 Clear to Send input pin
I2S bit clock pin
UART1_CTSn
I2S_BCLK
SPI2_MOSI0
SC1_RST
AD11
I/O
I/O
O
103
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
AI
ADC analog input11
104
105
NC
I/O
I
PD.4
General purpose digital I/O pin
I2S data input
I2S_DI
I/O
I
SPI2_MISO1
SC1_CD
LCD_SEG35
PD.5
SPI2 2nd MISO (Master In, Slave Out) pin
SmartCard1 card detect
AO
I/O
O
LCD segment output 35 at LQFP10
General purpose digital I/O pin
I2S data output
I2S_DO
106
SPI2_MOSI1
LCD_SEG34
PC.7
SPI2 2nd MOSI (Master Out, Slave In) pin
LCD segment output 34 at LQFP128
General purpose digital I/O pin
I/O
AO
I/O
107
53
May 31, 2016
Page 69 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
AO
I/O
I
DA1_OUT
EBI_AD5
TC1
DAC 1 output
EBI Address/Data bus bit5
Timer1 capture input
O
PWM0_CH1
LCD_SEG17*
PC.6
PWM1 Channel1 output
AO
I/O
I
LCD segment output 17 at LQFP64
General purpose digital I/O pin
DAC0 output
DA0_OUT
EBI_AD4
TC0
I/O
I
EBI Address/Data bus bit4
Timer0 capture input
108
54
I
SC1_CD
PWM0_CH0
PC.15
SmartCard1 card detect pin
PWM0 Channel0 output
O
I/O
I/O
I
General purpose digital I/O pin
EBI Address/Data bus bit3
Timer0 capture input
EBI_AD3
TC0
109
55
O
PWM1_CH2
LCD_SEG16
LCD_SEG33
PC.14
PWM1 Channel1 output
AO
AO
I/O
I/O
I/O
AO
AO
I/O
I
LCD segment output 16 at LQFP64
LCD segment output 33 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit2
PWM1 Channel3 output
EBI_AD2
PWM1_CH3
LCD_SEG15
LCD_SEG32
PB.15
110
56
LCD segment output 15 at LQFP64
LCD segment output 32 at LQFP128
General purpose digital I/O pin
External interrupt1 input pin
Snooper pin
INT1
I
111
57
58
SNOOPER
LCD_SEG14
LCD_SEG31
AO
AO
LCD segment output 14 at LQFP64
LCD segment output 31 at LQFP128
NC
112
113
O
XT1_IN
PF.3
External 4~24 MHz crystal output pin
General purpose digital I/O pin
I/O
May 31, 2016
Page 70 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
LQFP
Pin Name
Pin Type
Description
LQFP
LQFP
128-pin 64-pin
48-pin
I
XT1_OUT
PF.2
External 4~24 MHz crystal input pin
General purpose digital I/O pin
NC
114
115
116
59
I/O
External reset input: Low active, set this pin
low reset chip to initial state. With internal
pull-up.
I
60
61
nRESET
P
P
117
118
119
VSS
VSS
Ground
Ground
NC
Power supply for I/O ports and LDO source
for internal PLL and digital circuit
P
120
121
62
VDD
NC
I/O
I/O
I/O
I/O
P
PF.4
General purpose digital I/O pin
I2C0 data I/O pin
122
123
I2C0_SDA
PF.5
General purpose digital I/O pin
I2C0 clock pin
I2C0_SCL
VSS
124
125
Ground
P
63
64
PVSS
PLL Ground
I/O
I
PB.8
General purpose digital I/O pin
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
SmartCard2 Power pin
STADC
TM0
I
I
126
INT0
O
SC2_PWR
LCD_SEG13
LCD_SEG30
PE.15
AO
AO
I/O
O
LCD segment output 13 at LQFP64
LCD segment output 30 at LQFP128
General purpose digital I/O pin
LCD segment output 29 at LQFP128
General purpose digital I/O pin
LCD segment output 28 at LQFP128
127
128
LCD_SEG29
PE.14
I/O
O
LCD_SEG28
Note:
1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power;
2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance.
May 31, 2016
Page 71 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.4.3 NuMicro® Nano120 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I/O
I/O
I
1
PE.13
General purpose digital IO pin
General purpose digital IO pin
External interrupt0 input pin
SmartCard2 card detect
PB.14
INT0
2
1
I
SC2_CD
SPI2_SS1
PB.13
SPI2 2nd slave select pin
General purpose digital IO pin
EBI Address/Data bus bit1
General purpose digital IO pin
EBI Address/Data bus bit0
Frequency Divider output pin
NC
I/O
I/O
I/O
I/O
I/O
O
3
4
2
3
EBI_AD1
PB.12
1
EBI_AD0
FCLKO
5
6
7
8
O
I
4
5
2
3
X32O
X32I
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
NC
I/O
I/O
O
PA.11
General purpose digital IO pin
I2C 1 clock pin
I2C1_SCL
EBI_nRD
SC0_RST
SPI2_MOSI0
PA.10
9
6
4
EBI read enable output pin
SmartCard0 RST pin
O
SPI2 1st MOSI (Master Out, Slave In) pin
General purpose digital IO pin
I2C 1 data I/O pin
I/O
I/O
I/O
O
I2C1_SDA
EBI_nWR
SC0_PWR
SPI2_MISO0
PA.9
10
7
5
EBI write enable output pin
SmartCard0 Power pin
O
SPI2 1st MISO (Master In, Slave Out) pin
General purpose digital IO pin
I2C 0 clock pin
I/O
I/O
I/O
I/O
I/O
I/O
I2C0_SCL
SC0_DAT
SPI2_CLK
PA.8
11
12
8
9
6
7
SmartCard0 DATA pin(SC0_UART_RXD)
SPI2 serial clock pin
General purpose digital IO pin
May 31, 2016
Page 72 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I2C0_SDA
SC0_CLK
SPI2_SS0
PD.8
I2C 0 data I/O pin
I/O
O
SmartCard0 clock pin(SC0_UART_TXD)
SPI2 1st slave select pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
13
14
15
16
17
18
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
UART1_RXD
SC0_CD
SPI2_SS0
PB.5
19
20
21
22
10
11
12
13
8
9
I
I/O
I/O
O
General purpose digital IO pin
UART1 Data transmitter output pin
SmartCard0 RST pin
UART1_TXD
SC0_RST
SPI2_CLK
PB.6
O
I/O
I/O
O
SPI2 serial clock pin
General purpose digital IO pin
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 1st MISO (Master In, Slave Out) pin
General purpose digital IO pin
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
NC
UART1_nRTS
EBI_ALE
SPI2_MISO0
PB.7
O
I/O
I/O
I
UART1_nCTS
EBI_nCS
SPI2_MOSI0
O
I/O
23
24
25
26
27
P
14
15
10 LDO_CAP
LDO output pin
NC
NC
P
11 VDD
Power supply for I/O ports and LDO source
May 31, 2016
Page 73 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
P
16
12 VSS
VSS
Ground
P
Ground
P
VSS
Ground
P
VSS
Ground
I/O
I/O
I/O
I/O
I/O
I/O
PE.12
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
NC
PE.11
PE.10
PE.9
PE.8
PE.7
USB
USB
17
18
13 USB_VBUS
POWER SUPPLY: From USB Host or HUB.
USB_VDD33_C
AP
Internal Power Regulator Output 3.3V Decoupling
Pin
41
14
USB
USB
I/O
I
42
43
19
20
15 USB_D-
16 USB_D+
PB.0
USB Differential Signal D-
USB Differential Signal D+
General purpose digital IO pin
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
General purpose digital IO pin
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
General purpose digital IO pin
UART0 Request to Send output pin
EBI low byte write enable output pin
SPI1 serial clock pin
44
45
21
22
17 UART0_RXD
SPI1_MOSI0
PB.1
I/O
I/O
O
18 UART0_TXD
SPI1_MISO0
PB.2
I/O
I/O
O
UART0_nRTS
19
46
47
23
24
O
EBI_nWRL
I/O
I/O
I
SPI1_CLK
PB.3
General purpose digital IO pin
UART0 Clear to Send input pin
EBI high byte write enable output pin
SPI1 1st slave select pin
UART0_nCTS
20
O
EBI_nWRH
I/O
SPI1_SS0
May 31, 2016
Page 74 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
48
49
50
51
PD.6
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
General purpose digital IO pin
SPI0 2nd MOSI (Master Out, Slave In) pin
General purpose digital IO pin
SPI0 2nd MISO (Master In, Slave Out) pin
General purpose digital IO pin
SPI0 1st MOSI (Master Out, Slave In) pin
I2S data output
PD.7
PD.14
PD.15
PC.5
52
53
SPI0_MOSI1
PC.4
SPI0_MISO1
PC.3
SPI0_MOSI0
I2S_DO
SC1_RST
PC.2
54
55
56
25
26
27
21
22
23
O
SmartCard1 RST pin
I/O
I/O
I
General purpose digital IO pin
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
SPI0_MISO0
I2S_DI
O
SC1_PWR
PC.1
SmartCard1 PWR pin
I/O
I/O
I/O
I/O
General purpose digital IO pin
SPI0 serial clock pin
SPI0_CLK
I2S_BCLK
SC1_DAT
I2S bit clock pin
SmartCard1 DATA pin(SC1_UART_RXD)
General purpose digital IO pin / Module clock
output pin
I/O
PC.0 / MCLKO
I/O
I/O
O
SPI0_SS0
I2S_LRCLK
SC1_CLK
PE.6
SPI0 1st slave select pin
I2S left right channel clock
SmartCard1 clock pin(SC1_UART_TXD)
General purpose digital IO pin
NC
57
28
24
I/O
58
59
60
NC
I/O
I/O
I/O
PE.5
General purpose digital IO pin
PWM1 Channel1 output
General purpose digital IO pin
61
62
29
30
PWM1_CH1
PB.11
May 31, 2016
Page 75 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I/O
O
PWM1_CH0
TM3
PWM1 Channel0 output
Timer3 external counter input
SmartCard2 DATA pin(SC2_UART_RXD)
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital IO pin
SPI0 2nd slave select pin
I/O
I/O
I/O
I/O
O
SC2_DAT
SPI0_MISO0
PB.10
SPI0_SS1
TM2
63
31
Timer2 external counter input
SmartCard2 clock pin(SC2_UART_TXD)
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital IO pin
SPI1 2nd slave select pin
O
SC2_CLK
SPI0_MOSI0
PB.9
I/O
I/O
I/O
O
SPI1_SS1
TM1
64
32
Timer1 external counter input
SmartCard2 RST pin
O
SC2_RST
INT0
I
External interrupt0 input pin
General purpose digital IO pin
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital IO pin
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital IO pin
SPI0 serial clock pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PE.4
65
66
67
SPI0_MOSI0
PE.3
SPI0_MISO0
PE.2
SPI0_CLK
PE.1
General purpose digital IO pin
PWM1 Channel3 output
68
69
PWM1_CH3
SPI0_SS0
PE.0
SPI0 1st slave select pin
General purpose digital IO pin
PWM1 Channel2 output
PWM1_CH2
I2S_MCLK
PC.13
I2S master clock output pin
I/O
I/O
O
General purpose digital IO pin
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
SPI1_MOSI1
PWM1_CH1
SNOOPER
70
I
Snooper pin
May 31, 2016
Page 76 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I
INT1
External interrupt 1 input pin
I2C 0 clock pin
O
I2C0_SCL
PC.12
I/O
I/O
O
General purpose digital IO pin
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel 0 output
SPI1_MISO1
PWM1_CH0
INT0
71
I
External interrupt 0 input pin
I2C 0 data I/O pin
I/O
I/O
I/O
O
I2C0_SDA
PC.11
General purpose digital IO pin
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
General purpose digital IO pin
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
General purpose digital IO pin
SPI1 serial clock pin
72
73
74
33
34
35
SPI1_MOSI0
UART1_TXD
PC.10
I/O
I/O
I
SPI1_MISO0
UART1_RXD
PC.9
I/O
I/O
I/O
I/O
I/O
O
SPI1_CLK
I2C1_SCL
PC.8
I2C 1 clock pin
General purpose digital IO pin
SPI1 1st slave select pin
SPI1_SS0
EBI_MCLK
I2C1_SDA
PA.15
75
76
77
36
37
38
EBI external clock output pin
I2C 1 data I/O pin
I/O
I/O
I/O
O
General purpose digital IO pin
PWM0 Channel3 output
PWM0_CH3
I2S_MCLK
TC3
I2S master clock output pin
Timer3 capture input
25
I
O
SC0_PWR
UART0_TXD
PA.14
SmartCard0 Power pin
O
UART0 Data transmitter output pin
General purpose digital IO pin
PWM0 Channel2 output
I/O
I/O
I/O
I
PWM0_CH2
EBI_AD15
TC2
26
EBI Address/Data bus bit15
Timer 2 capture input
May 31, 2016
Page 77 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I
UART0_RXD
PA.13
UART0 Data receiver input pin
General purpose digital IO pin
PWM0 Channel1 output
EBI Address/Data bus bit14
Timer1 capture input
I/O
I/O
I/O
I
PWM0_CH1
78
39
27 EBI_AD14
TC1
I/O
I/O
I/O
I/O
I
I2C0_SCL
PA.12
I2C 0 clock pin
General purpose digital IO pin
PWM0 Channel0 output
EBI Address/Data bus bit13
Timer 0 capture input
PWM0_CH0
28 EBI_AD13
TC0
79
40
I/O
I/O
I/O
I
I2C0_SDA
ICE_DAT
29 PF.0
INT0
I2C 0 data I/O pin
Serial Wired Debugger Data pin
General purpose digital IO pin
External interrupt0 input pin
Serial Wired Debugger Clock pin
General purpose digital IO pin
Frequency Divider output pin
External interrupt1 input pin
NC
80
81
41
42
I
ICE_CLK
I/O
O
PF.1
30
FCLKO
I
INT1
82
83
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
P
VDD
84
85
86
87
88
NC
P
P
VSS
VSS
Ground
Ground
AP
AP
I/O
AI
I
43
31 AVSS
AVSS
Ground Pin for analog circuit
Ground Pin for analog circuit
General purpose digital IO pin
ADC analog input0
SmartCard2 card detect
General purpose digital IO pin
ADC analog input1
PA.0
89
90
44
45
32 AD0
SC2_CD
I/O
AI
PA.1
33
AD1
May 31, 2016
Page 78 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I/O
I/O
AI
I/O
I
EBI_AD12
EBI Address/Data bus bit12
General purpose digital IO pin
ADC analog input2
PA.2
AD2
91
92
46
34
EBI_AD11
UART1_RXD
PA.3
EBI Address/Data bus bit11
UART1 Data receiver input pin
General purpose digital IO pin
ADC analog input3
I/O
AI
I/O
O
AD3
47
48
35
EBI_AD10
UART1_TXD
PA.4
EBI Address/Data bus bit10
UART1 Data transmitter output pin
Digital GPIO pin
I/O
AI
I/O
O
AD4
ADC analog input4
93
36 EBI_AD9
SC2_PWR
I2C0_SDA
PA.5
EBI Address/Data bus bit9
SmartCard2 Power pin
I2C 0 data I/O pin
I/O
I/O
AI
I/O
O
General purpose digital IO pin
ADC analog input5
AD5
94
49
37 EBI_AD8
SC2_RST
I2C0_SCL
PA.6
EBI Address/Data bus bit8
SmartCard2 RST pin
I2C 0 clock pin
I/O
I/O
AI
I/O
I
General purpose digital IO pin
ADC analog input6
AD6
EBI_AD7
EBI Address/Data bus bit7
Timer3 capture input
95
50
38
TC3
O
SC2_CLK
PWM0_CH3
PA.7
SmartCard2 clock pin(SC2_UART_TXD)
PWM0 Channel3 output
General purpose digital IO pin
ADC analog input7
O
I/O
AI
I/O
I
AD7
96
EBI_AD6
TC2
EBI Address/Data bus bit6
Timer2 capture input
I/O
SC2_DAT
SmartCard2 DATA pin(SC2_UART_RXD)
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
O
PWM0_CH2
PWM0 Channel2 output
AP
97
98
99
51
52
39 VREF
Voltage reference input for ADC
NC
AP
I/O
I
40 AVDD
PD.0
Power supply for internal analog circuit
General purpose digital IO pin
UART1 Data receiver input pin
SPI2 1st slave select pin
UART1_RXD
I/O
O
100
SPI2_SS0
SC1_CLK
AD8
SmartCard1 clock pin(SC1_UART_TXD)
ADC analog input8
AI
I/O
O
PD.1
General purpose digital IO pin
UART1 Data transmitter output pin
SPI2 serial clock pin
UART1_TXD
SPI2_CLK
SC1_DAT
AD9
I/O
I/O
AI
I/O
O
101
SmartCard1 DATA pin(SC1_UART_RXD)
ADC analog input9
PD.2
General purpose digital IO pin
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
UART1_nRTS
I2S_LRCLK
SPI2_MISO0
SC1_PWR
AD10
I/O
I/O
O
102
AI
I/O
I
ADC analog input10
PD.3
General purpose digital IO pin
UART1 Clear to Send input pin
I2S bit clock pin
UART1_nCTS
I2S_BCLK
SPI2_MOSI0
SC1_RST
AD11
I/O
I/O
O
103
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
AI
ADC analog input11
104
105
NC
I/O
I
PD.4
General purpose digital IO pin
I2S data input
I2S_DI
SPI2 2nd MISO (Master In, Slave Out) pin
I/O
SPI2_MISO1
May 31, 2016
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Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I
SC1_CD
SmartCard1 card detect
I/O
O
PD.5
General purpose digital IO pin
I2S data output
106
107
I2S_DO
SPI2_MOSI1
PC.7
SPI2 2nd MOSI (Master Out, Slave In) pin
General purpose digital IO pin
DAC 1 output
I/O
I/O
AO
I/O
I
DA1+OUT
53
41 EBI_AD5
TC1
EBI Address/Data bus bit5
Timer1 capture input
O
PWM0_CH1
PWM1 Channel1 output
General purpose digital IO pin
DAC0 output
I/O
I
PC.6
DA0_OUT
EBI_AD4
TC0
I/O
I
EBI Address/Data bus bit4
Timer 0 capture input
108
54
42
SC1_CD
PWM0_CH0
PC.15
SmartCard1 card detect pin
PWM0 Channel0 output
General purpose digital IO pin
EBI Address/Data bus bit3
Timer0 capture input
O
I/O
I/O
I
EBI_AD3
TC0
109
110
111
55
56
57
O
PWM1_CH2
PC.14
PWM1 Channel1 output
General purpose digital IO pin
EBI Address/Data bus bit2
PWM1 Channel3 output
General purpose digital IO pin
External interrupt1 input pin
Snooper pin
I/O
I/O
I/O
I/O
I
EBI_AD2
PWM1_CH3
PB.15
INT1
43
44
I
SNOOPER
SC1_CD
I
SmartCard1 card detect
NC
112
113
114
O
I/O
I
XT1_IN
PF.3
External 4~24 MHz crystal output pin
General purpose digital I/O pin
External 4~24 MHz crystal input pin
58
59
45 XT1_OUT
May 31, 2016
Page 81 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP
128
LQFP LQFP
64
48
I/O
PF.2
General purpose digital I/O pin
NC
115
116
External reset input: Low active, set this pin low
reset chip to initial state. With internal pull-up.
I
60
61
46 nRESET
P
P
117
118
119
VSS
VSS
Ground
Ground
NC
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
P
120
121
62
VDD
NC
I/O
I/O
I/O
I/O
P
PF.4
I2C0_SDA
PF.5
General purpose digital IO pin
I2C 0 data I/O pin
122
123
General purpose digital IO pin
I2C 0 clock pin
I2C0_SCL
VSS
124
125
Ground
P
63
64
47 PVSS
PB.8
PLL Ground
I/O
I
General purpose digital IO pin
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
SmartCard2 Power pin
General purpose digital IO pin
General purpose digital IO pin
STADC
48 TM0
INT0
I
126
I
O
SC2_PWR
PE.15
I/O
I/O
127
128
PE.14
Note:
1. Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power;
May 31, 2016
Page 82 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
3.4.4 NuMicro® Nano130 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
I/O
O
PE.13
General purpose digital I/O pin
LCD segment output 27 at LQFP128
General purpose digital I/O pin
External interrupt0 input pin
SmartCard2 card detect
1
LCD_SEG27
I/O
I
PB.14
INT0
I
SC2_CD
2
1
I/O
O
SPI2_SS1
LCD_SEG12
LCD_SEG26
PB.13
SPI2 2nd slave select pin
LCD segment output 12 at LQFP64
LCD segment output 26 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit1
LCD segment output 11 at LQFP64
LCD segment output 25 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit0
Frequency Divider output pin
LCD segment output 10 at LQFP64
LCD segment output 24 at LQFP128
NC
O
I/O
I/O
O
EBI_AD1
3
4
2
3
LCD_SEG11
LCD_SEG25
PB.12
O
I/O
I/O
O
EBI_AD0
FCLKO
O
LCD_SEG10
LCD_SEG24
O
5
6
7
8
O
I
4
5
X32O
X32I
External 32.768 kHz crystal output pin
External 32.768 kHz crystal input pin
NC
I/O
I/O
O
PA.11
General purpose digital I/O pin
I2C1 clock pin
I2C1_SCL
EBI_nRD
SC0_RST
SPI2_MOSI0
LCD_SEG9
LCD_SEG23
PA.10
EBI read enable output pin
SmartCard0 RST pin
O
9
6
7
SPI2 1st MOSI (Master Out, Slave In) pin
LCD segment output 9 at LQFP64
LCD segment output 23 at LQFP128
General purpose digital I/O pin
I2C1 data I/O pin
I/O
O
O
I/O
I/O
10
I2C1_SDA
May 31, 2016
Page 83 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
O
O
EBI_nWR
EBI write enable output pin
SC0_PWR
SPI2_MISO0
LCD_SEG8
LCD_SEG22
PA.9
SmartCard0 Power pin
SPI2 1st MISO (Master In, Slave Out) pin
LCD segment output 8 at LQFP64
LCD segment output 22 at LQFP128
General purpose digital I/O pin
I2C0 clock pin
I/O
O
O
I/O
I/O
I/O
I/O
O
I2C0_SCL
SC0_DAT
SPI2_CLK
LCD_SEG7
LCD_SEG21
PA.8
SmartCard0 DATA pin(SC0_UART_RXD)
SPI2 serial clock pin
11
8
LCD segment output 7 at LQFP64
LCD segment output 21 at LQFP128
General purpose digital I/O pin
I2C0 data I/O pin
O
I/O
I/O
O
I2C0_SDA
SC0_CLK
SPI2_SS0
LCD_SEG6
LCD_SEG20
PD.8
SmartCard0 clock pin(SC0_UART_TXD)
SPI2 1st slave select pin
12
9
I/O
O
LCD segment output 6 at LQFP64
LCD segment output 20 at LQFP128
General purpose digital I/O pin
LCD segment output 19 at LQFP128
General purpose digital I/O pin
LCD segment output 18 at LQFP128
General purpose digital I/O pin
LCD segment output 17 at LQFP128
General purpose digital I/O pin
LCD segment output 16 at LQFP128
General purpose digital I/O pin
LCD segment output 15 at LQFP128
General purpose digital I/O pin
LCD segment output 14 at LQFP128
General purpose digital I/O pin
O
I/O
O
13
14
15
16
17
LCD_SEG19
PD.9
I/O
O
LCD_SEG18
PD.10
I/O
O
LCD_SEG17
PD.11
I/O
O
LCD_SEG16
PD.12
I/O
O
LCD_SEG15
PD.13
I/O
O
18
19
LCD_SEG14
PB.4
I/O
10
May 31, 2016
Page 84 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
I
UART1_RXD
SC0_CD
UART1 Data receiver input pin
SmartCard0 card detect pin
SPI2 1st slave select pin
I
I/O
O
SPI2_SS0
LCD_SEG5
LCD_SEG13
PB.5
LCD segment output 5 at LQFP64
LCD segment output 13 at LQFP128
General purpose digital I/O pin
UART1 Data transmitter output pin
SmartCard0 RST pin
O
I/O
O
UART1_TXD
SC0_RST
SPI2_CLK
LCD_SEG4
LCD_SEG12
PB.6
O
20
21
22
11
I/O
O
SPI2 serial clock pin
LCD segment output 4 at LQFP64
LCD segment output 12 at LQFP128
General purpose digital I/O pin
UART1 Request to Send output pin
EBI address latch enable output pin
SPI2 1st MISO (Master In, Slave Out) pin
LCD segment output 3 at LQFP64
LCD segment output 11 at LQFP128
General purpose digital I/O pin
UART1 Clear to Send input pin
EBI chip select enable output pin
SPI2 1st MOSI (Master Out, Slave In) pin
LCD segment output 2 at LQFP64
LCD segment output 10 at LQFP128
NC
O
I/O
O
UART1_RTSn
EBI_ALE
O
12
I/O
O
SPI2_MISO0
LCD_SEG3
LCD_SEG11
PB.7
O
I/O
I
UART1_CTSn
EBI_nCS
O
13
14
I/O
O
SPI2_MOSI0
LCD_SEG2
LCD_SEG10
O
23
24
25
26
27
28
29
P
LDO_CAP
LDO output pin
NC
NC
P
P
15
16
VDD
VSS
Power supply for I/O ports and LDO source
NC
Ground
May 31, 2016
Page 85 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
P
P
30
31
32
33
34
35
36
VSS
VSS
VSS
Ground
Ground
P
Ground
I/O
I/O
I/O
I/O
I/O
O
PE.12
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
General purpose digital I/O pin
LCD segment output 9 at LQFP128
General purpose digital I/O pin
LCD segment output 8 at LQFP128
NC
PE.11
PE.10
PE.9
PE.8
37
LCD_SEG9
PE.7
I/O
O
38
39
LCD_SEG8
USB
USB
USB
USB
I/O
40
41
42
43
17
18
19
20
USB_VBUS
USB_VDD33_CAP
USB_D-
POWER SUPPLY: From USB Host or HUB.
Internal Power Regulator Output 3.3V Decoupling Pin
USB Differential Signal D-
USB_D+
USB Differential Signal D+
General purpose digital I/O pin
UART0 Data receiver input pin
SPI1 1st MOSI (Master Out, Slave In) pin
PB.0
I
UART0_RXD
SPI1_MOSI0
I/O
44
21
LCD segment output
LCD_COM5)
1
at LQFP64 (or as
O
LCD_SEG1
O
I/O
O
LCD_SEG7
PB.1
LCD segment output 7 at LQFP128
General purpose digital I/O pin
UART0_TXD
SPI1_MISO0
UART0 Data transmitter output pin
SPI1 1st MISO (Master In, Slave Out) pin
I/O
45
46
22
23
LCD segment output
LCD_COM4)
0
at LQFP64 (or as
O
LCD_SEG0
O
I/O
O
LCD_SEG6
PB.2
LCD segment output 6 at LQFP128
General purpose digital I/O pin
UART0_RTSn
EBI_nWRL
UART0 Request to Send output pin
EBI low byte write enable output pin
O
May 31, 2016
Page 86 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
I/O
O
SPI1_CLK
SPI1 serial clock pin
LCD_COM3
LCD_SEG5
PB.3
LCD common output 3 at LQFP64
LCD segment output 5 at LQFP128
General purpose digital I/O pin
UART0 Clear to Send input pin
EBI high byte write enable output pin
SPI1 1st slave select pin
O
I/O
I
UART0_CTSn
EBI_nWRH
SPI1_SS0
LCD_COM2
LCD_SEG4
PD.6
O
47
24
I/O
O
LCD common output 2 at LQFP64
LCD segment output 4 at LQFP128
General purpose digital I/O pin
LCD segment output 3 at LQFP128
General purpose digital I/O pin
LCD segment output 2 at LQFP128
General purpose digital I/O pin
O
I/O
O
48
49
LCD_SEG3
PD.7
I/O
O
LCD_SEG2
PD.14
I/O
50
51
LCD segment output
LCD_COM5)
1
at LQFP128 (or as
O
I/O
O
LCD_SEG1
PD.15
General purpose digital I/O pin
LCD segment output
LCD_COM4)
0
at LQFP128 (or as
LCD_SEG0
I/O
I/O
O
PC.5
General purpose digital I/O pin
52
53
SPI0_MOSI1
LCD_COM3
PC.4
SPI0 2nd MOSI (Master Out, Slave In) pin
LCD common output 3 at LQFP128
General purpose digital I/O pin
SPI0 2nd MISO (Master In, Slave Out) pin
LCD common output 2 at LQFP128
General purpose digital I/O pin
SPI0 1st MOSI (Master Out, Slave In) pin
I2S data output
I/O
I/O
O
SPI0_MISO1
LCD_COM2
PC.3
I/O
I/O
O
SPI0_MOSI0
I2S_DO
54
25
O
SC1_RST
LCD_COM1
LCD_COM1
SmartCard1 RST pin
O
LCD common output 1 at LQFP64
LCD common output 1 at LQFP128
O
May 31, 2016
Page 87 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
I/O
I/O
I
PC.2
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
I2S data input
SPI0_MISO0
I2S_DI
55
26
O
SC1_PWR
LCD_COM0
LCD_COM0
PC.1
SmartCard1 PWR pin
O
LCD common output 0 at LQFP64
LCD common output 0 at LQFP128
General purpose digital I/O pin
SPI0 serial clock pin
O
I/O
I/O
I/O
I/O
SPI0_CLK
I2S_BCLK
SC1_DAT
I2S bit clock pin
SmartCard1 DATA pin(SC1_UART_RXD)
56
27
LCD externl capacitor pin of charge pump circuit at
LQFP64
O
O
LCD_DH2
LCD externl capacitor pin of charge pump circuit at
LQFP128
LCD_DH2
General purpose digital I/O pin / Module clock output
pin
I/O
PC.0 / MCLKO
I/O
I/O
O
SPI0_SS0
I2S_LRCLK
SC1_CLK
SPI0 1st slave select pin
I2S left right channel clock
57
28
SmartCard1 clock pin(SC1_UART_TXD)
LCD externl capacitor pin of charge pump circuit at
LQFP64
O
O
LCD_DH1
LCD_DH1
LCD externl capacitor pin of charge pump circuit at
LQFP128
I/O
58
59
60
61
PE.6
General purpose digital I/O pin
LCD power supply pin
AO
29
LCD_VLCD
NC
PE.5
General purpose digital I/O pin
General purpose digital I/O pin
PWM1 Channel0 output
I/O
I/O
O
PB.11
PWM1_CH0
TM3
62
30
Timer3 external counter input
SmartCard2 DATA pin(SC2_UART_RXD)
SPI0 1st MISO (Master In, Slave Out) pin
I/O
I/O
SC2_DAT
SPI0_MISO0
May 31, 2016
Page 88 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
LCD Unit voltage for LCD charge pump circuit at
LQFP64
O
O
LCD_V1
LCD Unit voltage for LCD charge pump circuit at
LQFP128
LCD_V1
I/O
I/O
O
PB.10
General purpose digital I/O pin
SPI0 2nd slave select pin
SPI0_SS1
TM2
Timer2 external counter input
SmartCard2 clock pin(SC2_UART_TXD)
SPI0 1st MOSI (Master Out, Slave In) pin
LCD driver biasing voltage at LQFP64
LCD driver biasing voltage at LQFP128
General purpose digital I/O pin
SPI1 2nd slave select pin
O
63
31
SC2_CLK
SPI0_MOSI0
LCD_V2
LCD_V2
PB.9
I/O
O
O
I/O
I/O
O
SPI1_SS1
TM1
Timer1 external counter input
SmartCard2 RST pin
O
64
32
SC2_RST
INT0
I
External interrupt0 input pin
O
LCD_V3
LCD_V3
PE.4
LCD driver biasing voltage at LQFP64
LCD driver biasing voltage at LQFP128
General purpose digital I/O pin
SPI0 1st MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
SPI0 1st MISO (Master In, Slave Out) pin
General purpose digital I/O pin
SPI0 serial clock pin
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
65
66
67
SPI0_MOSI0
PE.3
SPI0_MISO0
PE.2
SPI0_CLK
PE.1
General purpose digital I/O pin
PWM1 Channel3 output
68
PWM1_CH3
SPI0_SS0
PE.0
SPI0 1st slave select pin
General purpose digital I/O pin
PWM1 Channel2 output
69
70
PWM1_CH2
I2S_MCLK
PC.13
I2S master clock output pin
I/O
General purpose digital I/O pin
May 31, 2016
Page 89 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
SPI1_MOSI1
PWM1_CH1
SNOOPER
INT1
SPI1 2nd MOSI (Master Out, Slave In) pin
PWM1 Channel1 output
I/O
O
I
Snooper pin
I
External interrupt 1 input pin
I2C0 clock pin
O
I2C0_SCL
PC.12
I/O
I/O
O
General purpose digital I/O pin
SPI1 2nd MISO (Master In, Slave Out) pin
PWM1 Channel0 output
SPI1_MISO1
PWM1_CH0
INT0
71
I
External interrupt0 input pin
I2C0 data I/O pin
I/O
I/O
I/O
O
I2C0_SDA
PC.11
General purpose digital I/O pin
SPI1 1st MOSI (Master Out, Slave In) pin
UART1 Data transmitter output pin
LCD segment output 31 at LQFP64
General purpose digital I/O pin
SPI1 1st MISO (Master In, Slave Out) pin
UART1 Data receiver input pin
LCD segment output 30 at LQFP64
General purpose digital I/O pin
SPI1 serial clock pin
SPI1_MOSI0
UART1_TXD
LCD_SEG31
PC.10
72
73
74
33
34
35
O
I/O
I/O
I
SPI1_MISO0
UART1_RXD
LCD_SEG30
PC.9
O
I/O
I/O
I/O
O
SPI1_CLK
I2C1_SCL
LCD_SEG29
PC.8
I2C1 clock pin
LCD segment output 29 at LQFP64
General purpose digital I/O pin
SPI1 1st slave select pin
I/O
I/O
O
SPI1_SS0
EBI_MCLK
I2C1_SDA
LCD_SEG28
PA.15
75
76
36
37
EBI external clock output pin
I2C1 data I/O pin
I/O
O
LCD segment output 28 at LQFP64
General purpose digital I/O pin
PWM0 Channel3 output
I/O
I/O
O
PWM0_CH3
I2S_MCLK
I2S master clock output pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
I
TC3
Timer3 capture input
O
SC0_PWR
UART0_TXD
LCD_SEG27
PA.14
SmartCard0 Power pin
O
UART0 Data transmitter output pin
LCD segment output 27 at LQFP64
General purpose digital I/O pin
PWM0 Channel2 output
O
I/O
I/O
I/O
I
PWM0_CH2
EBI_AD15
TC2
EBI Address/Data bus bit15
Timer2 capture input
77
38
39
40
I
UART0_RXD
LCD_SEG26
PA.13
UART0 Data receiver input pin
LCD segment output 26 at LQFP64
General purpose digital I/O pin
PWM0 Channel1 output
O
I/O
I/O
I/O
I
PWM0_CH1
EBI_AD14
TC1
EBI Address/Data bus bit14
Timer1 capture input
78
I2C0 clock pin
I/O
O
I2C0_SCL
LCD_SEG25
PA.12
LCD segment output 25 at LQFP64
General purpose digital I/O pin
PWM0 Channel0 output
I/O
I/O
I/O
I
PWM0_CH0
EBI_AD13
TC0
EBI Address/Data bus bit13
Timer0 capture input
79
80
I2C0 data I/O pin
I/O
O
I2C0_SDA
LCD_SEG24
ICE_DAT
PF.0
LCD segment output 24 at LQFP64
Serial Wired Debugger Data pin
General purpose digital I/O pin
External interrupt0 input pin
Serial Wired Debugger Clock pin
General purpose digital I/O pin
Frequency Divider output pin
External interrupt1 input pin
NC
I/O
I/O
I
41
42
INT0
I
ICE_CLK
PF.1
I/O
O
81
82
FCLKO
I
INT1
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
P
83
VDD
84
85
86
NC
P
P
VSS
VSS
Ground
Ground
AP
AP
I/O
AI
87
88
43
44
45
AVSS
Ground Pin for analog circuit
Ground Pin for analog circuit
General purpose digital I/O pin
ADC analog input0
AVSS
PA.0
89
90
AD0
I
SC2_CD
PA.1
SmartCard2 card detect
General purpose digital I/O pin
ADC analog input1
I/O
AI
AD1
I/O
I/O
AI
EBI_AD12
PA.2
EBI Address/Data bus bit12
General purpose digital I/O pin
ADC analog input2
AD2
I/O
I
91
46
EBI_AD11
UART1_RXD
LCD_SEG23*
PA.3
EBI Address/Data bus bit11
UART1 Data receiver input pin
LCD segment output 23 at LQFP64
General purpose digital I/O pin
ADC analog input3
AO
I/O
AI
AD3
I/O
O
92
47
EBI_AD10
UART1_TXD
LCD_SEG22*
PA.4
EBI Address/Data bus bit10
UART1 Data transmitter output pin
LCD segment output 22 at LQFP64
General purpose digital I/O pin
ADC analog input4
AO
I/O
AI
AD4
I/O
O
EBI_AD9
SC2_PWR
I2C0_SDA
LCD_SEG21*
LCD_SEG39*
PA.5
EBI Address/Data bus bit9
SmartCard2 Power pin
93
94
48
49
I2C0 data I/O pin
I/O
AO
AO
I/O
LCD segment output 21 at LQFP64
LCD segment output 39 at LQFP128
General purpose digital I/O pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
AI
I/O
O
AD5
ADC analog input5
EBI_AD8
SC2_RST
I2C0_SCL
LCD_SEG20*
LCD_SEG38*
PA.6
EBI Address/Data bus bit8
SmartCard2 RST pin
I2C0 clock pin
I/O
AO
AO
I/O
AI
LCD segment output 20 at LQFP64
LCD segment output 38 at LQFP128
General purpose digital I/O pin
ADC analog input6
AD6
I/O
I
EBI_AD7
TC3
EBI Address/Data bus bit7
Timer3 capture input
95
50
O
SC2_CLK
PWM0_CH3
LCD_SEG19*
LCD_SEG37*
PA.7
SmartCard2 clock pin(SC2_UART_TXD)
PWM0 Channel3 output
O
AO
AO
I/O
AI
LCD segment output 19 at LQFP64
LCD segment output 37 at LQFP128
General purpose digital I/O pin
ADC analog input7
AD7
I/O
I
EBI_AD6
TC2
EBI Address/Data bus bit6
Timer2 capture input
96
I/O
O
SC2_DAT
PWM0_CH2
LCD_SEG36*
VREF
SmartCard2 DATA pin(SC2_UART_RXD)
PWM0 Channel2 output
AO
AP
LCD segment output 36 output at LQFP128
Voltage reference input for ADC
NC
97
98
99
51
52
AP
I/O
I
AVDD
Power supply for internal analog circuit
General purpose digital I/O pin
UART1 Data receiver input pin
SPI2 1st slave select pin
PD.0
UART1_RXD
SPI2_SS0
SC1_CLK
AD8
I/O
O
100
101
SmartCard1 clock pin(SC1_UART_TXD)
ADC analog input8
AI
I/O
PD.1
General purpose digital I/O pin
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
O
I/O
I/O
AI
I/O
O
TX1
UART1 Data transmitter output pin
SPI2 serial clock pin
SPI2_CLK
SC1_DAT
AD9
SmartCard1 DATA pin(SC1_UART_RXD)
ADC analog input9
PD.2
General purpose digital I/O pin
UART1 Request to Send output pin
I2S left right channel clock
SPI2 1st MISO (Master In, Slave Out) pin
SmartCard1 Power pin
UART1_RTSn
I2S_LRCLK
SPI2_MISO0
SC1_PWR
AD10
I/O
I/O
O
102
AI
I/O
I
ADC analog input10
PD.3
General purpose digital I/O pin
UART1 Clear to Send input pin
I2S bit clock pin
UART1_CTSn
I2S_BCLK
SPI2_MOSI0
SC1_RST
AD11
I/O
I/O
O
103
SPI2 1st MOSI (Master Out, Slave In) pin
SmartCard1 RST pin
AI
ADC analog input11
104
105
NC
I/O
I
PD.4
General purpose digital I/O pin
I2S data input
I2S_DI
I/O
I
SPI2_MISO1
SC1_CD
LCD_SEG35
PD.5
SPI2 2nd MISO (Master In, Slave Out) pin
SmartCard1 card detect
AO
I/O
O
LCD segment output 35 at LQFP128
General purpose digital I/O pin
I2S data output
I2S_DO
106
SPI2 2nd MOSI (Master Out, Slave In) pin
LCD segment output 34 at LQFP128
General purpose digital I/O pin
DAC 1 output
I/O
AO
I/O
AO
I/O
I
SPI2_MOSI1
LCD_SEG34
PC.7
DA1_OUT
EBI_AD5
TC1
107
53
EBI Address/Data bus bit5
Timer1 capture input
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
O
AO
I/O
I
PWM0_CH1
LCD_SEG17*
PC.6
PWM1 Channel1 output
LCD segment output 17 at LQFP64
General purpose digital I/O pin
DAC0 output
DA0_OUT
EBI_AD4
TC0
I/O
I
EBI Address/Data bus bit4
Timer0 capture input
108
54
SC1_CD
SmartCard1 card detect pin
PWM0 Channel0 output
O
I/O
I/O
I
PWM0_CH0
PC.15
General purpose digital I/O pin
EBI Address/Data bus bit3
Timer0 capture input
EBI_AD3
TC0
109
110
111
55
56
57
O
PWM1_CH2
LCD_SEG16
LCD_SEG33
PC.14
PWM1 Channel1 output
AO
AO
I/O
I/O
I/O
AO
AO
I/O
I
LCD segment output 16 at LQFP64
LCD segment output 33 at LQFP128
General purpose digital I/O pin
EBI Address/Data bus bit2
PWM1 Channel3 output
EBI_AD2
PWM1_CH3
LCD_SEG15
LCD_SEG32
PB.15
LCD segment output 15 at LQFP64
LCD segment output 32 at LQFP128
General purpose digital I/O pin
External interrupt1 input pin
Snooper pin
INT1
I
SNOOPER
SC1_CD
I
SmartCard1 card detect
AO
AO
LCD_SEG14
LCD_SEG31
LCD segment output 14 at LQFP64
LCD segment output 31 at LQFP128
NC
112
113
O
I/O
I
XT1_IN
PF.3
External 4~24 MHz crystal output pin
General purpose digital I/O pin
External 4~24 MHz crystal input pin
General purpose digital I/O pin
58
59
XT1_OUT
PF.2
114
I/O
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NUMICRO® NANO100 (B) DATASHEET
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
128-pin 64-pin 48-pin
115
NC
External reset input: Low active, set this pin low reset
chip to initial state. With internal pull-up.
I
116
60
61
nRESET
P
P
117
118
119
VSS
VSS
Ground
Ground
NC
Power supply for I/O ports and LDO source for
internal PLL and digital circuit
P
120
121
62
VDD
NC
I/O
I/O
I/O
I/O
P
PF.4
General purpose digital I/O pin
I2C0 data I/O pin
122
123
I2C0_SDA
PF.5
Digital GPI/O pin
I2C0_SCL
VSS
I2C0 clock pin
124
125
Ground
I/O
I/O
I
63
64
PVSS
PLL Ground
PB.8
General purpose digital I/O pin
ADC external trigger input.
Timer0 external counter input
External interrupt0 input pin
SmartCard2 Power pin
LCD segment output 13 at LQFP64
LCD segment output 30 at LQFP128
General purpose digital I/O pin
LCD segment output 29 at LQFP128
General purpose digital I/O pin
LCD segment output 28 at LQFP128
STADC
TM0
I
I
126
127
INT0
O
SC2_PWR
LCD_SEG13
LCD_SEG30
PE.15
AO
AO
I/O
O
LCD_SEG29
PE.14
I/O
O
128
LCD_SEG28
Note:
1. Pin Type: I=Digital Input, O=Digital Output; AI=Analog Input; AO=Analog Output; P=Power Pin; AP=Analog Power
2. * : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are without 5V tolerance.
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4
BLOCK DIAGRAM
4.1 Nano100 Block Diagram
LXT
LIRC
FLASH
123/64/
32 KB
P
L
L
Cortex-M0
42 MHz
DMA
EBI
CLK_CTL
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
SRAM
16/8 KB
ISP 4KB
GPIO
A,B,C,D,E,F
12-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
12-b DAC
PWM 0
1.8/2.5V REF
Timer 0/1
UART 0
SPI 0
TEMP Sensor
I2S
SPI 2
SC 0/UART3
SC 1/UART4
SC 2/UART5
RTC
WDT
Peripherals with PDMA
Peripherals with wake-up
NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too.
Figure 4‑1 NuMicro® Nano100 Block Diagram
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4.2 Nano110 Block Diagram
LXT
LIRC
FLASH
123/64/
32 KB
P
L
L
Cortex-M0
42 MHz
DMA
EBI
CLK_CTL
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB
GPIO
SRAM
A,B,C,D,E,F
16/8 KB
12-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
12-b DAC
PWM 0
1.8/2.5V REF
Timer 0/1
UART 0
SPI 0
TEMP Sensor
LCD Booster
LCD COM/SEG
Up to
I2S
SPI 2
LCD
4x40/6x38
SC 0/UART3
SC 1/UART4
SC 2/UART5
RTC
WDT
Peripherals with PDMA
Peripherals with wake-up
NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too.
Figure 4‑2 NuMicro® Nano110 Block Diagram
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4.3 Nano120 Block Diagram
LXT
LIRC
FLASH
123/64/
32 KB
P
L
L
Cortex-M0
42 MHz
DMA
EBI
CLK_CTL
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB
GPIO
SRAM
A,B,C,D,E,F
16/8 KB
12-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
12-b DAC
PWM 0
1.8/2.5V REF
Timer 0/1
UART 0
SPI 0
TEMP Sensor
USB PHY
I2S
SPI 2
SC 0/UART3
SC 1/UART4
SC 2/UART5
RTC
USB -512B
WDT
Peripherals with PDMA
Peripherals with wake-up
NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too.
Figure 4‑3 NuMicro® Nano120 Block Diagram
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4.4 Nano130 Block Diagram
LXT
LIRC
FLASH
123/64/
32 KB
P
L
L
Cortex-M0
42 MHz
DMA
EBI
CLK_CTL
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB
GPIO
SRAM
A,B,C,D,E,F
16/8 KB
12-b ADC
I2C 1
PWM 1
Timer 2/3
UART 1
SPI 1
I2C 0
12-b DAC
PWM 0
1.8/2.5V REF
Timer 0/1
UART 0
SPI 0
TEMP Sensor
LCD Booster
LCD COM/SEG
Up to
I2S
SPI 2
LCD
4x40/6x38
SC 0/UART3
SC 1/UART4
SC 2/UART5
RTC
USB -512B
USB PHY
WDT
Peripherals with PDMA
Peripherals with wake up
NOTE: BOD can wake up system.
External interrupts, included in GPIO, can wake up system, too.
Figure 4‑4 NuMicro® Nano130 Block Diagram
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5
FUNCTIONAL DESCRIPTION
5.1 Memory Organization
5.1.1 Overview
The Nano100 provides 4G-byte addressing space. The memory locations assigned to each on-
chip modules are shown in following. The detailed register definition, memory space, and
programming detailed will be described in the following sections for each on-chip module. The
Nano100 series only supports little-endian data format.
5.1.2 Memory Map
The memory locations assigned to each on-chip controllers are shown in the following table.
Address Space
Token
Modules
Flash & SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
0x6000_0000 --- 0x6001_FFFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128KB)
SRAM Memory Space (16KB)
External Memory Space(128KB)
EXTMEM_BA
AHB Modules Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
GCR_BA
CLK_BA
INT_BA
System Management Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
DMA_BA
FMC_BA
EBI_BA
DMA Control Registers
Flash Memory Control Registers
External Bus Interface Control Registers
APB1 Modules Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x400A_0000 – 0x400A_3FFF
0x400B_0000 – 0x400B_3FFF
0x400D_0000 – 0x400D_3FFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0 and Timer1 Control Registers
I2C0 Interface Control Registers
TMR01_BA
I2C0_BA
SPI0_BA
PWM0_BA
UART0_BA
USBD_BA
DAC_BA
LCD_BA
SPI0 with Master/Slave function Control Registers
PWM0 Control Registers
UART0 Control Registers
USB FS device Controller Registers
Digital-Analog-Converter (DAC) Control Registers
LCD Control Registers
SPI2_BA
SPI2 with Master/Slave function Control Registers
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0x400E_0000 – 0x400E_3FFF
ADC12_BA
12-bit Analog-Digital-Converter (ADC12) Control
Registers
APB2 Modules Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4013_0000 – 0x4013_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x4019_0000 – 0x4019_3FFF
0x401A_0000 – 0x401A_3FFF
0x401B_0000 – 0x401B_3FFF
0x401C_0000 – 0x401C_3FFF
TMR23_BA
I2C1_BA
SPI1_BA
PWM1_BA
UART1_BA
SC0_BA
Timer2 and Timer3 Control Registers
I2C1 Interface Control Registers
SPI1 with Master/Slave function Control Registers
PWM1 Control Registers
UART1 Control Registers
SmartCard0 Control Registers
I2S Control Registers
I2S_BA
SC1_BA
SmartCard1 Control Registers
SmartCard2 Control Registers
SC2_BA
System Control Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
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5.2 Nested Vectored Interrupt Controller (NVIC)
5.2.1 Overview
The Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and
provides following features:
5.2.2 Features
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Dynamic priority changing
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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5.3 System Manager
5.3.1 Overview
System manager mainly controls the power modes, wake-up source, system resets and system
memory map. It also provides information about product ID, chip reset, IP reset, and multi-function pin
control.
5.3.2 Features
Power modes and wake-up sources
System resets
System Memory Map
System manager registers for :
Product ID
Chip and IP reset
Multi-functional pin control
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5.4 Clock Controller
5.4.1 Overview
The clock controller generates clocks for the whole chip, Iincluding system clocks (CPU clock,
HCLKx, and PCLKx) and all peripheral engine clocks. HCLKx means AHB bus clock for
peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. The clock
controller also implements the power control function with the individually clock ON/OFF control,
clock source selection and a 4-bit clock divider. The chip will not enter power-down mode until
CPU sets the power down enable bit (PD_EN) and CPU executes the WFI instruction. In the
Power-down mode, clock controller turns off the external high frequency crystal, internal high
frequency oscillator, and system clocks (CPU clock, HCLKx, and PCLKx) to reduce the power
consumption to minimum.
5.4.2 Features
Generates clocks for system clocks and all peripheral engine clocks.
Each peripheral engine clock can be turned on/off.
High frequency crystal, internal high frequency oscillator, and system clocks will be
turned off when chip is in Power-down mode.
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5.5 Analog to Digital Converter (ADC)
5.5.1 Overview
This chip contains one 12-bit successive approximation analog-to-digital converter (SAR A/D
converter) with 12 external input channels and 6 internal channels. The A/D converter supports
three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started
by software and external STADC/PB.8 pin and timer event start.
Note that the I/O pins used as ADC analog input pins must be configured as input type and off
digital function (GPIOA_OFFD) should be turned on before ADC function is enabled.
5.5.2 Features
Analog input voltage range: 0~Vref (Max to 3.6V)
Selectable 12-bits, 10-bits, 8-bits and 6-bits resolution
Supports sampling time settings (in ADC_CLK unit) for channel 0~11 individually and
channel 12~17 share the same one sampling time setting
Supports two power-down modes:
Power-down mode
Standby mode
Up to 12 external analog input channels (channel0 ~ channel11), and 6 internal
channels (channel12~channel17) converting six voltage sources, including DAC0,
DAC1, internal band-gap voltage, internal temperature sensor output, AVDD, and
AVSS.
Maximum ADC clock frequency is 42 MHz and each conversion is 19 clocks+
sampling time depending on the input resistance.
Three operating modes
Single mode: A/D conversion is performed one time on a specified channel.
Single-cycle Scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the lowest numbered channel to the highest
numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion.
An A/D conversion can be started by:
Software write 1 to ADST bit
External pin STADC
Selects one from four timer events (TMR0, TMR1, TMR2 and TMR3) that enable
ADC and transfer AD results by PDMA
Conversion results held in data registers for each channel
Conversion result can be compared with a specified value and user can select
whether to generate an interrupt when conversion result is equal to the compare
register setting.
Supports Calibration and load Calibration words capability.
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5.6 Digital to Analog Converter (DAC)
5.6.1 Overview
DAC is a 12-bit voltage-output digital-to-analog converter. Two DACs are implemented in this
chip.
5.6.2 Features
DAC is a 12-bit voltage-output DAC. DAC can use in conjunction with the PDMA controller. When
two DACs are present, they may be grouped together for synchronous update operation.
Features:
Int_VREF or VREF or AVDD reference voltage selection
Synchronized update capability for two DACs
DAC maximum conversion rate is 500 KSPS
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5.7 DMA Controller
5.7.1 Overview
The DMA controller contains six channel peripheral direct memory access (PDMA) controllers, a
video direct memory access (VDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA controller can transfer data to and from memory or transfer data to and from APB
devices. The DMA has eight channels of DMA including one channel VDMA (Memory-to-Memory)
and six channels PDMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory)
and a CRC controller. For channel0 VDMA, it supports block transfer from memory to memory.
For PDMA channel (DMA CH1~CH6), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. And for channel 0 VDMA, there is a two-word buffer.
Software can stop the DMA operation by disable PDMA [PDMACEN]/VDMA [VDMACEN].
Software can recognize the completion of a DMA operation by software polling or when it receives
an internal DMA interrupt. The DMA controller can increase source or destination address, fixed
or wrap around them as well.
The DMA controller also contains a cyclic redundancy check (CRC) generator that can perform
CRC calculation with programmable polynomial settings. The CRC engine support CPU PIO
mode and DMA transfer mode.
5.7.2 Features
Seven DMA channels and a CRC generator: 1 VDMA channel and 6 PDMA channels. Each
channel can support a unidirectional transfer.
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Hardware round robin priority scheme.
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-to-memory
and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed, and wrap around
Cyclic Redundancy Check (CRC)
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 +
X2 + X + 1
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Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC
checksum
Supports CPU PIO mode or DMA transfer mode
Supports 8/16/32-bit of data width in CPU PIO mode
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports byte alignment transfer length in CRC DMA mode
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5.8 External Bus Interface
5.8.1 Overview
This chip is equipped with an external bus interface (EBI) to access external device. To save the
connections between external device and this chip, EBI support address bus and data bus
multiplex mode. Also, address latch enable (ALE) signal is used to differentiate the address and
data cycle.
5.8.2 Features
External devices with max. 64 Kbytes size (8-bit data width)/128 Kbytes (16-bit data
width) supported
Supports variable external bus base clock (MCLK)
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Address bus and data bus multiplex mode supported to save the address pins
Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R), Read-to-Write (R2W)
Supports PDMA and VDMA transfer
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5.9 FLASH Memory Controller (FMC)
5.9.1 Overview
This chip is equipped with 32K/64K/123K bytes on-chip embedded Flash EPROM for application
program memory (APROM) that can be updated through ISP/IAP procedure. In System
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip powered on Cortex-M0 CPU fetches code from APROM or LDROM decided by
boot select (CBS) in Config0. By the way, this chip also provides DATA Flash Region, the data
flash is shared with original program memory and its start address is configurable and defined by
user in Config1. The data flash size is defined by user application request.
5.9.2 Features
AHB interface compatible
Run up to 42 MHz with zero wait state for discontinuous address read access
32/64/123KB application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page erase
unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
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5.10 General Purpose I/O Controller
5.10.1 Overview
Up to 86 General Purpose I/O pins can be shared with other function pins; it depends on the chip
configuration. These 86 pins are arranged in 6 ports named with GPIOA, GPIOB, GPIOC,
GPIOD, GPIOE and GPIOF. Ports A ~ E have the maximum of 16 pins while port F have 6 pins.
Each one of the 86 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be independently software configured as input, output, and
open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110
K~300 K for VDD from 1.8 V to 3.6 V.
5.10.2 Features
Up to 86 general purpose I/O pins
Supports Input, Output, Open-drain Operation mode
Programmable de-bounce timing
Each I/O pin can be programmed as either edge-trigger or level-sensitive
Each I/O pin can be programmed as either low-level active or high-level active
Each I/O pin can be programmed as either falling-edge trigger or rising-edge trigger
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5.11 I2C
5.11.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1.0
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte.
A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL.
The controller’s on-chip I2C logic provides the serial interface that meets the I2C bus standard
mode specification. The I2C controller handles byte transfers autonomously. Pull up resistor is
needed for I2C operation as these are open drain pins.
The I2C controller is equipped with two slave address registers. The contents of the registers are
irrelevant when I2C is in Master mode. In the Slave mode, the seven most significant bits must be
loaded with the user’s own slave address. The I2C hardware will react if the contents of I2CADDR
are matched with the received slave address.
This controller supports the “General Call (GC)” function. If the GC bit is set this controller will
respond to General Call address (00H). Clear GC bit to disable general call function. When GC bit
is set and the I2C is in Slave mode, it can receive the general call address which is equal to 00H
after master sends general call address to the I2C bus, then it will follow status of GC mode. If it is
in Master mode, the ACK bit must be cleared when it sends general call address of 00H to the I2C
bus.
The I2C-bus controller supports multiple address recognition with two address mask register.
When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to zero, that means the received corresponding register
bit should be exact the same as address register.
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5.11.2 Features
Acts as Master or Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
One built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
Programmable clock divider allows versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( Two slave addresses with mask option)
Supports Power-down wake-up function
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5.12 I2S
5.12.1 Overview
The audio controller consists of I2S protocol to interface with external audio CODEC. Two 8 word
deep FIFO for receiving path and transmitting path respectively and is capable of handling 8 ~ 32
bit word sizes. PDMA controller handles the data movement between FIFO and memory.
5.12.2 Features
I2S can operate as either master or Slave mode.
Capable of handling 8, 16, 24 and 32 bits word sizes.
Mono and stereo of audio data are supported.
I2S and MSB justified data format are supported.
Two FIFO data buffers (each 32 bits) are provided, one is for transmitting and the other is for
receiving.
Generate interrupt when buffer levels cross a programmable boundary.
Two PDMA channels request, one is for transmitting and the other is for receiving.
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5.13 LCD Display Driver
5.13.1 Overview
The LCD driver can directly drive a LCD glass by creating the ac segment and common voltage
signals automatically. It can support static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty LCD
glass with up to 38 segments with 6 COM (segment 0 is used as LCD_COM4 and segment 1 is used
as LCD_COM5) or 40 segments with 4 COM (LCD_COM0 ~ LCD_COM3).
A built-in charge pump function can be enabled to provide the LCD glass with higher voltage than the
system voltage. The LCD driver would generate voltage higher than the threshold voltage in older to
darken a segment and a voltage lower than threshold to make a segment clear. However, the LCD
display segment will degrade if the applied voltage has a DC-component. To avoid this, the generated
waveform by LCD driver are arranged such that average voltage of each segment is zero and the
RMS(root-mean-square) voltage applied on a LCD segment lower than the segment threshold making
LCD clear and RMS voltage higher than the segment threshold making LCD dark.
Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are
without 5V tolerance.
(LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23)
(LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39)
5.13.2 Features
Supports up to 174 dots (6x29) or 124 dots (4x31) in LQFP64 package and 228 dots
(6x38) or 160 dots (4x40) in LQFP100/LQFP128 package Segment/Com pins:
Common 0-5 multiplexing functions with GPI/O pins
Segment 0-39 multiplexing function with GPI/O pins
Supports Static,1/2 bias and 1/3 bias voltage
Six display modes: Static,1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty or 1/6 duty Selectable
LCD frequency by frequency divider
Configurable frame frequency
Internal Charge pump, adjustable contrast adjustment
Embedded LCD bias reference ladder (R-Type, 200kΩ resisters)
Configurable Charge pump frequency
Blinking capability
Supports R/C-type method
LCD frame interrupt
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5.14 Pulse Width Modulation (PWM)
5.14.1 Overview
This chip has two PWM controllers, each controller has 4 independent PWM outputs, CH0~CH3,
or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone
generators.
Each two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock divider
providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent 16-bit
PWM down-count counter for PWM period control, and 16-bit comparators for PWM duty control.
Each dead-zone generator has two outputs. The first dead-zone generator output is CH0 and
CH1, and for the second dead-zone generator, the output is CH2 and CH3. The 2 sets of PWM
controller total provide eight independent PWM interrupt flags which are set by hardware when
the corresponding PWM period down counter reaches zero. PWM interrupt will be asserted when
both PWM interrupt source and its corresponding enable bit are active. Each PWM output can be
configured as one-shot mode to produce only one PWM cycle signal or continuous mode to
output PWM waveform continuously.
When DZEN01 of PWMx_CTL is set, CH0 and CH1 perform complementary PWM paired
function; the paired PWM timing, period, duty and dead-time are determined by PWM channel 0
timer and Dead-zone generator 0. Similarly, When DZEN23 of PWMx_CTL is set the
complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM
output is set as continuous mode, when the down counter reaches zero, it is reloaded with CN of
PWMx_DUTYy(y=0~3) Register automatically then start decreases, repeatedly. If the PWM
output is set as one-shot mode, the down counter will stop and generate one interrupt request
when it reaches zero.
The value of PWM counter comparator is used for pulse width modulation. The counter control
logic changes the output level when down-counter value matches the value of compare register.
The alternate feature of the PWM is digital input capture function. If capture function is enabled
the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share
one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user
must setup the PWM timer before enabling capture feature. After capture feature is enabled, the
capture always latches PWM timer to Capture Rising Latch Register (PWMx_CRLy) where
y=0~3, when input channel has a rising transition and latches PWM timer to Capture Falling Latch
Register (PWMx_CFLy) where y=0~3, when input channel has a falling transition. Capture
channel 0 interrupt is programmable by setting PWMx_CAPINTEN. Whenever Capture event
latched for channel 0/1/2/3, the PWM timer 0/1/2/3 will be reload at this moment if the
corresponding reload enable bit specified in CAPCTL are set.
The maximum captured frequency that PWM can capture is dominated by the capture interrupt
latency. When capture interrupt occurs, software will do at least three steps, they are:
Read PWMINTSTS to tell it from interrupt source and Read PWMx_CRLy/PWMx_CFLy(y=0~3) to
get capture value and finally write 1 to clear PWMx_INTSTS. If interrupt latency will take time T0
to finish, the capture signal mustn’t transient during this interval. In this case, the maximum
capture frequency will be 1/T0.
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5.14.2 Features
5.14.2.1 PWM Function:
Two PWM controllers, each controller having 4 independent PWM outputs,
CH0~CH3, or as 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2
programmable dead-zone generators
Up to 8 PWM channels or 4 PWM paired channels
Up to 16 bits PWM counter width
PWM Interrupt request synchronous with PWM period
Single-shot or Continuous mode
Four Dead-Zone generators
5.14.2.2 Capture Function:
Timing control logic shared with PWM timer.
8 Capture input channels shared with 8 PWM output channels.
Each channel supports one rising latch register (PWMx_CRLy), one falling latch
register (PWMx_CFLy) and Capture interrupt flag (CAPIFy) where x=0~1,y=0~3.
Eight 16-bit counters for eight capture channels or four 32-bit counter for four capture
channels when cascade is enabled: when CH01CASKEN is set, the original 16-bit
counter of channel 1 will combine with channel 0’s 16 bit counter for channel 0 input
capture counting and so does CH23CASKEN for channel 2, 3
Supports PDMA transfer function for PWMx channel 0, 2
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5.15 RTC
5.15.1 Overview
Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source
of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference to pin
Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit
provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as
calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is
expressed in BCD format. This unit offers alarm function that user can preset the alarm time in
Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR).
The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has
8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR
(TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and
CAR, the alarm interrupt status (RIIR.AIS) is set and the alarm interrupt is requested if the alarm
interrupt is enabled (RIER.AIER=1). The RTC Time Tick (if wake-up CPU function is enabled,
RTC_TTR[TWKE] high) and Alarm Match can cause CPU wake-up from idle or Power-down
mode.
5.15.2 Features
One time counter (second, minute, hour) and calendar counter (day, month, year) for
user to check the time
Alarm register (second, minute, hour, day, month, year)
12-hour or 24-hour mode is selectable
Leap year compensation automatically
Day of week counter
Frequency compensate register (FCR)
All time and calendar message is expressed in BCD code
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports wake-up CPU from Power-down mode
Supports 80 bytes spare registers and a snoop pin to clear the content of these spare
registers
5.16 Smart Card Host Interface (SC)
5.16.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.16.2 Features
ISO-7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Supports up to three ISO-7816-3 ports
Separates receive / transmit 4 byte entry buffer for data payloads
Programmable transmission clock frequency
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Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit counters for Answer to Reset (ATR) and waiting times
processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error number limitation function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal.
Support UART mode
Half duplex, asynchronous communications
Separate receiving / transmitting 4 bytes entry FIFO for data payloads
Support programmable baud rate generator for each channel
Support programmable receiver buffer trigger level
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
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5.17 SPI
5.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol.
Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to
perform a serial-to-parallel conversion on data received from a peripheral device, and a parallel-
to-serial conversion on data transmitted to a peripheral device. The SPI controller can be
configured as a master or a slave devicee.
The SPI controller supports wake-up function. When this chip stays in power-down mode, it can
be waked up chip by off-chip device.
This controller supports variable serial clock function for special application and 2-bit transfer
mode to connect 2 off-chip slave devices at the same time. The SPI controller also supports
PDMA function to access the data buffer.
5.17.2 Features
Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation
Supports 1 bit and 2 bit transfer mode
Support Dual IO transfer mode
Configurable bit length of a transaction from 8 to 32-bit
Supports MSB first or LSB first transfer sequence
Two slave select lines supported in Master mode
Configurable byte or word suspend mode
Supports byte re-ordering function
Supports variable serial clock in Master mode
Provide separate 8-level depth transmit and receive FIFO buffer
Supports wake-up function
Supports PDMA transfer
Supports three wires, no slave select signal, bi-direction interface
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5.18 Timer Controller
5.18.1 Overview
This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3
(TIMER0/1 is at APB1 and TIMER2/3 is at APB2), which allow user to easily implement a
counting scheme or timing control for applications. The timer can perform functions like frequency
measurement, event counting, interval measurement, clock generation, delay timing, and so on.
The timer can generate an interrupt signal upon timeout, or provide the current value of count
during operation.
5.18.2 Features
Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3)
Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Counting cycle time = (1 / TMRx_CLK) * (2^8) * (2^24)
Internal 8-bit pre-scale counter
Internal 24-bit up counter is readable through TDR (Timer Data Register)
Supports One-shot, Periodic,Output Toggle and Countinuous Counting Operation
mode
Supports external pin capture for interval measurement
Supports external pin capture for timer counter reset
Supports Inter-Timer trigger
Supports Internal trigger event to ADC, DAC and PDMA
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5.19 UART Controller
5.19.1 Overview
The UART controllers provides up to two channels of Universal Asynchronous
Receiver/Transmitter (UART) modules that are UART0 and UART1. (UART0 is at APB1 and
UART1 is at APB2).
The Universal Asynchronous Receiver/Transmitter (UART) performs
a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA (SIR) function mode, LIN
Master/Slave function mode and RS-485 function mode. Each UART channel supports nine types
of interrupts including receiver threshold level reaching interrupt (INT_RDA), transmitter FIFO
empty interrupt (INT_THRE), line status interrupt (break error, parity error, framing error or RS-
485 interrupt) (INT_RLS), time-out interrupt (INT_TOUT), MODEM status interrupt
(INT_MODEM), Buffer error interrupt (INT_BUF_ERR), wake-up interrupt (INT_WAKE), auto-
baud rate detect or auto-baud rate counter overflow flag (INT_ABAUD) and LIN function interrupt
(INT_LIN).
The UART0 and UART1 are built-in with a 16-byte transmitter FIFO (TX_FIFO) and a 16-byte
receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well
as 3 error conditions (parity error, framing error or break interrupt) occur while receiving data. The
UART controller supports auto-baud rate detection. The auto-baud rate detection controls the
process of measuring the incoming clock/data rate for the baud rate generation and can be read
and written at user discretion. The UART controller also support incoming data or CTSn wake-up
function. When the system is in power-down mode, an incoming data or CTSn signal will wake-up
CPU from power-down mode. The UART includes a programmable baud rate generator that is
capable of dividing crystal clock input by divisors to produce the clock that transmitter and
receiver need. The baud rate equation is Baud Rate = UART_CLK / [BRD + 1], where BRD are
defined in UART Baud Rate Divider Register (UARTx_BAUD). Below table lists the equations in
the various conditions and the UART baud rate setting table.
DIV_16_EN
BRD
A
Baud Rate Equation
Disable (Mode 0)
Enable (Mode 1)
UART_CLK / (A+1), A must >8
UART_CLK / [16 * (A+1)]
A
Table 5‑1 UART Baud Rate Equation
System clock =12 MHz
Baud rate
921600
Mode 0
A=12
Mode 1
Not Supported
Not Supported
A=2
460800
A=25
230400
A=51
115200
A=103
A=207
A=311
A=6
57600
A=12
38400
A=19
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19200
9600
4800
A=624
A=38
A=77
A=155
A=1249
A=2499
Table 5‑2 UART Baud Rate Setting
5.19.1.1 Auto-Flow Control
The UART0 and UART1 controllers support auto-flow control function that uses two low-level
signals, CTSn (clear-to-send) and RTSn (request-to-send) to control the flow of data transfer
between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is
not allowed to receive data until the UART asserts RTSn (RTSn high) to external device. When
the number of bytes in the RX-FIFO equals the value of UART_TLCTL [RTS_TRI_LEV], the
RTSn is de-asserted. The UART sends data out when UART controller detects CTSn is asserted
(CTSn high) from external device. If a valid asserted CTSn is not detected the UART controller
will not send data out.
5.19.1.2 Auto-Baud Rate Detection
The UART0 and UART1 controllers support auto-baud rate detection. The auto-baud rate function
can be used to measure the receiver incoming data baud rate. If enabled the auto-baud feature,
UART controller will measure the bit time of the received data stream and set the divisor latch
registers UART_BARD. Auto-baud rate detection is started by setting the UART_CTL
[ABAUD_EN].
5.19.1.3 UART Wake-Up Function
The UART0 and UART1 controllers support wake-up system function. The wake-up function
includes CTSn wake-up function (UART_CTL [WAKE_CTS_EN]) and data wake-up function
(UART_CTL [WAKE_DATA_EN]). When the system is operation in power-down mode, the UART
can wake-up system by CTSn pin or by incoming data.
5.19.1.4 IrDA Function Mode
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
UART_FUN_SEL to select IrDA function). The SIR specification defines a short-range infrared
asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. The
maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10 ms transfer
delay between transmission and reception, and in IrDA Operation mode the UART_BAUD setting
must be mode1 (UART_BAUD [DIV_16_EN] = “1”).
5.19.1.5 RS-485 Function Mode
Another alternate function of UART controllers is RS-485 9 bit mode function whose direction
control can be controlled by RTSn pin or GPIO. The RS-485 function mode is selected by setting
the UART_FUN_SEL register to select RS-485 function. The RS-485 driver control is
implemented by using the RTSn control signal from an asynchronous serial port to enable the RS-
485 driver. In RS-485 mode, many characteristics of the RX and TX are same as UART.
5.19.1.6 LIN Function Mode
5.19.2 The LIN mode is selected by setting the LIN_EN bit in UART_FUN_SEL register. In
LIN mode, one start bit and 8-bit data format with 1-bit stop bit are required in
accordance with the LIN standard. Features
Full duplex, asynchronous communications.
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Separate receiving / transmitting 16 bytes entry FIFO for data payloads.
Supports hardware auto-flow control/flow control function (CTSn, RTSn) and
programmable (CTSn, RTSn) flow control trigger level.
Supports programmable baud rate generator for each channel.
Supports auto-baud rate detect function.
Supports programmable receiver buffer trigger level.
Supports incoming data or CTSn to wake-up function.
Supports 9 bit receiver buffer time-out detection function.
All UART channels can be served by the PDMA controller.
Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting UART_TMCTL [DLY] register.
Supports break error, frame error, parity error and receiving / transmitting buffer
overflow detect function.
Fully programmable serial-interface characteristics:
Programmable number of data bit, 5, 6, 7, 8 character.
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection.
Programmable stop bit, 1, 1.5, or 2 stop bit generation.
Supports IrDA SIR function mode
Supports 3/16 bit period modulation.
Supports LIN function mode.
Supports LIN Master/Slave mode
Supports programmable break generation function for transmitter.
Supports break detect function for receiver.
Supports RS-485 function mode.
Supports RS-485 9bit mode.
Supports hardware or software controls RTSn or software control GPIO to
control transfer direction.
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5.20 USB
5.20.1 Overview
The USB controller is a USB 2.0 full-speed device controller. It is compliant with USB 2.0 full
speed device specification and supports control/bulk/interrupt/isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There is an internal 512-byte SRAM as data buffer in this controller. For IN token or OUT token
transfer, it is necessary to write data to SRAM or read data from SRAM through the APB
interface. Users need to allocate the effective starting address of SRAM for each endpoint buffer
through “buffer segmentation register (BUFSEG)”.
This device controller contains 8 configurable endpoints. Each endpoint can be configured as IN
or OUT endpoint. The function address of the device and endpoint number in each endpoint shall
be configured properly in advance for receiving or transmitting a data packet correctly. The
transmitting/receiving length in each endpoint is defined in maximum payload register (MXPLD)
and the handshakes between Host and Device are also handled by it.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of events
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables the DRVSE0 bit (USB_CTL[4]), the
USB controller will force USB_DP and USB_DM to level low and USB device function is disabled
(disconnected). After disable the DRVSE0 bit, USB_DP will be pulled high by internal pull-high
circuit then host will enumerate the USB device connection again.
Reference: Universal Serial Bus Specification Revision 2.0
5.20.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
Compliant with USB 2.0 Full-Speed specification.
Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS).
Supports Control/Bulk/Interrupt/Isochronous transfer type.
Supports suspend function when no bus activity existing for 3 ms.
Provide 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
512-byte SRAM buffer inside
Provide remote wake-up capability.
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5.21 Watchdog Timer Controller
5.21.1 Overview
The purpose of Watchdog Timer is to perform a system reset after the software running into a
problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up CPU from power-down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals.
5.21.2 Features
18-bit free running WDT counter for Watchdog timer time-out interval.
Selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.316
s (if WDT_CLK = 10 kHz).
Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz.
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5.22 Window Watchdog Timer Controller
5.22.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
5.22.2 Features
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable
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6
ARM® CORTEX™-M0 CORE
6.1 Overview
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M
profile processor. The profile supports two modes – Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The following figure shows the functional controller of processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
interface
BusMatrix
(DAP)
AHB- Lite
interface
Serial Wire or
JTAG debug port
Figure 6‑1 M0 Functional Block
6.2 Features
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
Supports little-endian data accesses
Capable of deterministic, fixed-latency, interrupt handling
Load/store-multiples and multi-cycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
32 external interrupt inputs, each with four levels of priority
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Dedicated Non-Maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Wake-up Interrupt Controller (WIC), providing Ultra-low Power Sleep mode
support
Debug support:
Four hardware breakpoints
Two watch points
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to
all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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7
APPLICATION CIRCUIT
7.1 LCD Charge Pump
7.1.1 C-type 1/3 Bias
VLC
D
DH
1
0.1uF
0.1uF
DH
2
V3
NANO130
0.1uF
V2
0.1uF
V1
0.1uF
7.1.2 C-type 1/2 Bias
DH
1
VLC
D
0.1uF
0.1uF
0.1uF
DH
2
V3
NANO130
V2
V1
0.1uF
0.1uF
7.1.3 Internal R-type
Nano110/130 series MCUs also support external R-type mode (bypass internal R) to reduce
current consumption. For external R-type application, VLCD is normally connected to system
VDD, or it can be connected to VDD through an external variable resistor (VR) which is used for
adjusting LCD contrast.
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VDD
VR
VLCD
DH1
DH2
200k
V3
NANO110
NANO130
200k
V2
200k
V1
7.1.4 External R-type
To reduce the current, the resistor ladder value can be increased. At some point, when the
resistor ladder value is increased, the contrast will become affected and the waveform shape will
be altered. Therefore, capacitors around 0.1uF should be chosen and place closed to resistor
ladder based on the contrast and size of the pixels on the glass.
VDD
VR
VLCD
V3
DH1
DH2
R1
R2
R3
NANO110
NANO130
V2
V1
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VDD
VR
VLCD
DH1
DH2
R1
R2
R3
0.1uF
NANO110
NANO130
V3
0.1uF
V2
V1
0.1uF
7.2 ADC Application Circuit
7.2.1 Voltage Reference Source
7.2.1.1 AVDD
NANO100
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AVDD
VREF
AVDD
M
U
X
ADC Vref
In Case
VREF = AVDD
1uF // 0.1F
REFSEL[1:0]
VREF
EXT_MODE=0
Int Vref
1uF // 0.1uF
REFSEL[1:0] of ADCR
AVDD as Voltage reference
AVSS
AVSS
00
01 Int. Vref as Voltage reference
10 Ext. VREF pin as Voltage reference
Reserve
11
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7.2.1.2 Vref Pin
NANO100
AD0
AD1
AVDD
AVDD
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
M
U
X
ADC Vref
In Case
VREF = AVDD
1uF // 0.1uF
VREF
REFSEL[1:0]
VREF
AVSS
EXT_MODE=0
Int Vref
1uF // 0.1uF
REFSEL[1:0] of ADCR
AVDD as Voltage reference
AVSS
00
01 Int. Vref as Voltage reference
10 Ext. VREF pin as Voltage reference
Reserve
11
7.2.1.3 Int Vref
NANO100
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AVDD
VREF
AVDD
M
U
X
ADC Vref
In Case
VREF = AVDD
1uF // 0.1uF
REFSEL[1:0]
VREF
AVSS
EXT_MODE=1
Int Vref
1uF // 0.1uF
REFSEL[1:0] of ADCR
AVDD as Voltage reference
AVSS
00
01 Int. Vref as Voltage reference
10 Ext. VREF pin as Voltage reference
Reserve
11
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7.3 DAC Application Circuit
7.3.1 Voltage Reference Source
7.3.1.1 AVDD
NANO100
AVDD
AVDD
M
U
X
DAC Vref
In Case
VREF = AVDD
1uF // 0.1uF
DAC1_out
DAC2_out
VREF
REFSEL[1:0]
VREF
EXT_MODE=0
Int Vref
1uF // 0.1uF
REFSEL[1:0] of DAC
AVSS
AVSS
00 Int. Vref as Voltage reference
01
10
Ext. VREF pin as Voltage reference
AVDD as Voltage reference
11 AVDD as Voltage reference
7.3.1.2 Vref Pin
NANO100
AVDD
VREF
AVDD
M
U
X
DAC Vref
In Case
VREF = AVDD
1uF // 0.1uF
DAC1_out
DAC2_out
REFSEL[1:0]
VREF
EXT_MODE=0
Int Vref
1uF // 0.1uF
REFSEL[1:0] of DAC
00 Int. Vref as Voltage reference
AVSS
AVSS
01
10
Ext. VREF pin as Voltage reference
AVDD as Voltage reference
11 AVDD as Voltage reference
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7.3.1.3 Int Vref
NANO100
AVDD
AVDD
M
U
X
DAC Vref
In Case
VREF = AVDD
1uF // 0.1uF
DAC1_out
DAC2_out
VREF
REFSEL[1:0]
VREF
AVSS
EXT_MODE=1
Int Vref
1uF // 0.1uF
REFSEL[1:0] of DAC
00 Int. Vref as Voltage reference
AVSS
01
10
Ext. VREF pin as Voltage reference
AVDD as Voltage reference
11 AVDD as Voltage reference
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7.4 Whole Chip Application Circuit
DVDD
R1
10K
0603R
SW1
TICE_RST
DVDD
DVDD
SW
C1
PUSH BUTTON
10uF/10V
TANT-A
CB3
0.1uF
C15
1uF
CB4
0.1uF
C0603
C0603
C0603
Reset Circuit
C13
0.1uF
C0603
C14
1uF
C0603
From ICE Bridge's USB Power
U1
DVDD
JP4
1
3
5
7
9
2
4
6
8
10
TICE_DAT
TICE_CLK
TICE_RST
1
2
3
4
5
6
7
8
9
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN96
PE.13
PA.7
PA.6
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
AVSS
AVSS
VSS
VSS
NC
PIN95
PIN94
PIN93
PIN92
PIN91
PIN90
PIN89
PIN88
PIN87
PIN86
PIN85
PIN84
PIN83
PIN82
PIN81
PIN80
PIN79
PIN78
PIN77
PIN76
PIN75
PIN74
PIN73
PIN72
PIN71
PIN70
PIN69
PIN68
PIN67
PIN66
PIN65
PB.14
PB.13
PB.12
NC
X32O
X32I
HEADER 5PX2
HEADER 5PX2
X32KO
X32KI
NC
PIN9
PA.11
PA.10
PA.9
PA.8
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO
NC
NC
VDD
NC
VSS
VSS
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
ICE Interface
DVDD
VDD
NC
ICE_CK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
TICE_CLK
TICE_DAT
NANO130_LQFP128
DVDD
DVDD
CB5
0.1uF
C0603
C2
PC.9
C3
R2
PC.10
PC.11
PC.12
PC.13
PE.0
PE.1
PE.2
XTAL2
XTAL1
10uF/10V
TANT-A
20pF
X2
33
0603C
12MHz
XTAL3-1
R4 0603R
1M/DNE
0603R
C5
PE.3
PE.4
VSS
20pF
0603C
DVDD
C7
CB2
0.1uF
C0603
X32KO
X32KI
6pF
0603C
X1
32.768KHz
XTAL3-1
C8
C12
1uF
C9
0.1uF
C10
1uF
6pF
0603C
C0603
C0603
C0603
Crystal
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8
POWER COMSUMPTION
Part No
Test Condition
VDD
3.3V
1.8V
3.3V
1.8V
CPU Clock
12 MHz
12 MHz
12 MHz
12 MHz
Current
2.41mA
200uA/MHz
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12 MHz Crystal Oscillator
Disable all peripherial
N/A
900uA
75uA/MHz
Idle Mode:
CPU stop
Clock = 12 MHz Crystal Oscillator
Disable all peripherial
N/A
10uA
8.5uA
4.5uA
N/A
RTC + LCD Mode:
(RAM retention)
C-type
(Power down with 32K
and LCD enabled)
CPU stop
Clock = 32.768 kHz
Crystal Oscillator
Disable all peripherial
except RTC and LCD
circuit
Internal R-type
( With 200kΩ
Resistor ladder )
3.3V
-
External R-type
( With 1MΩ
Resistor ladder )
Nano100 (B)
series
128 KB Flash
16 KB RAM
C-type/R-type
1.8V
3.3V
-
-
Without panel loading
RTC Mode: (RAM retention)
(Power down with 32K enabled)
CPU stop
Clock = 32.768 kHz Crystal Oscillator
Disable all peripherial except RTC circuit
2.5uA
2.0uA
1.8V
-
3.3V
1.8V
3.3V
-
-
1uA
0.8uA
N/A
Power-down Mode: (RAM retention)
CPU and all clocks stop
Wake-Up from Power-down Mode
7us
Note: Wake-up time: 7us from wake-up event to first CPU core valid clock; 10us from interrupt event
to interrupt service routine first instruction.
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9
ELECTRICAL CHARACTERISTIC
9.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
PARAMETER
VDDVSS
VIN
MIN
-0.3
MAX
+4.0
UNIT
V
V
Input Voltage on 5V Tolerance Pin
VSS -0.3
VDD +3.7
Input Voltage on Any Other Pin without 5V
Tolerance Pin
VIN
VSS -0.3
VDD +0.3
V
Oscillator Frequency
1/tCLCL
TA
4
24
+85
+150
150
150
25
MHz
C
Operating Temperature
-40
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
Maximum Current Sunk by Total I/O Pins
Maximum Current Sourced by Total I/O Pins
25
100
100
Note : Output voltage for ADC/LCD shared pins cannot be higher than VDD because these pins are
without 5V tolerance.
(LQFP64 : LCD_SEG17, LCD_SEG19, LCD_SEG20, LCD_SEG21, LCD_SEG22, LCD_SEG23)
(LQFP128 : LCD_SEG36, LCD_SEG37, LCD_SEG38, LCD_SEG39)
9.2 Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP. MAX. UNIT
Operation voltage
Power Ground
VDD
1.8
-
-
3.6
V
V
V
V
VDD =1.8V up to 42 MHz
VSS
-0.3
1.62
1.49
AVSS
VLDO1
1.8
1.66
1.98
1.83
MCU operating in Run or Idle mode
MCU operating in Power-down mode
LDO Output Voltage
VLDO2
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Analog Operating
Voltage
AVDD
Vref
VDD
V
V
Reference Voltage
1.8
AVDD
Run Mode
CPU run while(1) in FLASH ROM
Clock = 12 MHz Crystal Oscillator
Disable all peripherial
at IRC = 12 MHz
Crystal Oscillator
Disable all peripherial
VDD = 3.6V at 42 MHz,
all IP and PLL enabled [*5]
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
20.5
10.6
19.1
10.3
16.2
8.3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 3.6V at 42 MHz
Operating Current
Run Mode
all IP disabled and PLL enabled
at XTAL 12 MHz,
HCLK = 42 MHz
VDD = 1.8V at 42 MHz
all IP and PLL enabled [*5]
VDD = 1.8V at 42 MHz
all IP disabled and PLL enabled
VDD = 3.6V at 32 MHz,
all IP and PLL enabled [*5]
VDD = 3.6V at 32 MHz
Operating Current
Run Mode
all IP disabled and PLL enabled
at XTAL 12 MHz,
HCLK = 32 MHz
VDD = 1.8V at 32 MHz
all IP and PLL enabled [*5]
15.3
8.0
VDD = 1.8V at 32 MHz
all IP disabled and PLL enabled
VDD = 3.6V at 12 MHz,
6.4
all IP enabled and PLL disabled
VDD = 3.6V at 12 MHz,
all IP and PLL disabled
Operating Current
Run Mode
2.8
at XTAL 12 MHz,
HCLK = 12 MHz
VDD = 1.8V at 12 MHz,
6.3
all IP enabled and PLL disabled
VDD = 1.8V at 12 MHz,
all IP and PLL disabled
2.8
Operating Current
Run Mode
VDD = 3.6V at 12 MHz,
6.7
all IP enabled and PLL disabled
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN.
at IRC 12 MHz,
HCLK = 12 MHz
VDD = 3.6V at 12 MHz,
IDD14
IDD15
IDD16
IDD17
IDD18
IDD19
IDD20
IDD21
IDD22
IDD23
IDD24
IDD25
IDD26
IDD27
IDD28
IIDLE1
IIDLE2
3.0
6.6
3.0
3.3
1.3
3.2
1.3
82
mA
mA
mA
mA
mA
mA
mA
uA
all IP and PLL disabled
VDD = 1.8V at 12 MHz,
all IP enabled and PLL disabled
VDD = 1.8V at 12 MHz,
all IP and PLL disabled
VDD = 3.6V at 4 MHz,
all IP enabled and PLL disabled
VDD = 3.6V at 4 MHz,
all IP and PLL disabled
Operating Current
Run Mode
at XTAL 4 MHz,
HCLK = 4 MHz
VDD = 1.8V at 4 MHz,
all IP enabled and PLL disabled
VDD = 1.8V at 4 MHz,
all IP and PLL disabled
VDD = 3.6V at 32.768 kHz
all IP enabled and PLL disabled,
VDD = 3.6V at 32.768 kHz
all IP and PLL disabled
Operating Current
Run Mode
74
uA
at XTAL 32.768 kHz,
HCLK = 32.768 kHz
VDD = 1.8V at 32.768 kHz
77
uA
all IP enabled and PLL disabled
VDD = 1.8V at 32.768 kHz
all IP and PLL disabled
68
uA
VDD = 3.6V at 10 kHz
70
uA
all IP enabled and PLL disabled
VDD = 3.6V at 10 kHz
all IP and PLL disabled
Operating Current
Run Mode
68
uA
at IRC 10 kHz,
HCLK = 10 kHz
VDD = 1.8V at 10 kHz
65
uA
all IP enabled and PLL disabled
VDD = 1.8V at 10 kHz
all IP and PLL disabled
62
uA
VDD= 3.6V at 42 MHz
all IP and PLL enabled [*5]
Operating Current
Idle Mode
14.5
4.6
mA
mA
at XTAL 12 MHz,
HCLK = 42 MHz
VDD=3.6V at 42 MHz
all IP disabled and PLL enabled
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN.
VDD = 1.8V at 42MHz
all IP and PLL enabled [*5]
IIDLE3
13.8
4.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD = 1.8V at 42 MHz
IIDLE4
all IP disabled and PLL enabled
VDD= 3.6V at 32 MHz
all IP and PLL enabled [*5]
IIDLE5
11.6
3.6
VDD=3.6V at 32 MHz
Operating Current
Idle Mode
IIDLE6
all IP disabled and PLL enabled
at XTAL 12 MHz,
HCLK = 32 MHz
VDD = 1.8V at 32MHz
all IP and PLL enabled [*5]
IIDLE7
11.1
3.6
VDD = 1.8V at 32 MHz
IIDLE8
all IP disabled and PLL enabled
VDD = 3.6V at 12 MHz,
IIDLE9
4.7
all IP enabled and PLL disabled
VDD = 3.6V at 12 MHz,
all IP and PLL disabled
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
IIDLE16
IIDLE17
IIDLE18
IIDLE19
0.99
4.6
at XTAL 12 MHz,
HCLK = 12 MHz
VDD = 1.8V at 12 MHz,
all IP enabled and PLL disabled
VDD = 1.8V at 12 MHz,
all IP and PLL disabled
0.94
5.9
VDD = 3.6V at 12 MHz,
all IP enabled and PLL disabled
VDD = 3.6V at 12 MHz,
all IP and PLL disabled
Operating Current
Idle Mode
1.3
at IRC 12 MHz,
HCLK = 12 MHz
VDD = 1.8V at 12 MHz,
4.9
all IP enabled and PLL disabled
VDD = 1.8V at 12 MHz,
all IP and PLL disabled
1.3
VDD = 3.6V at 4 MHz,
2.7
all IP enabled and PLL disabled
Operating Current
Idle Mode
VDD = 3.6V at 4 MHz,
all IP and PLL disabled
0.66
2.7
at XTAL 4 MHz,
HCLK = 4 MHz
VDD = 1.8V at 4 MHz,
all IP enabled and PLL disabled
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN.
VDD = 1.8V at 4 MHz,
IIDLE20
IIDLE21
IIDLE22
IIDLE23
IIDLE24
IIDLE25
IIDLE26
IIDLE27
IIDLE28
IPWD1
0.64
78
mA
uA
uA
uA
uA
uA
uA
uA
uA
A
A
all IP and PLL disabled
VDD = 3.6V at 32.768 kHz
all IP enabled and PLL disabled
VDD = 3.6V at 32.768 kHz
all IP and PLL disabled
Operating Current
Idle Mode
69
at XTAL 32.768 kHz,
HCLK = 32.768 kHz
VDD = 1.8V at 32.768 kHz
72
all IP enabled and PLL disabled
VDD = 1.8V at 32.768 kHz
all IP and PLL disabled
63
VDD = 3.6V at 10 kHz
69
all IP enabled and PLL disabled
VDD = 3.6V at 10 kHz
all IP and PLL disabled
Operating Current
Idle Mode
66
at IRC 10 kHz,
HCLK = 10 kHz
VDD = 1.8V at 10 kHz
63
all IP enabled and PLL disabled
VDD = 1.8V at 10 kHz
all IP and PLL disabled
61
VDD = 3.6V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
1.2
0.8
VDD = 1.8V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
IPWD2
Standby Current
VDD = 3.6V, RTC ON, all clock stop
except 32.768 kHz
Power-down Mode
IPWD3
2.8
2.0
A
A
With RAM Retenstion, IO no loading
VDD = 1.8V, RTC ON, all clock stop
except 32.768 kHz
IPWD4
With RAM Retenstion, IO no loading
Input Pull Up Resistor
PA, PB, PC, PD, PE,
PF
40
98
KΩ VDD = 3.3V
KΩ VDD = 1.8V
RIN
Input Leakage Current
PA, PB, PC, PD, PE,
PF
ILK
-0.1
-
+0.1
VDD = 3.3V, 0<VIN<VDD
A
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Input Low Voltage PA,
PB, PC, PD, PE, PF
VIL1
-
0.4VDD
5.5
V
(Schmitt input)
Input High Voltage PA,
PB, PC, PD, PE, PF
ADC and DAC shared pins without Input
5V tolerance.
VIH1
0.6VDD
V
V
(Schmitt input)
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
VIL2
VIH2
VIL4
VIH4
0.2VDD
Input Low Voltage
XT1_IN / XT1_OUT
[*2]
0
-
0.4
VDD = 1.8V
VDD = 1.8V
Input High Voltage
VDD
+0.2
XT1_IN / XT1_OUT [*2]
1.5
0
-
-
V
V
Input Low Voltage
X32I / X32O [*2]
0.3
Input High Voltage
X32I / X32O [*2]
1.5
-
1.98
V
V
Negative going
threshold
VILS
1.28
1.33
1.37
2.25
VDD = 3.3V
VDD = 3.3V
(Schmitt input),
/RESET
Positive going
threshold
VIHS
1.75
1.98
V
(SchmittIput), /RESET
VDD = 3.3V,
ISR21
ISR22
ISK21
ISK22
-10
-3
-14
-5
-
-
-
-
mA
mA
mA
mA
Source Current PA,
PB, PC, PD, PE, PF
VS = Vdd-0.7V
VDD = 1.8V,
(Push-pull Mode)
VS = Vdd-0.45V
VDD = 3.3V,
VS = 0.7V
10
3
15
6
Sink Current PA, PB,
PC, PD, PE, PF
VDD = 1.8V,
VS = 0.45V
(Push-pull Mode)
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin and the closest VSS
pin of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
5. All peripherals’ clock source is from HXT (12 MHz), except SPI from HCLK.
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NUMICRO® NANO100 (B) DATASHEET
9.3 AC Electrical Characteristics
9.3.1 External Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
tCLCH
tCHCL
10
10
2
-
-
-
-
nS
nS
nS
nS
Clock Low Time
Clock Rise Time
Clock Fall Time
15
15
2
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
9.3.2 External 4~24 MHz XTAL Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
Oscillator frequency
Temperature
fHXT
THXT
IHXT
4
12
-
24
MHz
oC
VDD = 1.8V ~ 3.6V
-40
+85
Operating current
VDD = 3.0V
0.3
mA
9.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4MHz ~ 24 MHz
Optional(Depend on crystal specification)
without
C1
XTAL IN
R
XTAL OUT
C2
Figure 9‑1 Typical Crystal Application Circuit
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NUMICRO® NANO100 (B) DATASHEET
9.3.3 External 32.768 kHz Crystal
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Oscillator frequency
Temperature
fLXT
TLXT
ILXT
32.768
kHz
oC
VDD = 1.8V ~ 3.6V
-40
-
+85
Operating current
VDD = 3.0V
1.2
A
9.3.4 Internal 12 MHz Oscillator
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
Supply voltage[1]
SYM.
TEST CONDITION
VHRC
1.8
V
11.88
11.76
12
12
12.12 MHz 25oC, VDD = 3V
12.24 MHz -40oC~+85 oC, VDD = 1.8V~3.6V
-40oC~+85 oC, VDD = 1.8V~3.6V
Calibrated Internal Oscillator
Frequency
FHRC
11.97
12
12.03 MHz
Enable 32.768K crystal oscillator
and set TRIM_SEL[1:0]=”10”
Operating current
IHRC
450
A
Note: Internal oscillator operation voltage comes from LDO.
9.3.5 Internal 10 kHz Oscillator
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
Supply voltage[1]
SYM.
TEST CONDITION
VLRC
FLRC
ILRC
1.8
V
7
5
10
10
13
15
kHz 25oC, VDD = 3V
Center Frequency
Operating current
-40oC~+85 oC, VDD = 1.8V~3.6V
kHz
A
0.7
VDD = 3V
Note: Internal oscillator operation voltage comes from LDO.
9.4 Analog Characteristics
9.4.1 12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
Operating voltage
AVDD
1.8
3.6 AVDD = VDD
V
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NUMICRO® NANO100 (B) DATASHEET
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
AVDD = VDD = 3.0V
IADC42
147
50
ADC_VREF = AVDD
ADC Clock Rate = 42 MHz
A
A
Operating current
AVDD = VDD = 3.0V
ADC_VREF = AVDD
IADC12
ADC Clock Rate = 12 MHz
Resolution
RADC
VREF
IREF
12
AVDD
10
Bit
V
Reference voltage
Reference input current (Avg.)
ADC input voltage
Conversion time
Sampling Rate
1.8
A
V
VIN
0
VREF
TCONV
FSPS
INL
0.5
S
2M
±2
Hz VDD = 3V
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
±1
LSB VREF is external Vref pin
DNL
EG
±0.8 -1~+1.5 LSB VREF is external Vref pin
-
-
-
±2
±3
±6
42
LSB VREF is external Vref pin
Offset error
EOFFSET
EABS
FADC
ADCYC
CIN
LSB VREF is external Vref pin
Absolute error
LSB VREF is external Vref pin
ADC Clock frequency
Clock cycle
0.25
20
-
MHz
Cycle
pF
Internal Capacitance
Monotonic
5
-
-
Guaranteed
-
9.4.2 Brown-out Detector
PARAMETER
SPECIFICATIONS
MIN. TYP. MAX. UNIT
SYM.
TEST CONDITION
Operating voltage
VBOD
IBOD17
IBOD20
IBOD25
VB17dt
VB20dt
VB25dt
1.8
3.6
V
A
A
A
V
BOD17 Quiescent current
BOD20 Quiescent current
BOD25 Quiescent current
BOD17 detection level
BOD20 detection level
BOD25 detection level
1
1
AVDD = 3.0V, BOD17 enabled
AVDD = 3.0V, BOD20 enabled
1
AVDD = 3.0V, BOD25 enabled
1.6
1.9
2.4
1.7
2.0
2.5
1.8
2.1
2.6
25C
25oC
25oC
V
V
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NUMICRO® NANO100 (B) DATASHEET
9.4.3 Power-on Reset
PARAMETER
SPECIFICATIONS
MIN. TYP. MAX. UNIT
SYM.
TEST CONDITION
Reset voltage
VPOR
IPOR
-
-
1.6
1
-
-
V
Quiescent current
nA LDO output > Reset voltage
9.4.4 Temperature Sensor
SPECIFICATIONS
TYP. MAX. UNIT
TEST CONDITION
(SUPPLY VOLTAGE = 3.36V)
PARAMETER
SYM.
MIN.
Detection Temperature
Operating current
Gain
TDET
ITEMP
VTG
-40
-
+110
-
oC
5
A
-1.80
730
-1.73
740
-1.65 mV/ oC
mV Tempeature at 0 oC
Offset
VTO
750
Note: Internal operation voltage comes form LDO.
9.4.5 12-bit DAC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Operating voltage
AVDD
2.0
3.6
V
AVDD = VDD
AVDD = VDD = 3.0V,
Operating current
IDAC
2.20
mA DAC_VREF = AVDD
DAC conversion rate 500kHz
Resolution
RADC
VREF
12
Bit
V
Reference voltage
1.8
AVDD
AVDD = VDD = 3.0V
mA DAC_VREF=Ext_Vref
DAC conversion rate 500kHz
Reference input current (Avg.)
DAC output swin range
IREF
0.85
-
0.1 x
VREF
0.9 x
VREF
VOUT
FSPS
V
Conversion Rate (code to
adjacent code)
500
kHz VDD = 3V
VREF is external Vref pin
LSB
Integral Non-Linearity Error
Differential Non-Linearity
INL
±4
±1
±5
±2
Not include offset and gain error
VREF is external Vref pin
LSB
DNL
Not include offset and gain error
Gain error
EG
290
150
LSB
LSB
Offset error
EOFFSET
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NUMICRO® NANO100 (B) DATASHEET
9.4.6 LCD
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Operating voltage
VLCD voltage
VLCD voltage
VLCD voltage
VLCD voltage
VLCD voltage
VLCD voltage
VLCD voltage
VLCD voltage
VDD
1.8
-
3.6
V
V
V
V
V
V
V
V
V
VLCD34
VLCD33
VLCD32
VLCD31
VLCD30
VLCD29
VLCD28
VLCD27
-
-
-
-
-
-
-
-
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
-
-
-
-
-
-
-
-
CPUMP_VOL_SET=111, no loading
CPUMP_VOL_SET=110, no loading
CPUMP_VOL_SET=101, no loading
CPUMP_VOL_SET=100, no loading
CPUMP_VOL_SET=011, no loading
CPUMP_VOL_SET=010, no loading
CPUMP_VOL_SET=001, no loading
CPUMP_VOL_SET=000, no loading
VDD = 3V, frame rate = 32Hz
Without loading
Operating current
ILCD
-
10
-
A
9.4.7 Internal Voltage Reference
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Operating voltage
AVDD
VREF1
VREF2
TREFTAB
IVREF
1.8
1.69
2.35
-
-
3.6
1.87
2.60
-
V
V
1.8V voltage reference
2.5V voltage reference
Stable Time
1.8
2.5
1
AVDD ≥ 2.0V (-40C ~85C)
AVDD ≥ 2.8V (-40C ~85C)
V
ms
A
Operating current
-
30
-
AVDD = 3V
9.4.8 USB PHY Specifications
9.4.8.1 USB PHY DC Electrical Characteristics
SYMBOL
PARAMETER
Input high (driven)
Input low
CONDITION
MIN.
TYP. MAX. UNIT
VIH
VIL
VDI
2.0
-
-
-
V
V
V
0.8
Differential input sensitivity
|PADP-PADM|
0.2
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NUMICRO® NANO100 (B) DATASHEET
Differential
VCM
VSE
Includes VDI range
0.8
0.8
-
2.5
2.0
V
common-mode range
Single-ended receiver threshold
Receiver hysteresis
Output low (driven)
-
V
mV
V
200
VOL
VOH
VCRS
RPU
RPD
0
-
-
-
-
-
0.3
3.6
Output high (driven)
Output signal cross voltage
Pull-up resistor
2.8
V
1.3
2.0
V
1.425
14.25
1.575
15.75
kΩ
kΩ
Pull-down resistor
Termination Voltage for
upstream port pull up (RPU)
VTRM
3.0
-
3.6
V
ZDRV
CIN
Driver output resistance
Transceiver capacitance
Steady state drive*
Pin to GND
10
-
Ω
20
pF
*Driver output resistance doesn’t include series resistor resistance.
9.4.8.2 USB PHY Full-Speed Driver Elevtrical Characteristics
SYMBOL
TFR
PARAMETER
Rise Time
CONDITION
CL=50p
MIN.
4
TYP. MAX. UNIT
-
-
-
20
20
ns
ns
%
TFF
Fall Time
CL=50p
4
TFRFF
Rise and fall time matching
TFRFF=TFR/TFF
90
111.11
9.4.8.3 USB PHY Power Dissipation
SYMBOL
PARAMETER
CONDITION
MIN.
TYP. MAX. UNIT
IVDDREG
VDDD and VDDREG Supply
Current (Steady State)
Standby
50
uA
(Full
Speed)
9.4.8.4 USB LDO DC Electrical Characteristics
SYMBOL
VBUS
V33
PARAMETER
CONDITION
MIN.
TYP. MAX. UNIT
5
V
V
Output voltage
2.97
3.3
100
3.63
VBUS = 5V, 25C
Iop
Operation Current
uA
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NUMICRO® NANO100 (B) DATASHEET
9.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
1.62
20000
100
-
Typ
Max
Unit
V
Test Condition
[2]
VFLA
1.8
1.98
NENDUR
TRET
cycles[1]
year
ms
TA = 25℃
Data Retention
Page Erase Time
Program Time
Read Current
Program Current
Erase Current
TERASE
TPROG
IDD1
20
40
-
-
-
0.150
7
us
mA/MHz
mA
IDD2
IDD3
7
mA
Notes:
1.
2.
3.
Number of program/erase cycles.
VFLA is source from chip LDO output voltage.
Guaranteed by design, not test in production.
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NUMICRO® NANO100 (B) DATASHEET
10 PACKAGE DIMENSIONS
10.1 LQFP128 (14x14x1.4 mm footprint 2.0 mm)
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10.2 LQFP64 (10x10x1.4 mm footprint 2.0 mm)
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NUMICRO® NANO100 (B) DATASHEET
10.3 LQFP64 (7x7x1.4 mm footprint 2.0 mm)
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NUMICRO® NANO100 (B) DATASHEET
May 31, 2016
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NUMICRO® NANO100 (B) DATASHEET
10.4 LQFP48 (7x7x1.4 mm footprint 2.0 mm)
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NUMICRO® NANO100 (B) DATASHEET
10.5 QFN48 (7x7x0.85 mm)
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NUMICRO® NANO100 (B) DATASHEET
11 REVISION HISTORY
Revision Description
Date
2012.10.11 1.00
Initial release
1. Added SmartCard UART mode description in Pin Description.
2. Unified the abbreviation (TMR) in the Timer Controller section.
3. Modified the specifications of external input clock.
4. Added LCD COM4 and COM5 description for each pin description and
diagram.
2012.12.11 1.01
5. Updated the ADC enabled by timer event description in the ADC
section.
6. Changed Timer0/1 Ch0/1 to Timer x (x=0, 1, 2, 3) in the Timer
Controller section.
2012.12.17 1.02
2012.12.28 1.03
2013.01.02 1.04
1. Added description of reading UCID in ISP mode.
1. Added R-type related description in LCD section.
2. Updated the operating current data of Run mode and Idle mode at each
frequency and added related data at 42 MHz in section 9.2.
1. Updated the table in Power Consumption section.
1. Updated the display modes from four to six in section 5.13.2.
2. Corrected the pin descriptions in section 3.4.
2013.03.05 1.05
2013.05.28 1.06
3. Updated temperature sensor of analog characteristic in section 9.4.4.
4. Corrected Smart Card’s feature to be half duplex in UART mode in
section 5.16.2.
1. Updated the Nano110 LQFP128-pin diagram in section 3.3.2.
2. Updated “12 MHz OSC has 2 % deviation within all temperarure range”
in sections 2.1 to 2.4.
3. Updated DAC analog characteristics in section 9.4.5.
4. Added Nano110RC2BN to the Nano110 LCD Line Selection Guide.
1. Updated Nano100 series selection code in section 3.1.
2. Added the Nano100 QFN48 package in section 3.2 and QFN48
package dimensions in chapter 10.
3. Fixed the typo of LCD characteristic in section 9.4.7.
2013.12.04 1.07
4. Added a note that “Output voltage for ADC/LCD shared pins cannot be
higher than VDD because these pins are without 5V tolerance.” for pin
description in section 3.4, LCD overview in section 5.13.1 and Absolute
Maximum Ratings in section 9.1.
5. Modified the schematic for ADC and DAC application circuit in section
May 31, 2016
Page 158 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
7.2 and 7.3.
1. Added Flash DC Electrical Characteristics in section 9.5.
2. Fixed the typo of LCD Feature in section 5.13.2.
2016.05.31 1.08
3. Fixed the typo of Products Selection Guide in section 3.2
4. Modified the schematic for ADC, DAC and Whole Chip Application
Circuit in section 7.2, 7.3 and 7.4.
May 31, 2016
Page 159 of 160
Revision 1.08
NUMICRO® NANO100 (B) DATASHEET
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
May 31, 2016
Page 160 of 160
Revision 1.08
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