NAU88C22YG_技术文档

NAU88C22

24-bit Stereo Audio Codec with Speaker Driver

Description

The NAU88C22 is a low power, high quality CODEC for portable and general purpose audio applications. In

addition to precision 24-bit stereo ADCs and DACs, this device integrates a broad range of additional functions

to simplify implementation of complete audio system solutions. The NAU88C22 includes drivers for speaker,

headphone, and differential or stereo line outputs, and integrates preamps for stereo differential microphones,

significantly reducing external component requirements. Also, a fractional PLL is available to accurately

generate any audio sample rate for the CODEC using any commonly available system clock from 8MHz through

33MHz.

Advanced on-chip digital signal processing includes a 5-band equalizer, a 3-D audio enhancer, a mixed-signal

automatic level control for the microphone or line input through the ADC, and a digital limiter/dynamic-range-

compressor (DRC) function for the playback path. Additional digital filtering options are available in the ADC

path, to simplify implementation of specific application requirements such as “wind noise reduction” and speech

band enhancement. The digital audio input/output interface can operate as either a master or a slave.

The NAU88C22 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate at

1.7V to conserve power. The loudspeaker BTL output pair and two auxiliary line outputs can operate using a 5V

supply to increase output power capability, enabling the NAU88C22 to drive 1 Watt into an external speaker.

Internal register controls enable flexible power saving modes by powering down sub-sections of the chip under

software control.

The NAU88C22 is specified for operation from -40°C to +85°C, and is available in a space-saving 32-lead QFN

package.

Key Features

 DAC: 89dB SNR and -84dB THD (“A” weighted)

 ADC: 89dB SNR and -78dB THD (“A” weighted)

 Integrated BTL speaker driver: 1W into 8Ω

 Integrated head-phone driver: 40mW into 16Ω

 Integrated programmable microphone amplifier

 Integrated line input and line output

 On-chip PLL

 Integrated DSP with specific functions:

 5-band equalizer

 3-D audio enhancement

 Input automatic level control (ALC/AGC)/limiter

 Output dynamic-range-compressor/limiter

 Notch filter and high pass filter

 Standard audio interfaces: PCM and I²S

 Serial control interfaces with read/write capability

 Real time readback of signal level and DSP status

 Supports any sample rate from 8kHz, 48kHz,

96kHz and 192kHz

Applications

 Personal Media Players

 Smartphones

 Personal Navigation Devices

 Portable Game Players

 Camcorders

 Digital Still Cameras

 Portable TVs

 Stereo Bluetooth Headsets

NAU88C22 Datasheet Rev 0.6

Page 1 of 101

June, 2016

Headphones/

Line drivers

LAUXIN

RAUXIN

LLIN

AUXOUT2

AUXOUT1

LHP

ADC Filter

DAC Filter

LADC

RADC

LDAC

RDAC

Volume

Control

Volume

Control

RLIN

High Pass &

Notch Filters

Limiter

Input

Mixer

Output

Mixer

Stereo

Microphone

Interface

LMICN

LMICP

RHP

5-band EQ

3D

BTL Speaker

RMICN

RMICP

LSPKOUT

RSPKOUT

Digital Audio Interface

I²S

PCM

Serial

Control

Interface

Microphone

Bias

GPIO

PLL

NAU88C22LYG

Pinout

1

24

LMICP

LMICN

VSSSPK

2

23

RSPKOUT

AUXOUT2

AUXOUT1

RAUXIN

LAUXIN

MODE

3

22

LLIN/GPIO2

RMICP

NAU88C22YG

32-lead QFN

RoHS

4

21

5

20

RMICN

6

19

RLIN/GPIO3

FS

7

18

8

17

BCLK

SDIO

Package

Material

Part Number

Dimension

Package

32-QFN

5 x 5 mm

Green

NAU88C22YG

NAU88C22 Datasheet Rev 0.6

Page 2 of 101

June, 2016

Pin Descriptions

Pin #

Name

Type

Functionality

1

2

3

LMICP

LMICN

LLIN/GPIO2

Analog Input

Analog Input /

Digital I/O

Left MICP Input (common mode)

Left MICN Input

Left Line Input / alternate Left MICP Input / GPIO2

4

5

6

RMICP

RMICN

RLIN/GPIO3

Analog Input

Analog Input /

Digital I/O

Right MICP Input (common mode)

Right MICN Input

Right Line Input/ alternate Right MICP Input / Digital

Output

In 4-wire mode: Must be used for GPIO3

Digital Audio DAC and ADC Frame Sync

Digital Audio Bit Clock

Digital Audio ADC Data Output

Digital Audio DAC Data Input

Master Clock Input

Digital Ground

Digital Core Supply

7

8

9

10

11

12

13

14

15

FS

BCLK

ADCOUT

DACIN

MCLK

VSSD

VDDC

VDDB

Digital I/O

Digital Output

Digital Input

Supply

Digital I/O

Digital Buffer (Input/Output) Supply

3-Wire MPU Chip Select or GPIO1 multifunction

input/output

CSB/GPIO1

16

17

SCLK

SDIO

Digital Input

Digital I/O

3-Wire MPU Clock Input / 2-Wire MPU Clock Input/Open

Drain I/O needs external pull-up resistor

3-Wire MPU Data Input / 2-Wire MPU Data I/O /Open

Drain I/O needs external pull-up resistor

Control Interface Mode Selection Pin

Left Auxiliary Input

18

19

20

21

22

23

24

MODE

LAUXIN

RAUXIN

AUXOUT1

AUXOUT2

RSPKOUT

VSSSPK

Digital Input

Analog Input

Analog Output

Supply

Right Auxiliary Input

Headphone Ground / Mono Mixed Output / Line Output

Headphone Ground / Line Output

BTL Speaker Positive Output or Right high current output

Speaker Ground (ground pin for RSPKOUT, LSPKOUT,

AUXOUT2 and AUXTOUT1 output drivers)

BTL Speaker Negative Output or Left high current output

Speaker Supply (power supply pin for RSPKOUT,

LSPKOUT, AUXOUT2 and AUXTOUT1 output drivers)

Decoupling for Midrail Reference Voltage

Analog Ground

25

26

LSPKOUT

VDDSPK

Analog Output

Supply

27

28

29

30

31

32

VREF

VSSA

RHP

LHP

VDDA

MICBIAS

Reference

Supply

Analog Output

Supply

Headphone Positive Output / Line Output Right

Headphone Negative Output / Line Output Left

Analog Power Supply

Analog Output

Microphone Bias

NAU88C22 Datasheet Rev 0.6

Page 3 of 101

June, 2016

Figure 1: NAU88C22 Block Diagram

NAU88C22 Datasheet Rev 0.6

Page 4 of 101

June, 2016

Electrical Characteristics

Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), MCLK =

12.288MHz, T_A= +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, 64X oversampling rate, unless otherwise stated.

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

Analog to Digital Converter (ADC)

Full scale input signal ¹

V_INFS

PGABST = 0dB

1.0

0

89

-78

106

Vrms

dBV

dB

PGAGAIN = 0dB

Gain = 0dB, A-weighted

Input = -3dB FS input

1kHz input signal

Signal-to-noise ratio

Total harmonic distortion ²

Channel separation

SNR

THD+N

Digital to Analog Converter (DAC) driving RHP / LHP with 10kΩ / 50pF load

Full-scale output

Gain paths all at 0dB gain

VDDA / 3.3

V_rms

Signal-to-noise ratio

SNR

THD+N

A-weighted

R_L= 10kΩ; full-scale signal

1kHz input signal

88

89

-84

100

dB

Total harmonic distortion ²

Channel separation

Output Mixers

Maximum PGA gain into mixer

Minimum PGA gain into mixer

PGA gain step into mixer

+6

-15

3

dB

Guaranteed monotonic

Speaker Output (RSPKOUT / LSPKOUT with 8Ω bridge-tied-load) ⁷

Full scale output ⁴

SPKBST = 1,

VDDSPK=VDDA

SPKBST = 0

VDDSPK= 1.5 * VDDA

P_o= 200mW_,

VDDSPK=3.3V

P_o= 320mW_,

VDDSPK = 3.3V

P_o= 860mW,

VDDSPK = 1.5 * VDDA

VDDA / 3.3

V_rms

dB

(VDDA / 3.3) * 1.5

Total harmonic distortion ²

THD+N

-64

-65

-59

-37

96

dB

P_o= 1000mW,

VDDSPK = 1.5 * VDDA

VDDSPK = 3.3V

dB

Signal-to-noise ratio

SNR

dB

VDDSPK=1.5 * VDDA

VDDSPK = 3.3V

94

80

76

dB

Power supply rejection ratio

(50Hz - 22kHz)

PSRR

VDDSPK = 1.5 * VDDA

Analog Outputs (RHP / LHP; RSPKOUT / LSPKOUT)

Maximum programmable gain

Minimum programmable gain

+6

-57

1

dB

Programmable gain step size

Mute attenuation

Guaranteed monotonic

1kHz full scale signal

85

NAU88C22 Datasheet Rev 0.6

Page 5 of 101

June, 2016

Electrical Characteristics, cont’d.

Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), MCLK =

12.288MHz,

T_A= +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, unless otherwise stated.

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

Headphone Output (RHP / LHP with 32Ω load)

0dB full scale output voltage

VDDA / 3.3

V_rms

Signal-to-noise ratio

SNR

THD+N

A-weighted

R_L= 16Ω, P_o= 20mW,

VDDA = 3.3V

94

-86

dB

Total harmonic distortion ²

R_L= 32Ω, P_o= 20mW,

VDDA = 3.3V

-87

dB

AUXOUT1 / AUXOUT2 with 10kΩ / 50pF load

Full scale output

AUX1BST = 0

AUX2BST = 0

VDDSPK=VDDA

AUX1BST = 1

VDDA / 3.3

V_rms

(VDDA / 3.3) * 1.5

AUX2BST = 1

VDDSPK=1.5*VDDA

Signal-to-noise ratio

Total harmonic distortion ²

Channel separation

Power supply rejection ratio

(50Hz - 22kHz)

SNR

THD+N

91

-86

103

82

dB

1kHz signal

VDDSPK = 3.3V

PSRR

VDDSPK = 1.5 * VDDA

78

dB

Microphone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) and Programmable Gain Amplifier (PGA)

Full scale input signal ¹

PGABST = 0dB

PGAGAIN = 0dB

1.0

0

Vrms

dBV

dB

Programmable gain

Programmable gain step size

Mute Attenuation

-12

35.25

Guaranteed Monotonic

0.75

120

Input resistance

Inverting Input

PGA Gain = 35.25dB

PGA Gain = 0dB

PGA Gain = -12dB

Non-inverting Input

1.6

47

75

94

10

kΩ

pF

Input capacitance

PGA output noise

0 to 20kHz, Gain set to

35.25dB

120

µV

Input Boost Mixer

Gain boost

Boost disabled

Boost enabled

0

20

dB

Gain range LLIN / RLIN or

-12

6

LAUXIN / RAUXIN to boost/mixer

Gain step size to boost/mixer

3

dB

Auxiliary Analog Inputs (LAUXIN, RAUXIN)

Full scale input signal ¹

Gain = 0dB

1.0

0

Vrms

dBV

Input resistance

Aux direct-to-out path, only

Input gain = +6.0dB

Input gain = 0.0dB

20

40

159

10

kΩ

pF

Input gain = -12dB

Input capacitance

NAU88C22 Datasheet Rev 0.6

Page 6 of 101

June, 2016

Electrical Characteristics, cont’d.

Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), MCLK =

12.288MHz,

T_A= +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, unless otherwise stated.

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

Automatic Level Control (ALC) & Limiter: ADC path only

Target record level

-22.5

-12

-1.5

35.25

dBFS

dB

ms

Programmable gain

Gain hold time ³

t_HOLD

t_DCY

Doubles every gain step,

with 16 steps total

ALC Mode

0 / 2.67 / 5.33 / … / 43691

4 / 8 / 16 / … / 4096

1 / 2 / 4 / … / 1024

0.25 / 0.5 / 1 / … / 128

120

Gain ramp-up (decay) ³

ms

dB

ALC = 0

Limiter Mode

ALC = 1

ALC Mode

Gain ramp-down (attack) ³

t_ATK

ALC = 0

Limiter Mode

ALC = 1

Mute Attenuation

Microphone Bias

Bias voltage

V_MICBIAS

See Figure 3

0.50, 0.60,0.65, 0.70,

0.75, 0.85, or 0.90

VDDA

mA

Bias current source

Output noise voltage

Digital Input/Output

Input HIGH level

I_MICBIAS

V_n

3

14

1kHz to 20kHz

nV/√Hz

V_IL

V_IH

V_OH

V_OL

0.7 *

VDDB

V

Input LOW level

Output HIGH level

Output LOW level

0.3 *

VDDB

I_Load= 1mA

I_Load= -1mA

0.9 *

VDDB

V

0.1 *

V

VDDB

Input capacitance

10

pF

Notes

1. Full Scale is relative to the magnitude of VDDA and can be calculated as FS = VDDA/3.3.

2. Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The signal level

for distortion measurements is at 3dB below full scale, unless otherwise noted.

3. Time values scale proportionally with MCLK. Complete descriptions and definitions for these values are contained in

the detailed descriptions of the ALC functionality.

4. With default register settings, VDDSPK should be 1.5xVDDA (but not exceeding maximum recommended operating

voltage) to optimize available dynamic range in the AUXOUT1 and AUXOUT2 line output stages. Output DC bias

level is optimized for VDDSPK = 5.0Vdc (boost mode) and VDDA = 3.3Vdc.

5. Unused analog input pins should be left as no-connection.

6. Unused digital input pins should be tied to ground.

7. 4 Ω loading is not recommended for speaker outputs

NAU88C22 Datasheet Rev 0.6

Page 7 of 101

June, 2016

Absolute Maximum Ratings

Condition

Min

-0.3

Max

+3.61

+5.80

Units

V

VDDB, VDDC, VDDA supply voltages

VDDSPK supply voltage (default register configuration)

V

VDDSPK supply voltage (optional low voltage

configuration)

-0.3

+3.61

V

Core Digital Input Voltage range

Buffer Digital Input Voltage range

Analog Input Voltage range

VSSD – 0.3

VSSA – 0.3

-40

VDDC + 0.30

VDDB + 0.30

VDDA + 0.30

+85

V

Industrial operating temperature

Storage temperature range

°C

-65

+150

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions

may adversely influence product reliability and result in failures not covered by warranty.

Operating Conditions

Condition

Digital supply range (Core)

Digital supply range (Buffer)

Analog supply range

Symbol

VDDC

Min

1.65

2.50

Typical

Max

3.60

5.50

Units

V

VDDB

V

VDDA

V

Speaker supply (SPKBST=0)

Speaker supply (SPKBST=1)

VDDSPK

V

VSSD

VSSA

Ground

0

V

VSSSPK

1. VDDA must be ≥ VDDC.

2. VDDB must be ≥ VDDC.

NAU88C22 Datasheet Rev 0.6

Page 8 of 101

June, 2016

Table of Contents

1

GENERAL DESCRIPTION.............................................................................................................................12

1.1.1

1.1.2

1.1.3

1.1.4

1.1.5

1.1.6

Analog Inputs ......................................................................................................................................12

Analog Outputs ...................................................................................................................................12

ADC, DAC, and Digital Signal Processing...........................................................................................13

Realtime Signal Level Readout and DSP Status.................................................................................13

Digital Interfaces .................................................................................................................................13

Clock Requirements............................................................................................................................13

2

3

POWER SUPPLY.............................................................................................................................................14

2.1.1

2.1.2

2.1.3

Power-On Reset..................................................................................................................................14

Power Related Software Considerations.............................................................................................14

Software Reset....................................................................................................................................14

INPUT PATH DETAILED DESCRIPTIONS..................................................................................................16

3.1

3.1.1

Programmable Gain Amplifier (PGA) .........................................................................................................16

Zero Crossing Example.......................................................................................................................17

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Positive Microphone Input (MICP)..............................................................................................................17

Negative Microphone Input (MICN)............................................................................................................18

Microphone biasing ....................................................................................................................................19

Line/Aux Input Impedance and Variable Gain Stage Topology ..................................................................19

Left and Right Line Inputs (LLIN and RLIN) ...............................................................................................22

Auxiliary inputs (LAUXIN, RAUXIN) ...........................................................................................................22

ADC Mix/Boost Stage.................................................................................................................................22

Input Limiter / Automatic Level Control (ALC) ............................................................................................23

Normal Mode Example Operation.......................................................................................................23

3.9.1

3.9.2

3.10

3.10.1

ALC Parameter Definitions..................................................................................................................24

ALC Peak Limiter Function.........................................................................................................................25

ALC Normal Mode Example Using ALC Hold Time Feature ...............................................................25

3.11

3.12

Noise Gate (Normal Mode Only) ................................................................................................................25

ALC Example with ALC Min/Max Limits and Noise Gate Operation...........................................................27

3.12.1

ALC Register Map Overview...............................................................................................................27

3.13

Limiter Mode...............................................................................................................................................28

4

5

ADC DIGITAL BLOCK ..................................................................................................................................29

Sampling / Oversampling Rate, Polarity Control, Digital Passthrough .......................................................29

ADC Digital Volume Control and Update Bit Functionality .........................................................................30

ADC Programmable High Pass Filter.........................................................................................................30

Programmable Notch Filter.........................................................................................................................30

DAC DIGITAL BLOCK ..................................................................................................................................32

DAC Soft Mute ...........................................................................................................................................32

DAC AutoMute ...........................................................................................................................................32

DAC Sampling / Oversampling Rate, Polarity Control, Digital Passthrough...............................................32

DAC Digital Volume Control and Update Bit Functionality .........................................................................33

DAC Automatic Output Peak Limiter / Volume Boost.................................................................................33

5-Band Equalizer........................................................................................................................................34

3D Stereo Enhancement............................................................................................................................35

4.1

4.2

4.3

4.4

5.1

5.2

5.3

5.4

5.5

5.6

5.7

NAU88C22 Datasheet Rev 0.6

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June, 2016

5.8

Companding...............................................................................................................................................35

µ-law...........................................................................................................................................................35

A-law ..........................................................................................................................................................35

8-bit Word Length.......................................................................................................................................36

5.9

5.10

5.11

6

ANALOG OUTPUTS.......................................................................................................................................37

Main Mixers (LMAIN MIX and RMAIN MIX)................................................................................................37

Auxiliary Mixers (AUX1 MIXER and AUX2 MIXER)....................................................................................37

Right Speaker Submixer ............................................................................................................................38

Headphone Outputs (LHP and RHP) .........................................................................................................38

Speaker Outputs ........................................................................................................................................39

Auxiliary Outputs ........................................................................................................................................41

MISCELLANEOUS FUNCTIONS..................................................................................................................41

Slow Timer Clock .......................................................................................................................................41

General Purpose Inputs and Outputs (GPIO1, GPIO2, GPIO3) and Jack Detection..................................42

Automated Features Linked to Jack Detection...........................................................................................42

CLOCK SELECTION AND GENERATION ..................................................................................................43

Phase Locked Loop (PLL) General Description .........................................................................................44

6.1

6.2

6.3

6.4

6.5

6.6

7

8

7.1

7.2

7.3

8.1

8.1.1

Phase Locked Loop (PLL) Design Example........................................................................................45

8.2

CSB/GPIO1 as PLL output.........................................................................................................................45

CONTROL INTERFACES...............................................................................................................................47

Selection of Control Mode ..........................................................................................................................47

2-Wire-Serial Control Mode (I²C Style Interface)........................................................................................47

2-Wire Protocol Convention........................................................................................................................47

2-Wire Write Operation...............................................................................................................................48

2-Wire Read Operation ..............................................................................................................................49

SPI Control Interface Modes ......................................................................................................................49

SPI 3-Wire Write Operation........................................................................................................................50

SPI 4-Wire 24-bit Write and 32-bit Read Operation...................................................................................50

SPI 4-Wire Write Operation......................................................................................................................50

9

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

SPI 4-Wire Read Operation........................................................................................................................51

Software Reset...........................................................................................................................................52

10

DIGITAL AUDIO INTERFACES ...................................................................................................................53

10.1

Right-Justified Audio Data..........................................................................................................................53

Left-Justified Audio Data ............................................................................................................................53

I²S Audio Data............................................................................................................................................54

PCM A Audio Data .....................................................................................................................................54

PCM B Audio Data .....................................................................................................................................55

PCM Time Slot Audio Data.........................................................................................................................55

Control Interface Timing.............................................................................................................................57

Audio Interface Timing: ..............................................................................................................................59

10.2

10.3

10.4

10.5

10.6

10.7

10.8

11

APPLICATION INFORMATION....................................................................................................................61

11.1

11.2

11.2.1

11.2.2

11.2.3

11.3

Typical Application Schematic....................................................................................................................61

Recommended power up and power down sequences..............................................................................62

Power Up (and after a software generated register reset) Procedure Guidance.................................62

Power Down........................................................................................................................................62

Unused Input/Output Tie-Off Information ............................................................................................63

Power Consumption...................................................................................................................................65

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June, 2016

11.4

Supply Currents of Specific Blocks.............................................................................................................66

12

13

APPENDIX A: DIGITAL FILTER CHARACTERISTICS............................................................................67

APPENDIX B: COMPANDING TABLES .....................................................................................................73

13.1

13.2

µ-Law / A-Law Codes for Zero and Full Scale............................................................................................73

µ-Law / A-Law Output Codes (Digital mW).................................................................................................73

14

15

16

17

APPENDIX C: DETAILS OF REGISTER OPERATION..............................................................................74

APPENDIX D: REGISTER OVERVIEW.......................................................................................................94

PACKAGE DIMENSIONS ..............................................................................................................................96

ORDERING INFORMATION.........................................................................................................................99

NAU88C22 Datasheet Rev 0.6

Page 11 of 101

June, 2016

1

General Description

The NAU88C22 is an upgrade to the WAU8822, and delivers reduced out-of-band noise energy, improved ALC

and DSP signal processing, read-out capability of realtime signal level, readout of DSP status, and added

controls for industry leading pop/click noise management. Additionally, handling of settings for 5-volt and 3-

volt operation are simplified, and all registers unique to Nuvoton are moved to higher addresses. This makes the

part a direct hardware and software drop-in replacement for common industry parts.

The NAU88C22 is a stereo part with identical left and right channels that share common support elements.

Additionally, the right channel auxiliary output path includes a dedicated submixer that supports mixing the right

auxiliary input directly into the right speaker output driver. This enables the right speaker channel to output

audio that is not present on any other output.

1.1.1 Analog Inputs

All inputs, except for the wide range programmable amplifier (PGA), have available analog input gain

conditioning of -15dB through +6dB in 3dB steps. All inputs also have individual muting functions with

excellent channel isolation and off-isolation from all outputs. All inputs are suitable for full quality, high

bandwidth signals.

Each of the left-right stereo channels includes a low noise differential PGA amplifier, programmable for high-

gain input. This may be used for a microphone level through line level source. Gain may be set from +35.25db

through -12dB at the analog difference-amplifier type programmable amplifier input stage. A separate

additional 20dB analog gain is available on this input path, between the PGA output and ADC mixer input. The

output of the ADC mixer may be routed to the ADC and/or analog bypass to the analog output sections.

Each channel also has a line level input. This input may be routed to the input PGA, and/or directly to the ADC

input mixer.

Each channel has a separate additional auxiliary input. This is a line level input which may be routed the ADC

input mixer and/or directly to the analog output mixers.

1.1.2 Analog Outputs

There are six high current analog audio outputs. These are very flexible outputs that can be used individually or

in stereo pairs for a wide range of end uses. However, these outputs are optimized for specific functions and are

described in this section using the functional names that are applicable to those optimized functions.

Each output receives its signal source from built-in analog output mixers. These mixers enable a wide range of

signal combinations, including muting of all sources. Additionally, each output has a programmable gain

function, output mute function, and output disable function.

The RHP and LHP headphone outputs are optimized for driving a stereo pair of headphones, and are powered

from the main analog voltage supply rail, VDDA. These outputs may be coupled using traditional DC blocking

series capacitors. Alternatively, these may be configured in a no-capacitor DC coupled design using a virtual

ground at ½ VDDA provided by an AUXOUT analog output operating in the non-boost output mode.

The AUXOUT1 and AUXOUT2 analog outputs are powered from the VDDSPK supply rail and VSSSPK

ground return path. The supply rail may be the same as VDDA, or may be a separate voltage up to 5.5Vdc. This

higher voltage enables these outputs to have an increased output voltage range and greater output power

capability.

The RSPKOUT and LSPKOUT loudspeaker outputs are powered from the VDDSPK power supply rail and

VSSGND ground return path. RSPKOUT receives its audio signal via an additional submixer. This submixer

supports combining a traditional alert sound (from the RAUXIN input) with the right channel headphone output

mixer signal. This submixer also provides the signal invert function that is necessary for the normal BTL

(Bridge Tied Load) configuration used to drive a high power external loudspeaker. Alternatively, each

loudspeaker output may be used individually as a separate high current analog output driver.

A programmable low-noise MICBIAS microphone bias supply output is included. This is suitable for both

conventional electret (ECM) type microphone, and to power the newer MEMS all-silicon type microphones.

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1.1.3 ADC, DAC, and Digital Signal Processing

Each left and right channel has an independent high quality ADC and DAC associated with it. These are high

performance, 24-bit delta-sigma converters that are suitable for a very wide range of applications.

The ADC and DAC functions are each individually supported by powerful analog mixing and routing. The

ADC output may be routed to the digital output path and/or to the input of the DAC in a digital passthrough

mode. The ADC and DAC blocks are also supported by advanced digital signal processing subsystems that

enable a very wide range of programmable signal conditioning and signal optimizing functions. All digital

processing is with 24-bit precision, as to minimize processing artifacts and maximize the audio dynamic range

supported by the LL.

The ADCs are supported by a wide range, mixed-mode Automatic Level Control (ALC), a high pass filter, and a

notch filter. All of these features are optional and highly programmable. The high pass filter function is

intended for DC-blocking or low frequency noise reduction, such as to reduce unwanted ambient noise or “wind

noise” on a microphone input. The notch filter may be programmed to greatly reduce a specific frequency band

or frequency, such as a 50Hz, 60Hz, or 217Hz unwanted noise.

The DACs are supported by a programmable limiter/DRC (Dynamic Range Compressor). This is useful to

optimize the output level for various applications and for use with small loudspeakers. This is an optional

feature that may be programmed to limit the maximum output level and/or boost an output level that is too small.

Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer.

These features are optional, and are programmable over wide ranges. This pair of digital processing features

may be applied jointly to either the ADC audio path or to the DAC audio path, but not to both paths

simultaneously.

1.1.4 Realtime Signal Level Readout and DSP Status

In addition to general read-back ability of all its registers, the NAU88C22 includes powerful capabilities to

readback signal related DSP information not possible with almost any other CODEC. In conjunction with the

ALC, the software by means of the readback function can determine the realtime signal level at the inputs, as

well as the realtime actual gain setting being used by the ALC. Additionally, other signal related information

can also be determined, such as the Noise Gate on/off status and Automute/Softmute function status. These

greatly enhance both the ability to optimize software and to enhance dynamic end product functionality.

1.1.5 Digital Interfaces

Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This

is a simple, but highly flexible interface that is compatible with many commonly used command and control

serial data protocols and host drivers.

Digital audio input/output data streams are transferred to and from the device separately from command and

control. The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with

commonly used industry standard devices that follow either of these two serial data formats.

1.1.6 Clock Requirements

The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided

externally, or by optional operation of a built-in PLL (Phase Locked Loop).

The PLL is provided as a low cost, zero external component count optional method to generate required clocks

in almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired

audio sample rates derived from a very wide range of commonly available system clocks.

The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the

range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit

value, any desired sample rate supported by the NAU88C22 can be generated with very high accuracy, typically

limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these

ranges are also possible, but may involve performance tradeoffs and increased design verification.

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2

Power Supply

This device has been designed to operate reliably using a wide range of power supply conditions and power-

on/power-off sequences. There are no special requirements for the sequence or rate at which the various power

supply pins change. Any supply can rise or fall at any time without harm to the device. However, pops and

clicks may result from some sequences. Optimum handling of hardware and software power-on and power-off

sequencing is described in more detail in the Applications section of this document.

2.1.1 Power-On Reset

The NAU88C22 does not have an external reset pin. The device reset function is automatically generated

internally when power supplies are too low for reliable operation. The internal reset is generated any time that

either VDDA or VDDC is lower than is required for reliable maintenance of internal logic conditions. The reset

threshold voltage for VDDA and VDDC is approximately 1.4Vdc. If both VDDA and VDDC are being reduced

at the same time, the threshold voltage may be slightly lower. Note that these are much lower voltages than are

required for normal operation of the chip. These values are mentioned here as general guidance as to overall

system design.

If either VDDA or VDDC is below its respective threshold voltage, an internal reset condition is

asserted. During this time, all registers and controls are set to the hardware determined initial

conditions. Software access during this time will be ignored, and any expected actions from software activity

will be invalid.

When both VDDA and VDDC reach a value above their respective thresholds, an internal reset pulse is

generated which extends the reset condition for an additional time. The duration of this extended reset time is

approximately 50 microseconds, but not longer than 100 microseconds. The reset condition remains asserted

during this time. If either VDDA or VDDC at any time becomes lower than its respective threshold voltage, a

new reset condition will result. The reset condition will continue until both VDDA and VDDC again higher than

their respective thresholds. After VDDA and VDDC are again both greater than their respective threshold

voltage, a new reset pulse will be generated, which again will extend the reset condition for not longer than an

additional 100 microseconds.

2.1.2 Power Related Software Considerations

There is no direct way for software to determine that the device is actively held in a reset condition. If there is a

possibility that software could be accessing the device sooner than 100 microseconds after the VDDA and

VDDC supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a

value to any register other than register 0x00, with that value being different than the power-on reset initial

values. The optimum choice of register for this purpose may be dependent on the system design, and it is

recommended the system engineer choose the register and register test bit for this purpose. After writing the

value, software will then read back the same register. When the register test bit reads back as the new value,

instead of the power-on reset initial value, software can reliably determine that the reset condition has ended.

Although it is not required, it is strongly recommended that a Software Reset command should be issued after

power-on and after the power-on reset condition is ended. This will help insure reliable operation under every

power sequencing condition that could occur.

If there is any possibility that VDDA or VDDC could be unreliable during system operation, software may be

designed to monitor whether a power-on reset condition has happened. This can be accomplished by writing a

test bit to a register that is different from the power-on initial conditions. This test bit should be a bit that is

never used for any other reason, and does not affect desired operation in any way. Then, software at any time

can read this bit to determine if a power-on reset condition has occurred. If this bit ever reads back other than

the test value, then software can reliably know that a power-on reset event has occurred. Software can

subsequently re-initialize the device and the system as required by the system design.

2.1.3 Software Reset

All chip registers can be reset to power-on default conditions by writing any value to register 0, using any of the

control modes. Writing valid data to any other register disables the reset, but all registers need to have the

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correct operating data written. See the applications section on powering NAU88C22 up for information on

avoiding pops and clicks after a software reset.

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3

Input Path Detailed Descriptions

The NAU88C22 provides multiple inputs to acquire and process audio signals from microphones or other

sources with high fidelity and flexibility. There are left and right input paths, each with three input pins, which

can be used to capture signals from single-ended, differential or dual-differential microphones. These input

channels each include a programmable gain amplifier (PGA). The outputs of the PGAs, plus two additional

auxiliary inputs, are then connected to the input boost/mix stages for maximum flexibility handling various

signal sources.

All inputs are maintained at a DC bias at approximately ½ of the AVDD supply voltage. Connections to these

inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application.

Differential microphone input (MICN & MICP pins) and Programmable Gain Amplifier

The NAU88C22 features a low-noise, high common mode rejection ratio (CMRR), differential microphone

input pair, MICP and MICN, which are connected to a PGA gain stage. The differential input structure is

essential in noisy digital systems where amplification of low-amplitude analog signals is necessary such as in

portable digital media devices and cell phones. Differential inputs very useful to reduce ground noise in systems

in which there are ground voltage differences between different chips and other components. When properly

implemented, the differential input architecture offers an improved power-supply rejection ratio (PSRR) and

higher ground noise immunity.

3.1 Programmable Gain Amplifier (PGA)

Each PGA supports three possible inputs, MICP, MICN, and LIN. These are the microphone differential pair

and a separate line level input. The PGA has a gain range of -12dB through +35.25dB in evenly spaced decibel

increments of 0.75dB. Operation of the PGA is subject to control by the following registers:

R2 Power management controls for the left and right PGA

R2 Power management controls for ADC Mix/Boost (must be “on” for any PGA path to function)

R7 Zero crossing timeout control

R32 Automatic Level Control (ALC) for the left and right PGA

R44 Input selection options for the left and right PGA

R45 Volume (gain), mute, update bit, and zero crossing control for the left PGA

R46 Volume (gain), mute, update bit, and zero crossing control for the right PGA

Important: The R45 and R46 update bits are write-only bits. The primary intended purpose of the update bit is

to enable simultaneous changes to both the left and right PGA volume values, even though these values must be

written sequentially. When there is a write operation to either R45 or R46 volume settings, but the update bit is

not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When

there is a write operation to either R45 or R46 and the update bit is set (value = 1), then the new value in the

register being written is immediately put into effect, and any pending value in the other PGA volume register is

put into effect at the same time.

Note: If the ALC automatic level control is enabled, the function of the ALC is to automatically adjust the R45

or R46 volume setting. If ALC is enabled for the left or right, or both channels, then software should avoid

changing the volume setting for the affected channel or channels. The reason for this is to avoid unexpected

volume changes caused by competition between the ALC and the direct software control of the volume setting.

Zero-Crossing controls are implemented to suppress clicking sounds that may occur when volume setting

changes take place while an audio input signal is active. When the zero crossing function is enabled (logic = 1),

any volume change for the affected channel will not take place until the audio input signal passes through the

zero point in its peak-to-peak swing. This prevents any instantaneous voltage change to the audio signal caused

by volume setting changes. If the zero crossing function is disabled (logic = 0), volume changes take place

instantly on condition of the Update Bit, but without regard to the instantaneous voltage level of the affected

audio input signal.

The R7 zero crossing timeout control is an additional feature to limit the amount of time that a volume change to

the PGA is delayed pending a zero crossing event. If the input signal is such that there are no zero crossing

events, and the timeout control is enabled (level = 1), any new volume setting to either PGA will automatically

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be put into effect after between 2.5 and 3.5 periods of the Slow Timer Clock (see description under

“Miscellaneous Functions”).

3.1.1 Zero Crossing Example

This drawing shows in a graphical form the problem and benefits of using the zero crossing feature. There is a

major audible improvement as a result of using the zero crossing feature.

PGA Output with

Zero Cross Enabled

PGA Output with

Zero Cross Disabled

PGA Input

Gain Change

Figure 2: Zero Crossing Gain Update Operation

PGA Gain

R45, R46

Input Selection

R44

MICN

MICP

R

To ADC

Mix/Boost

R

-12 dB to

+35.25 dB

VREF

LIN

R

VREF

Figure 3: PGA Input Structure Simplified Schematic

3.2 Positive Microphone Input (MICP)

The positive (non-inverting) microphone input (MICP) can be used separately, or as part of a differential input

configuration. This input pin connects to the positive (non-inverting) terminal of the PGA amplifier under

control of register R44. When the R44 associated control bit is set (logic = 1), a switch connects MICP to the

PGA input. When the associated control bit is not set (logic = 0), the MICP pin is connected to a resistor of

approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound

by keeping the DC level of the MICP pin close to VREF at all times.

Note: If the MICP signal is not used differentially with MICN, the PGA gain values will be valid only if the

MICN pin is terminated to a low impedance signal point. This termination should normally be an AC coupled

path to signal ground.

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This input impedance is constant regardless of the gain value. The nominal input impedance for this input is

given by the following table. Impedance for specific gain values not listed in this table can be estimated

through interpolation between listed values.

Gain

(dB)

-12

Impedance

(kΩ)

Nominal Input Impedance

94

-9

-6

94

LMICP & RMICP to

non-inverting PGA input

-3

0

or

3

6

LLIN & RLIN to

non-inverting PGA input

9

12

18

30

35.25

Table 1: Microphone and Line Non-Inverting Input Impedances

3.3 Negative Microphone Input (MICN)

The negative (inverting) microphone input (MICN) can be used separately, or as part of a differential input

configuration. This input pin connects to the negative (inverting) terminal of the PGA amplifier under control of

register R44. When the R44 associated control bit is set (logic = 1), a switch connects MICP to the PGA input.

When the associated control bit is not set (logic = 0), the MICN pin is connected to a resistor of approximately

30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the

DC level of the MICN pin close to VREF at all times.

It is important for a system designer to know that the MICN input impedance varies as a function of the selected

PGA gain. This is normal and expected for a difference amplifier type topology. The nominal resistive

impedance values for this input over the possible gain range are given by the following table. Impedance for

specific gain values not listed in this table can be estimated through interpolation between listed values.

Gain

(dB)

Impedance

Nominal Input Impedance

(kΩ)

-12

-9

75

69

63

55

47

39

31

25

19

11

2.9

1.6

-6

-3

0

3

LMICN or RMICN to

inverting PGA input

6

9

12

18

30

35.25

Table 2: Microphone Inverting Input Impedances

System designers should also note that at the highest gain values, the input impedance is relatively low. For

most inputs, the best strategy if higher gain values are needed is to use the input PGA in combination with the

+20dB gain boost available on the PGA Mix/Boost stage that immediately follows the PGA output. A good

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guideline is to use the PGA gain for up to around 20dB of gain. If more gain than this is required and the lower

input impedance of the PGA at high gains is a problem, a combination of the PGA and boost stage should be

used. In this type of combined gain configuration, it is preferred to have at least 6dB gain at the PGA input stage

to benefit from the PGA low noise characteristics.

3.4 Microphone biasing

The MICBIAS pin provides a low-noise microphone DC bias voltage as may be required for operation of an

external microphone. This built-in feature can typically provide up to 3mA of microphone bias current. This

DC bias voltage is suitable for powering either traditional ECM (electret) type microphones, or for MEMS types

microphones with an independent power supply pin.

Seven different bias voltages are available for optimum system performance, depending on the specific

application. The microphone bias pin normally requires an external filtering capacitor as shown on the

schematic in the Application section. The microphone bias function is controlled by the following registers:

R1 Power control for MICBIAS feature (enabled when bit 4 = 1)

R58 Optional low-noise mode and different bias voltage levels (enabled when bit 4 = 1)

R44 Primary MICBIAS voltage selection

The low-noise feature results in greatly reduced noise in the external MICBIAS voltage by placing a resistor of

approximately 200-ohms in series with the output pin. This creates a low pass filter in conjunction with the

external micbias filter capacitor, but without any additional external components. The low noise feature is

enabled when the mode control bit 4 in register R58 is set (level = 1)

Register 44,

Bits 7-8

Register 58,

Bit 4

Microphone

Bias Voltage

Register 58, bit 4

MICBIASM

Register 1, bit 4

MICBIASEN

VREF

00

01

10

11

00

01

10

11

0

1

0.90 * VDDA

0.65 * VDDA

0.75 * VDDA

0.50 * VDDA

0.85 * VDDA

0.60 * VDDA

0.70 * VDDA

0.50 * VDDA

MICBIAS

R

Register 44, bits 7-8

MICBIASV

Figure 4: Microphone Bias Generator

3.5 Line/Aux Input Impedance and Variable Gain Stage Topology

Except for the input PGAs, other variable gain stages are implemented similarly to the simplified schematic

shown here. The gain value changes affect input impedance in the ranges detailed in the description of each type

of input path. If a path is in the “not selected” condition, then the input impedance will be in a high impedance

condition. If an external input pin is not used anywhere in the system, it will be coupled to a DC tie-off of

approximately 30kΩ coupled to VREF. The unused input/output tie-off function is explained in more detail in

the Application Information section of this document.

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Gain Value

Adjustment

“Not Selected”

Switch

Input

R

To Next

Stage

VREF

-15 dB to

+6.0 dB

Figure 5: Variable Gain Stage Simplified Schematic

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The input impedance presented to these inputs depends on the input routing choices and gain values. If an input

is routed to more than one internal input node, then the effective input impedance will be the parallel

combination of the impedance of the multiple nodes that are used. The impedance looking into the PGA non-

inverting input is constant as listed in the section discussing the microphone input PGAs. The nominal resistive

input impedances looking into the ADC Mix/Boost input inputs are listed in the following table:

Gain

(dB)

Impedance

Inputs

(kΩ)

Not Selected

High-Z

159

113

80

-12

-9

-6

-3

0

LAUXIN & RAUXIN to

L/RADC MIX/BOOST amp

or

57

40

LLIN & RLIN to

L/RADC MIX/BOOST amp

3

28

6

20

Table 3: MIX/BOOST Amp Impedances

The nominal resistive input impedances presented to signal pins that are directly routed to an output mixer are

listed in the following table. If an input is connected to other active nodes, then this value is in parallel with the

resistive input impedance of any such other node.

Gain

(dB)

-15

Impedance

(kΩ)

Inputs

225

LAUXIN & RAUXIN to

bypass amp

-12

-9

-6

-3

0

159

113

80

Or

57

40

RAUXIN to

RSPK SUBMIXER amp

3

28

6

20

Table 4: Bypass Amp and RSPK SUBMIXER Input Impedances

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3.6 Left and Right Line Inputs (LLIN and RLIN)

A third possible input to the left or right PGA is an optional associated LIN left or right line level input. These

inputs may be routed to the PGA non-inverting input, and/or connect directly to the ADC Mixer/Boost stage. If

routed to the PGA, this signal is processed as an alternate pin for the MICP signal. LIN may be received

differentially in relation to the MICN pin and has available the same gain range as for MICP. As in the

operational case of using the MICP input, the MICN input must have a low impedance path to signal ground, so

that the gain values chosen in the PGA are valid.

Note: It not recommended that both the LIN line input path to the PGA and the MICP path to the PGA be

enabled at the same time. This will cause the differential gain to be unbalanced, and result in poor common

mode rejection. Also, this will result in the LIN and MICP signals being connected together through internal

chip resistors.

The line input pins, may alternatively be configured to operate as a GPIO (General Purpose Input/Output) logic

input pin. This intended purpose is static logic voltage level sensing to determine if a headset is present or not as

part of a physical detection of a possible external headset. Only one GPIO pin at any one time can be assigned

for this purpose.

Registers that affect operation of the LLIN and RLIN inputs are:

R2 ADC Mix/Boost power control (must be “on” for any LIN path to function)

R9 GPIO selection for headset detect function

R44 PGA input selection control bits

If selected, all other PGA control registers (see PGA description)

R47 Left line input ADC Mix/Boost volume and mute (bits 4, 5, and 6)

R48 Right line input ADC Mix/Boost volume and mute (bits 4, 5, and 6)

3.7 Auxiliary inputs (LAUXIN, RAUXIN)

The left and right channels each have an additional input that is separate from the programmable amplifier stage.

These are the left and right auxiliary inputs, LAUXIN and RAUXIN. These inputs may be routed to either or

both the associated ADC Mix/Boost stage, or the associated LCH MIX or RCH MIX output mixer.

The RAUXIN input may additionally be routed to the Right Speaker Submixer in the analog output section.

This path enables a sound to be output from the RSPKOUT speaker output, but without being audible anywhere

else in the system. One purpose of this path is to support a traditional “beep” sound, such as from a

microprocessor toggle bit. This is a historical application scenario which is now uncommon.

The auxiliary inputs are affected by the following registers:

ADC Mix/Boost if used (see ADC Mix/Boost section)

LCH MIXER or RCH MIXER if used (see output mixer section)

BEEP MIXER if used (see Beep Mixer section)

Note: no power control registers affect only the auxiliary inputs

The input impedance presented to these inputs depends on the input routing choices and gain values. If an input

is routed to more than one internal input node, then the effective input impedance will be the parallel

combination of the impedance of the multiple nodes that are used. The input impedances presented to these

inputs are the same as those listed for the LLIN and RLIN inputs.

3.8 ADC Mix/Boost Stage

The left and right channels each have an independent ADC Mix/Boost stage. Most analog input signals must

pass through the ADC Mix/Boost stage before use anywhere else in this device. The only analog inputs that can

completely bypass the ADC Mix/Boost stage are the LAUXIN and RAUXIN auxiliary inputs.

The ADC mixer stage has three inputs, AUX, LIN, and PGA. The AUX input is for the associated auxiliary

input, and the LIN is for the associated line input. The PGA input is an internal connection to the associated

programmable gain amplifier servicing the microphone and line inputs.

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All three inputs to the ADC Mix/Boost stage can be independently muted, and all three inputs have independent

gain controls. The AUX and LIN inputs have an available gain range of -12dB through +6dB in 3dB steps. The

PGA input path has a choice of 0dB or 20dB of gain in addition to the gain in the PGA.

Registers that affect the ADC Mix/Boot stage are:

R2 Power control for left and right channels

R45 mute function for left channel PGA (bit 6 = 0 = muted condition)

R46 mute function for right channel PGA (bit 6 = 0 = muted condition)

R47 gain and mute control for left channel AUX and LIN

R48 gain and mute control for right channel AUX and LIN

3.9 Input Limiter / Automatic Level Control (ALC)

The input section of the NAU88C22 is supported by additional combined digital and analog functionality which

implement an Automatic Level Control (ALC) function. This can be very useful to automatically manage the

analog input gain to optimize the signal level at the output of the programmable amplifier. The ALC can

automatically amplify input signals that are too small, or decrease the amplitude if the signals are too loud. This

system also helps to prevent clipping (overdrive) at the input of the ADC while maximizing the full dynamic

range of the ADC.

The ALC may be operated in the normal mode just described, on in a special limiter mode of operation. The

limiter mode is a faster mode of operation, the primary purpose of which is to limit too-loud signals. The limiter

mode of operation is described after this section which provides details on the normal mode of operation.

The functional block architecture for the ALC is shown below. The ALC monitors the output of the ADC,

measured after the digital decimator. The ADC output is fed into a peak detector, which updates the measured

peak value whenever the absolute value of the input signal is higher than the current measured peak. The

measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate measurement of

the signal envelope. The peak value is used by a logic algorithm to determine whether the PGA input gain

should be increased, decreased, or remain the same.

Rate Convert/

Decimator

Digital

Decimator

PGA

ADC

Filter

ALC

Figure 6: ALC Block Diagram

3.9.1 Normal Mode Example Operation

Immediately following is a simple example of the ALC operation. In the steady state at the beginning of the

example time sequence, the PGA gain is at a steady value which results in the desired output level from the ADC.

When the input signal suddenly becomes louder, the ALC reduces volume at a register determined rate and step

size. This continues until the output level of the ADC is again at the desired target level. When the input signal

suddenly becomes quiet, the ALC increases volume at a register determined rate and step size. When the output

level from the ADC again reaches the target level, and now the input remains at a constant level, the ALC

remains in a steady state.

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PGA Input

PGA Output

PGA Gain

Figure 7: ALC Normal Mode Operation

3.9.2 ALC Parameter Definitions

Automatic level and volume control features are complex and have difficult to understand traditional names for

many features and controls. This section defines some terms so that the explanations of this subsystem are more

clear.

ALC Maximum Gain: Register 32 (ALCMXGAIN) This sets the maximum allowed gain in the PGA during

normal mode ALC operation. In the Limiter mode of ALC operation, the ALCMXGAIN value is not used. In

the Limiter mode, the maximum gain allowed for the PGA is set equal to the pre-existing PGA gain value that

was in effect at the moment in time that the Limiter mode is enabled.

ALC Minimum Gain: Register 32 (ALCMNGAIN) This sets the minimum allowed gain in the PGA during all

modes of ALC operation. This is useful to keep the AGC operating range close to the desired range for a given

application scenario.

ALC Target Value: Register 33 (ALCSL) Determines the value used by the ALC logic decisions comparing

this fixed value with the output of the ADC. This value is expressed as a fraction of Full Scale (FS) output from

the ADC. Depending on the logic conditions, the output value used in the comparison may be either the

instantaneous value of the ADC, or otherwise a time weighted average of the ADC peak output level.

ALC Attack Time: Register 34 (ALCATK) Attack time refers to how quickly a system responds to an

increasing volume level that is greater than some defined threshold. Typically, attack time is much faster than

decay time. In the NAU88C22, when the absolute value of the ADC output exceeds the ALC Target Value, the

PGA gain will be reduced at a step size and rate determined by this parameter. When the peak ADC output is at

least 1.5dB lower than the ALC Target Value, the stepped gain reduction will halt.

ALC Decay Time: Register 34 (ALCDCY) Decay time refers to how quickly a system responds to a decreasing

volume level. Typically, decay time is much slower than attack time. When the ADC output level is below the

ALC Target value by at least 1.5dB, the PGA gain will increase at a rate determined by this parameter. The

decay time constant is determined by the setting in register 34, bits 4 to 7 (ALCDCY), which sets the delay

between increases in gain. In Limiter mode, the time constants are faster than in ALC mode. (See Detailed

Register Map.)

ALC Hold Time Register 33 (ALCHLD) Hold time refers to a duration of time when no action is taken. This is

typically to avoid undesirable sounds that can happen when an ALC responds too quickly to a changing input

signal. The use and amount of hold time is very application specific. In the NAU88C22, the hold time value is

the duration of time that the ADC output peak value must be less than the target value before there is an actual

gain increase.

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3.10 ALC Peak Limiter Function

To reduce clipping and other bad audio effects, all ALC modes include a peak limiter function. This implements

an emergency PGA gain reduction when the ADC output level exceeds a built-in maximum value. When the

ADC output exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum ALC

Attack Time rate, regardless of the mode and attack rate settings, until the ADC output level has been reduced

below the emergency limit threshold. This limits ADC clipping if there is a sudden increase in the input signal

level.

3.10.1 ALC Normal Mode Example Using ALC Hold Time Feature

Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter

for optimum performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief

periods of silence such as those that may appear in music recordings; having a shorter hold time, may be useful

in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different

volumes. The waveform below shows the operation of the ALCHLD parameter.

16ms delay for

ALCHT = 0100

PGA Input

PGA Output

PGA Gain

Hold Delay Change

Figure 8: ALC Hold Delay Change

3.11 Noise Gate (Normal Mode Only)

A noise gate threshold prevents ALC amplification of noise when there is no input signal, or no signal above an

expected background noise level. The noise gate is enabled by setting register 35, bit 3 (NGEN), HIGH, and the

threshold level is set in register 35, bits 0 to 2 (NGTH). This does not remove noise from the signal; when there

is no signal or a very quiet signal (pause) composed mostly of noise, the ALC holds the gain constant instead of

amplifying the signal towards the target threshold. The NAU88C22 accomplishes this by comparing the input

signal level against the noise gate threshold. The noise gate only operates in conjunction with the ALC and only

in Normal mode. The noise gate is asserted when:

Equation 1: (Signal at ADC – PGA gain – MIC Boost gain) < NGTH (Noise Gate Threshold Level)

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PGA Input

PGA Output

PGA Gain

Figure 9: ALC Operation Without Noise Gate

Noise Gate Threshold

PGA Input

PGA Output

PGA Gain

Figure 10: Noise Gate Operation

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3.12 ALC Example with ALC Min/Max Limits and Noise Gate Operation

The drawing below shows the effects of ALC operation over the full scale signal range. The drawing is color

coded to be more clear as follows:

Blue Original Input signal (linear line from zero to maximum)

Green PGA gain value over time (inverse to signal in target range)

Red Output signal (held to a constant value in target range)

Input < noise ALC operation range

gate threshold Target ALCSL -6dB

Gain (Attenuation) Clipped

at ALCMNGAIN -12dB

+33dB

PGA Gain

0dB

-12dB

-39dB

-6dB +6dB

Input Level

Register Bits

Name

Value Description

ALC enabled both channels

32

33

35

7-8

3-5

0-2

0-3

3

ALCSEL

11

Max ALC gain @ 35.25dB

ALCMAXGAIN 111

000

1011

1

Min ALC gain @ -12dB

Target ALC gain @ -6dBFS

Noise gate enabled

ALCMINGAIN

ALCLVL

NGEN

Noise gate @ -39dB

0-2

NGTH

000

Figure 11: ALC Response Envelope

3.12.1 ALC Register Map Overview

ALC can be enabled for either or both the left and right ADC channels. All ALC functions and mode settings

are common to the left and right channels. When either the right or left PGA is disabled, the respective PGA

will remain at the most recent gain value as set by the ALC. Registers that control the ALC features and

functions are:

R32 Enable left/right ALC functions; set maximum gain, minimum gain

R33 ALC hold time, ALC target signal level

R34 ALC limiter mode selection, attack parameters, decay parameters

R35 Enable noise gate, noise gate parameters

R70 Selection of signal level averaging options and ALC table options

R70 Realtime readout of left channel gain value in use by ALC (same as left in stereo operation)

R71 Realtime readout of right channel gain value in use by ALC (same as right in stereo operation)

R76 Realtime readout of input signal level from averaging peak-to-peak input signal detector

R77 Realtime readout of input signal level from averaging input signal peak detector

The following table shows some of the ALC parameter values and their ranges. The complete list of settings and

values is included in the Detailed Register Map.

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Registe

r

Parameter

Bits

Name

Default

Setting

000

Programmable Range

Value

ALCMING

AIN

ALCMAX

GAIN

Range: -12dB to +30dB @ 6dB

increments

Range: -6.75dB to +35.25dB @ 6dB

increments

Minimum Gain of PGA

32

0-2

3-5

-12dB

Maximum Gain of

PGA

111

00

35.25dB

00 = Disable

Disable 01 = Enable right channel

ALC Function

32

33

7-8

0-3

4-7

ALCEN

ALCLVL

ALCHLD

d

10 = Enable left channel

11 = Enable both channels

Range: -22.5dB to -1.5dBFS @ 1.5dB

increments

Range: 0ms to 1024ms at 1010 and

above

(times are for 0.75dB steps, and double

with every step)

ALCM=0 - Range: 125μs to 128ms

ALCM=1 - Range: 31μs to 32ms

(times are for 0.75dB steps, and double

with every step)

ALC Target Level

ALC Hold Time

1011

0000

-6dBFS

0ms

500μs

4ms

ALC Attack time

34

0-3

ALCATK

0010

ALCM = 0 - Range: 500μs to 512ms

ALCM = 1 - Range: 125μs to 128ms

(times are for 0.75dB steps, and double

with every step)

ALC Decay Time

Limiter Function

34

4-7

8

ALCDCY

0011

0

Disable 0 = ALC mode

1 = Limiter mode

ALCMODE

d

Table 5: Registers associated with ALC and Limiter Control

3.13 Limiter Mode

When register 34, bit 8, is HIGH and ALC is enabled in register 32, bits 7-8 (ALCEN), the ALC block operates

in limiter mode. In this mode, the PGA gain is constrained to be less than or equal to the PGA gain setting when

the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode

as indicated by the different lookup tables for these parameters for limiter mode. The following waveform

illustrates the behavior of the ALC in limiter mode in response to changes in various ALC parameters.

PGA Input

PGA Output

PGA Gain

Limiter Enabled

Figure 12: ALC Limiter Mode Operation

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4

ADC Digital Block

ADC Digital Filters

Digital

Audio

Interface

Digital

Filter

5-Band

Equalizer

High Pass

Filter

Notch

Filter

ΣΔ

ADC

Gain

The ADC digital block performs 24-bit analog-to-digital conversion and signal processing, making available a

high quality audio sample stream the audio path digital interface. This block consists of a sigma-delta modulator,

digital decimator/ filter, 5-band graphic equalizer, 3D effects, high pass filter, and a notch filter. The equalizer

and 3D audio function block is a single resource that may be used by either the ADC or DAC, but not both at the

same time. The ADC coding scheme is in twos complement format and the full-scale input level is proportional

to VDDA. With a 3.3V supply voltage, the full-scale level is 1.0V_RMS

.

Registers that affect the ADC operation are:

R2 Power management enable/disable left/right ADC

R5 Digital passthrough of ADC output data into DAC input

R7 Sample rate indication bits (affect filter frequency scaling)

R14 Oversampling, polarity inversion, and filter controls for left/right ADC

R14 ADC high pass filter Audio Mode or Application Mode selection

R15 Left channel ADC digital volume control and update bit function

R16 Right channel ADC digital volume control and update bit function

4.1 Sampling / Oversampling Rate, Polarity Control, Digital Passthrough

The audio sample rate of the ADC is determined entirely by the IMCLK internal Master Clock frequency, which

is 128 times the base audio sample rate. A technique known as oversampling is used to improve noise and

distortion performance of the ADC, but this does not affect the final audio sample rate. The default

oversampling rate of the ADC is 64X (64 times the audio sample rate), but this can be changed to 128X for

greatly improved audio performance. The higher rate increases power consumption by only approximately three

milliwatts per channel, so for most applications, the improved quality is a good choice. There is almost zero

increased power to also run the DACs at 128X oversampling, and the best overall quality will be achieved when

both the DACs and ADCs are operated at the same oversampling rate.

The polarity of either ADC output signal can be changed independently on either ADC logic output as a feature

sometimes useful in management of the audio phase. This feature can help minimize any audio processing that

may be otherwise required as the data are passed to other stages in the system.

Digital audio passthrough allows the output of the ADCs to be directly sent to the DACs as the input signal to

the DAC for DAC output. In this mode of operation, the output data from the ADCs are still available on the

ADCOUT logic pin. However, any external input signal for the DAC will be ignored. The passthrough function

is useful for many test and application purposes, and the DAC output may be utilized in any way that is normally

supported for the DAC analog output signals.

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4.2 ADC Digital Volume Control and Update Bit Functionality

The effective output audio volume of each ADC can be changed using the digital volume control feature. This

processes the output of the ADC to scale the output by the amount indicated in the volume register setting.

Included is a “digital mute” value which will completely mute the signal output of the ADC. The digital volume

setting can range from 0dB through -127dB in 0.5dB steps.

Important: The R15 and R16 update bits are write-only bits. The primary intended purpose of the update bit is

to enable simultaneous changes to both the left and right ADC volume values, even though these values must be

written sequentially. When there is a write operation to either R15 or R16 volume settings, but the update bit is

not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When

there is a write operation to either R15 or R16 and the update bit is set (value = 1), then the new value in the

register being written is immediately put into effect, and any pending value in the other ADC volume register is

put into effect at the same time.

4.3 ADC Programmable High Pass Filter

Each ADC is optionally supported by a high pass filter in the digital output path. Filter operation and settings

are always the same for both left and right channels. The high pass filter has two different operating modes. In

the audio mode, the filter is a simple first order DC blocking filter, with a cut-off frequency of 3.7Hz. In the

application specific mode, the filter is a second order audio frequency filter, with a programmable cut-off

frequency. The cutoff frequency of the high pass filter is scaled depending on the sampling frequency indicated

to the system by the setting in Register 7.

Registers that affect operation of the programmable high pass filter are:

R7 Sample rate indication to the system (affects filter coefficient internal scaling)

R14 High-pass enable/disable, operating mode, and cut-off frequency

The following table provides the exact cutoff frequencies with different sample rates as indicated to the system

by means of Register 7. The table shows the assumed actual numerical sample rates as determined by the system

clocks. Detailed response curves are provided in the Appendix section of this document.

Register

14, bits 4 to

6

Sample Rate in kHz (FS)

R7(SMPLR) = 011 or 010

R7(SMPLR) = 101 or 100

R7(SMPLR) = 001 or 000

8

11.025

12

16

22.05

24

32

44.1

48

(HPF)

000

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

82

113

141

180

225

281

360

450

563

122

153

156

245

306

392

490

612

001

010

011

100

101

110

111

102

131

163

204

261

327

408

102

131

163

204

261

327

408

102

131

163

204

261

327

408

Table 6: High Pass Filter Cut-off Frequencies in Hz (with HPFAM register 14, bit 7 = 1)

4.4 Programmable Notch Filter

Each ADC is optionally supported by a notch filter in the digital output path. Filter operation and settings are

always the same for both left and right channels. A notch filter is useful to a very narrow band of audio

frequencies in a stop band around a given center frequency. The notch filter is enabled by setting register 27, bit

7 (NFCEN), to 1. The center frequency is programmed by setting registers 27, 28, 29, and 30, bits 0 to 6

(NFA0[13:7], NFA0[6:0], NFA1[13:7], NFA1[6:0]), with two’s compliment coefficient values calculated using

table __.

Registers that affect operation of the notch filter are:

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June, 2016

R27 Notch filter enable/disable

R27 Notch filter a0 coefficient high order bits and update bit

R28 Notch filter a0 coefficient low order bits and update bit

R29 Notch filter a1 coefficient high order bits and update bit

R30 Notch filter a1 coefficient low order bits and update bit

Important: The register update bits are write-only bits. The update bit function is important so that all filter

coefficients actively being used are changed simultaneously, even though these register values must be written

sequentially. When there is a write operation to any of the filter coefficient settings, but the update bit is not set

(value = 0), the value is stored as pending for the future, but does not go into effect. When there is a write

operation to any coefficient register, and the update bit is set (value = 1), then the new value in the register being

written is immediately put into effect, and any pending coefficient value is put into effect at the same time.

Coefficient values are in the form of 2’s-complement integer values, and must be calculated based upon the

desired filter properties. The mathematical operations for calculating these coefficients are detailed in the

following table.

A₀

A₁

Notation

Register Value (DEC)

NFCA0 = -A₀x 2¹³

NFCA1 = -A₁x 2¹²

























2  f_b

2 f_s

1 tan

1 tan

f_c= center frequency (Hz)

f_b= -3dB bandwidth (Hz)

 2 

f







c



x cos





1 A



0



f

Note: Values are rounded to

f_s= sample frequency (Hz) the nearest whole number and

s



2  f_b

2 f_s

converted to 2’s complement

Table 7: Equations to calculate notch filter coefficients

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5

DAC Digital Block

DAC Digital Filters

Digital

Peak

Limiter

Digital

Audio

Interface

5-Band

Equalizer

Digital

Filter

ΣΔ

DAC

3D

Gain

The DAC digital block uses 24-bit signal processing to generate analog audio with a 16-bit digital sample stream

input. This block consists of a sigma-delta modulator, digital decimator/filter, and optional 5-band graphic

equalizer/3D effects block, and a dynamic range compressor/limiter. The DAC coding scheme is in twos

complement format and the full-scale output level is proportional to VDDA. With a 3.3V supply voltage, the

full-scale output level is 1.0V_RMS

.

Registers that affect the DAC operation are:

R3 Power management enable/disable left/right DAC

R5 Digital passthrough of ADC output data into DAC input

R7 Sample rate indication bits (affect filter frequency scaling)

R10 Softmute, Automute, oversampling options, polarity controls for left/right DAC

R11 Left channel DAC digital volume value; update bit feature

R12 Right channel DAC digital volume value; update bit feature

5.1 DAC Soft Mute

Both DACs are initialized with the SoftMute function disabled, which is a shared single control bit. Softmute

automatically ramps the DAC digital volume down to zero volume when enabled, and automatically ramps the

DAC digital volume up to the register specified volume level for each DAC when disabled. This feature

provides a tool that is useful for using the DACs without introducing pop and click sounds.

5.2 DAC AutoMute

The analog output of both DACs can be automatically muted in a no signal condition. Both DACs share a single

control bit for this function. When automute is enabled, the analog output of the DAC will be muted any time

there are 1024 consecutive audio sample values with a zero value. If at any time there is a non-zero sample

value, the DAC will be un-muted, and the 1024 count will be reinitialized to zero.

5.3 DAC Sampling / Oversampling Rate, Polarity Control, Digital Passthrough

The sampling rate of the DAC is determined entirely by the frequency of its input clock and the oversampling

rate setting. The oversampling rate of the DAC can be changed to 128X for improved audio performance at

slightly higher power consumption. Because the additional supply current is only 1mA, in most applications the

128X oversampling is preferred for maximum audio performance.

The polarity of either DAC output signal can be changed independently on either DAC analog output as a feature

sometimes useful in management of the audio phase. This feature can help minimize any audio processing that

may be otherwise required as the data are passed to other stages in the system.

Digital audio passthrough allows the output of the ADCs to be directly sent to the DACs as the input signal to

the DAC for DAC output. In this mode of operation, the external digital audio signal for the DAC will be

NAU88C22 Datasheet Rev 0.6

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June, 2016

ignored. The passthrough function is useful for many test and application purposes, and the DAC output may be

utilized in any way that is normally supported for the DAC analog output signals.

5.4 DAC Digital Volume Control and Update Bit Functionality

The effective output audio volume of each DAC can be changed using the digital volume control feature. This

processes the output of the DAC to scale the output by the amount indicated in the volume register setting.

Included is a “digital mute” value which will completely mute the signal output of the DAC. The digital volume

setting can range from 0dB through -127dB in 0.5dB steps.

Important: The R11 and R12 update bits are write-only bits. The primary intended purpose of the update bit is

to enable simultaneous changes to both the left and right DAC volume values, even though these values must be

written sequentially. When there is a write operation to either R11 or R12 volume settings, but the update bit is

not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When

there is a write operation to either R11 or R12 and the update bit is set (value = 1), then the new value in the

register being written is immediately put into effect, and any pending value in the other DAC volume register is

put into effect at the same time.

5.5 DAC Automatic Output Peak Limiter / Volume Boost

Both DACs are supported by a digital output volume limiter/boost feature which can be useful to keep output

levels within a desired range without any host/processor intervention. Settings are shared by both DAC channels.

Registers that manage the peak limiter and volume boost functionality are:

R24 Limiter enable/disable, limiter attack rate, boost decay rate

R25 Limiter upper limit, limiter boost value

The operation of the peak limiter is shown in the following figure. The upper signal graphs show the time

varying level of the input and output signals, and the lower graph shows the gain characteristic of the limiter.

When the signal level exceeds the limiter threshold value by 0.5dB or greater, the DAC digital signal level will

be attenuated at a rate set by the limiter attack rate value. When the input signal level is less than the boost lower

limit by 0.5dB or greater, the DAC digital volume will be increased at a rate set by the boost decay rate value.

The default boost gain value is limited not to exceed 0dB (zero attenuation).

DAC Input

Signal

Envelope

Threshold

DAC Output

-1dB

Signal

Envelope

0dB

-0.5dB

-1dB

Digital Gain

Figure 13: DAC Digital Limiter Control

The limiter may optionally be set to automatically boost the DAC digital signal level when the signal is more

than 0.5dB below the limiter threshold. This can be useful in applications in which it is desirable to compress

the signal dynamic range. This is accomplished by setting the limiter boost register bits to a value greater than

zero. If the limiter is disabled, this boost value will be applied to the DAC digital output signal separate from

other gain affecting values.

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5.6 5-Band Equalizer

The NAU88C22 includes a 5-band graphic equalizer with low distortion, low noise, and wide dynamic range.

The equalizer is applied to both left and right channels. The equalizer is grouped with the 3D Stereo

Enhancement signal processing function. Both functions may be assigned to support either the ADC path, or the

DAC path, but not both paths simultaneously.

Registers that affect operation of the 5-Band Equalizer are:

R18 Assign equalizer to DAC path or to ADC path (default = ADC path)

R18 Band 1 gain control and cut-off frequency

R19 Band 2 gain control, center cut-off frequency, and bandwidth

R20 Band 3 gain control, center cut-off frequency, and bandwidth

R21 Band 4 gain control, center cut-off frequency, and bandwidth

R22 Band 5 gain control and cut-off frequency

Each of the five equalizer bands is independently adjustable for maximum system flexibility, and each offers up

to 12dB of boost and 12dB of cut with 1dB resolution. The high and the low bands are shelving filters (high-

pass and low-pass, respectively), and the middle three bands are peaking filters. Details of the register value

settings are described below. Response curve examples are provided in the Appendix of this document.

Equalizer Band

1 (High Pass)

Register 18

Bits 5 & 6

EQ1CF

2 (Band Pass)

Register 19

Bits 5 & 6

EQ2CF

3 (Band Pass)

Register 20

Bits 5 & 6

EQ3CF

4 (Band Pass)

Register 21

Bits 5 & 6

EQ4CF

5 (Low Pass)

Register 22

Bits 5 & 6

EQ5CF

Register

Value

00

01

10

11

80Hz

105Hz

135Hz

175Hz

230Hz

300Hz

385Hz

500Hz

650Hz

850Hz

1.1kHz

1.4kHz

1.8kHz

2.4kHz

3.2kHz

4.1kHz

5.3kHz

6.9kHz

9.0kHz

11.7kHz

Table 8: Equalizer Center/Cutoff Frequencies

Register Value

Binary

00000

00001

00010

- - -

01100

01101

- - -

11000

Gain

Registers

Hex

00h

01h

02h

- -

0Ch

17h

- -

18h

+12db

+11dB

+10dB

Bits 0 to 4

in registers

Increments 1dB per step

0dB

-11dB

Increments 1dB per step

-12dB

18 (EQ1GC)

19 (EQ2GC)

20 (EQ3GC)

21 (EQ4GC)

22 (EQ5GC)

11001 to 11111

19h to 1Fh

Reserved

Table 9: Equalizer Gains

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5.7 3D Stereo Enhancement

NAU88C22 includes digital circuitry to provide flexible 3D enhancement to increase the perceived separation

between the right and left channels, and has multiple options for optimum acoustic performance. The equalizer

is grouped with the 3D Stereo Enhancement signal processing function. Both functions may be assigned to

support either the ADC path, or the DAC path, but not both paths simultaneously.

Registers that affect operation of 3D Stereo Enhancement are:

R18 Assign equalizer to DAC path or to ADC path (default = ADC path)

R41 3D Audio depth enhancement setting

The amount of 3D enhancement applied can be programmed from the default 0% (no 3D effect) to 100% in

register 41, bits 0 to 3 (DEPTH3D), as shown in Table __. Note: 3D enhancement uses increased gain to

achieve its effect, so that the source signal may need to be attenuated by up to 6dB to avoid clipping.

Register 41

Bits 0 to 3

3DDEPTH

3D Effect

0000

0001

0010

0%

6.7%dB

13.4%dB

Increments 6.67% for each

binary step in the input word

- - -

1110

1111

93.3%

100%

Table 10: 3D Enhancement Depth

5.8 Companding

Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit

rates, using non-linear algorithms. NAU88C22 supports the two main telecommunications companding

standards on both the transmit and the receive sides: A-law and µ-law. The A-law algorithm is primarily used in

European communication systems and the µ-law algorithm is primarily used by North America, Japan, and

Australia. . Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization.

The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits)

Following are the data compression equations set in the ITU-T G.711 standard and implemented in the NAU88C22:

5.9 µ-law

F(x) = ln( 1 + µ|x|) / ln( 1 + µ)

-1 ≤ x ≤ 1

with µ=255 for the U.S. and Japan

5.10 A-law

with A=87.6 for Europe

The register affecting companding operation is:

R5 Enable 8-bit mode, enable DAC companding, enable ADC companding

The companded signal is an 8-bit word consisting of a sign bit, three bits for the exponent, and four bits for the

mantissa. When companding is enabled, the PCM interface must be set to an 8-bit word length. When in 8-bit

mode, the Register 4 word length control (WLEN) is ignored.

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June, 2016

Register 5

Bit3 Bit 2

Companding Mode

Bit 4

0

Bit 1

0

No Companding (default)

0

ADC

A-law

μ-law

1

0

DAC

A-law

μ-law

1

0

Table 11: Companding Control

5.11 8-bit Word Length

6

Writing a 1 to register 5, bit 5 (CMB8), will cause the PCM interface

to use 8-bit word length for data transfer, overriding the word length

configuration setting in WLEN (register 4, bits 5 and 6.).

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June, 2016

Analog Outputs

The NAU88C22 features six different analog outputs. These are highly flexible and may be used individually or

in pairs for many purposes. However, they are grouped in pairs and named for their most commonly used stereo

application end uses. The following sections detail key features and functions of each type of output. Included

is a description of the associated output mixers. These mixers are separate internal functional blocks that are

important toward understanding all aspects of the analog output section.

Important: For analog outputs depopping purpose, when powering up speakers, headphone, AUXOUTs,

certain delays are generated after enabling sequence. However, the delays are created by MCLK and sample

rate register. For correct operation, sending I2S signal no earlier than 250ms after speaker or headphone

enabled and MCLK appearing.

6.1 Main Mixers (LMAIN MIX and RMAIN MIX)

Each left and right channel is supported by an independent main mixer. This mixer combines signals from a

various available signal sources internal to the device. Each mixer may also be selectively enabled/disabled as

part of the power management features. The outputs of these mixers are the only signal source for the

headphone outputs, and the primary signal source for the loudspeaker outputs.

Each mixer can accept either or both the left and right digital to analog (DAC) outputs. Normally, the left and

right DAC is mixed into the associated left and right main output mix. This additional capability to mix opposite

DAC channels enables switching the left and right DAC outputs to the opposite channel, or mixing together the

left and right DAC signals – all without any processor or host intervention and processing overhead.

Each mixer also can also combine signals directly from the respective left or right AUX input, and from the

output of the respective ADC Mix/Boost stage output. Each of these paths may be muted, or have an applied

selectable gain between -15dB and +6dB in 3dB steps.

Registers that affect operation of the Main Mixers are:

R3 Power control for the left and right main mixer

R49 left and right DAC cross-mixing source selection options

R50 left DAC to left main mixer source selection option

R51 right DAC to right main mixer source selection option

R50 left AUX and ADC Mix/Boost source select, and gain settings

R51 right AUX and ADC Mix/Boost source select, and gain settings

6.2 Auxiliary Mixers (AUX1 MIXER and AUX2 MIXER)

Each auxiliary analog output channel is supported by an independent mixer dedicated to the auxiliary output

function. This mixer combines signals from a various available signal sources internal to the device. Each

mixer may also be selectively enabled/disabled as part of the power management features.

Unlike the main mixers, the auxiliary mixers are not identical and combine different signal sets internal to the

device. These mixers in conjunction with the auxiliary outputs greatly increase the overall capabilities and

flexibility of the NAU88C22.

The AUX1 mixer combines together any or all of the following:

Left Main Mixer output

Right Main Mixer output

Left DAC output

Right DAC output

Right ADC Mix/Boost stage output

The AUX2 mixer combines together any or all of the following:

Left Main Mixer output

Left DAC output

Left ADC Mix/Boost stage output

Inverted output from AUX1 mixer stage

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Registers that affect operation of the Auxiliary Mixers are:

R1 Power control for the left and right auxiliary mixer

R56 Signal source selection for the AUX2 mixer

R57 Signal source selection for the AUX1 mixer

6.3 Right Speaker Submixer

The right speaker submixer serves two important functions. One is to optionally invert the output from the Right

Main Mixer as an optional signal source for the right channel loudspeaker output driver. This inversion is

normal and necessary in typical applications using the loudspeaker drivers.

The other function of the right speaker submixer is to mix the RAUXIN input signal directly into the right

channel speaker output driver. This enables the RAUXIN signal to be output on the right loudspeaker channel,

but not be mixed to any other output. The traditional purpose of this path is to support an old-style beep sound,

such as traditionally generated by a microprocessor output toggle bit. On the NAU88C22, this traditional

function is supported by a full quality signal path that may be used for any purpose. The volume for this path

has a selectable gain from -15dB through +6dB in 3dB step increments.

There is no separate power management control feature for the Right Speaker Submixer. The register that

affects the Right Speaker Submixer is:

R43 Input mute controls, volume for RAUXIN path

6.4 Headphone Outputs (LHP and RHP)

These are high quality, high current output drivers intended for driving low impedance loads such as headphones,

but also suitable for a wide range of audio output applications. The only signal source for each of these outputs

is from the associated left and right Main Mixer. Power for this section is provided from the VDDA pin. Each

driver may be selectively enabled/disabled as part of the power management features.

Each output can be individually muted, or controlled over a gain range of -57dB through +6dB in 3dB steps.

Gain changes for the two headphone outputs can be coordinated through use of an update bit feature as part of

the register controls. Additionally, clicks that could result from gain changes can be suppressed using an

optional zero crossing feature.

Registers that affect the headphone outputs are:

R2 Power management control for the left and right headphone amplifier

R52 Volume, mute, update, and zero crossing controls for left headphone driver

R53 Volume, mute, update, and zero crossing controls for right headphone driver

Important: The R52 and R53 update bits are write-only bits. The primary intended purpose of the update bit is

to enable simultaneous changes to both the left and right headphone output volume values, even though these

two register values must be written sequentially. When there is a write operation to either R52 or R53 volume

settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but

does not go into effect. When there is a write operation to either R52 or R53 and the update bit is set (value = 1),

then the new value in the register being written is immediately put into effect, and any pending value in the other

headphone output volume register is put into effect at the same time.

Zero-Crossing controls are implemented to suppress clicking sounds that may occur when volume setting

changes take place while an audio input signal is active. When the zero crossing function is enabled (logic = 1),

any volume change for the affected channel will not take place until the audio input signal passes through the

zero point in its peak-to-peak swing. This prevents any instantaneous voltage change to the audio signal caused

by volume setting changes. If the zero crossing function is disabled (logic = 0), volume changes take place

instantly on condition of the Update Bit, but without regard to the instantaneous voltage level of the affected

audio input signal.

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6.5 Speaker Outputs

These are high current outputs suitable for driving low impedance loads, such as an 8-ohm loudspeaker. Both

outputs may be used separately for a wide range of applications, however, the intended application is to use both

outputs together in a BTL (Bridge-Tied-Load, and also, Balanced-Transformer-Less) configuration. In most

applications, this configuration requires an additional signal inversion, which is a feature supported in the right

speaker submixer block.

This inversion is normal and necessary when the two speaker outputs are used together in a BTL (Bridge-Tied-

Load, and also, Balanced-Transformer-Less) configuration. In this physical configuration, the RSPKOUT signal

is connected to one pole of the loudspeaker, and the LSPKOUT signal is connected to the other pole of the

loudspeaker. Mathematically, this creates within the loudspeaker a signal equal to (Left-Right). The desired

mathematical operation for a stereo signal is to drive the speaker with (Left+Right). This is accomplished by

implementing an additional inversion to the right channel signal. For most applications, best performance will

be achieved when care is taken to insure that all gain and filter settings in both the left and right channel paths to

the loudspeaker drivers are identical.

Power for the loudspeaker outputs is supplied via the VDDSPK pin, and ground is independently provided as the

VSSPK pin. This power option enables an operating voltage as high as 5Vdc and helps in a system design to

prevent high current outputs from creating noise on other supply voltage rails or system grounds. VSSPK must

be connected at some point in the system to VSSA, but provision of the VSSPK as a separate high current

ground pin facilitates managing the flow of current to prevent “ground bounce” and other ground noise related

problems.

Each loudspeaker output may be selectively enabled/disabled as part of the power management features.

Registers that affect the loudspeaker outputs are:

R3 Power management control of LSPKOUT and RSPKOUT driver outputs

R3 Speaker bias control (BIASGEN) set logic = 1 for maximum power and VDDSPK > 3.60Vdc

R48 Driver distortion mode control

R49 Disable boost control for speaker outputs for VDDSPK 3.3V or lower

R54 Volume (gain), mute, update bit, and zero crossing control for left speaker driver

R55 Volume (gain), mute, update bit, and zero crossing control for right speaker driver

Important: The R49 boost control option is set in the power-on reset condition for high voltage operation of

VDDSPK. If VDDSPK is greater than 3.6Vdc, the R49 boost control bits should be remain at the power-on

default settings. This insures reliable operation of the part, proper DC biasing, and optimum scaling of the signal

to enable the output to achieve full scale output when VDDSPK is greater than VDDA. In the boost mode, the

gain of the output stage is increased by a factor of 1.5 times the normal gain value.

Important: The R54 and R55 update bits are write-only bits. The primary intended purpose of the update bit is

to enable simultaneous changes to both the left and right headphone output volume values, even though these

two register values must be written sequentially. When there is a write operation to either R54 or R55 volume

settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but

does not go into effect. When there is a write operation to either R54 or R55 and the update bit is set (value = 1),