NUC029-LGN [NUVOTON]
Arm® Cortex®-M 32-bit Microcontroller;
| 型号： | NUC029-LGN |
| 厂家： | 
NUVOTON |
| 描述： | Arm® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总70页 (文件大小：1422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC029xDE
Arm® Cortex® -M
32-bit Microcontroller
NuMicro® Family
NUC029xDE Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Dec 18, 2018
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NUC029xDE
TABLE OF CONTENTS
1 GENERAL DESCRIPTION.....................................................................................7
2 FEATURES ............................................................................................................8
3 ABBREVIATIONS ................................................................................................11
4 PARTS INFORMATION LIST AND PIN CONFIGURATION................................12
4.1 NuMicro® NUC029 Series Selection Code ...................................................12
4.2 NuMicro® NUC029 Series Selection Guide ..................................................13
4.3 Pin Configuration .................................................................................14
4.3.1 NuMicro® NUC029LDE/NUC029SDE Pin Diagram ..............................................14
4.4 Pin Description....................................................................................16
4.4.1 NuMicro® NUC029LDE/NUC029SDE Pin Description...........................................16
5 BLOCK DIAGRAM...............................................................................................21
5.1 NuMicro® NUC029LDE/NUC029SDE Block Diagram......................................21
6 FUNCTIONAL DESCRIPTION.............................................................................22
6.1 ARM® Cortex® -M0 Core .........................................................................22
6.2 System Manager .................................................................................24
6.2.1 Overview ................................................................................................24
6.2.2 System Reset ..........................................................................................24
6.2.3 System Power Distribution ...........................................................................25
6.2.4 System Memory Map .................................................................................26
6.2.5 System Timer (SysTick) ..............................................................................27
6.2.6 Nested Vectored Interrupt Controller (NVIC)......................................................28
6.2.7 System Control.........................................................................................32
6.3 Clock Controller...................................................................................33
6.3.1 Overview ................................................................................................33
6.3.2 System Clock and SysTick Clock ...................................................................35
6.3.3 Power-down Mode Clock.............................................................................36
6.3.4 Frequency Divider Output ............................................................................37
6.4 Flash Memory Controller (FMC) ...............................................................38
6.4.1 Overview ................................................................................................38
6.4.2 Features.................................................................................................38
6.5 General Purpose I/O (GPIO) ...................................................................39
6.5.1 Overview ................................................................................................39
6.5.2 Features.................................................................................................39
6.7 Timer Controller (TIMER) .......................................................................40
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6.7.1 Overview ................................................................................................40
6.7.2 Features.................................................................................................40
6.8 PWM Generator and Capture Timer (PWM) .................................................41
6.8.1 Overview ................................................................................................41
6.8.2 Features.................................................................................................41
6.9 Watchdog Timer (WDT) .........................................................................43
6.9.1 Overview ................................................................................................43
6.9.2 Features.................................................................................................43
6.10Window Watchdog Timer (WWDT)............................................................44
6.10.1 Overview ................................................................................................44
6.10.2 Features.................................................................................................44
6.11UART Interface Controller (UART) ............................................................45
6.11.1 Overview ................................................................................................45
6.11.2 Features.................................................................................................45
6.12I2C Serial Interface Controller (I2C)............................................................46
6.12.1 Overview ................................................................................................46
6.12.2 Features.................................................................................................46
6.13Serial Peripheral Interface (SPI) ...............................................................47
6.13.1 Overview ................................................................................................47
6.13.2 Features.................................................................................................47
6.14Analog-to-Digital Converter (ADC) ............................................................48
6.14.1 Overview ................................................................................................48
6.14.2 Features.................................................................................................48
7 ELECTRICAL CHARACTERISTICS....................................................................49
7.1 Absolute Maximum Ratings.....................................................................49
7.2 DC Electrical Characteristics ...................................................................50
7.3 AC Electrical Characteristics ...................................................................54
7.3.1 External 4~24 MHz High Speed Oscillator ........................................................54
7.3.2 External 4~24 MHz High Speed Crystal ...........................................................54
7.3.3 Internal 22.1184 MHz High Speed Oscillator .....................................................55
7.3.4 Internal 10 kHz Low Speed Oscillator ..............................................................55
7.4 Analog Characteristics...........................................................................57
7.4.1 12-bit SARADC Specification........................................................................57
7.4.2 LDO and Power Management Specification ......................................................58
7.4.3 Low Voltage Reset Specification....................................................................59
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7.4.4 Brown-out Detector Specification ...................................................................59
7.4.5 Power-on Reset Specification .......................................................................59
7.5 Flash DC Electrical Characteristics............................................................61
7.6 I2C Dynamic Characteristics....................................................................62
7.7 SPI Dynamic Characteristics ...................................................................63
7.8 I2S Dynamic Characteristics ....................................................................65
8 APPLICATION CIRCUIT......................................................................................67
9 PACKAGE DIMENSIONS ....................................................................................68
9.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................68
9.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................69
10REVISION HISTORY............................................................................................70
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List of Figures
Figure 4-1 NuMicro® NUC029 Series Selection Code ................................................................... 12
Figure 4-2 NuMicro® NUC029SDE LQFP 64-pin Diagram ............................................................ 14
Figure 4-3 NuMicro® NUC029LDE LQFP 48-pin Diagram............................................................. 15
Figure 5-1 NuMicro® NUC029LDE/NUC029SDE Block Diagram.................................................. 21
Figure 6-1 Functional Controller Diagram...................................................................................... 22
Figure 6-2 NuMicro® NUC029LDE/NUC029SDE Power Distribution Diagram ............................. 25
Figure 6-3 Clock Generator Block Diagram................................................................................... 33
Figure 6-4 Clock Generator Global View Diagram......................................................................... 34
Figure 6-5 System Clock Block Diagram ....................................................................................... 35
Figure 6-6 SysTick Clock Control Block Diagram.......................................................................... 35
Figure 6-7 Clock Source of Frequency Divider .............................................................................. 37
Figure 6-8 Frequency Divider Block Diagram ................................................................................ 37
Figure 7-1 Typical Crystal Application Circuit ................................................................................ 55
Figure 7-2 HIRC Accuracy vs. Temperature.................................................................................. 55
Figure 7-3 Power-up Ramp Condition............................................................................................ 60
Figure 7-4 I2C Timing Diagram ...................................................................................................... 62
Figure 7-5 SPI Master Mode Timing Diagram ............................................................................... 63
Figure 7-6 SPI Slave Mode Timing Diagram ................................................................................. 64
Figure 7-8 I2S Slave Mode Timing Diagram................................................................................... 66
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List of Tables
Table 3-1 List of Abbreviations....................................................................................................... 11
Table 6-1 Address Space Assignments for On-Chip Controllers................................................... 26
Table 6-2 Exception Model ............................................................................................................ 29
Table 6-3 System Interrupt Map..................................................................................................... 30
Table 6-4 Vector Table Format ...................................................................................................... 31
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1
GENERAL DESCRIPTION
The NuMicro® NUC029LDE/NUC029SDE of NUC029 series is embedded with the Cortex® -M0
core and offers 68 Kbytes Flash, 4 Kbytes Flash for the ISP, and 8 Kbytes SRAM for industrial
control and applications which need rich communication interfaces or require high performance,
high integration.
Additionally, the NUC029LDE/SDE can run up to 50MHz and operate at standard industrial
voltage 2.5V ~ 5.5V with -40℃ ~ 105℃. It is also equipped with plenty of peripheral devices, such
as Timers, Watchdog Timer (WDT), Window Watchdog Timer (WWDT), UART, SPI, I2C, PWM,
GPIO, LIN, 1000 kSPS high speed 12-bit ADC, Low Voltage Reset Controller and Brown-out
Detector.
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2
FEATURES
Arm® Cortex® -M0 core
– Runs up to 50 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
– 68 Kbytes Flash for program code
– Configurable Flash memory for data memory (Data Flash), 4 Kbytes Flash for ISP loader
– Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for Flash
– Supports 2-wired ICP update through SWD/ICE interface
– Supports fast parallel programming mode by external programmer
SRAM Memory
– 8 Kbytes SRAM
Clock Control
– Flexible selection for different applications
– Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±2 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL output frequency up to 200 MHz, PWM clock frequency up to 100 MHz,
and System operation frequency up to 50 MHz
– External 4~24 MHz high speed crystal input for precise timing operation
GPIO
– Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level setting
Timer
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
Watchdog Timer
– Multiple clock sources
System clock (HCLK)
Internal 10 kHz oscillator (LIRC)
– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
– 6-bit down counter with 11-bit prescale for wide range window selected
PWM/Capture
– Supports maximum clock frequency up to 100MHz
– Supports up to two PWM modules, each module provides three 16-bit timers and 6 output
channels
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– Supports independent mode for PWM output/Capture input channel
– Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
– Supports 12-bit pre-scalar from 1 to 4096
– Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
– Supports mask function and tri-state enable for each PWM pin
– Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out detection and
CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
– Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
– Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
– Supports up to 12 capture input channels with 16-bit resolution
– Supports rising edges, falling edges or both edges capture condition
– Supports input rising edges, falling edges or both edges capture interrupt
– Supports rising edges, falling edges or both edges capture with counter reload option
UART
– Up to four UART controllers
– UART0 and UART1 ports with flow control (TXD, RXD, nCTS and nRTS)
– UART0, UART1 and UART2 with 16-byte FIFO for standard device
– Supports IrDA (SIR) and LIN function
– Supports RS-485 9-bit mode and direction control
– Supports auto baud-rate generator
SPI
– One set of SPI controller
– Supports SPI Master/Slave mode
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 8 to 32 bits
– MSB or LSB first data transfer
– Rx and Tx on both rising or falling edge of serial clock independently
– Supports Byte Suspend mode in 32-bit transmission
– Supports three wire, no slave select signal, bi-direction interface
I2C
– Up to two sets of I2C devices
– Master/Slave mode
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
– Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
– Programmable clocks allowing for versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports wake-up function
ADC
– 12-bit SAR ADC with 1000 kSPS
– Up to 8-ch single-end input or 4-ch differential input
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– Single scan/single cycle scan/continuous scan
– Each channel with individual result register
– Scan on enabled channels
– Threshold voltage detection
– Conversion started by software programming or external input
96-bit unique ID (UID)
128-bit unique customer ID(UCID)
Brown-out Detector
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ +105℃
Packages:
– All Green package (RoHS)
– LQFP 64-pin / 48-pin (7mm x 7mm)
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3
ABBREVIATIONS
Acronym
Description
ADC
APB
AHB
BOD
DAP
FIFO
FMC
GPIO
HCLK
HIRC
HXT
IAP
Analog-to-Digital Converter
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Debug Access Port
First In, First Out
Flash Memory Controller
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Phase-Locked Loop
PWM
SPI
Pulse Width Modulation
Serial Peripheral Interface
Samples per Second
SPS
TMR
UART
UCID
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
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4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC029 Series Selection Code
- X
NUC029 X X
CPU core
Temperature
Arm® Cortex M0
N: - 40 ℃ ~ +85℃
E: - 40 ℃ ~ +105℃
Package Type
Flash Size
A: Less than 68 KB
D: 68 KB
E: 128 KB
F: TSSOP 20
T: QFN 33 (5x5)
Z: QFN 33 (4x4)
N: QFN 48 (7x7)
L: LQFP 48 (7x7)
S: LQFP 64 (7x7)
K: LQFP 128 (14x14)
G: 256 KB
Figure 4-1 NuMicro® NUC029 Series Selection Code
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4.2 NuMicro® NUC029 Series Selection Guide
Connectivity
NUC029FAE 16
NUC029TAN 32
NUC029ZAN 64
NUC029LAN 64
NUC029LDE 68
NUC029SDE 68
2
4
4
4
8
8
Conf
4
-
-
2
4
4
4
4
4
8
8
4
4
4
17
24
24
40
42
56
31
45
35
49
86
2
4
4
4
4
4
4
4
4
4
4
1
2
2
2
4
4
2
3
3
3
3
1
1
1
2
1
1
1
2
2
2
2
1
2
2
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
3
5
4[1] 2[3]
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
-
√
√
√
√
√
√
√
√
√
√
√
TSSOP20 -40 to +105
QFN33(4*4) -40 to +85
QFN33(5*5) -40 to +85
5
5
3[2]
3[2]
4
-
√
√
√
√
√
√
√
√
√
√
4
-
-
-
-
-
5
-
-
-
4
-
-
-
-
-
8
8
-
-
√
-
LQFP48
LQFP48
LQFP64
LQFP48
LQFP64
LQFP48
LQFP64
LQFP128
-40 to +85
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
-40 to +105
Conf
Conf
-
-
-
3
3
2
3
-
-
12
12
4
8
-
-
-
-
-
-
8
-
-
-
-
NUC029LEE 128 16 Conf
NUC029SEE 128 16 Conf
NUC029LGE 256 20 Conf
NUC029SGE 256 20 Conf
NUC029KGE 256 20 Conf
-
-
1
1
1
1
1
-
10
12
9
-
9
9
5
5
5
√
√
√
√
√
-
-
-
-
6
-
√
√
√
√
2
2
2
3
3
3
2
2
2
10
2
2
2
-
12 15
12 20
-
[1] NUC029FAE is 10-bit ADC. All the others are 12-bit ADC.
[2] For NUC029TAN/NUC029ZAN, ACMP3 only has positive and negative input.
[3] For NUC029FAE , ACMP0 only has positive and negative input. And ACMP1 only has positive input.
[4] USCI can be configured to UART, SPI or I2C
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4.3 Pin Configuration
4.3.1 NuMicro® NUC029LDE/NUC029SDE Pin Diagram
4.3.1.1 NuMicro® NUC029SDE LQFP 64 pin (7 mm * 7mm)
UART3_RXD/ADC_CH5/PA.5
UART3_TXD/ADC_CH6/PA.6
VREF/ADC_CH7/PA.7
AVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
PB.11/TM3/PWM0_CH4
PE.5/TM1_EXT/TM1/PWM0_CH5
PC.0/SPI0_SS0
PC.1/SPI0_CLK
PC.2/SPI0_MISO0
PC.3/SPI0_MOSI0
PD.15/UART2_TXD
PD.14/UART2_RXD
PD.7
PWM0_BRAKE1/I2C0_SCL/PC.7
PWM0_BRAKE0/I2C0_SDA/PC.6
PC.15
NUC029SDE
LQFP 64-pin
PC.14
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
PD.6
VSS
PB.3/UART0_nCTS/TM3_EXT/TM3/PWM1_BRAKE0
PB.2/UART0_nRTS/TM2_EXT/TM2/PWM1_BRAKE1
PB.1/UART0_TXD
VDD
CLKO/PF.8
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 4-2 NuMicro® NUC029SDE LQFP 64-pin Diagram
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4.3.1.2 NuMicro® NUC029LDE LQFP 48 pin (7 mm * 7mm)
UART3_RXD/ADC_CH5/PA.5
UART3_TXD/ADC_CH6/PA.6
VREF/ADC_CH7/PA.7
AVDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPI0_SS0
PC.1/SPI0_CLK
PC.2/SPI0_MISO0
PC.3/SPI0_MOSI0
PD.15/UART2_TXD
PD.14/UART2_RXD
PD.7
PWM0_BRAKE1/I2C0_SCL/PC.7
PWM0_BRAKE0/I2C0_SDA/PC.6
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
NUC029LDE
LQFP 48-pin
PD.6
PB.3/UART0_nCTS/TM3_EXT/TM3/PWM1_BRAKE0
PB.2/UART0_nRTS/TM2_EXT/TM2/PWM1_BRAKE1
PB.1/UART0_TXD
XT1_IN/PF.1
nRESET
CLKO/PF.8
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 4-3 NuMicro® NUC029LDE LQFP 48-pin Diagram
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4.4 Pin Description
4.4.1 NuMicro® NUC029LDE/NUC029SDE Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
PB.14
I/O General purpose digital I/O pin.
External interrupt0 input pin.
1
2
3
INT0
I
PB.13
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PB.12
1
2
CLKO
O
Frequency divider clock output pin.
PF.5
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
4
5
6
7
8
9
I2C0_SCL
PWM1_CH5
PF.4
I/O PWM1 CH5 output/Capture input.
I/O General purpose digital I/O pin.
I/O I2C0 data input/output pin.
I/O PWM1 CH4 output/Capture input.
I/O General purpose digital I/O pin.
I/O I2C1 clock pin.
3
4
5
6
7
I2C0_SDA
PWM1_CH4
PA.11
I2C1_SCL
PWM1_CH3
PA.10
I/O PWM1 CH3 output/Capture input.
I/O General purpose digital I/O pin.
I/O I2C1 data input/output pin.
I/O PWM1 CH2 output/Capture input.
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
I2C1_SDA
PWM1_CH2
PA.9
I2C0_SCL
UART1_nCTS
PA.8
I
Clear to Send input pin for UART1.
I/O General purpose digital I/O pin.
I/O I2C0 data input/output pin.
I2C0_SDA
UART1_nRTS
PB.4
O
Request to Send output pin for UART1.
I/O General purpose digital I/O pin.
Data receiver input pin for UART1.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART1.
I/O General purpose digital I/O pin.
Request to Send output pin for UART1.
10
11
8
9
UART1_RXD
PB.5
I
UART1_TXD
PB.6
O
12
13
UART1_nRTS
PB.7
O
I/O General purpose digital I/O pin.
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NUC029xDE
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
UART1_nCTS
LDO_CAP
VDD
I
Clear to Send input pin for UART1.
LDO output pin.
14
15
16
10
11
12
P
P
P
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
Ground pin for digital circuit.
VSS
PB.0
I/O General purpose digital I/O pin.
Data receiver input pin for UART0.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART0.
I/O General purpose digital I/O pin.
17
18
13
14
UART0_RXD
PB.1
I
UART0_TXD
PB.2
O
UART0_nRTS
TM2_EXT
TM2
O
I
Request to Send output pin for UART0.
Timer2 external capture input pin.
Timer2 toggle output pin.
19
15
O
I
PWM1_BRAKE1
PB.3
PWM1 brake input pin.
I/O General purpose digital I/O pin.
UART0_nCTS
TM3_EXT
I
I
Clear to Send input pin for UART0.
Timer3 external capture input pin.
Timer3 toggle output pin.
20
16
TM3
O
I
PWM1_BRAKE0
PD.6
PWM1 brake input pin.
21
22
17
18
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PD.7
PD.14
I/O General purpose digital I/O pin.
23
19
UART2_RXD
I
Data receiver input pin for UART2.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART2.
PD.15
24
25
26
27
20
21
22
23
UART2_TXD
PC.3
O
I/O General purpose digital I/O pin.
I/O SPI0 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O SPI0 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O SPI0 serial clock pin.
SPI0_MOSI0
PC.2
SPI0_MISO0
PC.1
SPI0_CLK
PC.0
I/O General purpose digital I/O pin.
28
24
SPI0_SS0
I/O SPI0 slave select pin.
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Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
PE.5
I/O General purpose digital I/O pin.
I/O PWM0 CH5 output/Capture input.
PWM0_CH5
TM1_EXT
TM1
29
I
Timer1 external capture input pin.
Timer1 toggle output pin.
O
PB.11
I/O General purpose digital I/O pin.
30
TM3
I/O Timer3 event counter input / toggle output.
I/O PWM0 CH4 output/Capture input.
I/O General purpose digital I/O pin.
PWM0_CH4
PB.10
31
32
33
34
35
36
37
38
39
40
41
42
TM2
I/O Timer2 event counter input / toggle output.
I/O General purpose digital I/O pin.
PB.9
TM1
I/O Timer1 event counter input / toggle output.
I/O General purpose digital I/O pin.
PC.11
PWM1_BRAKE1
PC.10
I
PWM1 brake input pin.
I/O General purpose digital I/O pin.
PWM1 brake input pin.
I/O General purpose digital I/O pin.
PWM0 brake input pin.
I/O General purpose digital I/O pin.
PWM0 brake input pin.
PWM1_BRAKE0
PC.9
I
PWM0_BRAKE1
PC.8
I
PWM0_BRAKE0
PA.15
I
I/O General purpose digital I/O pin.
I/O PWM0 CH3 output/Capture input.
I/O General purpose digital I/O pin.
I/O PWM0 CH2 output/Capture input.
I/O General purpose digital I/O pin.
I/O PWM0 CH1 output/Capture input.
I/O General purpose digital I/O pin.
I/O PWM0 CH0 output/Capture input.
I/O General purpose digital I/O pin.
I/O Serial wire debugger data pin.
I/O General purpose digital I/O pin.
25
26
27
28
29
30
PWM0_CH3
PA.14
PWM0_CH2
PA.13
PWM0_CH1
PA.12
PWM0_CH0
PF.7
ICE_DAT
PF.6
ICE_CLK
AVSS
I
Serial wire debugger clock pin.
43
44
31
32
AP Ground pin for analog circuit.
I/O General purpose digital I/O pin.
PA.0
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Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
ADC_CH0
PWM0_CH4
I2C1_SCL
PA.1
AI
ADC_CH0 analog input.
I/O PWM0 CH4 output/Capture input.
I/O I2C1 clock pin.
I/O General purpose digital I/O pin.
ADC_CH1
PWM0_CH5
I2C1_SDA
PA.2
AI
ADC_CH1 analog input.
45
46
47
33
34
35
I/O PWM0 CH5 output/Capture input.
I/O I2C1 data input/output pin.
I/O General purpose digital I/O pin.
ADC_CH2
PWM1_CH0
UART3_TXD
PA.3
AI
I/O PWM1 CH0 output/Capture input.
Data transmitter output pin for UART3.
I/O General purpose digital I/O pin.
AI
ADC_CH3 analog input.
I/O PWM1 CH1 output/Capture input.
Data receiver input pin for UART3.
I/O General purpose digital I/O pin.
AI
ADC_CH4 analog input.
I/O General purpose digital I/O pin.
ADC_CH2 analog input.
O
ADC_CH3
PWM1_CH1
UART3_RXD
PA.4
I
48
49
36
37
ADC_CH4
PA.5
ADC_CH5
UART3_RXD
PA.6
AI
I
ADC_CH5 analog input.
Data receiver input pin for UART3.
I/O General purpose digital I/O pin.
50
38
ADC_CH6
UART3_TXD
PA.7
AI
O
ADC_CH6 analog input.
Data transmitter output pin for UART3.
I/O General purpose digital I/O pin.
AI
ADC_CH7 analog input.
51
52
53
39
40
41
ADC_CH7
VREF
AP Voltage reference input for ADC.
AP Power supply for internal analog circuit.
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
AVDD
PC.7
I2C0_SCL
PWM0_BRAKE1
PC.6
I
PWM0 brake input pin.
I/O General purpose digital I/O pin.
I/O I2C0 data input/output pin.
54
42
I2C0_SDA
PWM0_BRAKE0
I
PWM0 brake input pin.
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Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
55
56
PC.15
PC.14
PB.15
INT1
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I
I
External interrupt1 input pin.
Timer0 external capture input pin.
Timer0 toggle output pin.
57
58
43
44
TM0_EXT
TM0
O
PF.0
I/O General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
I/O General purpose digital I/O pin.
XT1_OUT
PF.1
O
59
60
45
46
XT1_IN
I
I
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up. Set this pin low reset
chip to initial state.
nRESET
61
62
VSS
P
P
Ground pin for digital circuit.
VDD
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
PF.8
CLKO
PB.8
STADC
TM0
I/O General purpose digital I/O pin.
Frequency divider clock output pin.
I/O General purpose digital I/O pin.
ADC external trigger input.
I/O Timer0 event counter input / toggle output.
Frequency divider clock output pin.
63
47
48
O
I
64
CLKO
O
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
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5
BLOCK DIAGRAM
5.1 NuMicro® NUC029LDE/NUC029SDE Block Diagram
Memory
Timer/PWM
Analog Interface
32-bit Timer x 4
12-bit ADC
8 Channels
With VREF
LDROM
4 KB
APROM
68 KB
ARM
Cortex-M0
50 MHz
Watchdog
Timer X 2
16-bit PWM
12 Channels
SRAM
8 KB
DataFlash
Configurable
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
Connectivity
UART x 4
I/O Ports
General Purpose
I/O
LDO
VREF
1.8 V
High Speed
Oscillator
22.1184 MHz
High Speed
Crystal Osc.
4 ~ 24 MHz
Power On Reset
LVR
External Interrupt
SPI x 1
I2C x 2
Low Speed
Oscillator
10 kHz
PLL
Brownout
Detection
Figure 5-1 NuMicro® NUC029LDE/NUC029SDE Block Diagram
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6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
Cortex® -M0 Components
Cortex® -M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex® -M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
-
-
-
-
-
-
-
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
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(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset
Low Voltage Reset
Brown-out Detector Reset
CPU Reset
System Reset
System Reset and Power-on Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-on Reset is external crystal circuit and BS
(ISPCON[1]) bit. System Reset does not reset external crystal circuit and BS (ISPCON[1]) bit, but
Power-on Reset does.
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6.2.3 System Power Distribution
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
The outputs of internal voltage regulators, LDO, require an external capacitor which should be
located close to the corresponding pin. Analog power (AVDD) should be the same voltage level
with the digital power (VDD). Figure 6-2 shows the NuMicro® NUC029LDE/NUC029SDE power
distribution.
NUC029LDE/NUC029SDE Power Distribution
AVDD
AVSS
12-bit
SAR-ADC
Brown-out
Detector
Low Voltage
Reset
Internal
22.1184 MHz & 10 kHz
Oscillator
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
ULDO
PLL
LDO
IO cell
GPIO
Figure 6-2 NuMicro® NUC029LDE/NUC029SDE Power Distribution Diagram
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6.2.4 System Memory Map
The NuMicro® NUC029LDE/NUC029SDE provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register definition,
memory space, and programming detailed will be described in the following sections for each on-chip
peripheral. The NuMicro® NUC029LDE/NUC029SDE only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_0FFF
0x2000_0000 – 0x2000_3FFF
FLASH_BA
SRAM_BA
Flash Memory Space (68 KB)
SRAM Memory Space (8 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_C000 – 0x5000_FFFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
FMC_BA
Flash Memory Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4005_4000 – 0x4005_7FFF
0x400E_0000 – 0x400E_FFFF
WDT_BA
TMR01_BA
I2C0_BA
Watchdog Timer Control Registers
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0 with master/slave function Control Registers
PWM0 Control Registers
SPI0_BA
PWM0_BA
UART0_BA
UART3_BA
ADC_BA
UART0 Control Registers
UART3 Control Registers
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x4015_4000 – 0x4015_7FFF
TMR23_BA
I2C1_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
PWM1 Control Registers
PWM1_BA
UART1_BA
UART2_BA
UART1 Control Registers
UART2 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6-1 Address Space Assignments for On-Chip Controllers
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6.2.5 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is unknown on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.6 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.6.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro® NUC029LDE/NUC029SDE.
Software can set four levels of priority on some of these exceptions as well as on all interrupts.
The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”.
The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as
the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
3
-1
4 ~ 10
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
11
Reserved
12 ~ 13
PendSV
14
SysTick
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 6-2 Exception Model
Interrupt Number
Vector
Number
Source
Module
Interrupt Name
Interrupt Description
(Bit In Interrupt
Registers)
1 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
-
0
-
-
System exceptions
BOD_INT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
1
WDT
GPIO
GPIO
GPIO
GPIO
-
Watchdog Timer interrupt
External signal interrupt from PB.14 pin
External signal interrupt from PB.15 pin
External signal interrupt from PA[15:0]/PB[13:0]
External interrupt from PC[15:0]/PD[15:0]/PE[15:0]/PF[8:0]
Reserved
2
3
EINT1
4
GPAB_INT
GPCDEF_INT
-
5
6
7
-
-
Reserved
8
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
SPI0_INT
TMR0
TMR1
TMR2
TMR3
UART0/2
UART1
SPI0
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
Timer 2 interrupt
Timer 3 interrupt
UART0 and UART2 interrupt
UART1 interrupt
SPI0 interrupt
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31
32
33
34
35
36
37
38
39
40
41
42
43
15
16
17
18
19
20
21
22
23
24
25
26
27
UART3_INT
UART3
UART3 interrupt
Reserved
-
-
-
-
Reserved
I2C0_INT
I2C0
I2C0 interrupt
I2C1 interrupt
Reserved
I2C1_INT
I2C1
-
-
-
-
Reserved
PWM0_INT
PWM1_INT
-
PWM0
PWM1
-
PWM0 interrupt
PWM1 interrupt
Reserved
-
-
Reserved
BRAKE0_INT
BRAKE1_INT
PWM0
PWM1
PWM0 brake interrupt
PWM1 brake interrupt
Clock controller interrupt for chip wake-up from Power-
down state
44
28
PWRWU_INT
CLKC
45
46
47
29
30
31
ADC_INT
CKD_INT
-
ADC
CLKC
-
ADC interrupt
Clock detection interrupt
Reserved
Table 6-3 System Interrupt Map
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6.2.6.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 6-4 Vector Table Format
Vector Number
6.2.6.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.2.7 System Control
The Cortex® -M0 status and operating mode control are managed by System Control Registers.
Including CPUID, Cortex® -M0 interrupt priority and Cortex® -M0 power management can be
controlled through these system control registers.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave
Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the
overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
The clock generator consists of 5 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency(PLL FOUT),PLL source can be from
external 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz
internal high speed RC oscillator (HIRC))
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
XTL12M_EN (PWRCON[0])
HXT
XT1_OUT
XT1_IN
4~24 MHz
HXT
PLL_SRC (PLLCON[19])
PLL
0
1
PLL FOUT
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN (PWRCON[3])
10 kHz
LIRC
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6-3 Clock Generator Block Diagram
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22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
ISP
4~24
MHz
PLLFOUT
Reserved
4~24 MHz
1/(HCLK_N+1)
10 kHz
PCLK
I2C 0~1
CAN 0
22.1184 MHz
10 kHz
111
101
011
010
001
000
CLKSEL0[2:0]
TMR 3
TMR 2
TMR 1
TMR 0
External trigger
HCLK
22.1184 MHz
4~24 MHz
1
PLLFOUT
Reserved
4~24 MHz
0
PLLCON[19]
22.1184 MHz
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
FMC
CPUCLK
22.1184 MHz
HCLK
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
SYST_CSR[2]
4~24 MHz
Reserved
4~24 MHz
PWM 0
PWM 1
PCLK
1
PLLFOUT
0
CLKSEL0[5:3]
CLKSEL3[16]
CLKSEL3[17]
CLKSEL2[17:16]
10 kHz
11
10
WWDT
WDT
HCLK
1/2048
10 kHz
11
10
HCLK
1/2048
CLKSEL1[1:0]
22.1184 MHz
11
01
00
PLLFOUT
4~24 MHz
HCLK
1
0
SPI 0
PLLFOUT
CLKSEL1[25:24]
CLKSEL1[4]
1/(UART_N+1)
1/(ADC_N+1)
UART 0~3
22.1184 MHz
HCLK
11
10
01
00
ADC
BOD
PLLFOUT
4~24 MHz
22.1184 MHz
HCLK
10 kHz
11
10
01
00
FDIV
Reserved
4~24 MHz
CLKSEL1[3:2]
CLKSEL2[3:2]
Figure 6-4 Clock Generator Global View Diagram
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6.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-5.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011
010
001
000
CPUCLK
HCLK
CPU
AHB
APB
PLLFOUT
Reserved
4~24 MHz
1/(HCLK_N+1)
PCLK
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
Figure 6-5 System Clock Block Diagram
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-6.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
Reserved
4~24 MHz
Figure 6-6 SysTick Clock Control Block Diagram
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6.3.3 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
-
10 kHz internal low speed RC oscillator (LIRC) clock
WDT/Timer Peripherals Clock (when 10 kHz intertnal low speed RC oscillator (LIRC)
is adopted as clock source)
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6.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN (APBCLK[6])
22.1184 MHz
11
FRQDIV_CLK
HCLK
10
01
00
Reserved
4~24 MHz
Figure 6-7 Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FSEL
(FRQDIV[3:0])
16 chained
divide-by-2 counter
FRQDIV_CLK
DIVIDER1
(FRQDIV[5])
1/2
1/22 1/23
…... 1/215 1/216
0000
0001
16 to 1
MUX
:
:
CLKO
0
1
1110
1111
Figure 6-8 Frequency Divider Block Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NuMicro® NUC029LDE/NUC029SDE has 68 Kbytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-System-
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex® -M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in CONFIG0. By the way, the NuMicro® NUC029LDE/NUC029SDE also
provides additional Data Flash for user to store some application dependent data.
The NuMicro® NUC029LDE/NUC029SDE supports another flexible feature: configurable Data
Flash size. The Data Flash size is decided by Data Flash variable size enable (DFVSEN), Data
Flash enable (DFEN) in Config0 and Data Flash base address (DFBADR) in Config1. When
DFVSEN is set to 1, the Data Flash size is fixed at 4K and the address is started from
0x0001_f000, and the APROM size is become 64K. When DFVSEN is set to 0 and DFEN is set to
1, the Data Flash size is zero and the APROM size is 68 Kbytes. When DFVSEN is set to 0 and
DFEN is set to 0, the APROM and Data Flash share 68 Kbytes continuous address and the start
address of Data Flash is defined by (DFBADR) in Config1.
6.4.2 Features
Runs up to 50 MHz with zero wait cycle for continuous address read access
All embedded Flash memory supports 512 bytes page erase
68 KB application program memory (APROM)
4KB In-System-Programming (ISP) loader program memory (LDROM)
Configurable Data Flash size
512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The NuMicro® NUC029LDE/NUC029SDE series has up to 56 General Purpose I/O pins to be
shared with other function pins depending on the chip configuration. These 56 pins are arranged
in 6 ports named as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B port has
the maximum of 16 pins. The GPIOC port has the maximum of 12 pins. The GPIOD port has the
maximum of 4 pins. The GPIOE port has the maximum of 1 pin. The GPIOF port has the
maximum of 7 pins. Each of the 56 pins is independent and has the corresponding register bits to
control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K for VDD from 5.0 V to 2.5 V.
6.5.2 Features
Four I/O modes:
Quasi-bidirectional
-
-
-
-
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
-
-
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function
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6.7 Timer Controller (TIMER)
6.7.1 Overview
The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.7.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external counter pin
(TM0~TM3)
Supports external pin capture (TM0_EXT~TM3_EXT) for interval measurement
Supports external pin capture (TM0_EXT~TM3_EXT) for reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
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6.8 PWM Generator and Capture Timer (PWM)
6.8.1 Overview
The NUC029LDE/NUC029SDE provides two PWM generators － PWM0 and PWM1. Each PWM
supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up,
down and up-down counter types. PWM uses the comparator compared with counter to generate
events. These events are used to generate PWM pulse, interrupt and trigger signal for ADC to
start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, which have difference architecture. In Complementary mode, there are
two comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM
output control unit, it supports polarity output, independent pin mask, tri-state output enable and
brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.8.2 Features
6.8.2.1 PWM function features
Supports maximum clock frequency up to100 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter, each module provides 3 PWM counters
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out
detection and CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
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6.8.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.9 Watchdog Timer (WDT)
6.9.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.9.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period
is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer reset delay period
-
Selectable it includes (1026、130、18 or 3) * WDT_CLK reset delay period.
Supports to force Watchdog Timer enabled after chip powered on or reset while
CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
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6.10 Window Watchdog Timer (WWDT)
6.10.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period
to prevent software run to uncontrollable status by any unpredictable condition.
6.10.2 Features
6-bit down counter value (WWDTVAL[5:0]) and 6-bit compare window value
(WWDTCR[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of
WWDT counter
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6.11 UART Interface Controller (UART)
6.11.1 Overview
The NuMicro® NUC029LDE/NUC029SDE provides up to four channels of Universal
Asynchronous Receiver/Transmitters (UART). UART0/UART1/UART2 supports 16 bytes entry
FIFO and UART3 support 1 byte buffer for data payload. Besides, only UART0 and UART1
support the flow control function. The UART Controller performs a serial-to-parallel conversion on
data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the
CPU. The UART controller also supports IrDA SIR Function. UART0/UART1 provides RS-485
function mode. UART0/UART1/UART2 provides LIN master/slave function.
6.11.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 16/16 bytes (UART0/UART1/UART2 support) entry FIFO
and 1/1 bytes buffer for data payloads (UART3 support)
Supports hardware auto-flow control function (CTS, RTS) and programmable RTS
flow control trigger level (UART0/UART1 support).
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function (UART0/UART1 support)
Supports 7-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UA_TOR [15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow
detect function
Fully programmable serial-interface characteristics
-
-
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
-
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3/16-bit duration for normal mode
LIN function mode (UART0/UART1/UART2 support)
-
-
-
-
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode. (UART0/UART1 support)
-
-
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by RTS pin.
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6.12 I2C Serial Interface Controller (I2C)
6.12.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
6.12.2 Features
The I2C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices
connected to the bus. The main features of the I2C bus include:
Supports up to two I2C serial interface controller
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
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6.13 Serial Peripheral Interface (SPI)
6.13.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® NUC029LDE/NUC029SDE contains one set of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. This SPI controller can be
configured as a master or a slave device.
The SPI controller supports the variable bus clock function for special applications.
6.13.2 Features
One set of SPI controller
Supports Master or Slave mode operation
Supports Dual I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32 bits
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the Byte Reorder function
Supports Byte or Word Suspend mode
Variable output bus clock frequency in Master mode
Supports 3-wire, no slave select signal, bi-direction interface
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6.14 Analog-to-Digital Converter (ADC)
6.14.1 Overview
The NuMicro® NUC029LDE/NUC029SDE contains one 12-bit successive approximation analog-
to-digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM trigger and external STADC pin.
6.14.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 8 single-end analog input channels or 4 differential analog input channels
Up to 1000 kSPS conversion rate (chip working at 5V)
Three operating modes
-
-
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
-
Continuous scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion
An A/D conversion can be started by:
-
-
-
Writing 1 to ADST bit (ADCR[11])through software
PWM trigger
External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators
Supports two set digital comparators. The conversion result can be compared with
specify value and user can select whether to generate an interrupt when conversion
result matches the compare register setting
Channel 7 supports 2 input sources: external analog voltage, and internal Band-gap
voltage
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Symbol
Parameter
VDDVSS
VIN
Min.
-0.3
VSS-0.3
4
Max.
+7.0
VDD+0.3
24
Unit
V
DC Power Supply
Input Voltage
V
Oscillator Frequency
1/tCLCL
TA
MHz
C
Operating Temperature
-40
+105
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
mA
mA
mA
mA
mA
mA
120
35
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
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7.2 DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
Specification
Parameter
Operation Voltage
Power Ground
Sym.
Test Conditions
Min.
Typ.
Max. Unit
VDD
2.5
5.5
0.3
V
V
V
VDD = 2.5V ~ 5.5V up to 50 MHz
VSS
-0.3
0
AVSS
LDO Output Voltage
Band-gap Voltage
VLDO
1.62
1.8
1.98
VDD ≥ 2.5V
1.20
1.20
V
V
VDD = 2.5 V ~ 5.5 V, TA = 25C
VBG
1.19
1.22
VDD = 2.5 V ~ 5.5 V, TA = -40C~105C
Analog Operating
Voltage
When system used analog function, please refer to TRM
chapter 6.5 for corresponding analog operating voltage
AVDD
VDD
V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
at 50 MHz
IDD1
26
mA
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
V
V
V
V
V
V
V
X
X
X
V
X
V
X
V
X
V
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
12
24
11
10
4.1
10
mA
mA
mA
mA
mA
mA
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
while(1){} executed
from flash
VLDO =1.8 V
Operating Current
Normal Run Mode
at 22.1184 MHz
-
-
-
-
-
-
X
X
while(1){} executed
from flash
IDD8
-
4.1
-
mA
3.3V
VLDO =1.8 V
X
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
X
V
X
V
X
Operating Current
Normal Run Mode
at 12 MHz
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
8.3
4.3
6.8
2.8
3.9
2.6
2.6
1.3
mA
mA
mA
mA
mA
mA
mA
mA
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
4 MHz
4 MHz
4 MHz
while(1){} executed
from flash
VLDO =1.8 V
Operating Current
Normal Run Mode
at 4 MHz
while(1){} executed
from flash
VLDO =1.8 V
All digital
module
Operating Current
Normal Run Mode
at 10 kHz
VDD
HXT/LXT LIRC (kHz)
10
PLL
X
IDD21
111
A
5.5V
X
V
Dec 18, 2018
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Specification
Parameter
Sym.
Test Conditions
Min.
Typ.
108
98
Max. Unit
while(1){} executed
from flash
IDD22
IDD23
IDD24
5.5V
3.3V
3.3V
A
A
A
X
X
X
10
10
10
X
X
X
X
V
X
VLDO =1.8 V
96
All digital
module
VDD
HXT
HIRC
PLL
IIDLE1
21
mA
Operating Current
Idle Mode
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
V
V
V
V
X
X
V
V
V
V
X
X
X
X
X
X
V
X
V
X
X
X
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
at 50 MHz
VLDO =1.8 V
20
6.7
7.7
2.1
7.7
2.1
7.3
3.2
-
-
-
-
-
-
-
-
Operating Current
Idle Mode
X
at 22.1184 MHz
VLDO =1.8 V
X
X
12 MHz
12 MHz
Operating Current
Idle Mode
at 12 MHz
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
IIDLE16
5.8
1.7
mA
mA
3.3V
3.3V
12 MHz
X
X
V
VLDO =1.8 V
12 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
V
X
3.6
2.2
mA
mA
5.5V
5.5V
Operating Current
Idle Mode
at 4 MHz
2.3
mA
mA
3.3V
3.3V
4 MHz
4 MHz
X
X
X
X
V
X
VLDO =1.8 V
0.96
All digital
module
VDD
HXT/LXT LIRC (kHz)
PLL
X
IIDLE21
110
A
5.5V
5.5V
X
X
X
X
10
10
10
10
V
X
V
X
Operating Current
Idle Mode
IIDLE22
IIDLE23
IIDLE24
107
97
A
A
A
X
at 10 kHz
3.3V
3.3V
X
95
X
HXT/HIRC
PLL
RAM
retension
VDD
LXT (kHz)
RTC
IPWD1
15
A
Standby Current
Power-down Mode
(Deep Sleep Mode)
VLDO =1.6 V
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
V
V
V
V
V
V
IPWD2
IPWD3
IPWD4
15
17
17
A
A
A
X
32.768
32.768
Dec 18, 2018
Page 51 of 70
Rev 1.01
NUC029xDE
Specification
Parameter
Sym.
Test Conditions
Min.
Typ.
10
Max. Unit
IPWD5
IPWD6
5.5V
3.3V
A
A
X
X
X
X
X
X
X
X
9
Input Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
mode)
IIN1
-67
-
-75
+1
VDD = 5.5V, VIN = 0V or VIN=VDD
A
A
A
V
Input Leakage
Current PA, PB, PC,
PD, PE, PF
VDD = 5.5V, 0<VIN<VDD
ILK
-1
Open-drain or input only mode.
Logic 1 to 0
Transition Current
PA~PF (Quasi-
bidirectional mode)
[3]
ITL
-610
-650
VDD = 5.5V, VIN=2.0V
Input Low Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
-0.3
-0.3
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
VIL1
VIH1
VIL3
VIH3
VDD
+0.2
2.0
1.5
-
-
VDD = 5.5V
VDD =3.0V
Input High Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
V
VDD
+0.2
0
0
-
-
0.8
0.4
VDD = 4.5V
VDD = 3.0V
Input Low Voltage
XT1_IN[*2]
V
V
VDD
+0.3
3.5
2.4
-
-
VDD = 5.5V
VDD = 3.0V
Input High Voltage
XT1_IN[*2]
VDD
+0.3
Negative going
threshold
VILS
-0.3
-
-
0.2VDD
V
V
(Schmitt input),
nRESET
Positive going
threshold
VDD
+0.3
VIHS
0.7 VDD
(Schmitt input),
nRESET
Internal nRESET pin
pull up resistor
RRST
40
150
kΩ
Negative going
threshold
0.3
VDD
VILS
-0.3
-
-
V
(Schmitt input),
Positive going
threshold
VDD
+0.3
VIHS
0.7 VDD
V
(Schmitt input),
ISR11
ISR12
ISR12
-300
-50
-400
-80
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
A
A
A
Source Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
Mode)
-40
-73
Dec 18, 2018
Page 52 of 70
Rev 1.01
NUC029xDE
Specification
Parameter
Sym.
Test Conditions
Min.
-20
-3
Typ.
-26
Max. Unit
ISR21
ISR22
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
mA VDD = 2.5V, VS = 2.0V
Source Current PA,
PB, PC, PD, PE, PF
(Push-pull Mode)
-5.2
ISR22
ISK1
ISK1
ISK1
-2.5
10
6
-5
17
11
10
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
mA VDD = 2.5V, VS = 0.45V
Sink Current PA, PB,
PC, PD, PE, PF
(Quasi-bidirectional
and Push-pull Mode)
5
Note:
1. nRESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
Dec 18, 2018
Page 53 of 70
Rev 1.01
NUC029xDE
7.3 AC Electrical Characteristics
7.3.1 External 4~24 MHz High Speed Oscillator
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Condition
Min.
Typ.
Max.
Unit
nS
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
10
10
2
-
-
-
-
-
tCLCX
-
nS
tCLCH
15
15
nS
tCHCL
2
nS
7.3.2 External 4~24 MHz High Speed Crystal
Symbol
VHXT
Parameter
Operation Voltage VDD
Temperature
Condition
Min.
2.5
-40
-
Typ.
Max.
5.5
105
-
Unit
V
-
-
-
-
TA
℃
12 MHz at VDD = 5V
12 MHz at VDD = 3V
External crystal
2
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
0.8
fHXT
4
24
7.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4 MHz ~ 24 MHz
10~20pF
10~20pF
without
XT1_OUT
XT1_IN
R
C1
C2
Dec 18, 2018
Page 54 of 70
Rev 1.01
NUC029xDE
Figure 7-1 Typical Crystal Application Circuit
7.3.3 Internal 22.1184 MHz High Speed Oscillator
Symbol
VHRC
Parameter
Operation Voltage VDD
Condition
Min.
2.5
-
Typ.
Max.
5.5
-
Unit
V
-
-
Center Frequency
-
22.1184
-
MHz
%
+25℃; VDD =5 V
-1
+1
fHRC
Calibrated Internal Oscillator Frequency
Operation Current
-40℃~+105℃;
-2
-
-
+2
-
%
VDD=2.5 V~5.5 V
IHRC
VDD =5 V
744
uA
HIRC oscillator accuracy vs. temperature
0.40
0.20
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
-1.20
-1.40
-1.60
-1.80
Min
Max
-40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100110
Temperature(℃)
Figure 7-2 HIRC Accuracy vs. Temperature
7.3.4 Internal 10 kHz Low Speed Oscillator
Symbol
parameter
Operation Voltage VDD
Center Frequency
Condition
Min.
2.5
-
Typ.
-
Max.
Unit
V
VLRC
fLRC
-
-
5.5
-
10
kHz
Dec 18, 2018
Page 55 of 70
Rev 1.01
NUC029xDE
+25℃; VDD =5 V
-10
-50
-
-
+10
+50
%
%
Calibrated Internal
Oscillator Frequency
-
-40℃~+105℃;
VDD=2.5 V~5.5 V
Dec 18, 2018
Page 56 of 70
Rev 1.01
NUC029xDE
7.4 Analog Characteristics
7.4.1 12-bit SARADC Specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
Bit
-
Resolution
-
-
-
-
-
-
-
12
DNL
INL
EO
Differential nonlinearity error
Integral nonlinearity error
Offset error
-1~2
-1~4
LSB
LSB
LSB
-
±2
±4
-
3
EG
Gain error (Transfer gain)
Absolute Error
-3
-
EA
4
-
LSB
-
Monotonic
Guaranteed
FADC
FS
ADC clock frequency (AVDD = 4.5V~5.5V)
-
-
-
-
21
MHz
kSPS
1/FADC
1/FADC
Sample rate (FADC/TCONV
)
1000
TACQ
TCONV
Acquisition Time (Sample Stage)
Total Conversion Time
2~9
16~23
VDDA
Supplt Current
3
0
-
5.5
V
IDDA
VIN
CIN
RIN
Supply current (Avg.)
Input voltage
2.9
-
mA
V
AVDD
Input Capacitance
Input Load
6
pF
kΩ
6.5
Dec 18, 2018
Page 57 of 70
Rev 1.01
NUC029xDE
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
7.4.2 LDO and Power Management Specification
Symbol
Parameter
Input Voltage VDD
Output Voltage
Min.
2.5
Typ.
Max.
5.5
Unit
V
Note
VDD
VDD input voltage
VDD > 2.5 V
VLDO
1.62
-40
1.8
25
1.98
105
V
℃
TA
Operating Temperature
Note:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of the
device..
Dec 18, 2018
Page 58 of 70
Rev 1.01
NUC029xDE
7.4.3 Low Voltage Reset Specification
Symbol
Parameter
Operation Voltage
Quiescent Current
Operation Temperature
Condition
-
Min.
0
Typ.
-
Max.
5.5
Unit
V
AVDD
TA
AVDD=5.5 V
-
-
1
5
A
℃
ILVR
-40
2.00
1.95
2.04
25
105
2.4
TA = 25 ℃
TA = -40 ℃
TA = 105 ℃
2.0
1.98
2.13
V
V
V
VLVR
Threshold Voltage
2.02
2.25
7.4.4 Brown-out Detector Specification
Symbol
Parameter
Operation Voltage
Temperature
Condition
-
Min.
0
Typ.
-
Max.
5.5
Unit
V
AVDD
TA
℃
μA
V
-
-40
25
105
140
4.56
3.84
2.8
IBOD
Quiescent Current
AVDD=5.5 V
-
-
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
4.45
3.74
2.73
2.22
4.34
3.65
2.66
2.16
4.53
3.8
Brown-out Voltage
(Falling edge)
V
VBOD
2.77
2.25
4.39
3.69
2.69
2.19
V
2.28
4.41
3.71
2.7
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
V
2.2
V
7.4.5 Power-on Reset Specification
Symbol
Parameter
Operation Temperature
Reset Voltage
Condition
Min.
-40
Typ.
25
Max.
105
2.4
Unit
℃
TA
-
VPOR
V+
1.6
2
V
VDD Start Voltage to
Ensure Power-on Reset
VPOR
-
-
-
-
-
100
-
mV
VDD Raising Rate to
Ensure Power-on Reset
RRVDD
0.025
V/ms
Minimum Time for VDD
Stays at VPOR to
tPOR
-
0.5
-
-
ms
Ensure Power-on Reset
Dec 18, 2018
Page 59 of 70
Rev 1.01
NUC029xDE
VDD
tPOR
RRVDD
VPOR
Time
Figure 7-3 Power-up Ramp Condition
Dec 18, 2018
Page 60 of 70
Rev 1.01
NUC029xDE
7.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Conditions
Min.
1.62
20000
100
20
Typ.
Max.
Unit
V[2]
[2]
1.8
1.98
VFLA
NENDUR
TRET
Endurance
-
-
-
-
-
-
-
-
-
-
cycles[1]
year
ms
At 25℃
Data Retention
Page Erase Time
Mass Erase Time
Program Time
TERASE
TMER
40
ms
TPROG
Note:
40
μs
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
Dec 18, 2018
Page 61 of 70
Rev 1.01
NUC029xDE
7.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
max.
Min.
max.
tLOW
SCL low period
SCL high period
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4
-
-
0.6
-
-
4
4.7[3]
250
0[4]
-
0.6
-
1.2[3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
-
-
-
Cb
Capacitive load for each bus line
-
Note:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8 MHz to
achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of
the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL
signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 7-4 I2C Timing Diagram
Dec 18, 2018
Page 62 of 70
Rev 1.01
NUC029xDE
7.7 SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI Master Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
1
2
SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
2
4
SPI Slave Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
3.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
16
22
SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
18
24
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 7-5 SPI Master Mode Timing Diagram
Dec 18, 2018
Page 63 of 70
Rev 1.01
NUC029xDE
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 7-6 SPI Slave Mode Timing Diagram
Dec 18, 2018
Page 64 of 70
Rev 1.01
NUC029xDE
7.8 I2S Dynamic Characteristics
Symbol
tw(CKH)
tw(CKL)
tv(WS)
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min
42
37
7
Max
Unit
Test Conditions
-
-
-
-
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
Master mode
Master mode
Slave mode
Slave mode
ns
th(WS)
WS hold time
1
tsu(WS)
th(WS)
WS setup time
WS hold time
34
0
I2S slave input clock
duty cycle
DuCy(SCK)
25
75
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
0
0
0
0
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
32
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
16
-
5
-
0
CPOL = 0
tw(CKH)
CPOL = 1
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 7-7 I2S Master Mode Timing Diagram
Dec 18, 2018
Page 65 of 70
Rev 1.01
NUC029xDE
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 7-8 I2S Slave Mode Timing Diagram
Dec 18, 2018
Page 66 of 70
Rev 1.01
NUC029xDE
8
APPLICATION CIRCUIT
AVCC
AVDD
DVCC
[1]
FB
DVCC
VDD
Power
SPISS0
SPICLK0
MISO_0
CS
CLK
MISO
MOSI
VDD
0.1uF
0.1uF
SPI Device
VSS
VSS
MOSI_0
FB
AVSS
DVCC
4.7K
DVCC
DVCC
4.7K
100K
100K
CLK
DIO
VDD
SCL
SDA
VDD
NUC029LDE /
NUC029SDE
I2C Device
ICE_CLK
ICE_DAT
nRST
VSS
SWD
Interface
VSS
20p
XT1_IN
PC COM Port
Crystal
4~24 MHz
crystal
20p
RS232 Transceiver
ROUT RIN
XT1_OUT
RXD
TXD
TIN
TOUT
UART
DVCC
10K
Reset
Circuit
LDO_CAP
nRESET
1uF
LDO
10uF/25V
Note: For the SPI device, the chip supply voltage
must be equal to SPI device working voltage. For
example, when the SPI Flash working voltage is
3.3 V, the chip supply voltage must also be 3.3V.
Dec 18, 2018
Page 67 of 70
Rev 1.01
NUC029xDE
9
PACKAGE DIMENSIONS
9.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Dec 18, 2018
Page 68 of 70
Rev 1.01
NUC029xDE
9.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Dec 18, 2018
Page 69 of 70
Rev 1.01
NUC029xDE
10 REVISION HISTORY
Date
Revision
Description
2018.06.19
1.00
Initial version.
1. Added the part number NUC029KGE in section 4.1 and section 4.2.
2018.12.18
1.01
2. Modified the application circuit - ICE added pull up resistor in chapter 8.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Dec 18, 2018
Page 70 of 70
Rev 1.01
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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