NUC125-SC2E [NUVOTON]
ARM Cortex® -M0 32-bit Microcontroller;
| 型号： | NUC125-SC2E |
| 厂家： | 
NUVOTON |
| 描述： | ARM Cortex® -M0 32-bit Microcontroller 微控制器 |
| 文件： | 总148页 (文件大小：2999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC121/125
ARM Cortex® -M0
32-bit Microcontroller
NuMicro® Family
NUC121/125 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Aug. 17, 2018
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TABLE OF CONTENTS
1
2
3
4
GENERAL DESCRIPTION.......................................................................9
Key Features Support Table ......................................................................... 9
FEATURES .......................................................................................10
NuMicro® NUC121/125 Features...................................................................10
Abbreviations....................................................................................16
Abbreviations ..........................................................................................16
PARTS INFORMATION LIST AND PIN CONFIGURATION .............................18
NuMicro® NUC121/125 Selection Guide..........................................................18
1.1
2.1
3.1
4.1
4.1.1
4.1.2
4.1.3
NuMicro® NUC121/125 Naming Rule .....................................................................18
NuMicro® NUC121 USB Series Selection Guide ........................................................19
NuMicro® NUC125 USB Series Selection Guide ........................................................19
Pin Configuration......................................................................................20
NuMicro® NUC121 QFN 33-Pin Diagram .................................................................20
NuMicro® NUC121 QFN 33-Pin Function Diagram......................................................21
NuMicro® NUC121 LQFP 48-Pin Diagram................................................................22
NuMicro® NUC121 LQFP 48-Pin Function Diagram ....................................................23
NuMicro® NUC121 LQFP 64-Pin Diagram................................................................24
NuMicro® NUC121 LQFP 64-Pin Function Diagram ....................................................25
NuMicro® NUC125 QFN 33-Pin Diagram .................................................................26
NuMicro® NUC125 QFN 33-Pin Function Diagram......................................................27
NuMicro® NUC125 LQFP 48-Pin Diagram................................................................28
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.2.10 NuMicro® NUC125 LQFP 48-Pin Function Diagram ....................................................29
4.2.11 NuMicro® NUC125 LQFP 64-Pin Diagram................................................................30
4.2.12 NuMicro® NUC125 LQFP 64-Pin Function Diagram ....................................................31
4.3
Pin Description ........................................................................................32
NUC121 USB Series QFN33 Pin Description............................................................32
NUC121 USB Series LQFP48 Pin Description ..........................................................37
NUC121 USB Series LQFP64 Pin Description ..........................................................44
NUC125 USB Series QFN33 Pin Description............................................................52
NUC125 USB Series LQFP48 Pin Description ..........................................................57
NUC125 USB Series LQFP64 Pin Description ..........................................................64
GPIO Multi-function Pin Summary .........................................................................72
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
5
BLOCK DIAGRAM ..............................................................................78
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5.1
NuMicro® NUC121/125 Block Diagram............................................................78
FUNCTIONAL DESCRIPTION ................................................................79
ARM® Cortex® -M0 Core..............................................................................79
System Manager......................................................................................81
6
6.1
6.2
6.2.1
6.2.2
Overview .......................................................................................................81
System Reset .................................................................................................81
Power Modes and Wake-up Sources......................................................................88
System Power Distribution ..................................................................................90
Clock Controller .......................................................................................92
Overview .......................................................................................................92
Clock Generator...............................................................................................94
System Clock and SysTick Clock ..........................................................................96
Peripherals Clock .............................................................................................98
Power-down Mode Clock....................................................................................98
Clock Output...................................................................................................98
Flash Memory Controller (FMC)..................................................................100
Overview ..................................................................................................... 100
Features...................................................................................................... 100
General Purpose I/O (GPIO)......................................................................101
Overview ..................................................................................................... 101
Features...................................................................................................... 101
PDMA Controller (PDMA) .........................................................................102
Overview ..................................................................................................... 102
Features...................................................................................................... 102
Timer Controller (TMR) ............................................................................103
Overview ..................................................................................................... 103
Features...................................................................................................... 103
Basic PWM Generator and Capture Timer (BPWM) ..........................................104
Overview ..................................................................................................... 104
Features...................................................................................................... 104
PWM Generator and Capture Timer (PWM) ...................................................105
Overview ..................................................................................................... 105
Features...................................................................................................... 105
Watchdog Timer (WDT) ...........................................................................107
6.2.3
6.2.4
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
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6.10.1 Overview ..................................................................................................... 107
6.10.2 Features...................................................................................................... 107
6.11
Window Watchdog Timer (WWDT) ..............................................................108
6.11.1 Overview ..................................................................................................... 108
6.11.2 Features...................................................................................................... 108
6.12
USCI - Universal Serial Control Interface Controller ..........................................109
6.12.1 Overview ..................................................................................................... 109
6.12.2 Features...................................................................................................... 109
6.13
USCI - UART Mode ................................................................................110
6.13.1 Overview ..................................................................................................... 110
6.13.2 Features...................................................................................................... 110
6.14
USCI - SPI Mode....................................................................................111
6.14.1 Overview ..................................................................................................... 111
6.14.2 Features...................................................................................................... 111
6.15
USCI - I2C Mode ....................................................................................113
6.15.1 Overview ..................................................................................................... 113
6.15.2 Features...................................................................................................... 113
6.16
UART Interface Controller (UART)...............................................................114
6.16.1 Overview ..................................................................................................... 114
6.16.2 Features...................................................................................................... 114
6.17
I2C Serial Interface Controller (I2C) ..............................................................115
6.17.1 Overview ..................................................................................................... 115
6.17.2 Features...................................................................................................... 115
6.18
Serial Peripheral Interface (SPI)..................................................................116
6.18.1 Overview ..................................................................................................... 116
6.18.2 Features...................................................................................................... 116
6.19
USB Device Controller (USBD)...................................................................117
6.19.1 Overview ..................................................................................................... 117
6.19.2 Features...................................................................................................... 117
6.20
Analog-to-Digital Converter (ADC)...............................................................118
6.20.1 Overview ..................................................................................................... 118
6.20.2 Features...................................................................................................... 118
7
8
APPLICATION CIRCUIT .....................................................................119
ELECTRICAL CHARACTERISTICS .......................................................121
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8.1
8.2
8.3
Absolute Maximum Ratings .......................................................................121
DC Electrical Characteristics......................................................................122
AC Electrical Characteristics......................................................................130
External 4~24 MHz High Speed Crystal (HXT) Input Clock.......................................... 130
External 4~24 MHz High Speed Crystal (HXT) Oscillator............................................ 130
External 32.768 kHz Low Speed Crystal (LXT) Input Clock ......................................... 131
External 32.768 kHz Low Speed Crystal (LXT) Oscillator............................................ 131
Analog Characteristics .............................................................................134
12-bit ADC ................................................................................................... 134
LDO ........................................................................................................... 136
Low-Voltage Reset ......................................................................................... 136
Brown-out Detector......................................................................................... 136
Power-on Reset............................................................................................. 137
Temperature Sensor ....................................................................................... 138
USB PHY..................................................................................................... 139
Flash DC Electrical Characteris ..................................................................140
I2C Dynamic Characteristics ......................................................................141
SPI Dynamic Characteristics......................................................................142
Dynamic Characteristics of Data Input and Output Pin............................................... 142
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.5
8.6
8.7
8.7.1
9
PACKAGE DIMENSIONS....................................................................144
LQFP 64S (7x7x1.4 mm) ..........................................................................144
LQFP 48L (7x7x1.4 mm) ..........................................................................145
QFN 33Z (5x5x0.8 mm)............................................................................146
9.1
9.2
9.3
10 REVISION HISTORY..........................................................................147
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List of Figures
Figure 4.1-1 NuMicro® NUC121/125 Selection Code .................................................................... 18
Figure 4.2-1 NuMicro® NUC121 QFN 33-Pin Diagram.................................................................. 20
Figure 4.2-2 NuMicro® NUC121 QFN 33-Pin Function Diagram ................................................... 21
Figure 4.2-3 NuMicro® NUC121 LQFP 48-Pin Diagram ................................................................ 22
Figure 4.2-4 NuMicro® NUC121 LQFP 48-Pin Function Diagram ................................................. 23
Figure 4.2-5 NuMicro® NUC121 LQFP 64-Pin Diagram ................................................................ 24
Figure 4.2-6 NuMicro® NUC121 LQFP 64-Pin Function Diagram ................................................. 25
Figure 4.2-7 NuMicro® NUC125 QFN 33-Pin Diagram.................................................................. 26
Figure 4.2-8 NuMicro® NUC125 QFN 33-Pin Function Diagram ................................................... 27
Figure 4.2-9 NuMicro® NUC125 LQFP 48-Pin Diagram ................................................................ 28
Figure 4.2-10 NuMicro® NUC125 LQFP 48-Pin Function Diagram ............................................... 29
Figure 4.2-11 NuMicro® NUC125 LQFP 64-Pin Diagram .............................................................. 30
Figure 4.2-12 NuMicro® NUC125 LQFP 64-Pin Function Diagram ............................................... 31
Figure 5.1-1 NuMicro® NUC121/125 Block Diagram ..................................................................... 78
Figure 6.1-1 Cortex® -M0 Block Diagram........................................................................................ 79
Figure 6.2-1 System Reset Sources .............................................................................................. 82
Figure 6.2-2 nRESET Reset Waveform......................................................................................... 85
Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 85
Figure 6.2-4 Low Voltage Reset (LVR) Waveform......................................................................... 86
Figure 6.2-5 Brown-out Detector (BOD) Waveform....................................................................... 87
Figure 6.2-6 Power Mode State Machine ...................................................................................... 88
Figure 6.2-7 NuMicro® NUC121/125 Power Distribution Diagram................................................. 91
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 93
Figure 6.3-2 Clock Generator Block Diagram................................................................................ 95
Figure 6.3-3 System Clock Block Diagram .................................................................................... 96
Figure 6.3-4 HXT Stop Protect Procedure..................................................................................... 97
Figure 6.3-5 SysTick Clock Control Block Diagram....................................................................... 98
Figure 6.3-6 Clock Source of Clock Output ................................................................................... 99
Figure 6.3-7 Clock Output Block Diagram ..................................................................................... 99
Figure 6.14-1 SPI Master Mode Application Block Diagram........................................................ 111
Figure 6.14-2 SPI Slave Mode Application Block Diagram.......................................................... 111
Figure 6.15-1 I2C Bus Timing....................................................................................................... 113
Figure 8.3-1 Typical Crystal Application Circuit ........................................................................... 131
Figure 8.3-2 Typical Crystal Application Circuit ........................................................................... 132
Figure 8.4-1 Power-up Ramp Condition ...................................................................................... 137
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Figure 8.6-1 I2C Timing Diagram ................................................................................................. 141
Figure 8.7-1 SPI Master Mode Timing Diagram .......................................................................... 142
Figure 8.7-2 SPI Slave Mode Timing Diagram ............................................................................ 143
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List of Tables
Table 1.1-1 Key Features Support Table......................................................................................... 9
Table 3.1-1 List of Abbreviations.................................................................................................... 17
Table 4.1-1 NuMicro® NUC121 USB Series Selection Guide........................................................ 19
Table 4.1-2 NuMicro® NUC125 USB Series Selection Guide........................................................ 19
Table 4.3-1 NUC121 USB Series QFN33 Pin Description ............................................................ 36
Table 4.3-2 NUC121 USB Series LQFP48 Pin Description........................................................... 43
Table 4.3-3 NUC121 USB Series LQFP64 Pin Description........................................................... 51
Table 4.3-4 NUC125 USB Series QFN33 Pin Description ............................................................ 56
Table 4.3-5 NUC125 USB Series LQFP48 Pin Description........................................................... 63
Table 4.3-6 NUC125 USB Series LQFP64 Pin Description........................................................... 71
Table 4.3-7 NUC121/125 GPIO Multi-function Table .................................................................... 77
Table 6.2-1 Reset Value of Registers............................................................................................ 84
Table 6.2-2 Power Mode Difference Table .................................................................................... 88
Table 6.2-3 Clocks in Power Modes .............................................................................................. 89
Table 6.2-4 Condition of Entering Power-down Mode Again......................................................... 90
Table 6.3-1 Clock Stable Count Value Table................................................................................. 94
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1 GENERAL DESCRIPTION
The NuMicro® NUC121/125 series is a 32-bit Cortex® -M0 microcontroller with USB 2.0 Full-speed
device, a 12-bit ADC and 4 sets of 6-channel BPWM. The NUC121/125 series provides the high
50 MHz operating speed, 8 Kbytes SRAM, 8 USB endpoints and 24 channels of BPWM, which
make it powerful in USB communication and data processing. The NUC121/125 series is ideal for
industrial control, consumer electronics, and communication system applications such as printers,
touch panel, gaming keyboard, gaming joystick, USB audio, PC peripherals, and alarm systems.
The NUC121/125 series runs up to 50 MHz and supports 32-bit multiplier, structure NVIC (Nested
Vector Interrupt Control), dual-channel APB and PDMA (Peripheral Direct Memory Access) with
CRC function. Besides, the NUC121/125 series is equipped with 32 Kbytes Flash memory, 8
Kbytes SRAM, and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V
~ 5.5V and temperature range of -40℃ ~ +105℃. It is also equipped with plenty of peripheral
devices, such as 8-channel 12-bit ADC, USCI, UART, SPI, I2C, I2S, USB 2.0 FS device, and
offers low-voltage reset and Brown-out detection, PWM (Pulse-width Modulation), capture and
compare features, four sets of 32-bit timers, Watchdog Timer, and internal RC oscillator. All these
peripherals have been incorporated into the NUC121/125 series to reduce component count,
board space and system cost.
Additionally, the NUC121/125 series is equipped with ISP (In-System Programming), IAP (In-
Application-Programming) and ICP (In-Circuit Programming) functions, which allows the user to
update the program under software control through the on-chip connectivity interface, such as
SWD, UART and USB. Also all series support SPROM. Moreover, the NUC125 support Voltage
Adjustable Interface with individual I/O (1.8V-5.5V) for saving additional cost on adjusting the
interface voltage difference of peripheral components.
1.1 Key Features Support Table
* USCI can be set to UART, I2C or SPI
Product Line
NUC121
USBD
USCI
UART
I2C
2
SPI/ I2S
Timer
BPWM
24
ADC
12
1
1
1
1
1
1
1
1
4
4
NUC125
2
23
11
Table 1.1-1 Key Features Support Table
The NuMicro® NUC121/125 series is suitable for a wide range of applications such as:
USB Keyboard / Mouse
Gaming - Joystick
Industrial Automation
Home Automation
VR peripheral application
USB audio
Alarm system
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2 FEATURES
2.1 NuMicro® NUC121/125 Features
Core
–
–
–
–
–
ARM® Cortex® -M0 core running up to 50 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
Supports programmable 4 level priorities of Nested Vectored Interrupt Controller
(NVIC)
–
–
Supports programmable mask-able interrupts
Supports Serial Wire Debug(SWD) with 2 watch-points/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Flash Memory
–
–
–
–
–
–
–
Supports 32 KB application ROM (APROM)
Supports 4.5 KB Flash for loader (LDROM)
Supports 512 bytes Security Protection Rom (SPROM)
Supports 12 bytes User Configuration block to control system initiation
Supports Data Flash with configurable memory size
Supports 512 bytes page erase for all embedded flash
Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
–
–
–
–
Supports CRC-32 checksum calculation function
Supports flash all one verification function
Hardware external read protection of whole flash memory by Security Lock Bit
Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
–
–
–
8 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
PDMA (Peripheral DMA)
–
Supports 5 independent configurable channels for automatic data transfer between
memories and peripherals
–
–
–
–
–
–
–
Supports single and burst transfer type
Supports Normal and Scatter-Gather Transfer modes
Supports two types of priorities modes: Fixed-priority and Round-robin modes
Supports byte-, half-word- and word-access
Supports incrementing mode for the source and destination address for each channel
Supports time-out function for channel 0 and channel 1
Supports software and SPI/I2S, UART, USCI, USB, ADC, PWM and TIMER request
Clock Control
–
Built-in 48 MHz internal high speed RC oscillator (HIRC) for USB device operation
(Frequency variation < 2% at -40℃ ~ +105℃)
Dynamically calibrating the HIRC OSC to 48 MHz ±0.25% from -40℃ to 105℃
by external 32.768K crystal oscillator (LXT) or internal USB synchronous mode
–
–
Built-in 10 kHz internal low speed RC oscillator for Watchdog Timer and Wake-up
operation
Supports one interface to connect external crystal oscillator for high speed or low
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speed application
Built-in 4~24 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Built-in 32.768 kHz external low speed crystal oscillator (LXT) for low-power
system operation
–
Supports one PLL up to 100 MHz for high performance system operation, sourced
from HIRC and HXT
–
–
–
–
–
Supports clock on-the-fly switch
Supports clock failure detection for high/low speed external crystal oscillator
Supports auto clock switch once clock failure detected
Supports exception (NMI) generated once a clock failure detected
Supports divided clock output
GPIO
–
–
–
–
–
–
Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports up to 52/38/22 GPIOs for LQFP64/48 and QFN33 respectively
Timer
–
–
–
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
–
–
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
BPWM, PWM, ADC and PDMA function
Supports Inter-Timer trigger mode
Watchdog Timer
–
–
–
–
Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT
Supports 8 selections of time-out period (1.6ms ~ 26.0sec for LIRC)
Supports wake up from Power-down or Idle mode
Supports Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
–
–
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Supports Window set by 6-bit counter with 11-bit prescale
Supports Interrupt
BPWM/Capture
–
–
Supports maximum clock frequency up to 100MHz
Supports up to two BPWM modules, each module provides one 16-bit counter and 6
output channels
–
–
–
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution BPWM counter
Up, down and up/down counter operation type
–
–
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt on the following events:
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BPWM counter match zero, period value or compared value
Supports trigger ADC on the following events:
BPWM counter match zero, period value or compared value
–
–
–
–
–
Supports capture mode with 16-bit resolution for each BPWM pin
Supports rising edges, falling edges or both edges capture condition
Supports input rising edges, falling edges or both edges capture interrupt
Supports rising edges, falling edges or both edges capture with counter reload option
PWM/Capture
–
–
Supports maximum clock frequency up to 100MHz
Supports up to two PWM modules, each module provides three 16-bit counter and 6
output channels
–
–
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
–
–
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
–
–
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out
detection and CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
–
–
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
–
–
–
–
–
Supports capture mode with 16-bit resolution for each PWM pin
Supports rising edges, falling edges or both edges capture condition
Supports input rising edges, falling edges or both edges capture interrupt
Supports rising edges, falling edges or both edges capture with counter reload option
Supports PDMA for capture mode
USCI
–
UART Mode
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-Bit Data Transfer (Support 9-Bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports Wake-up function (Data and nCTS Wakeup Only)
Supports PDMA transfer
–
SPI Mode
Supports Master or Slave mode operation (the maximum frequency -- Master =
fPCLK / 2, Slave = fPCLK / 5)
Supports one transmit buffer and two receive buffers for data payload
Configurable bit length of a transfer word from 4 to 16-bit
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
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Supports one data channel half-duplex transfer
Supports PDMA transfer
–
I2C Mode
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
UART
–
–
–
–
–
–
–
–
–
Supports one set of UART
Supports maximum clock frequency up to 10 Mbps
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control (RX, TX, CTS and RTS)
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UART_TOUT [15:8])
–
–
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
–
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
–
–
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
–
Supports RS-485 mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
–
–
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports PDMA transfer
SPI / I2S
–
SPI
Supports one set of SPI controller
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
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I2S
Supports PDMA transfer
–
Supports Master or Slave mode operation
Capable of handling 8-, 16-, 24- and 32-bit word sizes in I2S mode
Provides separate 4-level depth transmit and receive FIFO buffers in I2S mode
Supports monaural and stereo audio data in I2S mode
Supports PCM mode A, PCM mode B, I2S and MSB justified data format in I2S
mode
Supports PDMA transfer
I2C
–
–
–
–
–
–
Supports up to two sets of I2C devices
Supports speed up to 1Mbps
Supports Master/Slave mode
Supports bidirectional data transfer between masters and slaves
Supports multi-master bus bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
–
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
–
–
–
–
–
Programmable clocks allow versatile rate control
Supports multiple address recognition, four slave address with mask option
Supports two-level buffer function
Supports setup/hold time programmable
Supports wake-up function
USB 2.0 FS Device Controller
–
–
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
–
–
–
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 768 bytes buffer size
–
–
–
–
–
Provides remote wake-up capability
Start of Frame (SOF) locked clock pulse generation
Supports USB 2.0 Link Power Management (LPM)
Supports Crystal-less function
Supports PDMA transfer
ADC
–
–
–
–
–
–
–
–
Supports 12-bit SAR ADC
12-bit resolution and 10-bit accuracy is guaranteed
Analog input voltage range: 0~ AVDD
Up to 12 single-end analog input channels or 6 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Conversion rate up to 800K SPS at 5V
Configurable ADC internal sampling time
Supports single, burst, single-cycle scan, and continuous scan modes on enabled
channels
Aug. 17, 2018
Page 14 of 148
Rev 1.02
NUC121/125
–
–
–
Supports individual conversion result register with valid and overrun indicators for each
channel
Supports digital comparator to monitor conversion result and user can select whether
to generate an interrupt when conversion result matches the compare register setting
An A/D conversion can be triggered by:
Software enable
External pin (STADC)
Timer 0~3 overflow pulse trigger
PWM triggers with optional start delay period
–
–
Supports 2 internal channels for
Band-gap VBG input
Temperature sensor input
Supports PDMA transfer
Supports 96-bit Unique ID (UID)
Supports 128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out detector
–
–
With 4 levels: 4.3 V/ 3.7V/ 2.7V/ 2.2V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 2.0 V
Operating Temperature: -40℃~105℃
Packages
–
–
–
–
All Green package (RoHS)
LQFP 64-pin (7mm x 7mm)
LQFP 48-pin (7mm x 7mm)
QFN 33-pin (5mm x 5 mm)
Aug. 17, 2018
Page 15 of 148
Rev 1.02
NUC121/125
3 ABBREVIATIONS
3.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
DAP
DES
EBI
Advanced High-Performance Bus
Brown-out Detection
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
48 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital
SD
Aug. 17, 2018
Page 16 of 148
Rev 1.02
NUC121/125
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TMR
UART
UCID
USB
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
Aug. 17, 2018
Page 17 of 148
Rev 1.02
NUC121/125
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC121/125 Selection Guide
4.1.1
NuMicro® NUC121/125 Naming Rule
ARM–Based
32-bit Microcontroller
NUC 1 2 X - XXXXX
CPU Core
Temperature
E: -40oC ~ +105oC
1: Cortex® -M0
Reserved
Product Line Function
2: USB Line
SRAM Size
2: 8 KB
Flash ROM
C: 32 KB
Sub-Line
1: Without VDDIO
5: With VDDIO
Package Type
Z: QFN 33 5x5mm
L: LQFP 48 7x7mm
S: LQFP 64 7x7mm
Figure 4.1-1 NuMicro® NUC121/125 Selection Code
Aug. 17, 2018
Page 18 of 148
Rev 1.02
NUC121/125
4.1.2
NuMicro® NUC121 USB Series Selection Guide
* USCI can be set to UART, I2C or SPI
Connectivity
NUC121ZC2AE
NUC121LC2AE
NUC121SC2AE
32
32
32
8
8
8
4.5
4.5
4.5
22
38
52
4
4
4
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
17
24
24
4-ch
10-ch
12-ch
5-ch
5-ch
5-ch
√
√
√
-
-
-
QFN 33
LQFP 48
LQFP 64
Table 4.1-1 NuMicro® NUC121 USB Series Selection Guide
4.1.3
NuMicro® NUC125 USB Series Selection Guide
* USCI can be set to UART, I2C or SPI
Connectivity
NUC125ZC2AE
NUC125LC2AE
NUC125SC2AE
32
32
32
8
8
8
4.5
4.5
4.5
22
37
51
4
4
4
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
17
23
23
4-ch
9-ch
5-ch
5-ch
5-ch
√
√
√
√
√
√
QFN 33
LQFP 48
LQFP 64
11-ch
Table 4.1-2 NuMicro® NUC125 USB Series Selection Guide
Aug. 17, 2018
Page 19 of 148
Rev 1.02
NUC121/125
4.2 Pin Configuration
4.2.1
NuMicro® NUC121 QFN 33-Pin Diagram
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
AVDD
PD.1
PC.0
Top transparent view
PC.1
PD.2
PC.2
PD.3
PC.3
NUC121Z
QFN33
PF.0
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS
PF.1
nRESET
VSS
33 VSS
Figure 4.2-1 NuMicro® NUC121 QFN 33-Pin Diagram
Aug. 17, 2018
Page 20 of 148
Rev 1.02
NUC121/125
4.2.2
NuMicro® NUC121 QFN 33-Pin Function Diagram
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
AVDD
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
TM3 / BPWM1_CH3 / XT_OUT / PF.0
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
Top transparent view
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
NUC121Z
QFN33
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
USB_D+
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
USB_D-
nRESET
USB_VDD33_CAP
USB_VBUS
33 VSS
VSS
Figure 4.2-2 NuMicro® NUC121 QFN 33-Pin Function Diagram
Aug. 17, 2018
Page 21 of 148
Rev 1.02
NUC121/125
4.2.3
NuMicro® NUC121 LQFP 48-Pin Diagram
37
24
23
22
21
20
19
18
17
16
15
14
13
AVDD
PB.9
38
PD.0
PB.10
PC.0
39
PD.1
40
PD.2
PC.1
41
PD.3
PC.2
42
NUC121L
LQFP48
PD.4
PD.5
PC.3
43
44
45
46
47
48
PC.4
PF.0
PC.5
PF.1
USB_D+
USB_D-
nRESET
PF.2
USB_VDD33_CAP
USB_VBUS
PF.3
Figure 4.2-3 NuMicro® NUC121 LQFP 48-Pin Diagram
Aug. 17, 2018
Page 22 of 148
Rev 1.02
NUC121/125
4.2.4
NuMicro® NUC121 LQFP 48-Pin Function Diagram
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
AVDD
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
BPWM1_CH4 / ADC_CH5 / PD.5
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
NUC121L
LQFP48
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
USB_D+
nRESET
USB_D-
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
USB_VDD33_CAP
USB_VBUS
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
Figure 4.2-4 NuMicro® NUC121 LQFP 48-Pin Function Diagram
Aug. 17, 2018
Page 23 of 148
Rev 1.02
NUC121/125
4.2.5
NuMicro® NUC121 LQFP 64-Pin Diagram
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PD.0
PB.9
50
PD.1
PB.10
PC.0
51
PD.2
52
PD.3
PC.1
53
PD.4
PC.2
54
PD.5
PC.3
55
PB.15
PC.4
56
NUC121S
LQFP64
PF.0
PF.1
PC.5
57
58
59
60
61
62
63
64
PB.3
nRESET
VSS
PB.2
PB.1
VDD
PB.0
PF.2
USB_D+
USB_D-
PF.3
VSS
USB_VDD33_CAP
USB_VBUS
PB.8
Figure 4.2-5 NuMicro® NUC121 LQFP 64-Pin Diagram
Aug. 17, 2018
Page 24 of 148
Rev 1.02
NUC121/125
4.2.6
NuMicro® NUC121 LQFP 64-Pin Function Diagram
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
50
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
51
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
52
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
53
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
PB.3 / UART0_nCTS / TM3_EXT / PWM1_CH3
PB.2 / UART0_nRTS / TM2_EXT / PWM1_CH2
PB.1 / UART0_TXD / PWM1_CH1
54
BPWM1_CH4 / ADC_CH5 / PD.5
55
BPWM1_CH5 / TM0_EXT / INT1 / PB.15
56
57
58
59
60
61
62
63
64
NUC121S
LQFP64
TM3 / BPWM1_CH3 / XT_OUT / PF.0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
nRESET
VSS
VDD
PB.0 / UART0_RXD / PWM1_CH0
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
VSS
USB_D+
USB_D-
USB_VDD33_CAP
BPWM1_CH1 / ADC_CH8 / TM0 / PB.8
USB_VBUS
Figure 4.2-6 NuMicro® NUC121 LQFP 64-Pin Function Diagram
Aug. 17, 2018
Page 25 of 148
Rev 1.02
NUC121/125
4.2.7
NuMicro® NUC125 QFN 33-Pin Diagram
25
16
15
14
13
12
11
10
9
AVDD
PC.0
Top transparent view
26
27
28
29
30
31
32
PD.1
PD.2
PC.1
PC.2
PD.3
PC.3
NUC125Z
QFN33
PF.0
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS
PF.1
nRESET
VDDIO
33 VSS
VDDIO power domain
Figure 4.2-7 NuMicro® NUC125 QFN 33-Pin Diagram
Aug. 17, 2018
Page 26 of 148
Rev 1.02
NUC121/125
4.2.8
NuMicro® NUC125 QFN 33-Pin Function Diagram
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
AVDD
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
TM3 / BPWM1_CH3 / XT_OUT / PF.0
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
Top transparent view
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
NUC125Z
QFN33
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
USB_D+
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
USB_D-
nRESET
USB_VDD33_CAP
USB_VBUS
33 VSS
VDDIO
VDDIO power domain
Figure 4.2-8 NuMicro® NUC125 QFN 33-Pin Function Diagram
Aug. 17, 2018
Page 27 of 148
Rev 1.02
NUC121/125
4.2.9
NuMicro® NUC125 LQFP 48-Pin Diagram
37
24
23
22
21
20
19
18
17
16
15
14
13
AVDD
PB.9
38
PD.0
PB.10
PC.0
39
PD.1
40
PD.2
PC.1
41
PD.3
PC.2
42
NUC125L
LQFP48
PD.4
PD.5
PC.3
43
44
45
46
47
48
PC.4
PF.0
PC.5
PF.1
USB_D+
USB_D-
nRESET
PF.2
USB_VDD33_CAP
USB_VBUS
PF.3
VDDIO power domain
Figure 4.2-9 NuMicro® NUC125 LQFP 48-Pin Diagram
Aug. 17, 2018
Page 28 of 148
Rev 1.02
NUC121/125
4.2.10 NuMicro® NUC125 LQFP 48-Pin Function Diagram
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
AVDD
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
BPWM1_CH4 / ADC_CH5 / PD.5
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
NUC125L
LQFP48
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
TM3 / BPWM1_CH3 / XT_OUT / PF.0
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
USB_D+
nRESET
USB_D-
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
USB_VDD33_CAP
USB_VBUS
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
VDDIO power domain
Figure 4.2-10 NuMicro® NUC125 LQFP 48-Pin Function Diagram
Aug. 17, 2018
Page 29 of 148
Rev 1.02
NUC121/125
4.2.11 NuMicro® NUC125 LQFP 64-Pin Diagram
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PD.0
PB.9
50
PD.1
PB.10
PC.0
51
PD.2
52
PD.3
PC.1
53
PD.4
PC.2
54
PD.5
PC.3
55
PB.15
PC.4
56
NUC125S
LQFP64
PF.0
PF.1
PC.5
57
58
59
60
61
62
63
64
PB.3
nRESET
VSS
PB.2
PB.1
VDD
PB.0
PF.2
USB_D+
USB_D-
PF.3
VSS
USB_VDD33_CAP
USB_VBUS
VDDIO
VDDIO power domain
Figure 4.2-11 NuMicro® NUC125 LQFP 64-Pin Diagram
Aug. 17, 2018
Page 30 of 148
Rev 1.02
NUC121/125
4.2.12 NuMicro® NUC125 LQFP 64-Pin Function Diagram
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SPI0_SS / USCI0_CTL0 / UART0_nRTS / ADC_CH0 / PD.0
PB.9 / TM1 / SPI0_I2SMCLK / PWM0_CH4
50
SPI0_CLK / USCI0_CLK / UART0_RXD / TM0_EXT / ADC_CH1 / PD.1
PB.10 / TM2 / SPI0_I2SMCLK / PWM0_CH5
51
SPI0_MISO / USCI0_DAT1 / UART0_TXD / TM3 / ADC_CH2 / PD.2
PC.0 / SPI0_SS / PWM1_CH0 / TM2 / UART0_RXD / USCI0_CLK
PC.1 / SPI0_CLK / PWM1_CH1 / UART0_TXD / USCI0_CTL0
52
SPI0_MOSI / USCI0_DAT0 / UART0_nCTS / TM1_EXT / ADC_CH3 / PD.3
53
SPI0_SS / USCI0_CTL0 / UART0_nRTS / BPWM1_CH5 / ADC_CH4 / PD.4
PC.2 / SPI0_MISO / I2C1_SCL / PWM1_CH2 / UART0_nCTS / USCI0_DAT1
PC.3 / SPI0_MOSI / I2C1_SDA / PWM1_CH3 / UART0_nRTS / USCI0_DAT0
PC.4 / UART0_RXD / SPI0_I2SMCLK / PWM1_CH4 / USCI0_DAT1
PC.5 / UART0_TXD / PWM1_CH5 / USCI0_DAT0
PB.3 / UART0_nCTS / TM3_EXT / PWM1_CH3
PB.2 / UART0_nRTS / TM2_EXT / PWM1_CH2
PB.1 / UART0_TXD / PWM1_CH1
54
BPWM1_CH4 / ADC_CH5 / PD.5
55
BPWM1_CH5 / TM0_EXT / INT1 / PB.15
56
57
58
59
60
61
62
63
64
NUC125S
LQFP64
TM3 / BPWM1_CH3 / XT_OUT / PF.0
TM1_EXT / BPWM1_CH2 / XT_IN / PF.1
nRESET
VSS
VDD
PB.0 / UART0_RXD / PWM1_CH0
BPWM1_CH3 / ADC_CH6 / I2C0_SDA / PF.2
USB_D+
BPWM1_CH2 / ADC_CH7 / I2C0_SCL / PF.3
USB_D-
VSS
USB_VDD33_CAP
VDDIO
USB_VBUS
VDDIO power domain
Figure 4.2-12 NuMicro® NUC125 LQFP 64-Pin Function Diagram
Aug. 17, 2018
Page 31 of 148
Rev 1.02
NUC121/125
4.3 Pin Description
4.3.1
NUC121 USB Series QFN33 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
PB.14
Type
I/O
I
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
Description
1
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
2
PA.11
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
3
4
5
6
General purpose digital I/O pin.
I2C1 data input/output pin.
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PB.4
I/O
I/O
I/O
I
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
USCI0 DAT0 pin.
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
Timer3 event counter input / toggle output
USCI0 clock pin.
BPWM0_CH2
TM3
USCI0_CLK
USCI0_DAT1
LDO_CAP
USCI0 DAT1 pin.
LDO output pin.
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Pin No.
Pin Name
Type
MFP*
Description
7
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
8
VSS
A
A
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
Ground pin for digital circuit.
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
9
USB_VBUS
USB_VDD33_CAP
USB_D-
10
11
12
13
A
I
USB_D+
I
USB differential signal D+.
PC.3
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PC.2
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
I/O
I/O
I/O
I/O
I
14
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI0_MISO
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I/O
O
15
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
16
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
UART0_RXD
USCI0_CLK
PC.13
I/O
I/O
I/O
O
17
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
PWM0_CH3
CLKO
INT0
I
External interrupt0 input pin.
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Pin No.
Pin Name
I2C0_SDA
PC.12
Type
I/O
I/O
I/O
O
MFP*
MFP6
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
Description
I2C0 data input/output pin.
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
Clock Out
18
PWM0_CH2
SPI0_I2SMCLK
CLKO
O
INT0
I
External interrupt0 input pin.
I2C0 clock pin.
I2C0_SCL
USCI0_CTL1
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
USCI0 CTL1 pin.
19
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
I2C0_SDA
USCI0_DAT0
PC.10
20
21
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PC.9
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
22
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PF.4
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
O
23
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
Data transmitter output pin for UART0.
ICE_DAT
I2C0_SDA
UART0_TXD
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Pin No.
Pin Name
PWM0_CH3
PF.5
Type
I/O
I/O
I
MFP*
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
Description
PWM0 channel3 output/capture input.
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
24
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
25
26
A
PD.1
I/O
A
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
27
General purpose digital I/O pin.
ADC channel 2 analog input.
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
USCI0 DAT1 pin.
ADC_CH2
TM3
I/O
O
UART0_TXD
USCI0_DAT1
SPI0_MISO
PD.3
I/O
I/O
I/O
A
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
28
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PF.0
I
I
I/O
I/O
I/O
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
29
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
30
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
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Pin No.
Pin Name
Type
MFP*
Description
31
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
nRESET
I
MFP0
32
33
VSS
VSS
A
A
MFP0
MFP0
Ground pin for digital circuit.
Ground pin for digital circuit.
Table 4.3-1 NUC121 USB Series QFN33 Pin Description
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4.3.2
NUC121 USB Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0..
Pin No.
Pin Name
VSS
Type
A
MFP*
MFP0
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
Description
1
2
Ground pin for digital circuit.
General purpose digital I/O pin.
Timer0event counter input / toggle output
ADC channel 8 analog input.
BPWM1 channel 1 output/capture input.
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
PB.8
I/O
I/O
A
TM0
ADC_CH8
BPWM1_CH1
PB.14
I/O
I/O
I
3
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
4
PA.11
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
5
6
7
General purpose digital I/O pin.
I2C1 data input/output pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PB.4
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
I/O
I/O
I/O
I/O
USCI0 DAT0 pin.
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
BPWM0_CH2
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Pin No.
Pin Name
TM3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
MFP*
MFP5
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
Description
Timer3 event counter input / toggle output
USCI0 clock pin.
USCI0_CLK
USCI0_DAT1
PB.6
USCI0 DAT1 pin.
8
9
General purpose digital I/O pin.
BPWM0 channel 1 output/capture input.
USCI0 DAT0 pin.
BPWM0_CH1
USCI0_DAT0
USCI0_CTL1
PB.7
USCI0 CTL1 pin.
General purpose digital I/O pin.
BPWM0 channel 0 output/capture input.
USCI0 DAT1 pin.
BPWM0_CH0
USCI0_DAT1
USCI0_CTL0
LDO_CAP
USCI0 CTL0 pin.
10
11
LDO output pin.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
12
13
14
15
16
17
VSS
A
A
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
Ground pin for digital circuit.
USB_VBUS
USB_VDD33_CAP
USB_D-
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
A
I
USB_D+
I
USB differential signal D+.
PC.5
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel5 output/capture input.
USCI0 DAT0 pin.
UART0_TXD
PWM1_CH5
USCI0_DAT0
PC.4
I/O
I/O
I/O
I
18
General purpose digital I/O pin.
Data receiver input pin for UART0.
I2S0 master clock output pin.
PWM1 channel4 output/capture input.
USCI0 DAT1 pin.
UART0_RXD
SPI0_I2SMCLK
PWM1_CH4
USCI0_DAT1
PC.3
O
I/O
I/O
I/O
I/O
I/O
I/O
O
19
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
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Pin No.
Pin Name
PC.2
Type
I/O
I/O
I/O
I/O
I
MFP*
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP4
MFP0
MFP2
MFP3
MFP5
MFP6
MFP0
MFP2
MFP3
Description
20
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI0_MISO
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I/O
O
21
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
22
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
UART0_RXD
USCI0_CLK
PB.10
I/O
I/O
I/O
O
23
24
25
General purpose digital I/O pin.
Timer2 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel5 output/capture input.
General purpose digital I/O pin.
Timer1 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel4 output/capture input.
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
TM2
SPI0_I2SMCLK
PWM0_CH5
PB.9
I/O
I/O
I/O
O
TM1
SPI0_I2SMCLK
PWM0_CH4
PC.13
I/O
I/O
I/O
O
PWM0_CH3
CLKO
INT0
I
External interrupt0 input pin.
I2C0 data input/output pin.
I2C0_SDA
PC.12
I/O
I/O
I/O
O
26
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
PWM0_CH2
SPI0_I2SMCLK
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Pin No.
Pin Name
CLKO
Type
O
MFP*
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
Description
Clock Out
INT0
I
External interrupt0 input pin.
I2C0 clock pin.
I2C0_SCL
USCI0_CTL1
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
USCI0 CTL1 pin.
27
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
I2C0_SDA
USCI0_DAT0
PC.10
28
29
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PC.9
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
30
31
32
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PA.15
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH3
SPI_I2SMCLK
CLKO
O
PWM1_BRAKE1
UART0_nRTS
PA.14
I
Brake input pin 1 of PWM1.
Request to Send output pin for UART0.
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
O
I/O
I/O
PWM0_CH2
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Pin No.
Pin Name
UART0_nCTS
PWM0_BRAKE0
PA.13
Type
I
MFP*
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
Description
Clear to Send input pin for UART0.
Brake input pin 0 of PWM0.
General purpose digital I/O pin.
PWM0 channel1 output/capture input.
I2C1 data input/output pin.
I
33
I/O
I/O
I/O
O
PWM0_CH1
I2C1_SDA
UART0_TXD
PA.12
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM0 channel0 output/capture input.
I2C1 clock pin.
34
35
I/O
I/O
I/O
I
PWM0_CH0
I2C1_SCL
UART0_RXD
PF.4
Data receiver input pin for UART0.
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
I/O
I/O
I/O
O
ICE_DAT
I2C0_SDA
UART0_TXD
PWM0_CH3
PF.5
Data transmitter output pin for UART0.
PWM0 channel3 output/capture input.
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
I/O
I/O
I
36
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 0 analog input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
37
38
A
PD.0
I/O
A
ADC_CH0
UART0_nRTS
USCI0_CTL0
SPI0_SS
O
I/O
I/O
I/O
A
SPI0 slave select pin.
39
PD.1
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
40
General purpose digital I/O pin.
ADC channel 2 analog input.
ADC_CH2
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Pin No.
Pin Name
TM3
Type
I/O
O
MFP*
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP0
Description
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
USCI0 DAT1 pin.
UART0_TXD
USCI0_DAT1
SPI0_MISO
PD.3
I/O
I/O
I/O
A
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
41
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PD.4
I
I
I/O
I/O
I/O
A
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
ADC channel 4 analog input.
BPWM1 channel 5 output/capture input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
42
ADC_CH4
BPWM1_CH5
UART0_nRTS
USCI0_CTL0
SPI0_SS
I/O
O
I/O
I/O
I/O
A
SPI0 slave select pin.
43
44
PD.5
General purpose digital I/O pin.
ADC channel 5 analog input.
BPWM1 channel 4 output/capture input.
General purpose digital I/O pin.
ADC_CH5
BPWM1_CH4
PF.0
I/O
I/O
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
45
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
46
47
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
nRESET
I
MFP0
PF.2
I/O
I/O
A
MFP0
MFP2
MFP3
MFP4
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
ADC_CH6
BPWM1_CH3
ADC channel 6 analog input.
BPWM1 channel 3 output/capture input.
I/O
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Pin No.
Pin Name
PF.3
Type
I/O
I/O
A
MFP*
MFP0
MFP2
MFP3
MFP4
Description
48
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ADC_CH7
BPWM1_CH2
ADC channel 7 analog input.
BPWM1 channel 2 output/capture input.
I/O
Table 4.3-2 NUC121 USB Series LQFP48 Pin Description
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4.3.3
NUC121 USB Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
PB.14
Type
I/O
I
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP3
MFP6
MFP0
MFP2
MFP3
MFP6
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP6
MFP0
MFP5
MFP0
Description
1
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
A
I/O
I/O
I/O
A
2
3
PB.13
General purpose digital I/O pin.
ADC channel 10 analog input.
USCI0 CTL1 pin.
ADC_CH10
USCI0_CTL1
PB.12
I/O
I/O
O
General purpose digital I/O pin.
Clock Out
CLKO
ADC_CH11
USCI0_CTL0
PA.11
A
ADC channel 11 analog input.
USCI0 CTL0 pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
4
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
5
General purpose digital I/O pin.
I2C1 data input/output pin.
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PD.8
I/O
I/O
I/O
I/O
I
6
7
8
General purpose digital I/O pin.
USCI0 DAT0 pin.
USCI0_DAT0
PD.9
General purpose digital I/O pin.
Brake input pin 1 of PWM0.
General purpose digital I/O pin.
PWM0_BRAKE1
PD.10
I/O
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Pin No.
Pin Name
CLKO
Type
O
MFP*
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
Description
Clock Out
BPWM0_CH5
PD.11
I/O
I/O
I
BPWM0 channel 5 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
BPWM0 channel 4 output/capture input.
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
9
INT1
BPWM0_CH4
PB.4
I/O
I/O
I/O
I
10
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
USCI0 DAT0 pin.
11
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
Timer3 event counter input / toggle output
USCI0 clock pin.
BPWM0_CH2
TM3
USCI0_CLK
USCI0_DAT1
PB.6
USCI0 DAT1 pin.
12
13
General purpose digital I/O pin.
BPWM0 channel 1 output/capture input.
USCI0 DAT0 pin.
BPWM0_CH1
USCI0_DAT0
USCI0_CTL1
PB.7
USCI0 CTL1 pin.
General purpose digital I/O pin.
BPWM0 channel 0 output/capture input.
USCI0 DAT1 pin.
BPWM0_CH0
USCI0_DAT1
USCI0_CTL0
LDO_CAP
USCI0 CTL0 pin.
14
15
LDO output pin.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
16
17
18
19
20
21
VSS
A
A
A
I
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP4
Ground pin for digital circuit.
USB_VBUS
USB_VDD33_CAP
USB_D-
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
USB_D+
I
USB differential signal D+.
PB.0
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
PWM1 channel0 output/capture input.
UART0_RXD
PWM1_CH0
I/O
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Pin No.
Pin Name
PB.1
Type
I/O
O
MFP*
MFP0
MFP1
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
Description
22
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel1 output/capture input.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external counter input
PWM1 channel2 output/capture input.
General purpose digital I/O pin.
Clear to Send input pin for UART0.
Timer3 external counter input
PWM1 channel3 output/capture input.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel5 output/capture input.
USCI0 DAT0 pin.
UART0_TXD
PWM1_CH1
PB.2
I/O
I/O
O
23
24
25
26
UART0_nRTS
TM2_EXT
PWM1_CH2
PB.3
I
I/O
I/O
I
UART0_nCTS
TM3_EXT
PWM1_CH3
PC.5
I
I/O
I/O
O
UART0_TXD
PWM1_CH5
USCI0_DAT0
PC.4
I/O
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
I2S0 master clock output pin.
PWM1 channel4 output/capture input.
USCI0 DAT1 pin.
UART0_RXD
SPI0_I2SMCLK
PWM1_CH4
USCI0_DAT1
PC.3
O
I/O
I/O
I/O
I/O
I/O
I/O
O
27
28
29
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PC.2
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI0_MISO
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
General purpose digital I/O pin.
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Pin No.
Pin Name
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
Type
I/O
I/O
O
MFP*
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
MFP0
MFP2
MFP3
MFP4
MFP5
Description
SPI0 serial clock pin.
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
30
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
UART0_RXD
USCI0_CLK
PB.10
I/O
I/O
I/O
O
31
32
33
General purpose digital I/O pin.
Timer2 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel5 output/capture input.
General purpose digital I/O pin.
Timer1 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel4 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external counter input
I2C0 clock pin.
TM2
SPI0_I2SMCLK
PWM0_CH5
PB.9
I/O
I/O
I/O
O
TM1
SPI0_I2SMCLK
PWM0_CH4
PE.2
I/O
I/O
I
INT1
TM0_EXT
I2C0_SCL
USCI0_CTL1
PC.13
I
I/O
I/O
I/O
I/O
O
USCI0 CTL1 pin.
34
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
PWM0_CH3
CLKO
INT0
I
External interrupt0 input pin.
I2C0 data input/output pin.
I2C0_SDA
PC.12
I/O
I/O
I/O
O
35
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH2
SPI0_I2SMCLK
CLKO
O
INT0
I
External interrupt0 input pin.
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Pin No.
Pin Name
I2C0_SCL
USCI0_CTL1
PC.11
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
MFP*
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP2
MFP3
MFP5
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
Description
I2C0 clock pin.
USCI0 CTL1 pin.
36
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
I2C0_SDA
USCI0_DAT0
PC.10
37
38
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PE.1
General purpose digital I/O pin.
ADC external trigger input.
Clock Out
STADC
CLKO
O
TM3
I/O
I/O
I/O
I/O
I/O
I
Timer3 event counter input / toggle output
USCI0 DAT1 pin.
USCI0_DAT1
PC.9
39
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
40
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PA.15
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
O
41
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH3
SPI_I2SMCLK
CLKO
O
PWM1_BRAKE1
I
Brake input pin 1 of PWM1.
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Pin No.
Pin Name
UART0_nRTS
PE.0
Type
O
MFP*
MFP5
MFP0
MFP1
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP5
MFP6
Description
Request to Send output pin for UART0.
General purpose digital I/O pin.
External interrupt0 input pin.
Clock Out
42
I/O
I
INT0
CLKO
O
PWM0_CH3
TM1_EXT
USCI0_DAT0
PA.14
I/O
I
PWM0 channel3 output/capture input.
Timer1 external counter input
USCI0 DAT0 pin.
I/O
I/O
I/O
I
43
44
45
46
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
Clear to Send input pin for UART0.
Brake input pin 0 of PWM0.
General purpose digital I/O pin.
PWM0 channel1 output/capture input.
I2C1 data input/output pin.
PWM0_CH2
UART0_nCTS
PWM0_BRAKE0
PA.13
I
I/O
I/O
I/O
O
PWM0_CH1
I2C1_SDA
UART0_TXD
PA.12
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM0 channel0 output/capture input.
I2C1 clock pin.
I/O
I/O
I/O
I
PWM0_CH0
I2C1_SCL
UART0_RXD
PF.4
Data receiver input pin for UART0.
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
I/O
I/O
I/O
O
ICE_DAT
I2C0_SDA
UART0_TXD
PWM0_CH3
PF.5
Data transmitter output pin for UART0.
PWM0 channel3 output/capture input.
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
I/O
I/O
I
47
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 0 analog input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
48
49
A
PD.0
I/O
A
ADC_CH0
UART0_nRTS
USCI0_CTL0
O
I/O
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Pin No.
Pin Name
SPI0_SS
PD.1
Type
I/O
I/O
A
MFP*
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
Description
SPI0 slave select pin.
50
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
51
52
53
General purpose digital I/O pin.
ADC channel 2 analog input.
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
USCI0 DAT1 pin.
ADC_CH2
TM3
I/O
O
UART0_TXD
USCI0_DAT1
SPI0_MISO
PD.3
I/O
I/O
I/O
A
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PD.4
I
I
I/O
I/O
I/O
A
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
ADC channel 4 analog input.
BPWM1 channel 5 output/capture input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
ADC_CH4
BPWM1_CH5
UART0_nRTS
USCI0_CTL0
SPI0_SS
PD.5
I/O
O
I/O
I/O
I/O
A
SPI0 slave select pin.
54
55
General purpose digital I/O pin.
ADC channel 5 analog input.
BPWM1 channel 4 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external counter input
BPWM1 channel 5 output/capture input.
General purpose digital I/O pin.
ADC_CH5
BPWM1_CH4
PB.15
I/O
I/O
I
INT1
TM0_EXT
BPWM1_CH5
PF.0
I
I/O
I/O
56
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Pin No.
Pin Name
Type
MFP*
Description
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
57
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
58
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
nRESET
VSS
I
MFP0
MFP0
MFP0
59
60
A
A
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
61
PF.2
I/O
I/O
A
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
MFP0
MFP1
MFP3
MFP4
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
ADC_CH6
BPWM1_CH3
PF.3
ADC channel 6 analog input.
BPWM1 channel 3 output/capture input.
General purpose digital I/O pin.
I2C0 clock pin.
I/O
I/O
I/O
A
62
I2C0_SCL
ADC_CH7
BPWM1_CH2
VSS
ADC channel 7 analog input.
BPWM1 channel 2 output/capture input.
Ground pin for digital circuit.
I/O
A
63
64
PB.8
I/O
I/O
A
General purpose digital I/O pin.
Timer0event counter input / toggle output
ADC channel 8 analog input.
BPWM1 channel 1 output/capture input.
TM0
ADC_CH8
BPWM1_CH1
I/O
Table 4.3-3 NUC121 USB Series LQFP64 Pin Description
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4.3.4
NUC125 USB Series QFN33 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
PB.14
Type
I/O
I
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
Description
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
1
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PA.11
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
2
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
General purpose digital I/O pin.
I2C1 data input/output pin.
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PB.4
3
4
5
I/O
I/O
I/O
I
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
USCI0 DAT0 pin.
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
Timer3 event counter input / toggle output
USCI0 clock pin.
BPWM0_CH2
TM3
USCI0_CLK
USCI0_DAT1
LDO_CAP
USCI0 DAT1 pin.
6
7
LDO output pin.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
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Pin No.
Pin Name
VSS
Type
A
MFP*
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
Description
8
Ground pin for digital circuit.
Power supply from USB host or HUB.
9
USB_VBUS
USB_VDD33_CAP
USB_D-
A
10
11
12
A
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
I
USB_D+
I
USB differential signal D+.
PC.3
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PC.2
13
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI0_MISO
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
14
15
16
17
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
UART0_RXD
USCI0_CLK
PC.13
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
PWM0_CH3
CLKO
INT0
I
External interrupt0 input pin.
I2C0 data input/output pin.
I2C0_SDA
I/O
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Pin No.
Pin Name
PC.12
Type
I/O
I/O
O
MFP*
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
Description
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH2
SPI0_I2SMCLK
CLKO
18
O
INT0
I
External interrupt0 input pin.
I2C0 clock pin.
I2C0_SCL
USCI0_CTL1
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
USCI0 CTL1 pin.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
19
I2C0_SDA
USCI0_DAT0
PC.10
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PC.9
20
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
21
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
22
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PF.4
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
Data transmitter output pin for UART0.
PWM0 channel3 output/capture input.
ICE_DAT
I2C0_SDA
UART0_TXD
PWM0_CH3
23
I/O
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Pin No.
24
Pin Name
PF.5
Type
I/O
I
MFP*
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
Description
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
25
A
PD.1
I/O
A
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
26
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
General purpose digital I/O pin.
ADC channel 2 analog input.
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
USCI0 DAT1 pin.
ADC_CH2
TM3
I/O
O
27
UART0_TXD
USCI0_DAT1
SPI0_MISO
PD.3
I/O
I/O
I/O
A
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PF.0
I
28
I
I/O
I/O
I/O
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
29
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
30
31
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
nRESET
I
MFP0
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Pin No.
32
Pin Name
VDDIO
Type
A
MFP*
MFP0
MFP0
Description
Power supply for PB.14, PA.11, PA.10, PB.4 and PB.5.
Ground pin for digital circuit.
33
VSS
A
Table 4.3-4 NUC125 USB Series QFN33 Pin Description
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4.3.5
NUC125 USB Series LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0..
Pin No.
Pin Name
Type
MFP*
Description
1
VSS
A
MFP0
Ground pin for digital circuit.
Power supply for PB.14, PA.11, PA.10, PB.4, PB.5, PB.6
and PB.7.
2
3
VDDIO
A
MFP0
PB.14
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PA.11
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
4
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
General purpose digital I/O pin.
I2C1 data input/output pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PB.4
5
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
6
I/O
I/O
I/O
I/O
I/O
I/O
USCI0 DAT0 pin.
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
Timer3 event counter input / toggle output
USCI0 clock pin.
BPWM0_CH2
TM3
7
USCI0_CLK
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Pin No.
Pin Name
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
MFP*
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
Description
USCI0_DAT1
PB.6
USCI0 DAT1 pin.
General purpose digital I/O pin.
BPWM0 channel 1 output/capture input.
USCI0 DAT0 pin.
BPWM0_CH1
USCI0_DAT0
USCI0_CTL1
PB.7
8
USCI0 CTL1 pin.
General purpose digital I/O pin.
BPWM0 channel 0 output/capture input.
USCI0 DAT1 pin.
BPWM0_CH0
USCI0_DAT1
USCI0_CTL0
LDO_CAP
9
USCI0 CTL0 pin.
10
11
LDO output pin.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
12
13
14
15
16
VSS
A
A
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
Ground pin for digital circuit.
USB_VBUS
USB_VDD33_CAP
USB_D-
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
A
I
USB_D+
I
USB differential signal D+.
PC.5
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel5 output/capture input.
USCI0 DAT0 pin.
UART0_TXD
PWM1_CH5
USCI0_DAT0
PC.4
17
I/O
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
I2S0 master clock output pin.
PWM1 channel4 output/capture input.
USCI0 DAT1 pin.
UART0_RXD
SPI0_I2SMCLK
PWM1_CH4
USCI0_DAT1
PC.3
18
O
I/O
I/O
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PC.2
19
20
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
I/O
I/O
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SPI0_MISO
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Pin No.
Pin Name
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
Type
I/O
I/O
I
MFP*
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP4
MFP0
MFP2
MFP3
MFP5
MFP6
MFP0
MFP2
MFP3
MFP4
MFP5
Description
I2C1 clock pin.
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
21
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
22
UART0_RXD
USCI0_CLK
PB.10
I/O
I/O
I/O
O
General purpose digital I/O pin.
Timer2 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel5 output/capture input.
General purpose digital I/O pin.
Timer1 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel4 output/capture input.
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
TM2
23
24
SPI0_I2SMCLK
PWM0_CH5
PB.9
I/O
I/O
I/O
O
TM1
SPI0_I2SMCLK
PWM0_CH4
PC.13
I/O
I/O
I/O
O
PWM0_CH3
CLKO
25
INT0
I
External interrupt0 input pin.
I2C0 data input/output pin.
I2C0_SDA
PC.12
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH2
SPI0_I2SMCLK
CLKO
26
O
INT0
I
External interrupt0 input pin.
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Pin No.
Pin Name
I2C0_SCL
USCI0_CTL1
PC.11
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
MFP*
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP3
MFP4
Description
I2C0 clock pin.
USCI0 CTL1 pin.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
27
I2C0_SDA
USCI0_DAT0
PC.10
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PC.9
28
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
29
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
30
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PA.15
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH3
SPI_I2SMCLK
CLKO
31
O
PWM1_BRAKE1
UART0_nRTS
PA.14
I
Brake input pin 1 of PWM1.
Request to Send output pin for UART0.
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
Clear to Send input pin for UART0.
Brake input pin 0 of PWM0.
O
I/O
I/O
I
PWM0_CH2
UART0_nCTS
PWM0_BRAKE0
32
I
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Pin No.
Pin Name
PA.13
Type
I/O
I/O
I/O
O
MFP*
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
Description
General purpose digital I/O pin.
PWM0 channel1 output/capture input.
I2C1 data input/output pin.
PWM0_CH1
I2C1_SDA
UART0_TXD
PA.12
33
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM0 channel0 output/capture input.
I2C1 clock pin.
I/O
I/O
I/O
I
PWM0_CH0
I2C1_SCL
UART0_RXD
PF.4
34
Data receiver input pin for UART0.
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
I/O
I/O
I/O
O
ICE_DAT
I2C0_SDA
UART0_TXD
PWM0_CH3
PF.5
35
Data transmitter output pin for UART0.
PWM0 channel3 output/capture input.
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
I/O
I/O
I
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
36
37
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 0 analog input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
A
PD.0
I/O
A
ADC_CH0
UART0_nRTS
USCI0_CTL0
SPI0_SS
PD.1
38
O
I/O
I/O
I/O
A
SPI0 slave select pin.
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
39
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
General purpose digital I/O pin.
ADC channel 2 analog input.
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
ADC_CH2
TM3
40
I/O
O
UART0_TXD
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Pin No.
Pin Name
USCI0_DAT1
SPI0_MISO
PD.3
Type
I/O
I/O
I/O
A
MFP*
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP0
Description
USCI0 DAT1 pin.
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PD.4
I
41
I
I/O
I/O
I/O
A
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
ADC channel 4 analog input.
BPWM1 channel 5 output/capture input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
ADC_CH4
BPWM1_CH5
UART0_nRTS
USCI0_CTL0
SPI0_SS
I/O
O
42
I/O
I/O
I/O
A
SPI0 slave select pin.
PD.5
General purpose digital I/O pin.
ADC channel 5 analog input.
BPWM1 channel 4 output/capture input.
General purpose digital I/O pin.
43
44
ADC_CH5
BPWM1_CH4
PF.0
I/O
I/O
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
45
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
46
47
nRESET
I
MFP0
PF.2
I/O
I/O
A
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
General purpose digital I/O pin.
I2C0 data input/output pin.
ADC channel 6 analog input.
BPWM1 channel 3 output/capture input.
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SDA
ADC_CH6
BPWM1_CH3
PF.3
I/O
I/O
I/O
48
I2C0_SCL
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Pin No.
Pin Name
Type
A
MFP*
MFP3
MFP4
Description
ADC_CH7
ADC channel 7 analog input.
BPWM1 channel 2 output/capture input.
BPWM1_CH2
I/O
Table 4.3-5 NUC125 USB Series LQFP48 Pin Description
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4.3.6
NUC125 USB Series LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Pin No.
Pin Name
PB.14
Type
I/O
I
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP3
MFP6
MFP0
MFP2
MFP3
MFP6
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP0
MFP6
MFP0
MFP5
MFP0
Description
General purpose digital I/O pin.
External interrupt0 input pin.
Request to Send output pin for UART0.
ADC channel 9 analog input.
BPWM1 channel 0 output/capture input.
SPI0 slave select pin.
INT0
UART0_nRTS
ADC_CH9
BPWM1_CH0
SPI0_SS
O
1
A
I/O
I/O
I/O
A
PB.13
General purpose digital I/O pin.
ADC channel 10 analog input.
USCI0 CTL1 pin.
2
3
ADC_CH10
USCI0_CTL1
PB.12
I/O
I/O
O
General purpose digital I/O pin.
Clock Out
CLKO
ADC_CH11
USCI0_CTL0
PA.11
A
ADC channel 11 analog input.
USCI0 CTL0 pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
I2C1 clock pin.
I2C1_SCL
BPWM0_CH5
TM0
BPWM0 channel 5 output/capture input.
Timer0event counter input / toggle output
USCI0 clock pin.
4
USCI0_CLK
USCI0_DAT0
PA.10
USCI0 DAT0 pin.
General purpose digital I/O pin.
I2C1 data input/output pin.
BPWM0 channel 4 output/capture input.
Brake input pin 0 of PWM0.
USCI0 DAT1 pin.
I2C1_SDA
BPWM0_CH4
PWM0_BRAKE0
USCI0_DAT1
PD.8
5
6
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
USCI0 DAT0 pin.
USCI0_DAT0
PD.9
General purpose digital I/O pin.
Brake input pin 1 of PWM0.
General purpose digital I/O pin.
7
8
PWM0_BRAKE1
PD.10
I/O
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Pin No.
Pin Name
CLKO
Type
O
MFP*
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
Description
Clock Out
BPWM0_CH5
PD.11
I/O
I/O
I
BPWM0 channel 5 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
BPWM0 channel 4 output/capture input.
General purpose digital I/O pin.
BPWM0 channel 3 output/capture input.
Timer2 external counter input
USCI0 CTL0 pin.
9
INT1
BPWM0_CH4
PB.4
I/O
I/O
I/O
I
BPWM0_CH3
TM2_EXT
USCI0_CTL0
USCI0_DAT0
PB.5
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
USCI0 DAT0 pin.
General purpose digital I/O pin.
BPWM0 channel 2 output/capture input.
Timer3 event counter input / toggle output
USCI0 clock pin.
BPWM0_CH2
TM3
11
USCI0_CLK
USCI0_DAT1
PB.6
USCI0 DAT1 pin.
General purpose digital I/O pin.
BPWM0 channel 1 output/capture input.
USCI0 DAT0 pin.
BPWM0_CH1
USCI0_DAT0
USCI0_CTL1
PB.7
12
13
USCI0 CTL1 pin.
General purpose digital I/O pin.
BPWM0 channel 0 output/capture input.
USCI0 DAT1 pin.
BPWM0_CH0
USCI0_DAT1
USCI0_CTL0
LDO_CAP
USCI0 CTL0 pin.
14
15
LDO output pin.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
A
MFP0
16
17
18
19
20
VSS
A
A
A
I
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP4
Ground pin for digital circuit.
USB_VBUS
USB_VDD33_CAP
USB_D-
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
USB_D+
I
USB differential signal D+.
PB.0
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
PWM1 channel0 output/capture input.
21
UART0_RXD
PWM1_CH0
I/O
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Pin No.
Pin Name
PB.1
Type
I/O
O
MFP*
MFP0
MFP1
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
MFP2
MFP4
MFP7
MFP0
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
Description
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel1 output/capture input.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external counter input
PWM1 channel2 output/capture input.
General purpose digital I/O pin.
Clear to Send input pin for UART0.
Timer3 external counter input
PWM1 channel3 output/capture input.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
PWM1 channel5 output/capture input.
USCI0 DAT0 pin.
22
UART0_TXD
PWM1_CH1
PB.2
I/O
I/O
O
UART0_nRTS
TM2_EXT
PWM1_CH2
PB.3
23
24
25
I
I/O
I/O
I
UART0_nCTS
TM3_EXT
PWM1_CH3
PC.5
I
I/O
I/O
O
UART0_TXD
PWM1_CH5
USCI0_DAT0
PC.4
I/O
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
I2S0 master clock output pin.
PWM1 channel4 output/capture input.
USCI0 DAT1 pin.
UART0_RXD
SPI0_I2SMCLK
PWM1_CH4
USCI0_DAT1
PC.3
26
O
I/O
I/O
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
SPI0_MOSI
I2C1_SDA
PWM1_CH3
UART0_nRTS
USCI0_DAT0
PC.2
27
PWM1 channel3 output/capture input.
Request to Send output pin for UART0.
USCI0 DAT0 pin.
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI0_MISO
I2C1_SCL
PWM1_CH2
UART0_nCTS
USCI0_DAT1
PC.1
28
29
PWM1 channel2 output/capture input.
Clear to Send input pin for UART0.
USCI0 DAT1 pin.
I/O
I/O
General purpose digital I/O pin.
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Pin No.
Pin Name
SPI0_CLK
PWM1_CH1
UART0_TXD
USCI0_CTL0
PC.0
Type
I/O
I/O
O
MFP*
MFP1
MFP4
MFP6
MFP7
MFP0
MFP1
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
MFP0
MFP2
MFP3
MFP4
MFP5
Description
SPI0 serial clock pin.
PWM1 channel1 output/capture input.
Data transmitter output pin for UART0.
USCI0 CTL0 pin
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
PWM1_CH0
TM2
PWM1 channel0 output/capture input.
Timer2 event counter input / toggle output
Data receiver input pin for UART0.
USCI0 clock pin.
30
UART0_RXD
USCI0_CLK
PB.10
I/O
I/O
I/O
O
General purpose digital I/O pin.
Timer2 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel5 output/capture input.
General purpose digital I/O pin.
Timer1 event counter input / toggle output
I2S0 master clock output pin.
PWM0 channel4 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external counter input
I2C0 clock pin.
TM2
31
32
SPI0_I2SMCLK
PWM0_CH5
PB.9
I/O
I/O
I/O
O
TM1
SPI0_I2SMCLK
PWM0_CH4
PE.2
I/O
I/O
I
INT1
33
34
35
TM0_EXT
I2C0_SCL
USCI0_CTL1
PC.13
I
I/O
I/O
I/O
I/O
O
USCI0 CTL1 pin.
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
Clock Out
PWM0_CH3
CLKO
INT0
I
External interrupt0 input pin.
I2C0 data input/output pin.
I2C0_SDA
PC.12
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH2
SPI0_I2SMCLK
CLKO
O
INT0
I
External interrupt0 input pin.
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Pin No.
Pin Name
I2C0_SCL
USCI0_CTL1
PC.11
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
MFP*
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP7
MFP0
MFP2
MFP3
MFP5
MFP7
MFP0
MFP3
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
Description
I2C0 clock pin.
USCI0 CTL1 pin.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
PWM0 channel1 output/capture input.
Timer1 event counter input / toggle output
I2C0 data input/output pin.
USCI0 DAT0 pin.
SPI0_MOSI
PWM0_CH1
TM1
36
I2C0_SDA
USCI0_DAT0
PC.10
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
PWM0 channel0 output/capture input.
USCI0 DAT1 pin.
SPI0_MISO
PWM0_CH0
USCI0_DAT1
PE.1
37
General purpose digital I/O pin.
ADC external trigger input.
Clock Out
STADC
38
CLKO
O
TM3
I/O
I/O
I/O
I/O
I/O
I
Timer3 event counter input / toggle output
USCI0 DAT1 pin.
USCI0_DAT1
PC.9
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
PWM0_CH5
PWM0_BRAKE1
USCI0_CLK
PC.8
39
40
41
PWM0 channel5 output/capture input.
Brake input pin 1 of PWM0.
USCI0 clock pin
I/O
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
SPI0 slave select pin.
STADC
SPI0_SS
I/O
I/O
I
PWM0_CH4
PWM1_BRAKE0
USCI0_CTL0
PA.15
PWM0 channel4 output/capture input.
Brake input pin 0 of PWM1.
USCI0 CTL0 pin
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM0 channel3 output/capture input.
I2S0 master clock output pin.
Clock Out
PWM0_CH3
SPI_I2SMCLK
CLKO
O
PWM1_BRAKE1
I
Brake input pin 1 of PWM1.
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Pin No.
Pin Name
UART0_nRTS
PE.0
Type
O
MFP*
MFP5
MFP0
MFP1
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP3
MFP5
MFP6
Description
Request to Send output pin for UART0.
General purpose digital I/O pin.
External interrupt0 input pin.
Clock Out
I/O
I
INT0
CLKO
O
42
PWM0_CH3
TM1_EXT
USCI0_DAT0
PA.14
I/O
I
PWM0 channel3 output/capture input.
Timer1 external counter input
USCI0 DAT0 pin.
I/O
I/O
I/O
I
General purpose digital I/O pin.
PWM0 channel2 output/capture input.
Clear to Send input pin for UART0.
Brake input pin 0 of PWM0.
General purpose digital I/O pin.
PWM0 channel1 output/capture input.
I2C1 data input/output pin.
PWM0_CH2
UART0_nCTS
PWM0_BRAKE0
PA.13
43
44
45
I
I/O
I/O
I/O
O
PWM0_CH1
I2C1_SDA
UART0_TXD
PA.12
Data transmitter output pin for UART0.
General purpose digital I/O pin.
PWM0 channel0 output/capture input.
I2C1 clock pin.
I/O
I/O
I/O
I
PWM0_CH0
I2C1_SCL
UART0_RXD
PF.4
Data receiver input pin for UART0.
General purpose digital I/O pin.
Serial wired debugger data pin
I2C0 data input/output pin.
I/O
I/O
I/O
O
ICE_DAT
I2C0_SDA
UART0_TXD
PWM0_CH3
PF.5
46
Data transmitter output pin for UART0.
PWM0 channel3 output/capture input.
General purpose digital I/O pin.
Serial wired debugger clock pin
I2C0 clock pin.
I/O
I/O
I
ICE_CLK
I2C0_SCL
UART0_RXD
AVDD
47
48
49
I/O
I
Data receiver input pin for UART0.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC channel 0 analog input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
A
PD.0
I/O
A
ADC_CH0
UART0_nRTS
USCI0_CTL0
O
I/O
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Pin No.
Pin Name
SPI0_SS
PD.1
Type
I/O
I/O
A
MFP*
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP0
MFP1
MFP2
MFP4
MFP0
Description
SPI0 slave select pin.
General purpose digital I/O pin.
ADC channel 1 analog input.
Timer0 external counter input
Data receiver input pin for UART0.
USCI0 clock pin.
ADC_CH1
TM0_EXT
UART0_RXD
USCI0_CLK
SPI0_CLK
PD.2
I
50
I
I/O
I/O
I/O
A
SPI0 serial clock pin.
General purpose digital I/O pin.
ADC channel 2 analog input.
Timer3 event counter input / toggle output
Data transmitter output pin for UART0.
USCI0 DAT1 pin.
ADC_CH2
TM3
I/O
O
51
UART0_TXD
USCI0_DAT1
SPI0_MISO
PD.3
I/O
I/O
I/O
A
SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
Timer1 external counter input
Clear to Send input pin for UART0.
USCI0 DAT0 pin.
ADC_CH3
TM1_EXT
UART0_nCTS
USCI0_DAT0
SPI0_MOSI
PD.4
I
52
I
I/O
I/O
I/O
A
SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
ADC channel 4 analog input.
BPWM1 channel 5 output/capture input.
Request to Send output pin for UART0.
USCI0 CTL0 pin.
ADC_CH4
BPWM1_CH5
UART0_nRTS
USCI0_CTL0
SPI0_SS
PD.5
I/O
O
53
I/O
I/O
I/O
A
SPI0 slave select pin.
General purpose digital I/O pin.
ADC channel 5 analog input.
BPWM1 channel 4 output/capture input.
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external counter input
BPWM1 channel 5 output/capture input.
General purpose digital I/O pin.
54
ADC_CH5
BPWM1_CH4
PB.15
I/O
I/O
I
INT1
55
56
TM0_EXT
BPWM1_CH5
PF.0
I
I/O
I/O
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Pin No.
Pin Name
Type
MFP*
Description
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal output pin.
XT_OUT
O
MFP1
BPWM1_CH3
TM3
I/O
I/O
I/O
MFP4
MFP5
MFP0
BPWM1 channel 3 output/capture input.
Timer3 event counter input / toggle output
General purpose digital I/O pin.
PF.1
External 4~24 MHz (high speed) or 32.768 kHz (low
speed) crystal input pin.
XT_IN
I
MFP1
57
BPWM1_CH2
TM1_EXT
I/O
I
MFP4
MFP5
BPWM1 channel 2 output/capture input.
Timer1 external counter input
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
58
59
60
nRESET
VSS
I
MFP0
MFP0
MFP0
A
A
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal
PLL and digital function.
VDD
PF.2
I/O
I/O
A
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
ADC_CH6
BPWM1_CH3
PF.3
61
62
ADC channel 6 analog input.
BPWM1 channel 3 output/capture input.
General purpose digital I/O pin.
I2C0 clock pin.
I/O
I/O
I/O
A
I2C0_SCL
ADC_CH7
BPWM1_CH2
VSS
ADC channel 7 analog input.
BPWM1 channel 2 output/capture input.
Ground pin for digital circuit.
I/O
A
63
64
Power supply for PB.14, PB.13, PB.12, PA.11, PA.10,
PD.8, PD.9, PD.10, PD.11, PB.4, PB.5, PB.6 and PB.7.
VDDIO
A
MFP0
Table 4.3-6 NUC125 USB Series LQFP64 Pin Description
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4.3.7
GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.10 MFP5 means SYS_GPA_MFPH[11:8]=0x5.
PC.0 MFP0 means SYS_GPC_MFPL[3:0]=0x0.
Group
Pin Name
GPIO
PD.0
PD.1
PD.2
PD.3
PD.4
PD.5
PF.2
MFP*
MFP3
MFP3
MFP3
MFP3
MFP2
MFP2
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP2
MFP2
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
Type
A
Description
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
STADC
ADC0 analog input.
A
ADC1 analog input.
A
ADC2 analog input.
A
ADC3 analog input.
A
ADC4 analog input.
A
ADC5 analog input.
A
ADC6 analog input.
ADC0
PF.3
A
ADC7 analog input.
PB.8
PB.14
PB.13
PB.12
PC.8
PE.1
PB.7
PB.6
PB.5
PB.4
PA.10
PD.11
PA.11
PD.10
PB.14
PB.8
PF.1
A
ADC8 analog input.
A
ADC9 analog input.
A
ADC10 analog input.
A
ADC11 analog input.
I
ADC external trigger input.
ADC external trigger input
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM0 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
BPWM1 output/capture input.
STADC
I
BPWM0_CH0
BPWM0_CH1
BPWM0_CH2
BPWM0_CH3
BPWM0_CH4
BPWM0_CH4
BPWM0_CH5
BPWM0_CH5
BPWM1_CH0
BPWM1_CH1
BPWM1_CH2
BPWM1_CH2
BPWM1_CH3
BPWM1_CH3
BPWM1_CH4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BPWM0
BPWM1
PF.3
PF.0
PF.2
PD.5
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Group
Pin Name
BPWM1_CH5
BPWM1_CH5
CLKO
GPIO
PB.15
PD.4
MFP*
MFP4
MFP4
MFP3
MFP2
MFP4
MFP3
MFP1
MFP3
MFP3
MFP6
MFP6
MFP2
MFP2
MFP6
MFP6
MFP2
MFP2
MFP1
MFP2
MFP3
MFP1
MFP2
MFP3
MFP1
MFP1
MFP1
MFP5
MFP5
MFP1
MFP1
MFP1
MFP1
MFP5
Type
I/O
I/O
O
Description
BPWM1 output/capture input.
BPWM1 output/capture input.
Clock Out.
PA.15
PB.12
PC.12
PC.13
PD.10
PE.0
CLKO
O
Clock Out.
CLKO
O
Clock Out.
CLKO
CLKO
O
Clock Out.
CLKO
O
Clock Out.
CLKO
O
Clock Out.
CLKO
PE.1
O
Clock Out.
I2C0_SCL
I2C0_SCL
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C0_SDA
I2C0_SDA
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SDA
I2C1_SDA
ICE_CLK
ICE_DAT
INT0
PC.12
PE.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I2C0 clock pin.
I2C0 clock pin.
PF.3
I2C0 clock pin.
PF.5
I2C0 clock pin.
I2C0
PC.11
PC.13
PF.2
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C1 clock pin.
PF.4
PA.11
PA.12
PC.2
I2C1 clock pin.
I2C1 clock pin.
I2C1
PA.10
PA.13
PC.3
I2C1 data input/output pin.
I2C1 data input/output pin.
I2C1 data input/output pin.
Serial wired debugger clock pin.
Serial wired debugger data pin.
External interrupt0 input pin.
External interrupt0 input pin.
External interrupt0 input pin.
External interrupt0 input pin.
External interrupt1 input pin.
External interrupt1 input pin.
External interrupt1 input pin.
PWM0 brake input 0.
PF.5
ICE
PF.4
I/O
I
PB.14
PC.12
PC.13
PE.0
INT0
I
INT0
INT0
I
INT0
I
INT1
PB.15
PD.11
PE.2
I
INT1
INT1
I
INT1
I
PWM0
PWM0_BRAKE0
PA.10
I
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Group
Pin Name
GPIO
PA.14
PC.9
PD.9
PA.12
PC.10
PA.13
PC.11
PA.14
PC.12
PA.15
PC.13
PE.0
MFP*
MFP4
MFP5
MFP5
MFP1
MFP4
MFP1
MFP4
MFP1
MFP2
MFP1
MFP2
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP1
MFP3
MFP7
MFP1
Type
I
Description
PWM0_BRAKE0
PWM0_BRAKE1
PWM0_BRAKE1
PWM0_CH0
PWM0_CH0
PWM0_CH1
PWM0_CH1
PWM0_CH2
PWM0_CH2
PWM0_CH3
PWM0_CH3
PWM0_CH3
PWM0_CH3
PWM0_CH4
PWM0_CH4
PWM0_CH5
PWM0_CH5
PWM1_BRAKE0
PWM1_BRAKE1
PWM1_CH0
PWM1_CH0
PWM1_CH1
PWM1_CH1
PWM1_CH2
PWM1_CH2
PWM1_CH3
PWM1_CH3
PWM1_CH4
PWM1_CH5
SPI0_CLK
PWM0 brake input 0.
I
PWM0 brake input 1.
I
PWM0 brake input 1.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM1 brake input 0.
PF.4
PB.9
PC.8
PB.10
PC.9
PC.8
PA.15
PB.0
I
PWM1 brake input 1.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
SPI0 serial clock pin.
PC.0
PB.1
PC.1
PB.2
PWM1
PC.2
PB.3
PC.3
PC.4
PC.5
PC.1
PC.9
PD.1
PC.2
SPI0_CLK
SPI0 serial clock pin.
SPI0
SPI0_CLK
SPI0 serial clock pin.
SPI0_MISO0
SPI0 1st MISO (Master In, Slave Out) pin.
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Group
Pin Name
SPI0_MISO0
SPI0_MISO0
SPI0_MOSI0
SPI0_MOSI0
SPI0_MOSI0
SPI0_SS
SPI0_SS
SPI0_SS
SPI0_SS
SPI0_SS
SPI0_I2SMCLK
SPI0_I2SMCLK
SPI0_I2SMCLK
SPI0_I2SMCLK
SPI0_I2SMCLK
TM0
GPIO
PC.10
PD.2
PC.3
PC.11
PD.3
PB.14
PC.0
PC.8
PD.0
PD.4
PA.15
PB.9
PB.10
PC.4
PC.12
PA.11
PB.8
PB.15
PD.1
PE.2
PB.9
PC.11
PD.3
PF.1
MFP*
MFP3
MFP7
MFP1
MFP3
MFP7
MFP7
MFP1
MFP3
MFP7
MFP7
MFP2
MFP3
MFP3
MFP3
MFP3
MFP5
MFP1
MFP2
MFP4
MFP5
MFP5
MFP1
MFP4
MFP5
MFP5
MFP1
MFP5
MFP2
MFP5
MFP5
MFP4
MFP5
MFP5
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0 slave select pin.
SPI0 slave select pin.
SPI0 slave select pin.
SPI0 slave select pin.
SPI0 slave select pin.
I2S0 master clock output pin.
O
I2S0 master clock output pin.
O
I2S0 master clock output pin.
O
I2S0 master clock output pin.
O
I2S0 master clock output pin.
I/O
I/O
I
Timer0 event counter input / toggle output.
Timer0 event counter input / toggle output.
Timer0 external counter input.
TM0
TM0
TM0_EXT
TM0_EXT
TM0_EXT
TM1
I
Timer0 external counter input.
I
Timer0 external counter input.
I/O
I/O
I
Timer1 event counter input / toggle output.
Timer1 event counter input / toggle output.
Timer1 external counter input.
TM1
TM1
TM1_EXT
TM1_EXT
TM1_EXT
TM2
I
Timer1 external counter input.
PE.3
PB.10
PC.0
PB.2
PB.4
PB.5
PD.2
PE.1
PF.0
I
Timer1 external counter input.
I/O
I/O
I
Timer2 event counter input / toggle output.
Timer2 event counter input / toggle output.
Timer2 external counter input.
TM2
TM2
TM3
TM2_EXT
TM2_EXT
TM3
I
Timer2 external counter input.
I/O
I/O
I/O
I/O
Timer3 event counter input / toggle output.
Timer3 event counter input / toggle output.
Timer3 event counter input / toggle output.
Timer3 event counter input / toggle output.
TM3
TM3
TM3
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Group
Pin Name
GPIO
PB.3
PA12
PB.0
PC.0
PC.4
PD.1
PF.5
PA.13
PB.1
PC.1
PC.5
PD.2
PF.4
PA.14
PB.3
PC.2
PD.3
PA.15
PB.2
PB.14
PC.3
PD.0
PD.4
PC.0
PC.9
PD.1
PB.4
PB.7
PB.12
PC.1
PC.8
PD.0
PD.4
MFP*
MFP2
MFP3
MFP1
MFP6
MFP2
MFP5
MFP3
MFP3
MFP1
MFP6
MFP2
MFP5
MFP3
MFP3
MFP1
MFP6
MFP5
MFP5
MFP1
MFP2
MFP6
MFP5
MFP5
MFP7
MFP7
MFP6
MFP6
MFP7
MFP6
MFP7
MFP7
MFP6
MFP6
Type
I
Description
TM3_EXT
Timer3 external counter input.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
UART0_RXD
UART0_RXD
UART0_RXD
UART0_RXD
UART0_RXD
UART0_RXD
UART0_TXD
UART0_TXD
UART0_TXD
UART0_TXD
UART0_TXD
UART0_TXD
UART0_nCTS
UART0_nCTS
UART0_nCTS
UART0_nCTS
UART0_nRTS
UART0_nRTS
UART0_nRTS
UART0_nRTS
UART0_nRTS
UART0_nRTS
USCI0_CLK
USCI0_CLK
USCI0_CLK
USCI0_CTL0
USCI0_CTL0
USCI0_CTL0
USCI0_CTL0
USCI0_CTL0
USCI0_CTL0
USCI0_CTL0
I
I
I
I
I
I
O
O
O
O
O
O
I
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Clear to Send input pin for UART0.
Clear to Send input pin for UART0.
Clear to Send input pin for UART0.
Clear to Send input pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
USCI0 clock pin.
UART0
I
I
I
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USCI0 clock pin.
USCI0 clock pin.
USCI0 CTL0 pin.
USCI0 CTL0 pin.
USCI0
USCI0 CTL0 pin.
USCI0 CTL0 pin.
USCI0 CTL0 pin.
USCI0 CTL0 pin.
USCI0 CTL0 pin.
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Group
Pin Name
GPIO
PB6
MFP*
MFP7
MFP6
MFP7
MFP7
MFP7
MFP7
MFP6
MFP7
MFP7
MFP7
MFP6
MFP6
MFP7
MFP6
MFP7
MFP6
MFP7
MFP7
MFP7
MFP6
MFP7
MFP1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
USCI0_CTL1
USCI0_CTL1
USCI0_CTL1
USCI0_CTL1
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT0
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
USCI0_DAT1
XT_IN
USCI0 CTL1 pin.
USCI0 CTL1 pin.
USCI0 CTL1 pin.
USCI0 CTL1 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT0 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
USCI0 DAT1 pin.
PB.13
PC.12
PE.2
PA.11
PB4
PB.6
PC.3
PC.5
PC.11
PD.3
PD.8
PE.0
PA.10
PB.5
PB.7
PC.2
PC.4
PC.10
PD.2
PE.1
PF.1
External 4~24 MHz (high speed) or 32.768 kHz
(low speed) crystal input pin.
XT
XT_OUT
PF.0
MFP1
O
External 4~24 MHz (high speed) or 32.768 kHz
(low speed) crystal output pin.
Table 4.3-7 NUC121/125 GPIO Multi-function Table
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5 BLOCK DIAGRAM
5.1 NuMicro® NUC121/125 Block Diagram
Figure 5.1-1 NuMicro® NUC121/125 Block Diagram
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6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The
processor with optional hardware debug functionality can execute Thumb code and is compatible
with other Cortex-M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
an exception return. The Cortex® -M0 is a processor with the same capability as the Cortex® -M0
processor and includes floating point arithmetic functionality. The NuMicro® NUC121/125 series is
embedded with Cortex® -M0 processor. Throughout this document, the name Cortex® -M0 refers to
both Cortex® -M0 and Cortex® -M0 processors. Figure 6.1-1 shows the functional controller of the
processor.
Cortex-M0 components
Cortex-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
interface
Bus Matrix
(DAP)
AHB-Lite
interface
Serial Wire or
JTAG debug port
Figure 6.1-1 Cortex® -M0 Block Diagram
The implemented device provides:
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
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C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
NVIC:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug Support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for
System Reset
Power Modes and Wake-up Sources
System Power Distribution
SRAM Memory Orginization
System Control Register for Part Number ID, Chip Reset and Multi-function Pin
Control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
Hardware Reset Sources
–
–
–
–
–
–
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
CPU Lockup Reset
Software Reset Sources
–
–
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
–
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
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Glitch Filter
32 us
nRESET
~50k ohm
@5v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
Reset Controller
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
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There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex-M0 only; the other reset sources will reset Cortex-M0 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
Register
POR
0x001
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
SYS_RSTSTS
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
0x1
(CLK_APBCLK0[0])
HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
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except bit 1 and bit 7.
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
BL
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
-
Reload
from
CONFIG1
-
-
-
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base on
Reload
base on
Reload
base on
Reload
base on base on
Reload
Reload
base on
CONFIG0
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Other Peripheral
Registers
Reset Value
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 32 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
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nRESET
0.7 VDD
0.2 VDD
32 us
32 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by
writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until
the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by
LVRDGSEL (SYS_BODCTL[14:12]). The LVRF(SYS_RSTSTS[3]) will be set to 1 if the previous
reset source is LVR reset. The default setting of Low Voltage Reset is enabled without De-glitch
function. Figure 6.2-4 shows the Low Voltage Reset waveform.
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AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD which is decided by BOD_EN (BODCR[0])
and BOD_VL (BODCR[2:1]) and the state keeps longer than De-glitch time set by BODDGSEL
(SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the chip in reset state until
the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time set by
BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and
BODRSTEN(SYS_BODCTL[3]) is set by flash controller user configuration register CBODEN
(CONFIG0 [23]), CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can
determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-
Out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives
immediate indication of seriously errant kernel software. This is the result of the CPU being locked
because of an unrecoverable exception following the activation of the processor’s built in system
state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
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signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3
Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-Down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after
system reset released
CPU executes WFI instruction. CPU sets sleep mode enable
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
WDT, I²C, Timer, UART, BOD,
GPIO, EINT, USCI and USBD.
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SCR(SCB[2]) = 1
Wake-up events
occur
2. PD_EN(PWRCTL[7]) = 1 and
PDWTCPU(PWRCTL[8]) = 1
3. CPU executes WFI
Idle Mode
Power-down Mode
CPU Clock OFF
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
Flash Halt
Figure 6.2-6 Power Mode State Machine
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1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If UART clock source is selected as LXT and LXT is on.
Normal Mode
Idle Mode
Power-Down Mode
HXT (4~24 MHz XTL)
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
HIRC (48 MHz OSC)
LXT (32768 Hz XTL)
LIRC (10 kHz OSC)
PLL
ON/OFF1
ON/OFF2
Halt
LDO
ON
CPU
Halt
HCLK/PCLK
SRAM retention
FLASH
Halt
ON
Halt
GPIO
Halt
PDMA
Halt
TIMER
ON/OFF3
Halt
BPWM
PWM
Halt
WDT
ON/OFF4
Halt
WWDT
USCI
Halt
UART
ON/OFF5
Halt
I2C
SPI/I2S
Halt
USBD
Halt
ADC
Halt
Table 6.2-3 Clocks in Power Modes
Wake-up Sources in Power-down Mode:
WDT, I²C, Timer, UART, BOD, GPIO, EINT, USCI and USBD
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
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*User needs to wait this condition before setting PD_EN(PWRCTL[6]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the INTSRC[n] bit.
TIMER
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
WDT Interrupt
RX Data wake-up
nCTS wake-up
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear DATWKIF (UARTx_INTSTS[17]).
After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).
UART
I2C
Falling edge in the I2C_SDA
or I2C_CLK
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
USCI
USBD
Remote Wake-up
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
Table 6.2-4 Condition of Entering Power-down Mode Again
6.2.4
System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB
transceiver.
A dedicated power from VDDIO supplies the power for PA.10, PA.11, PB.4 ~ PB.7,
PB.12 ~ PB.14 and PD.8 ~ 11 of NUC125.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level of the digital power (VDD). Figure 6.2-7 shows the power distribution of the NuMicro®
NUC121 and NUC125.
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USB_D+
USB_D-
USB
Transceiver
IO Cell
Internal
Voltage
12-bit ADC
(Band-gap)
USB_VDD33_CAP
1uF
3.3V
AVDD
AVSS
Brown-out
Detector
Low Voltage
Reset
5V à 3.3V
LDO
USB_VBUS
Temperature
Sensor
SRAM
Flash
Digital Logic
1.8V
LDO_CAP
1uF
10 kHz
IRC
Oscillator
48 MHz IRC
Oscillator
PLL
POR18
XT1_OUT
XT1_IN
Power On
Control
5V à 1.8V
LDO
GPIO except
PA.10, PA.11,
PB.4 ~ PB.7,
PB.12 ~ PB.14
and PD.8 ~ 11
of NUC125
HXT / LXT
POR50
IO Cell
5.0V
NUC121/125 power distribution
Figure 6.2-7 NuMicro® NUC121/125 Power Distribution Diagram
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
Cortex® -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal
high speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-1
shows the clock generator and the overview of the clock source control.
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HIRC/2
111
101
100
011
010
001
000
CPUCLK
CPU
PLL_FOUT/2
48 MHz
(HIRC)
HIRC
GPIO
LIRC
PLLFOUT
LXT
4~24 MHz
(HXT)
1/(HCLKDIV+1)
HCLK
PDMA
32.768 kHz
(LXT)
PCLK 0
USCI
I2C 0
HXT
10 kHz
(LIRC)
CLK_CLKSEL0[2:0]
PCLK 1
I2C 1
HIRC/2
LIRC
111
HIRC/2
101
1
T0~T3
PCLK
PLL FOUT
TMR 0
011
010
HXT
0
TMR 1
TMR 2
TMR 3
LXT
HXT
CLK_PLLCTL[19]
001
000
LIRC
BOD
FMC
HIRC/2
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
HIRC
HIRC/2
1/2
101
111
011
010
001
000
HIRC/2
HCLK
LXT
HCLK
1/2
011
010
001
000
CPUCLK
1
0
Clock Output
HXT
1/2
SysTick
LXT
HXT
HXT
SYST_CTRL[2]
CLK_CLKSEL2[4:2]
CLK_CLKSEL0[5:3]
PCLK 0
PLLFOUT
1
0
HIRC
PCLK 0
11
10
01
00
BPWM 0
PWM 0
SPI
PLLFOUT
CLK_CLKSEL1[28]
CLK_CLKSEL1[30]
HXT
PCLK 1
1
0
BPWM 1
PWM 1
PLLFOUT
CLK_CLKSEL2[25:24]
CLK_CLKSEL1[29]
CLK_CLKSEL1[31]
LIRC
11
10
01
PLLFOUT
HIRC
1
0
HCLK
1/(USBDIV+1)
USB
1/2048
LXT
WDT
CLK_CLKSEL3[8]
CLK_CLKSEL1[1:0]
LXT
HIRC/2
PCLK 0
11
10
11
10
WWDT
PCLK 0
1/2048
1/(ADCDIV+1)
ADC
PLLFOUT
HXT
01
00
CLK_CLKSEL1[31:30]
HIRC/2
11
CLK_CLKSEL1[3:2]
LXT
PLLFOUT
10
01
00
1/(UARTDIV+1)
UART
HXT
CLK_CLKSEL1[25:24]
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2
Clock Generator
The clock generator consists of 5 clock sources, which are listed below:
32.768 kHz external low-speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~24 MHz external high speed crystal (HXT) or 24 MHz (Internal high
speed oscillator, HIRC/2)
48 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable frequency.
When clock source is enabled, a stable counter start counting and correlated clock stable index
(HIRCSTB(CLK_STATUS[4]), LIRCSTB(CLK_STATUS[3]), PLLSTB(CLK_STATUS[2]),
HXTSTB(CLK_STATUS[0]) and LXTSTB(CLK_STATUS[1]) are set to 1 after stable counter value
reach a define value as shown in the following table.
System and peripheral can use the clock as its operating clock only when correlate clock stable index
is set to 1. The clock stable index will auto clear when user disables the clock source
(LIRCEN(CLK_PWRCTL[3]), HIRCEN(CLK_PWRCTL[2]),XTLEN(CLK_PWRCTL[1:0]) and
PD(CLK_PLLCTL[16]). Besides, the clock stable index of HXT, HIRC and PLL will auto clear when
chip enter power-down and clock stable counter will re-counting after chip wake-up if correlate clock is
enabled.
Clock Source
HXT
Clock Stable Count Value
Clock Stable Time
4096 HXT clocks
341.33 uS for 12 Mhz
PLL
It’s based on the value of STBSEL (CLK_PLLCTL[23])
STBSEL = 0, stable count is 6144 PLL clocks.
STBSEL = 0
122.88 uS for 50 Mhz
STBSEL = 1:
STBSEL = 1, stable count is 12288 PLL clocks.(Default)
245.76 uS for 50 Mhz
HIRC
LIRC
LXT
512 HIRC clocks
1 LIRC clock
10.667 uS for 48Mhz
100 uS for 10 kHz
250 mS for 32 KHz
8192 LXT clock
Table 6.3-1 Clock Stable Count Value Table
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XTLEN (CLK_PWRCTL[1:0]) = 10
External 32.768
kHz Crystal
(LXT)
LXT
XTLEN (CLK_PWRCTL[1:0]) = 01
HXT
PF.1
PF.0
External 4~24
MHz Crystal
(HXT)
PLLSRC (CLK_PLLCTL[19])
0
1
PLL FOUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal 48 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN(CLK_PWRCTL[3])
Internal10 KHz
Oscillator
(LIRC)
Figure 6.3-2 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram
is shown in Figure 6.3-3
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC/2
111
PLL_FOUT/2
101
CPUCLK
HIRC
CPU
100
LIRC
HCLK
011
010
001
000
1/(HCLKDIV+1)
AHB
PLLFOUT
HCLKDIV
(CLK_CLKDIV0[3:0])
PCLK0
PCLK1
APB0
APB1
LXT
HXT
CPU in Power Down Mode
L: egend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source if stop and they have
individual enable and interrupt control. When HXT fail detector is enabled, the HIRC clock is
enabled automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock fail detector is enabled, the system clock will auto switch to HIRC/2 (24 MHz) if
HXT clock stop being detected on the following condition: system clock source comes from HXT
or system clock source comes from PLL with HXT as the input of PLL. If HXT clock stop condition
is detected, the HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE
(CLK_CLKDCTL[5]) is set to 1. User can trying to recover HXT by disable HXT and enable HXT
again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means
HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC/2 (24 MHz) procedure is shown in
Figure 6.3-4
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC/2 (24 MHz)
Figure 6.3-4 HXT Stop Protect Procedure
Except HXT fail(stop) detector, HXT also has a frequency detector to observe HXT clock frequncy
if normally and it also has individual enable(HXTFQDEN=CLK_CLKDCTL[16]) and interrupt
control (HXTFQIEN=CLK_CLKDCTL[17]). When HXT frequency detector is enabled, the HIRC
clock is enabled automatically. Otherwise, before HXT frequency detector is enabled, we need set
the frequency detector upper boundary(UPERBD=CLK_CDUPB[9:0]) and lower boundary
(LOWERBD=CLK_CDLOWB[9:0]).
If HXT clock frequency abnormally condition is detected, the HXTFQIF(CLK_CLKDSTS[8]) is set
to 1 and chip will enter interrupt if HXTFQIEN (CLK_CLKDCTL[17]) is set to 1. Different with HXT
fail(stop) detector, when HXT clock frequency abnormally condition is detected, the system clock
will NOT auto switch to HIRC/2 (24 MHz) even though system clock source comes from HXT or
system clock source comes from PLL with HXT as the input of PLL. The HXT frequency detector
just reminds user HXT clock frequency abnormally through to observe HXTFQIF
(CLK_CLKDSTS[8]).
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in Figure 6.3-5
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STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC/2
HCLK
HXT
111
011
010
001
000
1/2
1/2
1/2
STCLK
LXT
HXT
:Legend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4
Peripherals Clock
The peripherals clock had different clock source switch setting, which depends on the different
peripheral.
6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources, and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
10 kHz internal low-speed RC oscillator (LIRC) clock
32.768 kHz external low-speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
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CLKOSEL (CLK_CLKSEL2[4:2])
CLKOCKEN (CLK_APBCLK0[6])
HIRC
HIRC/2
HCLK
101
011
010
001
000
CLKO_CLK
LXT
HXT
:Legend
HXT = 4 MHz ~ 24 MHz High Speed External clock signal
LXT = 32.768 kHz Low Speed External clock signal
HIRC = 48 MHz High Speed Internal clock signal
LIRC = 10 kHz Low Speed Internal clock signal
Figure 6.3-6 Clock Source of Clock Output
CLKOEN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
16 chained
divide-by-2 counter
CLKO_CLK
1/22 1/23
1/215 1/216
…...
1/2
0000
0001
CLKO
16 to 1
MUX
:
:
1110
1111
FREQSEL
(CLK_CLKOCTL[3:0])
Figure 6.3-7 Clock Output Block Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NUC121/125 series is equipped with 32 K-bytes on-chip embedded flash for application and
Data Flash to store some application dependent data. A User Configuration block provides for
system initialization. A 4.5 K-bytes loader ROM (LDROM) is used for In-System-Programming
(ISP) function. A 512 bytes security protection ROM (SPROM) can conceal user program. This
chip also supports In-Application-Programming (IAP) function, user switches the code executing
without the chip reset after the embedded flash updated.
6.4.2
Features
Supports 32 K-bytes application ROM (APROM).
Supports 4.5 K-bytes loader ROM (LDROM).
Supports configurable Data Flash size to share with APROM.
Supports 512 bytes security protection ROM (SPROM) to conceal user program.
Supports 12 bytes User Configuration block to control system initialization.
Supports 512 bytes page erase for all embedded flash.
Supports CRC-32 checksum calculation function (must be 512 bytes page alignment).
Supports APROM, LDROM and embedded SRAM remap to system vector memory.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
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6.5 General Purpose I/O (GPIO)
6.5.1 Overview
The NUC121/125 series has up to 52 General Purpose I/O pins to be shared with other function
pins depending on the chip configuration. These 52 pins are arranged in 6 ports named as PA,
PB, PC, PD, PE and PF.
PA has 6 pins on port (PA.10 ~ PA.15).
PB has 15 pins on port (PB.0 ~ PB.15, exclude PB.11).
PC has 12 pins on port (PC.0 ~ PC.13, exclude PC.6, PC.7).
PD has 10 pins on port (PD.0 ~ PD.11, exclude PD.6, PD.7).
PE has 3 pins on port (PE.0 ~ PE.2).
PF has 6 pins on port (PF.0 ~ PF.5).
Each of the 52 pins is independent and has the corresponding register bits to control the pin
mode function and data
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
6.5.2
Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Slew Rate I/O mode
Supports High Drive Strength mode for Port C
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in input mode after chip reset
CIOIN = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
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6.6 PDMA Controller (PDMA)
6.6.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data
transfer. The PDMA controller can transfer data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controller has a total of 5 channels and each channel can
perform transfer between memory and peripherals or between memory and memory. The PDMA
supports time-out function for channel 0 and channel 1.
6.6.2
Features
Supports 5 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or no
increment
Supports software and SPI, UART, I2S, I2C, USCI, ADC, PWM and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function for channel 0 and channel 1
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6.7 Timer Controller (TMR)
6.7.1 Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.7.2
Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM,
BPWM, PDMA, ADC and DAC function
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6.8 Basic PWM Generator and Capture Timer (BPWM)
6.8.1 Overview
The NUC121/125 series provides two BPWM generators: BPWM0 and BPWM1. Each BPWM
supports 6 channels of BPWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit BPWM counter with 16-bit comparator. The BPWM counter supports
up, down and up-down counter types, all 6 channels share one counter. BPWM uses the
comparator compared with counter to generate events. These events are used to generate
BPWM pulse, interrupt and trigger signal for ADC to start conversion. For BPWM output control
unit, it supports polarity output, independent pin mask and tri-state output enable.
The BPWM generator also supports input capture function to latch BPWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.8.2
Features
6.8.2.1 BPWM function features
Supports maximum clock frequency up to100 MHz
Supports up to two BPWM modules, each module provides 6 output channels
Supports independent mode for BPWM output/Capture input channel
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution BPWM counter, each module provides 1 BPWM counter
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each BPWM pin
Supports interrupt on the following events:
BPWM counter match zero, period value or compared value
Supports trigger ADC on the following events:
BPWM counter match zero, period value or compared value
6.8.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising edge or falling edge or both edges capture condition
Supports input rising/falling edge or both edges capture interrupt
Supports rising/falling or both edges capture with counter reload option
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6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The NUC121/125 series provides two PWM generators － PWM0 and PWM1. Each PWM
supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up,
down and up-down counter types. PWM uses the comparator compared with counter to generate
events. These events are used to generate PWM pulse, interrupt and trigger signal for ADC to
start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, which have difference architecture. In Complementary mode, there are
two comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM
output control unit, it supports polarity output, independent pin mask, tri-state output enable and
brake functions.
The PWM generator also supports input capture function to latch PWM counter value to the
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.9.2
Features
6.9.2.1 PWM function features
Supports maximum clock frequency up to100 MHz
Supports up to two PWM modules, each module provides 6 output channels
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter, each module provides 3 PWM counters
Up, down and up/down counter operation type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events (clock failed, Brown-out detection
and CPU lockup)
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger ADC on the following events:
PWM counter match zero, period value or compared value
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6.9.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for WDT time-out interval.
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63.
Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset
delay period.
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in
Config0 register.
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
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6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified
window period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter value CNTDAT(WWDT_CNT[5:0]) and maximum 6-bit compare value
CMPDAT(WWDT_CTL[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value PSCSEL(WWDT_CTL[11:8]) to programmable maximum 11-bit
prescale counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
WWDT counter only can be reloaded within in valid window period to prevent system reset
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6.12 USCI - Universal Serial Control Interface Controller
6.12.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.12.2 Features
The controller can be individually configured to match the application needs. The following
protocols are supported:
UART
SPI
I2C
To increase readability, the registers of USCI have different alias names that depending on the
selected protocol. For example, register USCI_CTL has alias name UUART_CTL for protocol
UART, has alias name USPI_CTL for protocol SPI, and has alias name UI2C_CTL for protocol
I2C.
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6.13 USCI - UART Mode
6.13.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of
asynchronous data frames. It performs a serial-to-parallel conversion on data received from the
peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver
and transmitter are independent, frames can start at different points in time for transmission and
reception.
The UART controller also provides auto flow control. There are two conditions to wake-up the
system by incoming data or nCTS.
6.13.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Supports 9-Bit Data Transfer (9-Bit RS-485)
Supports baud rate detection by built-in capture event of baud rate generator
Supports PDMA capability
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.14 USCI - SPI Mode
6.14.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows
full duplex transfer. It supports both master and slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received
from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral
device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1
This SPI protocol can operate as master or slave mode by setting the SLAVE
(USPI_PROTCTL[0]) to communicate with the off-chip SPI slave or master device. The
application block diagrams in master and slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0
Figure 6.14-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0
Figure 6.14-2 SPI Slave Mode Application Block Diagram
6.14.2 Features
Supports master or slave mode operation (the maximum frequency for Master = fPCLK / 2, for
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
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Supports one transmit buffer and two receive buffers for data payload
Supports MSB first or LSB first transfer sequence
Supports word suspend function
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
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6.15 USCI - I2C Mode
6.15.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6.15-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
tBUF
(USCI_DAT0)
tLOW
tr
tf
SCL
tHIGH
(USCI_CLK)
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.15-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100b. When enable this port, the USCI interfaces to the I2C bus
via two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function
to I2C in advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-
drain pins when USCI is selected to I2C operation mode .
6.15.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
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6.16 UART Interface Controller (UART)
6.16.1 Overview
The NUC121/125 series provides one channel of Universal Asynchronous Receiver/Transmitters
(UART). UART controller performs Normal Speed UART and supports flow control function. The
UART controller performs a serial-to-parallel conversion on data received from the peripheral and
a parallel-to-serial conversion on data transmitted from the CPU. Each UART controller channel
supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN and RS-485
function modes and auto-baud rate measuring function.
6.16.2 Features
Full-duplex asynchronous communications
Supports maximum clock frequency up to 10 Mbps
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
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6.17 I2C Serial Interface Controller (I2C)
6.17.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.17.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Supports speed up to 1Mbps
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-
out counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports two-level buffer function
Supports setup/hold time programmable
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6.18 Serial Peripheral Interface (SPI)
6.18.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NUC121/125 series contains one SPI controller performing a serial-to-
parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion
on data transmitted to a peripheral device. The SPI controller can be configured as a master or a
slave device.
This controller also supports the PDMA function to access the data buffer. The SPI controller also
supports I2S mode to connect external audio CODEC.
6.18.2 Features
SPI Mode
One set of SPI controller
Supports Master or Slave mode operation
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports PDMA transfer
Supports one data channel half-duplex transfer
Support receive-only mode
I2S Mode
Supports Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Provides separate 4-level depth transmit and receive FIFO buffers
Supports monaural and stereo audio data
Supports PCM mode A, PCM mode B, I2S and MSB justified data format
Supports PDMA transfer
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6.19 USB Device Controller (USBD)
6.19.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports
control/bulk/interrupt/isochronous transfer types. It implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 768 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGn, n=0~7).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are five different interrupt events in this controller. They are the SOF event, no-event-wake-
up, device plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events,
like suspend and resume, etc. Any event will cause an interrupt, and users just need to check the
related event flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of
interrupt occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB
controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.
After disable the SE0 bit, host will enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
6.19.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 5 different interrupt events (NEVWK, VBUSDET, USB, BUS
and SOF)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and
maximum 768 bytes buffer size
Provides remote wake-up capability
Start of Frame (SOF) locked clock pulse generation
Supports USB 2.0 Link Power Management
Aug. 17, 2018
Page 117 of 148
Rev 1.02
NUC121/125
6.20 Analog-to-Digital Converter (ADC)
6.20.1 Overview
The NUC121/125 series contains one 12-bit successive approximation analog-to-digital converter
(SAR A/D converter) with 14 input channels. The A/D converter supports four operation modes:
Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D converter can be started
by software, external pin (STADC/PC.8), timer0~3 overflow pulse trigger and PWM trigger.
6.20.2 Features
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed
Up to 12 single-end analog input channels or 6 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Up to 800k SPS sampling rate
Configurable ADC internal sampling time
Four operation modes:
Single mode: A/D conversion is performed one time on a specified channel.
Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
Continuous Scan mode: A/D converter continuously performs Single-cycle Scan
mode until software stops A/D conversion.
An A/D conversion can be started by:
Software Write 1 to ADST bit
External pin (STADC)
Timer 0~3 overflow pulse trigger
PWM trigger with optional start delay period
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
Two internal channels which are band-gap voltage (VBG) and temperature sensor (VTEMP).
Supports PDMA transfer mode.
Note 1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note 2: If the internal channel (VTEMP) is selected to convert, the sampling rate needs to be less
than 300k SPS for accurate result.
Aug. 17, 2018
Page 118 of 148
Rev 1.02
NUC121/125
7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
AVDD
CS
CLK
MISO
MOSI
VDD
SPIx_SS
SPIx_CLK
SPIx_MISO
SPIx_MOSI
SPI Device
FB
DVCC
VDD
VSS
Power
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
FB
AVSS
4.7K
CLK
DIO
I2Cx_SCL
I2Cx_SDA
VDD
I2C Device
VDD
VSS
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
NUC121
Series
PC COM Port
RS232 Transceiver
ROUT RIN
DVCC
UARTx_RXD
UARTx_TXD
UART
TIN
TOUT
10K
Reset
Circuit
nRESET
10uF/25V
USB_VBUS
USB_D-
33
33
USB_D+
USB_ID
USB FS Device
USB_VDD33_CAP
1uF
LDO
LDO_CAP
1uF
Note: For the SPI device, the chip supply voltage
must be equal to SPI device working voltage. For
example, when the SPI Flash working voltage is
3.3 V, the NUC121 chip supply voltage must also
be 3.3V.
Aug. 17, 2018
Page 119 of 148
Rev 1.02
NUC121/125
DVCC1
[1]
AVCC
AVDD
VDD
CS
CLK
MISO
MOSI
VDD
SPIx_SS
SPIx_CLK
SPIx_MISO
SPIx_MOSI
SPI Device
FB
FB
DVCC1
VSS
0.1uF
0.1uF
VSS
DVCC2
4.7K
DVCC2
AVSS
Power
4.7K
CLK
DIO
I2Cx_SCL
I2Cx_SDA
VDD
I2C Device
[2]
VDDIO
DVCC2
VSS
VDD
NUC125
Series
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
PC COM Port
Interface
RS232 Transceiver
ROUT RIN
UARTx_RXD
UARTx_TXD
DVCC
UART
TIN
TOUT
10K
Reset
Circuit
USB_VBUS
USB_D-
USB_D+
33
33
nRESET
USB FS Device
10uF/25V
USB_ID
USB_VDD33_CAP
1uF
LDO
LDO_CAP
1uF
Note1: For the SPI device, the chip supply
voltage must be equal to SPI device working
voltage if SPIx_SS, SPIx_CLK, SPIx_MISO and
SPIx_MOSI are not in VDDIO domain. For
example, when the SPI Flash working voltage is
3.3 V, the NUC125 chip supply voltage must also
be 3.3V.
Note2: DVCC2 can be 1.8V ~ 5.5V.
Aug. 17, 2018
Page 120 of 148
Rev 1.02
NUC121/125
8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
PARAMETER
MIN
MAX
+7.0
VDD + 0.3
+5.5
24
UNIT
V
VDD-VSS
VIN
-0.3
Input Voltage
VSS – 0.3
V
Input Voltage on VDDIO
VDDIO
1/tCLCL
TA
+1.8
V
Oscillator Frequency
4
MHz
C
Operating Temperature
-40
+105
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
Maximum Current Sunk by Total I/O Pins
Maximum Current Sourced by Total I/O Pins
IDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
120
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the
device.
Aug. 17, 2018
Page 121 of 148
Rev 1.02
NUC121/125
8.2 DC Electrical Characteristics
(VDD-VSS = 2.5 ~ 5.5V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD
VSS
-
Operation Voltage
2.5
1.8
-
-
5.5
5.5
V
V
VDD = 2.5 ~ 5.5V up to 50 MHz
Power supply for
PB.14, PA.11, PA.10,
PB.4 and PB.5
VDDIO
VSS
-
VSS
AVSS
-
Power Ground
-0.05
1.62
-
+0.05
1.98
V
V
MCU operating in Run, Idle or Power-down
mode
VLDO
1.8
LDO Output Voltage
Band-gap Voltage
CLDO
VBG
1
-
-
1
-
uF Connect to LDO_CAP pin
1.21
V
V
VDD = 2.5 V ~ 5.5 V, TA = -40 ~ 105C
Allowed voltage
difference for VDD and
AVDD
VDD
-
-0.3
-
-
+0.3
-
AVDD
All digital
module
VDD
HXT
HIRC
X
PLL
V
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}executed
from flash
IDD1
20.4
mA
5.5 V
12 MHz
V
X
V
X
IDD2
IDD3
IDD4
-
-
-
9.5
20.0
9.3
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
X
X
X
V
V
V
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}executed
from flash
IDD5
-
24.6
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48 MHz
48 MHz
48 MHz
48 MHz
V
V
V
V
V
X
V
X
IDD6
IDD7
IDD8
-
-
-
11.5
24.1
11.4
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
mA
VDD
HXT
HIRC
PLL
V
Operating Current
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
IDD9
-
20.0
-
mA
mA
mA
mA
5.5 V
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
X
V
X
IDD10
IDD11
IDD12
-
-
-
9.1
19.5
8.8
-
-
-
V
V
VLDO=1.8 V
V
All digital
module
IDD13
-
20.0
-
mA
VDD
HXT
HIRC
PLL
Operating Current
Aug. 17, 2018
Page 122 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48 MHz
48 MHz
48 MHz
48 MHz
X
X
X
X
V
X
V
X
IDD14
IDD15
IDD16
-
-
-
8.5
19.5
8.4
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
IDD17
-
9.7
-
mA
5.5 V
24 MHz
V
X
V
X
IDD18
IDD19
IDD20
-
-
-
4.4
9.5
4.2
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
24 MHz
24 MHz
24 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
PLL
X
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
IDD21
-
11.1
-
mA
5.5 V
48/2 MHz
V
X
V
X
IDD22
IDD23
IDD24
-
-
-
5.2
10.9
5.1
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
X
X
X
48/2 MHz
48/2 MHz
48/2 MHz
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD25
-
6.4
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
16 MHz
16 MHz
16 MHz
16 MHz
X
X
X
X
X
X
X
X
V
X
V
X
IDD26
IDD27
IDD28
-
-
-
3.1
6.3
3.0
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
IDD29
-
8.3
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48/3 MHz
48/3 MHz
48/3 MHz
48/3 MHz
X
X
X
X
V
X
V
X
IDD30
IDD31
IDD32
-
-
-
4.2
8.1
4.1
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD33
-
4.9
-
mA
5.5 V
12 MHz
V
X
V
X
IDD34
IDD35
IDD36
-
-
-
2.2
4.7
2.1
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
Operating Current
Normal Run Mode
HCLK =12 MHz
VDD
HXT
X
HIRC
PLL
X
IDD37
-
6.8
-
mA
5.5 V
48/4 MHz
V
Aug. 17, 2018
Page 123 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
while(1){}executed
from flash
IDD38
IDD39
IDD40
-
-
-
3.7
6.6
3.6
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
X
X
X
48/4 MHz
48/4 MHz
48/4 MHz
X
X
X
X
V
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
IDD41
-
1.8
-
mA
5.5 V
4 MHz
V
X
V
X
IDD42
IDD43
IDD44
-
-
-
0.9
1.7
0.8
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
IDD45
-
3.9
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48/12 MHz
48/12 MHz
48/12 MHz
48/12 MHz
X
X
X
X
V
X
V
X
IDD46
IDD47
IDD48
-
-
-
2.5
3.9
2.5
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
Operating Current
Normal Run Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IDD49
-
120
-
uA
5.5 V 32.768 kHz
5.5 V 32.768 kHz
3.0 V 32.768 kHz
3.0 V 32.768 kHz
V
X
V
X
IDD50
IDD51
IDD52
-
-
-
113
105
98
-
-
-
uA
uA
uA
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
LXT
X
LIRC
PLL
X
Operating Current
Normal Run Mode
HCLK =10 kHz
while(1){}executed
from flash
IDD53
-
111
-
uA
5.5 V
10 kHz
V
X
V
X
IDD54
IDD55
IDD56
-
-
-
109
96
-
-
-
uA
uA
uA
5.5 V
3.0 V
3.0 V
X
X
X
10 kHz
10 kHz
10 kHz
X
X
X
VLDO=1.8 V
94
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Idle Mode
HCLK =50 MHz
while(1){}executed
from flash
IIDLE1
-
15.2
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
-
-
-
4.4
14.9
4.3
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =50 MHz
VDD
HXT
X
HIRC
PLL
V
IIDLE5
-
19.3
-
mA
5.5 V
48 MHz
V
Aug. 17, 2018
Page 124 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
while(1){}executed
from flash
IIDLE6
IIDLE7
IIDLE8
-
-
-
6.8
19.1
6.8
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
X
X
X
48 MHz
48 MHz
48 MHz
V
V
V
X
V
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
V
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
IIDLE9
-
14.7
-
mA
5.5 V
12 MHz
V
X
V
X
IIDLE10
IIDLE11
IIDLE12
-
-
-
4.3
14.3
4.1
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
X
X
X
V
V
V
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
PLL
X
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
IIDLE13
-
14.5
-
mA
5.5 V
48 MHz
V
X
V
X
IIDLE14
IIDLE15
IIDLE16
-
-
-
3.7
14.2
3.6
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
X
X
X
48 MHz
48 MHz
48 MHz
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Idle Mode
HCLK =24 MHz
while(1){}executed
from flash
IIDLE17
-
7.2
-
mA
5.5 V
24 MHz
V
X
V
X
IIDLE18
IIDLE19
IIDLE20
-
-
-
2.0
7.0
1.8
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
24 MHz
24 MHz
24 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
PLL
X
Operating Current
Idle Mode
HCLK =24 MHz
while(1){}executed
from flash
IIDLE21
-
8.3
-
mA
5.5 V
48/2 MHz
V
X
V
X
IIDLE22
IIDLE23
IIDLE24
-
-
-
2.8
8.1
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
X
X
X
48/2 MHz
48/2 MHz
48/2 MHz
X
X
X
VLDO=1.8 V
2.75
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Idle Mode
HCLK =16 MHz
while(1){}executed
from flash
IIDLE25
-
4.7
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
16 MHz
16 MHz
16 MHz
16 MHz
X
X
X
X
X
X
X
X
V
X
V
X
IIDLE26
IIDLE27
IIDLE28
-
-
-
1.3
4.6
1.2
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =16 MHz
while(1){}executed
from flash
VDD
HXT
HIRC
PLL
IIDLE29
-
-
6.3
2.6
-
-
mA
mA
5.5 V
5.5 V
X
X
48/3 MHz
48/3 MHz
X
X
V
X
IIDLE30
Aug. 17, 2018
Page 125 of 148
Rev 1.02
NUC121/125
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.8 V
IIDLE31
IIDLE32
-
-
6.1
2.5
-
-
mA
mA
3.0 V
3.0 V
X
X
48/3 MHz
48/3 MHz
X
X
V
X
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Idle Mode
HCLK =12 MHz
while(1){}executed
from flash
IIDLE33
-
3.6
-
mA
5.5 V
12 MHz
V
X
V
X
IIDLE34
IIDLE35
IIDLE36
-
-
-
1.0
3.5
0.9
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Idle Mode
HCLK =12 MHz
while(1){}executed
from flash
IIDLE37
-
5.2
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48/4 MHz
48/4 MHz
48/4 MHz
48/4 MHz
X
X
X
X
V
X
V
X
IIDLE38
IIDLE39
IIDLE40
-
-
-
2.4
5.1
2.4
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
PLL
X
Operating Current
Idle Mode
HCLK =4 MHz
while(1){}executed
from flash
IIDLE41
-
1.35
-
mA
5.5 V
4 MHz
V
X
V
X
IIDLE42
IIDLE43
IIDLE44
-
-
-
0.48
1.28
0.43
-
-
-
mA
mA
mA
5.5 V
3.0 V
3.0 V
4 MHz
4 MHz
4 MHz
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Idle Mode
HCLK =4 MHz
while(1){}executed
from flash
IIDLE45
-
3.2
-
mA
5.5 V
5.5 V
3.0 V
3.0 V
X
X
X
X
48/12 MHz
48/12 MHz
48/12 MHz
48/12 MHz
X
X
X
X
V
X
V
X
IIDLE46
IIDLE47
IIDLE48
-
-
-
2.2
3.1
2.1
-
-
-
mA
mA
mA
VLDO=1.8 V
All digital
module
VDD
LXT
LIRC
X
PLL
X
Operating Current
Idle Mode
HCLK =32.768 kHz
while(1){}executed
from flash
IIDLE49
-
116
-
uA
5.5 V 32.768 kHz
5.5 V 32.768 kHz
3.0 V 32.768 kHz
3.0 V 32.768 kHz
V
X
V
X
IIDLE50
IIDLE51
IIDLE52
-
-
-
110
101
95
-
-
-
uA
uA
uA
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =10 kHz
while(1){}executed
from flash
VDD
LXT
X
LIRC
PLL
X
IIDLE53
-
109
-
uA
5.5 V
10 kHz
V
X
V
IIDLE54
IIDLE55
-
-
107
95
-
-
uA
uA
5.5 V
3.0 V
X
X
10 kHz
10 kHz
X
X
VLDO=1.8 V
Aug. 17, 2018
Page 126 of 148
Rev 1.02
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SPECIFICATIONS
PARAMETER
SYM.
IIDLE56
IPWD1
TEST CONDITIONS
MIN. TYP. MAX. UNIT
-
93
-
uA
3.0 V
X
10 kHz
X
X
RAM
retention
VDD HXT/HIRC LXT/LIRC
PLL
X
-
6.7
-
uA
5.5 V
5.5 V
5.5 V
5.5 V
3.0 V
3.0 V
3.0 V
3.0 V
X
X
X
X
X
X
X
X
LXT
LIRC
V
V
V
V
V
V
V
V
IPWD2
IPWD3
IPWD4
IPWD5
IPWD6
IPWD7
IPWD8
-
-
-
-
-
-
-
6.8
7.4
6.1
5.7
5.8
6.3
5.1
-
-
uA
uA
uA
uA
uA
uA
uA
X
X
X
X
X
X
X
LXT & LIRC
X
Standby Current
Power-down Mode
VLDO=1.8 V
-
-
-
-
LXT
LIRC
LXT & LIRC
X
Input Current at
nRESET[1]
IIN
uA
VDD = 3.3V, VIN = 0.45V
-
-
TBD
-68
-
-
Logic 0 Input Current
(Quasi-bidirectional
mode)
IIL
uA
uA
VDD = VDDIO = 5.5V, VIN = 0V
VDD = VDDIO = 5.5V, VIN = 2.0V
Logic 1 to 0 Transition
Current (Quasi-
ITL
-
-600
-
bidirectional mode) [3]
KΩ
KΩ
KΩ
VDD = VDDIO = 5.5V
VDD = VDDIO = 3.3V
VDD = VDDIO = 1.8V
-
-
-
79
-
-
-
Input Pull Up Resistor
Input Leakage Current
RIN
143
428
VDD = VDDIO = 5.5V, 0 < VIN < VDD
Open-drain or input only mode
ILK
-
0
-
A
V
V
-0.3
-0.3
-
-
0.8
0.6
VDD = VDDIO = 4.5 V
VDD = VDDIO = 2.5 V
Input Low Voltage
(TTL input)
VIL1
Input Low Voltage
(TTL input for VDDIO
domain)
VDD = 2.5 ~ 5.5 V
VDDIO = 1.8 V
VIL2
V
-
0.58
-
VDD
0.3
+
V
V
VDD = VDDIO = 5.5V
VDD = VDDIO = 2.5V
2.0
1.5
-
-
Input High Voltage
(TTL input)
VIH1
VDD
0.3
+
Aug. 17, 2018
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Rev 1.02
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Input High Voltage
(TTL input for VDDIO
domain)
VDD = 2.5 ~ 5.5 V
VDDIO = 1.8 V
VIH2
VIL3
VIL4
V
V
V
-
0.64
-
Input Low Voltage
(Schmitt input)
VDD = VDDIO = 2.5 ~ 5.5 V
VDDIO = 1.8 ~ 5.5V
-0.3
-0.3
-
-
0.3VDD
0.3VDD
Input Low Voltage
(Schmitt input for VDDIO
domain)
VDD
0.3
+
Input High Voltage
(Schmitt input)
VIH3
VIH4
VHY
V
V
V
VDD = VDDIO = 2.5 ~ 5.5V
VDDIO = 1.8 ~ 5.5V
0.7VDD
0.7VDDIO
-
-
Input Low Voltage
VDDIO
0.3
+
-
(Schmitt input for VDDIO
domain)
Hysteresis voltage of
PA~PF (Schmitt input)
0.2VDD
-
Negative going
threshold
VIL5
V
-0.3
-
0.2VDD
(Schmitt input),
nRESET
Positive going
threshold
VDD
0.3
+
VIH5
V
0.8VDD
-
(Schmitt Input),
nRESET
Internal nRESET pin
pull up resistor
RRST
KΩ
-
17
-
ISR1
ISR2
ISR3
uA
uA
uA
VDD = VDDIO = 4.5V, VS = 2.4V
VDD = VDDIO = 2.7V, VS = 2.2V
VDD = VDDIO = 2.5V, VS = 2.0V
-
-
-
-390
-78
-
-
-
Source Current
(Quasi-bidirectional
Mode)
-71
Source Current
VDD = 2.5 ~ 5.5V
(Quasi-bidirectional
Mode for VDDIO
domain)
ISR4
uA
-
21.2
-
VDDIO = 1.8V, VS = 1.6V
ISR5
ISR6
ISR7
mA
mA
mA
VDD = VDDIO = 4.5V, VS = 2.4V
VDD = VDDIO = 2.7V, VS = 2.2V
VDD = VDDIO = 2.5V, VS = 2.0V
-
-
-
-25
-5
Source Current
-
-
(Push-pull Mode)
-4
Source Current
VDD = 2.5 ~ 5.5V
ISR8
mA
-
1.51
-
(Push-pull Mode for
VDDIO domain)
VDDIO = 1.8V, VS = 1.6V
Sink Current
ISK1
ISK2
mA
mA
VDD = VDDIO = 4.5V, VS = 0.45V
VDD = VDDIO = 2.7V, VS = 0.45V
-
-
15
10
-
-
(Quasi-bidirectional,
Open-Drain and Push-
Aug. 17, 2018
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Rev 1.02
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pull Mode)
ISK3
mA
mA
VDD = VDDIO = 2.5V, VS = 0.45V
-
-
9
-
-
Sink Current
VDD = 2.5 ~ 5.5V
(Quasi-bidirectional,
Open-Drain and Push-
pull Mode for VDDIO
domain)
ISK4
6.51
VDDIO = 1.8V, VS = 1.6V
Higher GPIO Rising
Rate
HIORR1
BIORR1
HIORR2
BIORR2
ns
ns
ns
ns
VDD = VDDIO = 5.5V, without capacitor
VDD = VDDIO = 5.5V, without capacitor
VDD = VDDIO = 3.3V, without capacitor
VDD = VDDIO = 3.3V, without capacitor
-
-
-
-
1.76
3.12
3.73
5.97
-
-
-
-
Basic GPIO Rising
Rate
Higher GPIO Rising
Rate
Basic GPIO Rising
Rate
Higher GPIO Rising
Rate
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
HIORR3
BIORR3
ns
ns
-
-
25
27
-
-
(for VDDIO domain)
Basic GPIO Rising
Rate
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
(for VDDIO domain)
Higher GPIO Falling
Rate
HIOFR1
BIOFR1
HIOFR2
BIOFR2
ns
ns
ns
ns
VDD = VDDIO = 5.5V, without capacitor
VDD = VDDIO = 5.5V, without capacitor
VDD = VDDIO = 3.3V, without capacitor
VDD = VDDIO = 3.3V, without capacitor
-
-
-
-
1.53
3.02
2.84
6.08
-
-
-
-
Basic GPIO Falling
Rate
Higher GPIO Falling
Rate
Basic GPIO Falling
Rate
Higher GPIO Falling
Rate
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
HIOFR3
BIOFR3
ns
ns
-
-
8.69
-
-
(for VDDIO domain)
Basic GPIO Falling
Rate
VDD = 2.5 ~ 5.5V, VDDIO = 1.8V, without
capacitor
20.28
(for VDDIO domain)
Note:
1. nRESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. All pins can source a transition current when they are externally driven from 1 to 0. In the condition of VDD = 5.5V, the
transition current reaches its maximum value when VIN approximates to 2V.
4. For ensuring power stability, a 1uF must be connected between LDO pin and the closest VSS pin of the device. Also
a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
Aug. 17, 2018
Page 129 of 148
Rev 1.02
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8.3 AC Electrical Characteristics
8.3.1 External 4~24 MHz High Speed Crystal (HXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
tCLCH
tCHCL
VIH
nS
nS
nS
nS
V
10
-
-
-
-
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
Input High Voltage
Input Low Voltage
10
2
15
2
0.7VDD
0
15
VDD
0.3VDD
VIL
V
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.3.2 External 4~24 MHz High Speed Crystal (HXT) Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Oscillator frequency
Temperature
fHXT
4
-40
-
-
24
MHz
C
VDD = 2.5 ~ 5.5V
THXT
-
+105
0.74
0.61
-
-
mA
mA
VDD = 5.5V @ 12MHz
VDD = 3.3V @ 12MHz
Operating current
IHXT
-
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
20pF
R1
4MHz ~ 24 MHz
20pF
without
Aug. 17, 2018
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XT_OUT
XT_IN
R1
C1
C2
Figure 8.3-1 Typical Crystal Application Circuit
8.3.3 External 32.768 kHz Low Speed Crystal (LXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
nS
nS
nS
nS
TBD
TBD
TBD
TBD
-
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
-
tCLCH
TBD
TBD
tCHCL
LXT Input Pin Input High
Voltage
Xin_VIH
V
V
0.7VDD
0
-
-
VDD
LXT Input Pin Input Low
Voltage
Xin_VIL
0.3VDD
tCLCL
tCLCH
tCLCX
90%
10%
Xin_VIH
Xin_VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.3.4 External 32.768 kHz Low Speed Crystal (LXT) Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
Aug. 17, 2018
Page 131 of 148
Rev 1.02
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SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Oscillator frequency
Temperature
fLXT
-
32.768
-
-
kHz
VDD = 2.5 ~ 5.5V
TLXT
-40
+105 C
A
1.15
0.58
VDD = 5.5V
VDD = 3.3V
Operating current
ILXT
-
-
A
8.3.4.1 Typical Crystal Application Circuits
CRYSTAL
C3
20pF
C4
R2
32.768 kHz
20pF
without
XT_OUT
XT_IN
R2
C3
C4
Figure 8.3-2 Typical Crystal Application Circuit
8.3.4.2 Internal 48 MHz High Speed RC Oscillator (HIRC)
SPECIFICATIONS
PARAMETER
Supply voltage[1]
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
VHRC 1.62
-
1.8
48
1.98
-
V
Center Frequency
MHz
TA = 25C, VDD = 3.3V
-40C ~ +105C,
-2
-
+2
%
%
VDD = 2.5 ~ 5.5V
-40C ~ +105 C,
fHRC
Calibrated Internal
VDD = 2.5 ~ 5.5V
Oscillator Frequency
Enable 32.768K crystal
oscillator or internal USB
synchronous mode, and set
SYS_IRCTCTL[1:0]=”10”
-0.25
-
+0.25
Aug. 17, 2018
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Rev 1.02
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SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
-
-
431
430
-
-
VDD = 5.5 V
VDD = 3.3 V
A
A
Operating current
IHRC
8.3.4.3 Internal 10 kHz Low Speed RC Oscillator (LIRC)
SPECIFICATIONS
PARAMETER
Supply voltage[1]
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
VLRC 1.62
-
1.8
10
1.98
-
V
Center Frequency
kHz
25C, VDD = 3.3V
25 C,
-30
-
-
+30
%
%
FLRC
VDD = 2.5 ~ 5.5V
Calibrated Internal
Oscillator Frequency
-40C ~+105 C,
-50
+50
-
VDD = 2.5 ~ 5.5V
-
0.74
0.66
VDD = 5.5V
VDD = 3.3V
A
A
Operating current
ILRC
Note: Internal oscillator operation voltage comes from LDO.
Aug. 17, 2018
Page 133 of 148
Rev 1.02
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8.4 Analog Characteristics
8.4.1 12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Operating voltage
AVDD
IADC1
V
AVDD = VDD
3.0
-
-
5.5
-
AVDD = VDD = 4.5V
Operating current (AVDD
current)
mA
2.72
ADC Clock Rate = 16 MHz
(Enable ADC and disable all
other analog modules)
AVDD = VDD = 2.5V
IADC2
A
ADC Clock Rate = 6 MHz
Resolution
RADC
VREF
VIN
Bit
V
-
-
-
12
-
Reference voltage
ADC input voltage
AVDD
AVDD = 5V
V
0
-
-
-
-
AVDD
16
8
MHz AVDD = 5 V
MHz AVDD = 3 V
ADC Clock frequency
FADC
-
Acquisition Time (Sample
Stage)
TACQ
1/FADC Default: 7 (1/FADC)
2
7
21
34
TCONV = TACQ + 13
1/FADC
Conversion time
TCONV
15
20
Default: 20 (1/FADC)
AVDD = 5V
kSPS TCONV = 20 clock
FADC = 16 MHz
-
-
-
800
300
Conversion Rate
FSPS
(FADC/TCONV
)
AVDD = 3V
kSPS TCONV = 20 clock
FADC = 6 MHz
-
-
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
INL
DNL
EG
LSB
LSB
LSB
LSB
LSB
pF
+1.6
-1
+2.1
-1.5
-4.7
+3.6
+4.7
-
-
-3.4
+2.2
+3.1
-
-
Offset error
EOFFSET
EABS
CIN
-
Absolute error
-
Internal Capacitance
Input Load
3.2
6
RIN
kΩ
-
-
Monotonic
-
Guaranteed
-
Aug. 17, 2018
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Rev 1.02
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EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Typical connection diagram using the ADC
VDD
(1)
RIN
12-bit
Converter
AINx
(1)
CIN
Note: GND < AINX < VDD
Aug. 17, 2018
Page 135 of 148
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8.4.2 LDO
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Min
2.5
Typ
-
Max
5.5
Unit
V
Test Condition
VLDO
TA
V
1.62
-40
1.8
25
1.98
+105
℃
Note 1: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS
pin of the device.
Note 2: For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin
and the closest VSS pin of the device.
8.4.3 Low-Voltage Reset
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
+105
-
Unit
V
Test Condition
℃
-
-40
-
-
ILVR
Quiescent Current
uA
V
AVDD = 5.5V
TA = 85℃
TA = 25℃
TA = -40℃
1.1
2.2
2.1
2.0
129
2.1
2.0
1.9
-
2.3
2.2
2.1
-
VPOR
Threshold Voltage
Start-up Time
V
V
TLVR_Start
uS
8.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-
-40
-
-
+105
-
IBOD
Quiescent Current
AVDD = 5.5V
BODVL [1:0] = 11
BODVL [1:0] = 10
BODVL [1:0] = 01
BODVL [1:0] = 00
BODVL [1:0] = 11
81
4.5
3.7
2.7
2.2
4.6
4.3
3.5
2.55
2.05
4.3
4.7
V
3.9
Brown-out Voltage
(Falling edge)
VBOD
V
2.85
2.35
.4.7
V
VBOD
Brown-out Voltage
V
Aug. 17, 2018
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Rev 1.02
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(Rising edge)
Start-up Time
V
V
BODVL [1:0] = 10
3.6
2.6
2.1
-
3.8
2.75
2.25
1060
4.0
2.9
2.4
-
BODVL [1:0] = 01
BODVL [1:0] = 00
V
TBOD_Start
uS
8.4.5 Power-on Reset
Symbol
TA
Parameter
Min
-40
1.5
Typ
-
Max
+105
2.2
Unit
℃
Test Condition
Temperature
Threshold Voltage
-
-
VPOR
VHYS
V
2
Power Drop Detect Voltage
V
1.78
VPOR
VHYS
t (don’t care)
Figure 8.4-1 Power-up Ramp Condition
Aug. 17, 2018
Page 137 of 148
Rev 1.02
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8.4.6 Temperature Sensor
SPECIFICATIONS
TEST CONDITION
(supply voltage = 3V)
PARAMETER
SYM.
MIN. TYP. MAX. UNIT
Detection Temperature
Operating current
Gain
TDET
ITEMP
VTG
-40
6.4
-1.8
-
+105
10.5
oC
-
-
A
-1.76
725
-1.73 mV/ oC
mV Temperature at 0 oC
Offset
VTO
-
Note 1: Internal operation voltage comes from LDO.
Note 2: The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃ ) x Temperature (℃) + Offset (mV)
Aug. 17, 2018
Page 138 of 148
Rev 1.02
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8.4.7
USB PHY
8.4.7.1 Low-full-Speed DC Electrical Specifications
Symbol
VIH
Parameter
Input High (driven)
Min.
2.0
-
Typ.
Max.
Unit
V
Test Conditions
-
-
-
-
0.8
-
-
VIL
Input Low
V
-
VDI
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
0.8
0.8
-
-
2.5
2.0
V
V
Includes VDI range
-
Common-mode Range
Single-ended Receiver
Threshold
VSE
Receiver Hysteresis
Output Low (driven)
Output High (driven)
Output Signal Cross Voltage
Pull-up Resistor
-
200
-
mV
V
-
-
-
-
-
VOL
VOH
VCRS
RPU
RPD
0
-
-
-
-
-
0.3
2.8
3.6
V
1.3
2.0
V
1.425
14.25
1.575
15.75
kΩ
kΩ
Pull-down Resistor
TERMINATION Voltage for
Uptream port pull up (RPU)
VTRM
3.0
-
3.6
V
ZDRV
CIN
Driver Output Resistance
Transceiver Capacitance
-
-
10
-
-
Ω
Steady state drive*
Pin to GND
20
pF
*Driver output resistance doesn’t include series resistor resistance.
8.4.7.2 USB Full-Speed Driver Electrical Characteristics
Symbol
TFR
Parameter
Min.
4
Typ.
Max.
20
Unit
ns
Test Conditions
CL=50p
Rise Time
Fall Time
-
-
-
TFF
4
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
111.11
%
TFRFF=TFR/TFF
8.4.7.3 USB LDO Specification
Symbol
VBUS
Parameter
VBUS Pin Input Voltage
LDO Output Voltage
Min.
4.0
3.0
-
Typ.
5.0
Max.
5.5
3.6
-
Unit
Test Conditions
V
V
-
-
-
VDD33
Cbp
3.3
External Bypass Capacitor
1.0
uF
Aug. 17, 2018
Page 139 of 148
Rev 1.02
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8.5 Flash DC Electrical Characteris
Symbol
Parameter
Supply Voltage
Endurance
Min
Typ
Max
1.98
-
Unit
V
Test Condition
[1]
VFLA
1.62
1.8
cycles[2]
year
mS
NENDUR
TRET
20,000
-
-
-
-
-
-
-
-
Data Retention
Page Erase Time
Mass Erase Time
Program Time
Read Current
100
20
20
20
-
-
TERASE
TMER
TPROG
IDD1
40
mS
TA = 25℃
40
uS
40
mA
TBD
TBD
TBD
IDD2
Program Current
Erase Current
mA
-
IDD3
uA
-
Note 1: VFLA is source from chip LDO output voltage.
Note 2: Number of program/erase cycles.
Note 3: This table is guaranteed by design, not test in production.
Aug. 17, 2018
Page 140 of 148
Rev 1.02
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8.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
Max.
-
Min.
1.2
Max.
tLOW
tHIGH
SCL low period
SCL high period
-
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
4
4.7
4
-
0.6
1.2
-
tSU; STA
tHD; STA
tSU; STO
tBUF
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
-
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must
be higher than 8 MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch
the low period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-1 I2C Timing Diagram
Aug. 17, 2018
Page 141 of 148
Rev 1.02
NUC121/125
8.7 SPI Dynamic Characteristics
8.7.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
4
0
-
2
-
-
-
ns
ns
ns
Data hold time
Data output valid time
7
11
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
5
0
-
3
-
-
-
ns
ns
ns
Data hold time
Data output valid time
13
18
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
-
-
ns
ns
ns
Data hold time
2*PCLK+4
-
-
Data output valid time
-
2*PCLK+11
2*PCLK+19
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
Aug. 17, 2018
Page 142 of 148
Rev 1.02
NUC121/125
tDS
tDH
tV
Data setup time
0
-
-
ns
ns
ns
Data hold time
2*PCLK+6
-
-
Data output valid time
-
2*PCLK+19
2*PCLK+25
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 8.7-2 SPI Slave Mode Timing Diagram
Aug. 17, 2018
Page 143 of 148
Rev 1.02
NUC121/125
9 PACKAGE DIMENSIONS
9.1 LQFP 64S (7x7x1.4 mm)
Aug. 17, 2018
Page 144 of 148
Rev 1.02
NUC121/125
9.2 LQFP 48L (7x7x1.4 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
L
0.024 0.030
0.45
0
0.039
0.004
7
1
L
Y
0.10
7
0
0
Aug. 17, 2018
Page 145 of 148
Rev 1.02
NUC121/125
9.3 QFN 33Z (5x5x0.8 mm)
Aug. 17, 2018
Page 146 of 148
Rev 1.02
NUC121/125
10 REVISION HISTORY
Revision
Date
Description
1.00
2017.02.15
Preliminary version
1.
Fixed the typo of Operating Current Normal Run Mode HCLK = 50
MHz in section 8.2 DC Electrical Characteristics.
1.01
1.02
2017.12.14
2018.08.17
2.
3.
Fixed the number of ADC channel in Table 4.1-2.
Fixed Internal Reference Voltage to Internal Voltage (Band-gap) in
Figure 6.2-7.
1.
Removed the ICE_DAT and ICE_CLK description from PF.2 and
PF.3 in section 4.2 and 4.3.
Aug. 17, 2018
Page 147 of 148
Rev 1.02
NUC121/125
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Aug. 17, 2018
Page 148 of 148
Rev 1.02
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