NUC126LG4BE [NUVOTON]
ARM CORTEX® -M 32-BIT MICROCONTROLLER;
| 型号： | NUC126LG4BE |
| 厂家： | 
NUVOTON |
| 描述： | ARM CORTEX® -M 32-BIT MICROCONTROLLER |
| 文件： | 总140页 (文件大小：2721K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC126
ARM CORTEX® -M
32-BIT MICROCONTROLLER
NuMicro® Family
NUC126 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Aug. 08, 2018
Page 1 of 140
Rev 1.04
NUC126
TABLE OF CONTENTS
1
2
3
4
GENERAL DESCRIPTION.................................................................................8
1.1
Key Feature and Application.........................................................................................9
FEATURES.......................................................................................................10
2.1
NuMicro® NUC126 Features.......................................................................................10
ABBREVIATIONS ............................................................................................18
3.1
Abbreviations ..............................................................................................................18
PARTS INFORMATION LIST AND PIN CONFIGURATION............................20
4.1
NuMicro® NUC126 Selection Guide ...........................................................................20
4.1.1 NuMicro® NUC126 Naming Rule ................................................................................... 20
4.1.2 NuMicro® NUC126 USB Series (M452 Compatible) Selection Guide............................ 21
Pin Configuration ........................................................................................................22
4.2
4.2.1 NuMicro® NUC126 USB Series QFN48 Pin Diagram .................................................... 22
4.2.2 NuMicro® NUC126 USB Series LQFP48 Pin Diagram................................................... 23
4.2.3 NuMicro® NUC126 USB Series LQFP64 Pin Diagram................................................... 24
4.2.4 NuMicro® NUC126 USB Series LQFP100 Pin Diagram................................................. 25
Pin Description............................................................................................................26
4.3
4.3.1 NUC126 USB Series Pin Description............................................................................. 26
4.3.2 GPIO Multi-function Pin Summary ................................................................................. 41
5
6
BLOCK DIAGRAM ...........................................................................................53
5.1
NuMicro® NUC126 Block Diagram .............................................................................53
FUNCTIONAL DESCRIPTION .........................................................................54
6.1
6.2
ARM® Cortex® -M0 Core..............................................................................................54
System Manager.........................................................................................................56
6.2.1 Overview........................................................................................................................ 56
6.2.2 System Reset................................................................................................................. 56
6.2.3 Power Modes and Wake-up Sources............................................................................. 63
6.2.4 System Power Distribution............................................................................................. 66
6.2.5 System Memory Map ..................................................................................................... 68
6.2.6 SRAM Memory Orginization........................................................................................... 70
6.2.7 Register Lock................................................................................................................. 71
6.2.8 Auto Trim ....................................................................................................................... 71
6.2.9 UART1_TXD modulation with PWM............................................................................... 72
6.2.10 Voltage Detector (VDET) ............................................................................................... 73
6.2.11 System Timer (SysTick)................................................................................................. 74
6.2.12 Nested Vectored Interrupt Controller (NVIC).................................................................. 75
Clock Controller ..........................................................................................................78
6.3
6.3.1 Overview........................................................................................................................ 78
6.3.2 System Clock and SysTick Clock................................................................................... 81
6.3.3 Peripherals Clock........................................................................................................... 82
6.3.4 Power-down Mode Clock ............................................................................................... 83
6.3.5 Clock Output .................................................................................................................. 83
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6.4
6.5
6.6
6.7
6.8
6.9
Flash Memeory Controller (FMC) ...............................................................................85
6.4.1 Overview........................................................................................................................ 85
6.4.2 Features......................................................................................................................... 85
Analog Comparator Controller (ACMP) ......................................................................86
6.5.1 Overview........................................................................................................................ 86
6.5.2 Features......................................................................................................................... 86
Analog-to-Digital Converter (ADC) .............................................................................87
6.6.1 Overview........................................................................................................................ 87
6.6.2 Features......................................................................................................................... 87
CRC Controller (CRC) ................................................................................................88
6.7.1 Overview........................................................................................................................ 88
6.7.2 Features......................................................................................................................... 88
External Bus Interface (EBI) .......................................................................................89
6.8.1 Overview........................................................................................................................ 89
6.8.2 Features......................................................................................................................... 89
General Purpose I/O (GPIO) ......................................................................................90
6.9.1 Overview........................................................................................................................ 90
6.9.2 Features......................................................................................................................... 90
6.10 Hardware Divider (HDIV)............................................................................................91
6.10.1 Overview........................................................................................................................ 91
6.10.2 Features......................................................................................................................... 91
6.10.3 Blcok Diagram................................................................................................................ 91
6.11 I2C Serial Interface Controller (I2C).............................................................................92
6.11.1 Overview........................................................................................................................ 92
6.11.2 Features......................................................................................................................... 92
6.12 PDMA Controller (PDMA)...........................................................................................93
6.12.1 Overview........................................................................................................................ 93
6.12.2 Features......................................................................................................................... 93
6.13 PWM Generator and Capture Timer (PWM) ..............................................................94
6.13.1 Overview........................................................................................................................ 94
6.13.2 Features......................................................................................................................... 94
6.14 Real Time Clock (RTC)...............................................................................................96
6.14.1 Overview........................................................................................................................ 96
6.14.2 Features......................................................................................................................... 96
6.15 Smart Card Host Interface (SC)..................................................................................97
6.15.1 Overview........................................................................................................................ 97
6.15.2 Features......................................................................................................................... 97
6.16 Serial Peripheral Interface (SPI).................................................................................98
6.16.1 Overview........................................................................................................................ 98
6.16.2 Features......................................................................................................................... 98
6.17 Timer Controller (TMR)...............................................................................................99
6.17.1 Overview........................................................................................................................ 99
6.17.2 Features......................................................................................................................... 99
6.18 USB Device Controller (USBD) ................................................................................101
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6.18.1 Overview...................................................................................................................... 101
6.18.2 Features....................................................................................................................... 101
6.19 USCI – Universal Serial Control Interface Controller................................................102
6.19.1 Overview...................................................................................................................... 102
6.19.2 Features....................................................................................................................... 102
6.20 USCI – UART Mode .................................................................................................103
6.20.1 Overview...................................................................................................................... 103
6.20.2 Features....................................................................................................................... 103
6.21 USCI – SPI Mode .....................................................................................................104
6.21.1 Overview...................................................................................................................... 104
6.21.2 Features....................................................................................................................... 104
6.22 USCI – I2C Mode ......................................................................................................106
6.22.1 Overview...................................................................................................................... 106
6.22.2 Features....................................................................................................................... 106
6.23 UART Interface Controller (UART) ...........................................................................107
6.23.1 Overview...................................................................................................................... 107
6.23.2 Features....................................................................................................................... 107
6.24 Watchdog Timer (WDT)............................................................................................108
6.24.1 Overview...................................................................................................................... 108
6.24.2 Features....................................................................................................................... 108
6.24.3 Clock Control ............................................................................................................... 108
6.25 Window Watchdog Timer (WWDT)...........................................................................109
6.25.1 Overview...................................................................................................................... 109
6.25.2 Features....................................................................................................................... 109
6.25.3 Clock Control ............................................................................................................... 109
7
8
APPLICATION CIRCUIT ................................................................................110
ELECTRICAL CHARACTERISTICS ..............................................................111
8.1
8.2
8.3
Absolute Maximum Ratings......................................................................................111
DC Electrical Characteristics ....................................................................................112
AC Electrical Characteristics ....................................................................................120
8.3.1 External 4~24 MHz High Speed Crystal (HXT) Input Clock ......................................... 120
8.3.2 External 4~24 MHz High Speed Crystal (HXT) Oscillator ............................................ 120
8.3.3 External 32.768 kHz Low Speed Crystal (LXT) Input Clock......................................... 121
8.3.4 External 32.768 kHz Low Speed Crystal (LXT) Input Clock......................................... 122
8.3.5 Internal 48 MHz High Speed RC Oscillator (HIRC48).................................................. 123
8.3.6 Internal 22.1184 MHz High Speed RC Oscillator (HIRC)............................................. 123
8.3.7 Internal 10 kHz Low Speed RC Oscillator (LIRC) ........................................................ 123
Analog Characteristics..............................................................................................125
8.4
8.4.1 LDO.............................................................................................................................. 125
8.4.2 Temperature Sensor.................................................................................................... 125
8.4.3 Internal Voltage Reference (Int_VREF).......................................................................... 125
8.4.4 Power-on Reset ........................................................................................................... 126
8.4.5 Low-Voltage Reset....................................................................................................... 126
8.4.6 Brown-out Detector...................................................................................................... 126
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8.4.7 12-bit ADC ................................................................................................................... 127
8.4.8 Analog Comparator...................................................................................................... 129
8.4.9 USB PHY ..................................................................................................................... 130
Flash DC Electrical Characteris................................................................................131
8.5
8.6
8.7
I2C Dynamic Characteristics ....................................................................................132
SPI Dynamic Characteristics ....................................................................................133
8.7.1 Dynamic Characteristics of Data Input and Output Pin ................................................ 133
9
PACKAGE DIMENSIONS ..............................................................................135
9.1
9.2
9.3
9.4
LQFP 100L (14x14x1.4 mm footprint 2.0 mm) .........................................................135
LQFP 64L (7x7x1.4 mm footprint 2.0 mm) ...............................................................136
LQFP 48L (7x7x1.4 mm Footprint 2.0 mm)..............................................................137
QFN 48L (7x7x0.8 mm) ............................................................................................138
10 REVISION HISTORY......................................................................................139
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LIST OF FIGURES
Figure 4.2-1 NuMicro® NUC126 USB Series QFN 48-pin Diagram ...............................................22
Figure 4.2-2 NuMicro® NUC126 USB Series LQFP 48-pin Diagram .............................................23
Figure 4.2-3 NuMicro® NUC126 USB Series LQFP 64-pin Diagram .............................................24
Figure 4.2-4 NuMicro® NUC126 USB Series LQFP 100-pin Diagram ...........................................25
Figure 5.1-1 NuMicro® NUC126 Block Diagram.............................................................................53
Figure 6.1-1 Functional Block Diagram ..........................................................................................54
Figure 6.2-1 System Reset Sources...............................................................................................57
Figure 6.2-2 nRESET Reset Waveform .........................................................................................59
Figure 6.2-3 Power-on Reset (POR) Waveform.............................................................................60
Figure 6.2-4 Low Voltage Reset (LVR) Waveform .........................................................................61
Figure 6.2-5 Brown-out Detector (BOD) Waveform .......................................................................62
Figure 6.2-6 NuMicro® NUC126 Power Mode State Machine........................................................64
Figure 6.2-7 NuMicro® NUC126 Power Distribution Diagram ........................................................67
Figure 6.2-8 SRAM Block Diagram ................................................................................................70
Figure 6.2-9 SRAM Memory Organization .....................................................................................71
Figure 6.2-10 UART1_TXD Modulated with PWM Channel...........................................................72
Figure 6.2-11 VDET Block Diagram ...............................................................................................73
Figure 6.3-1 Clock Generator Block Diagram.................................................................................79
Figure 6.3-2 Clock Generator Global View Diagram ......................................................................80
Figure 6.3-3 System Clock Block Diagram.....................................................................................81
Figure 6.3-4 HXT Stop Protect Procedure......................................................................................82
Figure 6.3-5 SysTick Clock Control Block Diagram .......................................................................82
Figure 6.3-6 Clock Source of Clock Output....................................................................................83
Figure 6.3-7 Clock Output Block Diagram......................................................................................84
Figure 6.10-1 Hardware Divider Block Diagram.............................................................................91
Figure 6.21-1 SPI Master Mode Application Block Diagram ........................................................104
Figure 6.21-2 SPI Slave Mode Application Block Diagram ..........................................................104
Figure 6.22-1 I2C Bus Timing .......................................................................................................106
Figure 6.24-1 Watchdog Timer Clock Control ..............................................................................108
Figure 6.25-1 WWDT Clock Control.............................................................................................109
Figure 8.3-1 Typical Crystal Application Circuit............................................................................121
Figure 8.3-2 Typical Crystal Application Circuit............................................................................122
Figure 8.6-1 I2C Timing Diagram..................................................................................................132
Figure 8.7-1 SPI Master Mode Timing Diagram...........................................................................133
Figure 8.7-2 SPI Slave Mode Timing Diagram.............................................................................134
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List of Tables
Table 1.1-1 Key Features Support Table .........................................................................................9
Table 3.1-1 List of Abbreviations ....................................................................................................19
Table 4.3-1 NUC126 GPIO Multi-function Table ............................................................................52
Table 6.2-1 Reset Value of Registers.............................................................................................59
Table 6.2-2 Power Mode Difference Table.....................................................................................63
Table 6.2-3 Clocks in Power Modes..............................................................................................65
Table 6.2-4 Condition of Entering Power-down Mode Again .........................................................66
Table 6.2-5 Address Space Assignments for On-Chip Controllers ................................................69
Table 6.2-6 Exception Model..........................................................................................................76
Table 6.2-7 Interrupt Number Table ...............................................................................................77
Table 6.3-8 Clock Stable Count Value Table .................................................................................79
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NUC126
1
GENERAL DESCRIPTION
The NuMicro® NUC126 series microcontroller based on the ARM® Cortex® -M0 core operates at up
to 72 MHz. With its crystal-less USB 2.0 FS interface, it is able to generate precise frequency
required by USB protocol without the need of external crystal. It features adjustable VDDIO pins for
specific I/O pins with a wide range of voltage from 1.8V to 5.5V for various operating voltages of
external components, a unique high-speed PWM with clock frequency up to 144 MHz for precision
control, and an integrated hardware divider to speed up the calculation for the control algorithms.
Apart from that, the NUC126 also integrates SPROM (Security Protection ROM) which provides a
secure code execution area to protect the intelligent property of developers. The NUC126 series
is ideal for industrial control, motor control and metering applications.
The NUC126 series supports the wide voltage range from 2.5V to 5.5V and temperature ranging
from -40℃ to 105℃, up to 256 Kbytes of Flash memory, 20 Kbytes of SRAM, 4 Kbytes of ISP (In-
System Programming) ROM as well as ICP (In-Circuit Programming) ROM and IAP (In-
Application Programming) ROM in 48-, 64- or 100-pin packages. It also supports high immunity of
8KV ESD (HBM)/4KV EFT. It is also equipped with plenty of peripherals such as USB interface,
Timers, Watchdog Timers, RTC, PDMA, EBI, UART, Smart Card Interface, SPI, I²S, I²C, GPIO, up
to 12 channels of 16-bit PWM, up to 20 channels of 12-bit ADC, analog comparator, temperature
sensor, low voltage reset, brown-out detector, 96-bit UID (Unique Identification), and 128-bit UCID
(Unique Customer Identification).
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1.1 Key Feature and Application
ISO
RTC
VBAT
Product Line USB
USCI UART
I2C
SPI/I2S
PWM
EBI
PDMA ADC ACMP
VDDIO
7816
2.0 FS
NUC126
3
3
2
2
2
12
Y
5
20
2
Y
Y
Device
Table 1.1-1 Key Features Support Table
The NuMicro® NUC126 series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation
Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
System Supervisors
Smart Card Reader
Printer
Bar Code Scanner
Motor Control
Digital Power
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NUC126
2 FEATURES
2.1 NuMicro® NUC126 Features
Core
–
–
–
–
–
–
–
ARM® Cortex® -M0 core running up to 72 MHz
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Supports programmable mask-able interrupts
Serial Wire Debug supports with 2 watch-points/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Flash Memory
–
–
–
–
–
–
–
Supports 256/128 KB application ROM (APROM)
Supports 4 KB Flash for loader (LDROM)
Supports 2 KB Security Protection Rom (SPROM)
Supports 12 bytes User Configuration block to control system initiation
Supports Data Flash with configurable memory size
Supports 2 KB page erase for all embedded flash
Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
–
–
–
–
Supports CRC-32 checksum calculation function
Supports flash all one verification function
Hardware external read protection of whole flash memory by Security Lock Bit
Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
–
–
–
20 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
Hardware Divider
–
–
–
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-
bit)
–
–
–
–
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
PDMA (Peripheral DMA)
–
Supports 5 independent configurable channels for automatic data transfer between
memories and peripherals
–
–
–
–
–
–
–
Supports single and burst transfer type
Supports Normal and Scatter-Gather Transfer modes
Supports two types of priorities modes: Fixed-priority and Round-robin modes
Supports byte-, half-word- and word-access
Supports incrementing mode for the source and destination address for each channel
Supports time-out function for channel 0 and channel 1
Supports software and SPI/I2S, UART, USCI, USB, ADC, PWM and TIMER request
Clock Control
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–
–
Built-in 22.1184 MHz high speed RC oscillator for system operation (Frequency
variation < 2% at -40oC ~ +105oC)
Built-in 48 MHz internal high speed RC oscillator for USB device operation(Frequency
variation < 2% at -40oC ~ +105oC)
–
–
–
–
–
Built-in 10 kHz low speed RC oscillator for Watchdog Timer and Wake-up operation
Built-in 4~24 MHz high speed crystal oscillator for precise timing operation
Built-in 32.768 kHz low speed crystal oscillator for Real Time Clock
Supports PLL up to 144 MHz for high resolution PWM operation
Supports dynamically calibrating the HIRC48 to 48 MHz ±0.25% by external 32.768K
crystal oscillator (LXT)
–
Supports dynamically calibrating the HIRC to 22.1184Mhz by external 32.768K crystal
oscillator (LXT)
–
–
–
–
–
Supports clock on-the-fly switch
Supports clock failure detection for system clock
Supports auto clock switch once clock failure detected
Supports exception (NMI) generated once a clock failure detected
Supports divided clock output
GPIO
–
–
–
–
–
–
Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports up to 81/49/35 GPIOs for LQFP100/64/48 respectively
Timer/PWM
–
Supports 4 sets of Timers/PWM
Timer Mode
PWM Mode
TM_CNT_OUT
PWM_CH0
TM_EXT
PWM_CH1 (Complementary)
–
Timer Mode
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to
trigger PWM, EADC and PDMA function
Supports Inter-Timer trigger mode
–
PWM Mode
Supports maximum clock frequency up to 72MHz
Supports independent mode for 4 sets of independent PWM output channel
Supports complementary mode for 4 sets of complementary paired PWM output
channel with 12-bit Dead-time generator
Supports 12-bit pre-scalar from 1 to 4096
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Supports 16-bit resolution PWM counter, each timer provides 1 PWM counter
Supports up, down and up/down counter operation type
Supports one-shot or Auto-reload counter operation mode
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Supports interrupt when PWM counter match zero, period value or compared
value, and brake condition happened
Supports trigger ADC when PWM counter match zero, period value or compared
value
Watchdog Timer
–
–
–
–
Supports multiple clock sources from LIRC(default selection), HCLK/2048 and LXT
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
–
–
Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
Interrupt or reset selectable on time-out
RTC
–
–
–
–
–
–
–
–
Supports separate battery power pin VBAT
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Supports Alarm mask registers
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
Supports wake-up function
PWM
–
–
–
–
Supports maximum clock frequency up to144MHz
Supports up to two PWM modules, each module provides 6 output channels.
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 2 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
–
–
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
–
–
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin and system safety events: clock failed, Brown-out
detection and CPU lockup.
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
Level detect brake source to auto recover function after brake condition removed
–
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
–
Supports trigger ADC on the following events:
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PWM counter match zero, period value or compared value
–
–
–
–
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
USCI
–
Supports up to 3 sets of USCI
USCI
UART Mode
SPI Mode
SPI_CLK
SPI_SS
-
I2C Mode
USCI_CLK
USCI_CTL0
USCI_CTL1
USCI_DAT0
-
SCL
nCTS
nRTS
Rx
-
-
SPI_MOSI
SPI_MISO
SDA
-
USCI_DAT1
Tx
–
–
UART Mode
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-Bit Data Transfer (Support 9-Bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports Wake-up function (Data and nCTS Wakeup Only)
SPI Mode
Supports Master or Slave mode operation (the maximum frequency -- Master =
fPCLK / 2, Slave = fPCLK / 5)
Supports one transmit buffer and two receive buffers for data payload
Configurable bit length of a transfer word from 4 to 16-bit
Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
–
I2C Mode
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports one transmit buffer and two receive buffer for data payload
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
UART
–
–
–
–
–
–
–
–
Supports up to 3 sets of UART
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control (RX, TX, CTS and RTS)
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit
by setting DLY (UART_TOUT [15:8])
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–
–
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
–
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
–
–
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
–
Supports RS-485 mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
–
–
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports PDMA transfer
Smart Card Host (SC)
– Supports up to two Smart Card Hosts
SC Mode
SC_DATA
SC_CLK
SC_CD
UART Mode
Rx
Tx
-
SC_PWR
SC_RST
-
-
–
SC Mode
Supports up to two ISO-7816-3 ports
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and
waiting times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card is
removal
–
UART Mode
Full duplex, asynchronous communications
Supports receiving / transmitting 4-bytes FIFO
Supports programmable baud rate generator for each channel
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
SPI/I2S
Aug. 08, 2018
Page 14 of 140
Rev 1.04
NUC126
–
Supports up to two SPI/I2S controllers
SPI Mode
SPI_CLK
SPI_SS
I2S Mode
I2S_BCLK
I2S_LRCLK
I2S_DO
SPI_MOSI
SPI_MISO
I2S_DI
-
I2S_MCLK
–
–
SPI Mode
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports PDMA transfer
I2S Mode
Supports Master or Slave mode operation
Capable of handling 8-, 16-, 24- and 32-bit word sizes in I2S mode
Provides separate 4-level depth transmit and receive FIFO buffers in I2S mode
Supports monaural and stereo audio data in I2S mode
Supports PCM mode A, PCM mode B, I2S and MSB justified data format in I2S
mode
Supports PDMA transfer
I2C
–
–
–
–
–
Supports up to two sets of I2C device
Supports Master/Slave mode
Supports bidirectional data transfer between masters and slaves
Supports multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
–
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Supports 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
–
–
–
–
–
Programmable clocks allow versatile rate control
Supports multiple address recognition, four slave address with mask option
Supports two-level buffer function
Supports setup/hold time programmable
Supports wake-up function
USB 2.0 FS Device Controller
–
–
–
–
–
–
–
–
–
–
Crystal-less USB 2.0 FS Device
Compliant to USB specification version 2.0
On-chip USB Transceiver
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Supports USB 2.0 Link Power Management (LPM)
Provides 8 programmable endpoints
Supports 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
On-chip 5V to 3.3V LDO for USB PHY
Aug. 08, 2018
Page 15 of 140
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NUC126
ADC
–
–
–
–
–
–
–
–
–
Supports 12-bit SAR ADC
12-bit resolution and 10-bit accuracy is guaranteed
Analog input voltage range: 0~ AVDD
Supports external VREF pin
Up to 20 single-end analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Conversion rate up to 800K SPS at 5V
Configurable ADC internal sampling time
Supports single-scan, single-cycle-scan, and continuous scan and scan on enabled
channels
–
–
–
Supports individual conversion result register with valid and overrun indicators for each
channel
Supports digital comparator to monitor conversion result and user can select whether
to generate an interrupt when conversion result matches the compare register setting
An A/D conversion can be triggered by:
Software enable
External pin (STADC)
Timer 0~3 overflow pulse trigger
PWM triggers with optional start delay period
–
Supports 4 internal channels for
Operational amplifier output
Band-gap VBG input
Temperature sensor input
VBAT voltage measure
–
–
Supports internal reference voltage: 2.048V, 2.560V, 3.072V and 4.096V
Supports PDMA transfer
Analog Comparator
–
–
–
–
Supports up to 2 rail-to-rail analog comparators
Supports 4 multiplexed I/O pins at positive node.
Supports I/O pin and internal voltages at negative node
Support selectable internal voltage reference from:
Band-gap VBG
Voltage divider source from AVDD and internal reference voltage.
–
–
–
Supports programmable hysteresis
Supports programmable speed and power consumption
Interrupts generated when compare results change, interrupt event condition is
programmable.
–
–
Supports power-down wake-up
Supports triggers for break events and cycle-by-cycle control for PWM
Cyclic Redundancy Calculation Unit
–
–
–
–
–
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
Programmable initial value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum.
Supports 8/16/32-bit of data width
–
Interrupt generated once checksum error occurs
User Configurable VDD1=1.8~5.5V IO Interface
Supports UART0, SPI0 and I2C0
–
Supports 96-bit Unique ID (UID)
Supports 128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Aug. 08, 2018
Page 16 of 140
Rev 1.04
NUC126
Brown-out detector
–
–
With 8 levels: 4.3 V/ 3.7V/ 2.7V/ 2.2V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 2.0 V
Power consumption
–
–
Chip power down current < 10 uA with RAM data retention.
VBAT power domain operating current <1.5 uA
Operating Temperature: -40℃~105℃
Packages
–
–
–
–
–
All Green package (RoHS)
LQFP 100-pin
LQFP 64-pin(7mmx7mm)
LQFP 48-pin
QFN 48-pin
Aug. 08, 2018
Page 17 of 140
Rev 1.04
NUC126
3 ABBREVIATIONS
3.1 Abbreviations
Acronym
ACMP
ADC
AES
APB
AHB
BOD
DAP
DES
EBI
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Aug. 08, 2018
Page 18 of 140
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NUC126
SPS
Samples per Second
TDES
TMR
Triple Data Encryption Standard
Timer Controller
UART
UCID
USB
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
Aug. 08, 2018
Page 19 of 140
Rev 1.04
NUC126
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC126 Selection Guide
4.1.1 NuMicro® NUC126 Naming Rule
ARM–Based
32-bit
Microcontroller
26X X 4 X E
NUC1
®
Corte -M0
CPU core
Temperature
E : -40oC ~ +105oC
Version
Product Line Function
2X : USB Line
A :
B :
SRAM Size
4 : 20K
Package type
N : QFN 48 7x7mm
L : LQFP 48 7x7mm
S : LQFP 64 7x7mm
V : LQFP 100 14x14mm
Flash ROM
E : 128K
G : 256K
Aug. 08, 2018
Page 20 of 140
Rev 1.04
NUC126
4.1.2 NuMicro® NUC126 USB Series (M452 Compatible) Selection Guide
Connectivity
Part Number
Conf*
NUC126NE4AE 128
NUC126LE4AE 128
NUC126LG4AE 256
NUC126SE4AE 128
NUC126SG4AE 256
20
20
20
20
20
20
2
2
2
2
2
2
4
4
4
4
4
4
35
35
35
49
49
81
4
4
4
4
4
4
10
10
10
12
12
12
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
9-ch
9-ch
2
2
2
2
2
2
5
5
5
5
5
5
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
QFN 48
LQFP 48
LQFP 48
LQFP 64*
LQFP 64*
LQFP 100
Conf*
Conf*
Conf*
Conf*
Conf*
9-ch
15-ch
15-ch
20-ch
NUC126VG4AE 256
Conf*: Configurable
USCI*: support UART, SPI or I2C
LQFP64*: 7x7 mm
Aug. 08, 2018
Page 21 of 140
Rev 1.04
NUC126
4.2 Pin Configuration
4.2.1
NuMicro® NUC126 USB Series QFN48 Pin Diagram
Corresponding Part Number: NUC126NE4AE
37
24
23
22
21
20
19
18
17
16
15
14
13
PA.3
PE.0
PC.4
PC.3
PC.2
PC.1
PC.0
LDO_CAP
VSS
38
PA.2
39
PA.1
40
PA.0
41
VDD
42
AVDD
QFN 48
43
VREF
44
PB.0
45
PB.1
PF.4
46
PB.2
PF.3
47
PB.3
PD.7
PF.2
VSS
48
PB.4
Top Transparent View
VDDIO power domain
VBAT power domain
Figure 4.2-1 NuMicro® NUC126 USB Series QFN 48-pin Diagram
Aug. 08, 2018
Page 22 of 140
Rev 1.04
NUC126
4.2.2 NuMicro® NUC126 USB Series LQFP48 Pin Diagram
Corresponding Part Number: NUC126LE4AE, NUC126LG4AE
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PA.3
PA.2
PA.1
PA.0
VDD
PE.0
PC.4
PC.3
PC.2
PC.1
PC.0
LDO_CAP
VSS
AVDD
VREF
PB.0
PB.1
PB.2
PB.3
PB.4
LQFP48
PF.4
PF.3
PD.7
PF.2
VDDIO power domain
VBAT power domain
Figure 4.2-2 NuMicro® NUC126 USB Series LQFP 48-pin Diagram
Aug. 08, 2018
Page 23 of 140
Rev 1.04
NUC126
4.2.3 NuMicro® NUC126 USB Series LQFP64 Pin Diagram
Corresponding Part Number: NUC126SE4AE, NUC126SG4AE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
PA.3
PA.2
PA.1
PA.0
VSS
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
LDO_CAP
VDD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
AVDD
VREF
PB.0
PB.1
PB.2
PB.3
PB.4
PB.8
PB.11
PE.2
LQFP64
VSS
PF.4
PF.3
PD.7
PD.15
PD.14
PD.13
PD.12
VDDIO power domain
VBAT power domain
Figure 4.2-3 NuMicro® NUC126 USB Series LQFP 64-pin Diagram
Aug. 08, 2018
Page 24 of 140
Rev 1.04
NUC126
4.2.4 NuMicro® NUC126 USB Series LQFP100 Pin Diagram
Corresponding Part Number: NUC126VG4AE
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PF.7
PC.5
77
USB_VDD33_CAP
PE.0
78
PB.12
PC.4
79
PA.3
PC.3
80
PA.2
PC.2
81
PA.1
PC.1
82
PA.0
PC.0
83
PA.12
PC.14
PC.13
PC.12
PC.11
PC.10
PC.9
84
PA.13
85
PA.14
86
PA.15
87
VSS
88
VDD
LQFP100
89
AVDD
LDO_CAP
VDD
90
VREF
91
PB.0
VSS
92
PB.1
PF.4
93
PB.2
PF.3
94
PB.3
PD.7
95
PB.4
PD.15
PD.14
PD.13
PD.12
PD.11
PD.10
96
PB.8
97
PB.9
98
PB.10
99
PB.11
100
PE.2
VDDIO power domain
VBAT power domain
Figure 4.2-4 NuMicro® NUC126 USB Series LQFP 100-pin Diagram
Aug. 08, 2018
Page 25 of 140
Rev 1.04
NUC126
4.3 Pin Description
4.3.1 NUC126 USB Series Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GP0_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GP0_MFPH[7:4]=0x5.
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
1
2
3
PB.13
I/O
A
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP9
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
ADC0 channel 10 analog input.
General purpose digital I/O pin.
ADC0 channel 11 analog input.
General purpose digital I/O pin.
ADC0 channel 12 analog input.
Analog comparator 0 positive input 3 pin.
EBI chip select 1 output pin.
ADC0_CH10
PB.14
I/O
A
ADC0_CH11
PB.15
1
2
I/O
A
ADC0_CH12
ACMP0_P3
EBI_nCS1
PB.5
A
O
1
4
I/O
A
General purpose digital I/O pin.
ADC0 channel 13 analog input.
SPI0 MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Analog comparator 0 positive input 2 pin.
Smart Card 1 reset pin.
ADC0_CH13
SPI0_MOSI
SPI1_MOSI
ACMP0_P2
SC1_RST
EBI_AD6
I/O
I/O
A
O
I/O
I
EBI address/data bus bit 6.
UART2_RXD
PB.6
UART2 data receiver input pin.
General purpose digital I/O pin.
ADC0 channel 14 analog input.
SPI0 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Analog comparator 0 positive input 1 pin.
Smart Card 1 power pin.
2
3
5
I/O
A
ADC0_CH14
SPI0_MISO
SPI1_MISO
ACMP0_P1
SC1_PWR
EBI_AD5
I/O
I/O
A
O
I/O
I/O
A
EBI address/data bus bit 5.
3
4
6
PB.7
General purpose digital I/O pin.
ADC0 channel 15 analog input.
SPI0 serial clock pin.
ADC0_CH15
SPI0_CLK
SPI1_CLK
USCI2_CTL1
I/O
I/O
I/O
SPI1 serial clock pin.
USCI2 control 1 pin.
Aug. 08, 2018
Page 26 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
ACMP0_P0
SC1_DAT
EBI_AD4
A
I/O
I/O
I
MFP5
MFP6
MFP7
MFP0
Analog comparator 0 positive input 0 pin.
Smart Card 1 data pin.
EBI address/data bus bit 4.
4
5
5
6
7
8
nRESET
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PD.0
I/O
I/O
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP0
General purpose digital I/O pin.
SPI0 I2S master clock output pin
SPI1 I2S master clock output pin
UART0 data receiver input pin.
USCI2 control 0 pin.
SPI0_I2SMCLK
SPI1_I2SMCLK
UART0_RXD
USCI2_CTL0
ACMP1_N
SC1_CLK
INT3
I/O
A
Analog comparator 1 negative input pin.
Smart Card 1 clock pin.
O
I
External interrupt 3 input pin.
Ground pin for analog circuit.
6
7
9
AVSS
P
10 VDD
P
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
11 VSS
P
I/O
A
MFP0
MFP0
MFP1
MFP3
MFP0
MFP1
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
Ground pin for digital circuit.
12 PC.8
General purpose digital I/O pin.
ADC0 channel 16 analog input.
UART0 request to Send output pin.
General purpose digital I/O pin.
ADC0 channel 17 analog input.
UART0 clear to Send input pin.
USCI2 control 1 pin.
ADC0_CH16
UART0_nRTS
13 PD.8
O
8
I/O
A
ADC0_CH17
UART0_nCTS
USCI2_CTL1
TM2
I
I/O
I/O
O
Timer2 event counter input/toggle output pin.
EBI chip select 0 output pin.
EBI_nCS0
9
14 PD.9
I/O
A
General purpose digital I/O pin.
ADC0 channel 18 analog input.
UART0 data receiver input pin.
USCI2 control 0 pin.
ADC0_CH18
UART0_RXD
USCI2_CTL0
ACMP1_P3
TM3
I
I/O
A
Analog comparator 1 positive input 3 pin.
Timer3 event counter input/toggle output pin.
EBI address latch enable output pin.
General purpose digital I/O pin.
ADC0 channel 19 analog input.
I/O
O
EBI_ALE
7
10 15 PD.1
ADC0_CH19
I/O
A
Aug. 08, 2018
Page 27 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
PWM0_SYNC_IN
I
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
PWM0 counter synchronous trigger input pin.
UART0 data transmitter output pin.
USCI2 clock pin.
UART0_TXD
USCI2_CLK
ACMP1_P2
TM0
O
I/O
A
Analog comparator 1 positive input 2 pin.
Timer0 event counter input/toggle output pin.
EBI read enable output pin.
I/O
O
EBI_nRD
8
11 16 PD.2
I/O
I
General purpose digital I/O pin.
ADC0 external trigger input pin.
Timer0 external capture input/toggle output pin.
USCI2 data 0 pin.
ADC0_ST
TM0_EXT
USCI2_DAT0
ACMP1_P1
PWM0_BRAKE0
EBI_nWR
I/O
I/O
A
Analog comparator 1 positive input 1 pin.
PWM0 Brake 0 input pin.
I
O
EBI write enable output pin.
INT0
I
External interrupt 0 input pin.
General purpose digital I/O pin.
Timer2 event counter input/toggle output pin.
SPI0 I2S master clock output pin
Timer1 external capture input/toggle output pin.
USCI2 data 1 pin.
9
12 17 PD.3
I/O
I/O
I/O
I/O
I/O
A
TM2
SPI0_I2SMCLK
TM1_EXT
USCI2_DAT1
ACMP1_P0
PWM0_BRAKE1
EBI_MCLK
INT1
Analog comparator 1 positive input 0 pin.
PWM0 Brake 1 input pin.
I
O
EBI external clock output pin.
External interrupt 1 input pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
I
18 PD.4
I/O
I/O
I/O
O
SPI1_CLK
I2C0_SDA
UART2_nRTS
PWM0_BRAKE0
TM0
I2C0 data input/output pin.
UART2 request to Send output pin.
PWM0 Brake 0 input pin.
I
I/O
I/O
O
Timer0 event counter input/toggle output pin.
General purpose digital I/O pin.
Clock Out
19 PD.5
CLKO
SPI1_MISO
I2C0_SCL
UART2_nCTS
I/O
I/O
I
SPI1 MISO (Master In, Slave Out) pin.
I2C0 clock pin.
UART2 clear to Send input pin.
Aug. 08, 2018
Page 28 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
PWM0_BRAKE1
I
MFP5
MFP6
MFP0
MFP2
MFP4
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP0
MFP1
MFP5
MFP8
MFP0
MFP1
MFP5
MFP6
MFP0
MFP5
MFP6
MFP0
MFP4
MFP5
MFP0
MFP4
MFP5
MFP0
MFP1
PWM0 Brake 1 input pin.
TM1
I/O
I/O
I/O
I
Timer1 event counter input/toggle output pin.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
UART2 data receiver input pin.
PWM0 channel 3 output/capture input.
General purpose digital I/O pin.
Clock Out
20 PE.3
SPI1_MOSI
UART2_RXD
PWM0_CH3
I/O
I/O
O
21 PD.6
CLKO
SPI1_SS
I/O
I
SPI1 slave select pin.
UART0_RXD
UART2_TXD
ACMP0_O
PWM0_CH5
EBI_nWR
UART0 data receiver input pin.
UART2 data transmitter output pin.
Analog comparator 0 output pin.
PWM0 channel 5 output/capture input.
EBI write enable output pin.
Power supply by batteries for RTC.
General purpose digital I/O pin.
External 32.768 kHz crystal output pin.
USCI2 control 1 pin.
O
O
I/O
O
10 13 22 VBAT
11 14 23 PF.0
X32_OUT
P
I/O
O
USCI2_CTL1
INT5
I/O
I
External interrupt 5 input pin.
General purpose digital I/O pin.
External 32.768 kHz crystal input pin.
USCI2 control 0 pin.
12 15 24 PF.1
I/O
I
X32_IN
USCI2_CTL0
PWM1_BRAKE0
I/O
I
PWM1 Brake 0 input pin.
13 16 25 PF.2
I/O
I/O
I
General purpose digital I/O pin.
USCI2 clock pin.
USCI2_CLK
PWM1_BRAKE1
PWM1 Brake 1 input pin.
26 PD.10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
Timer2 event counter input/toggle output pin.
USCI2 data 0 pin.
TM2
USCI2_DAT0
27 PD.11
General purpose digital I/O pin.
Timer3 event counter input/toggle output pin.
USCI2 data 1 pin.
TM3
USCI2_DAT1
17 28 PD.12
USCI1_CTL0
General purpose digital I/O pin.
USCI1 control 0 pin.
Aug. 08, 2018
Page 29 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
SPI1_SS
UART0_TXD
PWM1_CH0
EBI_ADR16
I/O
O
MFP2
MFP3
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP0
SPI1 slave select pin.
UART0 data transmitter output pin.
PWM1 channel 0 output/capture input.
EBI address bus bit 16.
I/O
O
18 29 PD.13
USCI1_DAT1
SPI1_MOSI
I/O
I/O
I/O
I
General purpose digital I/O pin.
USCI1 data 1 pin.
SPI1 MOSI (Master Out, Slave In) pin.
UART0 data receiver input pin.
PWM1 channel 1 output/capture input.
EBI address bus bit 17.
UART0_RXD
PWM1_CH1
EBI_ADR17
I/O
O
19 30 PD.14
USCI1_DAT0
SPI1_MISO
I/O
I/O
I/O
I
General purpose digital I/O pin.
USCI1 data 0 pin.
SPI1 MISO (Master In, Slave Out) pin.
UART0 clear to Send input pin.
PWM1 channel 2 output/capture input.
EBI address bus bit 18.
UART0_nCTS
PWM1_CH2
EBI_ADR18
I/O
O
20 31 PD.15
USCI1_CLK
I/O
I/O
I/O
O
General purpose digital I/O pin.
USCI1 clock pin.
SPI1_CLK
SPI1 serial clock pin.
UART0_nRTS
PWM1_CH3
EBI_ADR19
UART0 request to Send output pin.
PWM1 channel 3 output/capture input.
EBI address bus bit 19.
I/O
O
14 21 32 PD.7
USCI1_CTL1
SPI0_I2SMCLK
PWM0_SYNC_IN
TM1
I/O
I/O
I/O
I
General purpose digital I/O pin.
USCI1 control 1 pin.
SPI0 I2S master clock output pin
PWM0 counter synchronous trigger input pin.
Timer1 event counter input/toggle output pin.
Analog comparator 0 output pin.
PWM0 channel 5 output/capture input.
EBI read enable output pin.
I/O
O
ACMP0_O
PWM0_CH5
EBI_nRD
I/O
O
15 22 33 PF.3
XT1_OUT
I/O
O
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
I2C1 clock pin.
I2C1_SCL
I/O
I/O
16 23 34 PF.4
General purpose digital I/O pin.
Aug. 08, 2018
Page 30 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
XT1_IN
I2C1_SDA
I
I/O
P
MFP1
MFP3
MFP0
MFP0
External 4~24 MHz (high speed) crystal input pin.
I2C1 data input/output pin.
17 24 35 VSS
25 36 VDD
Ground pin for digital circuit.
P
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
18 26 37 LDO_CAP
38 PC.9
A
MFP0
MFP0
MFP2
MFP3
MFP4
MFP6
MFP0
MFP2
MFP3
MFP4
MFP6
MFP0
MFP2
MFP4
MFP6
MFP0
MFP2
MFP4
MFP6
MFP0
MFP2
MFP4
MFP6
MFP0
MFP6
MFP0
MFP1
MFP2
MFP3
LDO output pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI0 I2S master clock output pin
I2C1 clock pin.
SPI0_I2SMCLK
I2C1_SCL
USCI2_CTL1
PWM1_CH0
USCI2 control 1 pin.
PWM1 channel 0 output/capture input.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
USCI2 data 1 pin.
39 PC.10
SPI0_MOSI
I2C1_SDA
USCI2_DAT1
PWM1_CH1
PWM1 channel 1 output/capture input.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
USCI2 clock pin.
40 PC.11
SPI0_MISO
USCI2_CLK
PWM1_CH2
PWM1 channel 2 output/capture input.
General purpose digital I/O pin.
SPI0 serial clock pin.
41 PC.12
SPI0_CLK
USCI2_CTL0
PWM1_CH3
USCI2 control 0 pin.
PWM1 channel 3 output/capture input.
General purpose digital I/O pin.
SPI0 slave select pin.
42 PC.13
SPI0_SS
USCI2_DAT0
PWM1_CH4
USCI2 data 0 pin.
PWM1 channel 4 output/capture input.
General purpose digital I/O pin.
PWM1 channel 5 output/capture input.
General purpose digital I/O pin.
Smart Card 0 data pin.
43 PC.14
PWM1_CH5
19 27 44 PC.0
SC0_DAT
SPI0_CLK
SPI0 serial clock pin.
UART2_nCTS
UART2 clear to Send input pin.
Aug. 08, 2018
Page 31 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
USCI0_DAT0
ACMP0_WLAT
PWM0_CH0
EBI_AD8
I/O
I
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
USCI0 data 0 pin.
Analog comparator 0 window latch input pin
PWM0 channel 0 output/capture input.
EBI address/data bus bit 8.
External interrupt 2 input pin.
General purpose digital I/O pin.
Clock Out
I/O
I/O
I
INT2
20 28 45 PC.1
CLKO
I/O
O
SC0_CLK
O
Smart Card 0 clock pin.
UART2_nRTS
USCI0_DAT1
ACMP1_WLAT
PWM0_CH1
EBI_AD9
O
UART2 request to Send output pin.
USCI0 data 1 pin.
I/O
I
Analog comparator 1 window latch input pin
PWM0 channel 1 output/capture input.
EBI address/data bus bit 9.
General purpose digital I/O pin.
Smart Card 0 reset pin.
I/O
I/O
I/O
O
21 29 46 PC.2
SC0_RST
SPI0_SS
I/O
O
SPI0 slave select pin.
UART2_TXD
USCI0_CTL1
ACMP1_O
UART2 data transmitter output pin.
USCI0 control 1 pin.
I/O
O
Analog comparator 1 output pin.
PWM0 channel 2 output/capture input.
EBI address/data bus bit 10.
General purpose digital I/O pin.
Smart Card 0 power pin.
PWM0_CH2
EBI_AD10
I/O
I/O
I/O
O
22 30 47 PC.3
SC0_PWR
SPI0_MOSI
UART2_RXD
USCI0_CTL0
PWM0_CH3
EBI_AD11
I/O
I
SPI0 MOSI (Master Out, Slave In) pin.
UART2 data receiver input pin.
USCI0 control 0 pin.
I/O
I/O
I/O
I/O
I
PWM0 channel 3 output/capture input.
EBI address/data bus bit 11.
General purpose digital I/O pin.
Smart Card 0 card detect pin.
SPI0 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
23 31 48 PC.4
SC0_nCD
SPI0_MISO
I2C1_SCL
I/O
I/O
I/O
I/O
USCI0_CLK
PWM0_CH4
USCI0 clock pin.
PWM0 channel 4 output/capture input.
Aug. 08, 2018
Page 32 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
EBI_AD12
I/O
I/O
I/O
I/O
I/O
I
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP4
MFP5
MFP6
MFP7
MFP0
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
EBI address/data bus bit 12.
General purpose digital I/O pin.
SPI0 serial clock pin.
24
49 PE.0
SPI0_CLK
I2C1_SDA
TM2_EXT
SC0_nCD
PWM0_CH0
EBI_nCS1
INT4
I2C1 data input/output pin.
Timer2 external capture input/toggle output pin.
Smart Card 0 card detect pin.
PWM0 channel 0 output/capture input.
EBI chip select 1 output pin.
External interrupt 4 input pin.
General purpose digital I/O pin.
SPI0 I2S master clock output pin
I2C1 data input/output pin.
USCI0 data 0 pin.
I/O
O
I
32 50 PC.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI0_I2SMCLK
I2C1_SDA
USCI0_DAT0
PWM0_CH5
EBI_AD13
PWM0 channel 5 output/capture input.
EBI address/data bus bit 13.
General purpose digital I/O pin.
USCI0 data 1 pin.
33 51 PC.6
USCI0_DAT1
ACMP1_O
Analog comparator 1 output pin.
PWM1 channel 0 output/capture input.
EBI address/data bus bit 14.
General purpose digital I/O pin.
USCI0 control 1 pin.
PWM1_CH0
EBI_AD14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
34 52 PC.7
USCI0_CTL1
PWM1_CH1
EBI_AD15
PWM1 channel 1 output/capture input.
EBI address/data bus bit 15.
General purpose digital I/O pin.
I2C0 clock pin.
53 PE.4
I2C0_SCL
I2C1_SCL
USCI0_CTL0
SC0_PWR
PWM1_BRAKE0
EBI_nCS0
INT0
I2C1 clock pin.
USCI0 control 0 pin.
Smart Card 0 power pin.
I
PWM1 Brake 0 input pin.
O
EBI chip select 0 output pin.
External interrupt 0 input pin.
General purpose digital I/O pin.
I2C0 data input/output pin.
I
54 PE.5
I2C0_SDA
I/O
I/O
Aug. 08, 2018
Page 33 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
I2C1_SDA
USCI0_CLK
SC0_RST
I/O
I/O
O
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
I2C1 data input/output pin.
USCI0 clock pin.
Smart Card 0 reset pin.
PWM1_BRAKE1
I
PWM1 Brake 1 input pin.
EBI_ALE
INT1
O
EBI address latch enable output pin.
External interrupt 1 input pin.
General purpose digital I/O pin.
Serial wired debugger clock pin.
I2C0 clock pin.
I
25 35 55 PE.6
I/O
I
ICE_CLK
I2C0_SCL
UART0_RXD
I/O
I
UART0 data receiver input pin.
General purpose digital I/O pin.
Serial wired debugger data pin.
I2C0 data input/output pin.
UART0 data transmitter output pin.
General purpose digital I/O pin.
Clock Out
26 36 56 PE.7
I/O
O
ICE_DAT
I2C0_SDA
UART0_TXD
I/O
O
57 PA.8
I/O
O
CLKO
I2C1_SCL
UART1_TXD
SC0_PWR
SC1_RST
TM_BRAKE0
PWM0_BRAKE0
TM1
I/O
O
I2C1 clock pin.
UART1 data transmitter output pin.
Smart Card 0 power pin.
O
O
Smart Card 1 reset pin.
I
Timer Brake 0 input pin.
I
PWM0 Brake 0 input pin.
I/O
I/O
I/O
I/O
I
Timer1 event counter input/toggle output pin.
General purpose digital I/O pin.
SPI1 I2S master clock output pin
I2C1 data input/output pin.
UART1 data receiver input pin.
Smart Card 0 reset pin.
58 PA.9
SPI1_I2SMCLK
I2C1_SDA
UART1_RXD
SC0_RST
O
SC1_PWR
TM_BRAKE1
PWM1_BRAKE1
TM2
O
Smart Card 1 power pin.
I
Timer Brake 1 input pin.
I
PWM1 Brake 1 input pin.
I/O
I/O
I/O
Timer2 event counter input/toggle output pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
59 PA.7
SPI1_CLK
Aug. 08, 2018
Page 34 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
TM0_EXT
TM_BRAKE1
EBI_AD7
I/O
I
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP7
MFP0
MFP0
Timer0 external capture input/toggle output pin.
Timer Brake 1 input pin.
I/O
I/O
I/O
I/O
I
EBI address/data bus bit 7.
60 PA.6
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
Timer1 external capture input/toggle output pin.
Timer Brake 2 input pin.
SPI1_MISO
TM1_EXT
TM_BRAKE2
EBI_AD6
I/O
I/O
I/O
I/O
I
EBI address/data bus bit 6.
61 PA.5
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
Timer2 external capture input/toggle output pin.
Timer Brake 3 input pin.
SPI1_MOSI
TM2_EXT
TM_BRAKE3
EBI_AD5
I/O
I/O
I/O
I/O
I/O
P
EBI address/data bus bit 5.
62 PA.4
General purpose digital I/O pin.
SPI1 slave select pin.
SPI1_SS
TM3_EXT
EBI_AD4
Timer3 external capture input/toggle output pin.
EBI address/data bus bit 4.
63 VSS
Ground pin for digital circuit.
64 VDD
P
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
65 PE.1
TM3_EXT
SC0_nCD
PWM0_CH1
37 66 PE.8
UART1_TXD
TM0
I/O
I/O
I
MFP0
MFP3
MFP5
MFP6
MFP0
MFP1
MFP3
MFP4
MFP5
MFP0
MFP1
MFP3
MFP4
MFP5
General purpose digital I/O pin.
Timer3 external capture input/toggle output pin.
Smart Card 0 card detect pin.
PWM0 channel 1 output/capture input.
General purpose digital I/O pin.
UART1 data transmitter output pin.
Timer0 event counter input/toggle output pin.
I2C1 clock pin.
I/O
I/O
O
I/O
I/O
O
I2C1_SCL
SC0_PWR
38 67 PE.9
UART1_RXD
TM1
Smart Card 0 power pin.
I/O
I
General purpose digital I/O pin.
UART1 data receiver input pin.
Timer1 event counter input/toggle output pin.
I2C1 data input/output pin.
I/O
I/O
O
I2C1_SDA
SC0_RST
Smart Card 0 reset pin.
Aug. 08, 2018
Page 35 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
27 39 68 PE.10
SPI1_MISO
SPI0_MISO
UART1_nCTS
SC0_DAT
I/O
I/O
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
MFP0
MFP0
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI0 MISO (Master In, Slave Out) pin.
UART1 clear to Send input pin.
Smart Card 0 data pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI1_CLK
SPI1 serial clock pin.
EBI_AD7
EBI address/data bus bit 7.
TM0_EXT
Timer0 external capture input/toggle output pin.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI0 MOSI (Master Out, Slave In) pin.
UART1 request to Send output pin.
Smart Card 0 clock pin.
28 40 69 PE.11
SPI1_MOSI
SPI0_MOSI
UART1_nRTS
SC0_CLK
O
SPI1_MISO
EBI_AD6
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI1 MISO (Master In, Slave Out) pin.
EBI address/data bus bit 6.
TM1_EXT
Timer1 external capture input/toggle output pin.
General purpose digital I/O pin.
SPI1 slave select pin.
29 41 70 PE.12
SPI1_SS
SPI0_SS
SPI0 slave select pin.
UART1_TXD
I2C0_SCL
UART1 data transmitter output pin.
I2C0 clock pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SPI1_MOSI
EBI_AD5
SPI1 MOSI (Master Out, Slave In) pin.
EBI address/data bus bit 5.
TM2_EXT
Timer2 external capture input/toggle output pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
30 42 71 PE.13
SPI1_CLK
SPI0_CLK
SPI0 serial clock pin.
UART1_RXD
I2C0_SDA
UART1 data receiver input pin.
I2C0 data input/output pin.
I/O
I/O
I/O
I/O
P
SPI1_SS
SPI1 slave select pin.
EBI_AD4
EBI address/data bus bit 4.
TM3_EXT
Timer3 external capture input/toggle output pin.
Power supply for PE.1, PE.8~PE.13.
Power supply from USB host or HUB.
31 43 72 VDDIO
32 44 73 USB_VBUS
P
Aug. 08, 2018
Page 36 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
33 45 74 USB_D-
34 46 75 USB_D+
35 47 76 PF.7
36 48 77 USB_VDD33_CAP
78 PB.12
A
A
MFP0
MFP0
MFP0
MFP0
MFP0
MFP6
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
USB differential signal D+.
USB differential signal D-.
I/O
A
General purpose digital I/O pin.
Internal power regulator output 3.3V decoupling pin.
General purpose digital I/O pin.
PWM1 channel 1 output/capture input.
General purpose digital I/O pin.
UART0 data receiver input pin.
UART0 request to Send output pin.
I2C0 clock pin.
I/O
I/O
I/O
I
PWM1_CH1
37 49 79 PA.3
UART0_RXD
UART0_nRTS
I2C0_SCL
O
I/O
O
SC0_PWR
Smart Card 0 power pin.
PWM1_CH2
I/O
I/O
I/O
I/O
O
PWM1 channel 2 output/capture input.
EBI address/data bus bit 3.
USCI1 clock pin.
EBI_AD3
USCI1_CLK
38 50 80 PA.2
UART0_TXD
General purpose digital I/O pin.
UART0 data transmitter output pin.
UART0 clear to Send input pin.
I2C0 data input/output pin.
UART0_nCTS
I2C0_SDA
I
I/O
O
SC0_RST
Smart Card 0 reset pin.
PWM1_CH3
I/O
I/O
I/O
I/O
O
PWM1 channel 3 output/capture input.
EBI address/data bus bit 2.
USCI1 control 0 pin.
EBI_AD2
USCI1_CTL0
39 51 81 PA.1
UART1_nRTS
UART1_RXD
USCI1_CTL1
SC0_DAT
General purpose digital I/O pin.
UART1 request to Send output pin.
UART1 data receiver input pin.
USCI1 control 1 pin.
I
I/O
I/O
I/O
I/O
I/O
I
Smart Card 0 data pin.
PWM1_CH4
PWM1 channel 4 output/capture input.
EBI address/data bus bit 1.
General purpose digital I/O pin.
UART1 clear to Send input pin.
UART1 data transmitter output pin.
USCI1 control 0 pin.
EBI_AD1
40 52 82 PA.0
UART1_nCTS
UART1_TXD
O
USCI1_CTL0
SC0_CLK
I/O
O
Smart Card 0 clock pin.
Aug. 08, 2018
Page 37 of 140
Rev 1.04
NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
PWM1_CH5
EBI_AD0
I/O
I/O
I
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP6
MFP0
MFP3
MFP4
MFP6
MFP0
MFP3
MFP4
MFP6
MFP0
MFP3
MFP4
MFP6
MFP0
MFP0
PWM1 channel 5 output/capture input.
EBI address/data bus bit 0.
INT0
External interrupt 0 input pin.
General purpose digital I/O pin.
SPI1 I2S master clock output pin
UART2 data receiver input pin.
UART1 data receiver input pin.
Timer Brake 2 input pin.
83 PA.12
I/O
I/O
I
SPI1_I2SMCLK
UART2_RXD
UART1_RXD
TM_BRAKE2
84 PA.13
I
I
I/O
O
General purpose digital I/O pin.
UART2 data transmitter output pin.
UART1 data transmitter output pin.
Timer Brake 3 input pin.
UART2_TXD
UART1_TXD
TM_BRAKE3
85 PA.14
O
I
I/O
I
General purpose digital I/O pin.
UART2 clear to Send input pin.
USCI1 control 1 pin.
UART2_nCTS
USCI1_CTL1
TM2
I/O
I/O
I/O
O
Timer2 event counter input/toggle output pin.
General purpose digital I/O pin.
UART2 request to Send output pin.
USCI1 clock pin.
86 PA.15
UART2_nRTS
USCI1_CLK
TM3
I/O
I/O
P
Timer3 event counter input/toggle output pin.
Ground pin for digital circuit.
53 87 VSS
41 54 88 VDD
P
Power supply for I/O ports and LDO source for internal PLL
and digital circuit.
42 55 89 AVDD
43 56 90 VREF
P
A
MFP0
MFP0
Power supply for internal analog circuit.
ADC reference voltage input.
Note: This pin needs to be connected with a 1uF capacitor.
44 57 91 PB.0
ADC0_CH0
VDET_P0
UART2_RXD
TM2
I/O
A
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
General purpose digital I/O pin.
ADC0 channel 0 analog input.
Voltage detector positive input 0 pin.
UART2 data receiver input pin.
Timer2 event counter input/toggle output pin.
USCI1 data 0 pin.
A
I
I/O
I/O
O
USCI1_DAT0
EBI_nWRL
INT1
EBI low byte write enable output pin.
External interrupt 1 input pin.
I
TM1_EXT
I/O
MFP10 Timer1 external capture input/toggle output pin.
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48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
45 58 92 PB.1
ADC0_CH1
VDET_P1
I/O
A
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
General purpose digital I/O pin.
ADC0 channel 1 analog input.
Voltage detector positive input 1 pin.
UART2 data transmitter output pin.
Timer3 event counter input/toggle output pin.
Smart Card 0 reset pin.
A
UART2_TXD
TM3
O
I/O
O
SC0_RST
PWM0_SYNC_OUT
O
PWM0 counter synchronous trigger output pin.
EBI high byte write enable output pin
USCI1 data 1 pin.
EBI_nWRH
O
USCI1_DAT1
I/O
I/O
A
46 59 93 PB.2
General purpose digital I/O pin.
ADC0 channel 2 analog input.
SPI0 serial clock pin.
ADC0_CH2
SPI0_CLK
SPI1_CLK
UART1_RXD
SC0_nCD
I/O
I/O
I
SPI1 serial clock pin.
UART1 data receiver input pin.
Smart Card 0 card detect pin.
Timer Brake 0 input pin.
I
TM_BRAKE0
EBI_nCS0
USCI0_DAT0
TM2_EXT
I
O
EBI chip select 0 output pin.
USCI0 data 0 pin.
I/O
I/O
I/O
A
MFP10 Timer2 external capture input/toggle output pin.
47 60 94 PB.3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
General purpose digital I/O pin.
ADC0 channel 3 analog input.
SPI0 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
UART1 data transmitter output pin.
Timer Brake 1 input pin.
ADC0_CH3
SPI0_MISO
SPI1_MISO
UART1_TXD
TM_BRAKE1
EBI_ALE
I/O
I/O
O
I
O
EBI address latch enable output pin.
USCI0 data 1 pin.
USCI0_DAT1
TM0_EXT
I/O
I/O
I/O
A
MFP10 Timer0 external capture input/toggle output pin.
48 61 95 PB.4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
General purpose digital I/O pin.
ADC0 channel 4 analog input.
SPI0 slave select pin.
ADC0_CH4
SPI0_SS
I/O
I/O
I
SPI1_SS
SPI1 slave select pin.
UART1_nCTS
ACMP0_N
UART1 clear to Send input pin.
Analog comparator 0 negative input pin.
A
Aug. 08, 2018
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NUC126
48 64 100 Pin Name
Pin Pin Pin
Type
MFP*
Description
SC1_nCD
EBI_AD7
I
MFP6
MFP7
MFP8
MFP9
Smart Card 1 card detect pin.
EBI address/data bus bit 7.
USCI0 control 1 pin.
I/O
I/O
I
USCI0_CTL1
UART2_RXD
TM1_EXT
UART2 data receiver input pin.
I/O
I/O
A
MFP10 Timer1 external capture input/toggle output pin.
62 96 PB.8
ADC0_CH5
UART1_nRTS
TM_BRAKE2
PWM0_CH2
USCI0_CTL0
97 PB.9
MFP0
MFP1
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP4
MFP5
MFP6
MFP8
General purpose digital I/O pin.
ADC0 channel 5 analog input.
UART1 request to Send output pin.
Timer Brake 2 input pin.
O
I
I/O
I/O
I/O
A
PWM0 channel 2 output/capture input.
USCI0 control 0 pin.
General purpose digital I/O pin.
ADC0 channel 6 analog input.
USCI0 clock pin.
ADC0_CH6
USCI0_CLK
98 PB.10
I/O
I/O
A
General purpose digital I/O pin.
ADC0 channel 7 analog input.
General purpose digital I/O pin.
ADC0 channel 8 analog input.
General purpose digital I/O pin.
ADC0 channel 9 analog input.
UART1 request to Send output pin.
Timer Brake 3 input pin.
ADC0_CH7
63 99 PB.11
ADC0_CH8
64 100 PE.2
ADC0_CH9
UART1_nRTS
TM_BRAKE3
PWM0_CH2
USCI0_CTL0
I/O
A
I/O
A
O
I
I/O
I/O
PWM0 channel 2 output/capture input.
USCI0 control 0 pin.
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4.3.2 GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GP0_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GP0_MFPH[7:4]=0x5.
Group
Pin Name
GPIO
PB.4
PD.6
PD.7
PB.7
PB.6
PB.5
PB.15
PC.0
PD.0
PC.2
PC.6
PD.3
PD.2
PD.1
PD.9
PC.1
PB.0
PB.1
PB.2
PB.3
PB.4
PB.8
PB.9
PB.10
PB.11
PE.2
PB.13
PB.14
PB.15
PB.5
PB.6
MFP*
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
Type
A
O
O
A
A
A
A
I
Description
ACMP0_N
Analog comparator 0 negative input pin.
ACMP0_O
Analog comparator 0 output pin.
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP0_WLAT
ACMP1_N
Analog comparator 0 positive input 0 pin.
Analog comparator 0 positive input 1 pin.
Analog comparator 0 positive input 2 pin.
Analog comparator 0 positive input 3 pin.
Analog comparator 0 window latch input pin
Analog comparator 1 negative input pin.
ACMP0
A
O
O
A
A
A
A
I
ACMP1_O
Analog comparator 1 output pin.
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP1_WLAT
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
ADC0_CH8
ADC0_CH9
ADC0_CH10
ADC0_CH11
ADC0_CH12
ADC0_CH13
ADC0_CH14
Analog comparator 1 positive input 0 pin.
Analog comparator 1 positive input 1 pin.
Analog comparator 1 positive input 2 pin.
Analog comparator 1 positive input 3 pin.
Analog comparator 1 window latch input pin
ADC0 channel 0 analog input.
ACMP1
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
ADC0 channel 1 analog input.
ADC0 channel 2 analog input.
ADC0 channel 3 analog input.
ADC0 channel 4 analog input.
ADC0 channel 5 analog input.
ADC0 channel 6 analog input.
ADC0
ADC0 channel 7 analog input.
ADC0 channel 8 analog input.
ADC0 channel 9 analog input.
ADC0 channel 10 analog input.
ADC0 channel 11 analog input.
ADC0 channel 12 analog input.
ADC0 channel 13 analog input.
ADC0 channel 14 analog input.
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Group
Pin Name
GPIO
PB.7
PC.8
PD.8
PD.9
PD.1
PD.2
PD.5
PD.6
PA.8
PC.1
PA.0
PA.1
PA.2
PA.3
PB.7
PA.4
PE.13
PB.6
PA.5
PE.12
PB.5
PA.6
PE.11
PA.7
PE.10
PB.4
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PC.6
PC.7
MFP*
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
Type
A
Description
ADC0_CH15
ADC0_CH16
ADC0_CH17
ADC0_CH18
ADC0_CH19
ADC0_ST
ADC0 channel 15 analog input.
ADC0 channel 16 analog input.
ADC0 channel 17 analog input.
ADC0 channel 18 analog input.
ADC0 channel 19 analog input.
ADC0 external trigger input pin.
A
A
A
A
I
O
O
CLKO
CLKO
Clock Out
O
O
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EBI address/data bus bit 0.
EBI address/data bus bit 1.
EBI address/data bus bit 2.
EBI address/data bus bit 3.
EBI_AD4
EBI_AD5
EBI_AD6
EBI_AD7
EBI address/data bus bit 4.
EBI address/data bus bit 5.
EBI address/data bus bit 6.
EBI address/data bus bit 7.
EBI
EBI_AD8
EBI address/data bus bit 8.
EBI address/data bus bit 9.
EBI address/data bus bit 10.
EBI address/data bus bit 11.
EBI address/data bus bit 12.
EBI address/data bus bit 13.
EBI address/data bus bit 14.
EBI address/data bus bit 15.
EBI_AD9
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
EBI_AD14
EBI_AD15
Aug. 08, 2018
Page 42 of 140
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NUC126
Group
Pin Name
GPIO
PD.12
PD.13
PD.14
PD.15
PD.9
PE.5
PB.3
PD.3
PD.8
PE.4
PB.2
PB.15
PE.0
PD.1
PD.7
PD.2
PD.6
PB.1
PB.0
PD.5
PE.4
PE.6
PE.12
PA.3
PD.4
PE.5
PE.7
PE.13
PA.2
PF.3
PC.9
PC.4
PE.4
PA.8
MFP*
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP3
MFP2
MFP2
MFP4
MFP4
MFP3
MFP2
MFP2
MFP4
MFP4
MFP3
MFP3
MFP3
MFP3
MFP2
Type
O
Description
EBI_ADR16
EBI_ADR17
EBI_ADR18
EBI_ADR19
EBI address bus bit 16.
EBI address bus bit 17.
EBI address bus bit 18.
EBI address bus bit 19.
O
O
O
O
EBI_ALE
O
EBI address latch enable output pin.
EBI external clock output pin.
EBI chip select 0 output pin.
O
EBI_MCLK
EBI_nCS0
O
O
O
O
O
EBI_nCS1
EBI_nRD
EBI_nWR
EBI chip select 1 output pin.
EBI read enable output pin.
EBI write enable output pin.
O
O
O
O
O
EBI_nWRH
EBI_nWRL
O
EBI high byte write enable output pin
EBI low byte write enable output pin.
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C0 clock pin.
I2C0
I2C0 data input/output pin.
I2C1
I2C1 clock pin.
Aug. 08, 2018
Page 43 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PE.8
PF.4
PC.10
PE.0
PC.5
PE.5
PA.9
PE.9
PE.6
PE.7
PD.2
PE.4
PA.0
PD.3
PE.5
PB.0
PC.0
PD.0
PE.0
PF.0
PD.2
PD.4
PA.8
PD.3
PD.5
PC.0
PE.0
PC.1
PE.1
PC.2
PB.8
PE.2
PE.3
PC.3
MFP*
MFP4
MFP3
MFP3
MFP3
MFP3
MFP3
MFP2
MFP4
MFP1
MFP1
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP6
MFP5
MFP7
MFP6
MFP5
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
Type
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I2C1_SDA
I2C1 data input/output pin.
ICE_CLK
ICE_DAT
Serial wired debugger clock pin.
Serial wired debugger data pin.
ICE
O
I
INT0
INT0
INT1
I
External interrupt 0 input pin.
External interrupt 1 input pin.
I
I
INT1
I
I
INT2
INT3
INT4
INT5
INT2
INT3
INT4
INT5
I
External interrupt 2 input pin.
External interrupt 3 input pin.
External interrupt 4 input pin.
External interrupt 5 input pin.
I
I
I
I
PWM0_BRAKE0
I
PWM0 Brake 0 input pin.
I
I
PWM0_BRAKE1
PWM0_CH0
PWM0 Brake 1 input pin.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM0 channel 0 output/capture input.
PWM0 channel 1 output/capture input.
PWM0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0 channel 2 output/capture input.
PWM0 channel 3 output/capture input.
Aug. 08, 2018
Page 44 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PC.4
PD.6
PD.7
PC.5
PD.1
PD.7
PB.1
MFP*
MFP6
MFP6
MFP6
MFP6
MFP2
MFP3
MFP6
MFP6
MFP6
MFP6
MFP6
MFP7
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP2
MFP5
MFP5
MFP1
MFP5
Type
I/O
I/O
I/O
I/O
I
Description
PWM0_CH4
PWM0 channel 4 output/capture input.
PWM0_CH5
PWM0 channel 5 output/capture input.
PWM0_SYNC_IN
PWM0_SYNC_OUT
PWM1_BRAKE0
PWM0 counter synchronous trigger input pin.
PWM0 counter synchronous trigger output pin.
PWM1 Brake 0 input pin.
I
O
PF.1
I
PE.4
I
PF.2
I
PWM1_BRAKE1
PWM1_CH0
PE.5
I
PWM1 Brake 1 input pin.
PA.9
I
PD.12
PC.9
PC.6
PD.13
PC.10
PC.7
PB.12
PD.14
PC.11
PA.3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PWM1 channel 0 output/capture input.
PWM1_CH1
PWM1 channel 1 output/capture input.
PWM1
PWM1_CH2
PWM1_CH3
PWM1 channel 2 output/capture input.
PWM1 channel 3 output/capture input.
PD.15
PC.12
PA.2
PC.13
PA.1
PWM1_CH4
PWM1_CH5
PWM1 channel 4 output/capture input.
PWM1 channel 5 output/capture input.
PC.14
PA.0
PC.1
PE.11
PA.0
SC0_CLK
SC0_DAT
O
Smart Card 0 clock pin.
Smart Card 0 data pin.
SC0
O
PC.0
PE.10
I/O
I/O
Aug. 08, 2018
Page 45 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PA.1
PC.3
PE.4
PE.8
PA.3
PA.8
PC.2
PE.5
PE.9
PA.2
PB.1
PA.9
PC.4
PE.0
PE.1
PB.2
PD.0
MFP*
MFP5
MFP1
MFP5
MFP5
MFP5
MFP4
MFP1
MFP5
MFP5
MFP5
MFP5
MFP4
MFP1
MFP5
MFP5
MFP5
MFP6
Type
I/O
O
O
O
O
O
O
O
O
O
O
O
I
Description
SC0_PWR
Smart Card 0 power pin.
SC0_RST
Smart Card 0 reset pin.
I
SC0_nCD
Smart Card 0 card detect pin.
I
I
SC1_CLK
SC1_DAT
O
Smart Card 1 clock pin.
Smart Card 1 data pin.
PB.7
MFP6
I/O
PB.6
PA.9
PB.5
PA.8
PB.4
PB.7
PC.12
PC.0
PE.0
PE.13
PB.2
PD.0
PD.3
PD.7
PC.9
PC.5
MFP6
MFP5
MFP6
MFP5
MFP6
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP1
MFP2
MFP2
MFP2
MFP2
O
SC1_PWR
Smart Card 1 power pin.
SC1
O
O
SC1_RST
SC1_nCD
Smart Card 1 reset pin.
O
I
Smart Card 1 card detect pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI0_CLK
SPI0 serial clock pin.
SPI0
SPI0_I2SMCLK
SPI0 I2S master clock output pin
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Rev 1.04
NUC126
Group
Pin Name
GPIO
PB.6
MFP*
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP3
MFP2
MFP2
MFP2
MFP6
MFP1
MFP3
MFP2
MFP1
MFP2
MFP3
MFP2
MFP2
MFP2
MFP1
MFP6
MFP3
MFP3
MFP2
MFP2
MFP2
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
PC.11
PC.4
PE.10
PB.3
SPI0_MISO
SPI0 MISO (Master In, Slave Out) pin.
PB.5
PC.10
PC.3
PE.11
PC.13
PC.2
PE.12
PB.4
SPI0_MOSI
SPI0 MOSI (Master Out, Slave In) pin.
SPI0_SS
SPI0 slave select pin.
PB.7
PD.4
PD.15
PA.7
SPI1_CLK
SPI1 serial clock pin.
PE.10
PE.13
PB.2
PD.0
PA.9
SPI1_I2SMCLK
SPI1 I2S master clock output pin
PA.12
PB.6
SPI1
PD.5
PD.14
PA.6
SPI1_MISO
SPI1 MISO (Master In, Slave Out) pin.
PE.10
PE.11
PB.3
PB.5
PE.3
SPI1_MOSI
SPI1 MOSI (Master Out, Slave In) pin.
PD.13
PA.5
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Page 47 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PE.11
PE.12
PD.6
PD.12
PA.4
PE.12
PE.13
PB.4
PD.1
PD.4
PE.8
PD.2
PA.7
PE.10
PB.3
PD.5
PD.7
PA.8
PE.9
PD.3
PA.6
PE.11
PB.0
PB.4
PD.8
PD.3
PD.10
PA.14
PA.9
PB.0
PE.0
PA.5
PE.12
PB.2
MFP*
MFP1
MFP6
MFP2
MFP2
MFP2
MFP1
MFP6
MFP3
MFP6
MFP6
MFP3
MFP3
MFP3
MFP8
MFP10
MFP6
MFP4
MFP8
MFP3
MFP3
MFP3
MFP8
MFP10
MFP10
MFP6
MFP1
MFP4
MFP6
MFP8
MFP4
MFP4
MFP3
MFP8
MFP10
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
SPI1_SS
SPI1 slave select pin.
TM0
Timer0 event counter input/toggle output pin.
TM0
Timer0 external capture input/toggle output
pin.
TM0_EXT
TM1
Timer1 event counter input/toggle output pin.
\TM1
Timer1 external capture input/toggle output
pin.
TM1_EXT
TM2
Timer2 event counter input/toggle output pin.
TM2
Timer2 external capture input/toggle output
pin.
TM2_EXT
Aug. 08, 2018
Page 48 of 140
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NUC126
Group
Pin Name
GPIO
PD.9
PD.11
PA.15
PB.1
PA.4
PE.1
PE.13
PA.8
PB.2
PA.9
PA.7
PB.3
PA.6
PA.12
PB.8
PA.5
PA.13
PE.2
PD.0
PD.9
PD.6
PD.13
PE.6
PA.3
PD.1
PD.12
PE.7
PA.2
PD.8
PD.14
PA.2
PC.8
PD.15
PA.3
MFP*
MFP6
MFP4
MFP6
MFP4
MFP3
MFP3
MFP8
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP5
MFP6
MFP6
MFP5
MFP3
MFP3
MFP3
MFP3
MFP3
MFP2
MFP3
MFP3
MFP3
MFP2
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
Type
Description
I/O
I/O
TM3
Timer3 event counter input/toggle output pin.
I/O
I/O
TM3
I/O
Timer3 external capture input/toggle output
pin.
TM3_EXT
I/O
I/O
I
TM_BRAKE0
TM_BRAKE1
Timer Brake 0 input pin.
Timer Brake 1 input pin.
I
I
I
I
TM
I
TM_BRAKE2
TM_BRAKE3
I
Timer Brake 2 input pin.
Timer Brake 3 input pin.
I
I
I
I
I
I
I
UART0_RXD
UART0 data receiver input pin.
I
I
I
O
O
O
O
I
UART0
UART0_TXD
UART0 data transmitter output pin.
UART0_nCTS
UART0_nRTS
I
UART0 clear to Send input pin.
UART0 request to Send output pin.
Rev 1.04
I
O
O
O
Aug. 08, 2018
Page 49 of 140
NUC126
Group
Pin Name
GPIO
PA.9
PE.9
PE.13
PA.1
PA.12
PB.2
PA.8
PE.8
PE.12
PA.0
PA.13
PB.3
PE.10
PA.0
PB.4
MFP*
MFP3
MFP1
MFP3
MFP3
MFP4
MFP4
MFP3
MFP1
MFP3
MFP3
MFP4
MFP4
MFP3
MFP1
MFP4
Type
Description
I
I
I
UART1_RXD
UART1 data receiver input pin.
I
I
I
O
O
O
O
O
O
I
UART1_TXD
UART1 data transmitter output pin.
UART1
UART1_nCTS
UART1_nRTS
UART1 clear to Send input pin.
I
I
PE.11
MFP3
O
PA.1
PB.8
PE.2
PE.3
PC.3
PA.12
PB.0
PD.6
PC.2
PA.13
PB.1
PB.4
PB.5
PD.5
PC.0
PA.14
PD.4
PC.1
MFP1
MFP4
MFP4
MFP4
MFP3
MFP3
MFP3
MFP4
MFP3
MFP3
MFP3
MFP9
MFP9
MFP4
MFP3
MFP3
MFP4
MFP3
O
O
O
I
UART1 request to Send output pin.
I
UART2_RXD
UART2 data receiver input pin.
I
I
O
O
O
O
O
O
I
UART2_TXD
UART2 data transmitter output pin.
UART2
UART2_nCTS
UART2_nRTS
I
UART2 clear to Send input pin.
I
O
O
UART2 request to Send output pin.
Aug. 08, 2018
Page 50 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PA.15
PC.4
PE.5
PB.9
PC.3
PE.4
PB.8
PE.2
PC.2
PC.7
PB.4
PC.0
PC.5
PB.2
PC.1
PC.6
PB.3
PD.15
PA.3
PA.15
PD.12
PA.2
PA.0
PD.7
PA.1
PA.14
PD.14
PB.0
PD.13
PB.1
PD.1
PF.2
PC.11
PD.0
MFP*
MFP3
MFP5
MFP4
MFP8
MFP5
MFP4
MFP8
MFP8
MFP4
MFP4
MFP8
MFP4
MFP4
MFP8
MFP4
MFP4
MFP8
MFP1
MFP8
MFP4
MFP1
MFP8
MFP4
MFP1
MFP4
MFP4
MFP1
MFP6
MFP1
MFP8
MFP4
MFP5
MFP4
MFP4
Type
O
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USCI0_CLK
USCI0 clock pin.
USCI0_CTL0
USCI0 control 0 pin.
USCI0
USCI0_CTL1
USCI0_DAT0
USCI0_DAT1
USCI1_CLK
USCI1_CTL0
USCI1_CTL1
USCI0 control 1 pin.
USCI0 data 0 pin.
USCI0 data 1 pin.
USCI1 clock pin.
USCI1 control 0 pin.
USCI1 control 1 pin.
USCI1
USCI1_DAT0
USCI1_DAT1
USCI1 data 0 pin.
USCI1 data 1 pin.
USCI2_CLK
USCI2_CTL0
USCI2 clock pin.
USCI2
USCI2 control 0 pin.
Aug. 08, 2018
Page 51 of 140
Rev 1.04
NUC126
Group
Pin Name
GPIO
PD.9
PF.1
MFP*
MFP4
MFP5
MFP4
MFP4
MFP4
MFP5
MFP4
MFP4
MFP5
MFP4
MFP4
MFP5
MFP4
MFP2
MFP2
MFP1
MFP1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
Description
PC.12
PB.7
PD.8
PF.0
USCI2_CTL1
USCI2 control 1 pin.
PC.9
PD.2
PD.10
PC.13
PD.3
PD.11
PC.10
PB.0
PB.1
PF.1
USCI2_DAT0
USCI2_DAT1
USCI2 data 0 pin.
USCI2 data 1 pin.
VDET_P0
VDET_P1
X32_IN
Voltage detector positive input 0 pin.
Voltage detector positive input 1 pin.
External 32.768 kHz crystal input pin.
External 32.768 kHz crystal output pin.
VDET
X32
A
I
X32_OUT
PF.0
O
External 4~24 MHz (high speed) crystal input
pin.
XT1_IN
PF.4
PF.3
MFP1
MFP1
I
XT1
External 4~24 MHz (high speed) crystal output
pin.
XT1_OUT
O
Table 4.3-1 NUC126 GPIO Multi-function Table
Aug. 08, 2018
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NUC126
5 BLOCK DIAGRAM
5.1 NuMicro® NUC126 Block Diagram
Analog Interface
12-bit ADC 20-ch
RTC / PWM / Timer
RTC (VBAT
Speed Up
Memory
APROM
256/128KB
LDROM
4 KB
)
PDMA-5ch
ARM
Cortex-M0
72 MHz
Watchdog Timer
DataFlash
Configurable
SRAM
20 KB
Hard Divider
CRC
Analog
Comparator x 2
Timer/PWM X4
PWM 12-ch
SPROM
2 KB
Bridge
AHB Bus
APB Bus
Power Control
Connectivity
UART x 3
SPI/I2S x2
I2Cx2
Clock Control
PLL
I/O Ports
General Purpose
I/O
LDO 1.8V
High Speed
Oscillator
48 MHz
High Speed
Crystal Osc.(HXT)
4 ~ 24 MHz
External
Interrupt
POR LVR BOR
High Speed
Oscillator
22.1184 MHz
Low Speed
Oscillator(LIRC)
10 kHz
External Bus
Interface
ISO-7816-3 x2
USCI x3
VREF
(2.048V/2.56V/
3.072V/4.96V)
Low Speed
Crystal Osc.(LXT)
32.768 kHz
USB 2.0 FS
Figure 5.1-1 NuMicro® NUC126 Block Diagram
Aug. 08, 2018
Page 53 of 140
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NUC126
6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes –Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6.1-1 shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Debug
Interrupts
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
Unit
Cortex-M0
Processor
Core
Wakeup
Interrupt
Controller
(WIC)
Debug
Access Port
(DAP)
Debugger
interface
Bus matrix
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 6.1-1 Functional Block Diagram
The implemented device provides:
A low gate count processor:
– ARMv6-M Thumb® instruction set
– Thumb-2 technology
– ARMv6-M compliant 24-bit SysTick timer
– A 32-bit hardware multiplier
– System interface supported with little-endian data accesses
– Ability to have deterministic, fixed-latency, interrupt handling
– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
– C Application Binary Interface compliant exception model. This is the ARMv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use of
pure C functions as interrupt handlers
– Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
Aug. 08, 2018
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NUC126
NVIC:
– 32 external interrupt inputs, each with four levels of priority
– Dedicated Non-maskable Interrupt (NMI) input
– Supports for both level-sensitive and pulse-sensitive interrupt lines
– Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Debug support:
– Four hardware breakpoints
– Two watchpoints
– Program Counter Sampling Register (PCSR) for non-intrusive code profiling
– Single step and vector catch capabilities
Bus interfaces:
– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
– Single 32-bit slave port that supports the DAP (Debug Access Port)
Aug. 08, 2018
Page 55 of 140
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NUC126
6.2 System Manager
6.2.1 Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for
System Reset
Power Modes and Wake-up Sources
System Power Distribution
SRAM Memory organization
System Control Register for Part Number ID, Chip Reset and Multi-function Pin
Control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2 System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset sourcces are
from peripheral signals. Software reset can trigger reset through setting control registers.
Hardware Reset Sources
–
–
–
–
–
–
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
CPU Lockup Reset
Software Reset Sources
–
–
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
–
CPU Reset for Cortex® -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1])
Aug. 08, 2018
Page 56 of 140
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NUC126
Glitch Filter
~36 us
nRESET
~50k ohm
@5v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
~3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
Reset Controller
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
Aug. 08, 2018
Page 57 of 140
Rev 1.04
NUC126
There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6.2-1.
Reset Sources
Register
POR
NRESET WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
SYS_RSTSTS
0x01
0x0
Bit 1 = 1
-
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
0x1
(CLK_APBCLK0[0])
HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
Aug. 08, 2018
Page 58 of 140
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NUC126
WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
BL
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1]]
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
VECMAP
Reload
base on
Reload
base on
Reload
base on
Reload
base on base on
Reload
-
Reload
base on
CONFIG0
-
-
-
(FMC_ISPSTS[23:9])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Peripheral
Reset Value
Other
Registers
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be reset.
The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7
VDD and the state keeps longer than 36 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set
to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
nRESET
0.7 VDD
36 us
0.2 VDD
36 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
Aug. 08, 2018
Page 59 of 140
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NUC126
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system
to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to
MCU, the POR module will detect the rising voltage and generate reset signal to system until the
voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to
indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1
to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until
the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by
LVRDGSEL (SYS_BODCTL[14:12]). The default setting of Low Voltage Reset is enabled without
De-glitch function. Figure 6.2-4 shows the Low Voltage Reset waveform.
Aug. 08, 2018
Page 60 of 140
Rev 1.04
NUC126
AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD which is decided by BODEN
(SYS_BODCTL[0]) and BODVL (SYS_BODCTL[2:1]) and the state keeps longer than De-glitch
time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the
chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-
glitch time set by BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and
BODRSTEN (SYS_BODCTL[3]) is set by flash controller user configuration register CBODEN
(CONFIG0 [23]), CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can
determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-
out Detector waveform.
Aug. 08, 2018
Page 61 of 140
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NUC126
AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may cause
the watchdog time-out. User may decide to enable system reset during watchdog time-out to
recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives
immediate indication of seriously errant kernel software. This is the result of the CPU being locked
because of an unrecoverable exception following the activation of the processor’s built in system
state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-on Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
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The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
6.2.3 Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-Down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable
system reset released
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C, Timer, UART,
BOD, GPIO, EINT, USCI,
USBD, ACMP and VDET.
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6.2-2 Power Mode Difference Table
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System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, HIRC48, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFI
Wake-up events
occur
Idle Mode
Power-down Mode
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
CPU Clock OFF
HXT, HIRC, HIRC48, PCLK OFF
LXT, LIRC ON
Flash Halt
Flash Halt
Figure 6.2-6 NuMicro® NUC126 Power Mode State Machine
1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in normal mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
6. If UART clock source is selected as LXT and LXT is on.
Normal Mode
ON
Idle Mode
Power-Down Mode
HXT (4~20 MHz XTL)
ON
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
HIRC (22.1184 MHz OSC)
ON
HIRC48 (48 MHz OSC)
LXT (32768 Hz XTL)
LIRC (10 kHz OSC)
PLL
ON
Halt
ON
ON/OFF1
ON/OFF2
Halt
ON
ON
LDO
ON
ON
CPU
ON
Halt
HCLK/PCLK
SRAM retention
FLASH
ON
Halt
ON
ON
ON
Halt
GPIO
ON
Halt
PDMA
ON
Halt
TIMER
ON
ON/OFF3
Halt
PWM
ON
WDT
ON
ON/OFF4
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WWDT
RTC
UART
SC
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
ON/OFF5
ON/OFF6
Halt
USCI
I2C
Halt
Halt
SPI
Halt
USBD
ADC
ACMP
Halt
Halt
Halt
Table 6.2-3 Clocks in Power Modes
Wake-up sources in Power-down mode:
RTC, WDT, I²C, Timer, UART, USCI, BOD, VDET, GPIO, USBD, and ACMP.
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to
enter Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear BODIF (SYS_BODCTL[4]).
Voltage Detector Interrupt After software writes 1 to clear VDETIF (SYS_BODCTL[19]).
VDET
GPIO
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the Px_INTSRC[n] bit.
TIMER
After software writes
(TIMERx_INTSTS[0]).
1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
WDT
RTC
WDT Interrupt
Alarm Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear ALMIF (RTC_INTSTS[0]).
After software writes 1 to clear TICKIF (RTC_INTSTS[1]).
After software writes 1 to clear CTSWKF (UARTx_WKSTS[0]).
After software writes 1 to clear DATWKF (UARTx_WKSTS[1]).
Time Tick Interrupt
nCTS wake-up
UART
RX Data wake-up
Received FIFO Threshold
Wake-up
After software writes 1 to clear RFRTWKF (UARTx_WKSTS[2]).
RS-485 AAD Mode Wake-up After software writes 1 to clear RS485WKF (UARTx_WKSTS[3]).
Received FIFO Threshold
After software writes 1 to clear TOUTWKF (UARTx_WKSTS[4]).
Time-out Wake-up
USCI UART
CTS Toggle
After software writes 1 to clear WKF (UUART_WKSTS[0]).
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Data Toggle
Data toggle
After software writes 1 to clear WKF (UUART_WKSTS[0]).
After software writes 1 to clear WKF (UI2C_WKSTS[0]).
USCI I2C
After software writes 1 to clear WKAKDONE (UI2C_PROTSTS[16], then writes 1
to clear WKF (UI2C_WKSTS[0]).
Address match
SS Toggle
USCI SPI
I2C
After software writes 1 to clear WKF (USPI_WKSTS[0]).
After software writes 1 to clear WKAKDONE (I2C_WKSTS[1]). Then software
writes 1 to clear WKIF(I2C_WKSTS[0]).
Address match wake-up
Remote Wake-up
USBD
ACMP
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
Comparator Power-Down After software writes 1 to clear WKIF0 (ACMP_STATUS[8]) and WKIF1
Wake-Up Interrupt (ACMP_STATUS[9]).
Table 6.2-4 Condition of Entering Power-down Mode Again
6.2.4 System Power Distribution
In this chip, power distribution is divided into four segments:
Analog power from AVDD and AVSS provides the power for analog components
operation. The VREF should be connected with an external 1uF capacitor that should
be located close to the VREF pin to avoid power noise for analog applications.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
RTC power from VBAT provides the power for RTC.
A dedicated power from VDDIO supplies the power for PE.8 ~ PE.13.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level of the digital power (VDD). Figure 6.2-7 shows the power distribution of the NUC126
series.
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Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
USB_D+
USB_D-
USB
Transceiver
IO Cell
12-bit ADC
USB_VDD33_CAP
1uF
3.3V
AVDD
AVSS
Analog
Comparator
1.8V
Brown-
out
Detector
VBAT to 1.8V
LDO
5V to 3.3V
LDO
Low Voltage Reset
RTC
VBUS
Temperature
Sensor
SRAM
Flash
Digital Logic
IO Cell
PE.8~PE.13
1.8V
LDO_CAP
1uF
22.1184 MHz
HIRC
Oscillator
48 MHz
HIRC48
Oscillator
10 kHz
LIRC
Oscillator
PLL
POR18
VDDIO
4~24 MHz
crystal
oscillator
XT1_OUT
XT1_IN
VDD to 1.8V
LDO
Power On
Control
POR50
IO Cell
Figure 6.2-7 NuMicro® NUC126 Power Distribution Diagram
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6.2.5 System Memory Map
The NUC126 series provides 4G-byte addressing space. The memory locations assigned to each on-
chip controllers are shown in Table 6.2-5. The detailed register definition, memory space, and
programming will be described in the following sections for each on-chip peripheral. The NUC126
series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x0000_0000 – 0x0003_FFFF
0x0004_0000 – 0x0005_FFFF
0x0006_0000 – 0x0007_FFFF
0x2000_0000 – 0x2000_4FFF
0x2000_4000 – 0x2000_BFFF
0x2000_C000 – 0x2000_FFFF
0x6000_0000 – 0x601F_FFFF
FLASH_BA
FLASH_BA
Reserved
FLASH Memory Space (128 KB)
FLASH Memory Space (256 KB)
Reserved
Reserved
Reserved
SRAM_BA
Reserved
SRAM Memory Space (20 KB)
Reserved
Reserved
Reserved
EXTMEM_BA
External Memory Space for EBI Interface (2 MB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
0x5001_4000 – 0x5001_7FFF
0x5001_8000 – 0x5001_FFFF
SYS_BA
CLK_BA
INT_BA
System Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
FMC_BA
EBI_BA
Peripheral DMA Control Registers
Flash Memory Control Registers
EBI Control Registers
HDIV_BA
CRC_BA
Hardware Divider Registers
CRC Generator Registers
Peripheral Controllers Space (0x4000_0000 – 0x401F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4004_4000 – 0x4004_7FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x4007_0000 – 0x4007_3FFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0 Control Registers
TMR01_BA
I2C0_BA
SPI0_BA
SPI1_BA
PWM0_BA
Reserved
UART0_BA
USBD_BA
USCI0_BA
Reserved
UART0 Control Registers
USB 2.0 FS device Controller Registers
USCI0 Control Registers
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0x4007_4000 – 0x4007_7FFF
0x400D_0000 – 0x400D_3FFF
0x400D_4000 – 0x400D_7FFF
0x400E_0000 – 0x400E_FFFF
0x4010_0000 – 0x4010_3FFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4014_0000 – 0x4014_3FFF
0x4014_4000 – 0x4014_7FFF
0x4015_0000 – 0x4015_3FFF
0x4015_4000 – 0x4015_7FFF
0x4017_0000 – 0x4017_3FFF
0x4017_4000 – 0x4017_7FFF
0x4019_0000 – 0x4019_3FFF
0x4019_4000 – 0x4019_7FFF
0x401A_0000 – 0x401A_3FFF
USCI2_BA
ACMP01_BA
Reserved
ADC_BA
USCI2 Control Registers
Analog Comparator Control Registers
Reserved
Analog-Digital-Converter (ADC) Control Registers
Reserved
Reserved
TMR23_BA
I2C1_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
PWM1 Control Registers
Reserved
PWM1_BA
Reserved
UART1_BA
UART2_BA
USCI1_BA
Reserved
SC0_BA
UART1 Control Registers
UART2 Control Registers
USCI1 Control Registers
Reserved
SC0 Control Registers
SC1 Control Registers
Reserved
SC1_BA
Reserved
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-5 Address Space Assignments for On-Chip Controllers
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6.2.6 SRAM Memory Orginization
The NUC126 supports embedded SRAM with total 20 Kbytes size in one bank.
Supports total 20 Kbytes SRAM
Supports byte / half word / word write
Supports oversize response error
AHB interface
controller
SRAM decoder
SRAM bank
Figure 6.2-8 SRAM Block Diagram
Figure 6.2-9 shows the SRAM organization of NUC126. There is one SRAM bank in the NUC126
and addressed to 20 Kbytes. The address space is from 0x2000_0000 to 0x2000_4FFF. The
address between 0x2000_5000 to 0x3FFF_FFFF is illegal memory space and chip will enter
hardfault if CPU accesses these illegal memory addresses.
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0x3FFF_FFFF
Reserved
0x2000_5000
0x2000_4FFF
20K byte
SRAM bank0
0x2000_0000
20K byte device
Figure 6.2-9 SRAM Memory Organization
6.2.7 Register Lock
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register SYS_REGLCTL address at 0x5000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
After the protection is disabled, user can check the protection disable bit at address 0x5000_0100 bit0,
1 is protection disable, and 0 is protection enable. Then user can update the target protected register
value and then write any data to the address “0x5000_0100” to enable register protection.
6.2.8 Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz and 22.1184 MHz RC oscillator),
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according to the accurate external 32.768 kHz crystal oscillator or internal USB synchronous mode,
automatically gets accurate HIRC output frequency, 0.25 % deviation within all temperature ranges.
For instance, the system needs an accurate 22.1184 MHz clock. In such case, if users do not want to
use PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set
FREQSEL (SYS_IRCTCTL0[1:0] trim frequency selection) to “01”, set REFCKSEL (SYS_IRCTCTL0[9]
reference clock selection) to “0”, and the auto-trim function will be enabled. Interrupt status bit
FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) “1” indicates the HIRC0 output frequency
is accurate within 0.25% deviation. To get better results, it is recommended to set both LOOPSEL
(SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT (SYS_IRCTCTL[7:6] trim value update
limitation count) to “11”.
Another example is that the system needs an accurate 48 MHz clock for USB application. In such
case, if neither using use PLL as the system clock source nor soldering 32.768 kHz crystal in system,
user has to set REFCKSEL (SYS_IRCTCTL1[10] reference clock selection) to “1”, set FREQSEL
(SYS_IRCTCTL1[1:0] trim frequency selection) to “10”, and the auto-trim function will be enabled.
Interrupt status bit FREQLOCK1 (SYS_IRCTISTS[8] HIRC frequency lock status) “1” indicates the
HIRC1 output frequency is accurate within 0.25% deviation.
6.2.9 UART1_TXD modulation with PWM
This chip supports UART1_TXD to modulate with PWM channel. User can set
MODPWMSEL(SYS_MODCTL[6:4]) to choice which PWM0 channel to modulate with UART1_TXD
and set MODEN(SYS_MODCTL[0]) to enable modulation function. User can set
TXDINV(UART_LINE[8]) to inverse UART1_TXD before moulating with PWM.
PWM0_CHx
UART1_TXD
TXDINV = 0 & MODH = 0
TXDINV = 0 & MODH = 1
TXDINV = 1 & MODH = 0
TXDINV = 1 & MODH = 1
Figure 6.2-10 UART1_TXD Modulated with PWM Channel
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6.2.10 Voltage Detector (VDET)
This chip supports low power comparator to detect external voltage. User can control Bandgap active
interval and comparator active interval to achieve low power detection purpose. There is no debounce
function in Power-down mode since no HCLK available in Power-down mode.
VDETPINSEL(SYS_BODCTL[17])
VDET_
0
P0
VDET_
De-glitch
VDETDGSEL
(SYS_BODCTL[27:
VDETOUT(SYS_BODCTL[24
])
1
P1
25])
1.2V
Bandgap
VDETEN(SYS_BODCTL[16])
VDETEN(SYS_BODCTL[16])
Figure 6.2-11 VDET Block Diagram
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6.2.11 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with
this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.12 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.12.1 Exception Model and System Interrupt Map
Table 6.2-6 lists the exception model supported by the NUC126 series. Software can set four
levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority
of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Type
Reset
Vector Number
Vector Address
0x00000004
0x00000008
0x0000000C
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
SVCall
3
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
0x0000002C
0x00000038
Reserved
PendSV
12 ~ 13
14
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SysTick
15
0x0000003C
Configurable
Configurable
0x00000000 +
Interrupt (IRQ0 ~ IRQ)
16 ~ 47
(Vector Number)*4
Table 6.2-6 Exception Model
Interrupt Number
(Bit In Interrupt
Registers)
Vector
Number
Interrupt Name
Interrupt Description
0 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
-
-
System exceptions
0
BOD_INT
WDT_INT
EINT024
Brown-out low voltage detected interrupt
Window Watchdog Timer interrupt
External interrupt from PA.0/PC.0/PD.2/PE.0/PE.4 pin
External interrupt from PB.0/PC.0/ PD.0/PD.3/PE.5/PF.0 pin
External signal interrupt from PA[15:0]/PB[13:0]
External interrupt from PC[15:0]/PD[15:0]/PE[13:0]/PF[7:0]
PWM0 interrupt
1
2
3
EINT135
4
GPAB_INT
GPCDEF_INT
PWM0_INT
PWM1_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
SPI0_INT
SPI1_INT
5
6
7
PWM1 interrupt
8
Timer 0 interrupt
9
Timer 1 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Timer 2 interrupt
Timer 3 interrupt
UART0 and UART2 interrupt
UART1 interrupt
SPI0 interrupt
SPI1 interrupt
Reserved
Reserved
I2C0_INT
I2C1_INT
I2C0 interrupt
I2C1 interrupt
Reserved
Reserved
USCI_INT
USBD_INT
SC_INT
USCI0, USCI1 and USCI2 interrupt
USB Device interrupt
SC0 and SC1 interrupt
Analog Comparator interrupt
ACMP01_INT
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42
43
44
45
46
47
26
27
28
29
30
31
PDMA_INT
PDMA interrupt
Reserved
PWRWU_INT
ADC_INT
Clock controller interrupt for chip wake-up from Power-down state
ADC interrupt
CLKDIRC_INT
RTC_INT
Clock fail detect and IRC TRIM interrupt
Real Time Clock interrupt
Table 6.2-7 Interrupt Number Table
6.2.12.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
Cortex® -M0 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~24 MHz external high speed crystal (HXT), internal 22.1184 MHz
internal high speed RC oscillator (HIRC) and 48 MHz internal high speed RC oscillator (HIRC48)
to reduce the overall system power consumption. Figure 6.3-1 shows the clock generator and the
overview of the clock source control.
The clock generator consists of 6 clock sources, which are listed below:
32.768 kHz external low-speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~24 MHz external high speed crystal (HXT) or 22.1184 MHz internal
high speed oscillator (HIRC)
22.1184 MHz internal high speed RC oscillator (HIRC)
48 MHz internal high speed RC oscillator (HIRC48)
10 kHz internal low speed RC oscillator (LIRC)
Each of these clock sources has certain stable time to wait for clock operating at stable frequency.
When clock source is enabled, a stable counter start counting and correlated clock stable index
(HIRCSTB(CLK_STATUS[4]),
LIRCSTB(CLK_STATUS[3]),
PLLSTB(CLK_STATUS[2]),
HXTSTB(CLK_STATUS[0]), LXTSTB(CLK_STATUS[1]) and HIRC48STB(CLK_STATUS[5])) are
set to 1 after stable counter value reach a define value as shown in Table 6.3-8. System and
peripheral can use the clock as its operating clock only when correlate clock stable index is set to
1. The clock stable index will auto clear when user disables the clock source
(LIRCEN(CLK_PWRCTL[3]),
HIRCEN(CLK_PWRCTL[2]),
HXTEN(CLK_PWRCTL[0]),
PD(CLK_PLLCTL[16]), LXTEN(CLK_PWRCTL[1]) and HIRC48EN(CLK_PWRCTL[13])). Besides,
the clock stable index of HXT, HIRC and PLL will auto clear when chip enter power-down and
clock stable counter will re-counting after chip wake-up if correlate clock is enabled.
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Clock Source
HXT
Clock Stable Count Value
Clock Stable Time
4096 HXT clock
341.33 uS for 12 Mhz
PLL
It’s based on the value of STBSEL (CLK_PLLCTL[23])
STBSEL = 0, 512 uS for 512 Mhz
STBSEL = 1, 1024 uS for 12 Mhz
STBSEL = 0, stable count is 6144 clocks of PLL clock source.
STBSEL = 1, stable count is 12288 clocks of PLL clock source.
(Default)
HIRC48
HIRC
LIRC
512 HIRC48 clock
256 HIRC clock
1 LIRC clock
10.67 uS for 48 Mhz
11.574 uS for 22.1184 Mhz
100 uS for 10 kHz
LXT
1 LXT clock
30.51 uS for 32.768 khz
Table 6.3-8 Clock Stable Count Value Table
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
(LXT)
LXT
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~24
MHz Crystal
(HXT)
PLLSRC (CLK_PLLCTL[19])
XT1_OUT
0
1
PLL FOUT
HIRCEN (CLK_PWRCTL[2])
PLL
Internal
22.1184 MHz
Oscillator
(HIRC)
HIRC
LIRCEN(CLK_PWRCTL[3])
Internal10 KHz
Oscillator
(LIRC)
LIRC
LIRCEN(CLK_PWRCTL[13])
Internal 48 MHz
Oscillator
HIRC48
(HIRC48)
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-1 Clock Generator Block Diagram
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48 MHz
CPUCLK
HCLK
CPU
48 MHz
48 MHz
22.1184 MHz
22.1184 MHz
10 kHz
10 kHz
PLLFOUT
PLLFOUT
32.768 kHz
32.768 kHz
4~24 MHz
4~24 MHz
100
100
22.1184
MHz
CRC
111
111
1/(HCLKDIV+1)
PDMA
011
011
4~24
MHz
010
010
EBI
CLK_CLKSEL0[6]
001
001
000
000
HDIV
I2C0
32.768
kHz
1
0
0
1/2
1
PCLK0
PCLK1
ACMP
CLK_CLKSEL0[2:0]
USCI0/2
USCI1
I2C1
10 kHz
1
1/2
1
0
0
CLK_CLKSEL0[7]
22.1184 MHz
22.1184 MHz
22.1184 MHz
22.1184 MHz
10 kHz
10 kHz
1
0
0
1
PLL FOUT
111
111
4~24 MHz
4~24 MHz
101
101
T0~T3
T0~T3
PCLK
PCLK
CLK_PLLCTL[19]
CLK_PLLCTL[19]
TMR 0
011
011
10 kHz
10 kHz
TMR 1
TMR 2
TMR 3
010
010
BOD
FMC
32.768 kHz
32.768 kHz
22.1184 MHz
22.1184 MHz
001
001
4~24 MHz
4~24 MHz
000
000
48 MHz
48 MHz
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
0
1
1
0
USB
PLLFOUT
PLLFOUT
1/(USBDIV+1)
CLK_CLKSEL3[8]
22.1184 MHz
22.1184 MHz
111
111
1/2
1/2
1/2
HCLK
HCLK
CPUCLK
CPUCLK
10 kHz
10 kHz
011
011
1
0
0
1
1
1
0
4~24 MHz
4~24 MHz
SysTick
RTC
32.768 kHz
32.768 kHz
010
010
0
32.768 kHz
32.768 kHz
001
001
CLK_CLKSEL2[18]
4~24 MHz
4~24 MHz
SYST_CSR
SYST_CSR
000
000
48 MHz
48 MHz
22.1184 MHz
22.1184 MHz
CLK_CLKSEL0[5:3]
101
101
011
011
HCLK
HCLK
Clock Output
PCLK
PCLK
010
010
32.768 kHz
32.768 kHz
4~24 MHz
4~24 MHz
1
0
0
1
001
001
000
000
PWM 0
PWM 1
PLLFOUT
PLLFOUT
CLK_CLKSEL1[28]
CLK_CLKSEL1[29]
CLK_CLKSEL2[4:2]
48 MHz
48 MHz
11
11
10
SPI0
SPI1
PCLK
PCLK
PLLFOUT
PLLFOUT
10 kHz
10 kHz
10
11
11
HCLK
HCLK
01
01
00
00
1/2048
WDT
10
10
4~24 MHz
4~24 MHz
32.768 kHz
32.768 kHz
01
01
CLK_CLKSEL1[1:0]
CLK_CLKSEL1[1:0]
CLK_CLKSEL2[25:24]
CLK_CLKSEL2[27:26]
22.1184 MHz
22.1184 MHz
10 kHz
10 kHz
11
10
10
11
10
10
11
11
WWDT
PCLK
PCLK
HCLK
HCLK
1/2048
1/(ADCDIV)+1
ADC
PLLFOUT
PLLFOUT
01
01
CLK_CLKSEL1[31:30]
CLK_CLKSEL1[31:30]
4~24 MHz
4~24 MHz
00
00
22.1184 MHz
22.1184 MHz
32.768 KHz
32.768 KHz
11
11
PCLK
PCLK
10
11
11
CLK_CLKSEL1[3:2]
10
10
10
SMC0
SMC1
22.1184 MHz
22.1184 MHz
PLLFOUT
PLLFOUT
1/(UARTDIV+1)
UART 0-2
PLLFOUT
PLLFOUT
4~24 MHz
4~24 MHz
01
01
01
01
4~24 MHz
4~24 MHz
00
00
00
00
CLK_CLKSEL1[25:24]
CLK_CLKSEL3[1:0]
CLK_CLKSEL3[3:2]
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-2 Clock Generator Global View Diagram
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6.3.2 System Clock and SysTick Clock
The system clock has 6 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram
is shown in Figure 6.3-3.
HCLKSEL (CLK_CLKSEL0[2:0])
HIRC
111
011
011
111
LIRC
PLLFOUT
LXT
CPUCLK
HCLK
CPU
AHB
010
010
1/(HCLKDIV+1)
001
001
HCLKDIV (CLK_CLKDIV0[3:0])
HXT
1
0
1/2
1
000
000
APB
HIRC48
0
100
100
CPU in Power Down Mode
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled
automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to
1
and chip will enter interrupt if HXTFIEN
(CLK_CLKDCTL[5]) is set to 1. User can trying to recover HXT by disable HXT and enable HXT
again to check if the clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means
HXT is recover to oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in Figure 6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
1/2
1/2
HCLK
HXT
STCLK
010
001
000
1/2
LXT
HXT
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.3 Peripherals Clock
The peripherals clock had different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSEL1, CLK_CLKSEL2 and CLK_CLKSEL3 register
description in section 6.3.7.
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6.3.4 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources, and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
– 10 kHz internal low-speed RC oscillator (LIRC) clock
– 32.768 kHz external low-speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.5 Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stay in low state.
If DIVI1EN(CLK_CLKOCTL[5]) set to 1, the clock output clock (CLKO_CLK) will bypass power-of-
2 frequency divider. The clock output clock will be output to CLKO pin directly.
CLKOSEL (CLK_CLKSEL2[4:2])
CLKOCKEN (CLK_APBCLK0[6])
HIRC
011
010
HCLK
LXT
CLKO_CLK
001
000
101
HXT
HIRC48
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-6 Clock Source of Clock Output
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CLKOEN
(CLK_CLKOCTL[4])
Enable
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
DIV1EN
(CLK_CLKOCTL[5])
CLKO_CLK
1/2
1/22
1/23
…...
1/215 1/216
CLK1HZEN
(CLK_CLKOCTL[6])
0000
0001
:
16 to 1
MUX
0
1
:
0
1
1110
CLKO
1111
RTCSEL(CLK_CLKSEL2[18])
LIRC
LXT
0
1
1 Hz clock from RTC
/32768
Figure 6.3-7 Clock Output Block Diagram
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6.4 Flash Memeory Controller (FMC)
6.4.1 Overview
The NUC126 series is equipped with 128/256 Kbytes on-chip embedded flash for application and
configurable Data Flash to store some application dependent data. A User Configuration block
provides for system initiation. A 4 Kbytes loader ROM (LDROM) is used for In-System-
Programming (ISP) function. A 2 Kbytes security protection ROM (SPROM) can conceal user
program. A 4KB cache with zero wait cycle is used to improve flash access performance. This
chip also supports In-Application-Programming (IAP) function, user switches the code executing
without the chip reset after the embedded flash updated.
6.4.2 Features
Supports 128/256 Kbytes application ROM (APROM).
Supports 4 Kbytes loader ROM (LDROM).
Supports 2 Kbytes security protection ROM (SPROM) to conceal user program.
Supports Data Flash with configurable memory size.
Supports 12 bytes User Configuration block to control system initiation.
Supports 2 Kbytes page erase for all embedded flash.
Supports 32-bit/64-bit and multi-word flash programming function.
Supports CRC-32 checksum calculation function.
Supports flash all one verification function.
Supports embedded SRAM remap to system vector memory.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
Supports cache memory to improve flash access performance and reduce power
consumption.
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6.5 Analog Comparator Controller (ACMP)
6.5.1 Overview
NUC126 contains two analog comparators. The comparator output is logic 1 when positive input is
greater than negative input; otherwise, the output is 0. Each comparator can be configured to
generate an interrupt when the comparator output state changes.
6.5.2 Features
Analog input voltage range: 0 ~ VDDA (voltage of AVDD pin)
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports
– 4 positive sources:
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
– 3 negative sources:
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
ACMP1 supports
– 4 positive sources:
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
– 3 negative sources
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
Shares one ACMP interrupt vector for all comparators
Supports window Latch mode
Supports window compare mode
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6.6 Analog-to-Digital Converter (ADC)
6.6.1 Overview
The NUC126 series contains one 12-bit successive approximation analog-to-digital converter
(SAR A/D converter) with twenty input channels. The A/D converter supports four operation
modes: Single, Burst, Single-cycle Scan and Continuous Scan mode. The A/D converter can be
started by software, external pin (STADC/PD.2), timer0~3 overflow pulse trigger and PWM trigger.
6.6.2 Features
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed
Up to 20 single-end analog input channels or 10 differential analog input channels
Maximum ADC peripheral clock frequency is 16 MHz
Up to 800k SPS sampling rate
Configurable ADC internal sampling time
Four operation modes:
– Single mode: A/D conversion is performed one time on a specified channel.
– Burst mode: A/D converter samples and converts the specified single channel and
sequentially stores the result in FIFO.
– Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel.
– Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode
until software stops A/D conversion.
An A/D conversion can be started by:
– Software Write 1 to ADST bit
– External pin (STADC)
– Timer 0~3 overflow pulse trigger
– PWM trigger with optional start delay period
Each conversion result is held in data register of each channel with valid and overrun
indicators.
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP), and
Battery power (VBAT
)
Support PDMA transfer mode.
Note1: ADC sampling rate = (ADC peripheral clock frequency) / (total ADC conversion cycle)
Note2: If the internal channel (VTEMP) is selected to convert, the sampling rate needs to be less
than 300k SPS for accurate result.
Note3: If the internal channel for band-gap voltage is active, the maximum sampling rate will be
300k SPS.
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6.7 CRC Controller (CRC)
6.7.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with four common
polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 settings.
6.7.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
– CRC-CCITT: X16 + X12 + X5 + 1
– CRC-8: X8 + X2 + X + 1
– CRC-16: X16 + X15 + X2 + 1
– CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
– 8-bit write mode: 1-AHB clock cycle operation
– 16-bit write mode: 2-AHB clock cycle operation
– 32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to program DATA (CRC_DAT[31:0]) to perform CRC operation
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6.8 External Bus Interface (EBI)
6.8.1 Overview
The NUC126 series is equipped with an external bus interface (EBI) for external device used. To
save the connections between external device and the NUC126, EBI operating at address bus
and data bus multiplex mode. The EBI supports two chip selects that can connect two external
devices with different timing setting requirement.
6.8.2 Features
Supports address bus and data bus multiplex mode to save the address pins
Supports two chip selects with polarity control
Supports external devices with maximum 1 MB size for each chip select
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width for each chip select
Supports variable address latch enable time (tALE)
Supports variable data access time (tACC) and data access hold time (tAHD) for each
chip select
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports continuous data access mode to bypass tASU, tALE and tLHD cycles for
improving EBI access
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6.9 General Purpose I/O (GPIO)
6.9.1 Overview
The NUC126 series has up to 86 General Purpose I/O pins to be shared with other function pins
depending on the chip configuration. These 86 pins are arranged in 6 ports named as PA, PB,
PC, PD, PE and PF. PA, PB, PC, PD has 16 pins on port. PE has 14 pins on port. PF has 8 pins
on port. Each of the 86 pins is independent and has the corresponding register bits to control the
pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
6.9.2 Features
Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOIN = 0, all GPIO pins in input tri-state mode after chip reset
– CIOIN = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
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6.10
Hardware Divider (HDIV)
6.10.1 Overview
The hardware divider (HDIV) is useful to the high performance application. The hardware divider
is a signed, integer divider with both quotient and remainder outputs.
6.10.2 Features
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)
Divided by zero warning flag
6 HCLK clocks taken for one cycle calculation
Write divisor to trigger calculation
Waiting for calculation ready automatically when reading quotient and remainder
6.10.3 Blcok Diagram
Dividend Source Divisor Source Quotient Result
Divider Status
Register
(DIVSTS)
Remainder Result
Register(DIVREM)
Register
Register
Register
(DIVIDEND)
(DIVISOR)
(DIVQUO)
Sign extension
Divider Calculation
Digital Control Logic
Figure 6.10-1 Hardware Divider Block Diagram
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6.11
I2C Serial Interface Controller (I2C)
6.11.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
There are two sets of I2C controllers which support Power-down wake-up function.
6.11.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports PDMA with one buffer capability
Supports two-level buffer function
Supports setup/hold time programmable
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6.12
PDMA Controller (PDMA)
6.12.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data
transfer. The PDMA controller can transfer data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controller has a total of 5 channels and each channel can
perform transfer between memory and peripherals or between memory and memory. The PDMA
supports time-out function for channel 0 and channel 1.
6.12.2 Features
Supports 5 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and SPI, UART, I2S, I2C, USB, ADC, PWM and TIMER request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function for channel0 and channel 1
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6.13
PWM Generator and Capture Timer (PWM)
6.13.1 Overview
The NUC126 provides two PWM generator: PWM0 and PWM1. Each PWM supports 6 channels
of PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit
PWM counter with 16-bit comparator. The PWM counter supports up, down and up-down counter
types. PWM uses comparator compared with counter to generate events. These events use to
generate PWM pulse, interrupt and trigger signal for ADC to start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. There are two output functions based on
standard output modes: Group function and Synchronous function. Group function can be enabled
under Independent mode or complementary mode. Synchronous function only enabled under
complementary mode. Complementary mode has two comparators to generate various PWM
pulse with 12-bit dead-time generator and another free trigger comparator to generate trigger
signal for ADC. For PWM output control unit, it supports polarity output, independent pin mask
and brake functions.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened. Capture function also support PDMA to transfer captured data to memory.
6.13.2 Features
6.13.2.1 PWM function features
Supports maximum clock frequency up to144MHz
Supports up to two PWM modules, each module provides 6 output channels.
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channels:
– Dead-time insertion with 12-bit resolution
– Synchronous function for phase control
– Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
– Up, down and up-down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each PWM output pin
Supports brake function
– Brake source from pin, analog comparator, ADC result monitor and system safety
events (clock failed, Brown-out detection and CPU lockup).
– Noise filter for brake source from pin
– Leading edge blanking (LEB) function for brake source from analog comparator
– Edge detect brake source to control brake state until brake interrupt cleared
Aug. 08, 2018
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– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM zero point, period point, up-count compared or down-count compared point
events
– Brake condition happened
Supports trigger ADC on the following events:
– PWM zero point, period point, zero or period point, up-count compared point, down-
count compared point events
– PWM up-count free trigger compared point, down-count free trigger compared point
events
6.13.2.2 Capture Function Features
Supports up to 6 capture input channels with 16-bit resolution for each PWM module
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
Aug. 08, 2018
Page 95 of 140
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6.14
Real Time Clock (RTC)
6.14.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
6.14.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable
in RTC_TAMSK and RTC_CAMSK
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counter in RTC_WEEKDAY register
Frequency of RTC clock source compensate by RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while an RTC interrupt signal is
generated
Supports Daylight Saving Time backup control in RTC_DSTCTL
Aug. 08, 2018
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6.15
Smart Card Host Interface (SC)
6.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.15.2 Features
ISO-7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Two ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the interval between PWR on and
CLK start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
– Full duplex, asynchronous communications
– Separates receiving/transmitting 4 bytes entry FIFO for data payloads
– Supports programmable baud rate generator
– Supports programmable receiver buffer trigger level
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting EGT (SC_EGT[7:0])
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1- or 2- stop bit generation
Aug. 08, 2018
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6.16
Serial Peripheral Interface (SPI)
6.16.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The NUC126 series contains up to two sets of SPI controllers performing a serial-to-
parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion
on data transmitted to a peripheral device. Each SPI controller can be configured as a master or a
slave device.
This controller also supports the PDMA function to access the data buffer. The SPI controller also
support I2S mode to connect external audio CODEC.
6.16.2 Features
SPI Mode
– Up to two sets of SPI controllers
– Supports Master or Slave mode operation
– Configurable bit length of a transaction word from 8 to 32-bit
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports MSB first or LSB first transfer sequence
– Supports Byte Reorder function
– Supports PDMA transfer
– Supports one data channel half-duplex transfer
– Support receive-only mode
I2S Mode
– Supports Master or Slave
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Provides separate 4-level depth transmit and receive FIFO buffers
– Supports monaural and stereo audio data
– Supports PCM mode A, PCM mode B, I2S and MSB justified data format
– Supports PDMA transfer
Aug. 08, 2018
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6.17
Timer Controller (TMR)
6.17.1 Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
The Timer controller also provides four PWM generators. Each PWM generator supports two
PWM output channels in independent mode and complementary mode. The output state of PWM
output pin can be control by pin mask, polarity and break control, and dead-time generator.
6.17.2 Features
6.17.2.1 Timer Function Features
Four sets of 32-bit timers, each timer equips one 24-bit up counter and one 8-bit prescale
counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger
PWM, ADC and PDMA function
Supports internal capture triggered while internal ACMP output signal transition
Supports Inter-Timer trigger mode
Supports event counting source from internal USB SOF signal
6.17.2.2 PWM Function Features
Supports maximum clock frequency up to 72MHz
Supports independent mode for PWM generator with two output channels
Supports complementary mode for PWM generator with paired PWM output channel
– 12-bit dead-time insertion with 12-bit prescale
Supports 12-bit prescale from 1 to 4096
Supports 16-bit PWM counter
– Up, down and up-down count operation type
– One-shot or auto-reload counter operation mode
Supports mask function and tri-state enable for each PWM output pin
Aug. 08, 2018
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Supports brake function
– Brake source from pin, analog comparator and system safety events (clock failed,
Brown-out detection and CPU lockup)
– Brake pin noise filter control for brake source
– Edge detect brake source to control brake state until brake interrupt cleared
– Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
– PWM zero point, period point, up-count compared or down-count compared point
events
– Brake condition happened
Supports trigger ADC on the following events:
– PWM zero point, period, zero or period point, up-count compared or down-count
compared point events
Aug. 08, 2018
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6.18
6.18.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
USB Device Controller (USBD)
compliant with USB 2.0 full-speed device specification and supports
control/bulk/interrupt/isochronous transfer types. It implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up idle event, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB
controller will force the output of USB_D+ and USB_D- to level low. It will casue host detect
disconnect after user enable SE0 bit for a while. Finally, user can disable the SE0 bit, host will
enumerate the USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
6.18.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WKIDLE, VBUSDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
and maximum 512 bytes buffer size
Provides remote wake-up capability
Supports Start of Frame (SOF) interrupt and USB frame number monitor.
Supports USB 2.0 Link Power Management
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6.19
USCI – Universal Serial Control Interface Controller
Clock
Generator
NVIC
VBUS
VBUS
Detection
De-bouncing
Detection
USB
control
and
Interrupt
control
DPLL
status
registers
USB_D+
USB_D-
APB Bus
RXDP
Endpoint
Control
RXDM
S0
SRAM
(512
Bytes)
SIE
Buffer
Control
USB_VBUS
S1
Transceiver
6.19.1 Overview
The Universal Serial Control Interface (USCI) is a flexible interface module covering several serial
communication protocols. The user can configure this controller as UART, SPI, or I2C functional
protocol.
6.19.2 Features
The controller can be individually configured to match the application needs. The following
protocols are supported:
UART
SPI
I2C
Aug. 08, 2018
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6.20
USCI – UART Mode
6.20.1 Overview
The asynchronous serial channel UART covers the reception and the transmission of
asynchronous data frames. It performs a serial-to-parallel conversion on data received from the
peripheral, and a parallel-to-serial conversion on data transmitted from the controller. The receiver
and transmitter being independent, frames can start at different points in time for transmission and
reception.
The UART controller also provides auto flow control. There are two conditions to wake up the
system.
6.20.2 Features
Supports one transmit buffer and two receive buffer for data payload
Supports hardware auto flow control function
Supports programmable baud-rate generator
Support 9-Bit Data Transfer (Support 9-Bit RS-485)
Baud rate detection possible by built-in capture event of baud rate generator
Supports Wake-up function (Data and nCTS Wakeup Only)
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6.21
USCI – SPI Mode
6.21.1 Overview
The SPI protocol of USCI controller applies to synchronous serial data communication and allows
full duplex transfer. It supports both master and Slave operation mode with the 4-wire bi-direction
interface. SPI mode of USCI controller performs a serial-to-parallel conversion on data received
from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral
device. The SPI mode is selected by FUNMODE (USPI_CTL[2:0]) = 0x1.
This SPI protocol can operate as master or Slave mode by setting the SLAVE
(USPI_PROTCTL[0]) to communicate with the off-chip SPI Slave or master device. The
application block diagrams in master and Slave mode are shown below.
USCI SPI Master
USCI SPI Master
SPI Slave Device
SPI_MOSI
Master Transmit Data
Master Receive Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_SS
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
Note: x = 0, 1, 2
Figure 6.21-1 SPI Master Mode Application Block Diagram
USCI SPI Slave
USCI SPI Slave
SPI Master Device
SPI_MOSI
Slave Receive Data
Slave Transmit Data
Serial Bus Clock
SPI_MOSI
(USCIx_DAT0)
SPI_MISO
(USCIx_DAT1)
SPI_MISO
SPI_CLK
SPI_CLK
(USCIx_CLK)
Slave Select
SPI_SS
(USCIx_CTL)
SPI_SS
Note: x = 0, 1, 2
Figure 6.21-2 SPI Slave Mode Application Block Diagram
6.21.2 Features
Supports Master or Slave mode operation (the maximum frequency – Master = fPCLK / 2,
Slave < fPCLK / 5)
Configurable bit length of a transfer word from 4 to 16-bit
Supports one transmit buffer and two receive buffers for data payload
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Supports MSB first or LSB first transfer sequence
Supports Word Suspend function
Supports 3-wire, no slave select signal, bi-direction interface
Supports wake-up function by slave select signal in Slave mode
Supports one data channel half-duplex transfer
Aug. 08, 2018
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6.22
USCI – I2C Mode
6.22.1 Overview
On I2C bus, data is transferred between a Master and a Slave. Data bits transfer on the SCL and
SDA lines are synchronously on a byte-by-byte basis. Each data byte is 8-bit. There is one SCL
clock pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows
each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line
may be changed only during the low period of SCL and must be held stable during the high period
of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6.22-1 for more detailed I2C BUS Timing.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD_STA
tSU_STA
tSU_STO
tSU_DAT
tHD_DAT
Figure 6.22-1 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. The I2C mode is selected by
FUNMODE (UI2C_CTL [2:0]) = 100b. When enable this port, the USCI interfaces to the I2C bus
via two pins: SDA and SCL. When I/O pins are used as I2C ports, user must set the pins function
to I2C in advance.
Note: Pull-up resistor is needed for I2C operation because the SDA and SCL are set to open-drain
pins when USCI is selected to I2C operation mode .
6.22.2 Features
Full master and slave device capability
Supports of 7-bit addressing, as well as 10-bit addressing
Communication in standard mode (100 kBit/s) or in fast mode (up to 400 kBit/s)
Supports multi-master bus
Supports 10-bit bus time-out capability
Supports bus monitor mode.
Supports Power down wake-up by data toggle or address match
Supports setup/hold time programmable
Supports multiple address recognition (two slave address with mask option)
Aug. 08, 2018
Page 106 of 140
Rev 1.04
NUC126
6.23
UART Interface Controller (UART)
6.23.1 Overview
The NUC126 series provides three channels of Universal Asynchronous Receiver/Transmitters
(UART). The UART controller performs Normal Speed UART and supports flow control function.
The UART controller performs a serial-to-parallel conversion on data received from the peripheral
and a parallel-to-serial conversion on data transmitted from the CPU. Each UART controller
channel supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN and
RS-485 function modes and auto-baud rate measuring function.
6.23.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Support for 3/16 bit duration for normal mode
Supports LIN function mode
– Supports LIN master/slave mode
– Supports programmable break generation function for transmitter
– Supports break detection function for receiver
Supports RS-485 function mode
– Supports RS-485 9-bit mode
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Support PDMA transfer function
Aug. 08, 2018
Page 107 of 140
Rev 1.04
NUC126
6.24
Watchdog Timer (WDT)
6.24.1 Overview
The Watchdog Timer (WDT) is used to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, the
Watchdog Timer supports the function to wake up system from Idle/Power-down mode.
6.24.2 Features
Supports 18-bit free running up counter
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214s if
WDT_CLK is 10 kHzSupports selectable WDT reset delay period between WDT time-out
event to WDT reset system event, and it includes 1026、130、18 or 3 * WDT_CLK delay
period
System kept in reset state about 63 * WDT_CLK period time after system reset event
occurred
Supports to force WDT function enabled after chip powered on or reset by setting
CWDTEN[2:0] in Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT
6.24.3 Clock Control
The WDT clock control is shown in Figure 6.24-1.
WDTSEL (CLK_CLKSEL1[1:0])
WDTCKEN (CLK_APBCLK0[0])
WDT_CLK
32.768 kHz (LXT)
HCLK/2048
01
10
11
10 kHz (LIRC)
Figure 6.24-1 Watchdog Timer Clock Control
Aug. 08, 2018
Page 108 of 140
Rev 1.04
NUC126
6.25
Window Watchdog Timer (WWDT)
6.25.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset while WWDT counter is
not reload within a specified window period when application program run to uncontrollable status
by any unpredictable condition.
6.25.2 Features
Supports 6-bit down counter value CNTDAT (WWDT_CNT[5:0]) and maximum 6-bit
compare value CMPDAT (WWDT_CTL[21:16]) to adjust the WWDT compare time-out
window period flexible
Supports PSCSEL (WWDT_CTL[11:8]) to programmable maximum 11-bit prescale
counter period of WWDT counter
WWDT counter suspends in Idle/Power-down mode
WWDT counter only can be reloaded within in valid window period to prevent system
reset
6.25.3 Clock Control
The WWDT clock control and block diagram are shown as follows.
WWDTSEL (CLK_CLKSEL2[17:16])
WDTCKEN (CLK_APBCLK0[0])
HCLK/2048
WWDT_CLK
10
11
10 kHz (LIRC)
Figure 6.25-1 WWDT Clock Control
Aug. 08, 2018
Page 109 of 140
Rev 1.04
NUC126
7 APPLICATION CIRCUIT
AVCC
VREF
AVDD
USB_VBUS
USB_D-
33R
33R
USB_D+
USB OTG Slot
FB
DVCC
VDD
USB_VDD33_CAP
VDDIO
0.1uF
1uF
1uF
VBAT
VSS
DVCC
Power
0.1uF
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
CS
CLK
MISO
MOSI
VDD
VSS
FB
SPI Device
AVSS
VDD
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
DVCC
4.7K
DVCC
NUC126 Series
20p
4.7K
XT1_IN
CLK
DIO
I2C_SCL
I2C_SDA
VDD
VSS
I2C Device
4~ 24 MHz
crystal
20p
20p
XT1_OUT
X32_IN
Crystal
DVCC
32.768kHz
crystal
20p
X32_OUT
SC_PWR
SC_RST
SC_CLK
Smart Card Slot
DVCC
SC_DAT
SC_ Detect
Reset
Circuit
10K
nRST
10uF/10V
PC COM Port
RS 232 Transceiver
ROUT RIN
RXD
TXD
UART
LDO CAP
_
TIN
TOUT
LDO
1uF
Aug. 08, 2018
Page 110 of 140
Rev 1.04
NUC126
8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
+7.0
VDD + 0.3
24
UNIT
V
DC Power Supply
Input Voltage
VDD-VSS
VIN
-0.3
VSS – 0.3
V
Oscillator Frequency
1/tCLCL
TA
4
MHz
C
Operating Temperature
-40
+105
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
IDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
ISS
120
Maximum Current sunk by a I/O Pin
Maximum Current Sourced by a I/O Pin
Maximum Current Sunk by Total I/O Pins
Maximum Current Sourced by Total I/O Pins
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device.
Aug. 08, 2018
Page 111 of 140
Rev 1.04
NUC126
8.2 DC Electrical Characteristics
(VDD-VSS = 2.5 ~ 5.5V, TA = 25C, FOSC = 72 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD
VSS
–
Operation Voltage
2.5
1.8
-
5.5
5.5
V
V
V
V
V
VDD = 2.5 ~ 5.5V up to 72 MHz
Power supply for PE.8 VDDIO
-
-
~ PE.13
– VSS
Power
supply
for VBAT
VSS
–
2.5
5.5
PF.0, PF.1 and PF.2
VSS
AVSS
–
Power Ground
-0.05
1.62
-
+0.05
1.98
MCU operating in Run, Idle or Power-down
mode
VLDO
1.8
LDO Output Voltage
Band-gap Voltage
CLDO
VBG
1
uF Connect to LDO_CAP pin
V
-
1.21
-
Allowed
difference for VDD and
AVDD
voltage
VDD
AVDD
–
-0.3
-
+0.3
V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
V
IDD1
-
-
mA
57
Operating Current
Normal Run Mode
HCLK =72 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
V
X
V
X
IDD2
IDD3
IDD4
-
-
-
-
-
-
mA
mA
mA
22
57
22
X
X
X
X
X
X
V
V
V
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
HIRC48
PLL
IDD5
-
-
mA
55
Operating Current
Normal Run Mode
HCLK =72 MHz
while(1){}executed
from flash
5.5 V
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
V
X
V
X
IDD6
IDD7
IDD8
-
-
-
-
-
-
mA
mA
mA
21
55
21
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
V
IDD9
-
-
mA
33
Operating Current
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
V
X
V
X
IDD10
IDD11
IDD12
-
-
-
-
-
-
mA
mA
mA
14
33
14
X
X
X
X
X
X
V
V
V
VLDO=1.8 V
Aug. 08, 2018
Page 112 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
All digital
module
VDD
HXT
X
HIRC
X
HIRC48
V
PLL
X
IDD13
-
-
mA
TBD
Operating Current
Normal Run Mode
HCLK =48 MHz
while(1){}executed
from flash
5.5 V
V
IDD14
IDD15
IDD16
-
-
-
-
-
-
mA
mA
mA
TBD
TBD
TBD
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
V
V
V
X
X
X
X
V
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IDD17
-
-
mA
15.8
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
5.5 V 24 MHz
5.5 V 24 MHz
3.3 V 24 MHz
3.3 V 24 MHz
V
X
V
X
IDD18
IDD19
IDD20
-
-
-
-
-
-
mA
mA
mA
6.7
15.8
6.7
X
X
X
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
X
HIRC48
PLL
X
IDD21
-
-
mA
TBD
Operating Current
Normal Run Mode
HCLK =24 MHz
while(1){}executed
from flash
5.5 V
HIRC48/2
V
X
V
X
IDD22
IDD23
IDD24
-
-
-
-
-
-
mA
mA
mA
TBD
TBD
TBD
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
HIRC48/2
HIRC48/2
HIRC48/2
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
V
HIRC48
X
PLL
X
IDD25
-
-
mA
16.6
Operating Current
Normal Run Mode
HCLK =22.1184 MHz
while(1){}executed
from flash
5.5 V
V
X
V
X
IDD26
IDD27
IDD28
-
-
-
-
-
-
mA
mA
mA
6.2
16.6
6.2
5.5 V
3.3 V
3.3 V
X
X
X
V
V
V
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IDD29
-
-
mA
7.8
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
V
X
V
X
IDD30
IDD31
IDD32
-
-
-
-
-
-
mA
mA
mA
3.1
7.8
3.1
X
X
X
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IDD33
-
-
mA
2.74
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}executed
from flash
5.5 V 4 MHz
5.5 V 4 MHz
3.3 V 4 MHz
3.3 V 4 MHz
V
X
V
X
IDD34
IDD35
IDD36
IDD37
-
-
-
-
-
-
-
-
mA
mA
mA
uA
1.23
2.72
1.20
136
X
X
X
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
LXT
LIRC
PLL
Operating Current
Aug. 08, 2018
Page 113 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Normal Run Mode
HCLK =32.768 kHz
while(1){}executed
from flash
5.5 V 32.768 kHz
5.5 V 32.768 kHz
3.3 V 32.768 kHz
3.3 V 32.768 kHz
X
X
X
X
X
X
X
X
V
X
V
X
IDD38
IDD39
IDD40
-
-
-
-
-
-
uA
uA
uA
123
123
109
VLDO=1.8 V
All digital
module
VDD
LXT
X
LIRC
PLL
X
IDD41
-
-
uA
121
Operating Current
Normal Run Mode
HCLK =10 kHz
while(1){}executed
from flash
5.5 V
10 kHz
V
X
V
X
IDD42
IDD43
IDD44
-
-
-
-
-
-
uA
uA
uA
117
107
102
5.5 V
3.3 V
3.3 V
X
X
X
10 kHz
10 kHz
10 kHz
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
PLL
V
IIDLE1
-
-
mA
47
Operating Current
Idle Mode
HCLK =72 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
X
X
X
X
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
-
-
-
-
-
-
mA
mA
mA
9
47
9
X
X
X
V
V
V
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
X
HIRC48
V
PLL
V
IIDLE5
-
-
mA
47
Operating Current
Idle Mode
HCLK =72 MHz
while(1){}executed
from flash
5.5 V
V
X
V
X
IIDLE6
IIDLE7
IIDLE8
-
-
-
-
-
-
mA
mA
mA
9.5
47
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
V
V
V
V
V
V
VLDO=1.8 V
9.5
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
V
IIDLE9
-
-
mA
27
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
V
X
V
X
IIDLE10
IIDLE11
IIDLE12
-
-
-
-
-
-
mA
mA
mA
5.5
27
X
X
X
X
X
X
V
V
V
VLDO=1.8 V
5.5
All digital
module
VDD
HXT
X
HIRC
X
HIRC48
V
PLL
X
IIDLE13
-
-
mA
TBD
Operating Current
Idle Mode
HCLK =48 MHz
while(1){}executed
from flash
5.5 V
V
X
V
X
IIDLE14
IIDLE15
IIDLE16
-
-
-
-
-
-
mA
mA
mA
TBD
TBD
TBD
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
V
V
V
X
X
X
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =24 MHz
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IIDLE17
-
-
mA
12.5
5.5 V 24 MHz
V
Aug. 08, 2018
Page 114 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
while(1){}executed
from flash
IIDLE18
IIDLE19
IIDLE20
-
-
-
-
-
-
mA
mA
mA
2.2
12.5
2.2
5.5 V 24 MHz
3.3 V 24 MHz
3.3 V 24 MHz
X
X
X
X
X
X
X
X
X
X
V
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
X
HIRC48
PLL
X
IIDLE21
-
-
mA
TBD
Operating Current
Idle Mode
HCLK =24 MHz
while(1){}executed
from flash
5.5 V
HIRC48/2
V
X
V
X
IIDLE22
IIDLE23
IIDLE24
-
-
-
-
-
-
mA
mA
mA
TBD
TBD
TBD
5.5 V
3.3 V
3.3 V
X
X
X
X
X
X
HIRC48/2
HIRC48/2
HIRC48/2
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
X
HIRC
V
HIRC48
X
PLL
X
IIDLE25
-
-
mA
12.3
Operating Current
Idle Mode
HCLK =22.1184 MHz
while(1){}executed
from flash
5.5 V
V
X
V
X
IIDLE26
IIDLE27
IIDLE28
-
-
-
-
-
-
mA
mA
mA
1.9
12.3
1.9
5.5 V
3.3 V
3.3 V
X
X
X
V
V
V
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IIDLE29
-
-
mA
6.3
Operating Current
Idle Mode
HCLK =12 MHz
while(1){}executed
from flash
5.5 V 12 MHz
5.5 V 12 MHz
3.3 V 12 MHz
3.3 V 12 MHz
V
X
V
X
IIDLE30
IIDLE31
IIDLE32
-
-
-
-
-
-
mA
mA
mA
1.2
6.3
1.2
X
X
X
X
X
X
X
X
X
VLDO=1.8 V
All digital
module
VDD
HXT
HIRC
X
HIRC48
X
PLL
X
IIDLE33
-
-
mA
2.2
Operating Current
Idle Mode
HCLK =4 MHz
while(1){}executed
from flash
5.5 V 4 MHz
5.5 V 4 MHz
3.3 V 4 MHz
3.3 V 4 MHz
V
X
V
X
IIDLE34
IIDLE35
IIDLE36
-
-
-
-
-
-
mA
mA
mA
0.50
2.2
X
X
X
X
X
X
X
X
X
VLDO=1.8 V
0.46
All digital
module
VDD
LXT
LIRC
PLL
X
IIDLE37
-
-
uA
129
Operating Current
Idle Mode
HCLK =32.768 kHz
while(1){}executed
from flash
5.5 V 32.768 kHz
5.5 V 32.768 kHz
3.3 V 32.768 kHz
3.3 V 32.768 kHz
X
X
X
X
V
X
V
X
IIDLE38
IIDLE39
IIDLE40
-
-
-
-
-
-
uA
uA
uA
115
115
101
X
X
X
VLDO=1.8 V
All digital
module
Operating Current
Idle Mode
HCLK =10 kHz
while(1){}executed
from flash
VDD
LXT
X
LIRC
PLL
X
IIDLE41
-
-
-
-
uA
uA
119
114
5.5 V
10 kHz
V
IIDLE42
5.5 V
X
10 kHz
X
X
Aug. 08, 2018
Page 115 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VLDO=1.8 V
IIDLE43
IIDLE44
-
-
-
-
uA
uA
104
100
3.3 V
3.3 V
X
X
10 kHz
10 kHz
X
X
V
X
RAM
retention
VDD HXT/HIRC LXT/LIRC
PLL
X
IPWD1
-
-
uA
TBD
5.5 V
5.5 V
5.5 V
5.5 V
3.3 V
3.3 V
3.3 V
3.3 V
X
X
X
X
X
X
X
X
LXT
LIRC
V
V
V
V
V
V
V
V
IPWD2
IPWD3
IPWD4
IPWD5
IPWD6
IPWD7
IPWD8
-
-
-
-
-
-
-
-
-
uA
uA
uA
uA
uA
uA
uA
TBD
TBD
20
X
X
X
X
X
X
X
LXT & LIRC
X
Standby Current
Power-down Mode
VLDO=1.8 V
-
-
-
-
13.5
13.3
14.3
12.5
LXT
LIRC
LXT & LIRC
X
Logic 0 Input Current
(Quasi-bidirectional
mode)
IIL
-
-
-70
-
-
uA
uA
VDD = VBAT = VDDIO = 5.5V, VIN = 0V
Logic 1 to 0 Transition
Current
(Quasi- ITL
-620
VDD = VBAT = VDDIO = 5.5V, VIN = 2.0V
bidirectional mode) [3]
-
-
TBD
TBD
-
-
KΩ
KΩ
VDD = VBAT = VDDIO = 5.5V
VDD = VBAT = VDDIO = 3.3V
Input Pull Up Resistor RIN
Input Leakage Current ILK
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V
-
-
TBD
0
-
-
KΩ
VDD = VBAT = VDDIO = 5.5V, 0 < VIN < VDD
Open-drain or input only mode
A
-0.3
-0.3
-
-
0.8
0.6
V
V
VDD = VBAT = VDDIO = 4.5 V
VDD = VBAT = VDDIO = 2.5 V
Input Low Voltage
VIL1
(TTL input)
Input Low Voltage
(TTL input for VDDIO VIL2
domain)
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V
-0.3
-
TBD
V
VDD
0.3
+
2.0
1.5
-
-
V
V
VDD = VBAT = VDDIO = 5.5V
VDD = VBAT = VDDIO = 2.5V
Input High Voltage
VIH1
(TTL input)
VDD
0.3
+
Input High Voltage
(TTL input for VDDIO VIH2
domain)
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V
VDD
0.3
+
TBD
-0.3
-
-
V
V
Input Low Voltage
VIL3
0.3VDD
VDD = VBAT = VDDIO = 2.5 ~ 5.5 V
(Schmitt input)
Aug. 08, 2018
Page 116 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Input Low Voltage
VIL4
for
-0.3
-
0.3VDD
V
V
V
V
VDDIO = 1.8 ~ 5.5V
VDD = VBAT = VDDIO = 2.5 ~ 5.5V
VDDIO = 1.8 ~ 5.5V
(Schmitt
VDDIO domain)
input
Input High Voltage
(Schmitt input)
VDD +
0.3
VIH3 0.7VDD
-
Input High Voltage
0.7VDDI
VDDIO
0.3
+
VIH4
for
-
(Schmitt
VDDIO domain)
input
O
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
-
0.2VDD
-
Negative
threshold
going
VIL5
-0.3
-
0.2VDD
V
(Schmitt
nRESET
input),
Positive
going
threshold
VDD
0.3
+
VIH5 0.8VDD
-
V
(Schmitt
nRESET
Input),
Internal nRESET pin
pull up resistor
RRST
-
16
-
KΩ
VDD = 5.5V
ISR1
ISR2
ISR3
-
-
-
-400
-80
-
-
-
uA
uA
uA
VDD = VBAT = VDDIO = 4.5V, VS = 2.4V
VDD = VBAT = VDDIO = 2.7V, VS = 2.2V
VDD = VBAT = VDDIO = 2.5V, VS = 2.0V
Source Current
(Quasi-bidirectional
Mode)
-73
Source Current
VDD = VBAT = 2.5 ~ 5.5V
VDDIO = 1.8V, VS = 1.6V
(Quasi-bidirectional
ISR4
-
-19
-
uA
Mode
for
VDDIO
domain)
ISR5
ISR6
ISR7
-18
-26
-5.8
-5.2
mA
mA
mA
VDD = VBAT = VDDIO = 4.5V, VS = 2.4V
VDD = VBAT = VDDIO = 2.7V, VS = 2.2V
VDD = VBAT = VDDIO = 2.5V, VS = 2.0V
Source Current
-
-
-
-
(Push-pull Mode)
Source Current
VDD = VBAT = 2.5 ~ 5.5V
VDDIO = 1.8V, VS = 1.6V
ISR8
-
-1.5
-
mA
(Push-pull Mode for
VDDIO domain)
ISK1
ISK2
ISK3
7
-
15
10
9
-
-
-
mA
mA
mA
VDD = VBAT = VDDIO = 4.5V, VS = 0.45V
VDD = VBAT = VDDIO = 2.7V, VS = 0.45V
VDD = VBAT = VDDIO = 2.5V, VS = 0.45V
Sink Current
(Quasi-bidirectional,
Open-Drain and Push-
pull Mode)
-
Aug. 08, 2018
Page 117 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
Sink Current
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD = VBAT = 2.5 ~ 5.5V
VDDIO = 1.8V, VS = 1.6V
(Quasi-bidirectional,
Open-Drain and Push-
pull Mode for VDDIO
domain)
ISK4
-
-
-2.2
-
-
mA
VDD = VBAT = VDDIO = 5.5V
, without capacitor
HIORR1
HIORR2
HIORR3
HIORR4
2.46
3.24
3.12
4.56
ns
ns
ns
ns
VDD = VBAT = VDDIO = 5.5V
, with 10pF capacitor
VDD = VBAT = VDDIO = 3.0V
, without capacitor
-
-
-
-
VDD = VBAT = VDDIO = 3.0V
, with 10pF capacitor
Higher GPIO Rising
Rate
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, without capacitor
(for VDDIO domain)
HIORR5
HIORR6
-
-
TBD
TBD
-
-
ns
ns
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, with 10pF capacitor
(for VDDIO domain)
VDD = VBAT = VDDIO = 5.5V
, without capacitor
BIORR1
BIORR2
BIORR3
BIORR4
-
-
-
-
3.24
4.15
4.75
6.43
-
-
-
-
ns
ns
ns
ns
VDD = VBAT = VDDIO = 5.5V
, with 10pF capacitor
VDD = VBAT = VDDIO = 3.0V
, without capacitor
VDD = VBAT = VDDIO = 3.0V
, with 10pF capacitor
Basic GPIO Rising
Rate
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, without capacitor
(for VDDIO domain)
BIORR5
-
TBD
-
ns
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, with 10pF capacitor
(for VDDIO domain)
BIORR6
HIOFR1
-
-
TBD
2.10
-
-
ns
ns
VDD = VBAT = VDDIO = 5.5V
, without capacitor
Higher GPIO Falling
Rate
Aug. 08, 2018
Page 118 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD = VBAT = VDDIO = 5.5V
, with 10pF capacitor
HIOFR2
HIOFR3
HIOFR4
-
-
-
2.83
3.12
4.19
-
-
-
ns
ns
ns
VDD = VBAT = VDDIO = 3.3V
, without capacitor
VDD = VBAT = VDDIO = 3.3V
, with 10pF capacitor
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, without capacitor
(for VDDIO domain)
HIOFR5
HIOFR6
-
-
TBD
TBD
-
-
ns
ns
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, with 10pF capacitor
(for VDDIO domain)
VDD = VBAT = VDDIO = 5.5V
, without capacitor
BIOFR1
BIOFR2
BIOFR3
BIOFR4
-
-
-
-
3.42
4.40
6.14
7.87
-
-
-
-
ns
ns
ns
ns
VDD = VBAT = VDDIO = 5.5V
, with 10pF capacitor
VDD = VBAT = VDDIO = 3.3V
, without capacitor
VDD = VBAT = VDDIO = 3.3V
, with 10pF capacitor
Basic GPIO Falling
Rate
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, without capacitor
(for VDDIO domain)
BIOFR5
BIOFR6
-
-
TBD
TBD
-
-
ns
ns
VDD = VBAT = 2.5 ~ 5.5V
, VDDIO = 1.8V, with 10pF capacitor
(for VDDIO domain)
Aug. 08, 2018
Page 119 of 140
Rev 1.04
NUC126
8.3 AC Electrical Characteristics
8.3.1
External 4~24 MHz High Speed Crystal (HXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
tCLCH
tCHCL
VIH
nS
nS
nS
nS
V
10
-
-
-
-
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
Input High Voltage
Input Low Voltage
10
2
15
2
0.7VDD
0
15
VDD
0.3VDD
VIL
V
tCLCL
tCLCH
tCLCX
90%
10%
VIH
VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
8.3.2
External 4~24 MHz High Speed Crystal (HXT) Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Oscillator frequency
Temperature
fHXT
4
-40
-
-
-
24
MHz
C
VDD = 2.5 ~ 5.5V
THXT
+105
TBD
0.4
-
-
mA
mA
VDD = 5.5V @ 12MHz
VDD = 3.3V @ 12MHz
Operating current
IHXT
-
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
20pF
R1
4MHz ~ 24 MHz
20pF
without
Aug. 08, 2018
Page 120 of 140
Rev 1.04
NUC126
XT_OUT
XT_IN
R1
C1
C2
Figure 8.3-1 Typical Crystal Application Circuit
8.3.3
External 32.768 kHz Low Speed Crystal (LXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Clock High Time
tCHCX
tCLCX
tCLCH
tCHCL
nS
nS
nS
nS
TBD
TBD
TBD
TBD
-
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
-
TBD
TBD
LXT Input Pin Input High Xin_VIH
Voltage
V
V
0.7VLDO
0
-
-
VLDO
LXT Input Pin Input Low Xin_VIL
Voltage
0.3VLDO
tCLCL
tCLCH
tCLCX
90%
10%
Xin_VIH
Xin_VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
Aug. 08, 2018
Page 121 of 140
Rev 1.04
NUC126
8.3.4
External 32.768 kHz Low Speed Crystal (LXT) Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
-
TYP. MAX. UNIT
Oscillator frequency
Temperature
fLXT
TLXT
ILXT
32.768
-
kHz
VDD = VBAT = 2.5 ~ 5.5V
-40
-
+105 C
A
Operating current
0.7
VDD = VBAT = 2.5 ~ 5.5V
8.3.4.1 Typical Crystal Application Circuits
CRYSTAL
C3
20pF
C4
20pF
R2
32.768 kHz
without
XT_OUT
XT_IN
R2
C3
C4
Figure 8.3-2 Typical Crystal Application Circuit
Aug. 08, 2018
Page 122 of 140
Rev 1.04
NUC126
8.3.5
Internal 48 MHz High Speed RC Oscillator (HIRC48)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Center Frequency
-
48
-
-
MHz
%
TA = 25C, VDD = 3.3V
TA = 25C,
-1
+1
VDD = 2.5 ~ 5.5V
TA = -40C ~ +105 C,
fHRC
-2
-
+2
%
Calibrated Internal
Oscillator Frequency
VDD = 2.5 ~ 5.5V
TA = -40C ~ +105 C,
VDD = 2.5 ~ 5.5V
-0.25
-
-
+0.25
-
%
Auto trimmed by LXT
Operating current
IHRC
440
A
8.3.6
Internal 22.1184 MHz High Speed RC Oscillator (HIRC)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
22.11
84
Center Frequency
-
-
MHz
%
TA = 25C, VDD = 3.3V
TA = 25C,
-1
-2
-
+1
+2
VDD = 2.5 ~ 5.5V
fHRC
-40C ~ +105 C,
-
%
Calibrated Internal
Oscillator Frequency
VDD = 2.5 ~ 5.5V
-40C ~ +105 C,
VDD = 2.5 ~ 5.5V
-0.25
-
-
+0.25
-
%
Auto trimmed by LXT
Operating current
IHRC
470
A
8.3.7
Internal 10 kHz Low Speed RC Oscillator (LIRC)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Center Frequency
Calibrated
-
10
-
-
kHz
%
TA = 25C, VDD = 3.3V
FLRC
TA = 25 C,
Internal
-30
+30
Oscillator Frequency
VDD = 2.5 ~ 5.5V
Aug. 08, 2018
Page 123 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
-40C ~+105 C,
-50
-
+50
%
VDD = 2.5 ~ 5.5V
Operating current
ILRC
0.9
A
Aug. 08, 2018
Page 124 of 140
Rev 1.04
NUC126
8.4 Analog Characteristics
8.4.1
LDO
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Temperature
TA
-40
2.5
+105
5.5
oC
-
-
DC Power Supply
Output Voltage
VDD
VLDO
V
V
1.62
1.8
1.98
Note 1: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS
pin of the device.
Note 2: For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin
and the closest VSS pin of the device.
8.4.2
Temperature Sensor
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Detection Temperature
Gain
TDET
VTG
-40
-1.76
-
+105
-1.64 mV/ oC
oC
-
-1.70
745
-
Offset
VTO
-
mV Temperature at 0 oC
A
Operating current
ITEMP
6.4
10.5
Note 1: The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/℃ ) x Temperature (℃) + Offset (mV)
8.4.3 Internal Voltage Reference (Int_VREF
)
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
VREF (2.048V)
VREF1
VREF2
1.986
2.483
2.98
3.973
-
2.151
2.637
3.164
4.219
2000
-
V
V
VREFCTL = 3, AVDD≥2.5V
VREFCTL = 3, AVDD≥2.9V
VREFCTL = 3, AVDD≥3.4V
VREFCTL = 3, AVDD≥4.5V
CVREF = 4.7uF
VREF (2.56V)
-
-
VREF (3.072V)
VREF (4.096V)
Start-up Time
Operating current
VREF3
V
VREF4
-
V
TVREF_Start
IVREF
uS
A
700
100
Aug. 08, 2018
Page 125 of 140
Rev 1.04
NUC126
8.4.4
Power-on Reset
PARAMETER
SPECIFICATIONS
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Temperature
Threshold Voltage
TA
-40
-
+105
-
oC
-
VPOR
V
2
8.4.5
Low-Voltage Reset
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Temperature
TA
-40
2.0
1.8
1.75
-
+105
2.45
2.2
2.2
-
oC
-
TA = +105℃
V
2.2
2.0
1.95
130
1.1
TA = +25℃
TA = -40 ℃
TA = +25℃
Threshold Voltage
VLVR
V
V
Start-up Time
TLVR_Start
ILVR
uS
uA
Quiescent Current
AVDD = 5.5V
-
-
8.4.6
Brown-out Detector
SPECIFICATIONS
MIN. TYP. MAX. UNIT
PARAMETER
SYM.
TEST CONDITION
Temperature
TA
-40
4.2
3.5
2.55
2.05
4.3
3.6
2.6
2.1
-
+105
4.6
3.9
2.85
2.35
4.7
4.0
2.9
2.4
-
oC
-
V
BODVL [1:0] = 11
BODVL [1:0] = 10
BODVL [1:0] = 01
BODVL [1:0] = 00
BODVL [1:0] = 11
BODVL [1:0] = 10
BODVL [1:0] = 01
BODVL [1:0] = 00
TA = +25℃
4.4
V
3.7
Brown-out Voltage
(Falling edge)
VBODF
V
2.7
V
2.2
V
4.5
V
3.8
Brown-out Voltage
(Rising edge)
VBODR
V
2.75
2.25
1030
V
Start-up Time
TBOD_Start
uS
TA = +25℃, AVDD = 5.5V
Quiescent Current
IBOD
uA
83
-
BODLPM = 0
Aug. 08, 2018
Page 126 of 140
Rev 1.04
NUC126
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
TA = +25℃, AVDD = 5.5V
uA
0.7
BODLPM = 1
8.4.7
12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN. TYP. MAX. UNIT
Temperature
TA
AVDD
VREF
VIN
-40
3.0
3.0
0
+105
5.5
oC
-
-
Operating voltage
Reference voltage
ADC input voltage
Resolution
V
AVDD = VDD
V
AVDD
AVREF
V
-
12
+1.5
+1.5
-2
RADC
INL
Bit
Integral Non-Linearity Error
Differential Non-Linearity
Gain error
LSB
LSB
LSB
LSB
LSB
-
-2
-1
-4
-4
-4
+2
+2
+4
+4
+4
DNL
EG
Offset error
EOFFSET
EABS
-
2
Absolute error
-
Monotonic
Guaranteed
ADC Clock frequency
FADC
MHz
1
2
16
21
Acquisition Time (Sample
Stage)
TACQ
1/FADC Default: 7 (1/FADC)
7
TCONV = TACQ + 13
1/FADC
Conversion time
TCONV
15
-
20
34
Default: 20 (1/FADC)
Conversion Rate
TCONV = 20 clock
kSPS
FSPS
-
800
FADC = 16 MHz
(FADC/TCONV
)
Internal Capacitance[1]
Input Load[1]
CIN
RIN
pF
-
-
TBD
TBD
-
-
kΩ
AVDD = VDD = 5V
mA
Operating current
IADC1
-
4
-
ADC Clock Rate = 16 MHz
Note 1: Design by guarantee, no test in production.
Aug. 08, 2018
Page 127 of 140
Rev 1.04
NUC126
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Typical connection diagram using the ADC
VDD
(1)
RIN
12-bit
Converter
AINx
(1)
CIN
Note: GND < AINX <VREF < VDD
Aug. 08, 2018
Page 128 of 140
Rev 1.04
NUC126
8.4.8 Analog Comparator
PARAMETER SYM.
SPECIFICATIONS
TEST CONDITION
MIN. TYP. MAX. UNIT
Temperature
TA
-40
0.1
+105
oC
-
-
AVDD
-
Input Common Mode Range
VCOM
V
0.1
Input Offset Voltage
Hysteresis
VOFF
VHYS
-
-
10
60
-
-
mV
mV
dB
nS
uS
uA
V
HYSEN = 0
10
40
HYSEN = 1, VCM = AVDD/2
DC Gain[1005D
70
Propagation Delay
Stable time
TPGD
TSTB
ICMP
VREF
VIN
125
0.35
35
200
1
VCM = 1.2 V, VDIFF = 0.1 V
AVDD = 5V
Operation Current
Reference voltage
ADC input voltage
70
3.0
0
AVDD
AVREF
V
-
Note1: Guaranteed by design, not tested in production.
Aug. 08, 2018
Page 129 of 140
Rev 1.04
NUC126
8.4.9
USB PHY
8.4.9.1 Low-full-Speed DC Electrical Specifications
Symbol
VIH
Parameter
Input High (driven)
Min.
2.0
-
Typ.
Max.
Unit
V
Test Conditions
-
-
-
-
0.8
-
-
VIL
Input Low
V
-
VDI
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
0.8
0.8
-
-
2.5
2.0
V
V
Includes VDI range
-
Common-mode Range
Single-ended
Threshold
Receiver
VSE
Receiver Hysteresis
Output Low (driven)
Output High (driven)
Output Signal Cross Voltage
Pull-up Resistor
-
200
-
mV
V
-
-
-
-
-
VOL
VOH
VCRS
RPU
RPD
0
-
-
-
-
-
0.3
2.8
3.6
V
1.3
2.0
V
1.425
14.25
1.575
15.75
kΩ
kΩ
Pull-down Resistor
TERMINATION
Voltage
for
VTRM
3.0
-
3.6
V
Uptream port pull up (RPU)
Driver Output Resistance
Transceiver Capacitance
ZDRV
CIN
-
-
10
-
-
Ω
Steady state drive*
Pin to GND
20
pF
*Driver output resistance doesn’t include series resistor resistance.
8.4.9.2 USB Full-Speed Driver Electrical Characteristics
Symbol
TFR
Parameter
Min.
4
Typ.
Max.
20
Unit
ns
Test Conditions
CL=50p
Rise Time
Fall Time
-
-
-
TFF
4
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
111.11
%
TFRFF=TFR/TFF
8.4.9.3 USB LDO Specification
Symbol
VBUS
Parameter
VBUS Pin Input Voltage
LDO Output Voltage
Min.
4.0
3.0
-
Typ.
5.0
Max.
5.5
3.6
-
Unit
Test Conditions
V
V
-
-
-
VDD33
Cbp
3.3
External Bypass Capacitor
1.0
uF
Aug. 08, 2018
Page 130 of 140
Rev 1.04
NUC126
8.5 Flash DC Electrical Characteris
Symbol
Parameter
Supply Voltage
Endurance
Min
Typ
Max
1.98
-
Unit
V
Test Condition
[1]
VFLA
1.62
1.8
cycles[2]
year
mS
NENDUR
TRET
20,000
-
-
-
-
-
-
-
-
Data Retention
Page Erase Time
Mass Erase Time
Program Time
Read Current
100
20
20
20
-
-
TERASE
TMER
TPROG
IDD1
40
mS
TA = 25℃
40
uS
40
mA
TBD
TBD
TBD
IDD2
Program Current
Erase Current
mA
-
IDD3
uA
-
Note 1: VFLA is source from chip LDO output voltage.
Note 2: Number of program/erase cycles.
Note 3: This table is guaranteed by design, not test in production.
Aug. 08, 2018
Page 131 of 140
Rev 1.04
NUC126
8.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
Max.
-
Min.
1.2
Max.
tLOW
tHIGH
SCL low period
SCL high period
-
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
4
4.7
4
-
0.6
-
tSU; STA
tHD; STA
tSU; STO
tBUF
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
-
1.2
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
-
-
-
Cb
Capacitive load for each bus line
-
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must
be higher than 8 MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to
bridge the undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch
the low period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-1 I2C Timing Diagram
Aug. 08, 2018
Page 132 of 140
Rev 1.04
NUC126
8.7 SPI Dynamic Characteristics
8.7.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
4
0
-
2
-
-
-
ns
ns
ns
Data hold time
Data output valid time
7
11
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
5
0
-
3
-
-
-
ns
ns
ns
Data hold time
Data output valid time
13
18
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tDS
tDH
tV
Data setup time
0
-
-
ns
ns
ns
Data hold time
2*PCLK+4
-
-
-
Data output valid time
2*PCLK+11
2*PCLK+19
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
tDS
Data setup time
0
-
-
ns
Aug. 08, 2018
Page 133 of 140
Rev 1.04
NUC126
tDH
tV
Data hold time
2*PCLK+6
-
-
-
ns
ns
Data output valid time
2*PCLK+19
2*PCLK+25
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 8.7-2 SPI Slave Mode Timing Diagram
Aug. 08, 2018
Page 134 of 140
Rev 1.04
NUC126
9 PACKAGE DIMENSIONS
9.1 LQFP 100L (14x14x1.4 mm footprint 2.0 mm)
Aug. 08, 2018
Page 135 of 140
Rev 1.04
NUC126
9.2 LQFP 64L (7x7x1.4 mm footprint 2.0 mm)
Aug. 08, 2018
Page 136 of 140
Rev 1.04
NUC126
9.3 LQFP 48L (7x7x1.4 mm Footprint 2.0 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
0.024 0.030
0.45
0
L
L
Y
0.039
0.004
7
1
0.10
7
0
0
Aug. 08, 2018
Page 137 of 140
Rev 1.04
NUC126
9.4
QFN 48L (7x7x0.8 mm)
Aug. 08, 2018
Page 138 of 140
Rev 1.04
NUC126
10 REVISION HISTORY
Date
Revision
Description
2017.05.05
1.00
1. Preliminary version
1. Revised part number in section 4.1.2
2017.07.13
2017.09.14
2017.12.15
1.01
1.02
1.03
2. Revised the range of Xin_VIH and Xin_VIL in section 8.3.3
1. Revised IPWD4, MIN sink current/source current in section 8.2
2. Revised LVR in section 8.4.5
3. Revised BOD in section 8.4.6
1. Revised HIRC trim description in section 6.2.8
2. Revised Clock Output description in section 6.3.5
1. Revised VDDIO description in section 1.1 and 4.1.2.
2. Revised Timer/PWM PWM mode description in section 2.1.
3. Revised VBAT description in section 4.1.2.
2018.08.08
1.04
4. Added NUC126 QFN48 information in section 2.1, 4.1, 4.2 and 9.4.
Aug. 08, 2018
Page 139 of 140
Rev 1.04
NUC126
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Aug. 08, 2018
Page 140 of 140
Rev 1.04
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