NUC1311-LD2AE_技术文档

NUC1311

Arm^®Cortex^®-M

32-bit Microcontroller

NuMicro^®Family

NUC1311 Series

Datasheet

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro^®microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

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TABLE OF CONTENTS

1 GENERAL DESCRIPTION.....................................................................................7

2 FEATURES ............................................................................................................8

3 ABBREVIATIONS ................................................................................................11

4 PARTS INFORMATION LIST AND PIN CONFIGURATION................................12

4.1 NuMicro^®NUC1311 Series Selection Code .................................................12

4.2 NuMicro^®NUC1311 Selection Guide .........................................................13

4.3 Pin Configuration .................................................................................14

4.3.1 NuMicro^®NUC1311 Pin Diagram ...................................................................14

4.4 Pin Description....................................................................................15

4.4.1 NuMicro^®NUC1311 Pin Description................................................................15

5 BLOCK DIAGRAM...............................................................................................19

5.1 NuMicro^®NUC1311 Block Diagram...........................................................19

6 FUNCTIONAL DESCRIPTION.............................................................................20

6.1 Arm^®Cortex^®-M0 Core ..........................................................................20

6.2 System Manager .................................................................................22

6.2.1 Overview ................................................................................................22

6.2.2 System Reset ..........................................................................................22

6.2.3 System Power Distribution ...........................................................................23

6.2.4 System Timer (SysTick) ..............................................................................24

6.2.5 Nested Vectored Interrupt Controller (NVIC)......................................................25

6.2.6 System Control.........................................................................................29

6.3 Clock Controller...................................................................................29

6.3.1 Overview ................................................................................................29

6.3.2 System Clock and SysTick Clock ...................................................................32

6.3.3 Power-down Mode Clock.............................................................................33

6.3.4 Frequency Divider Output ............................................................................33

6.4 Flash Memory Controller (FMC) ...............................................................35

6.4.1 Overview ................................................................................................35

6.4.2 Features.................................................................................................35

6.5 General Purpose I/O (GPIO) ...................................................................36

6.5.1 Overview ................................................................................................36

6.5.2 Features.................................................................................................36

6.6 Timer Controller (TIMER) .......................................................................37

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6.6.1 Overview ................................................................................................37

6.6.2 Features.................................................................................................37

6.7 PWM Generator and Capture Timer (PWM).................................................38

6.7.1 Overview ................................................................................................38

6.7.2 Features.................................................................................................38

6.8 Watchdog Timer (WDT) .........................................................................40

6.8.1 Overview ................................................................................................40

6.8.2 Features.................................................................................................40

6.9 Window Watchdog Timer (WWDT)............................................................41

6.9.1 Overview ................................................................................................41

6.9.2 Features.................................................................................................41

6.10UART Interface Controller (UART) ............................................................42

6.10.1 Overview ................................................................................................42

6.10.2 Features.................................................................................................42

6.11I²C Serial Interface Controller (I²C)............................................................43

6.11.1 Overview ................................................................................................43

6.11.2 Features.................................................................................................43

6.12Serial Peripheral Interface (SPI) ...............................................................44

6.12.1 Overview ................................................................................................44

6.12.2 Features.................................................................................................44

6.13Controller Area Network (CAN) ................................................................45

6.13.1 Overview ................................................................................................45

6.13.2 Features.................................................................................................45

6.14Analog-to-Digital Converter (ADC) ............................................................46

6.14.1 Overview ................................................................................................46

6.14.2 Features.................................................................................................46

7 APPLICATION CIRCUIT......................................................................................47

8 ELECTRICAL CHARACTERISTICS....................................................................48

8.1 Absolute Maximum Ratings.....................................................................48

8.2 DC Electrical Characteristics ...................................................................49

8.3 AC Electrical Characteristics ...................................................................53

8.3.1 External 4~24 MHz High Speed Clock Input Signal Characteristics ..........................53

8.3.2 External 4~24 MHz High Speed Crystal ...........................................................54

8.3.3 Internal 22.1184 MHz High Speed Oscillator .....................................................56

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8.3.4 Internal 10 kHz Low Speed Oscillator ..............................................................57

8.4 Analog Characteristics...........................................................................58

8.4.1 12-bit SARADC Specification........................................................................58

8.4.2 LDO and Power Management Specification ......................................................59

8.4.3 Low Voltage Reset Specification....................................................................60

8.4.4 Brown-out Detector Specification ...................................................................60

8.4.5 Power-on Reset Specification .......................................................................60

8.5 Flash DC Electrical Characteristics............................................................61

8.6 I²C Dynamic Characteristics....................................................................62

8.7 SPI Dynamic Characteristics ...................................................................63

9 PACKAGE DIMENSIONS ....................................................................................65

9.1 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................65

10REVISION HISTORY............................................................................................66

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List of Figures

Figure 4.1-1 NuMicro^®NUC1311 Series Selection Code............................................................. 12

Figure 4.3-1 NuMicro^®NUC1311LxxAE LQFP 48-pin Diagram .................................................... 14

Figure 5.1-1 NuMicro^®NUC1311 Block Diagram .......................................................................... 19

Figure 6.1-1 Functional Controller Diagram................................................................................... 20

Figure 6.2-1 NuMicro^®NUC1311 Power Distribution Diagram...................................................... 23

Figure 6.3-1 Clock Generator Block Diagram................................................................................ 30

Figure 6.3-2 Clock Generator Global View Diagram...................................................................... 31

Figure 6.3-3 System Clock Block Diagram .................................................................................... 32

Figure 6.3-4 SysTick Clock Control Block Diagram....................................................................... 32

Figure 6.3-5 Clock Source of Frequency Divider........................................................................... 33

Figure 6.3-6 Frequency Divider Block Diagram............................................................................. 34

Figure 8.3-1 Typical Crystal Application Circuit ............................................................................. 55

Figure 8.3-2 HIRC Accuracy vs. Temperature............................................................................... 56

Figure 8.4-3 Power-up Ramp Condition ........................................................................................ 61

Figure 8.6-1 I²C Timing Diagram ................................................................................................... 62

Figure 8.7-1 SPI Master Mode Timing Diagram ............................................................................ 63

Figure 8.7-2 SPI Slave Mode Timing Diagram .............................................................................. 64

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List of Tables

Table 3-1 List of Abbreviations....................................................................................................... 11

Table 6.2-1 Exception Model ......................................................................................................... 26

Table 6.2-2 System Interrupt Map ................................................................................................. 27

Table 6.2-3 Vector Table Format................................................................................................... 28

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1

GENERAL DESCRIPTION

The NuMicro^®NUC1311 series is embedded with the Cortex^®-M0 core running up to 50 MHz and

features 36/68 KB Flash, 8 KB SRAM, and 4 KB loader ROM for the ISP. It is also equipped with

plenty of peripheral devices, such as Timers, Watchdog Timer (WDT), Window Watchdog Timer

(WWDT), UART, SPI, I²C, PWM, GPIO, built-in Controller Area Network (CAN) 2.0 interface, 760

kSPS high speed 12-bit ADC, Low Voltage Reset Controller and Brown-out Detector.

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2

FEATURES

 Arm^®Cortex^®-M0 core

– Runs up to 50 MHz

– One 24-bit system timer

– Supports low power sleep mode

– Single-cycle 32-bit hardware multiplier

– NVIC for the 32 interrupt inputs, each with 4-levels of priority

– Serial Wire Debug supports with 2 watchpoints/4 breakpoints

 Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V

 Flash Memory

– 36/68 KB Flash for program code

– Configurable Flash memory for data memory (Data Flash), 4 KB flash for ISP loader

– Supports In-System-Program (ISP) and In-Application-Program (IAP) application code

update

– 512 byte page erase for Flash

– Supports 2-wired ICP update through SWD/ICE interface

– Supports fast parallel programming mode by external programmer

 SRAM Memory

– 8 KB SRAM

 Clock Control

– Flexible selection for different applications

– Built-in 22.1184 MHz high speed oscillator for system operation

 Trimmed to ±1 % at +25 C and V_DD= 5 V

 Trimmed to ±2 % at -40 C ~ +105C and V_DD= 2.5 V ~ 5.5 V

– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation

– Supports one PLL, output frequency up to 200 MHz, PWM clock frequency up to 100 MHz,

and System operation frequency up to 50 MHz

– External 4~24 MHz high speed crystal input for precise timing operation

 GPIO

– Four I/O modes:

 Quasi-bidirectional

 Push-pull output

 Open-drain output

 Input only with high impendence

– TTL/Schmitt trigger input selectable

– I/O pin configured as interrupt source with edge/level setting

 Timer

– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter

– Independent clock source for each timer

– Provides one-shot, periodic, toggle and continuous counting operation modes

– Supports event counting function

– Supports input capture function

 Watchdog Timer

– Multiple clock sources

 System clock (HCLK)

 Internal 10 kHz oscillator (LIRC)

– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)

– Wake-up from Power-down or Idle mode

– Interrupt or reset selectable on watchdog time-out

 Window Watchdog Timer

– 6-bit down counter with 11-bit prescale for wide range window selected

 PWM/Capture

– Supports maximum clock frequency up to 100 MHz

– Supports up to two PWM modules, each module provides three 16-bit timers and 6 output

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channels

– Supports independent mode for PWM output/Capture input channel

– Supports complementary mode for 3 complementary paired PWM output channel

 Dead-time insertion with 12-bit resolution

 Two compared values during one period

– Supports 12-bit pre-scalar from 1 to 4096

– Supports 16-bit resolution PWM counter

 Up, down and up/down counter operation type

– Supports mask function and tri-state enable for each PWM pin

– Supports brake function

 Brake source from pin and system safety events (clock failed, Brown-out detection and

CPU lockup)

 Noise filter for brake source from pin

 Edge detect brake source to control brake state until brake interrupt cleared

 Level detect brake source to auto recover function after brake condition removed

– Supports interrupt on the following events:

 PWM counter match zero, period value or compared value

 Brake condition happened

– Supports trigger ADC on the following events:

 PWM counter match zero, period value or compared value

– Supports up to 12 capture input channels with 16-bit resolution

– Supports rising edges, falling edges or both edges capture condition

– Supports input rising edges, falling edges or both edges capture interrupt

– Supports rising edges, falling edges or both edges capture with counter reload option

 UART

– Up to 4 UART controllers

– UART0 and UART1 ports with flow control (TXD, RXD, nCTS and nRTS)

– UART0, UART1 and UART2 with 16-byte FIFO for standard device

– Supports IrDA (SIR) and LIN function

– Supports RS-485 9-bit mode and direction control

– Supports auto baud-rate generator

 SPI

– One set of SPI controller

– Supports SPI Master/Slave mode

– Full duplex synchronous serial data transfer

– Variable length of transfer data from 8 to 32 bits

– MSB or LSB first data transfer

– Rx and Tx on both rising or falling edge of serial clock independently

– Supports Byte Suspend mode in 32-bit transmission

– Supports three wire, no slave select signal, bi-direction interface

 I²C

– One set of I²C devices

– Master/Slave mode

– Bidirectional data transfer between masters and slaves

– Multi-master bus (no central master)

– Arbitration between simultaneously transmitting masters without corruption of serial data on

the bus

– Serial clock synchronization allowing devices with different bit rates to communicate via one

serial bus

– Serial clock synchronization used as a handshake mechanism to suspend and resume serial

transfer

– Programmable clocks allowing for versatile rate control

– Supports multiple address recognition (four slave address with mask option)

– Supports wake-up function

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 CAN 2.0

– One set of CAN device

– Supports CAN protocol version 2.0 part A and B

– Bit rates up to 1M bit/s

– 32 Message Objects

– Each Message Object has its own identifier mask

– Programmable FIFO mode (concatenation of Message Object)

– Maskable interrupt

– Disabled Automatic Re-transmission mode for Time Triggered CAN applications

– Support power-down wake-up function

 ADC

– 12-bit SAR ADC with 760 kSPS

– Up to 8-ch single-end input or 4-ch differential input

– Single scan/single cycle scan/continuous scan

– Each channel with individual result register

– Scan on enabled channels

– Threshold voltage detection

– Conversion started by software programming or external input

 96-bit unique ID (UID)

 128-bit unique customer ID(UCID)

 Brown-out Detector

– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V

– Supports Brown-out Interrupt and Reset option

 Low Voltage Reset

– Threshold voltage level: 2.0 V

 Operating Temperature: -40C ~ +105C

 Packages:

– All Green package (RoHS)

– LQFP 48-pin (7mm x 7mm)

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3

ABBREVIATIONS

Acronym

Description

ADC

APB

Analog-to-Digital Converter

Advanced Peripheral Bus

Advanced High-Performance Bus

Brown-out Detection

AHB

BOD

BPWM

CAN

DAP

FIFO

FMC

GPIO

HCLK

HIRC

HXT

Basic Pulse Width Modulation

Controller Area Network

Debug Access Port

First In, First Out

Flash Memory Controller

General-Purpose Input/Output

The Clock of Advanced High-Performance Bus

22.1184 MHz Internal High Speed RC Oscillator

4~24 MHz External High Speed Crystal Oscillator

In Application Programming

In Circuit Programming

IAP

ICP

ISP

In System Programming

LDO

LIN

Low Dropout Regulator

Local Interconnect Network

10 kHz internal low speed RC oscillator (LIRC)

Memory Protection Unit

LIRC

MPU

NVIC

PCLK

PLL

Nested Vectored Interrupt Controller

The Clock of Advanced Peripheral Bus

Phase-Locked Loop

PWM

SPI

Pulse Width Modulation

Serial Peripheral Interface

Samples per Second

SPS

TMR

UART

UCID

WDT

WWDT

Timer Controller

Universal Asynchronous Receiver/Transmitter

Unique Customer ID

Watchdog Timer

Window Watchdog Timer

Table 3-1 List of Abbreviations

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4

PARTS INFORMATION LIST AND PIN CONFIGURATION

4.1 NuMicro^®NUC1311 Series Selection Code

NUC1311- X X X X E

CPU core

ARM Cortex M0

Temperature

E : -40°C ~ +105°C

Package Type

Version

L : LQFP 48 (7x7)

A : Version

Flash ROM

SRAM Size

D : 68 KB Flash ROM

C : 32 KB Flash ROM

2 : 8 KB SRAM

Figure 4.1-1 NuMicro^®NUC1311 Series Selection Code

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4.2 NuMicro^®NUC1311 Selection Guide

Connectivity

NUC1311LC2AE

NUC1311LD2AE

36

68

8

Configurable

4

42

4

1

12

8 ch

√

LQFP48

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4.3 Pin Configuration

4.3.1 NuMicro^®NUC1311 Pin Diagram

4.3.1.1 NuMicro^®NUC1311LxxAE LQFP 48 pin

UART3_RXD/ADC_CH5/PA.5

UART3_TXD/ADC_CH6/PA.6

Vref/ADC_CH7/PA.7

AV_DD

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

PC.0/SPI0_SS0

PC.1/SPI0_CLK

PC.2/SPI0_MISO0

PC.3/SPI0_MOSI0

PD.15/UART2_TXD

PD.14/UART2_RXD

PD.7/CAN0_TXD

PD.6/CAN0_RXD

PWM0_BRAKE1/I2C0_SCL/PC.7

PWM0_BRAKE0/I2C0_SDA/PC.6

TM0/TM0_EXT/INT1/PB.15

XT1_OUT/PF.0

NUC1311LxxAE

LQFP 48-pin

PB.3/UART0_nCTS/TM3_EXT/TM3/PWM1_BRAKE0

PB.2/UART0_nRTS/TM2_EXT/TM2/PWM1_BRAKE1

PB.1/UART0_TXD

XT1_IN/PF.1

nRESET

CLKO/PF.8

CLKO/TM0/STADC/PB.8

PB.0/UART0_RXD

Figure 4.3-1 NuMicro^®NUC1311LxxAE LQFP 48-pin Diagram

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4.4 Pin Description

4.4.1 NuMicro^®NUC1311 Pin Description

Pin No.

Pin Name

Pin Type

Description

LQFP

48-pin

PB.12

I/O

O

General purpose digital I/O pin.

Frequency divider clock output pin.

General purpose digital I/O pin.

I2C0 clock pin.

1

2

CLKO

PF.5

I/O

I

I2C0_SCL

PWM1_CH5

PF.4

PWM1 CH5 output/Capture input.

General purpose digital I/O pin.

I2C0 data input/output pin.

3

I2C0_SDA

PWM1_CH4

PA.11

PWM1 CH4 output/Capture input.

General purpose digital I/O pin.

PWM1 CH3 output/Capture input.

General purpose digital I/O pin.

PWM1 CH2 output/Capture input.

General purpose digital I/O pin.

I2C0 clock pin.

4

5

PWM1_CH3

PA.10

PWM1_CH2

PA.9

6

7

I2C0_SCL

UART1_nCTS

PA.8

Clear to Send input pin for UART1.

General purpose digital I/O pin.

I2C0 data input/output pin.

I/O

O

I2C0_SDA

UART1_nRTS

PB.4

Request to Send output pin for UART1.

General purpose digital I/O pin.

Data receiver input pin for UART1.

General purpose digital I/O pin.

Data transmitter output pin for UART1.

LDO output pin.

I/O

I

8

9

UART1_RXD

PB.5

I/O

O

UART1_TXD

LDO_CAP

V_DD

10

11

12

P

Power supply for I/O ports and LDO source for internal PLL and digital circuit.

Ground pin for digital circuit.

V_SS

P

PB.0

I/O

I

General purpose digital I/O pin.

13

14

UART0_RXD

PB.1

Data receiver input pin for UART0.

I/O

O

General purpose digital I/O pin.

UART0_TXD

Data transmitter output pin for UART0.

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Pin No.

Pin Name

Pin Type

Description

LQFP

48-pin

PB.2

I/O

General purpose digital I/O pin.

Request to Send output pin for UART0.

Timer2 external capture input pin.

Timer2 toggle output pin.

UART0_nRTS

TM2_EXT

TM2

O

I

O

I

15

PWM1_BRAKE1

PB.3

PWM1 brake input pin.

I/O

I

General purpose digital I/O pin.

Clear to Send input pin for UART0.

Timer3 external capture input pin.

UART0_nCTS

TM3_EXT

I

16

TM3

O

Timer3 toggle output pin.

PWM1_BRAKE0

PD.6

I

PWM1 brake input pin.

I/O

I

General purpose digital I/O pin.

Data receiver input pin for CAN0.

General purpose digital I/O pin.

Data transmitter output pin for CAN0.

17

18

CAN0_RXD

PD.7

I/O

O

CAN0_TXD

PD.14

I/O

I

General purpose digital I/O pin.

19

UART2_RXD

Data receiver input pin for UART2.

PD.15

I/O

O

General purpose digital I/O pin.

Data transmitter output pin for UART2.

General purpose digital I/O pin.

SPI0 MOSI (Master Out, Slave In) pin.

General purpose digital I/O pin.

SPI0 MISO (Master In, Slave Out) pin.

General purpose digital I/O pin.

SPI0 serial clock pin.

20

21

22

23

UART2_TXD

PC.3

I/O

SPI0_MOSI0

PC.2

SPI0_MISO0

PC.1

SPI0_CLK

PC.0

General purpose digital I/O pin.

24

25

SPI0_SS0

I/O

SPI0 slave select pin.

PA.15

I/O

General purpose digital I/O pin.

PWM0 CH3 output/Capture input.

General purpose digital I/O pin.

PWM0 CH2 output/Capture input.

General purpose digital I/O pin.

PWM0_CH3

PA.14

26

27

PWM0_CH2

PA.13

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Pin No.

Pin Name

Pin Type

Description

LQFP

48-pin

PWM0_CH1

PA.12

I/O

PWM0 CH1 output/Capture input.

General purpose digital I/O pin.

PWM0 CH0 output/Capture input.

General purpose digital I/O pin.

Serial wire debugger data pin.

28

29

PWM0_CH0

PF.7

ICE_DAT

PF.6

I/O

I

Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin.

General purpose digital I/O pin.

30

31

Serial wire debugger clock pin.

ICE_CLK

Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin.

AV_SS

AP

I/O

AI

Ground pin for analog circuit.

General purpose digital I/O pin.

ADC_CH0 analog input.

PA.0

32

33

ADC_CH0

PWM0_CH4

PA.1

I/O

AI

PWM0 CH4 output/Capture input.

General purpose digital I/O pin.

ADC_CH1 analog input.

ADC_CH1

PWM0_CH5

PA.2

I/O

AI

PWM0 CH5 output/Capture input.

General purpose digital I/O pin.

ADC_CH2 analog input.

ADC_CH2

PWM1_CH0

UART3_TXD

PA.3

34

35

I/O

O

PWM1 CH0 output/Capture input.

Data transmitter output pin for UART3.

General purpose digital I/O pin.

ADC_CH3 analog input.

I/O

AI

ADC_CH3

PWM1_CH1

UART3_RXD

PA.4

I/O

I

PWM1 CH1 output/Capture input.

Data receiver input pin for UART3.

General purpose digital I/O pin.

ADC_CH4 analog input.

I/O

AI

36

37

ADC_CH4

PA.5

I/O

AI

General purpose digital I/O pin.

ADC_CH5 analog input.

ADC_CH5

UART3_RXD

PA.6

I

Data receiver input pin for UART3.

General purpose digital I/O pin.

ADC_CH6 analog input.

I/O

AI

38

ADC_CH6

UART3_TXD

O

Data transmitter output pin for UART3.

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Pin No.

Pin Name

Pin Type

Description

LQFP

48-pin

PA.7

I/O

AI

AP

I/O

I

General purpose digital I/O pin.

ADC_CH7 analog input.

39

40

41

ADC_CH7

V_REF

Voltage reference input for ADC.

Power supply for internal analog circuit.

General purpose digital I/O pin.

I2C0 clock pin.

AV_DD

PC.7

I2C0_SCL

PWM0_BRAKE1

PC.6

PWM0 brake input pin.

I/O

I

General purpose digital I/O pin.

I2C0 data input/output pin.

42

43

I2C0_SDA

PWM0_BRAKE0

PB.15

PWM0 brake input pin.

I/O

I

General purpose digital I/O pin.

External interrupt1 input pin.

Timer0 external capture input pin.

Timer0 toggle output pin.

INT1

TM0_EXT

TM0

I

O

PF.0

I/O

O

General purpose digital I/O pin.

External 4~24 MHz (high speed) crystal output pin.

General purpose digital I/O pin.

External 4~24 MHz (high speed) crystal input pin.

44

45

XT1_OUT

PF.1

I/O

I

XT1_IN

External reset input: active LOW, with an internal pull-up. Set this pin low reset

chip to initial state.

46

47

nRESET

I

Note: It is recommended to use 10 kΩ pull-up resistor and 10 μF capacitor on

nRESET pin.

PF.8

I/O

O

General purpose digital I/O pin.

Frequency divider clock output pin.

General purpose digital I/O pin.

ADC external trigger input.

CLKO

PB.8

I/O

I

STADC

TM0

48

I/O

O

Timer0 event counter input / toggle output.

Frequency divider clock output pin.

CLKO

Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power

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5

BLOCK DIAGRAM

5.1 NuMicro^®NUC1311 Block Diagram

Clock Control

High Speed

Timer

Analog Interface

12-bit ADC 8-ch

Watchdog Timer

PLL

Oscillator

ARM

22.1184 MHz

Cortex®-M0

16-bit PWM x 12

32-bit Timer x 4

High Speed

50 MHz

Low Speed

Oscillator

10 kHz

External

Crystal

4~24 MHz

AHB Bus

Bridge

APB Bus

Memory

Power Control

GPIO

Connectivity

UART x 4

APROM 68/36 KB

LDO

V_REF

LVR

General Purpose

I/O

1.8 V

LDROM 4 KB

SPI x 1

I²C x 1

Power On Reset

Configurable

Data Flash

External

Interrupt

Brown-out Detection

SRAM 8 KB

CAN x 1

Figure 5.1-1 NuMicro^®NUC1311 Block Diagram

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6

FUNCTIONAL DESCRIPTION

6.1 Arm^®Cortex^®-M0 Core

The Cortex^®-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA

AHB-Lite interface and includes an NVIC component. It also has optional hardware debug

functionality. The processor can execute Thumb code and is compatible with other Cortex^®-M profile

processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is

entered as a result of an exception. An exception return can only be issued in Handler mode. Thread

mode is entered on Reset, and can be entered as a result of an exception return.

Figure 6.1-1 shows the functional controller of processor.

Cortex^®-M0 Components

Cortex^®-M0 processor

Debug

Nested

Vectored

Interrupt

Controller

(NVIC)

Interrupts

Breakpoint

and

Watchpoint

Unit

Cortex^®-M0

Processor

Core

Debug

Access

Port

Wakeup

Interrupt

Controller

(WIC)

Debugger

Interface

Bus Matrix

(DAP)

AHB-Lite

Interface

Serial Wire or

JTAG Debug Port

Figure 6.1-1 Functional Controller Diagram

The implemented device provides the following components and features:

A low gate count processor:



-

Armv6-M Thumb^®instruction set

Thumb-2 technology

Armv6-M compliant 24-bit SysTick timer

A 32-bit hardware multiplier

System interface supported with little-endian data accesses

Ability to have deterministic, fixed-latency, interrupt handling

Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to

facilitate rapid interrupt handling

-

C Application Binary Interface compliant exception model. This is the Armv6-M, C

Application Binary Interface (C-ABI) compliant exception model that enables the use of

pure C functions as interrupt handlers

-

Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE)

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instructions, or the return from interrupt sleep-on-exit feature

NVIC:



-

32 external interrupt inputs, each with four levels of priority

Dedicated Non-maskable Interrupt (NMI) input

Supports for both level-sensitive and pulse-sensitive interrupt lines

Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode

Debug support

-

Four hardware breakpoints

Two watchpoints

Program Counter Sampling Register (PCSR) for non-intrusive code profiling

Single step and vector catch capabilities

Bus interfaces:

-

Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all

system peripherals and memory

-

Single 32-bit slave port that supports the DAP (Debug Access Port)

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6.2 System Manager

6.2.1 Overview

System management includes the following sections:



System Resets

System Memory Map

System management registers for Part Number ID, chip reset and on-chip controllers reset ,

multi-functional pin control



System Timer (SysTick)

Nested Vectored Interrupt Controller (NVIC)

System Control registers

6.2.2 System Reset

The system reset can be issued by one of the following listed events. For these reset event flags can

be read by RSTSRC register.



Power-on Reset

Low level on the nRESET pin

Watchdog Time-out Reset

Low Voltage Reset

Brown-out Detector Reset

CPU Reset

System Reset

System Reset and Power-on Reset all reset the whole chip including all peripherals. The difference

between System Reset and Power-on Reset is external crystal circuit and BS (ISPCON[1]) bit. System

Reset does not reset external crystal circuit and BS (ISPCON[1]) bit, but Power-on Reset does.

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6.2.3 System Power Distribution

In this chip, the power distribution is divided into three segments.



Analog power from AV_DDand AV_SSprovides the power for analog components operation.

Digital power from V_DDand V_SSsupplies the power to the internal regulator which provides a

fixed 1.8 V power for digital operation and I/O pins.

The outputs of internal voltage regulators, LDO, require an external capacitor which should be located

close to the corresponding pin. Analog power (AV_DD) should be the same voltage level with the digital

power (V_DD). Figure 6.2-1 shows the NuMicro^®NUC1311 power distribution.

NUC1311 Power Distribution

AV_DD

AV_SS

12-bit

SAR-ADC

Brown-out

Detector

Low Voltage

Reset

Internal

22.1184 MHz & 10 kHz

Oscillator

FLASH

Digital Logic

LDO_CAP

1uF

1.8V

POR18

POR50

ULDO

PLL

LDO

IO cell

GPIO

Figure 6.2-1 NuMicro^®NUC1311 Power Distribution Diagram

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6.2.4 System Timer (SysTick)

The Cortex^®-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-

on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be

used as a Real Time Operating System (RTOS) tick timer or as a simple counter.

When system timer is enabled, it will count down from the value in the SysTick Current Value Register

(SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR)

on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to 0, the

COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.

The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0

before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than

an arbitrary value when it is enabled.

If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with this

value. This mechanism can be used to disable the feature independently from the timer enable bit.

For more detailed information, please refer to the “Arm^®Cortex^®-M0 Technical Reference Manual” and

“Arm^®v6-M Architecture Reference Manual”.

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6.2.5 Nested Vectored Interrupt Controller (NVIC)

The Cortex^®-M0 provides an interrupt controller as an integral part of the exception mode, named as

“Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel and

provides following features:



Nested and Vectored interrupt support

Automatic processor state saving and restoration

Reduced and deterministic interrupt latency

The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler

Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of

the interrupts and most of the system exceptions can be configured to different priority levels. When

an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s

priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will

override the current handler.

When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched

from a vector table in memory. There is no need to determine which interrupt is accepted and branch

to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC

will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the

stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the

normal execution. Thus it will take less and deterministic time to process the interrupt request.

The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the

overhead of states saving and restoration and therefore reduces delay time in switching to pending

ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of

concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to

execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the

higher one without delay penalty. Thus it advances the real-time capability.

For more detailed information, please refer to the “Arm^®Cortex^®-M0 Technical Reference Manual” and

“Arm^®v6-M Architecture Reference Manual”.

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6.2.5.1 Exception Model and System Interrupt Map

Table 6.2-1 lists the exception model supported by NuMicro^®NUC1311 series. Software can set four

levels of priority on some of these exceptions as well as on all interrupts. The highest user-

configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of

all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the

system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.

Exception Name

Reset

Vector Number

Priority

-3

1

NMI

2

-2

Hard Fault

Reserved

3

-1

4 ~ 10

Reserved

Configurable

Reserved

Configurable

SVCall

11

Reserved

12 ~ 13

PendSV

14

SysTick

15

16 ~ 47

Interrupt (IRQ0 ~ IRQ31)

Table 6.2-1 Exception Model

Interrupt Number

Vector

Number

Source

Module

Interrupt Name

Interrupt Description

(Bit In Interrupt

Registers)

1 ~ 15

16

-

0

-

System exceptions

BOD_INT

WDT_INT

-

Brown-out Brown-out low voltage detected interrupt

17

1

WDT

-

Watchdog Timer interrupt

Reserved

18

-

19

3

EINT1

GPIO

-

External signal interrupt from PB.15 pin

External signal interrupt from PA[15:0]/PB[13:0]

External interrupt from PC[15:0]/PD[15:0]/PF[8:0]

Reserved

20

4

GPAB_INT

GPCDF_INT

-

21

5

22

6

23

7

-

Reserved

24

8

TMR0_INT

TMR1_INT

TMR2_INT

TMR3_INT

UART02_INT

UART1_INT

TMR0

TMR1

TMR2

TMR3

UART0/2

UART1

Timer 0 interrupt

25

9

Timer 1 interrupt

26

10

11

12

13

Timer 2 interrupt

27

Timer 3 interrupt

28

UART0 and UART2 interrupt

UART1 interrupt

29

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30

31

32

33

34

35

36

37

38

39

40

41

42

43

14

15

16

17

18

19

20

21

22

23

24

25

26

27

SPI0_INT

SPI0

SPI0 interrupt

UART3 interrupt

Reserved

UART3_INT

UART3

-

Reserved

I2C0_INT

I²C0

I²C0 interrupt

Reserved

-

CAN0_INT

CAN0

-

CAN0 interrupt

Reserved

-

PWM0_INT

PWM1_INT

-

PWM0

PWM1

-

PWM0 interrupt

PWM1 interrupt

Reserved

-

Reserved

BRAKE0_INT

BRAKE1_INT

PWM0

PWM1

PWM0 brake interrupt

PWM1 brake interrupt

Clock controller interrupt for chip wake-up from Power-

down state

44

28

PWRWU_INT

CLKC

45

46

47

29

30

31

ADC_INT

CKD_INT

-

ADC

CLKC

-

ADC interrupt

Clock detection interrupt

Reserved

Table 6.2-2 System Interrupt Map

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6.2.5.2 Vector Table

When an interrupt is accepted, the processor will automatically fetch the starting address of the

interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base

address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer

on reset, and the entry point addresses for all exception handlers. The vector number on previous

page defines the order of entries in the vector table associated with exception handler entry as

illustrated in previous section.

Vector Table Word Offset

Description

0

SP_main – The Main stack pointer

Exception Entry Pointer using that Vector Number

Table 6.2-3 Vector Table Format

Vector Number

6.2.5.3 Operation Description

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or

Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear

policy, both registers reading back the current enabled state of the corresponding interrupts. When an

interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the

interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until

cleared by reset or an exception return. Clearing the enable bit prevents new activations of the

associated interrupt.

NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to

enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register

respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading

back the current pended state of the corresponding interrupts. The Clear-Pending Register has no

effect on the execution status of an Active interrupt.

NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register

supporting four interrupts).

The general registers associated with the NVIC are all accessible from a block of memory in the

System Control Space and will be described in next section.

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6.2.6 System Control

The Cortex^®-M0 status and operating mode control are managed by System Control Registers.

Including CPUID, Cortex^®-M0 interrupt priority and Cortex^®-M0 power management can be controlled

through these system control registers.

For more detailed information, please refer to the “Arm^®Cortex^®-M0 Technical Reference Manual” and

“Arm^®v6-M Architecture Reference Manual”.

6.3 Clock Controller

6.3.1 Overview

The clock controller generates the clocks for the whole chip, including system clocks and all peripheral

clocks. The clock controller also implements the power control function with the individually clock

ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when

Cortex^®-M0 core executes the WFI instruction only if the PWR_DOWN_EN (PWRCON[7]) bit and

PD_WAIT_CPU (PWRCON[8]) bit are both set to 1. After that, chip enters Power-down mode and wait

for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock

controller turns off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high

speed RC oscillator to reduce the overall system power consumption. Figure 6.3-1 and Figure 6.3-2

show the clock generator and the overview of the clock source control.

The clock generator consists of 5 clock sources as listed below:



4~24 MHz external high speed crystal oscillator (HXT)

Programmable PLL output clock frequency(PLL FOUT),PLL source can be from 4~24 MHz

external high speed crystal oscillator (HXT) or 22.1184 MHz internal high speed RC oscillator

(HIRC))



22.1184 MHz internal high speed RC oscillator (HIRC)

10 kHz internal low speed RC oscillator (LIRC)

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XTL12M_EN (PWRCON[0])

HXT

XT1_OUT

XT1_IN

4~24 MHz

HXT

PLL_SRC (PLLCON[19])

PLL

0

1

PLL FOUT

OSC22M_EN (PWRCON[2])

22.1184 MHz

HIRC

LIRC

OSC10K_EN (PWRCON[3])

10 kHz

LIRC

Legend:

HXT = 4~24 MHz external high speed crystal oscillator

HIRC = 22.1184 MHz internal high speed RC oscillator

LIRC = 10 kHz internal low speed RC oscillator

Figure 6.3-1 Clock Generator Block Diagram

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22.1184

MHz

22.1184 MHz

10 kHz

111

011

010

001

000

CPUCLK

HCLK

CPU

ISP

4~24

MHz

PLLFOUT

Reserved

4~24 MHz

1/(HCLK_N+1)

10 kHz

PCLK

I2C 0

22.1184 MHz

10 kHz

111

101

011

010

001

000

CAN 0

CLKSEL0[2:0]

TMR 3

TMR 2

TMR 1

TMR 0

External trigger

HCLK

22.1184 MHz

4~24 MHz

1

PLLFOUT

Reserved

4~24 MHz

0

PLLCON[19]

22.1184 MHz

CLKSEL1[22:20]

CLKSEL1[18:16]

CLKSEL1[14:12]

CLKSEL1[10:8]

FMC

CPUCLK

22.1184 MHz

HCLK

1

0

1/2

111

011

010

001

000

SysTick

SYST_CSR[2]

4~24 MHz

Reserved

4~24 MHz

PWM 0

PWM 1

PCLK

1

PLLFOUT

0

CLKSEL0[5:3]

CLKSEL3[16]

CLKSEL3[17]

CLKSEL2[17:16]

10 kHz

11

10

WWDT

WDT

HCLK

1/2048

10 kHz

11

10

HCLK

1/2048

CLKSEL1[1:0]

22.1184 MHz

11

01

00

PLLFOUT

4~24 MHz

HCLK

1

0

SPI 0

PLLFOUT

CLKSEL1[25:24]

CLKSEL1[4]

1/(UART_N+1)

1/(ADC_N+1)

UART 0~3

22.1184 MHz

HCLK

11

10

01

00

ADC

BOD

PLLFOUT

4~24 MHz

22.1184 MHz

HCLK

10 kHz

11

10

01

00

FDIV

Reserved

4~24 MHz

CLKSEL1[3:2]

CLKSEL2[3:2]

Figure 6.3-2 Clock Generator Global View Diagram

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6.3.2 System Clock and SysTick Clock

The system clock has 4 clock sources which were generated from clock generator block. The clock

source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is shown in

Figure 6.3-3.

HCLK_S (CLKSEL0[2:0])

22.1184 MHz

111

10 kHz

011

010

001

000

CPUCLK

HCLK

CPU

AHB

APB

PLLFOUT

Reserved

4~24 MHz

1/(HCLK_N+1)

PCLK

HCLK_N (CLKDIV[3:0])

CPU in Power Down Mode

Figure 6.3-3 System Clock Block Diagram

The clock source of SysTick in Cortex^®-M0 core can use CPU clock or external clock (SYST_CSR[2]).

If using external clock, the SysTick clock (STCLK) has 4 clock sources. The clock source switch

depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block diagram is shown in

Figure 6.3-4.

STCLK_S (CLKSEL0[5:3])

22.1184 MHz

111

011

010

001

000

1/2

HCLK

STCLK

4~24 MHz

Reserved

4~24 MHz

Figure 6.3-4 SysTick Clock Control Block Diagram

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6.3.3 Power-down Mode Clock

When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks

will be disabled. Some clock sources and peripherals clocks are still active in Power-down mode.

The clocks still kept active are listed below:



Clock Generator

-

10 kHz internal low speed RC oscillator (LIRC) clock

WDT/Timer Peripherals Clock (when 10 kHz intertnal low speed RC oscillator (LIRC) is adopted

as clock source)

6.3.4 Frequency Divider Output

This device is equipped with a power-of-2 frequency divider which is composed by16 chained divide-

by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is

reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided clocks with the

frequency from F_in/2¹to F_in/2¹⁶where Fin is input clock frequency to the clock divider.

The output formula is F_out= F_in/2^(N+1), where F_inis the input clock frequency, F_outis the clock divider

output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).

When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0 to

DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low state

and stay in low state.

If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass power-of-

2 frequency divider. The frequency divider clock will be output to CLKO pin directly.

FRQDIV_S (CLKSEL2[3:2])

FDIV_EN (APBCLK[6])

22.1184 MHz

11

FRQDIV_CLK

HCLK

10

01

00

Reserved

4~24 MHz

Figure 6.3-5 Clock Source of Frequency Divider

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DIVIDER_EN

(FRQDIV[4])

Enable

divide-by-2 counter

FSEL

(FRQDIV[3:0])

16 chained

divide-by-2 counter

FRQDIV_CLK

DIVIDER1

(FRQDIV[5])

1/2

1/2²1/2³

…... 1/2¹⁵1/2¹⁶

0000

0001

16 to 1

MUX

:

CLKO

0

1

1110

1111

Figure 6.3-6 Frequency Divider Block Diagram

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6.4 Flash Memory Controller (FMC)

6.4.1 Overview

The NuMicro^®NUC1311 series has 68/36 KB on-chip embedded Flash for application program

memory (APROM) that can be updated through ISP procedure. The In-System-Programming (ISP)

function enables user to update program memory when chip is soldered on PCB. After chip is

powered on, Cortex^®-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in

CONFIG0. By the way, the NuMicro^®NUC1311 series also provides additional Data Flash for user to

store some application dependent data.

The NuMicro^®NUC1311 supports another flexible feature: configurable Data Flash size. The Data

Flash size is decided by Data Flash variable size enable (DFVSEN), Data Flash enable (DFEN) in

Config0 and Data Flash base address (DFBADR) in Config1. When DFVSEN is set to 1, the Data

Flash size is fixed at 4 KB and the address is started from 0x0001_F000, and the APROM size is

become 68/36 KB. When DFVSEN is set to 0 and DFEN is set to 1, the Data Flash size is zero and

the APROM size is 68/36 KB. When DFVSEN is set to 0 and DFEN is set to 0, the APROM and Data

Flash share 68/36 KB continuous address and the start address of Data Flash is defined by

(DFBADR) in Config1.

6.4.2 Features



Runs up to 50 MHz with zero wait cycle for continuous address read access

All embedded flash memory supports 512 bytes page erase

68/36 KB application program memory (APROM)

4 KB In-System-Programming (ISP) loader program memory (LDROM)

Configurable Data Flash size

512 bytes page erase unit

Supports In-Application-Programming (IAP) to switch code between APROM and LDROM

without reset



In-System-Programming (ISP) to update on-chip Flash

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6.5 General Purpose I/O (GPIO)

6.5.1 Overview

The NuMicro^®NUC1311 series has up to 42 General Purpose I/O pins to be shared with other

function pins depending on the chip configuration. These 42 pins are arranged in 5 ports named as

GPIOA, GPIOB, GPIOC, GPIOD and GPIOF. The GPIOA port has the maximum of 16 pins. The

GPIOB port has the maximum of 9 pins. The GPIOC port has the maximum of 6 pins. The GPIOD port

has the maximum of 4 pins. The GPIOF port has the maximum of 7 pins. Each of the 42 pins is

independent and has the corresponding register bits to control the pin mode function and data.

The I/O type of each of I/O pins can be configured by software individually as input, output, open-drain

or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on Config0[10] setting.

In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up resistor which is about 110~300

K for V_DDfrom 5.0 V to 2.5 V.

6.5.2 Features



Four I/O modes:

-

Quasi-bidirectional

Push-Pull output

Open-Drain output

Input only with high impendence



TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]

I/O pin configured as interrupt source with edge/level setting

Configurable default I/O mode of all pins after reset by Config0[10] setting

-

If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset

If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset



I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode

Enabling the pin interrupt function will also enable the pin wake-up function

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6.6 Timer Controller (TIMER)

6.6.1 Overview

The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily implement

a timer control for applications. The timer can perform functions, such as frequency measurement,

delay timing, clock generation, and event counting by external input pins, and interval measurement

by external capture pins.

6.6.2 Features



Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter

Independent clock source for each timer

Provides four timer counting modes: one-shot, periodic, toggle and continuous counting

Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)

Maximum counting cycle time = (1 / T MHz) * (2⁸) * (2²⁴), T is the period of timer clock

24-bit up counter value is readable through TDR (Timer Data Register)

Supports event counting function to count the event from external counter pin (TM0~TM3)

Supports external pin capture (TM0_EXT~TM3_EXT) for interval measurement

Supports external pin capture (TM0_EXT~TM3_EXT) for reset 24-bit up counter

Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated

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6.7 PWM Generator and Capture Timer (PWM)

6.7.1 Overview

The NUC1311 provides two PWM generators － PWM0 and PWM. Each PWM supports 6 channels of

PWM output or input capture. There is a 12-bit prescaler to support flexible clock to the 16-bit PWM

counter with 16-bit comparator. The PWM counter supports up, down and up-down counter types.

PWM uses the comparator compared with counter to generate events. These events are used to

generate PWM pulse, interrupt and trigger signal for ADC to start conversion.

The PWM generator supports two standard PWM output modes: Independent mode and

Complementary mode, which have difference architecture. In Complementary mode, there are two

comparators to generate various PWM pulse with 12-bit dead-time generator. For PWM output control

unit, it supports polarity output, independent pin mask, tri-state output enable and brake functions.

The PWM generator also supports input capture function to latch PWM counter value to the

corresponding register when input channel has a rising transition, falling transition or both transition is

happened.

6.7.2 Features

6.7.2.1 PWM function features



Supports maximum clock frequency up to 100 MHz

Supports up to two PWM modules, each module provides 6 output channels

Supports independent mode for PWM output/Capture input channel

Supports complementary mode for 3 complementary paired PWM output channel

-

Dead-time insertion with 12-bit resolution

Two compared values during one period



Supports 12-bit pre-scalar from 1 to 4096

Supports 16-bit resolution PWM counter, each module provides 3 PWM counters

-

Up, down and up/down counter operation type



Supports mask function and tri-state enable for each PWM pin

Supports brake function

-

Brake source from pin and system safety events (clock failed, Brown-out detection and

CPU lockup)

-

Noise filter for brake source from pin

Edge detect brake source to control brake state until brake interrupt cleared

Level detect brake source to auto recover function after brake condition removed



Supports interrupt on the following events:

-

PWM counter match zero, period value or compared value

Brake condition happened

Supports trigger ADC on the following events:

PWM counter match zero, period value or compared value

-

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6.7.2.2 Capture Function Features



Supports up to 12 capture input channels with 16-bit resolution

Supports rising or falling capture condition

Supports input rising/falling capture interrupt

Supports rising/falling capture with counter reload option

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6.8 Watchdog Timer (WDT)

6.8.1 Overview

The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown

state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer

supports the function to wake-up system from Idle/Power-down mode.

6.8.2 Features



18-bit free running up counter for Watchdog Timer time-out interval.

Selectable time-out interval (2⁴~ 2¹⁸) WDT_CLK cycle and the time-out interval period is 104 ms

~ 26.3168 s if WDT_CLK = 10 kHz.



System kept in reset state for a period of (1 / WDT_CLK) * 63

Supports Watchdog Timer reset delay period

-

Selectable it includes (1026, 130, 18 or 3) * WDT_CLK reset delay period.



Supports to force Watchdog Timer enabled after chip powered on or reset while CWDTEN

(CONFIG0[31] Watchdog Enable) bit is set to 0.

Supports Watchdog Timer time-out wake-up function only if WDT clock source is selected as 10

kHz

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6.9 Window Watchdog Timer (WWDT)

6.9.1 Overview

The Window Watchdog Timer is used to perform a system reset within a specified window period to

prevent software run to uncontrollable status by any unpredictable condition.

6.9.2 Features



6-bit down counter value (WWDTVAL[5:0]) and 6-bit compare window value (WWDTCR[21:16])

to make the WWDT time-out window period flexible

Supports 4-bit value to programmable maximum 11-bit prescale counter period of WWDT

counter

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6.10 UART Interface Controller (UART)

6.10.1 Overview

The NuMicro^®NUC1311 series provides up to

4

channels of Universal Asynchronous

Receiver/Transmitters (UART). UART0/UART1/UART2 supports 16 bytes entry FIFO and UART3

support 1 byte buffer for data payload. Besides, only UART0 and UART1 support the flow control

function. The UART Controller performs a serial-to-parallel conversion on data received from the

peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller

also supports IrDA SIR Function. UART0/UART1 provides RS-485 function mode.

UART0/UART1/UART2 provides LIN master/slave function.

6.10.2 Features



Full duplex, asynchronous communications

Separates receive / transmit 16/16 bytes (UART0/UART1/UART2 support) entry FIFO and 1/1

bytes buffer for data payloads (UART3 support)



Supports hardware auto-flow control function (CTS, RTS) and programmable RTS flow control

trigger level (UART0/UART1 support).



Programmable receiver buffer trigger level

Supports programmable baud-rate generator for each channel individually

Supports CTS wake-up function (UART0/UART1 support)

Supports 7-bit receiver buffer time-out detection function

Programmable transmitting data delay time between the last stop and the next start bit by setting

DLY (UA_TOR [15:8]) register



Supports break error, frame error, parity error and receive / transmit buffer overflow detect

function

Fully programmable serial-interface characteristics

-

Programmable data bit length, 5-, 6-, 7-, 8-bit character

Programmable parity bit, even, odd, no parity or stick parity bit generation and detection

Programmable stop bit length, 1, 1.5, or 2 stop bit generation



IrDA SIR function mode

Supports 3/16-bit duration for normal mode

LIN function mode (UART0/UART1/UART2 support)

-

Supports LIN master/slave mode

Supports programmable break generation function for transmitter

Supports break detect function for receiver



RS-485 function mode. (UART0/UART1 support)

-

Supports RS-485 9-bit mode

Supports hardware or software direct enable control provided by RTS pin

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6.11 I²C Serial Interface Controller (I²C)

6.11.1 Overview

I²C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange

between devices. The I²C standard is a true multi-master bus including collision detection and

arbitration that prevents data corruption if two or more masters attempt to control the bus

simultaneously.

6.11.2 Features

The I²C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices

connected to the bus. The main features of the I²C bus include:



Supports one I²C serial interface controller

Master/Slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of serial data on the

bus



Serial clock synchronization allow devices with different bit rates to communicate via one serial

bus

Built-in a 14-bit time-out counter requesting the I²C interrupt if the I²C bus hangs up and timer-out

counter overflows.



Programmable clocks allow for versatile rate control

Supports 7-bit addressing mode

Supports multiple address recognition ( four slave address with mask option)

Supports Power-down wake-up function

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6.12 Serial Peripheral Interface (SPI)

6.12.1 Overview

The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that

operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-direction

interface. The NuMicro^®NUC1311 series contains one set of SPI controllers performing a serial-to-

parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on

data transmitted to a peripheral device. This SPI controller can be configured as a master or a slave

device.

The SPI controller supports the variable bus clock function for special applications.

6.12.2 Features



One set of SPI controller

Supports Master or Slave mode operation

Supports Dual I/O Transfer mode

Configurable bit length of a transaction word from 8 to 32 bits

Provides separate 8-layer depth transmit and receive FIFO buffers

Supports MSB first or LSB first transfer sequence

Supports the Byte Reorder function

Supports Byte or Word Suspend mode

Variable output bus clock frequency in Master mode

Supports 3-wire, no slave select signal, bi-direction interface

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6.13 Controller Area Network (CAN)

6.13.1 Overview

The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and

Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0

part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the

physical layer, additional transceiver hardware is required.

For communication on a CAN network, individual Message Objects are configured. The Message

Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message

RAM. All functions concerning the handling of messages are implemented in the Message Handler.

These functions include acceptance filtering, the transfer of messages between the CAN Core and the

Message RAM, and the handling of transmission requests as well as the generation of the module

interrupt.

The register set of the C_CAN can be accessed directly by the software through the module interface.

These registers are used to control/configure the CAN Core and the Message Handler and to access

the Message RAM.

6.13.2 Features



Supports CAN protocol version 2.0 part A and B.

Bit rates up to 1 MBit/s.

32 Message Objects.

Each Message Object has its own identifier mask.

Programmable FIFO mode (concatenation of Message Objects).

Maskable interrupt.

Disabled Automatic Re-transmission mode for Time Triggered CAN applications.

Programmable loop-back mode for self-test operation.

16-bit module interfaces to the AMBA APB bus.

Supports wake-up function

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6.14 Analog-to-Digital Converter (ADC)

6.14.1 Overview

The NuMicro^®NUC1311 series contains one 12-bit successive approximation analog-to-digital

converters (SAR A/D converter) with 8 input channels. The A/D converter supports three operation

modes: single, single-cycle scan and continuous scan mode. The A/D converter can be started by

software, PWM, BPWM trigger and external STADC pin.

6.14.2 Features



Analog input voltage range: 0~V_REF

12-bit resolution and 10-bit accuracy is guaranteed

Up to 8 single-end analog input channels or 4 differential analog input channels

Up to 760 kSPS conversion rate (chip working at 5V)

Three operating modes

-

Single mode: A/D conversion is performed one time on a specified channel

Single-cycle scan mode: A/D conversion is performed one cycle on all specified channels

with the sequence from the smallest numbered channel to the largest numbered channel

-

Continuous scan mode: A/D converter continuously performs Single-cycle scan mode until

software stops A/D conversion



An A/D conversion can be started by:

-

Writing 1 to ADST bit (ADCR[11])through software

PWM trigger

External pin STADC



Conversion results are held in data registers for each channel with valid and overrun indicators

Supports two set digital comparators. The conversion result can be compared with specify value

and user can select whether to generate an interrupt when conversion result matches the

compare register setting



Channel 7 supports 2 input sources: external analog voltage, and internal Band-gap voltage

Apr. 07, 2020

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NUC1311

7

APPLICATION CIRCUIT

AVCC

ODB Port

CAN Transceiver

AV_DD

FB

CAN_TX

CAN_RX

D

R

CAN_H

CAN_L

DVCC

CAN

V_DD

Power

0.1 uF

V_SS

FB

DVCC

AV_SS

[3]

SPISS0

SPICLK0

MISO_0

CS

CLK

MISO

MOSI

V_DD

SPI Device

DVCC

100 k

V_SS

MOSI_0

[1]

100 k

V_DD

ICE_CLK

ICE_DAT

nRST

V_SS

SWD

Interface

DVCC

4.7 k

DVCC

4.7 k

NUC1311

Series

CLK

DIO

SCL

SDA

V_DD

I²C Device

20 p

XT1_IN

V_SS

Crystal

4~24 MHz

crystal

XT1_OUT

PC COM Port

RS232 Transceiver

ROUT RIN

RXD

TXD

UART

LDO

DVCC

TIN

TOUT

[2]

10 k

Reset Circuit

nRESET

LDO_CAP

10uF/25V

1 uF

Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin.

Note 2: It is recommended to use 10 kΩ pull-up resistor and 10 μF capacitor on nRESET pin.

Note 3: For the SPI device, the chip supply voltage must be equal to SPI device working voltage. For

example, when the SPI Flash working voltage is 3.3 V, the NUC1311 chip supply voltage must also be

3.3 V

Apr. 07, 2020

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8

ELECTRICAL CHARACTERISTICS

8.1 Absolute Maximum Ratings

SYMBOL

DC Power Supply

PARAMETER

MIN.

-0.3

V_SS-0.3

4

MAX

+7.0

V_DD+0.3

24

UNIT

V

V_DDV_SS

V_IN

Input Voltage

V

Oscillator Frequency

1/t_CLCL

T_A

MHz

C

Operating Temperature

-40

+105

+150

120

Storage Temperature

T_ST

-55

C

Maximum Current into V_DD

Maximum Current out of V_SS

Maximum Current sunk by a I/O pin

Maximum Current sourced by a I/O pin

Maximum Current sunk by total I/O pins

Maximum Current sourced by total I/O pins

-

mA

120

35

100

Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability

of the device.

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8.2 DC Electrical Characteristics

(V_DD-V_SS=5.5 V, T_A= 25C, F_OSC= 50 MHz unless otherwise specified.)

SPECIFICATION

PARAMETER

Operation Voltage

Power Ground

SYM.

TEST CONDITIONS

MIN.

TYP.

MAX. UNIT

V_DD

2.5

5.5

0.3

V

V_DD= 2.5V ~ 5.5V up to 50 MHz

V_SS

-0.3

0

AV_SS

LDO Output Voltage

Band-gap Voltage

V_LDO

1.62

1.8

1.98

V_DD≥ 2.5V

1.20

V

V_DD= 2.5 V ~ 5.5 V, T_A= 25C

V_BG

1.19

-0.3

1.22

+0.3

V_DD= 2.5 V ~ 5.5 V, T_A= -40C~105C

Allowed voltage

difference for V_DD

and AV_DD

V_DD

-

V

AV_DD

All digital

PLL

V_DD

HXT

HIRC

module

Operating Current

Normal Run Mode

at 50 MHz

I_DD1

18.2

mA

5.5V

12 MHz

X

V

X

V

X

V

X

V

X

V

I_DD2

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

11.4

16.6

9.9

mA

5.5V

3.3V

5.5V

3.3V

while(1){} executed

from flash

V_LDO=1.8 V

Operating Current

Normal Run Mode

at 22.1184 MHz

-

8.0

-

3.7

X

7.9

X

while(1){} executed

from flash

I_DD8

-

3.7

-

mA

3.3V

VLDO =1.8 V

X

V

X

V

X

V

X

V

X

V

X

Operating Current

Normal Run Mode

at 12 MHz

I_DD9

I_DD10

I_DD11

I_DD12

I_DD13

I_DD14

I_DD15

I_DD16

5.6

4.0

4.1

2.5

3.0

2.5

1.8

1.2

mA

5.5V

3.3V

5.5V

3.3V

12 MHz

4 MHz

while(1){} executed

from flash

V_LDO=1.8 V

Operating Current

Normal Run Mode

at 4 MHz

while(1){} executed

from flash

V_LDO=1.8 V

All digital

module

Operating Current

I_DD21

115

VDD

HXT

LIRC (kHz)

PLL

A

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SPECIFICATION

PARAMETER

SYM.

TEST CONDITIONS

MIN.

TYP.

MAX. UNIT

Normal Run Mode

at 10 kHz

5.5V

3.3V

X

10

X

V

X

V

X

I_DD22

I_DD23

I_DD24

114

102

101

A

while(1){} executed

from flash

VLDO =1.8 V

All digital

module

VDD

HXT

HIRC

PLL

I_IDLE1

25.9

mA

Operating Current

Idle Mode

5.5V

3.3V

5.5V

3.3V

5.5V

12 MHz

X

V

X

V

X

V

X

V

X

V

X

V

X

I_IDLE2

I_IDLE3

I_IDLE4

I_IDLE5

I_IDLE6

I_IDLE7

I_IDLE8

I_IDLE9

I_IDLE10

12.9

24.4

11.4

12.3

4.3

mA

at 50 MHz

VLDO =1.8 V

-

Operating Current

Idle Mode

X

at 22.1184 MHz

VLDO =1.8 V

12.2

4.3

X

7.5

12 MHz

Operating Current

Idle Mode

4.4

at 12 MHz

I_IDLE11

I_IDLE12

I_IDLE13

I_IDLE14

I_IDLE15

I_IDLE16

6.0

2.9

mA

3.3V

12 MHz

X

V

V_LDO=1.8 V

12 MHz

4 MHz

X

V

X

3.7

2.7

mA

5.5V

Operating Current

Idle Mode

at 4 MHz

2.4

1.4

mA

3.3V

4 MHz

X

V

X

V_LDO=1.8 V

4 MHz

X

All digital

module

V_DD

HXT

X

LIRC (kHz)

PLL

X

I_IDLE21

106

A

5.5V

10

V

X

V

X

Operating Current

Idle Mode

I_IDLE22

I_IDLE23

I_IDLE24

103

94

A

X

at 10 kHz

3.3V

X

92

X

RAM

retension

V_DD

HXT/HIRC LIRC (kHz)

PLL

Standby Current

Power-down Mode

(Deep Sleep Mode)

V_LDO=1.6 V

I_PWD1

-

15

-

A

5.5V

3.3V

X

10

X

V

I_PWD2

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NUC1311

SPECIFICATION

PARAMETER

SYM.

TEST CONDITIONS

MIN.

TYP.

MAX. UNIT

Input Current PA,

PB, PC, PD, PF

(Quasi-bidirectional

mode)

I_IN1

-67

-75

+1

V_DD= 5.5V, V_IN= 0V or V_IN=V_DD

A

V

Input Leakage

Current PA, PB, PC,

PD, PF

V_DD= 5.5V, 0<V_IN<V_DD

I_LK

-1

-

Open-drain or input only mode.

Logic 1 to 0

Transition Current

PA~PF (Quasi-

bidirectional mode)

[3]

I_TL

-610

-650

V_DD= 5.5V, V_IN=2.0V

Input Low Voltage

PA, PB, PC, PD, PF

(TTL input)

-0.3

-

0.8

0.6

V_DD= 4.5V

V_DD= 2.5V

V_IL1

V_IH1

V_IL3

V_IH3

V_DD

+0.2

2.0

1.5

-

V_DD= 5.5V

V_DD=3.0V

Input High Voltage

PA, PB, PC, PD, PF

(TTL input)

V

V_DD

+0.2

0

-

0.8

0.4

V_DD= 4.5V

V_DD= 3.0V

Input Low Voltage

XT1_IN^[*2]

V

V_DD

+0.3

3.5

2.4

-

V_DD= 5.5V

V_DD= 3.0V

Input High Voltage

XT1_IN^[*2]

V_DD

+0.3

Negative going

threshold

V_ILS

-0.3

-

0.2V_DD

V

(Schmitt input),

nRESET

Positive going

threshold

V_DD

+0.3

V_IHS

0.7 V_DD

(Schmitt input),

nRESET

Internal nRESET pin

pull up resistor

R_RST

40

150

kΩ

Negative going

threshold

0.3

VDD

V_ILS

-0.3

-

V

(Schmitt input),

Positive going

threshold

V_DD

+0.3

V_IHS

0.7 V_DD

V

(Schmitt input),

I_SR11

I_SR12

I_SR21

-300

-50

-40

-20

-400

-80

-73

-26

V_DD= 4.5V, V_S= 2.4V

V_DD= 2.7V, V_S= 2.2V

V_DD= 2.5V, V_S= 2.0V

A

Source Current PA,

PB, PC, PD, PF

(Quasi-bidirectional

Mode)

mA V_DD= 4.5V, V_S= 2.4V

Source Current PA,

Apr. 07, 2020

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NUC1311

SPECIFICATION

PARAMETER

SYM.

TEST CONDITIONS

MIN.

-3

TYP.

-5.2

-5

MAX. UNIT

PB, PC, PD, PF

(Push-pull Mode)

I_SR22

I_SK1

mA V_DD= 2.7V, V_S= 2.2V

-2.5

10

6

mA V_DD= 2.5V, V_S= 2.0V

mA V_DD= 4.5V, V_S= 0.45V

mA V_DD= 2.7V, V_S= 0.45V

mA V_DD= 2.5V, V_S= 0.45V

17

Sink Current PA, PB,

PC, PD, PF (Quasi-

bidirectional and

I_SK1

11

Push-pull Mode)

I_SK1

5

10

Note:

1. nRESET pin is a Schmitt trigger input.

2. Crystal Input is a CMOS input.

3. Pins of PA, PB, PC, PD and PF can source a transition current when they are being externally driven from 1 to 0. In the

condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.

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8.3 AC Electrical Characteristics

8.3.1 External 4~24 MHz High Speed Clock Input Signal Characteristics

For clock input mode, the HXT oscillator is enabled, XT1_IN is a standard input pin to receive external

clock and XT1_OUT is output pin to ouput inversed signal of XT1_IN. The external clock signal has to

respect the below Table. The characteristics result from tests performed using a wavefrom generator.

External

clock source

XT1_IN

t_CLCL

t_CLCH

90%

10%

0.7 V_DD

0.3 V_DD

t_CLCX

t_CHCL

t_CHCX

Note: Duty cycle is 50%.

SYMBOL

t_CHCX

PARAMETER

CONDITION

MIN.

TYP.

MAX.

UNIT

ns

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

10

2

-

t_CLCX

t_CLCH

t_CHCL

-

ns

15

ns

2

ns

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NUC1311

8.3.2 External 4~24 MHz High Speed Crystal

The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator

oscillator. All the information given in this secion are based on characterization results obtained with

typical external components. In the application, the external components have to be placed as close

as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order

to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer

for more details on the resonator characteristics (frequency, package, accuracy).

SYMBOL

V_HXT

PARAMETER

Operation Voltage V_DD

Temperature

CONDITION

MIN.

2.5

-40

-

TYP..

MAX.

5.5

105

-

UNIT

V

-

T_A

-

C

12 MHz at V_DD= 5 V

12 MHz at V_DD= 3 V

External crystal

2

mA

MHz

I_HXT

Operating Current

Clock Frequency

-

0.8

-

f_HXT

4

24

Notes:

1. Safety factor (S_f) must be higher than 10 for HXT to determine the oscillator safe operation during the application life.

If Safety factor isn’t enough, the HXT gain need be changed to higher driving level.

ꢃꢄ

ꢐꢂꢄ

ꢑ

ꢁꢂ^ꢄ

ꢎꢏꢏꢂ

ꢁꢂ

ꢀ

ꢅꢆꢇꢈꢉꢊꢋꢂꢌꢍꢄ

ꢄ

ꢑ

R_ADD: The value of smallest series resistance preventing the oscillator from starting up successfully. This resistance is

only used to measure Safety factor (S_f) of crystal in engineer stage, not for mass produciton.

R_S: Equivalent series resisotr(ESR) of crystal.

XT1_OUT

XT1_IN

R_ADD

C2

C1

Apr. 07, 2020

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NUC1311

8.3.2.1 Typical Crystal Application Circuits

CRYSTAL

C1

C2

R

4 MHz ~ 24 MHz

10~20 pF

without

XT1_OUT

XT1_IN

R

C1

C2

Figure 8.3-1 Typical Crystal Application Circuit

Apr. 07, 2020

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NUC1311

8.3.3 Internal 22.1184 MHz High Speed Oscillator

SYMBOL

PARAMETER

Operation Voltage V_DD

CONDITION

MIN.

2.5

-

TYP.

MAX.

5.5

-

UNIT

V

V_HRC

-

Center Frequency

-

22.1184

-

MHz

%

+25°C; V_DD= 5 V

-1

+1

f_HRC

Calibrated Internal Oscillator Frequency

Operation Current

-40°C ~ +105°C;

-2

-

+2

-

%

V_DD= 2.5 V ~ 5.5 V

I_HRC

V_DD= 5 V

744

μA

HIRC oscillator accuracy vs. temperature

0.40

0.20

0.00

-0.20

-0.40

-0.60

-0.80

-1.00

-1.20

-1.40

-1.60

-1.80

Min

Max

-40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100110

Temperature(℃)

Figure 8.3-2 HIRC Accuracy vs. Temperature

Apr. 07, 2020

Page 56 of 67

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NUC1311

8.3.4 Internal 10 kHz Low Speed Oscillator

SYMBOL

PARAMETER

Operation Voltage V_DD

Center Frequency

CONDITION

MIN.

2.5

-

TYP.

MAX.

5.5

-

UNIT

V

V_LRC

f_LRC

-

10

-

kHz

%

+25°C; V_DD=5 V

-10

+10

Calibrated Internal

Oscillator Frequency

-

-40°C ~ +105°C;

-50

-

+50

%

V_DD= 2.5 V ~ 5.5 V

Apr. 07, 2020

Page 57 of 67

Rev 1.00

NUC1311

8.4 Analog Characteristics

8.4.1 12-bit SARADC Specification

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Bit

-

Resolution

-

12

DNL

INL

E_O

Differential nonlinearity error

Integral nonlinearity error

Offset error

-1~2

-1~4

LSB

-

±2

±4

-

3

E_G

Gain error (Transfer gain)

Absolute Error

-3

-

E_A

4

-

LSB

-

Monotonic

Guaranteed

F_ADC

F_S

ADC clock frequency (AV_DD= 4.5V~5.5V)

-

16

MHz

kSPS

1/F_ADC

Sample rate (F_ADC/T_CONV

)

760

T_ACQ

T_CONV

Acquisition Time (Sample Stage)

Total Conversion Time

2~9

16~23

V_DDA

Supply Current

3

0

-

5.5

V

I_DDA

V_IN

C_IN

R_IN

Supply current (Avg.)

Input voltage

2.9

-

mA

V

AV_DD

Input Capacitance

Input Load

6

pF

kΩ

6.5

Apr. 07, 2020

Page 58 of 67

Rev 1.00

NUC1311

E_F(Full scale error) = E_O+ E_G

Gain Error Offset Error

E_GE_O

4095

4094

4093

4092

Ideal transfer curve

7

6

5

4

3

2

1

ADC

output

code

Actual transfer curve

DNL

1 LSB

4095

Analog input voltage

(LSB)

Offset Error

E_O

8.4.2 LDO and Power Management Specification

SYMBOL

PARAMETER

Input Voltage V_DD

Output Voltage

MIN.

2.5

TYP.

MAX.

5.5

UNIT

V

NOTE

V_DD

V_DDinput voltage

V_DD> 2.5 V

V_LDO

1.62

-40

1.8

25

1.98

105

V

T_A

Operating Temperature

C

Note:

1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.

2. For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin and the closest VSS pin of the

device..

Apr. 07, 2020

Page 59 of 67

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NUC1311

8.4.3 Low Voltage Reset Specification

SYMBOL

PARAMETER

Operation Voltage

Quiescent Current

Operation Temperature

CONDITION

-

MIN.

0

TYP.

-

MAX.

5.5

UNIT

V

AV_DD

T_A

AV_DD=5.5 V

-

1

5

A

C

V

I_LVR

-40

2.00

1.95

2.04

25

105

2.4

2.0

1.98

2.13

TA = 25 C

TA = -40 C

TA = 105 C

V_LVR

Threshold Voltage

2.02

2.25

V

8.4.4 Brown-out Detector Specification

SYMBOL

PARAMETER

Operation Voltage

Temperature

CONDITION

-

MIN.

0

TYP.

-

MAX.

5.5

UNIT

V

AV_DD

T_A

-

-40

25

105

140

4.56

3.84

2.85

2.28

4.41

3.71

2.7

C

μA

V

I_BOD

Quiescent Current

AVDD=5.5 V

-

BOD_VL[1:0]=11

BOD_VL [1:0]=10

BOD_VL [1:0]=01

BOD_VL [1:0]=00

BOD_VL[1:0]=11

BOD_VL [1:0]=10

BOD_VL [1:0]=01

BOD_VL [1:0]=00

4.45

3.74

2.73

2.22

4.34

3.65

2.66

2.16

4.53

3.8

Brown-out Voltage

(Rising edge)

V

V_BOD

2.77

2.25

4.39

3.69

2.69

2.19

V

Brown-out Voltage

(Falling edge)

V_BOD

V

2.2

V

8.4.5 Power-on Reset Specification

SYMBOL

PARAMETER

Operation Temperature

Reset Voltage

CONDITION

MIN.

-40

TYP.

25

MAX.

105

UNIT

C

T_A

-

V_POR

V+

1.6

2

2.4

V

V_DDStart Voltage to

Ensure Power-on Reset

V_POR

-

100

-

mV

V_DDRaising Rate to

Ensure Power-on Reset

RR_VDD

0.025

V/ms

Minimum Time for V_DD

Stays at V_PORto Ensure

Power-on Reset

t_POR

-

0.5

-

ms

Apr. 07, 2020

Page 60 of 67

Rev 1.00

NUC1311

V_DD

t_POR

RR_VDD

V_POR

Time

Figure 8.4-3 Power-up Ramp Condition

8.5 Flash DC Electrical Characteristics

SYMBOL

PARAMETER

Supply Voltage

CONDITIONS

MIN.

1.62

20000

10

TYP.

MAX.

UNIT

V^[2]

[1]

1.8

1.98

V_FLA

N_ENDUR

T_RET

Endurance

-

cycles^[2]

year

ms

Data Retention

Page Erase Time

Mass Erase Time

Program Time

At 85C

T_ERASE

20

T_MER

40

ms

T_PROG

Note:

40

μs

1. V_FLAis source from chip LDO output voltage

2. Number of program/erase cycles.

Apr. 07, 2020

Page 61 of 67

Rev 1.00

NUC1311

8.6 I²C Dynamic Characteristics

STANDARD MODE^[1][2]

FAST MODE^[1][2]

SYMBOL

PARAMETER

UNIT

MIN.

MAX.

MIN.

MAX.

t_LOW

SCL low period

μs

ns

μs

ns

pF

t_HIGH

t_{SU; STA}

t_{HD; STA}

t_{SU; STO}

t_BUF

SCL high period

Repeated START condition setup time

START condition hold time

STOP condition setup time

Bus free time

4

-

0.6

-

4

4.7^[3]

250

0^[4]

-

0.6

-

1.2^[3]

-

t_SU;DAT

t_HD;DAT

t_r

Data setup time

-

100

-

Data hold time

3.45^[5]

1000

300

400

0^[4]

0.8^[5]

300

400

SCL/SDA rise time

20+0.1Cb

t_f

SCL/SDA fall time

-

C_b

Capacitive load for each bus line

-

Note:

1. Guaranteed by design, not tested in production.

2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I²C frequency. It must be higher than 8 MHz to

achieve the maximum fast mode I²C frequency.

3. I²C controller must be retriggered immediately at slave mode after receiving STOP condition.

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of

the falling edge of SCL.

5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL

signal.

Repeated

START

STOP

START

STOP

SDA

SCL

t_BUF

t_LOW

t_r

t_f

t_HIGH

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_SU;DAT

Figure 8.6-1 I²C Timing Diagram

Apr. 07, 2020

Page 62 of 67

Rev 1.00

NUC1311

8.7 SPI Dynamic Characteristics

Symbol

Parameter

Min.

Typ.

Max.

Unit

SPI Master Mode (V_DD= 4.5 V ~ 5.5 V, 0 pF loading Capacitor)

t_DS

t_DH

t_V

Data setup time

0

4

-

ns

Data hold time

Data output valid time

1

2

SPI Master Mode (V_DD= 3.0 V ~ 3.6 V, 0 pF loading Capacitor)

t_DS

t_DH

t_V

Data setup time

0

4.5

-

ns

Data hold time

Data output valid time

2

4

SPI Slave Mode (V_DD= 4.5 V ~ 5.5 V, 0 pF loading Capacitor)

t_DS

t_DH

t_V

Data setup time

0

3.5

-

ns

Data hold time

Data output valid time

16

22

SPI Slave Mode (V_DD= 3.0 V ~ 3.6 V, 0 pF loading Capacitor)

t_DS

t_DH

t_V

Data setup time

0

4.5

-

ns

Data hold time

Data output valid time

18

24

CLKP=0

CLKP=1

SPICLK

t_V

Data Valid

MOSI

MISO

Data Valid

CLKP=0, TX_NEG=1, RX_NEG=0

or

CLKP=1, TX_NEG=0, RX_NEG=1

t_DS

t_DH

Data Valid

t_V

Data Valid

MOSI

MISO

CLKP=0, TX_NEG=0, RX_NEG=1

or

CLKP=1, TX_NEG=1, RX_NEG=0

t_DS

t_DH

Data Valid

Figure 8.7-1 SPI Master Mode Timing Diagram

Apr. 07, 2020

Page 63 of 67

Rev 1.00

NUC1311

CLKP=0

CLKP=1

SPICLK

t_DS

t_DH

Data Valid

MOSI

MISO

Data Valid

CLKP=0, TX_NEG=1, RX_NEG=0

or

CLKP=1, TX_NEG=0, RX_NEG=1

t_v

Data Valid

t_DS

t_DH

Data Valid

MOSI

MISO

CLKP=0, TX_NEG=0, RX_NEG=1

or

CLKP=1, TX_NEG=1, RX_NEG=0

t_v

Data Valid

Figure 8.7-2 SPI Slave Mode Timing Diagram

Apr. 07, 2020

Page 64 of 67

Rev 1.00

NUC1311

9

PACKAGE DIMENSIONS

9.1 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)

Apr. 07, 2020

Page 65 of 67

Rev 1.00

NUC1311

10 REVISION HISTORY

Date

Revision

Description

2020.04.07

1.00

Initial version

Apr. 07, 2020

Page 66 of 67

Rev 1.00

NUC1311

Important Notice

Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any

malfunction or failure of which may cause loss of human life, bodily injury or severe property

damage. Such applications are deemed, “Insecure Usage”.

Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic

energy control instruments, airplane or spaceship instruments, the control or operation of

dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all

types of safety devices, and other applications intended to support or sustain life.

All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay

claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the

damages and liabilities thus incurred by Nuvoton.

Apr. 07, 2020

Page 67 of 67

Rev 1.00


型号：	NUC1311-LD2AE
厂家：	NUVOTON
描述：	ArmÂ® CortexÂ®-M 32-bit Microcontroller 微控制器
文件：	总67页 (文件大小：1368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NUC1311-LD2AE [NUVOTON]

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