NUC472-KI8N [NUVOTON]
ARM® Cortex®-M4 32-bit Microcontroller;
| 型号： | NUC472-KI8N |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M4 32-bit Microcontroller 微控制器 |
| 文件： | 总228页 (文件大小：7150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC442
ARM® Cortex® -M4
32-bit Microcontroller
NuMicro® Family
NUC442 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
June 16, 2016
Page 1 of 228
Rev 1.09
NUC442
TABLE OF CONTENTS
1
2
3
4
GENERAL DESCRIPTION .............................................................. 9
1.1
2.1
3.1
NuMicro NUC442 General Description.................................................. 9
FEATURES .............................................................................. 10
NuMicro NUC442 Features – Connectivity Series ...................................10
ABBREVIATIONS....................................................................... 17
Abbreviations .................................................................................17
PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 19
NuMicro NUC442 Connectivity Series Selection Guide.............................19
Pin Configuration.............................................................................21
4.1
4.2
4.2.1
NuMicro NUC442 Pin Diagrams ...............................................................21
Pin Description ...............................................................................25
NuMicro NUC442 Package LQFP 64-pin Description ......................................25
NuMicro NUC442 Package LQFP 100-pin Description.....................................36
NuMicro NUC442 Package LQFP 128-pin Description.....................................56
NuMicro NUC442 Package LQFP 144-pin Description.....................................80
Summary GPIO Multi-function Pin Description ..............................................105
Summary Function Pin Description ............................................................ 111
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
5
6
BLOCK DIAGRAM .....................................................................133
FUNCTIONAL DESCRIPTION.......................................................134
ARM® Cortex® -M4 Core...................................................................134
System Manager...........................................................................137
6.1
6.2
6.2.1
6.2.2
Overview ........................................................................................... 137
System Reset...................................................................................... 137
System Power Distribution ......................................................................138
System Memory Map.............................................................................139
SRAM Memory Organization ...................................................................142
System Timer (SysTick) .........................................................................145
Nested Vectored Interrupt Controller (NVIC) .................................................145
Clock Controller ............................................................................152
Overview ........................................................................................... 152
System Clock and SysTick Clock .............................................................. 155
Clock Monitor...................................................................................... 155
Peripherals Clock .................................................................................157
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3
6.3.1
6.3.2
6.3.3
6.3.4
June 16, 2016
Page 2 of 228
Rev 1.09
NUC442
6.3.5
6.3.6
Power-down Mode Clock ........................................................................157
Frequency Divider Output .......................................................................157
Flash Memory Controller (FMC).........................................................159
Overview ........................................................................................... 159
Features............................................................................................ 159
External Bus Interface (EBI) .............................................................160
Overview ........................................................................................... 160
Features............................................................................................ 160
General Purpose I/O (GPIO).............................................................161
Overview ........................................................................................... 161
Features............................................................................................ 161
PDMA Controller (PDMA) ................................................................162
Overview ........................................................................................... 162
Features............................................................................................ 162
Timer Controller (TIMER).................................................................163
Overview ........................................................................................... 163
Features............................................................................................ 163
PWM Generator and Capture Timer (PWM) ..........................................164
Overview ........................................................................................... 164
Features............................................................................................ 164
Enhanced PWM Generator (EPWM) ...................................................165
Overview ........................................................................................ 165
Features ......................................................................................... 165
Enhanced Input Capture Timer..........................................................167
Overview ........................................................................................ 167
Features ......................................................................................... 167
Quadrature Encoder Interface (QEI)....................................................168
Overview ........................................................................................ 168
Features ......................................................................................... 168
Watchdog Timer (WDT)...................................................................169
Overview ........................................................................................ 169
Features ......................................................................................... 169
Window Watchdog Timer (WWDT) .....................................................170
Overview ........................................................................................ 170
Features ......................................................................................... 170
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.12
6.12.1
6.12.2
6.13
6.13.1
6.13.2
6.14
6.14.1
6.14.2
June 16, 2016
Page 3 of 228
Rev 1.09
NUC442
6.15
Real Time Clock (RTC) ...................................................................171
6.15.1
6.15.2
Overview ........................................................................................ 171
Features ......................................................................................... 171
UART Interface Controller (UART)......................................................172
Overview ........................................................................................ 172
Features ......................................................................................... 172
Smart Card Host Interface (SC) .........................................................174
Overview ........................................................................................ 174
Features ......................................................................................... 174
PS/2 Device Controller (PS2D)..........................................................175
Overview ........................................................................................ 175
Features ......................................................................................... 175
6.16
6.16.1
6.16.2
6.17
6.17.1
6.17.2
6.18
6.18.1
6.18.2
6.19
I2C Serial Interface Controller (Master/Slave) .........................................176
6.19.1
6.19.2
Overview ........................................................................................ 176
Features ......................................................................................... 177
Serial Peripheral Interface (SPI).........................................................178
Overview ........................................................................................ 178
Features ......................................................................................... 178
I2S Controller (I2S) .........................................................................179
Overview ........................................................................................ 179
Features ......................................................................................... 179
USB 2.0 Device Controller (USBD) .....................................................180
Overview ........................................................................................ 180
Features ......................................................................................... 180
USB 1.1 Host Controller (USBH)........................................................181
Overview ........................................................................................ 181
Features ......................................................................................... 181
USB OTG Controller.......................................................................182
Overview ........................................................................................ 182
Features ......................................................................................... 182
Controller Area Network (CAN)..........................................................183
Overview ........................................................................................ 183
Features ......................................................................................... 183
Secure Digital Host Controller ...........................................................184
Overview ........................................................................................ 184
6.20
6.20.1
6.20.2
6.21
6.21.1
6.21.2
6.22
6.22.1
6.22.2
6.23
6.23.1
6.23.2
6.24
6.24.1
6.24.2
6.25
6.25.1
6.25.2
6.26
6.26.1
June 16, 2016
Page 4 of 228
Rev 1.09
NUC442
6.26.2
Features ......................................................................................... 184
6.27
Cryptographic Accelerator................................................................185
Overview ........................................................................................ 185
Features ......................................................................................... 185
Image Capture Interface (ICAP).........................................................186
Overview ........................................................................................ 186
Features ......................................................................................... 186
CRC Controller .............................................................................187
Overview ........................................................................................ 187
Features ......................................................................................... 187
Analog-to-Digital Converter (ADC)......................................................188
Overview ........................................................................................ 188
Features ......................................................................................... 188
12-bit Analog-to-Digital Converter (Enhanced ADC).................................189
Overview ........................................................................................ 189
Features ......................................................................................... 189
Analog Comparator Controller (ACMP) ................................................191
Overview ........................................................................................ 191
Features ......................................................................................... 191
OP Amplifier ................................................................................192
Overview ........................................................................................ 192
Features ......................................................................................... 192
6.27.1
6.27.2
6.28
6.28.1
6.28.2
6.29
6.29.1
6.29.2
6.30
6.30.1
6.30.2
6.31
6.31.1
6.31.2
6.32
6.32.1
6.32.2
6.33
6.33.1
6.33.2
7
ELECTRICAL CHARACTERISTICS ................................................193
Absolute Maximum Ratings ..............................................................193
DC Electrical Characteristics.............................................................194
AC Electrical Characteristics.............................................................204
7.1
7.2
7.3
7.3.1
7.3.2
External Input Clock ..............................................................................204
External 4~24 MHz High Speed Crystal (HXT) ..............................................204
Typical Crystal Application Circuits ............................................................ 205
External 32 kHz Low Speed Crystal (LXT) ...................................................205
22.1184 MHz Internal High Speed RC Oscillator (HIRC) ..................................205
10 kHz Internal Low Speed RC Oscillator (LIRC) ...........................................206
Input/Output AC Characteristics................................................................ 206
Analog Characteristics ....................................................................207
12-bit SAR ADC...................................................................................207
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.4
7.4.1
June 16, 2016
Page 5 of 228
Rev 1.09
NUC442
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
LDO and Power Management ..................................................................209
Low Voltage Reset ...............................................................................209
Brown-out Detector...............................................................................210
Power-on Reset...................................................................................210
Temperature Sensor .............................................................................212
Comparator ........................................................................................ 212
OP Amplifier ....................................................................................... 212
Internal Voltage Reference......................................................................213
USB PHY Specification .......................................................................214
Flash DC Electrical Characteristics .....................................................216
I2C Dynamic Characteristics .............................................................217
SPI Dynamic Characteristics.............................................................218
I2S Dynamic Characteristics..............................................................220
7.5
7.6
7.7
7.8
8
9
PACKAGE DIMENSIONS ............................................................222
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) .........................................222
LQFP 100L (14x14x1.4 mm footprint 2.0 mm) ........................................223
LQFP 128L (14x14x1.4 mm footprint 2.0 mm) ........................................224
LQFP 144L (20x20x1.4 mm footprint 2.0 mm) ........................................225
REVISION HISTORY..................................................................227
8.1
8.2
8.3
8.4
June 16, 2016
Page 6 of 228
Rev 1.09
NUC442
List of Figure
Figure 4.1-1 NuMicro NUC442 Series Selection Code............................................................... 20
Figure 4.2-1 NuMicro NUC442Rxxxx LQFP 64-pin Diagram...................................................... 21
Figure 4.2-2 NuMicro NUC442Vxxxx LQFP 100-pin Diagram.................................................... 22
Figure 4.2-3 NuMicro NUC442Kxxxx LQFP 128-pin Diagram.................................................... 23
Figure 4.2-4 NuMicro NUC442Jxxxx LQFP 144-pin Diagram .................................................... 24
Figure 4.3-1 NuMicro NUC442 Series Block Diagram.............................................................. 133
Figure 6.1-1 Cortex® -M4 Block Diagram...................................................................................... 134
Figure 6.2-1 NuMicro NUC442 Power Distribution Diagram..................................................... 138
Figure 6.2-2 SRAM Block Diagram.............................................................................................. 142
Figure 6.2-3 SRAM Memory Organization................................................................................... 143
Figure 6.3-1 Clock Generator Block Diagram .............................................................................. 153
Figure 6.3-2 System Clock Block Diagram .................................................................................. 155
Figure 6.3-3 System Clock Switch Procedure ............................................................................. 156
Figure 6.3-4 SysTick Clock Control Block Diagram..................................................................... 156
Figure 6.3-5 Clock Source of Frequency Divider......................................................................... 157
Figure 6.3-6 Block Diagram of Frequency Divider ....................................................................... 158
Figure 6.10-1 PWM Block Diagram.............................................................................................. 166
Figure 6.19-1 I2C Bus Timing....................................................................................................... 176
Figure 7.3-1 NUC442 Typical Crystal Application Circuit ............................................................ 205
Figure 7.4-1 Power-up Ramp Condition ...................................................................................... 211
Figure 7.6-1 I2C Timing Diagram ................................................................................................. 217
Figure 7.7-1 SPI Master Mode Timing Diagram .......................................................................... 218
Figure 7.7-2 SPI Slave Mode Timing Diagram ............................................................................ 219
Figure 7.8-1 I2S Master Mode Timing Diagram............................................................................ 221
Figure 7.8-2 I2S Slave Mode Timing Diagram.............................................................................. 221
June 16, 2016
Page 7 of 228
Rev 1.09
NUC442
List of Tables
Table 1.1-1 Key Features Support Table......................................................................................... 9
Table 3.1-1 List of Abbreviations.................................................................................................... 18
Table 6.2-1 Address Space Assignments for On-Chip Controllers.............................................. 141
Table 6.2-2 Exception Model ....................................................................................................... 146
Table 6.2-3 Interrupt Number Table............................................................................................. 150
June 16, 2016
Page 8 of 228
Rev 1.09
NUC442
1
GENERAL DESCRIPTION
1.1 NuMicro NUC442 General Description
The NuMicro NUC442 Connectivity series with embedded Cortex® -M4F core with DSP
extensions and a Floating Point Unit runs up to 84 MHz with 256/512 Kbytes embedded flash
memories and 64K-byte embedded SRAM. It is also equipped with plenty of peripheral devices,
such as Timers, Watchdog Timers, RTC, PDMA, EBI, UART, Smart Card interface, SD HOST,
SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2, 12-bit ADC, analog comparator, operational
amplifier, temperature sensor, Low Voltage Reset Controller and Brown-out Detector. The
NUC442 also provides USB 2.0 full-speed Device/Host/OTG, USB 2.0 HS device and security
functions such as tamper detection, symmetric cryptographic accelerator and secure Hash
function accelerator.
Smart
Card
Interface
Product
Series
Ethernet
USB
CAN
SD Host
UART
SPI
I2C
Security
ADC
NUC442
●
●
●
●
●
●
●
●
●
Table 1.1-1 Key Features Support Table
The NuMicro NUC442 series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation
Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
System Supervisors
USB Accessories
Smart Card Reader
Printer
POS
Motor Control
June 16, 2016
Page 9 of 228
Rev 1.09
NUC442
2
FEATURES
2.1 NuMicro NUC442 Features – Connectivity Series
Core
–
–
ARM® Cortex® -M4 core running up to 84 MHz
Supports DSP extension
Supports hardware divider
–
–
–
–
Supports IEEE 754 compliant Floating-point Unit (FPU)
Supports Memory Protection Unit (MPU)
One 24-bit system timer
Supports low power sleep mode
Supports both WFI and WFE instructions
–
–
Single-cycle 32-bit hardware multiplier
Supports Nested Vectored Interrupt Controller (NVIC)
Supports programmable 256 level priorities for interrupts
–
Supports programmable maskable interrupts
Build-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
–
–
–
–
–
–
–
256/512 Kbytes Flash memory
Configurable program code/data allocation
ISP loader sizes 16 Kbytes
Supports 2-wired ICP update through SWD/ICE interface
Supports In-system program (ISP), In application program (IAP) update
2 Kbytes page erase for flash
Supports fast parallel programming mode by external programmer
SRAM
–
–
–
–
–
64 Kbytes embedded SRAM
24 Kbytes SRAM with hardware parity check
Supports byte-, half-word- and word-access parity check
Supports exception (NMI) generated once a parity check error occurs
Supports PDMA mode
Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed RC oscillator for system operation (variation < 2% at
-40℃ ~ +105℃)
–
–
Built-in 10 kHz low speed RC oscillator for Watchdog Timer and Wake-up operation
Built-in 4~24 MHz high speed oscillator for external crystal input for precise timing
operation
–
–
Built-in 32.768 kHz low speed oscillator for external crystal input for RTC function and
low power system operation
Supports one PLL, up to 84 MHz for high performance system operation, sourced from
Built-in 22.1184 MHz high speed RC oscillator
4~24 MHz external high speed crystal oscillator
–
–
–
–
–
Supports clock failure detection for system clock
Supports exception (NMI) generated once a clock failure detected
Flexible selection for different applications
Supports clock out
CPU clock source can be selected from USB PHY Embedded PLL
EBI
–
Supports accessible space up to 256MB configured into 4 memory blocks
(64MB/Memory Block), the actually external addressable space is dependent on
June 16, 2016
Page 10 of 228
Rev 1.09
NUC442
package pin out
–
–
–
–
–
–
–
Dedicated external chip select pin for each memory block
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports PDMA mode
Supports Address/Data Separated/Multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
Supports “Timing Transparent Encrypt/Decrypt” for protecting data in each memory
block (Individual Enable/Disable)
GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
–
–
–
–
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
High driver and high sink IO mode support (To source 20mA and sink 15mA at 5V)
Supports up to 114/101/77/45 GPIOs for LQFP144/128/100/64, respectively.
PDMA (Peripheral DMA)
–
Supports 16 independent configurable channels for automatic data transfer between
memories and peripherals
–
–
–
–
–
–
Supports normal and Scatter-Gather Transfer modes
Supports 2 types of priorities modes: fixed-priority and round-robin modes
Supports byte-, half-word- and word-access
Auto increment the source and destination address
Supports 16-level FIFO
Supports bus abort status flag
Timer
–
–
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
PWM
–
–
–
–
–
–
–
–
–
–
Supports up to two 6-channel PWM outputs with 16-bit resolution
Supports 8-bit presale and clock divider
Supports period point, center point and edge point PWM Interrupt
Supports One-shot or Auto-reload PWM counter operation mode
Supports Edge-aligned or Center-aligned PWM counter type
Supports 8-bit dead zone with maximum divided 8 pre-scale
Supports brake function source from pin or comparator output
Supports mask function for each PWM pin
Supports independent, complementary, synchronized and group PWM output mode
Supports trigger ADC start conversion at PWM counter period point, PWM counter
center point, PWM output rising edge and PWM output falling edge
Supports 12 Capture input channels with 16-bit resolution
Supports rising or falling capture condition
–
–
–
Supports capture interrupt
EPWM (Enhanced PWM)
–
–
Supports up to two EPWM
Each EPWM has
June 16, 2016
Page 11 of 228
Rev 1.09
NUC442
Three independent 16-bit PWM duty control units with maximum 6 port pins
Group control bit: PWM2 and PWM4 are synchronized with PWM0
Supports Edge-aligned mode and Center-aligned mode
Programmable dead-time insertion between complementary paired PWMs
Each pin of from PWM0 to PWM5 has independent polarity setting control
Mask output control for Electrically Commutated Motor operation
Tri-state output at reset and brake state
Hardware brake protections
Two Interrupt Sources
PWM signals before polarity control stage are defined in view of positive logic.
The PWM ports active high or active low are controlled by polarity control
register.
High Source/Sink current
Enhanced Input Capture Timer
–
Supports up to two Input Capture Timer/Counter Units, Input Capture 0 and Input
Capture 1
–
–
–
–
Each unit has own interrupt vector
24-bit Input Capture up-counting timer/counter
With noise filter in front end of input ports
Edge detector with three options
Rising edge detection
Falling edge detection
Both edge detection
–
–
–
Each input channel is supported with one capture counter hold register
Captured event reset/reload capture counter option
Supports compare-match function
Quadrature Encoder Interface (QEI)
–
–
Supports up to two QEI controllers, QEI0 and QEI1
Each QEI has
Two QEI phase inputs, QEA and QEB; One Index input
One QEI control register (QEI_CTR) and one QEI Status Register (QEI_STS)
Four Quadrature encoder pulse counter operation modes
Watchdog Timer
–
–
–
–
Supports multiple clock sources
8 selectable time out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
–
–
Supports multiple clock sources
Window set by 6-bit counter with 11-bit pre-scale
Interrupt or reset selectable on time-out
RTC
–
–
–
–
–
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
–
–
Supports wake-up function
Supports 96 bytes backup registers
Programmable backup-register erase function
June 16, 2016
Page 12 of 228
Rev 1.09
NUC442
–
–
Supports external power input pin (VBAT
Supports tamper detection function
)
Tamper Detection
–
–
Supports external tamper detection up to 2 input pins
Reset, NMI or Interrupt generated once tamper detected
UART
–
–
–
–
–
–
–
–
Supports up to six UART controllers
Supports flow control (CTS and RTS)
UART0 with 64-byte FIFO is for high speed
UART1~5 with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
Smart Card Interface
–
–
–
–
–
–
–
Supports up to six ISO-7816-3 ports
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
A 24-bit and two 8 bit time out counter for Answer to Request (ATR) and waiting times
processing
–
–
–
–
–
–
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation/deactivation sequence process
Supports hardware warm reset sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART function
PS/2 Device Controller
–
–
–
–
–
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
I2C
–
–
–
–
–
Supports up to five sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
–
–
–
–
–
Programmable clocks allowing versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports speed up to 1Mbps
Supports PDMA mode
Supports multi-address wake-up function
SPI
June 16, 2016
Page 13 of 228
Rev 1.09
NUC442
–
–
–
–
–
–
–
–
–
–
–
–
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports byte reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Master up to 32 MHz, and Slave up to 16 MHz (chip working at 5V)
I2S
–
–
–
–
–
–
–
Supports up to two I2S interface
Interface with external audio CODEC
Supports Master and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I2S and MSB justified data format
Each provides two 8-word FIFO data buffers, one for transmitting and the other for
receiving
–
–
Generates interrupt requests when buffer levels cross a programmable boundary
Each supports two PDMA requests, one for transmitting and the other for receiving
USB 2.0 Controller
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Supports one set of USB 2.0 FS Device/Host/OTG or USB 2.0 HS Device
Supports one set of USB 2.0 FS Host
FS Host compatible with Open HCI 1.0 specification
Compliant to USB specification version 2.0
OTG supports USB OTG Supplement 1.3
On-chip USB Transceiver
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 12 programmable endpoints and one dedicated control end point
Supports 4095 bytes internal SRAM as USB buffer
Provides remote wake-up capability
On-chip 5V to 3.3V LDO for USB PHY
On-chip PLL able to support 480 MHz clock
Supports DMA master
CAN 2.0
–
–
–
–
–
–
–
–
–
Supports up to two CAN controllers
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
Each supports 32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Object)
Supports interrupts
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Supports power-down wake-up function
SD Host Interface
–
–
–
–
Supports SD (Secure Digital) card and SD HOST interface
Compliant with SD Memory Card Specification Version 2.0
Supports 1 and 4-bit modes
Supports 25 MHz to achieve 100 Mbps at 3.3V operation
June 16, 2016
Page 14 of 228
Rev 1.09
NUC442
–
Supports DMA master
Cryptographic Accelerator
–
DES/TDES accelerator
Supports hardware DES (Data Encryption Standard)/TDES (Triple DES)
accelerator
Supports 56, 112 and 168-bit keys
Supports ECB, CBC, CFB, OFB and CTR modes
Compliant with NIST 800 38A
–
–
AES accelerator
Supports hardware AES (Advanced Encryption Standard) accelerator
Supports 128-, 192- and 256-bit keys
Supports ECB, CBC, CFB, OFB and CTR modes
Compliant with NIST 800 38A
Secure Hash Function accelerator
Supports hardware SHA (Secure Hash) accelerator
Supports SHA-1 and SHA-224, -256
Compliant with FIPS 180-2
Random Number Generator
–
–
Supports random bit generator
Supports a random number generator programmable 64, 128, 192 and 256 bits
Image Capture Interface
–
–
–
–
CCIR601 & CCIR656 interfaces supported for connection to CMOS image sensor
Resolution up to 3M pixel
YUV422 and RGB565 color format supported for data-in from CMOS sensor
YUV422, RGB565, RGB555 and Y-only color format supported for data storing to
system memory
–
–
–
–
–
–
–
–
–
Planar and packet data format supported for data storing to system memory
Image cropping supported with the cropping window up to 4096x2048
Image scaling-down supported
Vertical and horizontal scaling-down for preview mode supported
Scaling factor as N/M
Two pairs of configurable 8-bit N and 8-bit M for vertical and horizontal scaling-down
The value of N has to be equal to or less than M
Frame rate control supported
Combines two interlace fields to a single frame supported for data in from TV-decoder
Cyclic Redundancy Calculation Unit
–
–
–
–
–
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
Programmable initial value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
–
Interrupt generated once checksum error occurs
ADC
–
Supports two operating modes: ADC mode and EADC (Enhance ADC mode with dual
ADC Sampling)
–
Selected as ADC mode
Supports single 12-bit ADC conversion
Analog input voltage range: 0~AVDD
Up to 12 external single-ended analog input channels
Up to 6 differential analog input pairs
Supports single ADC interrupt
Supports easy control for power saving
June 16, 2016
Page 15 of 228
Rev 1.09
NUC442
External VREF pin can be used as input
Supports PDMA transfer
–
Selected as EADC mode
Supports two 12-bit ADC simultaneous conversion
Analog input voltage range: 0~ AVDD
Up to 16 external single-ended analog input channels
Each ADC can convert individually at normal operation
Four ADC interrupts with individual interrupt vector addresses
An A/D conversion source can be triggered by different events
Conversion results are held in 16 data registers with valid and overrun indicators
Sampling-oriented trigger setting and input setting for each sampling
Supports converting internal OP0, OP1 Amplifier output voltage
Supports converting internal band-gap voltage, internal temperature sensor
output and analog ground
Analog Comparator
–
–
–
–
Supports up to three rail-to-rail analog comparators
External input or internal Band-gap voltage selectable at negative node
Interrupts generated when compare results change
Supports power-down wake-up
Operational Amplifier
–
–
Supports up to two analog operational amplifiers
Outputs can be used as the input of ADC
Debug
–
Supports Flash Patch and Breakpoint Unit (FPB)
Supports 8 hardware breakpoints
Supports 6 watchpoints
–
Supports the following debug ports
2-pin Serial Wire Debug port (SWD)
Supports 96-bit Unique ID (UID)
Supports 128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
–
–
With 4 levels: 4.4 V/ 3.7 V/ 2.7 V/ 2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 2.0 V
Operating Temperature: -40℃~105℃
Packages
–
–
All Green package (RoHS)
LQFP 144-pin/ 128-pin/ 100-pin/ 64-pin
June 16, 2016
Page 16 of 228
Rev 1.09
NUC442
3
ABBREVIATIONS
3.1 Abbreviations
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
CAN
DAP
DES
EBI
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital
SD
June 16, 2016
Page 17 of 228
Rev 1.09
NUC442
SPI
Serial Peripheral Interface
Samples per Second
SPS
TDES
TMR
UART
UCID
USB
Triple Data Encryption Standard
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
June 16, 2016
Page 18 of 228
Rev 1.09
NUC442
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro NUC442 Connectivity Series Selection Guide
Connectivity
x2,
16-ch
NUC442JI8AE 512 64 16 114
NUC442JG8AE 256 64 16 114
NUC442KI8AE 512 64 16 100
NUC442KG8AE 256 64 16 100
NUC442VI8AE 512 64 16 77
NUC442VG8AE 256 64 16 77
NUC442RI8AE 512 64 16 45
NUC442RG8AE 256 64 16 45
4
4
4
4
4
4
4
4
6+6
6+6
6+6
6+6
6+5
6+5
4+3
4+3
4
4
4
4
4
4
3
3
5
5
5
5
5
5
2
2
v
v
v
v
v
v
v
v
6
6
6
6
6
6
4
4
2
2
2
2
2
2
2
2
6
6
6
6
5
5
3
3
2
2
2
2
2
2
1
1
--
--
--
--
--
--
--
--
16
16
16
16
16
16
8
3
3
3
3
3
3
2
2
2
2
2
v
v
v
v
v
v
v
v
6
6
6
6
5
5
3
3
v
v
v
v
v
v
v
v
LQFP144
LQFP144
LQFP128
LQFP128
LQFP100
LQFP100
LQFP64
x2,
16-ch
x2,
16-ch
x2,
16-ch
2
--
x2,
16-ch
--
x2,
16-ch
-- x2, 8-
ch
-- x2, 8-
ch
8
LQFP64
*Marked in this table (6+6) means 6 UART + 6 ISO-7816 UART
*ISO-7816 UART supports full duplex mode
June 16, 2016
Page 19 of 228
Rev 1.09
NUC442
Reserved or Memory size
4: Cortex-M4
N: - 40oC~ +85oC
E: - 40oC~+105oC
4: Connectivity Series
7: Advanced Series
8: 64 KB
R: LQFP 64 10x10mm
V: LQFP 100 14x14mm
K: LQFP 128 14x14mm
J: LQFP 144 20x20mm
H: LQFP 176 24x24mm
G: 256 KB
I : 512 KB
Figure 4.1-1 NuMicro NUC442 Series Selection Code
June 16, 2016
Page 20 of 228
Rev 1.09
NUC442
4.2 Pin Configuration
4.2.1 NuMicro NUC442 Pin Diagrams
4.2.1.1 NuMicro NUC442Rxxxx LQFP 64-pin
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
INT2/EBI_MCLK/UART4_RXD/SC1_DAT/I2S1_DI/PC.0
EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1
EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2
EBI_AD11/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3
EBI_AD10/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4
EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6
EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7
SPI0_CLK/TM0_EXT/PC.8
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
VSS
LDO_CAP
PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3
PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2
PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1
PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0
PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20
PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19
PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18
PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17
PA.6/SC2_CD/I2S0_LRCK/PWM0_1/CAN1_TXD/EBI_A16
PA.0/TAMPER0/SC0_CD/CAN1_RXD/INT0
VBAT
NUC442 LQFP 64
LDO_CAP
SPI0_SS0/ACMP0_P2/ADC0_4/PE.4
SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5
EBI_nWR/SD0_CMD/SPI0_MISO0/ACMP0_P0/ADC0_6/PE.6
EBI_nRD/SD0_CLK/SPI0_MOSI0/ACMP0_N/ADC0_7/PE.7
AVSS
VREF
AVDD
PG.14/X32K_OUT/I2C1_SDA
PG.15/X32K_IN/I2C1_SCL
Figure 4.2-1 NuMicro NUC442Rxxxx LQFP 64-pin Diagram
June 16, 2016
Page 21 of 228
Rev 1.09
NUC442
4.2.1.2 NuMicro NUC442Vxxxx LQFP 100-pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD
EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1
EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2
ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3
ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4
ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5
EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6
EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7
VSS
LDO_CAP
PC.11/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3
PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2
PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6
PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21
PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3
SPI0_CLK/TM0_EXT/PC.8
LDO_CAP
PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2
VSS
PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1
PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0
PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20
PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19
PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18
PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17
PA.6/SC2_CD/I2S0_LRCK/PWM0_1/QEI1_A/CAN1_TXD/EBI_A16/ECAP1_IC0
PA.5/SC2_RST/SPI3_SS0/I2S0_BCLK/PWM0_0/QEI1_B/EBI_A15/ECAP1_IC1
PA.4/SC2_PWR/SPI3_CLK/I2S0_DI/QEI1_Z/EBI_A14/ECAP1_IC2
PA.3/SC2_CLK/SPI3_MOSI0/I2S0_DO/BRAKE10/EBI_A13
PA.2/SC2_DAT/SPI3_MISO0/I2S0_MCLK/BRAKE11/CAP_SFIELD/EBI_A12
PA.1/TAMPER1/SC5_CD/CAN1_TXD/EBI_A22
INT4/ADC0_0/PE.0
TM2_CNT_OUT/ADC0_1/PE.1
SPI0_MISO0/ACMP0_O/ADC0_2/PE.2
NUC442 LQFP 100
SPI0_MOSI0/ACMP0_P3/ADC0_3/PE.3
SPI0_SS0/ACMP0_P2/ADC0_4/PE.4
SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5
EBI_nWR/SD0_CMD/SPI0_MISO0/ACMP0_P0/ADC0_6/PE.6
EBI_nRD/SD0_CLK/SPI0_MOSI0/ACMP0_N/ADC0_7/PE.7
AVSS
VREF
AVDD
EBI_ALE/SD0_DAT3/TM1_CNT_OUT/ACMP1_N/ADC0_8/ADC1_0/PE.8
EBI_nWRH/SD0_DAT2/ACMP1_P0/ADC0_9/ADC1_1/PE.9
EBI_nWRL/SD0_DAT1/SPI0_MISO1/ACMP1_P1/ADC0_10/ADC1_2/PE.10
EBI_nCS0/ACMP2_P3/SD0_DAT0/SPI0_MOSI1/ACMP1_P2/ADC0_11/ADC1_3/PE.11
PA.0/TAMPER0/SC0_CD/CAN1_RXD/INT0
VBAT
PG.14/X32K_OUT/I2C1_SDA
PG.15/X32K_IN/I2C1_SCL
Figure 4.2-2 NuMicro NUC442Vxxxx LQFP 100-pin Diagram
June 16, 2016
Page 22 of 228
Rev 1.09
NUC442
4.2.1.3 NuMicro NUC442Kxxxx LQFP 128-pin
VDD
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2
VSS
98
ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3
LDO_CAP
99
ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4
PC.11/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3
PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2
100
ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5
101
EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6
PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6
PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21
PD.12/SC3_CLK/I2C4_SDA
102
EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7
103
SPI0_CLK/TM0_EXT/PC.8
104
SD0_DAT3/SPI3_SS0/PF.2
PD.11/SC3_RST/TM3_CNT_OUT
PD.10/SC3_DAT/I2C4_SCL
105
SD0_DAT2/SPI3_CLK/PF.3
106
SD0_DAT1/SPI3_MISO0/PF.4
PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3
PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2
PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1
PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0
PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20
PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19
PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18
PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17
VSS
107
SD0_DAT0/SPI3_MOSI0/PF.5
108
SD0_CDn/UART2_RXD/PF.6
109
SD0_CMD/UART2_TXD/PF.7
110
SD0_CLK/UART2_RTS/PF.8
111
LDO_CAP
112
VSS
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NUC442 LQFP 128
VDD
INT4/ADC0_0/PE.0
TM2_CNT_OUT/ADC0_1/PE.1
VDD
SPI0_MISO0/ACMP0_O/ADC0_2/PE.2
PA.6/SC2_CD/I2S0_LRCK/PWM0_1/QEI1_A/CAN1_TXD/EBI_A16/ECAP1_IC0
PA.5/SC2_RST/SPI3_SS0/I2S0_BCLK/PWM0_0/QEI1_B/EBI_A15/ECAP1_IC1
PA.4/SC2_PWR/SPI3_CLK/I2S0_DI/QEI1_Z/EBI_A14/ECAP1_IC2
PA.3/SC2_CLK/SPI3_MOSI0/I2S0_DO/BRAKE10/EBI_A13
PA.2/SC2_DAT/SPI3_MISO0/I2S0_MCLK/BRAKE11/CAP_SFIELD/EBI_A12
PD.9/SPI3_MOSI1/I2C0_SDA
SPI0_MOSI0/ACMP0_P3/ADC0_3/PE.3
SPI0_SS0/ACMP0_P2/ADC0_4/PE.4
SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5
EBI_nWR/SD0_CMD/SPI0_MISO0/ACMP0_P0/ADC0_6/PE.6
EBI_nRD/SD0_CLK/SPI0_MOSI0/ACMP0_N/ADC0_7/PE.7
AVSS
PD.8/SPI3_MISO1/I2C0_SCL
VREF
AVDD
PA.1/TAMPER1/SC5_CD/CAN1_TXD/EBI_A22
PA.0/TAMPER0/SC0_CD/CAN1_RXD/INT0
VBAT
EBI_ALE/SD0_DAT3/TM1_CNT_OUT/ACMP1_N/ADC0_8/ADC1_0/PE.8
EBI_nWRH/SD0_DAT2/ACMP1_P0/ADC0_9/ADC1_1/PE.9
EBI_nWRL/SD0_DAT1/SPI0_MISO1/ACMP1_P1/ADC0_10/ADC1_2/PE.10
EBI_nCS0/ACMP2_P3/SD0_DAT0/SPI0_MOSI1/ACMP1_P2/ADC0_11/ADC1_3/PE.11
PG.14/X32K_OUT/I2C1_SDA
PG.15/X32K_IN/I2C1_SCL
Figure 4.2-3 NuMicro NUC442Kxxxx LQFP 128-pin Diagram
June 16, 2016
Page 23 of 228
Rev 1.09
NUC442
4.2.1.4 NuMicro NUC442Jxxxx LQFP 144-pin
109
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VDD
EBI_AD13/TM3_CNT_OUT/UART4_TXD/SC1_CLK/I2S1_BCLK/PC.1
110
VSS
EBI_AD12/SPI0_SS0/UART4_RTS/SC1_PWR/I2S1_LRCK/PC.2
111
LDO_CAP
ECAP0_IC2/EBI_AD11/QEI0_Z/SPI0_MISO1/UART4_CTS/SC1_CD/I2S1_MCLK/PC.3
112
PC.11/UART2_TXD/PWM0_3/EBI_A24/EBI_AD3
PC.10/SC3_CD/UART2_RXD/PWM0_2/EBI_A23/EBI_AD2
ECAP0_IC1/EBI_AD10/QEI0_B/SPI0_MOSI1/SC1_RST/I2S1_DO/PC.4
113
ECAP0_IC0/EBI_MCLK/QEI0_A/CLKO/PC.5
114
PC.9/STADC/UART2_CTS/SC3_RST/I2C0_SDA/CAP_DATA1/I2C3_SCL/EBI_A22/SD1_DAT0/EBI_A6
PA.15/SC3_PWR/UART2_RTS/I2C0_SCL/EBI_A21
PD.12/SC3_CLK/I2C4_SDA
EBI_AD9/TM2_CNT_OUT/SPI0_MISO0/TM2_EXT/PC.6
115
EBI_AD8/SPI0_MOSI0/TM1_EXT/PC.7
116
SPI0_CLK/TM0_EXT/PC.8
117
PD.11/SC3_RST/TM3_CNT_OUT
PD.10/SC3_DAT/I2C4_SCL
SD0_DAT3/SPI3_SS0/PF.2
118
SD0_DAT2/SPI3_CLK/PF.3
119
PA.14/UART0_TXD/SC3_CLK/PWM1_5/EBI_AD3
PA.13/UART0_RXD/SC3_DAT/PWM1_4/EBI_AD2
PA.12/UART0_CTS/SPI3_MOSI1/PWM0_4/EPWM0_0/EBI_AD1
PA.11/UART0_RTS/SPI3_MISO1/PWM0_5/EPWM0_1/EBI_AD0
PA.10/SC0_DAT/SPI3_MOSI0/PWM1_0/EPWM0_2/EBI_A20
PA.9/SC0_PWR/SPI3_MISO0/PWM1_1/EPWM0_3/EBI_A19
PA.8/SC0_RST/SPI3_CLK/PWM1_2/EPWM0_4/EBI_A18
PA.7/SC0_CLK/SPI3_SS0/PWM1_3/EPWM0_5/EBI_A17
VSS
SD0_DAT1/SPI3_MISO0/PF.4
120
SD0_DAT0/SPI3_MOSI0/PF.5
121
VSS
VDD
122
123
SD0_CDn/UART2_RXD/PF.6
124
SD0_CMD/UART2_TXD/PF.7
125
SD0_CLK/UART2_RTS/PF.8
126
UART2_CTS/PH.2
127
LDO_CAP
NUC442 LQFP 144
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VDD
VSS
VDD
PG.6/I2S1_LRCK/SC1_CLK
PG.5/I2S1_BCLK/SC1_DAT
INT4/ADC0_0/PE.0
PG.4/PS2_DAT/I2S1_DI/SC1_PWR
TM2_CNT_OUT/ADC0_1/PE.1
PG.3/PS2_CLK/I2S1_DO/SC1_RST
SPI0_MISO0/ACMP0_O/ADC0_2/PE.2
PA.6/SC2_CD/I2S0_LRCK/PWM0_1/QEI1_A/CAN1_TXD/EBI_A16/ECAP1_IC0
PA.5/SC2_RST/SPI3_SS0/I2S0_BCLK/PWM0_0/QEI1_B/EBI_A15/ECAP1_IC1
PA.4/SC2_PWR/SPI3_CLK/I2S0_DI/QEI1_Z/EBI_A14/ECAP1_IC2
PA.3/SC2_CLK/SPI3_MOSI0/I2S0_DO/BRAKE10/EBI_A13
PA.2/SC2_DAT/SPI3_MISO0/I2S0_MCLK/BRAKE11/CAP_SFIELD/EBI_A12
PD.9/SPI3_MOSI1/I2C0_SDA
SPI0_MOSI0/ACMP0_P3/ADC0_3/PE.3
SPI0_SS0/ACMP0_P2/ADC0_4/PE.4
SD0_CDn/SPI0_CLK/ACMP0_P1/ADC0_5/PE.5
EBI_nWR/SD0_CMD/SPI0_MISO0/ACMP0_P0/ADC0_6/PE.6
EBI_nRD/SD0_CLK/SPI0_MOSI0/ACMP0_N/ADC0_7/PE.7
AVSS
PD.8/SPI3_MISO1/I2C0_SCL
VREF
AVDD
PA.1/TAMPER1/SC5_CD/CAN1_TXD/EBI_A22
PA.0/TAMPER0/SC0_CD/CAN1_RXD/INT0
VBAT
EBI_ALE/SD0_DAT3/TM1_CNT_OUT/ACMP1_N/ADC0_8/ADC1_0/PE.8
EBI_nWRH/SD0_DAT2/ACMP1_P0/ADC0_9/ADC1_1/PE.9
EBI_nWRL/SD0_DAT1/SPI0_MISO1/ACMP1_P1/ADC0_10/ADC1_2/PE.10
EBI_nCS0/ACMP2_P3/SD0_DAT0/SPI0_MOSI1/ACMP1_P2/ADC0_11/ADC1_3/PE.11
PG.14/X32K_OUT/I2C1_SDA
PG.15/X32K_IN/I2C1_SCL
Figure 4.2-4 NuMicro NUC442Jxxxx LQFP 144-pin Diagram
June 16, 2016
Page 24 of 228
Rev 1.09
NUC442
4.3 Pin Description
4.3.1 NuMicro NUC442 Package LQFP 64-pin Description
MFP = Multi-function pin.
Pin No.
Pin Name
PE.8
Type
I/O
A
MFP*
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
Description
1
General purpose digital I/O pin.
ADC1 analog input.
ADC1_0
ADC0_8
ACMP1_N
TM1_CNT_OUT
SD0_DAT3
EBI_ALE
HS
A
ADC0 analog input.
A
Analog comparator1 negative input pin.
Timer1 event counter input/toggle output.
SD mode #0 data line bit 3.
EBI address latch enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
2
PE.9
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_1
ADC0_9
ACMP1_P0
SD0_DAT2
EBI_nWRH
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
SD mode #0 data line bit 2.
EBI write enable output pin.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
3
PE.10
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_2
ADC0_10
ACMP1_P1
SPI0_MISO1
SD0_DAT1
EBI_nWRL
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 25 of 228
Rev 1.09
NUC442
4
PE.11
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_3
ADC0_11
ACMP1_P2
SPI0_MOSI1
SD0_DAT0
ACMP2_P3
EBI_nCS0
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
I/O
I/O
A
Analog comparator2 positive input pin.
EBI chip select 0 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
5
6
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
7
PD.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
Slew
General purpose digital I/O pin.
SmartCard5 clock pin.
SC5_CLK
I2C3_SDA
ACMP2_O
SD0_CDn
HS
I/O
O
I2C3 data input/output pin.
Analog comparator2 output .
SD mode #0 – card detect
I
This pad is embedded with “Slew Rate Control”
capability.
8
PD.4
I/O
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
SmartCard5 card detect pin.
Data receiver input pin for UART3.
Analog comparator1 output .
SC5_CD
UART3_RXD
ACMP1_O
HS
I
I
O
This pad is embedded with “Slew Rate Control”
capability.
9
PD.5
I/O
O
MFP0
MPF1
MPF2
Slew
General purpose digital I/O pin.
SmartCard5 reset pin.
SC5_RST
UART3_TXD
HS
O
Data transmitter output pin for UART3.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 26 of 228
Rev 1.09
NUC442
10
PD.6
I/O
O
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
SmartCard5 power pin.
SC5_PWR
UART3_RTS
SD0_CMD
HS
O
Request to Send output pin for UART3.
SD mode #0 – command/response
I/O
This pad is embedded with “Slew Rate Control”
capability.
11
PD.7
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
SmartCard5 data pin.
SC5_DAT
UART3_CTS
SD0_CLK
HS
Clear to Send input pin for UART3.
SD mode #0– clock.
O
This pad is embedded with “Slew Rate Control”
capability.
12
13
PG.13
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
General purpose digital I/O pin.
XT1_IN
PG.12
External 4~24 MHz (high-speed) crystal input pin.
General purpose digital I/O pin.
I/O
O
I
XT1_OUT
nRESET
External 4~24 MHz (high-speed) crystal output pin.
14
15
External reset input: active LOW, with an internal
pull-up. Set this pin low reset to initial state.
PG.10
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
MPF1
MPF3
MFP0
MPF1
MPF3
MFP0
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal input pin.
I2C1 clock pin.
ICE_CLK
PG.11
16
17
I/O
I/O
I/O
I
ICE_DAT
PG.15
X32K_IN
I2C1_SCL
PG.14
I/O
I/O
O
18
19
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal output pin.
I2C1 data input/output pin.
X32K_OUT
I2C1_SDA
VBAT
I/O
P
Battery power input pin.
June 16, 2016
Page 27 of 228
Rev 1.09
NUC442
20
PA.0
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF8
MFP0
MPF1
MPF3
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
Tamper detect pin 0.
TAMPER0
SC0_CD
CAN1_RXD
INT0
SmartCard0 card detect pin.
CAN bus receiver1 input.
External interrupt0 input pin.
General purpose digital I/O pin.
SmartCard2 card detect pin.
I2S0 left right channel clock.
PWM0_1 output/capture input.
CAN bus transmitter1 input.
EBI address bus bit16.
I
I
21
PA.6
I/O
I
SC2_CD
I2S0_LRCK
PWM0_1
CAN1_TXD
EBI_A16
HS
O
I/O
I
O
This pad is embedded with “Slew Rate Control”
capability.
22
PA.7
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 clock pin.
SC0_CLK
SPI3_SS0
PWM1_3
EPWM0_5
EBI_A17
HS
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM1_3 output/capture input.
PWM0_5 output/capture input.
EBI address bus bit17.
This pad is embedded with “Slew Rate Control”
capability.
23
PA.8
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 reset pin.
SC0_RST
SPI3_CLK
PWM1_2
EPWM0_4
EBI_A18
HS
O
SPI3 serial clock pin.
I/O
I/O
O
PWM1_2 output/capture input.
PWM0_4 output/capture input.
EBI address bus bit18.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 28 of 228
Rev 1.09
NUC442
24
25
26
27
PA.9
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 power pin.
SC0_PWR
SPI3_MISO0
PWM1_1
EPWM0_3
EBI_A19
HS
I/O
I/O
I/O
O
1st SPI3 MISO (Master In, Slave Out) pin.
PWM1_1 output/capture input.
PWM0_3 output/capture input.
EBI address bus bit19.
This pad is embedded with “Slew Rate Control”
capability.
PA.10
I/O
I/O
I/O
I/O
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 data pin.
SC0_DAT
SPI3_MOSI0
PWM1_0
EPWM0_2
EBI_A20
HS
1st SPI3 MOSI (Master Out, Slave In) pin.
PWM1_0 output/capture input.
PWM0_2 output/capture input.
EBI address bus bit20.
This pad is embedded with “Slew Rate Control”
capability.
PA.11
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART0.
2nd SPI3 MISO (Master In, Slave Out) pin.
PWM0_5 output/capture input.
UART0_RTS
SPI3_MISO1
PWM0_5
EPWM0_1
EBI_AD0
HS
I/O
I/O
I/O
O
PWM0_1 output/capture input.
EBI address/data bus bit 0.
This pad is embedded with “Slew Rate Control”
capability.
PA.12
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF5
General purpose digital I/O pin.
Clear to Send input pin for UART0.
2nd SPI3 MOSI (Master Out, Slave In) pin.
PWM0_4 output/capture input.
UART0_CTS
SPI3_MOSI1
PWM0_4
I/O
I/O
I/O
EPWM0_0
PWM0_0 output/capture input.
June 16, 2016
Page 29 of 228
Rev 1.09
NUC442
EBI_AD1
HS
O
MPF7
Slew
EBI address/data bus bit 1.
This pad is embedded with “Slew Rate Control”
capability.
28
29
30
PA.13
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART0.
SmartCard3 data pin.
UART0_RXD
SC3_DAT
PWM1_4
EBI_AD2
HS
I/O
I/O
O
PWM1_4 output/capture input.
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
PA.14
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART0.
SmartCard3 clock pin.
UART0_TXD
SC3_CLK
PWM1_5
EBI_AD3
HS
O
I/O
O
PWM1_5 output/capture input.
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
31
32
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
33
VRES
A
MFP0
USB PHY VRES ground input pin. Add an 8.2K
ohm resistor to VSSA.
34
35
36
VBUS
A
P
P
MFP0
MFP0
MFP0
USB PHY VBUS power input pin.
USB_VDD33_CAP
VSSA
Internal power regulator output 3.3V decoupling pin.
Ground pin for digital circuit. Add a Feritte Bead to
digital ground VSS
.
37
38
39
USB0_D-
A
A
I
MFP0
MFP0
MFP0
USB0 differential signal D-.
USB0 differential signal D+.
USB0 OTG ID pin.
USB0_D+
USB0_OTG_ID
June 16, 2016
Page 30 of 228
Rev 1.09
NUC442
40
41
42
PB.0
I/O
I
MFP0
MPF1
MPF2
MPF8
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
USB0 external VBUS regulator status
I2C4 clock pin.
USB0_OTG5V_ST
I2C4_SCL
INT1
I/O
I
External interrupt1 input pin.
General purpose digital I/O pin.
USB0 external VBUS regulator enable
I2C4 data input/output pin.
PB.1
I/O
O
USB0_OTG5V_EN
I2C4_SDA
TM1_CNT_OUT
PB.2
I/O
I/O
I/O
I
Timer1 event counter input/toggle output.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
USB1 differential signal D-.
UART1_RXD
SPI2_SS0
USB1_D-
EBI_AD4
HS
I/O
A
O
EBI address/data bus bit 4.
This pad is embedded with “Slew Rate Control”
capability.
43
PB.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI2 serial clock pin.
UART1_TXD
SPI2_CLK
USB1_D+
EBI_AD5
HS
O
A
USB1 differential signal D+.
EBI address/data bus bit 5.
O
This pad is embedded with “Slew Rate Control”
capability.
44
PB.4
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
General purpose digital I/O pin.
UART1_RTS
SPI2_MISO0
UART4_RXD
TM0_CNT_OUT
EBI_AD6
Request to Send output pin for UART1.
1st SPI2 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART4.
Timer0 event counter input/toggle output.
EBI address/data bus bit 6.
I/O
I
I/O
O
June 16, 2016
Page 31 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
45
46
47
PB.5
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART1.
1st SPI2 MOSI (Master Out, Slave In) pin.
Data transmitter output pin for UART4.
EBI address/data bus bit 7.
UART1_CTS
SPI2_MOSI0
UART4_TXD
EBI_AD7
HS
I/O
O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.12
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART4.
2nd SPI2 MISO (Master In, Slave Out) pin.
CAN bus receiver0 input.
UART4_RTS
SPI2_MISO1
CAN0_RXD
EBI_AD14
HS
I/O
I
O
EBI address/data bus bit 14.
This pad is embedded with “Slew Rate Control”
capability.
PB.13
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART4.
2nd SPI2 MOSI (Master Out, Slave In) pin.
CAN bus transmitter0 input.
UART4_CTS
SPI2_MOSI1
CAN0_TXD
EBI_AD15
HS
I/O
I
O
EBI address/data bus bit 15.
This pad is embedded with “Slew Rate Control”
capability.
48
49
VDD
P
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
PC.0
I/O
MFP0
MPF1
MPF2
MPF3
MPF7
MPF8
General purpose digital I/O pin.
I2S1 data input.
I2S1_DI
SC1_DAT
UART4_RXD
EBI_MCLK
INT2
I
I/O
I
SmartCard1 data pin.
Data receiver input pin for UART4.
EBI interface clock output pin.
External interrupt2 input pin.
O
I
June 16, 2016
Page 32 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
50
51
52
53
PC.1
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2S1 bit clock pin.
I2S1_BCLK
SC1_CLK
UART4_TXD
TM3_CNT_OUT
EBI_AD13
HS
O
SmartCard1 clock pin.
O
Data transmitter output pin for UART4.
Timer3 event counter input/toggle output.
EBI address/data bus bit 13.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.2
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
I2S1 left right channel clock.
SmartCard1 power pin.
I2S1_LRCK
SC1_PWR
UART4_RTS
SPI0_SS0
EBI_AD12
HS
O
O
Request to Send output pin for UART4.
General purpose digital I/O pin.
EBI address/data bus bit 12.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.3
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
I2S1 master clock output pin.
I2S1_MCLK
SC1_CD
UART4_CTS
SPI0_MISO1
EBI_AD11
HS
SmartCard1 card detect pin.
I
Clear to Send input pin for UART4.
2nd SPI0 MISO (Master In, Slave Out) pin.
EBI address/data bus bit 11.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.4
I/O
O
MFP0
MPF1
MPF2
MPF4
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_RST
SPI0_MOSI1
O
SmartCard1 reset pin.
I/O
2nd SPI0 MOSI (Master Out, Slave In) pin.
June 16, 2016
Page 33 of 228
Rev 1.09
NUC442
EBI_AD10
HS
O
MPF7
Slew
EBI address/data bus bit 10.
This pad is embedded with “Slew Rate Control”
capability.
54
PC.6
I/O
I
MFP0
MPF1
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Timer2 external counter input
TM2_EXT
SPI0_MISO0
TM2_CNT_OUT
EBI_AD9
HS
I/O
I/O
O
1st SPI0 MISO (Master In, Slave Out) pin.
Timer2 event counter input/toggle output.
EBI address/data bus bit 9.
This pad is embedded with “Slew Rate Control”
capability.
55
PC.7
I/O
I
MFP0
MPF1
MPF4
MPF7
Slew
General purpose digital I/O pin.
Timer1 external counter input
TM1_EXT
SPI0_MOSI0
EBI_AD8
HS
I/O
O
1st SPI0 MOSI (Master Out, Slave In) pin.
EBI address/data bus bit 8.
This pad is embedded with “Slew Rate Control”
capability.
56
PC.8
I/O
I
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Timer0 external counter input
SPI0 serial clock pin.
TM0_EXT
SPI0_CLK
HS
O
This pad is embedded with “Slew Rate Control”
capability.
57
58
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
PE.4
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_4
ACMP0_P2
SPI0_SS0
HS
A
Analog comparator0 positive input pin.
General purpose digital I/O pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
59
PE.5
I/O
A
MFP0
MPF1
General purpose digital I/O pin.
ADC0 analog input.
ADC0_5
June 16, 2016
Page 34 of 228
Rev 1.09
NUC442
ACMP0_P1
SPI0_CLK
SD0_CDn
HS
A
O
I
MPF2
MPF3
MPF4
Slew
Analog comparator0 positive input pin.
SPI0 serial clock pin.
SD mode #0 – card detect
This pad is embedded with “Slew Rate Control”
capability.
60
PE.6
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_6
ACMP0_P0
SPI0_MISO0
SD0_CMD
EBI_nWR
HS
A
Analog comparator0 positive input pin.
1st SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 – command/response
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
61
PE.7
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_7
ACMP0_N
SPI0_MOSI0
SD0_CLK
EBI_nRD
HS
A
Analog comparator0 negative input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 – clock.
I/O
O
O
EBI read enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
62
63
AVSS
VREF
P
A
MFP0
MFP0
Ground pin for digital circuit.
Voltage reference input for ADC.
Note: This pin needs to be connected with
0.1uF/10uF capacitors.
64
AVDD
P
MFP0
Power supply for internal analog circuit.
Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin;
June 16, 2016
Page 35 of 228
Rev 1.09
NUC442
4.3.2 NuMicro NUC442 Package LQFP 100-pin Description
MFP = Multi-function pin.
Pin No.
Pin Name
PE.12
Type
I/O
A
MFP*
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
Description
1
General purpose digital I/O pin.
ADC1 analog input.
ADC1_4
ACMP1_P3
ACMP2_P2
EBI_nCS1
HS
A
Analog comparator1 positive input pin.
Analog comparator2 positive input pin.
EBI chip select 1 enable output pin.
A
O
This pad is embedded with “Slew Rate Control”
capability.
2
3
4
PE.13
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_5
ACMP2_P1
EBI_nCS2
HS
A
Analog comparator2 positive input pin.
EBI chip select 2 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
PE.14
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_6
ACMP2_P0
EBI_nCS3
HS
A
Analog comparator2 positive input pin.
EBI chip select 3 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
PE.15
ADC1_7
ACMP2_N
VSS
I/O
A
MFP0
MPF1
MPF3
MFP0
MFP0
General purpose digital I/O pin.
ADC1 analog input.
A
Analog comparator2 negative input pin.
Ground pin for digital circuit.
5
6
P
VDD
P
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
7
PC.12
I/O
I/O
MFP0
MPF1
General purpose digital I/O pin.
1st SPI1 slave select pin..
SPI1_SS0
June 16, 2016
Page 36 of 228
Rev 1.09
NUC442
SC4_CD
SD1_CDn
CAP_DATA7
EBI_A0
I
I
MPF2
MPF4
MPF5
MPF7
Slew
SmartCard4 card detect pin.
SD mode #1 – card detect
Image data input bus bit 7.
EBI address bus bit0.
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
8
PC.13
I/O
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
2nd SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 reset pin.
SPI1_MOSI1
SC4_RST
SD1_CMD
CAP_DATA6
EBI_A1
I/O
I
SD mode #1 – command/response
Image data input bus bit 6.
O
EBI address bus bit1.
HS
This pad is embedded with “Slew Rate Control”
capability.
9
PC.14
I/O
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 power pin.
SPI1_MISO1
SC4_PWR
TM3_EXT
SD1_CLK
CAP_DATA5
EBI_A2
Timer3 external counter input
SD mode #1 – clock.
O
I
Image data input bus bit 5.
EBI address bus bit2.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
10
PC.15
I/O
I/O
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 data pin.
SPI1_MOSI0
SC4_DAT
SD1_DAT3
CAP_DATA4
EBI_A3
SD mode #1 data line bit 3.
Image data input bus bit 4.
EBI address bus bit3.
O
June 16, 2016
Page 37 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
11
PD.0
I/O
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 clock pin.
SPI1_MISO0
SC4_CLK
SD1_DAT2
CAP_DATA3
EBI_A4
I/O
I
SD mode #1 data line bit 2.
Image data input bus bit 3.
EBI address bus bit4.
O
INT3
I
External interrupt3 input pin.
HS
This pad is embedded with “Slew Rate Control”
capability.
12
PD.1
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
TM0_CNT_OUT
SD1_DAT1
CAP_DATA2
EBI_A5
I/O
I/O
I
Timer0 event counter input/toggle output.
SD mode #1 data line bit 1.
Image data input bus bit 2.
EBI address bus bit5.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
13
PD.3
I/O
O
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 clock pin.
SC5_CLK
I2C3_SDA
ACMP2_O
SD0_CDn
CAP_DATA0
EBI_A7
I2C3 data input/output pin.
Analog comparator2 output.
SD mode #0 – card detect
Image data input bus bit 0.
EBI address bus bit7.
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
14
PD.4
I/O
I
MFP0
MPF1
General purpose digital I/O pin.
SmartCard5 card detect pin.
SC5_CD
June 16, 2016
Page 38 of 228
Rev 1.09
NUC442
UART3_RXD
ACMP1_O
CAP_SCLK
EBI_A8
I
MPF2
MPF3
MPF5
MPF7
Slew
Data receiver input pin for UART3.
Analog comparator1 output.
O
O
O
Image capture interface sensor clock pin.
EBI address bus bit8.
HS
This pad is embedded with “Slew Rate Control”
capability.
15
PD.5
I/O
O
O
I
MFP0
MPF1
MPF2
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 reset pin.
SC5_RST
UART3_TXD
CAP_VSYNC
EBI_A9
Data transmitter output pin for UART3.
Image capture interface VSYNC input pin.
EBI address bus bit9.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
16
PD.6
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 power pin.
SC5_PWR
UART3_RTS
SD0_CMD
CAP_HSYNC
EBI_A10
HS
O
Request to Send output pin for UART3.
SD mode #0 – command/response
Image capture interface HSYNC input pin.
EBI address bus bit10.
I/O
I
O
This pad is embedded with “Slew Rate Control”
capability.
17
PD.7
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 data pin.
SC5_DAT
UART3_CTS
SD0_CLK
CAP_PIXCLK
EBI_A11
HS
Clear to Send input pin for UART3.
SD mode #0 – clock.
O
I
Image capture interface pix clock input pin.
EBI address bus bit11.
O
This pad is embedded with “Slew Rate Control”
capability.
18
PG.13
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 39 of 228
Rev 1.09
NUC442
XT1_IN
PG.12
I
MPF1
MFP0
MPF1
External 4~24 MHz (high-speed) crystal input pin.
19
I/O
O
General purpose digital I/O pin.
XT1_OUT
External 4~24 MHz (high-speed) crystal output
pin.
20
21
nRESET
I
MFP0
MFP0
External reset input: active LOW, with an internal
pull-up. Set this pin low reset to initial state.
LDO_CAP
P
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
22
23
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
24
25
26
PG.10
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
MPF1
MPF3
MFP0
MPF1
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal input pin.
I2C1 clock pin.
ICE_CLK
PG.11
I/O
I/O
I/O
I
ICE_DAT
PG.15
X32K_IN
I2C1_SCL
PG.14
I/O
I/O
O
27
General purpose digital I/O pin.
X32K_OUT
External 32.768 kHz (low-speed) crystal output
pin.
I2C1_SDA
VBAT
I/O
P
MPF3
MFP0
MFP0
MPF1
MPF2
MPF3
MPF8
MFP0
MPF1
I2C1 data input/output pin.
Battery power input pin.
28
29
PA.0
I/O
I/O
I
General purpose digital I/O pin.
Tamper detect pin 0.
TAMPER0
SC0_CD
CAN1_RXD
INT0
SmartCard0 card detect pin.
CAN bus receiver1 input.
External interrupt0 input pin.
General purpose digital I/O pin.
Tamper detect pin 1.
I
I
30
PA.1
I/O
I/O
TAMPER1
June 16, 2016
Page 40 of 228
Rev 1.09
NUC442
SC5_CD
CAN1_TXD
EBI_A22
PA.2
I
I
MPF2
MPF3
MPF7
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
SmartCard5 card detect pin.
CAN bus transmitter1 input.
EBI address bus bit22.
O
I/O
I/O
I/O
O
I
31
General purpose digital I/O pin.
SmartCard2 data pin.
SC2_DAT
SPI3_MISO0
I2S0_MCLK
BRAKE11
CAP_SFIELD
EBI_A12
HS
1st SPI3 MISO (Master In, Slave Out) pin.
I2S0 master clock output pin.
Brake input pin 1 of EPWM0.
Video input interface SFIELD input pin.
EBI address bus bit12.
I
O
This pad is embedded with “Slew Rate Control”
capability.
32
PA.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
SmartCard2 clock pin.
SC2_CLK
SPI3_MOSI0
I2S0_DO
BRAKE10
EBI_A13
HS
I/O
O
1st SPI3 MOSI (Master Out, Slave In) pin.
I2S0 data output.
I
Brake input pin 0 of EPWM0.
EBI address bus bit13.
O
This pad is embedded with “Slew Rate Control”
capability.
33
PA.4
I/O
O
O
I
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 power pin.
SC2_PWR
SPI3_CLK
I2S0_DI
QEI1_Z
EBI_A14
ECAP1_IC2
HS
SPI3 serial clock pin.
I2S0 data input.
I
Quadrature encoder phase Z input of QEI Unit 1.
EBI address bus bit14.
O
I
Input 2 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 41 of 228
Rev 1.09
NUC442
34
PA.5
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 reset pin.
SC2_RST
SPI3_SS0
I2S0_BCLK
PWM0_0
QEI1_B
I/O
O
General purpose digital I/O pin.
I2S0 bit clock pin.
I/O
I
PWM0_0 output/capture input.
Quadrature encoder phase B input of QEI Unit 1.
EBI address bus bit15.
EBI_A15
ECAP1_IC1
HS
O
I
Input 1 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
35
PA.6
I/O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 card detect pin.
SC2_CD
I2S0_LRCK
PWM0_1
QEI1_A
I
O
I/O
I
I2S0 left right channel clock.
PWM0_1 output/capture input.
Quadrature encoder phase A input of QEI Unit 1.
CAN bus transmitter1 input.
CAN1_TXD
EBI_A16
ECAP1_IC0
HS
I
O
I
EBI address bus bit16.
Input 0 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
36
PA.7
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 clock pin.
SC0_CLK
SPI3_SS0
PWM1_3
EPWM0_5
EBI_A17
HS
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM1_3 output/capture input.
PWM0_5 output/capture input.
EBI address bus bit17.
This pad is embedded with “Slew Rate Control”
capability.
37
PA.8
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 42 of 228
Rev 1.09
NUC442
SC0_RST
SPI3_CLK
PWM1_2
EPWM0_4
EBI_A18
HS
O
O
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
SmartCard0 reset pin.
SPI3 serial clock pin.
I/O
I/O
O
PWM1_2 output/capture input.
PWM0_4 output/capture input.
EBI address bus bit18.
This pad is embedded with “Slew Rate Control”
capability.
38
39
40
PA.9
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 power pin.
SC0_PWR
SPI3_MISO0
PWM1_1
EPWM0_3
EBI_A19
HS
I/O
I/O
I/O
O
1st SPI3 MISO (Master In, Slave Out) pin.
PWM1_1 output/capture input.
PWM0_3 output/capture input.
EBI address bus bit19.
This pad is embedded with “Slew Rate Control”
capability.
PA.10
I/O
I/O
I/O
I/O
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 data pin.
SC0_DAT
SPI3_MOSI0
PWM1_0
EPWM0_2
EBI_A20
HS
1st SPI3 MOSI (Master Out, Slave In) pin.
PWM1_0 output/capture input.
PWM0_2 output/capture input.
EBI address bus bit20.
This pad is embedded with “Slew Rate Control”
capability.
PA.11
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
General purpose digital I/O pin.
Request to Send output pin for UART0.
2nd SPI3 MISO (Master In, Slave Out) pin.
PWM0_5 output/capture input.
PWM0_1 output/capture input.
EBI address/data bus bit 0.
UART0_RTS
SPI3_MISO1
PWM0_5
I/O
I/O
I/O
O
EPWM0_1
EBI_AD0
June 16, 2016
Page 43 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
41
PA.12
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART0.
2nd SPI3 MOSI (Master Out, Slave In) pin.
PWM0_4 output/capture input.
PWM0_0 output/capture input.
EBI address/data bus bit 1.
UART0_CTS
SPI3_MOSI1
PWM0_4
EPWM0_0
EBI_AD1
HS
I/O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
42
43
44
PA.13
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART0.
SmartCard3 data pin.
UART0_RXD
SC3_DAT
PWM1_4
EBI_AD2
HS
I/O
I/O
O
PWM1_4 output/capture input.
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
PA.14
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART0.
SmartCard3 clock pin.
UART0_TXD
SC3_CLK
PWM1_5
EBI_AD3
HS
O
I/O
O
PWM1_5 output/capture input.
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
PA.15
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
SmartCard3 power pin.
SC3_PWR
UART2_RTS
I2C0_SCL
EBI_A21
HS
O
Request to Send output pin for UART2.
I2C0 clock pin.
I/O
O
EBI address bus bit21.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 44 of 228
Rev 1.09
NUC442
45
PC.9
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8
MPF9
Slew
General purpose digital I/O pin.
ADC analog input.
STADC
UART2_CTS
SC3_RST
I2C0_SDA
CAP_DATA1
I2C3_SCL
EBI_A22
SD1_DAT0
EBI_A6
I
Clear to Send input pin for UART2.
SmartCard3 reset pin.
O
I/O
I
I2C0 data input/output pin.
Image data input bus bit 1.
I2C3 clock pin.
I/O
O
EBI address bus bit22.
SD mode #1 data line bit 0.
EBI address bus bit6.
I/O
O
HS
This pad is embedded with “Slew Rate Control”
capability.
46
PC.10
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
SmartCard3 card detect pin.
Data receiver input pin for UART2.
PWM0_2 output/capture input.
EBI address bus bit23.
SC3_CD
UART2_RXD
PWM0_2
EBI_A23
EBI_AD2
HS
I
I/O
O
O
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
47
PC.11
I/O
O
MFP0
MPF2
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART2.
PWM0_3 output/capture input.
EBI address bus bit24.
UART2_TXD
PWM0_3
EBI_A24
EBI_AD3
HS
I/O
O
O
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
48
49
LDO_CAP
P
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
VSS
MFP0
Ground pin for digital circuit.
June 16, 2016
Page 45 of 228
Rev 1.09
NUC442
50
51
VDD
P
A
MFP0
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
VRES
USB PHY VRES ground input pin. Add an 8.2K
ohm resistor to VSSA.
52
53
VBUS
A
P
MFP0
MFP0
USB PHY VBUS power input pin.
USB_VDD33_CAP
Internal power regulator output 3.3V decoupling
pin.
54
VSSA
P
MFP0
Ground pin for digital circuit. Add a Feritte Bead
to digital ground VSS
.
55
56
57
58
USB0_D-
USB0_D+
USB0_OTG_ID
PB.0
A
A
MFP0
MFP0
MFP0
MFP0
MPF1
MPF2
MPF8
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
USB0 differential signal D-.
USB0 differential signal D+.
USB0 OTG ID pin.
I
I/O
I
General purpose digital I/O pin.
USB0 external VBUS regulator status
I2C4 clock pin.
USB0_OTG5V_ST
I2C4_SCL
INT1
I/O
I
External interrupt1 input pin.
General purpose digital I/O pin.
USB0 external VBUS regulator enable
I2C4 data input/output pin.
59
PB.1
I/O
O
USB0_OTG5V_EN
I2C4_SDA
TM1_CNT_OUT
PB.2
I/O
I/O
I/O
I
Timer1 event counter input/toggle output.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
USB1 differential signal D-.
EBI address/data bus bit 4.
60
UART1_RXD
SPI2_SS0
USB1_D-
EBI_AD4
I/O
A
O
HS
This pad is embedded with “Slew Rate Control”
capability.
61
PB.3
I/O
O
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI2 serial clock pin.
UART1_TXD
SPI2_CLK
USB1_D+
O
A
USB1 differential signal D+.
June 16, 2016
Page 46 of 228
Rev 1.09
NUC442
EBI_AD5
HS
O
MPF7
Slew
EBI address/data bus bit 5.
This pad is embedded with “Slew Rate Control”
capability.
62
PB.4
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
UART1_RTS
SPI2_MISO0
UART4_RXD
TM0_CNT_OUT
EBI_AD6
Request to Send output pin for UART1.
1st SPI2 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART4.
Timer0 event counter input/toggle output.
EBI address/data bus bit 6.
I/O
I
I/O
O
HS
This pad is embedded with “Slew Rate Control”
capability.
63
PB.5
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
UART1_CTS
SPI2_MOSI0
UART4_TXD
EBI_AD7
HS
Clear to Send input pin for UART1.
1st SPI2 MOSI (Master Out, Slave In) pin.
Data transmitter output pin for UART4.
EBI address/data bus bit 7.
I/O
O
O
This pad is embedded with “Slew Rate Control”
capability.
64
PB.6
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2C2 clock pin.
I2C2_SCL
BRAKE01
UART4_RTS
PWM1_4
EPWM1_0
EBI_AD8
HS
Brake input pin 1 of EPWMB.
Request to Send output pin for UART4.
PWM1_4 output/capture input.
PWM1_0 output/capture input.
EBI address/data bus bit 8.
O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
65
PB.7
I/O
I/O
I
MFP0
MPF1
MPF2
General purpose digital I/O pin.
I2C2 data input/output pin.
Brake input pin 0 of EPWMB.
I2C2_SDA
BRAKE00
June 16, 2016
Page 47 of 228
Rev 1.09
NUC442
UART4_CTS
PWM1_5
EPWM1_1
EBI_AD9
HS
I
MPF3
MPF4
MPF5
MPF7
Slew
Clear to Send input pin for UART4.
PWM1_5 output/capture input.
PWM1_1 output/capture input.
EBI address/data bus bit 9.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
66
67
68
69
70
PB.8
I/O
I
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART5.
PWM1_2 output/capture input.
EBI address/data bus bit 10.
UART5_CTS
EPWM1_2
EBI_AD10
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.9
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART5.
PWM1_3 output/capture input.
EBI address/data bus bit 11.
UART5_RTS
EPWM1_3
EBI_AD11
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.10
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART5.
PWM1_4 output/capture input.
EBI address/data bus bit 12.
UART5_TXD
EPWM1_4
EBI_AD12
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.11
I/O
I
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART5.
PWM1_5 output/capture input.
EBI address/data bus bit 13.
UART5_RXD
EPWM1_5
EBI_AD13
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.12
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 48 of 228
Rev 1.09
NUC442
UART4_RTS
SPI2_MISO1
CAN0_RXD
EBI_AD14
HS
O
I/O
I
MPF1
MPF2
MPF3
MPF7
Slew
Request to Send output pin for UART4.
2nd SPI2 MISO (Master In, Slave Out) pin.
CAN bus receiver0 input.
O
EBI address/data bus bit 14.
This pad is embedded with “Slew Rate Control”
capability.
71
PB.13
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART4.
2nd SPI2 MOSI (Master Out, Slave In) pin.
CAN bus transmitter0 input.
UART4_CTS
SPI2_MOSI1
CAN0_TXD
EBI_AD15
HS
I/O
I
O
EBI address/data bus bit 15.
This pad is embedded with “Slew Rate Control”
capability.
72
PB.14
I/O
O
O
I
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
I2S1 master clock output pin.
SmartCard1 reset pin.
I2S1_MCLK
SC1_RST
BRAKE01
HS
Brake input pin 1 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
73
PB.15
I/O
O
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_DAT
BRAKE00
HS
I/O
I
SmartCard1 data pin.
Brake input pin 0 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
74
75
VDD
P
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
PC.0
I/O
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
I2S1 data input.
I2S1_DI
I
I/O
I
SC1_DAT
UART4_RXD
SmartCard1 data pin.
Data receiver input pin for UART4.
June 16, 2016
Page 49 of 228
Rev 1.09
NUC442
EBI_MCLK
INT2
O
I
MPF7
MPF8
Slew
EBI interface clock output pin.
External interrupt2 input pin.
HS
This pad is embedded with “Slew Rate Control”
capability.
76
77
78
PC.1
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2S1 bit clock pin.
I2S1_BCLK
SC1_CLK
UART4_TXD
TM3_CNT_OUT
EBI_AD13
HS
O
SmartCard1 clock pin.
O
Data transmitter output pin for UART4.
Timer3 event counter input/toggle output.
EBI address/data bus bit 13.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.2
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
I2S1 left right channel clock.
SmartCard1 power pin.
I2S1_LRCK
SC1_PWR
UART4_RTS
SPI0_SS0
EBI_AD12
HS
O
O
Request to Send output pin for UART4.
General purpose digital I/O pin.
EBI address/data bus bit 12.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.3
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1_MCLK
SC1_CD
UART4_CTS
SPI0_MISO1
QEI0_Z
I2S1 master clock output pin.
SmartCard1 card detect pin.
I
Clear to Send input pin for UART4.
2nd SPI0 MISO (Master In, Slave Out) pin.
Quadrature encoder phase Z input of QEI Unit 0.
EBI address/data bus bit 11.
I/O
I
EBI_AD11
ECAP0_IC2
HS
O
O
Input 2 of enhanced capture unit 0.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 50 of 228
Rev 1.09
NUC442
79
PC.4
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_RST
SPI0_MOSI1
QEI0_B
O
SmartCard1 reset pin.
I/O
I
2nd SPI0 MOSI (Master Out, Slave In) pin.
Quadrature encoder phase B input of QEI Unit 0.
EBI address/data bus bit 10.
EBI_AD10
ECAP0_IC1
HS
O
O
Input 1 of enhanced capture unit 0.
This pad is embedded with “Slew Rate Control”
capability.
80
PC.5
I/O
O
I
MFP0
MFP1
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
Clock Output Pin.
CLKO
QEI0_A
EBI_MCLK
ECAP0_IC0
HS
Quadrature encoder phase A input of QEI Unit 0.
EBI interface clock output pin.
Input 0 of enhanced capture unit 0.
O
O
This pad is embedded with “Slew Rate Control”
capability.
81
PC.6
I/O
I
MFP0
MPF1
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Timer2 external counter input
TM2_EXT
SPI0_MISO0
TM2_CNT_OUT
EBI_AD9
HS
I/O
I/O
O
1st SPI0 MISO (Master In, Slave Out) pin.
Timer2 event counter input/toggle output.
EBI address/data bus bit 9.
This pad is embedded with “Slew Rate Control”
capability.
82
PC.7
I/O
I
MFP0
MPF1
MPF4
MPF7
Slew
General purpose digital I/O pin.
Timer1 external counter input
TM1_EXT
SPI0_MOSI0
EBI_AD8
HS
I/O
O
1st SPI0 MOSI (Master Out, Slave In) pin.
EBI address/data bus bit 8.
This pad is embedded with “Slew Rate Control”
capability.
83
PC.8
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 51 of 228
Rev 1.09
NUC442
TM0_EXT
SPI0_CLK
HS
I
MPF1
MPF4
Slew
Timer0 external counter input
SPI0 serial clock pin.
O
This pad is embedded with “Slew Rate Control”
capability.
84
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
85
86
VSS
P
I/O
A
MFP0
MFP0
MPF1
MPF8
MFP0
MPF1
MPF3
MFP0
MPF1
MPF2
MPF3
Slew
Ground pin for digital circuit.
General purpose digital I/O pin.
ADC0 analog input.
PE.0
ADC0_0
INT4
I
External interrupt4 input pin.
General purpose digital I/O pin.
ADC0 analog input.
87
88
PE.1
I/O
A
ADC0_1
TM2_CNT_OUT
PE.2
I/O
I/O
A
Timer2 event counter input/toggle output.
General purpose digital I/O pin.
ADC0 analog input.
ADC0_2
ACMP0_O
SPI0_MISO0
HS
O
Analog comparator0 output .
1st SPI0 MISO (Master In, Slave Out) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
89
PE.3
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_3
ACMP0_P3
SPI0_MOSI0
HS
A
Analog comparator0 positive input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
90
PE.4
I/O
A
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
ADC0 analog input.
ADC0_4
ACMP0_P2
SPI0_SS0
A
Analog comparator0 positive input pin.
General purpose digital I/O pin.
I/O
June 16, 2016
Page 52 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
91
PE.5
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_5
ACMP0_P1
SPI0_CLK
SD0_CDn
HS
A
Analog comparator0 positive input pin.
SPI0 serial clock pin.
O
I
SD mode #0 – card detect
This pad is embedded with “Slew Rate Control”
capability.
92
PE.6
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_6
ACMP0_P0
SPI0_MISO0
SD0_CMD
EBI_nWR
HS
A
Analog comparator0 positive input pin.
1st SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 – command/response
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
93
PE.7
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_7
ACMP0_N
SPI0_MOSI0
SD0_CLK
EBI_nRD
HS
A
Analog comparator0 negative input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 – clock.
I/O
O
O
EBI read enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
94
95
AVSS
P
A
MFP0
MFP0
Ground pin for digital circuit.
VREF
Voltage reference input for ADC.
Note: This pin needs to be connected with
0.1uF/10uF capacitors.
96
97
AVDD
PE.8
P
MFP0
MFP0
Power supply for internal analog circuit.
General purpose digital I/O pin.
I/O
June 16, 2016
Page 53 of 228
Rev 1.09
NUC442
ADC1_0
A
A
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
ADC1 analog input.
ADC0_8
ADC0 analog input.
ACMP1_N
TM1_CNT_OUT
SD0_DAT3
EBI_ALE
HS
A
Analog comparator1 negative input pin.
Timer1 event counter input/toggle output.
SD mode #0 data line bit 3.
I/O
I/O
O
EBI address latch enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
98
PE.9
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_1
ADC0_9
ACMP1_P0
SD0_DAT2
EBI_nWRH
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
SD mode #0 data line bit 2.
EBI write enable output pin.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
99
PE.10
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_2
ADC0_10
ACMP1_P1
SPI0_MISO1
SD0_DAT1
EBI_nWRL
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
100
PE.11
I/O
A
MFP0
MPF1
MPF1
MPF2
General purpose digital I/O pin.
ADC1 analog input.
ADC1_3
ADC0_11
ACMP1_P2
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
June 16, 2016
Page 54 of 228
Rev 1.09
NUC442
SPI0_MOSI1
SD0_DAT0
ACMP2_P3
EBI_nCS0
HS
I/O
I/O
A
MPF3
MPF4
MPF5
MPF7
Slew
2nd SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
Analog comparator2 positive input pin.
EBI chip select 0 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin;
June 16, 2016
Page 55 of 228
Rev 1.09
NUC442
4.3.3 NuMicro NUC442 Package LQFP 128-pin Description
MFP = Multi-function pin.
Pin No.
Pin Name
PE.12
Type
I/O
A
MFP*
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
Description
1
General purpose digital I/O pin.
ADC1 analog input.
ADC1_4
ACMP1_P3
ACMP2_P2
EBI_nCS1
HS
A
Analog comparator1 positive input pin.
Analog comparator2 positive input pin.
EBI chip select 1 enable output pin.
A
O
This pad is embedded with “Slew Rate Control”
capability.
2
PE.13
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_5
ACMP2_P1
EBI_nCS2
HS
A
Analog comparator2 positive input pin.
EBI chip select 2 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
3
PE.14
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_6
ACMP2_P0
EBI_nCS3
HS
A
Analog comparator2 positive input pin.
EBI chip select 3 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
4
5
PE.15
I/O
A
MFP0
MPF1
MPF3
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_7
ACMP2_N
PF.9
A
Analog comparator2 negative input pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM0_0 output/capture input.
I/O
I/O
I/O
OPA0_P
PWM0_0
HS
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 56 of 228
Rev 1.09
NUC442
6
PF.10
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM0_1 output/capture input.
OPA0_N
PWM0_1
HS
This pad is embedded with “Slew Rate Control”
capability.
7
8
PF.11
I/O
O
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MFP0
General purpose digital I/O pin.
Operational amplifier output pin
Request to Send output pin for UART1.
General purpose digital I/O pin.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
General purpose digital I/O pin.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Operational amplifier output pin
Data receiver input pin for UART1.
Ground pin for digital circuit.
OPA0_O
UART1_RTS
PF.12
O
I/O
I/O
I
OPA1_P
UART1_CTS
PF.13
9
I/O
I/O
O
OPA1_N
UART1_TXD
PF.14
10
I/O
O
OPA1_O
UART1_RXD
VSS
I
11
12
P
VDD
P
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
13
PC.12
I/O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
1st SPI1 slave select pin..
SmartCard4 card detect pin.
SD mode #1 – card detect
Image data input bus bit 7.
EBI address bus bit0.
SPI1_SS0
SC4_CD
SD1_CDn
CAP_DATA7
EBI_A0
I/O
I
I
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
14
PC.13
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 57 of 228
Rev 1.09
NUC442
SPI1_MOSI1
SC4_RST
SD1_CMD
CAP_DATA6
EBI_A1
I/O
O
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
2nd SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 reset pin.
I/O
I
SD mode #1 – command/response
Image data input bus bit 6.
O
EBI address bus bit1.
HS
This pad is embedded with “Slew Rate Control”
capability.
15
PC.14
I/O
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 power pin.
SPI1_MISO1
SC4_PWR
TM3_EXT
SD1_CLK
CAP_DATA5
EBI_A2
Timer3 external counter input
SD mode #1– clock.
O
I
Image data input bus bit 5.
EBI address bus bit2.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
16
PC.15
I/O
I/O
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 data pin.
SPI1_MOSI0
SC4_DAT
SD1_DAT3
CAP_DATA4
EBI_A3
SD mode #1 data line bit 3.
Image data input bus bit 4.
EBI address bus bit3.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
17
PD.0
I/O
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 clock pin.
SPI1_MISO0
SC4_CLK
SD1_DAT2
CAP_DATA3
I/O
I
SD mode #1 data line bit 2;
Image data input bus bit 3.
June 16, 2016
Page 58 of 228
Rev 1.09
NUC442
EBI_A4
INT3
HS
O
I
MPF7
MPF8
Slew
EBI address bus bit4.
External interrupt3 input pin.
This pad is embedded with “Slew Rate Control”
capability.
18
19
20
PD.1
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
TM0_CNT_OUT
SD1_DAT1
CAP_DATA2
EBI_A5
I/O
I/O
I
Timer0 event counter inpu/toggle output.
SD mode #1 data line bit 1.
Image data input bus bit 2.
EBI address bus bit5.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
PD.2
I/O
A
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
ADC analog input.
STADC
I2C3_SCL
SD1_DAT0
CAP_DATA1
EBI_A6
HS
I/O
I/O
I
I2C3 clock pin.
SD mode #1 data line bit 0.
Image data input bus bit 1.
EBI address bus bit6.
O
This pad is embedded with “Slew Rate Control”
capability.
PD.3
I/O
O
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 clock pin.
SC5_CLK
I2C3_SDA
ACMP2_O
SD0_CDn
CAP_DATA0
EBI_A7
I2C3 data input/output pin.
Analog comparator2 output .
SD mode #0 – card detect
Image data input bus bit 0.
EBI address bus bit7.
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
21
PD.4
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 59 of 228
Rev 1.09
NUC442
SC5_CD
UART3_RXD
ACMP1_O
CAP_SCLK
EBI_A8
I
MPF1
MPF2
MPF3
MPF5
MPF7
Slew
SmartCard5 card detect pin.
Data receiver input pin for UART3.
Analog comparator1 output .
Image capture interface sensor clock pin.
EBI address bus bit8.
I
O
O
O
HS
This pad is embedded with “Slew Rate Control”
capability.
22
PD.5
I/O
O
O
I
MFP0
MPF1
MPF2
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 reset pin.
SC5_RST
UART3_TXD
CAP_VSYNC
EBI_A9
Data transmitter output pin for UART3.
Image capture interface VSYNC input pin.
EBI address bus bit9.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
23
PD.6
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 power pin.
SC5_PWR
UART3_RTS
SD0_CMD
CAP_HSYNC
EBI_A10
HS
O
Request to Send output pin for UART3.
SD mode #0 – command/response
Image capture interface HSYNC input pin.
EBI address bus bit10.
I/O
I
O
This pad is embedded with “Slew Rate Control”
capability.
24
PD.7
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 data pin.
SC5_DAT
UART3_CTS
SD0_CLK
CAP_PIXCLK
EBI_A11
HS
Clear to Send input pin for UART3.
SD mode #0 – clock.
O
I
Image capture interface pix clock input pin.
EBI address bus bit11.
O
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 60 of 228
Rev 1.09
NUC442
25
26
PG.13
I/O
I
MFP0
MPF1
MFP0
MPF1
General purpose digital I/O pin.
XT1_IN
PG.12
External 4~24 MHz (high-speed) crystal input pin.
General purpose digital I/O pin.
I/O
O
XT1_OUT
External 4~24 MHz (high-speed) crystal output
pin.
27
28
nRESET
I
MFP0
MFP0
External reset input: active LOW, with an internal
pull-up. Set this pin low reset to initial state.
LDO_CAP
P
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
29
30
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
31
32
33
PG.10
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
MPF1
MPF3
MFP0
MPF1
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal input pin.
I2C1 clock pin.
ICE_CLK
PG.11
I/O
I/O
I/O
I
ICE_DAT
PG.15
X32K_IN
I2C1_SCL
PG.14
I/O
I/O
O
34
General purpose digital I/O pin.
X32K_OUT
External 32.768 kHz (low-speed) crystal output
pin.
I2C1_SDA
VBAT
I/O
P
MPF3
MFP0
MFP0
MPF1
MPF2
MPF3
MPF8
MFP0
I2C1 data input/output pin.
Battery power input pin.
35
36
PA.0
I/O
I/O
I
General purpose digital I/O pin.
Tamper detect pin 0.
TAMPER0
SC0_CD
CAN1_RXD
INT0
SmartCard0 card detect pin.
CAN bus receiver1 input.
External interrupt0 input pin.
General purpose digital I/O pin.
I
I
37
PA.1
I/O
June 16, 2016
Page 61 of 228
Rev 1.09
NUC442
TAMPER1
SC5_CD
CAN1_TXD
EBI_A22
PD.8
I/O
I
MPF1
MPF2
MPF3
MPF7
MFP0
MPF1
MPF2
Slew
Tamper detect pin 1.
SmartCard5 card detect pin.
CAN bus transmitter1 input.
EBI address bus bit22.
I
O
38
39
40
I/O
I/O
I/O
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
I2C0 clock pin.
SPI3_MISO1
I2C0_SCL
HS
This pad is embedded with “Slew Rate Control”
capability.
PD.9
I/O
I/O
I/O
MFP0
MPF1
MPF2
Slew
General purpose digital I/O pin.
2nd SPI3 MOSI (Master Out, Slave In) pin.
I2C0 data input/output pin.
SPI3_MOSI1
I2C0_SDA
HS
This pad is embedded with “Slew Rate Control”
capability.
PA.2
I/O
I/O
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard2 data pin.
SC2_DAT
SPI3_MISO0
I2S0_MCLK
BRAKE11
CAP_SFIELD
EBI_A12
HS
1st SPI3 MISO (Master In, Slave Out) pin.
I2S0 master clock output pin.
Brake input pin 1 of EPWM0_.
Video input interface SFIELD input pin.
EBI address bus bit12.
I
I
O
This pad is embedded with “Slew Rate Control”
capability.
41
PA.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
General purpose digital I/O pin.
SmartCard2 clock pin.
SC2_CLK
SPI3_MOSI0
I2S0_DO
BRAKE10
EBI_A13
I/O
O
1st SPI3 MOSI (Master Out, Slave In) pin.
I2S0 data output.
I
Brake input pin 0 of EPWM0_.
EBI address bus bit13.
O
June 16, 2016
Page 62 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
42
PA.4
I/O
O
O
I
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 power pin.
SC2_PWR
SPI3_CLK
I2S0_DI
QEI1_Z
EBI_A14
ECAP1_IC2
HS
SPI3 serial clock pin.
I2S0 data input.
I
Quadrature encoder phase Z input of QEI Unit 1.
EBI address bus bit14.
O
I
Input 2 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
43
PA.5
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 reset pin.
SC2_RST
SPI3_SS0
I2S0_BCLK
PWM0_0
QEI1_B
I/O
O
General purpose digital I/O pin.
I2S0 bit clock pin.
I/O
I
PWM0_0 output/capture input.
Quadrature encoder phase B input of QEI Unit 1.
EBI address bus bit15.
EBI_A15
ECAP1_IC1
HS
O
I
Input 1 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
44
PA.6
I/O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8
General purpose digital I/O pin.
SmartCard2 card detect pin.
SC2_CD
I2S0_LRCK
PWM0_1
QEI1_A
I
O
I/O
I
I2S0 left right channel clock.
PWM0_1 output/capture input.
Quadrature encoder phase A input of QEI Unit 1.
CAN bus transmitter1 input.
CAN1_TXD
EBI_A16
ECAP1_IC0
I
O
I
EBI address bus bit16.
Input 0 of enhanced capture unit 1.
June 16, 2016
Page 63 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
45
VDD
P
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
46
47
VSS
P
MFP0
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
Ground pin for digital circuit.
General purpose digital I/O pin.
SmartCard0 clock pin.
PA.7
I/O
O
SC0_CLK
SPI3_SS0
PWM1_3
EPWM0_5
EBI_A17
HS
I/O
I/O
I/O
O
General purpose digital I/O pin.
PWM1_3 output/capture input.
PWM0_5 output/capture input.
EBI address bus bit17.
This pad is embedded with “Slew Rate Control”
capability.
48
49
50
PA.8
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 reset pin.
SC0_RST
SPI3_CLK
PWM1_2
EPWM0_4
EBI_A18
HS
O
SPI3 serial clock pin.
I/O
I/O
O
PWM1_2 output/capture input.
PWM0_4 output/capture input.
EBI address bus bit18.
This pad is embedded with “Slew Rate Control”
capability.
PA.9
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 power pin.
SC0_PWR
SPI3_MISO0
PWM1_1
EPWM0_3
EBI_A19
HS
I/O
I/O
I/O
O
1st SPI3 MISO (Master In, Slave Out) pin.
PWM1_1 output/capture input.
PWM0_3 output/capture input.
EBI address bus bit19.
This pad is embedded with “Slew Rate Control”
capability.
PA.10
I/O
I/O
MFP0
MPF2
General purpose digital I/O pin.
SmartCard0 data pin.
SC0_DAT
June 16, 2016
Page 64 of 228
Rev 1.09
NUC442
SPI3_MOSI0
PWM1_0
EPWM0_2
EBI_A20
HS
I/O
I/O
I/O
O
MPF3
MPF4
MPF5
MPF7
Slew
1st SPI3 MOSI (Master Out, Slave In) pin.
PWM1_0 output/capture input.
PWM0_2 output/capture input.
EBI address bus bit20.
This pad is embedded with “Slew Rate Control”
capability.
51
PA.11
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART0.
2nd SPI3 MISO (Master In, Slave Out) pin.
PWM0_5 output/capture input.
PWM0_1 output/capture input.
EBI address/data bus bit 0.
UART0_RTS
SPI3_MISO1
PWM0_5
EPWM0_1
EBI_AD0
HS
I/O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
52
PA.12
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART0.
2nd SPI3 MOSI (Master Out, Slave In) pin.
PWM0_4 output/capture input.
PWM0_0 output/capture input.
EBI address/data bus bit 1.
UART0_CTS
SPI3_MOSI1
PWM0_4
EPWM0_0
EBI_AD1
HS
I/O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
53
PA.13
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART0.
SmartCard3 data pin.
UART0_RXD
SC3_DAT
PWM1_4
EBI_AD2
HS
I/O
I/O
O
PWM1_4 output/capture input.
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
54
PA.14
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 65 of 228
Rev 1.09
NUC442
UART0_TXD
SC3_CLK
PWM1_5
EBI_AD3
HS
O
O
MPF1
MPF3
MPF4
MPF7
Slew
Data transmitter output pin for UART0.
SmartCard3 clock pin.
I/O
O
PWM1_5 output/capture input.
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
55
56
57
58
PD.10
I/O
I/O
I/O
I/O
O
MFP0
MPF1
MPF2
MFP0
MPF1
MPF3
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
SmartCard3 data pin.
SC3_DAT
I2C4_SCL
PD.11
I2C4 clock pin.
General purpose digital I/O pin.
SmartCard3 reset pin.
SC3_RST
TM3_CNT_OUT
PD.12
I/O
I/O
O
Timer3 event counter input//toggle output.
General purpose digital I/O pin.
SmartCard3 clock pin.
SC3_CLK
I2C4_SDA
PA.15
I/O
I/O
O
I2C4 data input/output pin.
General purpose digital I/O pin.
SmartCard3 power pin.
SC3_PWR
UART2_RTS
I2C0_SCL
EBI_A21
HS
O
Request to Send output pin for UART2.
I2C0 clock pin.
I/O
O
EBI address bus bit21.
This pad is embedded with “Slew Rate Control”
capability.
59
PC.9
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF6
General purpose digital I/O pin.
ADC analog input.
STADC
UART2_CTS
SC3_RST
I2C0_SDA
CAP_DATA1
I2C3_SCL
I
Clear to Send input pin for UART2.
SmartCard3 reset pin.
O
I/O
I
I2C0 data input/output pin.
Image data input bus bit 1.
I2C3 clock pin.
I/O
June 16, 2016
Page 66 of 228
Rev 1.09
NUC442
EBI_A22
SD1_DAT0
EBI_A6
HS
O
I/O
O
MPF7
MPF8
MPF9
Slew
EBI address bus bit22.
SD mode #1 data line bit 0.
EBI address bus bit6.
This pad is embedded with “Slew Rate Control”
capability.
60
PC.10
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
SmartCard3 card detect pin.
Data receiver input pin for UART2.
PWM0_2 output/capture input.
EBI address bus bit23.
SC3_CD
UART2_RXD
PWM0_2
EBI_A23
EBI_AD2
HS
I
I/O
O
O
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
61
PC.11
I/O
O
MFP0
MPF2
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART2.
PWM0_3 output/capture input.
EBI address bus bit24.
UART2_TXD
PWM0_3
EBI_A24
EBI_AD3
HS
I/O
O
O
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
62
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
63
64
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
65
PD.13
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
1st SPI1 slave select pin..
SPI1_SS0
UART5_CTS
ECAP0_IC2
HS
Clear to Send input pin for UART5.
Input 2 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 67 of 228
Rev 1.09
NUC442
66
67
68
69
PD.14
I/O
O
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
UART5_RTS
ECAP0_IC1
HS
O
Request to Send output pin for UART5.
Input 1 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
PD.15
I/O
I/O
O
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
SPI1_MISO0
UART5_TXD
ECAP0_IC0
HS
1st SPI1 MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART5.
Input 0 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
PF.0
I/O
MFP0
MPF1
MPF2
MPF8
Slew
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART5.
External interrupt5 input pin.
SPI1_MOSI0
UART5_RXD
INT5
I/O
I
I
HS
This pad is embedded with “Slew Rate Control”
capability.
VRES
A
MFP0
USB PHY VRES ground input pin. Add an 8.2K
ohm resistor to VSSA.
70
71
VBUS
A
P
MFP0
MFP0
USB PHY VBUS power input pin.
USB_VDD33_CAP
Internal power regulator output 3.3V decoupling
pin.
72
VSSA
P
MFP0
Ground pin for digital circuit. Add a Feritte Bead to
digital ground VSS
.
73
74
75
76
USB0_D-
A
A
MFP0
MFP0
MFP0
MFP0
MPF1
MPF2
USB0 differential signal D-.
USB0 differential signal D+.
USB0 OTG ID pin.
USB0_D+
USB0_OTG_ID
PB.0
I
I/O
I
General purpose digital I/O pin.
USB0 external VBUS regulator status
I2C4 clock pin.
USB0_OTG5V_ST
I2C4_SCL
I/O
June 16, 2016
Page 68 of 228
Rev 1.09
NUC442
INT1
I
MPF8
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
Slew
External interrupt1 input pin.
77
PB.1
I/O
O
General purpose digital I/O pin.
USB0 external VBUS regulator enable
I2C4 data input/output pin.
USB0_OTG5V_EN
I2C4_SDA
TM1_CNT_OUT
PF.1
I/O
I/O
I/O
I/O
Timer1 event counter input/toggle output.
General purpose digital I/O pin.
2nd SPI2 MOSI (Master Out, Slave In) pin.
78
79
SPI2_MOSI1
HS
This pad is embedded with “Slew Rate Control”
capability.
PB.2
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
USB1 differential signal D-.
UART1_RXD
SPI2_SS0
USB1_D-
EBI_AD4
HS
I/O
A
O
EBI address/data bus bit 4.
This pad is embedded with “Slew Rate Control”
capability.
80
PB.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI2 serial clock pin.
UART1_TXD
SPI2_CLK
USB1_D+
EBI_AD5
HS
O
A
USB1 differential signal D+.
EBI address/data bus bit 5.
O
This pad is embedded with “Slew Rate Control”
capability.
81
PB.4
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
General purpose digital I/O pin.
UART1_RTS
SPI2_MISO0
UART4_RXD
TM0_CNT_OUT
EBI_AD6
Request to Send output pin for UART1.
1st SPI2 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART4.
Timer0 event counter input/toggle output.
EBI address/data bus bit 6.
I/O
I
I/O
O
June 16, 2016
Page 69 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
82
PB.5
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART1.
1st SPI2 MOSI (Master Out, Slave In) pin.
Data transmitter output pin for UART4.
EBI address/data bus bit 7.
UART1_CTS
SPI2_MOSI0
UART4_TXD
EBI_AD7
HS
I/O
O
O
This pad is embedded with “Slew Rate Control”
capability.
83
PB.6
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2C2 clock pin.
I2C2_SCL
BRAKE01
UART4_RTS
PWM1_4
EPWM1_0
EBI_AD8
HS
Brake input pin 1 of EPWMB.
Request to Send output pin for UART4.
PWM1_4 output/capture input.
PWM1_0 output/capture input.
EBI address/data bus bit 8.
O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
84
PB.7
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2C2 data input/output pin.
I2C2_SDA
BRAKE00
UART4_CTS
PWM1_5
EPWM1_1
EBI_AD9
HS
Brake input pin 0 of EPWMB.
Clear to Send input pin for UART4.
PWM1_5 output/capture input.
PWM1_1 output/capture input.
EBI address/data bus bit 9.
I
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
85
PB.8
I/O
I
MFP0
MPF1
MPF5
General purpose digital I/O pin.
Clear to Send input pin for UART5.
PWM1_2 output/capture input.
UART5_CTS
EPWM1_2
I/O
June 16, 2016
Page 70 of 228
Rev 1.09
NUC442
EBI_AD10
HS
O
MPF7
Slew
EBI address/data bus bit 10.
This pad is embedded with “Slew Rate Control”
capability.
86
87
88
89
PB.9
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART5.
PWM1_3 output/capture input.
EBI address/data bus bit 11.
UART5_RTS
EPWM1_3
EBI_AD11
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.10
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART5.
PWM1_4 output/capture input.
EBI address/data bus bit 12.
UART5_TXD
EPWM1_4
EBI_AD12
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.11
I/O
I
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART5.
PWM1_5 output/capture input.
EBI address/data bus bit 13.
UART5_RXD
EPWM1_5
EBI_AD13
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.12
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART4.
2nd SPI2 MISO (Master In, Slave Out) pin.
CAN bus receiver0 input.
UART4_RTS
SPI2_MISO1
CAN0_RXD
EBI_AD14
HS
I/O
I
O
EBI address/data bus bit 14.
This pad is embedded with “Slew Rate Control”
capability.
90
PB.13
I/O
I
MFP0
MPF1
MPF2
General purpose digital I/O pin.
UART4_CTS
SPI2_MOSI1
Clear to Send input pin for UART4.
2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O
June 16, 2016
Page 71 of 228
Rev 1.09
NUC442
CAN0_TXD
EBI_AD15
HS
I
MPF3
MPF7
Slew
CAN bus transmitter0 input.
EBI address/data bus bit 15.
O
This pad is embedded with “Slew Rate Control”
capability.
91
92
93
PB.14
I/O
O
O
I
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
I2S1 master clock output pin.
SmartCard1 reset pin.
I2S1_MCLK
SC1_RST
BRAKE01
HS
Brake input pin 1 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
PB.15
I/O
O
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_DAT
BRAKE00
HS
I/O
I
SmartCard1 data pin.
Brake input pin 0 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
VDD
P
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
94
95
VSS
P
I/O
I
MFP0
MFP0
MPF1
MPF2
MPF3
MPF7
MPF8
Slew
Ground pin for digital circuit.
General purpose digital I/O pin.
I2S1 data input.
PC.0
I2S1_DI
SC1_DAT
UART4_RXD
EBI_MCLK
INT2
I/O
I
SmartCard1 data pin.
Data receiver input pin for UART4.
EBI interface clock output pin.
External interrupt2 input pin.
O
I
HS
This pad is embedded with “Slew Rate Control”
capability.
96
PC.1
I/O
O
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
I2S1 bit clock pin.
I2S1_BCLK
SC1_CLK
UART4_TXD
O
SmartCard1 clock pin.
O
Data transmitter output pin for UART4.
June 16, 2016
Page 72 of 228
Rev 1.09
NUC442
TM3_CNT_OUT
EBI_AD13
HS
I/O
O
MPF5
MPF7
Slew
Timer3 event counter input/toggle output.
EBI address/data bus bit 13.
This pad is embedded with “Slew Rate Control”
capability.
97
PC.2
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
I2S1 left right channel clock.
SmartCard1 power pin.
I2S1_LRCK
SC1_PWR
UART4_RTS
SPI0_SS0
EBI_AD12
HS
O
O
Request to Send output pin for UART4.
General purpose digital I/O pin.
EBI address/data bus bit 12.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
98
PC.3
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1_MCLK
SC1_CD
UART4_CTS
SPI0_MISO1
QEI0_Z
I2S1 master clock output pin.
SmartCard1 card detect pin.
I
Clear to Send input pin for UART4.
2nd SPI0 MISO (Master In, Slave Out) pin.
Quadrature encoder phase Z input of QEI Unit 0.
EBI address/data bus bit 11.
I/O
I
EBI_AD11
ECAP0_IC2
HS
O
O
Input 2 of enhanced capture unit 0.
This pad is embedded with “Slew Rate Control”
capability.
99
PC.4
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
MPF8
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_RST
SPI0_MOSI1
QEI0_B
O
SmartCard1 reset pin.
I/O
I
2nd SPI0 MOSI (Master Out, Slave In) pin.
Quadrature encoder phase B input of QEI Unit 0.
EBI address/data bus bit 10.
EBI_AD10
ECAP0_IC1
O
O
Input 1 of enhanced capture unit 0.
June 16, 2016
Page 73 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
100
101
102
PC.5
I/O
O
I
MFP0
MFP1
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
Clock Output Pin.
CLKO
QEI0_A
EBI_MCLK
ECAP0_IC0
HS
Quadrature encoder phase A input of QEI Unit 0.
EBI interface clock output pin.
Input 0 of enhanced capture unit 0.
O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.6
I/O
I
MFP0
MPF1
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Timer2 external counter input
TM2_EXT
SPI0_MISO0
TM2_CNT_OUT
EBI_AD9
HS
I/O
I/O
O
1st SPI0 MISO (Master In, Slave Out) pin.
Timer2 event counter input/toggle output.
EBI address/data bus bit 9.
This pad is embedded with “Slew Rate Control”
capability.
PC.7
I/O
I
MFP0
MPF1
MPF4
MPF7
Slew
General purpose digital I/O pin.
Timer1 external counter input
TM1_EXT
SPI0_MOSI0
EBI_AD8
HS
I/O
O
1st SPI0 MOSI (Master Out, Slave In) pin.
EBI address/data bus bit 8.
This pad is embedded with “Slew Rate Control”
capability.
103
PC.8
I/O
I
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Timer0 external counter input
SPI0 serial clock pin.
TM0_EXT
SPI0_CLK
HS
O
This pad is embedded with “Slew Rate Control”
capability.
104
PF.2
I/O
I/O
I/O
MFP0
MPF1
MPF4
General purpose digital I/O pin.
General purpose digital I/O pin.
SD mode #0 data line bit 3.
SPI3_SS0
SD0_DAT3
June 16, 2016
Page 74 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
105
106
107
108
109
110
PF.3
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
SPI3 serial clock pin.
SD mode #0 data line bit 2.
SPI3_CLK
SD0_DAT2
HS
I/O
This pad is embedded with “Slew Rate Control”
capability.
PF.4
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
1st SPI3 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
SPI3_MISO0
SD0_DAT1
HS
This pad is embedded with “Slew Rate Control”
capability.
PF.5
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
1st SPI3 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
SPI3_MOSI0
SD0_DAT0
HS
This pad is embedded with “Slew Rate Control”
capability.
PF.6
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Data receiver input pin for UART2.
SD mode #0 – card detect
UART2_RXD
SD0_CDn
HS
I
I
This pad is embedded with “Slew Rate Control”
capability.
PF.7
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
UART2_TXD
SD0_CMD
HS
Data transmitter output pin for UART2.
SD mode #0 – command/response
I/O
This pad is embedded with “Slew Rate Control”
capability.
PF.8
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Request to Send output pin for UART2.
SD mode #0 – clock.
UART2_RTS
SD0_CLK
HS
O
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 75 of 228
Rev 1.09
NUC442
111
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
112
113
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
114
115
116
PE.0
I/O
A
MFP0
MPF1
MPF8
MFP0
MPF1
MPF3
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_0
INT4
I
External interrupt4 input pin.
General purpose digital I/O pin.
ADC0 analog input.
PE.1
I/O
A
ADC0_1
TM2_CNT_OUT
PE.2
I/O
I/O
A
Timer2 event counter input/toggle output.
General purpose digital I/O pin.
ADC0 analog input.
ADC0_2
ACMP0_O
SPI0_MISO0
HS
O
Analog comparator0 output .
1st SPI0 MISO (Master In, Slave Out) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
117
118
119
PE.3
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_3
ACMP0_P3
SPI0_MOSI0
HS
A
Analog comparator0 positive input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
PE.4
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_4
ACMP0_P2
SPI0_SS0
HS
A
Analog comparator0 positive input pin.
General purpose digital I/O pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
PE.5
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 76 of 228
Rev 1.09
NUC442
ADC0_5
ACMP0_P1
SPI0_CLK
SD0_CDn
HS
A
A
O
I
MPF1
MPF2
MPF3
MPF4
Slew
ADC0 analog input.
Analog comparator0 positive input pin.
SPI0 serial clock pin.
SD mode #0 – card detect
This pad is embedded with “Slew Rate Control”
capability.
120
PE.6
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_6
ACMP0_P0
SPI0_MISO0
SD0_CMD
EBI_nWR
HS
A
Analog comparator0 positive input pin.
1st SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 – command/response
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
121
PE.7
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_7
ACMP0_N
SPI0_MOSI0
SD0_CLK
EBI_nRD
HS
A
Analog comparator0 negative input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0– clock.
I/O
O
O
EBI read enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
122
123
AVSS
P
A
MFP0
MFP0
Ground pin for digital circuit.
VREF
Voltage reference input for ADC.
Note: This pin needs to be connected with
0.1uF/10uF capacitors.
124
125
AVDD
P
I/O
A
MFP0
MFP0
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC1 analog input.
PE.8
ADC1_0
ADC0_8
ACMP1_N
MPF1
A
MPF1
ADC0 analog input.
A
MPF2
Analog comparator1 negative input pin.
Rev 1.09
June 16, 2016
Page 77 of 228
NUC442
TM1_CNT_OUT
SD0_DAT3
EBI_ALE
HS
I/O
I/O
O
MPF3
MPF4
MPF7
Slew
Timer1 event counter input/toggle output.
SD mode #0 data line bit 3.
EBI address latch enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
126
PE.9
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_1
ADC0_9
ACMP1_P0
SD0_DAT2
EBI_nWRH
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
SD mode #0 data line bit 2.
EBI write enable output pin.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
127
PE.10
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_2
ADC0_10
ACMP1_P1
SPI0_MISO1
SD0_DAT1
EBI_nWRL
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
128
PE.11
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF5
General purpose digital I/O pin.
ADC1 analog input.
ADC1_3
ADC0_11
ACMP1_P2
SPI0_MOSI1
SD0_DAT0
ACMP2_P3
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
I/O
I/O
A
Analog comparator2 positive input pin.
June 16, 2016
Page 78 of 228
Rev 1.09
NUC442
EBI_nCS0
HS
O
MPF7
Slew
EBI chip select 0 enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin;
June 16, 2016
Page 79 of 228
Rev 1.09
NUC442
4.3.4 NuMicro NUC442 Package LQFP 144-pin Description
MFP = Multi-function pin.
Pin No.
Pin Name
PE.12
Type
I/O
A
MFP*
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
Description
1
General purpose digital I/O pin.
ADC1 analog input.
ADC1_4
ACMP1_P3
ACMP2_P2
EBI_nCS1
HS
A
Analog comparator1 positive input pin.
Analog comparator2 positive input pin.
EBI chip select 1 enable output pin.
A
O
This pad is embedded with “Slew Rate Control”
capability.
2
PE.13
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_5
ACMP2_P1
EBI_nCS2
HS
A
Analog comparator2 positive input pin.
EBI chip select 2 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
3
PE.14
I/O
A
MFP0
MPF1
MPF3
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_6
ACMP2_P0
EBI_nCS3
HS
A
Analog comparator2 positive input pin.
EBI chip select 3 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
4
5
PE.15
I/O
A
MFP0
MPF1
MPF3
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_7
ACMP2_N
PF.9
A
Analog comparator2 negative input pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM0_0 output/capture input.
I/O
I/O
I/O
OPA0_P
PWM0_0
HS
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 80 of 228
Rev 1.09
NUC442
6
PF.10
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM0_1 output/capture input.
OPA0_N
PWM0_1
HS
This pad is embedded with “Slew Rate Control”
capability.
7
8
PF.11
I/O
O
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MFP0
MFP0
General purpose digital I/O pin.
Operational amplifier output pin
Request to Send output pin for UART1.
General purpose digital I/O pin.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
General purpose digital I/O pin.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Operational amplifier output pin
Data receiver input pin for UART1.
Ground pin for digital circuit.
OPA0_O
UART1_RTS
PF.12
O
I/O
I/O
I
OPA1_P
UART1_CTS
PF.13
9
I/O
I/O
O
OPA1_N
UART1_TXD
PF.14
10
I/O
O
OPA1_O
UART1_RXD
VSS
I
11
12
P
VDD
P
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
13
14
PF.15
I/O
O
MFP0
MPF1
MFP0
MPF1
MPF8
MFP0
MPF1
MFP0
MPF1
General purpose digital I/O pin.
Request to Send output pin for UART0.
General purpose digital I/O pin.
Clear to Send input pin for UART0.
External interrupt6 input pin.
UART0_RTS
PG.0
I/O
I
UART0_CTS
INT6
I
15
16
PG.1
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
UART0_RXD
PG.2
I/O
O
UART0_TXD
June 16, 2016
Page 81 of 228
Rev 1.09
NUC442
17
18
19
PC.12
I/O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
1st SPI1 slave select pin..
SmartCard4 card detect pin.
SD mode #1 – card detect
Image data input bus bit 7.
EBI address bus bit0.
SPI1_SS0
SC4_CD
SD1_CDn
CAP_DATA7
EBI_A0
I/O
I
I
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
PC.13
I/O
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
2nd SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 reset pin.
SPI1_MOSI1
SC4_RST
SD1_CMD
CAP_DATA6
EBI_A1
I/O
I
SD mode #1 – command/response
Image data input bus bit 6.
O
EBI address bus bit1.
HS
This pad is embedded with “Slew Rate Control”
capability.
PC.14
I/O
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 power pin.
SPI1_MISO1
SC4_PWR
TM3_EXT
SD1_CLK
CAP_DATA5
EBI_A2
Timer3 external counter input
SD mode #1– clock.
O
I
Image data input bus bit 5.
EBI address bus bit2.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
20
PC.15
I/O
I/O
I/O
I/O
MFP0
MPF1
MPF2
MPF4
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
SmartCard4 data pin.
SPI1_MOSI0
SC4_DAT
SD1_DAT3
SD mode #1 data line bit 3;
June 16, 2016
Page 82 of 228
Rev 1.09
NUC442
CAP_DATA4
EBI_A3
HS
I
MPF5
MPF7
Slew
Image data input bus bit 4.
EBI address bus bit3.
O
This pad is embedded with “Slew Rate Control”
capability.
21
PD.0
I/O
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
SmartCard4 clock pin.
SPI1_MISO0
SC4_CLK
SD1_DAT2
CAP_DATA3
EBI_A4
I/O
I
SD mode #1 data line bit 2;
Image data input bus bit 3.
EBI address bus bit4.
O
INT3
I
External interrupt3 input pin.
HS
This pad is embedded with “Slew Rate Control”
capability.
22
23
24
PD.1
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
TM0_CNT_OUT
SD1_DAT1
CAP_DATA2
EBI_A5
I/O
I/O
I
Timer0 event counter input/toggle output.
SD mode #1 data line bit 1;
Image data input bus bit 2.
EBI address bus bit5.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
PD.2
I/O
A
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
ADC analog input.
STADC
I2C3_SCL
SD1_DAT0
CAP_DATA1
EBI_A6
HS
I/O
I/O
I
I2C3 clock pin.
SD mode #1 data line bit 0.
Image data input bus bit 1.
EBI address bus bit6.
O
This pad is embedded with “Slew Rate Control”
capability.
PD.3
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 83 of 228
Rev 1.09
NUC442
SC5_CLK
I2C3_SDA
ACMP2_O
SD0_CDn
CAP_DATA0
EBI_A7
O
I/O
O
I
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
SmartCard5 clock pin.
I2C3 data input/output pin.
Analog comparator2 output .
SD mode #0 – card detect
Image data input bus bit 0.
EBI address bus bit7.
I
O
HS
This pad is embedded with “Slew Rate Control”
capability.
25
PD.4
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 card detect pin.
Data receiver input pin for UART3.
Analog comparator1 output.
SC5_CD
UART3_RXD
ACMP1_O
CAP_SCLK
EBI_A8
I
O
O
O
Image capture interface sensor clock pin.
EBI address bus bit8.
HS
This pad is embedded with “Slew Rate Control”
capability.
26
PD.5
I/O
O
O
I
MFP0
MPF1
MPF2
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 reset pin.
SC5_RST
UART3_TXD
CAP_VSYNC
EBI_A9
Data transmitter output pin for UART3.
Image capture interface VSYNC input pin.
EBI address bus bit9.
O
HS
This pad is embedded with “Slew Rate Control”
capability.
27
PD.6
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
General purpose digital I/O pin.
SmartCard5 power pin.
SC5_PWR
UART3_RTS
SD0_CMD
CAP_HSYNC
EBI_A10
O
Request to Send output pin for UART3.
SD mode #0 – command/response
Image capture interface HSYNC input pin.
EBI address bus bit10.
I/O
I
O
June 16, 2016
Page 84 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
28
PD.7
I/O
I/O
I
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard5 data pin.
SC5_DAT
UART3_CTS
SD0_CLK
CAP_PIXCLK
EBI_A11
HS
Clear to Send input pin for UART3.
SD mode #0 – clock.
O
I
Image capture interface pix clock input pin.
EBI address bus bit11.
O
This pad is embedded with “Slew Rate Control”
capability.
29
30
PG.13
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
General purpose digital I/O pin.
XT1_IN
PG.12
External 4~24 MHz (high-speed) crystal input pin.
General purpose digital I/O pin.
I/O
O
I
XT1_OUT
nRESET
External 4~24 MHz (high-speed) crystal output pin.
31
32
External reset input: active LOW, with an internal
pull-up. Set this pin low reset to initial state.
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
33
34
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
35
36
37
PG.10
I/O
I
MFP0
MPF1
MFP0
MPF1
MFP0
MPF1
MPF3
MFP0
MPF1
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal input pin.
I2C1 clock pin.
ICE_CLK
PG.11
I/O
I/O
I/O
I
ICE_DAT
PG.15
X32K_IN
I2C1_SCL
PG.14
I/O
I/O
O
38
General purpose digital I/O pin.
External 32.768 kHz (low-speed) crystal output pin.
X32K_OUT
June 16, 2016
Page 85 of 228
Rev 1.09
NUC442
I2C1_SDA
VBAT
I/O
P
MPF3
MFP0
MFP0
MPF1
MPF2
MPF3
MPF8
MFP0
MPF1
MPF2
MPF3
MPF7
MFP0
MPF1
MPF2
Slew
I2C1 data input/output pin.
Battery power input pin.
39
40
PA.0
I/O
I/O
I
General purpose digital I/O pin.
Tamper detect pin 0.
TAMPER0
SC0_CD
CAN1_RXD
INT0
SmartCard0 card detect pin.
CAN bus receiver1 input.
External interrupt0 input pin.
General purpose digital I/O pin.
Tamper detect pin 1.
I
I
41
PA.1
I/O
I/O
I
TAMPER1
SC5_CD
CAN1_TXD
EBI_A22
PD.8
SmartCard5 card detect pin.
CAN bus transmitter1 input.
EBI address bus bit22.
I
O
42
43
44
I/O
I/O
I/O
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
I2C0 clock pin.
SPI3_MISO1
I2C0_SCL
HS
This pad is embedded with “Slew Rate Control”
capability.
PD.9
I/O
I/O
I/O
MFP0
MPF1
MPF2
Slew
General purpose digital I/O pin.
2nd SPI3 MOSI (Master Out, Slave In) pin.
I2C0 data input/output pin.
SPI3_MOSI1
I2C0_SDA
HS
This pad is embedded with “Slew Rate Control”
capability.
PA.2
I/O
I/O
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
General purpose digital I/O pin.
SmartCard2 data pin.
SC2_DAT
SPI3_MISO0
I2S0_MCLK
BRAKE11
CAP_SFIELD
EBI_A12
1st SPI3 MISO (Master In, Slave Out) pin.
I2S0 master clock output pin.
Brake input pin 1 of EPWMA.
Video input interface SFIELD input pin.
EBI address bus bit12.
I
I
O
June 16, 2016
Page 86 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
45
PA.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
SmartCard2 clock pin.
SC2_CLK
SPI3_MOSI0
I2S0_DO
BRAKE10
EBI_A13
HS
I/O
O
1st SPI3 MOSI (Master Out, Slave In) pin.
I2S0 data output.
I
Brake input pin 0 of EPWMA.
EBI address bus bit13.
O
This pad is embedded with “Slew Rate Control”
capability.
46
PA.4
I/O
O
O
I
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 power pin.
SC2_PWR
SPI3_CLK
I2S0_DI
QEI1_Z
EBI_A14
ECAP1_IC2
HS
SPI3 serial clock pin.
I2S0 data input.
I
Quadrature encoder phase Z input of QEI Unit 1.
EBI address bus bit14.
O
I
Input 2 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
47
PA.5
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
SmartCard2 reset pin.
SC2_RST
SPI3_SS0
I2S0_BCLK
PWM0_0
QEI1_B
I/O
O
General purpose digital I/O pin.
I2S0 bit clock pin.
I/O
I
PWM0_0 output/capture input.
Quadrature encoder phase B input of QEI Unit 1.
EBI address bus bit15.
EBI_A15
ECAP1_IC1
HS
O
I
Input 1 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
48
PA.6
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 87 of 228
Rev 1.09
NUC442
SC2_CD
I2S0_LRCK
PWM0_1
QEI1_A
I
O
I/O
I
MPF1
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8
Slew
SmartCard2 card detect pin.
I2S0 left right channel clock.
PWM0_1 output/capture input.
Quadrature encoder phase A input of QEI Unit 1.
CAN bus transmitter1 input.
CAN1_TXD
EBI_A16
ECAP1_IC0
HS
I
O
I
EBI address bus bit16.
Input 0 of enhanced capture unit 1.
This pad is embedded with “Slew Rate Control”
capability.
49
PG.3
I/O
O
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
MPF2
MPF3
MFP0
MPF2
MPF3
MFP0
MPF2
MPF3
MFP0
General purpose digital I/O pin.
PS2 clock pin.
PS2_CLK
I2S1_DO
SC1_RST
PG.4
O
I2S1 data output.
O
SmartCard1 reset pin.
General purpose digital I/O pin.
PS2 data pin.
50
I/O
I/O
I
PS2_DAT
I2S1_DI
SC1_PWR
PG.5
I2S1 data input.
O
SmartCard1 power pin.
General purpose digital I/O pin.
I2S1 bit clock pin.
51
52
53
I/O
O
I2S1_BCLK
SC1_DAT
PG.6
I/O
I/O
O
SmartCard1 data pin.
General purpose digital I/O pin.
I2S1 left right channel clock.
SmartCard1 clock pin.
I2S1_LRCK
SC1_CLK
VDD
O
P
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
54
55
VSS
P
MFP0
MFP0
MPF2
MPF3
Ground pin for digital circuit.
General purpose digital I/O pin.
SmartCard0 clock pin.
PA.7
I/O
O
SC0_CLK
SPI3_SS0
I/O
General purpose digital I/O pin.
June 16, 2016
Page 88 of 228
Rev 1.09
NUC442
PWM1_3
EPWM0_5
EBI_A17
HS
I/O
I/O
O
MPF4
MPF5
MPF7
Slew
PWM1_3 output/capture input.
PWM0_5 output/capture input.
EBI address bus bit17.
This pad is embedded with “Slew Rate Control”
capability.
56
57
58
59
PA.8
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 reset pin.
SC0_RST
SPI3_CLK
PWM1_2
EPWM0_4
EBI_A18
HS
O
SPI3 serial clock pin.
I/O
I/O
O
PWM1_2 output/capture input.
PWM0_4 output/capture input.
EBI address bus bit18.
This pad is embedded with “Slew Rate Control”
capability.
PA.9
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 power pin.
SC0_PWR
SPI3_MISO0
PWM1_1
EPWM0_3
EBI_A19
HS
I/O
I/O
I/O
O
1st SPI3 MISO (Master In, Slave Out) pin.
PWM1_1 output/capture input.
PWM0_3 output/capture input.
EBI address bus bit19.
This pad is embedded with “Slew Rate Control”
capability.
PA.10
I/O
I/O
I/O
I/O
I/O
O
MFP0
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
SmartCard0 data pin.
SC0_DAT
SPI3_MOSI0
PWM1_0
EPWM0_2
EBI_A20
HS
1st SPI3 MOSI (Master Out, Slave In) pin.
PWM1_0 output/capture input.
PWM0_2 output/capture input.
EBI address bus bit20.
This pad is embedded with “Slew Rate Control”
capability.
PA.11
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 89 of 228
Rev 1.09
NUC442
UART0_RTS
SPI3_MISO1
PWM0_5
EPWM0_1
EBI_AD0
HS
O
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
Request to Send output pin for UART0.
2nd SPI3 MISO (Master In, Slave Out) pin.
PWM0_5 output/capture input.
I/O
I/O
I/O
O
PWM0_1 output/capture input.
EBI address/data bus bit 0.
This pad is embedded with “Slew Rate Control”
capability.
60
PA.12
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART0.
2nd SPI3 MOSI (Master Out, Slave In) pin.
PWM0_4 output/capture input.
PWM0_0 output/capture input.
EBI address/data bus bit 1.
UART0_CTS
SPI3_MOSI1
PWM0_4
EPWM0_0
EBI_AD1
HS
I/O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
61
62
63
PA.13
I/O
I
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART0.
SmartCard3 data pin.
UART0_RXD
SC3_DAT
PWM1_4
EBI_AD2
HS
I/O
I/O
O
PWM1_4 output/capture input.
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
PA.14
I/O
O
MFP0
MPF1
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART0.
SmartCard3 clock pin.
UART0_TXD
SC3_CLK
PWM1_5
EBI_AD3
HS
O
I/O
O
PWM1_5 output/capture input.
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
PD.10
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 90 of 228
Rev 1.09
NUC442
SC3_DAT
I2C4_SCL
PD.11
I/O
I/O
I/O
O
MPF1
MPF2
MFP0
MPF1
MPF3
MFP0
MPF1
MPF2
MFP0
MPF1
MPF2
MPF4
MPF7
Slew
SmartCard3 data pin.
I2C4 clock pin.
64
65
66
General purpose digital I/O pin.
SmartCard3 reset pin.
SC3_RST
TM3_CNT_OUT
PD.12
I/O
I/O
O
Timer3 event counter input/toggle output.
General purpose digital I/O pin.
SmartCard3 clock pin.
SC3_CLK
I2C4_SDA
PA.15
I/O
I/O
O
I2C4 data input/output pin.
General purpose digital I/O pin.
SmartCard3 power pin.
SC3_PWR
UART2_RTS
I2C0_SCL
EBI_A21
HS
O
Request to Send output pin for UART2.
I2C0 clock pin.
I/O
O
EBI address bus bit21.
This pad is embedded with “Slew Rate Control”
capability.
67
PC.9
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8
MPF9
Slew
General purpose digital I/O pin.
ADC analog input.
STADC
UART2_CTS
SC3_RST
I2C0_SDA
CAP_DATA1
I2C3_SCL
EBI_A22
SD1_DAT0
EBI_A6
I
Clear to Send input pin for UART2.
SmartCard3 reset pin.
O
I/O
I
I2C0 data input/output pin.
Image data input bus bit 1.
I2C3 clock pin.
I/O
O
EBI address bus bit22.
SD mode #1 data line bit 0.
EBI address bus bit6.
I/O
O
HS
This pad is embedded with “Slew Rate Control”
capability.
68
PC.10
I/O
I
MFP0
MPF1
General purpose digital I/O pin.
SmartCard3 card detect pin.
SC3_CD
June 16, 2016
Page 91 of 228
Rev 1.09
NUC442
UART2_RXD
PWM0_2
EBI_A23
EBI_AD2
HS
I
MPF2
MPF4
MPF6
MPF7
Slew
Data receiver input pin for UART2.
PWM0_2 output/capture input.
EBI address bus bit23.
I/O
O
O
EBI address/data bus bit 2.
This pad is embedded with “Slew Rate Control”
capability.
69
PC.11
I/O
O
MFP0
MPF2
MPF4
MPF6
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART2.
PWM0_3 output/capture input.
EBI address bus bit24.
UART2_TXD
PWM0_3
EBI_A24
EBI_AD3
HS
I/O
O
O
EBI address/data bus bit 3.
This pad is embedded with “Slew Rate Control”
capability.
70
LDO_CAP
P
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
71
72
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
73
74
75
PD.13
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
1st SPI1 slave select pin.
SPI1_SS0
UART5_CTS
ECAP0_IC2
HS
Clear to Send input pin for UART5.
Input 2 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
PD.14
I/O
O
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
UART5_RTS
ECAP0_IC1
HS
O
Request to Send output pin for UART5.
Input 1 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
PD.15
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 92 of 228
Rev 1.09
NUC442
SPI1_MISO0
UART5_TXD
ECAP0_IC0
HS
I/O
O
MPF1
MPF2
MPF3
Slew
1st SPI1 MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART5.
Input 0 of enhanced capture unit 0.
O
This pad is embedded with “Slew Rate Control”
capability.
76
PF.0
I/O
MFP0
MPF1
MPF2
MPF8
Slew
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART5.
External interrupt5 input pin.
SPI1_MOSI0
UART5_RXD
INT5
I/O
I
I
HS
This pad is embedded with “Slew Rate Control”
capability.
77
VRES
A
MFP0
USB PHY VRES ground input pin. Add an 8.2K
ohm resistor to VSSA.
78
79
VBUS
A
P
MFP0
MFP0
USB PHY VBUS power input pin.
USB_VDD33_CAP
Internal power regulator output 3.3V decoupling
pin.
80
VSSA
P
MFP0
Ground pin for digital circuit. Add a Feritte Bead to
digital ground VSS
.
81
82
83
84
USB0_D-
A
A
MFP0
MFP0
MFP0
MFP0
MPF1
MPF2
MPF8
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
USB0 differential signal D-.
USB0_D+
USB0_OTG_ID
PB.0
USB0 differential signal D+.
I
USB0 OTG ID pin.
I/O
I
General purpose digital I/O pin.
USB0 external VBUS regulator status
I2C4 clock pin.
USB0_OTG5V_ST
I2C4_SCL
INT1
I/O
I
External interrupt1 input pin.
General purpose digital I/O pin.
USB0 external VBUS regulator enabled
I2C4 data input/output pin.
85
PB.1
I/O
O
USB0_OTG5V_EN
I2C4_SDA
TM1_CNT_OUT
PG.7
I/O
I/O
I/O
I/O
Timer1 event counter input/toggle output.
General purpose digital I/O pin.
1st SPI2 MISO (Master In, Slave Out) pin.
86
SPI2_MISO0
June 16, 2016
Page 93 of 228
Rev 1.09
NUC442
I2S1_MCLK
SC1_CD
SC3_RST
HS
O
I
MPF2
MPF3
MPF4
Slew
I2S1 master clock output pin.
SmartCard1 card detect pin.
SmartCard3 reset pin.
O
This pad is embedded with “Slew Rate Control”
capability.
87
88
89
90
PG.8
I/O
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
Slew
General purpose digital I/O pin.
1st SPI2 MOSI (Master Out, Slave In) pin.
I2S1 data output.
SPI2_MOSI0
I2S1_DO
UART4_RTS
SC3_DAT
HS
O
Request to Send output pin for UART4.
SmartCard3 data pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
PG.9
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
Slew
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
I2S1_DI
UART4_CTS
SC3_CLK
HS
I2S1 data input.
I
Clear to Send input pin for UART4.
SmartCard3 clock pin.
O
This pad is embedded with “Slew Rate Control”
capability.
PB.2
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
USB1 differential signal D-.
UART1_RXD
SPI2_SS0
USB1_D-
EBI_AD4
HS
I/O
A
O
EBI address/data bus bit 4.
This pad is embedded with “Slew Rate Control”
capability.
PB.3
I/O
O
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI2 serial clock pin.
UART1_TXD
SPI2_CLK
USB1_D+
O
A
USB1 differential signal D+.
June 16, 2016
Page 94 of 228
Rev 1.09
NUC442
EBI_AD5
HS
O
MPF7
Slew
EBI address/data bus bit 5.
This pad is embedded with “Slew Rate Control”
capability.
91
PB.4
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
UART1_RTS
SPI2_MISO0
UART4_RXD
TM0_CNT_OUT
EBI_AD6
Request to Send output pin for UART1.
1st SPI2 MISO (Master In, Slave Out) pin.
Data receiver input pin for UART4.
Timer0 event counter input/toggle output.
EBI address/data bus bit 6.
I/O
I
I/O
O
HS
This pad is embedded with “Slew Rate Control”
capability.
92
PB.5
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
UART1_CTS
SPI2_MOSI0
UART4_TXD
EBI_AD7
HS
Clear to Send input pin for UART1.
1st SPI2 MOSI (Master Out, Slave In) pin.
Data transmitter output pin for UART4.
EBI address/data bus bit 7.
I/O
O
O
This pad is embedded with “Slew Rate Control”
capability.
93
PB.6
I/O
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2C2 clock pin.
I2C2_SCL
BRAKE01
UART4_RTS
PWM1_4
EPWM1_0
EBI_AD8
HS
Brake input pin 1 of EPWMB.
Request to Send output pin for UART4.
PWM1_4 output/capture input.
PWM1_0 output/capture input.
EBI address/data bus bit 8.
O
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
94
PB.7
I/O
I/O
I
MFP0
MPF1
MPF2
General purpose digital I/O pin.
I2C2 data input/output pin.
Brake input pin 0 of EPWMB.
I2C2_SDA
BRAKE00
June 16, 2016
Page 95 of 228
Rev 1.09
NUC442
UART4_CTS
PWM1_5
EPWM1_1
EBI_AD9
HS
I
MPF3
MPF4
MPF5
MPF7
Slew
Clear to Send input pin for UART4.
PWM1_5 output/capture input.
PWM1_1 output/capture input.
EBI address/data bus bit 9.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
95
96
97
98
99
PB.8
I/O
I
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART5.
PWM1_2 output/capture input.
EBI address/data bus bit 10.
UART5_CTS
EPWM1_2
EBI_AD10
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.9
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Request to Send output pin for UART5.
PWM1_3 output/capture input.
EBI address/data bus bit 11.
UART5_RTS
EPWM1_3
EBI_AD11
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.10
I/O
O
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data transmitter output pin for UART5.
PWM1_4 output/capture input.
EBI address/data bus bit 12.
UART5_TXD
EPWM1_4
EBI_AD12
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PB.11
I/O
I
MFP0
MPF1
MPF5
MPF7
Slew
General purpose digital I/O pin.
Data receiver input pin for UART5.
PWM1_5 output/capture input.
EBI address/data bus bit 13.
UART5_RXD
EPWM1_5
EBI_AD13
HS
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PH.0
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 96 of 228
Rev 1.09
NUC442
I2C1_SCL
UART4_RXD
CAN1_RXD
INT7
I/O
I
MPF1
MPF2
MPF3
MPF8
MFP0
MPF1
MPF2
MPF3
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
I2C1 clock pin.
Data receiver input pin for UART4.
CAN bus receiver1 input.
I
I
External interrupt7 input pin.
General purpose digital I/O pin.
Data transmitter output pin for UART4.
I2C1 data input/output pin.
100
PH.1
I/O
O
I/O
I
UART4_TXD
I2C1_SDA
CAN1_TXD
PB.12
CAN bus transmitter1 input.
General purpose digital I/O pin.
Request to Send output pin for UART4.
2nd SPI2 MISO (Master In, Slave Out) pin.
CAN bus receiver0 input.
101
I/O
O
I/O
I
UART4_RTS
SPI2_MISO1
CAN0_RXD
EBI_AD14
HS
O
EBI address/data bus bit 14.
This pad is embedded with “Slew Rate Control”
capability.
102
PB.13
I/O
I
MFP0
MPF1
MPF2
MPF3
MPF7
Slew
General purpose digital I/O pin.
Clear to Send input pin for UART4.
2nd SPI2 MOSI (Master Out, Slave In) pin.
CAN bus transmitter0 input.
UART4_CTS
SPI2_MOSI1
CAN0_TXD
EBI_AD15
HS
I/O
I
O
EBI address/data bus bit 15.
This pad is embedded with “Slew Rate Control”
capability.
103
PB.14
I/O
O
O
I
MFP0
MPF1
MPF2
MPF4
Slew
General purpose digital I/O pin.
I2S1 master clock output pin.
SmartCard1 reset pin.
I2S1_MCLK
SC1_RST
BRAKE01
HS
Brake input pin 1 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
104
PB.15
I/O
MFP0
General purpose digital I/O pin.
June 16, 2016
Page 97 of 228
Rev 1.09
NUC442
I2S1_DO
SC1_DAT
BRAKE00
HS
O
I/O
I
MPF1
MPF2
MPF4
Slew
I2S1 data output.
SmartCard1 data pin.
Brake input pin 0 of EPWMB.
This pad is embedded with “Slew Rate Control”
capability.
105
VDD
P
MFP0
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
106
107
VSS
P
P
MFP0
MFP0
Ground pin for digital circuit.
LDO output pin.
LDO_CAP
Note: This pin needs to be connected with a 1uF
capacitor.
108
109
110
PC.0
I/O
MFP0
MPF1
MPF2
MPF3
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1 data input.
I2S1_DI
SC1_DAT
UART4_RXD
EBI_MCLK
INT2
I
I/O
I
SmartCard1 data pin.
Data receiver input pin for UART4.
EBI interface clock output pin.
External interrupt2 input pin.
O
I
HS
This pad is embedded with “Slew Rate Control”
capability.
PC.1
I/O
O
MFP0
MPF1
MPF2
MPF3
MPF5
MPF7
Slew
General purpose digital I/O pin.
I2S1 bit clock pin.
I2S1_BCLK
SC1_CLK
UART4_TXD
TM3_CNT_OUT
EBI_AD13
HS
O
SmartCard1 clock pin.
O
Data transmitter output pin for UART4.
Timer3 event counter input/toggle output.
EBI address/data bus bit 13.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
PC.2
I/O
O
MFP0
MPF1
MPF2
MPF3
General purpose digital I/O pin.
I2S1 left right channel clock.
SmartCard1 power pin.
I2S1_LRCK
SC1_PWR
UART4_RTS
O
O
Request to Send output pin for UART4.
June 16, 2016
Page 98 of 228
Rev 1.09
NUC442
SPI0_SS0
EBI_AD12
HS
I/O
O
MPF4
MPF7
Slew
General purpose digital I/O pin.
EBI address/data bus bit 12.
This pad is embedded with “Slew Rate Control”
capability.
111
PC.3
I/O
O
I
MFP0
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1_MCLK
SC1_CD
UART4_CTS
SPI0_MISO1
QEI0_Z
I2S1 master clock output pin.
SmartCard1 card detect pin.
I
Clear to Send input pin for UART4.
2nd SPI0 MISO (Master In, Slave Out) pin.
Quadrature encoder phase Z input of QEI Unit 0.
EBI address/data bus bit 11.
I/O
I
EBI_AD11
ECAP0_IC2
HS
O
O
Input 2 of enhanced capture unit 0.
This pad is embedded with “Slew Rate Control”
capability.
112
PC.4
I/O
O
MFP0
MPF1
MPF2
MPF4
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
I2S1 data output.
I2S1_DO
SC1_RST
SPI0_MOSI1
QEI0_B
O
SmartCard1 reset pin.
I/O
I
2nd SPI0 MOSI (Master Out, Slave In) pin.
Quadrature encoder phase B input of QEI Unit 0.
EBI address/data bus bit 10.
EBI_AD10
ECAP0_IC1
HS
O
O
Input 1 of enhanced capture unit 0.
This pad is embedded with “Slew Rate Control”
capability.
113
PC.5
I/O
O
I
MFP0
MFP1
MPF5
MPF7
MPF8
Slew
General purpose digital I/O pin.
Clock Output Pin.
CLKO
QEI0_A
EBI_MCLK
ECAP0_IC0
HS
Quadrature encoder phase A input of QEI Unit 0.
EBI interface clock output pin.
Input 0 of enhanced capture unit 0.
O
O
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 99 of 228
Rev 1.09
NUC442
114
PC.6
I/O
I
MFP0
MPF1
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
Timer2 external counter input
TM2_EXT
SPI0_MISO0
TM2_CNT_OUT
EBI_AD9
HS
I/O
I/O
O
1st SPI0 MISO (Master In, Slave Out) pin.
Timer2 event counter input/toggle output.
EBI address/data bus bit 9.
This pad is embedded with “Slew Rate Control”
capability.
115
PC.7
I/O
I
MFP0
MPF1
MPF4
MPF7
Slew
General purpose digital I/O pin.
Timer1 external counter input
TM1_EXT
SPI0_MOSI0
EBI_AD8
HS
I/O
O
1st SPI0 MOSI (Master Out, Slave In) pin.
EBI address/data bus bit 8.
This pad is embedded with “Slew Rate Control”
capability.
116
117
118
119
PC.8
I/O
I
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Timer0 external counter input
SPI0 serial clock pin.
TM0_EXT
SPI0_CLK
HS
O
This pad is embedded with “Slew Rate Control”
capability.
PF.2
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
General purpose digital I/O pin.
SD mode #0 data line bit 3.
SPI3_SS0
SD0_DAT3
HS
This pad is embedded with “Slew Rate Control”
capability.
PF.3
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
SPI3 serial clock pin.
SPI3_CLK
SD0_DAT2
HS
I/O
SD mode #0 data line bit 2.
This pad is embedded with “Slew Rate Control”
capability.
PF.4
I/O
I/O
I/O
MFP0
MPF1
MPF4
General purpose digital I/O pin.
1st SPI3 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
SPI3_MISO0
SD0_DAT1
June 16, 2016
Page 100 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
120
PF.5
I/O
I/O
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
1st SPI3 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
SPI3_MOSI0
SD0_DAT0
HS
This pad is embedded with “Slew Rate Control”
capability.
121
122
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
123
124
125
PF.6
I/O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Data receiver input pin for UART2.
SD mode #0 – card detect
UART2_RXD
SD0_CDn
HS
I
I
This pad is embedded with “Slew Rate Control”
capability.
PF.7
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
UART2_TXD
SD0_CMD
HS
Data transmitter output pin for UART2.
SD mode #0 – command/response
I/O
This pad is embedded with “Slew Rate Control”
capability.
PF.8
I/O
O
MFP0
MPF1
MPF4
Slew
General purpose digital I/O pin.
Request to Send output pin for UART2.
SD mode #0– clock.
UART2_RTS
SD0_CLK
HS
O
This pad is embedded with “Slew Rate Control”
capability.
126
127
PH.2
I/O
I
MFP0
MPF1
MFP0
General purpose digital I/O pin.
Clear to Send input pin for UART2.
LDO output pin.
UART2_CTS
LDO_CAP
P
Note: This pin needs to be connected with a 1uF
capacitor.
128
129
VSS
VDD
P
P
MFP0
MFP0
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
June 16, 2016
Page 101 of 228
Rev 1.09
NUC442
130
131
132
PE.0
I/O
A
MFP0
MPF1
MPF8
MFP0
MPF1
MPF3
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_0
INT4
I
External interrupt4 input pin.
General purpose digital I/O pin.
ADC0 analog input.
PE.1
I/O
A
ADC0_1
TM2_CNT_OUT
PE.2
I/O
I/O
A
Timer2 event counter input/toggle output.
General purpose digital I/O pin.
ADC0 analog input.
ADC0_2
ACMP0_O
SPI0_MISO0
HS
O
Analog comparator0 output .
1st SPI0 MISO (Master In, Slave Out) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
133
134
135
PE.3
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_3
ACMP0_P3
SPI0_MOSI0
HS
A
Analog comparator0 positive input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
PE.4
I/O
A
MFP0
MPF1
MPF2
MPF3
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_4
ACMP0_P2
SPI0_SS0
HS
A
Analog comparator0 positive input pin.
General purpose digital I/O pin.
I/O
This pad is embedded with “Slew Rate Control”
capability.
PE.5
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
General purpose digital I/O pin.
ADC0 analog input.
ADC0_5
ACMP0_P1
SPI0_CLK
SD0_CDn
A
Analog comparator0 positive input pin.
SPI0 serial clock pin.
O
I
SD mode #0 – card detect
June 16, 2016
Page 102 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
136
PE.6
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_6
ACMP0_P0
SPI0_MISO0
SD0_CMD
EBI_nWR
HS
A
Analog comparator0 positive input pin.
1st SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 – command/response
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
137
PE.7
I/O
A
MFP0
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC0 analog input.
ADC0_7
ACMP0_N
SPI0_MOSI0
SD0_CLK
EBI_nRD
HS
A
Analog comparator0 negative input pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0– clock.
I/O
O
O
EBI read enable output pin.
This pad is embedded with “Slew Rate Control”
capability.
138
139
AVSS
P
A
MFP0
MFP0
Ground pin for digital circuit.
VREF
Voltage reference input for ADC.
Note: This pin needs to be connected with
0.1uF/10uF capacitors.
140
141
AVDD
P
I/O
A
MFP0
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC1 analog input.
PE.8
ADC1_0
ADC0_8
ACMP1_N
TM1_CNT_OUT
SD0_DAT3
EBI_ALE
A
ADC0 analog input.
A
Analog comparator1 negative input pin.
Timer1 event counter input/toggle output.
SD mode #0 data line bit 3.
I/O
I/O
O
EBI address latch enable output pin.
June 16, 2016
Page 103 of 228
Rev 1.09
NUC442
HS
Slew
This pad is embedded with “Slew Rate Control”
capability.
142
PE.9
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_1
ADC0_9
ACMP1_P0
SD0_DAT2
EBI_nWRH
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
SD mode #0 data line bit 2.
EBI write enable output pin.
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
143
PE.10
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_2
ADC0_10
ACMP1_P1
SPI0_MISO1
SD0_DAT1
EBI_nWRL
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
SD mode #0 data line bit 1.
EBI write enable output pin.
I/O
I/O
O
This pad is embedded with “Slew Rate Control”
capability.
144
PE.11
I/O
A
MFP0
MPF1
MPF1
MPF2
MPF3
MPF4
MPF5
MPF7
Slew
General purpose digital I/O pin.
ADC1 analog input.
ADC1_3
ADC0_11
ACMP1_P2
SPI0_MOSI1
SD0_DAT0
ACMP2_P3
EBI_nCS0
HS
A
ADC0 analog input.
A
Analog comparator1 positive input pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
SD mode #0 data line bit 0.
I/O
I/O
A
Analog comparator2 positive input pin.
EBI chip select 0 enable output pin.
O
This pad is embedded with “Slew Rate Control”
capability.
Note: Pin Type I = Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin
June 16, 2016
Page 104 of 228
Rev 1.09
NUC442
4.3.5 Summary GPIO Multi-function Pin Description
MFP* = Multi-function pin. (Reference section 6.2.5 of TRM)
MFP
Oth Sle
MPF1
MPF2
MPF3
MPF4
MPF5
MPF6
MPF7
MPF8 MPF9
INT0
0
er
w
PA.0 TAMPER0
PA.1 TAMPER1
SC0_CD CAN1_RXD
SC5_CD CAN1_TXD
SPI3_MIS
EBI_A22
EBI_A12
CAP_SFIEL
D
PA.2 SC2_DAT
PA.3 SC2_CLK
PA.4 SC2_PWR
PA.5 SC2_RST
PA.6 SC2_CD
I2S0_MCLK BRAKE11
HS
HS
HS
HS
HS
O0
SPI3_MO
SI0
I2S0_DO
BRAKE10
EBI_A13
EBI_A14
EBI_A15
ECAP1_I
C2
SPI3_CLK I2S0_DI
QEI1_Z
ECAP1_I
C1
SPI3_SS0 I2S0_BCLK PWM0_0 QEI1_B
I2S0_LRCK PWM0_1 QEI1_A
ECAP1_I
C0
CAN1_TXD EBI_A16
PA.7
PA.8
PA.9
SC0_CLK SPI3_SS0
SC0_RST SPI3_CLK
PWM1_3 EPWM0_5
PWM1_2 EPWM0_4
EBI_A17
EBI_A18
EBI_A19
HS
HS
HS
SC0_PWR SPI3_MISO0 PWM1_1 EPWM0_3
SC0_DAT SPI3_MOSI0 PWM1_0 EPWM0_2
PA.1
0
EBI_A20
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
EBI_A21
HS
HS
HS
HS
HS
HS
PA.1
UART0_RTS
1
SPI3_MISO1 PWM0_5 EPWM0_1
SPI3_MOSI1 PWM0_4 EPWM0_0
PA.1
UART0_CTS
2
PA.1
UART0_RXD
3
SC3_DAT
SC3_CLK
PWM1_4
PWM1_5
I2C0_SCL
PA.1
UART0_TXD
4
PA.1
UART2_R
TS
SC3_PWR
5
USB0_OTG5V
PB.0
_ST
I2C4_SCL
I2C4_SDA
INT1
USB0_OTG5V
TM1_CNT_O
UT
PB.1
_EN
PB.2 UART1_RXD SPI2_SS0 USB1_D-
EBI_AD4
EBI_AD5
HS
HS
PB.3 UART1_TXD
SPI2_CLK USB1_D+
TM0_CNT
_
SPI2_MIS
UART4_RXD
O0
PB.4 UART1_RTS
EBI_AD6
HS
OUT
SPI2_MO
UART4_TXD
SI0
PB.5 UART1_CTS
PB.6 I2C2_SCL
EBI_AD7
EBI_AD8
HS
HS
BRAKE01 UART4_RTS PWM1_4 EPWM1_0
June 16, 2016
Page 105 of 228
Rev 1.09
NUC442
PB.7 I2C2_SDA
BRAKE00 UART4_CTS PWM1_5 EPWM1_1
EPWM1_2
EBI_AD9
HS
EBI_AD1
0
PB.8 UART5_CTS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
EBI_AD1
1
PB.9 UART5_RTS
EPWM1_3
EPWM1_4
EPWM1_5
PB.1
EBI_AD1
2
UART5_TXD
0
PB.1
EBI_AD1
3
UART5_RXD
1
PB.1
SPI2_MIS
CAN0_RXD
O1
EBI_AD1
4
UART4_RTS
2
PB.1
SPI2_MO
CAN0_TXD
SI1
EBI_AD1
5
UART4_CTS
3
PB.1
I2S1_MCLK
4
SC1_RST
BRAKE01
BRAKE00
PB.1
I2S1_DO
5
SC1_DAT
EBI_MC
LK
PC.0 I2S1_DI
SC1_DAT UART4_RXD
SC1_CLK UART4_TXD
INT2
TM3_CNT_O
UT
EBI_AD1
3
PC.1 I2S1_BCLK
PC.2 I2S1_LRCK
PC.3 I2S1_MCLK
PC.4 I2S1_DO
PC.5 CLKO
EBI_AD1
2
SC1_PWR UART4_RTS SPI0_SS0
SPI0_MIS
SC1_CD UART4_CTS
O1
EBI_AD1 ECAP0_I
C2
QEI0_Z
QEI0_B
QEI0_A
1
SPI0_MO
EBI_AD1 ECAP0_I
C1
SC1_RST
SI1
0
EBI_MC ECAP0_I
LK
C0
SPI0_MIS TM2_CNT_O
PC.6 TM2_EXT
EBI_AD9
O0
UT
SPI0_MO
SI0
PC.7 TM1_EXT
PC.8 TM0_EXT
PC.9 STADC
EBI_AD8
HS
HS
HS
SPI0_CLK
UART2_C
TS
SD1_DA EBI_
SC3_RST
I2C0_SDA CAP_DATA1 I2C3_SCL
EBI_A22
EBI_AD2
EBI_AD3
EBI_A0
EBI_A1
EBI_A2
T0
A6
PC.1
SC3_CD
0
UART2_R
XD
PWM0_2
EBI_A23
EBI_A24
HS
HS
HS
HS
HS
PC.1
1
UART2_T
XD
PWM0_3
PC.1
SPI1_SS0
2
SC4_CD
SD1_CDn CAP_DATA7
SD1_CMD CAP_DATA6
SD1_CLK CAP_DATA5
PC.1
SPI1_MOSI1
3
SC4_RST
PC.1
SPI1_MISO1
4
SC4_PWR TM3_EXT
June 16, 2016
Page 106 of 228
Rev 1.09
NUC442
PC.1
5
SD1_DAT
3
SPI1_MOSI0
SC4_DAT
SC4_CLK
CAP_DATA4
CAP_DATA3
CAP_DATA2
CAP_DATA1
EBI_A3
HS
SD1_DAT
2
PD.0 SPI1_MISO0
PD.1 SPI1_CLK
EBI_A4 INT3
EBI_A5
HS
HS
TM0_CNT_O SD1_DAT
UT
1
SD1_DAT
0
PD.2 STADC
PD.3 SC5_CLK
PD.4 SC5_CD
I2C3_SCL
EBI_A6
EBI_A7
EBI_A8
HS
HS
HS
I2C3_SDA ACMP2_O
SD0_CDn CAP_DATA0
CAP_SCLK
UART3_R
ACMP1_O
XD
UART3_T
XD
CAP_VSYN
C
PD.5 SC5_RST
PD.6 SC5_PWR
PD.7 SC5_DAT
EBI_A9
HS
HS
HS
UART3_R
TS
CAP_HSYN
SD0_CMD
C
EBI_A10
EBI_A11
UART3_C
TS
CAP_PIXCL
SD0_CLK
K
PD.8 SPI3_MISO1
PD.9 SPI3_MOSI1
I2C0_SCL
I2C0_SDA
HS
HS
PD.1
SC3_DAT
0
I2C4_SCL
PD.1
TM3_CNT_O
UT
SC3_RST
1
PD.1
SC3_CLK
2
I2C4_SDA
PD.1
UART5_C
ECAP0_IC2
TS
SPI1_SS0
3
HS
HS
HS
PD.1
UART5_R
ECAP0_IC1
TS
SPI1_CLK
4
PD.1
UART5_T
ECAP0_IC0
XD
SPI1_MISO0
5
PE.0 ADC0_0
PE.1 ADC0_1
PE.2 ADC0_2
PE.3 ADC0_3
INT4
TM2_CNT_O
UT
ACMP0_O SPI0_MISO0
HS
HS
ACMP0_P
SPI0_MOSI0
3
ACMP0_P
SPI0_SS0
2
PE.4 ADC0_4
PE.5 ADC0_5
HS
HS
ACMP0_P
SPI0_CLK
1
SD0_CDn
ACMP0_P
0
EBI_nW
R
PE.6 ADC0_6
PE.7 ADC0_7
SPI0_MISO0 SD0_CMD
HS
HS
ACMP0_N SPI0_MOSI0 SD0_CLK
EBI_nRD
June 16, 2016
Page 107 of 228
Rev 1.09
NUC442
ADC1_0/
ADC0_8
TM1_CNT_O SD0_DAT
PE.8
PE.9
ACMP1_N
EBI_ALE
HS
UT
3
ADC1_1/ADC0 ACMP1_P
_9
SD0_DAT
2
EBI_nW
RH
HS
HS
HS
HS
HS
HS
0
PE.1 ADC1_2/ADC0 ACMP1_P
SD0_DAT
1
EBI_nW
RL
SPI0_MISO1
SPI0_MOSI1
ACMP2_P2
ACMP2_P1
ACMP2_P0
ACMP2_N
0
_10
1
PE.1 ADC1_3/ADC0 ACMP1_P
SD0_DAT
0
EBI_nCS
0
ACMP2_P3
1
_11
2
PE.1
2
ACMP1_P
3
EBI_nCS
1
ADC1_4
PE.1
3
EBI_nCS
2
ADC1_5
ADC1_6
ADC1_7
PE.1
4
EBI_nCS
3
PE.1
5
UART5_R
XD
PF.0 SPI1_MOSI0
PF.1 SPI2_MOSI1
PF.2 SPI3_SS0
INT5
HS
HS
HS
SD0_DAT
3
SD0_DAT
2
PF.3 SPI3_CLK
HS
HS
HS
SD0_DAT
1
PF.4 SPI3_MISO0
PF.5 SPI3_MOSI0
SD0_DAT
0
PF.6 UART2_RXD
PF.7 UART2_TXD
PF.8 UART2_RTS
PF.9 OPA0_P
SD0_CDn
SD0_CMD
SD0_CLK
PWM0_0
HS
HS
HS
HS
PF.1
OPA0_N
0
PWM0_1
HS
PF.1
OPA0_O
1
UART1_R
TS
PF.1
OPA1_P
2
UART1_C
TS
PF.1
OPA1_N
3
UART1_T
XD
PF.1
OPA1_O
4
UART1_R
XD
PF.1
UART0_RTS
5
PG.0 UART0_CTS
PG.1 UART0_RXD
INT6
June 16, 2016
Page 108 of 228
Rev 1.09
NUC442
PG.2 UART0_TXD
PG.3 PS2_CLK
PG.4 PS2_DAT
I2S1_DO SC1_RST
I2S1_DI
SC1_PWR
SC1_DAT
I2S1_BCL
K
PG.5
I2S1_LRC
K
PG.6
SC1_CLK
SC1_CD
I2S1_MCL
K
PG.7 SPI2_MISO0
SC3_RST
HS
PG.8 SPI2_MOSI0
PG.9 SPI2_CLK
I2S1_DO UART4_RTS SC3_DAT
HS
HS
I2S1_DI
UART4_CTS SC3_CLK
PG.1
ICE_CLK
0
PG.1
ICE_DAT
1
PG.1
XT1_OUT
2
PG.1
XT1_IN
3
PG.1
X32K_OUT
4
I2C1_SDA
I2C1_SCL
CAN1_RXD
PG.1
X32K_IN
5
UART4_R
XD
PH.0 I2C1_SCL
INT7
PH.1 UART4_TXD
PH.2 UART2_CTS
PH.3 I2C3_SCL
PH.4 I2C3_SDA
PH.5 SPI2_SS0
PH.6 SPI2_CLK
PH.7 SPI2_MISO0
PH.8 SPI2_MOSI0
PH.9 SPI2_MISO1
I2C1_SDA CAN1_TXD
HS
HS
HS
HS
HS
PH.1
SPI2_MOSI1
0
HS
PH.1
UART3_RXD
1
PH.1
UART3_TXD
2
PH.1
UART3_RTS
3
June 16, 2016
Page 109 of 228
Rev 1.09
NUC442
PH.1
4
UART3_CTS
PH.1
5
SC5_CLK
PI.0
PI.1
SC5_RST
SC5_PWR
PI.2 SC5_DAT
PI.3 SPI3_SS0
PI.4 SPI3_CLK
PI.5 SPI3_MISO0
PI.6 SPI3_MOSI0
HS
HS
HS
HS
SPI3_MIS
O1
PI.7 I2C2_SCL
PI.8 I2C2_SDA
HS
HS
SPI3_MO
SI1
PI.9
I2C4_SCL
PI.10
I2S1_BCL
K
PI.11 SPI2_SS0
I2C4_SCL
I2C4_SDA
SC3_PWR
SC3_CD
HS
I2S1_LRC
K
PI.12 SPI2_MISO1
PI.13
PI.14
PI.15
Note: PA.0* = TAMPER0 PA.1* = TAMPER1
June 16, 2016
Page 110 of 228
Rev 1.09
NUC442
4.3.6 Summary Function Pin Description
Group
ACMP0
ACMP0
ACMP0
ACMP0
ACMP0
ACMP0
ACMP1
ACMP1
ACMP1
ACMP1
ACMP1
ACMP1
ACMP2
ACMP2
ACMP2
ACMP2
ACMP2
ACMP2
ADC0
Pin Name
ACMP0_N
ACMP0_O
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP1_N
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
ACMP2_N
ACMP2_O
ACMP2_P0
ACMP2_P1
ACMP2_P2
ACMP2_P3
ADC0_0
GPIO
PE.7
PE.2
PE.6
PE.5
PE.4
PE.3
PE.8
PD.4
PE.9
PE.10
PE.11
PE.12
PE.15
PD.3
PE.14
PE.13
PE.12
PE.11
PE.0
PE.1
PE.10
PE.11
PE.2
PE.3
PE.4
PE.5
PE.6
PE.7
PE.8
PE.9
PD.2
PE.8
PE.9
*MFP Type Description
MPF2
MPF2
MPF2
MPF2
MPF2
MPF2
MPF2
MPF3
MPF2
MPF2
MPF2
MPF2
MPF3
MPF3
MPF3
MPF3
MPF3
MPF5
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
A
O
A
A
A
A
A
O
A
A
A
A
A
O
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Analog comparator0 negative input pin.
Analog comparator0 output.
Analog comparator0 positive input pin.
Analog comparator0 positive input pin.
Analog comparator0 positive input pin.
Analog comparator0 positive input pin.
Analog comparator1 negative input pin.
Analog comparator1 output.
Analog comparator1 positive input pin.
Analog comparator1 positive input pin.
Analog comparator1 positive input pin.
Analog comparator1 positive input pin.
Analog comparator2 negative input pin.
Analog comparator2 output.
Analog comparator2 positive input pin.
Analog comparator2 positive input pin.
Analog comparator2 positive input pin.
Analog comparator2 positive input pin.
ADC0 analog input.
ADC0
ADC0_1
ADC0 analog input.
ADC0
ADC0_10
ADC0_11
ADC0_2
ADC0 analog input.
ADC0
ADC0 analog input.
ADC0
ADC0 analog input.
ADC0
ADC0_3
ADC0 analog input.
ADC0
ADC0_4
ADC0 analog input.
ADC0
ADC0_5
ADC0 analog input.
ADC0
ADC0_6
ADC0 analog input.
ADC0
ADC0_7
ADC0 analog input.
ADC0
ADC0_8
ADC0 analog input.
ADC0
ADC0_9
ADC0 analog input.
ADC0
STADC
ADC analog input.
ADC1
ADC1_0
ADC1 analog input.
ADC1
ADC1_1
ADC1 analog input.
June 16, 2016
Page 111 of 228
Rev 1.09
NUC442
ADC1
ADC1_2
PE.10
PE.11
PE.12
PE.13
PE.14
PE.15
PA.5
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF2
MPF4
MPF2
MPF4
MPF4
MPF4
MPF3
MPF3
MPF3
MPF3
MPF3
MPF6
MPF3
A
A
A
A
A
A
ADC1 analog input.
ADC1 analog input.
ADC1 analog input.
ADC1 analog input.
ADC1 analog input.
ADC1 analog input.
ADC1
ADC1_3
ADC1
ADC1_4
ADC1
ADC1_5
ADC1
ADC1_6
ADC1
ADC1_7
BPWMA
BPWMA
BPWMA
BPWMA
BPWMA
BPWMA
BPWMA
BPWMA
BPWMB
BPWMB
BPWMB
BPWMB
BPWMB
BPWMB
BPWMB
BPWMB
BRAKE
BRAKE
BRAKE
BRAKE
BRAKE
BRAKE
CAN0
PWM0_0
PWM0_0
PWM0_1
PWM0_1
PWM0_2
PWM0_3
PWM0_4
PWM0_5
PWM1_0
PWM1_1
PWM1_2
PWM1_3
PWM1_4
PWM1_4
PWM1_5
PWM1_5
BRAKE00
BRAKE00
BRAKE01
BRAKE01
BRAKE10
BRAKE11
CAN0_RXD
CAN0_TXD
CAN1_RXD
CAN1_RXD
CAN1_TXD
CAN1_TXD
CAN1_TXD
I/O PWM0_0 output/capture input.
I/O PWM0_0 output/capture input.
I/O PWM0_1 output/capture input.
I/O PWM0_1 output/capture input.
I/O PWM0_2 output/capture input.
I/O PWM0_3 output/capture input.
I/O PWM0_4 output/capture input.
I/O PWM0_5 output/capture input.
I/O PWM1_0 output/capture input.
I/O PWM1_1 output/capture input.
I/O PWM1_2 output/capture input.
I/O PWM1_3 output/capture input.
I/O PWM1_4 output/capture input.
I/O PWM1_4 output/capture input.
I/O PWM1_5 output/capture input.
I/O PWM1_5 output/capture input.
PF.9
PA.6
PF.10
PC.10
PC.11
PA.12
PA.11
PA.10
PA.9
PA.8
PA.7
PA.13
PB.6
PA.14
PB.7
PB.7
I
I
I
I
I
I
I
I
I
I
I
I
I
Brake input pin 0 of EPWMB.
Brake input pin 0 of EPWMB.
Brake input pin 1 of EPWMB.
Brake input pin 1 of EPWMB.
Brake input pin 0 of EPWMA.
Brake input pin 1 of EPWMA.
CAN bus receiver0 input.
PB.15
PB.6
PB.14
PA.3
PA.2
PB.12
PB.13
PA.0
CAN0
CAN bus transmitter0 input.
CAN bus receiver1 input.
CAN1
CAN1
PH.0
PA.1
CAN bus receiver1 input.
CAN1
CAN bus transmitter1 input.
CAN bus transmitter1 input.
CAN bus transmitter1 input.
CAN1
PA.6
CAN1
PH.1
June 16, 2016
Page 112 of 228
Rev 1.09
NUC442
CLKO
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
EBI
CLKO
PC.5
PC.12
PC.13
PD.6
PD.7
PA.2
MPF1
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF6
MPF6
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Clock Output Pin.
EBI_A0
EBI address bus bit0.
EBI address bus bit1.
EBI address bus bit10.
EBI address bus bit11.
EBI address bus bit12.
EBI address bus bit13.
EBI address bus bit14.
EBI address bus bit15.
EBI address bus bit16.
EBI address bus bit17.
EBI address bus bit18.
EBI address bus bit19.
EBI address bus bit2.
EBI address bus bit20.
EBI address bus bit21.
EBI address bus bit22.
EBI address bus bit23.
EBI address bus bit24.
EBI address bus bit3.
EBI address bus bit4.
EBI address bus bit5.
EBI address bus bit6.
EBI address bus bit7.
EBI address bus bit8.
EBI address bus bit9.
EBI address/data bus bit 0.
EBI address/data bus bit 1.
EBI address/data bus bit 10.
EBI address/data bus bit 10.
EBI address/data bus bit 11.
EBI address/data bus bit 11.
EBI address/data bus bit 12.
EBI address/data bus bit 12.
EBI address/data bus bit 13.
EBI_A1
EBI_A10
EBI_A11
EBI_A12
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A19
EBI_A2
PA.3
PA.4
PA.5
PA.6
PA.7
PA.8
PA.9
PC.14
PA.10
PA.15
PC.9
PC.10
PC.11
PC.15
PD.0
PD.1
PD.2
PD.3
PD.4
PD.5
PA.11
PA.12
PB.8
PC.4
PB.9
PC.3
PB.10
PC.2
PB.11
EBI_A20
EBI_A21
EBI_A22
EBI_A23
EBI_A24
EBI_A3
EBI_A4
EBI_A5
EBI_A6
EBI_A7
EBI_A8
EBI_A9
EBI_AD0
EBI_AD1
EBI_AD10
EBI_AD10
EBI_AD11
EBI_AD11
EBI_AD12
EBI_AD12
EBI_AD13
June 16, 2016
Page 113 of 228
Rev 1.09
NUC442
EBI
EBI_AD13
EBI_AD14
EBI_AD15
EBI_AD2
PC.1
PB.12
PB.13
PA.13
PA.14
PB.2
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF7
MPF8
MPF3
MPF8
MPF3
MPF8
MPF3
MPF8
MPF8
MPF8
MPF5
MPF5
MPF5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
EBI address/data bus bit 13.
EBI address/data bus bit 14.
EBI address/data bus bit 15.
EBI address/data bus bit 2.
EBI
EBI
EBI
EBI
EBI_AD3
EBI address/data bus bit 3.
EBI
EBI_AD4
EBI address/data bus bit 4.
EBI
EBI_AD5
PB.5
EBI address/data bus bit 5.
EBI
EBI_AD6
PB.4
EBI address/data bus bit 6.
EBI
EBI_AD7
PB.5
EBI address/data bus bit 7.
EBI
EBI_AD8
PB.6
EBI address/data bus bit 8.
EBI
EBI_AD8
PC.7
PB.7
EBI address/data bus bit 8.
EBI
EBI_AD9
EBI address/data bus bit 9.
EBI
EBI_AD9
PC.6
PE.8
EBI address/data bus bit 9.
EBI
EBI_ALE
EBI address latch enable output pin.
EBI interface clock output pin.
EBI chip select 0 enable output pin.
EBI chip select 1 enable output pin.
EBI chip select 2 enable output pin.
EBI chip select 3 enable output pin.
EBI read enable output pin.
EBI
EBI_MCLK
EBI_nCS0
EBI_nCS1
EBI_nCS2
EBI_nCS3
EBI_nRD
PC.0
PE.11
PE.12
PE.13
PE.14
PE.7
EBI
EBI
EBI
EBI
EBI
EBI
EBI_nWR
EBI_nWRH
EBI_nWRL
ECAP0_IC0
ECAP0_IC0
ECAP0_IC1
ECAP0_IC1
ECAP0_IC2
ECAP0_IC2
ECAP1_IC0
ECAP1_IC1
ECAP1_IC2
EPWM0_0
EPWM0_1
EPWM0_2
PE.6
EBI write enable output pin.
EBI
PE.9
EBI write enable output pin.
EBI
PE.10
PC.5
PD.15
PC.4
PD.14
PC.3
PD.13
PA.6
EBI write enable output pin.
ECAP0
ECAP0
ECAP0
ECAP0
ECAP0
ECAP0
ECAP1
ECAP1
ECAP1
EPWMA
EPWMA
EPWMA
Input 0 of enhanced capture unit 0.
Input 0 of enhanced capture unit 0.
Input 1 of enhanced capture unit 0.
Input 1 of enhanced capture unit 0.
Input 2 of enhanced capture unit 0.
Input 2 of enhanced capture unit 0.
Input 0 of enhanced capture unit 1.
Input 1 of enhanced capture unit 1.
Input 2 of enhanced capture unit 1.
I
I
I
I
I
I
PA.5
I
PA.4
I
PA.12
PA.11
PA.10
I/O PWM0_0 output/capture input.
I/O PWM0_1 output/capture input.
I/O PWM0_2 output/capture input.
June 16, 2016
Page 114 of 228
Rev 1.09
NUC442
EPWMA
EPWMA
EPWMA
EPWMB
EPWMB
EPWMB
EPWMB
EPWMB
EPWMB
I2C0
EPWM0_3
EPWM0_4
EPWM0_5
EPWM1_0
EPWM1_1
EPWM1_2
EPWM1_3
EPWM1_4
EPWM1_5
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SDA
I2C2_SCL
I2C2_SCL
I2C2_SDA
I2C2_SDA
I2C3_SCL
I2C3_SCL
I2C3_SDA
I2C3_SDA
I2C4_SCL
I2C4_SCL
I2C4_SCL
I2C4_SDA
I2C4_SDA
I2C4_SDA
I2S0_BCLK
I2S0_DI
PA.9
PA.8
PA.7
PB.6
PB.7
PB.8
PB.9
PB.10
PB.11
PA.15
PD.8
PC.9
PD.9
PG.15
PH.0
PG.14
PH.1
PB.6
PI.7
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF4
MPF2
MPF4
MPF2
MPF3
MPF1
MPF3
MPF2
MPF1
MPF1
MPF1
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF2
MPF3
MPF2
MPF2
MPF3
MPF3
MPF3
MPF3
MPF3
I/O PWM0_3 output/capture input.
I/O PWM0_4 output/capture input.
I/O PWM0_5 output/capture input.
I/O PWM1_0 output/capture input.
I/O PWM1_1 output/capture input.
I/O PWM1_2 output/capture input.
I/O PWM1_3 output/capture input.
I/O PWM1_4 output/capture input.
I/O PWM1_5 output/capture input.
I/O I2C0 clock pin.
I2C0
I/O I2C0 clock pin.
I2C0
I/O I2C0 data input/output pin.
I/O I2C0 data input/output pin.
I/O I2C1 clock pin.
I2C0
I2C1
I2C1
I/O I2C1 clock pin.
I2C1
I/O I2C1 data input/output pin.
I/O I2C1 data input/output pin.
I/O I2C2 clock pin.
I2C1
I2C2
I2C2
I/O I2C2 clock pin.
I2C2
PB.7
PI.8
I/O I2C2 data input/output pin.
I/O I2C2 data input/output pin.
I/O I2C3 clock pin.
I2C2
I2C3
PD.2
PH.3
PD.3
PH.4
PB.0
PD.10
PI.11
PB.1
PD.12
PI.12
PA.5
PA.4
PA.3
PA.6
I2C3
I/O I2C3 clock pin.
I2C3
I/O I2C3 data input/output pin.
I/O I2C3 data input/output pin.
I/O I2C4 clock pin.
I2C3
I2C4
I2C4
I/O I2C4 clock pin.
I2C4
I/O I2C4 clock pin.
I2C4
I/O I2C4 data input/output pin.
I/O I2C4 data input/output pin.
I/O I2C4 data input/output pin.
I2C4
I2C4
I2S0
O
I
I2S0 bit clock pin.
I2S0
I2S0 data input.
I2S0
I2S0_DO
O
O
I2S0 data output.
I2S0
I2S0_LRCK
I2S0 left right channel clock.
June 16, 2016
Page 115 of 228
Rev 1.09
NUC442
I2S0
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
I2S1
ICE_SW
ICE_SW
INT
I2S0_MCLK
I2S1_BCLK
I2S1_BCLK
I2S1_BCLK
I2S1_DI
I2S1_DI
I2S1_DI
I2S1_DO
I2S1_DO
I2S1_DO
I2S1_DO
I2S1_LRCK
I2S1_LRCK
I2S1_LRCK
I2S1_MCLK
I2S1_MCLK
I2S1_MCLK
ICE_CLK
ICE_DAT
INT0
PA.2
PC.1
PG.5
PI.11
PC.0
PG.4
PG.9
PB.15
PC.4
PG.3
PG.8
PC.2
PG.6
PI.12
PB.14
PC.3
PG.7
PG.10
PG.11
PA.0
PB.0
PC.0
PD.0
PE.0
PF.0
MPF3
MPF1
MPF2
MPF2
MPF1
MPF2
MPF2
MPF1
MPF1
MPF2
MPF2
MPF1
MPF2
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF8
MPF8
MPF8
MPF8
MPF8
MPF8
MPF8
MPF8
O
O
O
O
I
I2S0 master clock output pin.
I2S1 bit clock pin.
I2S1 bit clock pin.
I2S1 bit clock pin.
I2S1 data input.
I
I2S1 data input.
I
I2S1 data input.
O
O
O
O
O
O
O
O
O
O
I
I2S1 data output.
I2S1 data output.
I2S1 data output.
I2S1 data output.
I2S1 left right channel clock.
I2S1 left right channel clock.
I2S1 left right channel clock.
I2S1 master clock output pin.
I2S1 master clock output pin.
I2S1 master clock output pin.
Serial wired debugger clock pin
I/O Serial wired debugger data pin
I
I
I
I
I
I
I
I
External interrupt0 input pin.
External interrupt1 input pin.
External interrupt2 input pin.
External interrupt3 input pin.
External interrupt4 input pin.
External interrupt5 input pin.
External interrupt6 input pin.
External interrupt7 input pin.
INT
INT1
INT
INT2
INT
INT3
INT
INT4
INT
INT5
INT
INT6
PG.0
PH.0
INT
INT7
External reset input: active LOW, with an internal pull-
up. Set this pin low reset to initial state.
GPIO
nRESET
nRESET
MFP0
I
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PA.0
PA.0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PA.1
PA.1
PA.10
PA.11
PA.12
PA.13
PA.14
PA.10
PA.11
PA.12
PA.13
PA.14
June 16, 2016
Page 116 of 228
Rev 1.09
NUC442
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PA.15
PA.2
PA.15
PA.2
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PA.3
PA.3
PA.4
PA.4
PA.5
PA.5
PA.6
PA.6
PA.7
PA.7
PA.8
PA.8
PA.9
PA.9
PB.0
PB.1
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
PC.0
PC.1
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PC.2
PC.3
PC.4
PB.0
PB.1
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
PC.0
PC.1
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PC.2
PC.3
PC.4
June 16, 2016
Page 117 of 228
Rev 1.09
NUC442
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PC.5
PC.6
PC.7
PC.8
PC.9
PD.0
PD.1
PD.10
PD.11
PD.12
PD.13
PD.14
PD.15
PD.2
PD.3
PD.4
PD.5
PD.6
PD.7
PD.8
PD.9
PE.0
PC.5
PC.6
PC.7
PC.8
PC.9
PD.0
PD.1
PD.10
PD.11
PD.12
PD.13
PD.14
PD.15
PD.2
PD.3
PD.4
PD.5
PD.6
PD.7
PD.8
PD.9
PE.0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PE.1
PE.1
PE.10
PE.11
PE.12
PE.13
PE.14
PE.15
PE.2
PE.10
PE.11
PE.12
PE.13
PE.14
PE.15
PE.2
PE.3
PE.3
PE.4
PE.4
PE.5
PE.5
PE.6
PE.6
PE.7
PE.7
June 16, 2016
Page 118 of 228
Rev 1.09
NUC442
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PE.8
PE.9
PF.0
PE.8
PE.9
PF.0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PF.1
PF.1
PF.10
PF.11
PF.12
PF.13
PF.14
PF.15
PF.2
PF.10
PF.11
PF.12
PF.13
PF.14
PF.15
PF.2
PF.3
PF.3
PF.4
PF.4
PF.5
PF.5
PF.6
PF.6
PF.7
PF.7
PF.8
PF.8
PF.9
PF.9
PG.0
PG.1
PG.10
PG.11
PG.12
PG.13
PG.14
PG.15
PG.2
PG.3
PG.4
PG.5
PG.6
PG.7
PG.8
PG.9
PH.0
PG.0
PG.1
PG.10
PG.11
PG.12
PG.13
PG.14
PG.15
PG.2
PG.3
PG.4
PG.5
PG.6
PG.7
PG.8
PG.9
PH.0
June 16, 2016
Page 119 of 228
Rev 1.09
NUC442
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
OTG_PHY
OTG_PHY
PH.1
PH.10
PH.11
PH.12
PH.13
PH.14
PH.15
PH.2
PH.3
PH.4
PH.5
PH.6
PH.7
PH.8
PH.9
PI.0
PH.1
PH.10
PH.11
PH.12
PH.13
PH.14
PH.15
PH.2
PH.3
PH.4
PH.5
PH.6
PH.7
PH.8
PH.9
PI.0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PI.1
PI.1
PI.10
PI.11
PI.12
PI.13
PI.14
PI.15
PI.2
PI.10
PI.11
PI.12
PI.13
PI.14
PI.15
PI.2
PI.3
PI.3
PI.4
PI.4
PI.5
PI.5
PI.6
PI.6
PI.7
PI.7
PI.8
PI.8
PI.9
PI.9
USB0_D-
USB0_D+
USB0_D-
USB0_D+
A
A
USB0 differential signal D-.
USB0 differential signal D+.
USB0_OTG
_ID
OTG_PHY
OTG_PHY
USB0_OTG_ID
VBUS
I
USB0 OTG ID pin.
VBUS
A
USB PHY VBUS power input pin.
June 16, 2016
Page 120 of 228
Rev 1.09
NUC442
Voltage reference input for ADC.
ADC
VREF
VREF
A
Note: This pin needs to be connected with
0.1uF/10uF capacitors.
USB PHY VRES ground input pin. Add an 8.2K ohm
resistor to VSSA.
OTG_PHY
OTG_PHY
VRES
VSSA
VRES
VSSA
A
P
Ground pin for digital circuit. Add a Feritte Bead to
digital ground VSS
.
LDO output pin.
LDO_CAP
LDO_CAP
LDO_CAP
LDO_CAP
P
P
Note: This pin needs to be connected with a 1uF
capacitor.
USB_VDD33
_CAP
USB_VDD33_CAP
Internal power regulator output 3.3V decoupling pin.
OPA0
OPA0_N
OPA0_P
OPA0_O
OPA1_N
OPA1_P
OPA1_O
USB0_OTG5V_EN
USB0_OTG5V_ST
CLKO
PF.10
PF.9
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
OPA0
OPA0
PF.11
PF.13
PF.12
PF.14
PB.1
PB.0
PC.5
AVDD
AVSS
VBAT
O
Operational amplifier output pin
OPA1
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
OPA1
OPA1
O
O
I
Operational amplifier output pin
USB0 external VBUS regulator enabled
USB0 external VBUS regulator status
Clock Output Pin.
OTG
OTG
OTHER
POWER
POWER
POWER
POWER
O
P
P
P
A
AVDD
Power supply for internal analog circuit.
Ground pin for digital circuit.
AVSS
VBAT
Battery power input pin.
VBUS
VBUS
USB PHY VBUS power input pin.
Power supply for I/O ports and LDO source for
internal PLL and digital circuit.
POWER
POWER
POWER
VDD
VDD
P
P
P
O
VSS
VSS
Ground pin for digital circuit.
Ground pin for digital circuit. Add a Feritte Bead to
VSSA
VSSA
digital ground VSS
.
PS2D
PS2D
QEI0
QEI0
QEI0
QEI1
QEI1
QEI1
SC0
PS2_CLK
PS2_DAT
QEI0_A
QEI0_B
QEI0_Z
QEI1_A
QEI1_B
QEI1_Z
SC0_CD
PG.3
PG.4
PC.5
PC.4
PC.3
PA.6
PA.5
PA.4
PA.0
MPF1
MPF1
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF2
PS2 clock pin.
I/O PS2 data pin.
I
I
I
I
I
I
I
Quadrature encoder phase A input of QEI Unit 0.
Quadrature encoder phase B input of QEI Unit 0.
Quadrature encoder phase Z input of QEI Unit 0.
Quadrature encoder phase A input of QEI Unit 1.
Quadrature encoder phase B input of QEI Unit 1.
Quadrature encoder phase Z input of QEI Unit 1.
SmartCard0 card detect pin.
June 16, 2016
Page 121 of 228
Rev 1.09
NUC442
SC0
SC0
SC0
SC0
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC1
SC2
SC2
SC2
SC2
SC2
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC3
SC4
SC0_CLK
SC0_DAT
SC0_PWR
SC0_RST
SC1_CD
PA.7
MPF2
MPF2
MPF2
MPF2
MPF2
MPF3
MPF2
MPF3
MPF2
MPF2
MPF3
MPF2
MPF3
MPF2
MPF2
MPF3
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF4
MPF3
MPF1
MPF4
MPF3
MPF1
MPF4
MPF1
MPF4
MPF3
MPF1
MPF4
MPF2
O
SmartCard0 clock pin.
PA.10
PA.9
I/O SmartCard0 data pin.
O
O
I
SmartCard0 power pin.
SmartCard0 reset pin.
PA.8
PC.3
PG.7
PC.1
PG.6
PB.15
PC.0
PG.5
PC.2
PG.4
PB.14
PC.4
PG.3
PA.6
SmartCard1 card detect pin.
SmartCard1 card detect pin.
SmartCard1 clock pin.
SmartCard1 clock pin.
SC1_CD
I
SC1_CLK
SC1_CLK
SC1_DAT
SC1_DAT
SC1_DAT
SC1_PWR
SC1_PWR
SC1_RST
SC1_RST
SC1_RST
SC2_CD
O
O
I/O SmartCard1 data pin.
I/O SmartCard1 data pin.
I/O SmartCard1 data pin.
O
O
O
O
O
I
SmartCard1 power pin.
SmartCard1 power pin.
SmartCard1 reset pin.
SmartCard1 reset pin.
SmartCard1 reset pin.
SmartCard2 card detect pin.
SmartCard2 clock pin.
SC2_CLK
SC2_DAT
SC2_PWR
SC2_RST
SC3_CD
PA.3
O
PA.2
I/O SmartCard2 data pin.
PA.4
O
O
I
SmartCard2 power pin.
SmartCard2 reset pin.
SmartCard3 card detect pin.
SmartCard3 card detect pin.
SmartCard3 clock pin.
SmartCard3 clock pin.
SmartCard3 clock pin.
PA.5
PC.10
PI.12
PA.14
PD.12
PG.9
PA.13
PD.10
PG.8
PA.15
PI.11
PC.9
PD.11
PG.7
PC.12
SC3_CD
I
SC3_CLK
SC3_CLK
SC3_CLK
SC3_DAT
SC3_DAT
SC3_DAT
SC3_PWR
SC3_PWR
SC3_RST
SC3_RST
SC3_RST
SC4_CD
O
O
O
I/O SmartCard3 data pin.
I/O SmartCard3 data pin.
I/O SmartCard3 data pin.
O
O
O
O
O
I
SmartCard3 power pin.
SmartCard3 power pin.
SmartCard3 reset pin.
SmartCard3 reset pin.
SmartCard3 reset pin.
SmartCard4 card detect pin.
June 16, 2016
Page 122 of 228
Rev 1.09
NUC442
SC4
SC4_CLK
SC4_DAT
SC4_PWR
SC4_RST
SC5_CD
PD.0
PC.15
PC.14
PC.13
PA.1
PD.4
PD.3
PH.15
PD.7
PI.2
MPF2
MPF2
MPF2
MPF2
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF1
MPF2
MPF1
MPF2
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
MPF4
O
SmartCard4 clock pin.
SC4
I/O SmartCard4 data pin.
SC4
O
O
I
SmartCard4 power pin.
SmartCard4 reset pin.
SC4
SC5
SmartCard5 card detect pin.
SmartCard5 card detect pin.
SmartCard5 clock pin.
SmartCard5 clock pin.
SC5
SC5_CD
I
SC5
SC5_CLK
SC5_CLK
SC5_DAT
SC5_DAT
SC5_PWR
SC5_PWR
SC5_RST
SC5_RST
SD0_CDn
SD0_CDn
SD0_CDn
SD0_CLK
SD0_CLK
SD0_CLK
SD0_CMD
SD0_CMD
SD0_CMD
SD0_DAT0
SD0_DAT0
SD0_DAT1
SD0_DAT1
SD0_DAT2
SD0_DAT2
SD0_DAT3
SD0_DAT3
SD1_CDn
SD1_CLK
SD1_CMD
SD1_DAT0
O
O
SC5
SC5
I/O SmartCard5 data pin.
I/O SmartCard5 data pin.
SC5
SC5
PD.6
PI.1
O
O
O
O
I
SmartCard5 power pin.
SmartCard5 power pin.
SmartCard5 reset pin.
SmartCard5 reset pin.
SD mode #0 – card detect
SD mode #0 – card detect
SD mode #0 – card detect
SD mode #0– clock;
SC5
SC5
PD.5
PI.0
SC5
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST0
SDHOST1
SDHOST1
SDHOST1
SDHOST1
PD.3
PE.5
PF.6
I
I
PD.7
PE.7
PF.8
O
O
O
SD mode #0– clock;
SD mode #0– clock;
PD.6
PE.6
PF.7
I/O SD mode #0 – command/response
I/O SD mode #0 – command/response
I/O SD mode #0 – command/response
I/O SD mode #0 data line bit 0;
I/O SD mode #0 data line bit 0;
I/O SD mode #0 data line bit 1;
I/O SD mode #0 data line bit 1;
I/O SD mode #0 data line bit 2;
I/O SD mode #0 data line bit 2;
I/O SD mode #0 data line bit 3;
I/O SD mode #0 data line bit 3;
PE.11
PF.5
PE.10
PF.4
PE.9
PF.3
PE.8
PF.2
PC.12
PC.14
PC.13
PD.2
I
SD mode #1 – card detect
SD mode #1– clock;
O
I/O SD mode #1 – command/response
I/O SD mode #1 data line bit 0;
June 16, 2016
Page 123 of 228
Rev 1.09
NUC442
SDHOST1
SDHOST1
SDHOST1
SD1_DAT1
SD1_DAT2
SD1_DAT3
PD.1
PD.0
PC.15
MPF4
MPF4
MPF4
I/O SD mode #1 data line bit 1;
I/O SD mode #1 data line bit 2;
I/O SD mode #1 data line bit 3;
This pad is embedded with “Slew Rate Control”
capability.
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PA.8
PA.9
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 124 of 228
Rev 1.09
NUC442
This pad is embedded with “Slew Rate Control”
capability.
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
PC.0
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
PC.1
This pad is embedded with “Slew Rate Control”
capability.
PC.2
This pad is embedded with “Slew Rate Control”
capability.
PC.3
This pad is embedded with “Slew Rate Control”
capability.
PC.4
This pad is embedded with “Slew Rate Control”
capability.
PC.5
This pad is embedded with “Slew Rate Control”
capability.
PC.6
This pad is embedded with “Slew Rate Control”
capability.
PC.7
This pad is embedded with “Slew Rate Control”
capability.
PC.8
This pad is embedded with “Slew Rate Control”
capability.
PC.9
This pad is embedded with “Slew Rate Control”
capability.
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PD.0
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 125 of 228
Rev 1.09
NUC442
This pad is embedded with “Slew Rate Control”
capability.
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
PD.1
PD.2
PD.3
PD.4
PD.5
PD.6
PD.7
PD.8
PD.9
PD.13
PD.14
PD.15
PE.2
PE.3
PE.4
PE.5
PE.6
PE.7
PE.8
PE.9
PE.10
PE.11
PE.12
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 126 of 228
Rev 1.09
NUC442
This pad is embedded with “Slew Rate Control”
capability.
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
HS
PE.13
PE.14
PF.0
PF.1
PF.2
PF.3
PF.4
PF.5
PF.6
PF.7
PF.8
PF.9
PF.10
PG.7
PG.8
PG.9
PH.5
PH.6
PH.7
PH.8
PH.9
PH.10
PI.3
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
Slew
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
June 16, 2016
Page 127 of 228
Rev 1.09
NUC442
This pad is embedded with “Slew Rate Control”
capability.
Slew
Slew
Slew
Slew
Slew
Slew
HS
HS
HS
HS
HS
HS
PI.4
PI.5
PI.6
PI.7
PI.8
PI.11
Slew
Slew
Slew
Slew
Slew
Slew
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
This pad is embedded with “Slew Rate Control”
capability.
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI2
SPI2
SPI0_CLK
PC.8
PE.5
MPF4
MPF3
MPF4
MPF3
MPF3
MPF4
MPF3
MPF4
MPF3
MPF3
MPF4
MPF3
MPF4
MPF3
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF2
MPF1
O
O
SPI0 serial clock pin.
SPI0 serial clock pin.
SPI0_CLK
SPI0_MISO0
SPI0_MISO0
SPI0_MISO0
SPI0_MISO1
SPI0_MISO1
SPI0_MOSI0
SPI0_MOSI0
SPI0_MOSI0
SPI0_MOSI1
SPI0_MOSI1
SPI0_SS0
PC.6
PE.2
I/O 1st SPI0 MISO (Master In, Slave Out) pin.
I/O 1st SPI0 MISO (Master In, Slave Out) pin.
I/O 1st SPI0 MISO (Master In, Slave Out) pin.
I/O 2nd SPI0 MISO (Master In, Slave Out) pin.
I/O 2nd SPI0 MISO (Master In, Slave Out) pin.
I/O 1st SPI0 MOSI (Master Out, Slave In) pin.
I/O 1st SPI0 MOSI (Master Out, Slave In) pin.
I/O 1st SPI0 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI0 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI0 MOSI (Master Out, Slave In) pin.
I/O 1st SPI0 slave select pin.
PE.6
PC.3
PE.10
PC.7
PE.3
PE.7
PC.4
PE.11
PC.2
PE.4
SPI0_SS0
I/O 1st SPI0 slave select pin.
SPI1_CLK
PD.1
PD.14
PD.0
PD.15
PC.14
PC.15
PF.0
O
O
SPI1 serial clock pin.
SPI1 serial clock pin.
SPI1_CLK
SPI1_MISO0
SPI1_MISO0
SPI1_MISO1
SPI1_MOSI0
SPI1_MOSI0
SPI1_MOSI1
SPI1_SS0
I/O 1st SPI1 MISO (Master In, Slave Out) pin.
I/O 1st SPI1 MISO (Master In, Slave Out) pin.
I/O 2nd SPI1 MISO (Master In, Slave Out) pin.
I/O 1st SPI1 MOSI (Master Out, Slave In) pin.
I/O 1st SPI1 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI1 MOSI (Master Out, Slave In) pin.
I/O 1st SPI1 slave select pin.
PC.13
PC.12
PD.13
PB.3
SPI1_SS0
I/O 1st SPI1 slave select pin.
SPI2_CLK
O
O
SPI2 serial clock pin.
SPI2 serial clock pin.
SPI2_CLK
PG.9
June 16, 2016
Page 128 of 228
Rev 1.09
NUC442
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI2
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI3
SPI2_CLK
PH.6
PB.4
PG.7
PH.7
PB.12
PH.9
PI.12
PB.5
PG.8
PH.8
PB.13
PF.1
PH.10
PB.2
PH.5
PI.11
PA.4
PA.8
PF.3
PI.4
MPF1
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF2
MPF1
MPF1
MPF2
MPF3
MPF1
MPF1
MPF2
MPF3
MPF1
MPF1
MPF3
MPF1
MPF2
MPF2
MPF3
MPF1
MPF1
MPF3
MPF1
MPF2
MPF2
O
SPI2 serial clock pin.
SPI2_MISO0
SPI2_MISO0
SPI2_MISO0
SPI2_MISO1
SPI2_MISO1
SPI2_MISO1
SPI2_MOSI0
SPI2_MOSI0
SPI2_MOSI0
SPI2_MOSI1
SPI2_MOSI1
SPI2_MOSI1
SPI2_SS0
I/O 1st SPI2 MISO (Master In, Slave Out) pin.
I/O 1st SPI2 MISO (Master In, Slave Out) pin.
I/O 1st SPI2 MISO (Master In, Slave Out) pin.
I/O 2nd SPI2 MISO (Master In, Slave Out) pin.
I/O 2nd SPI2 MISO (Master In, Slave Out) pin.
I/O 2nd SPI2 MISO (Master In, Slave Out) pin.
I/O 1st SPI2 MOSI (Master Out, Slave In) pin.
I/O 1st SPI2 MOSI (Master Out, Slave In) pin.
I/O 1st SPI2 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O 1st SPI2 slave select pin.
SPI2_SS0
I/O 1st SPI2 slave select pin.
SPI2_SS0
I/O 1st SPI2 slave select pin.
SPI3_CLK
O
O
O
O
SPI3 serial clock pin.
SPI3 serial clock pin.
SPI3 serial clock pin.
SPI3 serial clock pin.
SPI3_CLK
SPI3_CLK
SPI3_CLK
SPI3_MISO0
SPI3_MISO0
SPI3_MISO0
SPI3_MISO0
SPI3_MISO1
SPI3_MISO1
SPI3_MISO1
SPI3_MOSI0
SPI3_MOSI0
SPI3_MOSI0
SPI3_MOSI0
SPI3_MOSI1
SPI3_MOSI1
SPI3_MOSI1
SPI3_SS0
PA.2
PA.9
PF.4
PI.5
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
I/O 2nd SPI3 MISO (Master In, Slave Out) pin.
I/O 2nd SPI3 MISO (Master In, Slave Out) pin.
I/O 2nd SPI3 MISO (Master In, Slave Out) pin.
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI3 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI3 MOSI (Master Out, Slave In) pin.
I/O 2nd SPI3 MOSI (Master Out, Slave In) pin.
I/O 1st SPI3 slave select pin.
PA.11
PD.8
PI.7
PA.3
PA.10
PF.5
PI.6
PA.12
PD.9
PI.8
PA.5
June 16, 2016
Page 129 of 228
Rev 1.09
NUC442
SPI3
SPI3_SS0
PA.7
PF.2
MPF3
MPF1
MPF1
MPF1
MPF1
MPF1
MPF3
MPF1
MPF1
MPF4
MPF3
MPF3
MPF3
MPF5
MPF3
MPF5
MPF3
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF2
MPF1
I/O 1st SPI3 slave select pin.
I/O 1st SPI3 slave select pin.
I/O 1st SPI3 slave select pin.
SPI3
SPI3_SS0
SPI3
SPI3_SS0
PI.3
T0EX
TM0_EXT
PC.8
PC.7
PC.6
PC.14
PA.0
PA.1
PB.4
PD.1
PB.1
PE.8
PC.6
PE.1
PC.1
PD.11
PA.12
PG.0
PA.11
PF.15
PA.13
PG.1
PA.14
PG.2
PB.5
PF.12
PB.4
PF.11
PB.2
PF.14
PB.3
PF.13
PC.9
PH.2
I
I
I
I
Timer0 external capture input
Timer1 external capture input
Timer2 external capture input
Timer3 external capture input
T1EX
TM1_EXT
T2EX
TM2_EXT
T3EX
TM3_EXT
TAMPER
TAMPER
Timer0
Timer0
Timer1
Timer1
Timer2
Timer2
Timer3
Timer3
UART0
UART0
UART0
UART0
UART0
UART0
UART0
UART0
UART1
UART1
UART1
UART1
UART1
UART1
UART1
UART1
UART2
UART2
TAMPER0
I/O Tamper detect pin 0.
TAMPER1
I/O Tamper detect pin 1.
TM0_CNT_OUT
TM0_CNT_OUT
TM1_CNT_OUT
TM1_CNT_OUT
TM2_CNT_OUT
TM2_CNT_OUT
TM3_CNT_OUT
TM3_CNT_OUT
UART0_CTS
UART0_CTS
UART0_RTS
UART0_RTS
UART0_RXD
UART0_RXD
UART0_TXD
UART0_TXD
UART1_CTS
UART1_CTS
UART1_RTS
UART1_RTS
UART1_RXD
UART1_RXD
UART1_TXD
UART1_TXD
UART2_CTS
UART2_CTS
I/O Timer0 event counter input/toggle output.
I/O Timer0 event counter input/toggle output.
I/O Timer1 event counter input/toggle output.
I/O Timer1 event counter input/toggle output.
I/O Timer2 event counter input/toggle output.
I/O Timer2 event counter input/toggle output.
I/O Timer3 event counter input/toggle output.
I/O Timer3 event counter input/toggle output.
I
I
Clear to Send input pin for UART0.
Clear to Send input pin for UART0.
Request to Send output pin for UART0.
Request to Send output pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Clear to Send input pin for UART1.
Clear to Send input pin for UART1.
Request to Send output pin for UART1.
Request to Send output pin for UART1.
Data receiver input pin for UART1.
Data receiver input pin for UART1.
Data transmitter output pin for UART1.
Data transmitter output pin for UART1.
Clear to Send input pin for UART2.
Clear to Send input pin for UART2.
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
June 16, 2016
Page 130 of 228
Rev 1.09
NUC442
UART2
UART2
UART2
UART2
UART2
UART2
UART3
UART3
UART3
UART3
UART3
UART3
UART3
UART3
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART4
UART5
UART5
UART5
UART5
UART5
UART5
UART5
UART2_RTS
UART2_RTS
UART2_RXD
UART2_RXD
UART2_TXD
UART2_TXD
UART3_CTS
UART3_CTS
UART3_RTS
UART3_RTS
UART3_RXD
UART3_RXD
UART3_TXD
UART3_TXD
UART4_CTS
UART4_CTS
UART4_CTS
UART4_CTS
UART4_RTS
UART4_RTS
UART4_RTS
UART4_RTS
UART4_RXD
UART4_RXD
UART4_RXD
UART4_TXD
UART4_TXD
UART4_TXD
UART5_CTS
UART5_CTS
UART5_RTS
UART5_RTS
UART5_RXD
UART5_RXD
UART5_TXD
PA.15
PF.8
MPF2
MPF1
MPF2
MPF1
MPF1
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF1
MPF3
MPF1
MPF3
MPF3
MPF3
MPF1
MPF3
MPF3
MPF3
MPF3
MPF2
MPF3
MPF3
MPF1
MPF1
MPF2
MPF1
MPF2
MPF1
MPF2
MPF1
O
O
I
Request to Send output pin for UART2.
Request to Send output pin for UART2.
Data receiver input pin for UART2.
Data receiver input pin for UART2.
Data transmitter output pin for UART2.
Data transmitter output pin for UART2.
Clear to Send input pin for UART3.
Clear to Send input pin for UART3.
Request to Send output pin for UART3.
Request to Send output pin for UART3.
Data receiver input pin for UART3.
Data receiver input pin for UART3.
Data transmitter output pin for UART3.
Data transmitter output pin for UART3.
Clear to Send input pin for UART4.
Clear to Send input pin for UART4.
Clear to Send input pin for UART4.
Clear to Send input pin for UART4.
Request to Send output pin for UART4.
Request to Send output pin for UART4.
Request to Send output pin for UART4.
Request to Send output pin for UART4.
Data receiver input pin for UART4.
Data receiver input pin for UART4.
Data receiver input pin for UART4.
Data transmitter output pin for UART4.
Data transmitter output pin for UART4.
Data transmitter output pin for UART4.
Clear to Send input pin for UART5.
Clear to Send input pin for UART5.
Request to Send output pin for UART5.
Request to Send output pin for UART5.
Data receiver input pin for UART5.
Data receiver input pin for UART5.
Data transmitter output pin for UART5.
PC.10
PF.6
I
PC.11
PF.7
O
O
I
PD.7
PH.14
PD.6
PH.13
PD.4
PH.11
PD.5
PH.12
PB.7
PB.13
PC.3
PG.9
PB.6
PB.12
PC.2
PG.8
PB.4
PC.0
PH.0
PB.5
PC.1
PH.1
PB.8
PD.13
PB.9
PD.14
PB.11
PF.0
I
O
O
I
I
O
O
I
I
I
I
O
O
O
O
I
I
I
O
O
O
I
I
O
O
I
I
PB.10
O
June 16, 2016
Page 131 of 228
Rev 1.09
NUC442
UART5
UART5_TXD
USB1_D-
PD.15
PB.2
PB.3
MPF2
MPF3
MPF3
O
A
A
Data transmitter output pin for UART5.
USB1 differential signal D-.
USBIOPHY
USBIOPHY
USB1_D+
USB1 differential signal D+.
USB_VDD33
_CAP
USBPHY
USB_VDD33_CAP
P
Internal power regulator output 3.3V decoupling pin.
USBPHY
USBPHY
USB0_D-
USB0_D-
A
A
USB0 differential signal D-.
USB0_D+
USB0_D+
USB0 differential signal D+.
USB0_OTG
_ID
USBPHY
USBPHY
USBPHY
USB0_OTG_ID
VBUS
I
USB0 OTG ID pin.
VBUS
VRES
A
A
USB PHY VBUS power input pin.
USB PHY VRES ground input pin. Add an 8.2K ohm
resistor to VSSA.
VRES
Ground pin for digital circuit. Add a Feritte Bead to
USBPHY
VSSA
VSSA
A
digital ground VSS
.
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
X32K
X32K
XIN1
XIN1
CAP_DATA0
CAP_DATA1
CAP_DATA2
CAP_DATA3
CAP_DATA4
CAP_DATA5
CAP_DATA6
CAP_DATA7
CAP_HSYNC
CAP_PIXCLK
CAP_SCLK
CAP_SFIELD
CAP_VSYNC
X32K_IN
PD.3
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF5
MPF1
MPF1
MPF1
MPF1
I
I
Image data input bus bit 0.
PD.2
Image data input bus bit 1.
PD.1
I
Image data input bus bit 2.
PD.0
I
Image data input bus bit 3.
PC.15
PC.14
PC.13
PC.12
PD.6
I
Image data input bus bit 4.
I
Image data input bus bit 5.
I
Image data input bus bit 6.
I
Image data input bus bit 7.
I
Image capture interface HSYNC input pin.
Image capture interface pix clock input pin.
Image capture interface sensor clock pin.
Video input interface SFIELD input pin.
Image capture interface VSYNC input pin.
External 32.768 kHz (low-speed) crystal input pin.
External 32.768 kHz (low-speed) crystal output pin.
External 4~24 MHz (high-speed) crystal input pin.
External 4~24 MHz (high-speed) crystal output pin.
PD.7
I
PD.4
O
I
PA.2
PD.5
I
PG.15
PG.14
PG.13
PG.12
I
X32K_OUT
XT1_IN
O
I
XT1_OUT
O
June 16, 2016
Page 132 of 228
Rev 1.09
NUC442
5
BLOCK DIAGRAM
Figure 4.3-1 NuMicro NUC442 Series Block Diagram
June 16, 2016
Page 133 of 228
Rev 1.09
NUC442
6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M4 Core
The Cortex® -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The
processor with optional hardware debug functionality can execute Thumb code and is compatible
with other Cortex® -M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
an exception return. The Cortex® -M4F is a processor with the same capability as the Cortex® -M4
processor and includes floating point arithmetic functionality. The NUC442 series is embedded
with Cortex™-M4F processor. Throughout this document, the name Cortex® -M4 refers to both
Cortex® -M4 and Cortex® -M4F processors. The following figure shows the functional controller of
the processor.
Figure 6.1-1 Cortex® -M4 Block Diagram
Cortex® -M4 processor features:
A low gate count processor core, with low latency interrupt processing that has:
A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual
Banked Stack Pointer (SP)
June 16, 2016
Page 134 of 228
Rev 1.09
NUC442
Hardware integer divide instructions, SDIV and UDIV
Handler and Thread modes
Thumb and Debug states
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt
Service Routine (ISR) entry and exit
Support for ARMv6 big-endian byte-invariant or little-endian accesses
Support for ARMv6 unaligned accesses
Floating Point Unit (FPU) in the Cortex® -M4F processor providing:
32-bit instructions for single-precision (C float) data-processing operations
Combined Multiply and Accumulate instructions for increased precision (Fused
MAC)
Hardware support for conversion, addition, subtraction, multiplication with
optional accumulate, division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single precision registers, also addressable as 16 double-
word registers
Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing. Features include:
External interrupts. Configurable from 1 to 240 (the NUC442 series configured
with 97 interrupts)
Bits of priority, configurable from 3 to 8
Dynamic reprioritization of interrupts
Priority grouping which enables selection of preempting interrupt levels and non-
preempting interrupt levels
Support for tril-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration
between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
Eight memory regions
Sub Region Disable (SRD), enabling efficient use of memory regions
The ability to enable a background region that implements the default memory
map attributes
Low-cost debug solution that features:
Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is
June 16, 2016
Page 135 of 228
Rev 1.09
NUC442
asserted.
Serial Wire Debug Port(SW-DP) debug access
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
and code patches
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode,
Dcode, and System bus interfaces
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB)
interface
Bit-band support that includes atomic bit-band write and read operations.
Memory access alignment
Write buffer for buffering of write data
Exclusive access transfers for multiprocessor systems
June 16, 2016
Page 136 of 228
Rev 1.09
NUC442
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the below listed events. For these reset event flags can
be read by SYS_RSTSTS register.
Hardware Reset
Power-on Reset (POR)
Low level on the nRESEST Pin (nRST)
Watchdag Time-out Reset (WDT)
Low Voltage Reset (LVR)
Brown out Detector Reset BOD_RST)
Software Reset
MCU Reset- SYSRESETREQ(AIRCR[2])
Cortes-M4 Core One-shot Reset – CPURST(IPRSTC[1])
Chip One-shot Reset – CHIPRST(IPRSTC[0])
Note: ISPCON.BS keeps the original value after MCU Reset and CPU Reset.
June 16, 2016
Page 137 of 228
Rev 1.09
NUC442
6.2.3 System Power Distribution
In this chip, power distribution is divided into three segments:
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB
transceiver.
RTC power from VBAT supplies the power to internal regulator which provides a fixed
1.8V power for RTC operation and I/O pins .
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level of the digital power (VDD). The following figure shows the power distribution of the
NuMicro NUC442.
0.1uF
10uF
Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
USB_D+
USB_D-
USB
Transceiver
12-bit ADC
IO Cell
USB_VDD33_CAP
10uF
3.3V
AVDD
AVSS
Operating
Amp.
Analog
Comparator
1.8V
RTC &
80 bytes
backup
register
VSSA
VDD
VBUS
Brown-
out
Detector Reset
Low
Voltage
Temperature
sensor
VBAT to 1.8V
LDO
5V to 3.3V
LDO
SRAM
Flash
Digital Logic
1.8V
PLL
LDO_CAP
1uF
22.1184 MHz
10 kHz
LIRC
POR18
HIRC
Oscillator
Oscillator
4~20 MHz
crystal
oscillator
GPIO except
PA.0 ~PA.1
XT1_OUT
XT1_IN
VDD to 1.8V
LDO
Power On
Control
POR50
IO Cell
NUC442 Power Distribution
Figure 6.2-1 NuMicro NUC442 Power Distribution Diagram
June 16, 2016
Page 138 of 228
Rev 1.09
NUC442
6.2.4 System Memory Map
The NUC442 series provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown in the following table. The detailed register definition, memory
space, and programming detailed will be described in the following sections for each on-chip
peripherals. The NUC442 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0007_FFFF
0x2000_0000 – 0x2000_FFFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128KB)
SRAM Memory Space (16KB)
EXTMEM_BA
External Memory Space (256MB)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_9000 – 0x4000_9FFF
0x4000_C000 – 0x4000_CFFF
0x4000_D000 – 0x4000_DFFF
0x4001_0000 – 0x4001_0FFF
0x4001_9000 – 0x4001_9FFF
0x4003_0000 – 0x4003_0FFF
0x4003_1000 – 0x4003_1FFF
0x5000_8000 – 0x5000_FFFF
SYS_BA
CLK_BA
INT_BA
System Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
USBH_BA
FMC_BA
SDH_BA
EBI_BA
Peripheral DMA Control Registers
USB Host Control Registers
Flash Memory Control Registers
SD HOST Control Registers
External Bus Interface Control Registers
USB device Control Registers
Image Capture interface Registers
CRC Generator Registers
USBD_BA
CAP_BA
CRC_BA
CRYP_BA
Cryptographic Accelerator Registers
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_4000 – 0x4004_4FFF
0x4004_5000 – 0x4004_5FFF
0x4004_6000 – 0x4004_6FFF
0x4004_8000 – 0x4004_8FFF
0x4004_9000 – 0x4004_9FFF
0x4004_D000 – 0x4004_DFFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Analog-Digital-Converter (ADC) Control Registers
Enhance Analog-Digital-Converter (ADC) Control Registers
Analog Comparator Control Registers
OP Amplifier Control Registers
ADC_BA
EADC_BA
ACMP_BA
OPA_BA
I2S0_BA
I2S0 Interface Control Registers
I2S1_BA
I2S1 Interface Control Registers
OTG_BA
TMR01_BA
TMR23_BA
USB OTG
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
June 16, 2016
Page 139 of 228
Rev 1.09
NUC442
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4005_C000 – 0x4005_CFFF
0x4005_D000 – 0x4005_DFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4006_2000 – 0x4006_2FFF
0x4006_3000 – 0x4006_3FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4007_3000 – 0x4007_3FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x4008_2000 – 0x4008_2FFF
0x4008_3000 – 0x4008_3FFF
0x4008_4000 – 0x4008_4FFF
0x4009_0000 – 0x4009_0FFF
0x4009_1000 – 0x4009_1FFF
0x4009_2000 – 0x4009_2FFF
0x4009_3000 – 0x4009_3FFF
0x4009_4000 – 0x4009_4FFF
0x4009_5000 – 0x4009_5FFF
0x400A_0000 – 0x400A_0FFF
0x400A_1000 – 0x400A_1FFF
0x400B_0000 – 0x400B_0FFF
0x400B_1000 – 0x400B_1FFF
0x400B_0000 – 0x400B_0FFF
0x400B_1000 – 0x400B_1FFF
0x400E_0000 – 0x400E_0FFF
PWM0_BA
PWM1_BA
EPWM0_BA
EPWM1_BA
SPI0_BA
SPI1_BA
SPI2_BA
SPI3_BA
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
I2C0_BA
PWM0_0/1/2/3/4/5 Control Registers
PWM1_0/1/2/3/4/5 Control Registers
Enhanced PWM0_0/1/2/3/4/5 Control Registers
Enhanced PWM1_0/1/2/3/4/5 Control Registers
SPI0 with Master/Slave function Control Registers
SPI1 with Master/Slave function Control Registers
SPI2 with Master/Slave function Control Registers
SPI3 with Master/Slave function Control Registers
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
UART4 Control Registers
UART5 Control Registers
I2C0 Interface Control Registers
I2C1_BA
I2C1 Interface Control Registers
I2C2_BA
I2C2 Interface Control Registers
I2C3_BA
I2C3 Interface Control Registers
I2C4_BA
I2C4 Interface Control Registers
SC0_BA
Smartcard0 Control Registers
SC1_BA
Smartcard1 Control Registers
SC2_BA
Smartcard2 Control Registers
SC3_BA
Smartcard3 Control Registers
SC4_BA
Smartcard4 Control Registers
SC5_BA
Smartcard5 Control Registers
CAN0_BA
CAN1_BA
QEI0_BA
QEI1_BA
ECAP0_BA
ECAP1_BA
PS2_BA
CAN0 Bus Control Registers
CAN1 Bus Control Registers
Quadrature Encoder Interface 0 Control Registers
Quadrature Encoder Interface 1 Control Registers
Capture Engine 0 Control Registers
Capture Engine 1 Control Registers
PS/2 interface Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
June 16, 2016
Page 140 of 228
Rev 1.09
NUC442
0xE000_ED00 – 0xE000_ED8F
SCS_BA
System Control Registers
Table 6.2-1 Address Space Assignments for On-Chip Controllers
June 16, 2016
Page 141 of 228
Rev 1.09
NUC442
6.2.5 SRAM Memory Organization
The NUC442 series supports embedded SRAM with total 64 Kbytes size and the SRAM
organization is separated to two banks: SRAM bank0 (16 Kbytes) and SRAM bank1 (48 Kbytes).
Each of these two banks address space and can be accessed simultaneously.
Supports total 64 Kbytes SRAM
Supports byte / half word / word write
Supports SRAM bank0 / SRAM bank1 for independent access
Supports parity error check function on SRAM bank0 full range, and SRAM bank1 first 8
Kbytes range
Supports oversize response error
Supports remap address to 0x1000_0000
AHB interface
controller
SRAM decoder
SRAM decoder
SRAM bank0
SRAM bank1
AHB interface
controller
Figure 6.2-2 SRAM Block Diagram
June 16, 2016
Page 142 of 228
Rev 1.09
NUC442
Figure 6.2-3 shows the SRAM organization of NUC442 series. The bank0 address space is from
0x2000_0000 to 0x2000_3FFF. The bank1 address space is from 0x2000_4000 to 0x2000_FFFF.
The address between 0x2001_0000 to 0x3FFF_FFFF is illegal memory space and chip will enter
hardfault if CPU accesses these illegal memory addresses.
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can access
SRAM bank0 through 0x2000_0000 to 0x2000_3FFF or 0x1000_0000 to 0x1000_3FFF, and
access SRAM bank1 through 0x2000_4000 to 0x2000_FFFF or 0x1000_4000 to 0x1000_FFFF
0x3FFF_FFFF
Reserved
0x2001_0000
0x2000_FFFF
0x1000_FFFF
remapping
48K byte
48K byte
SRAM bank1
SRAM bank1
0x2000_4000
0x2000_3FFF
0x1000_4000
0x1000_3FFF
remapping
16K byte
16K byte
SRAM bank0
SRAM bank0
0x2000_0000
0x1000_0000
64K byte device
64K byte device
Figure 6.2-3 SRAM Memory Organization
First 24 Kbytes of SRAM has byte parity error check function. When CPU is accessing SRAM
address (0x2000_0000 – 0x2000_5FFF), the parity error checking mechanism is dynamic
operating. As bank0 parity error occured, the PERRIF (SYS_SRAM_STATUS[0]) will be asserted
to 1, bank1 parity error occured, the PERRIF (SYS_SRAM_STATUS[1]) will be asserted to 1 and
the SYS_SRAM0_ERRADDR register will record the address with parity error of bank0,
June 16, 2016
Page 143 of 228
Rev 1.09
NUC442
SYS_SRAM1_ERRADDR register will record the address with parity error of bank1 .Chip will
enter interrupt when SRAM parity error occurred if PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1.
When SRAM parity error occured, chip will stop detecting SRAM parity error until user writes 1 to
clear the PERRIF (SYS_SRAM_STATUS[0]) bit.
June 16, 2016
Page 144 of 228
Rev 1.09
NUC442
6.2.6 System Timer (SysTick)
The Cortex® -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_RVR) on the next clock cycle, and then decrement on subsequent clocks. When
the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on
reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_RVR value
rather than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M4 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.7 Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access
the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user
mode if you enable the Configuration and Control Register. Any other user mode access causes a
bus fault. You can access all NVIC registers using byte, halfword, and word accesses unless
otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC
registers and system debug registers are little-endian regardless of the endianness state of the
processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-16 for each interrupt; a higher level corresponds to
a lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
June 16, 2016
Page 145 of 228
Rev 1.09
NUC442
6.2.7.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NUC4xx series. Software can set 16 levels
of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as “0x00” and the lowest priority is denoted as “0xF0” (The 4-LSB always 0). The
default priority of all the user-configurable interrupts is “0x00”. Note that priority “0” is treated as the
fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixed
at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start
address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
The vector table contains the initialization value for the stack pointer on reset, and the entry point
addresses for all exception handlers. The vector number on previous page defines the order of entries
in the vector table associated with exception handler entry as illustrated in previous section.
Exception Type
Reset
Vector Number
Vector Address
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
Priority
1
-3
NMI
2
-2
Hard Fault
Memory Manager Fault
Bus Fault
Usage Fault
Reserved
3
-1
4
Configurable
Configurable
Configurable
Reserved
Configurable
Configurable
Reserved
Configurable
Configurable
5
6
7 ~ 10
11
12
13
14
15
SVCall
0x0000002C
0x00000030
Debug Monitor
Reserved
PendSV
0x00000038
0x0000003C
SysTick
0x00000000 +
Interrupt (IRQ0 ~ IRQ)
16 ~ 144
Configurable
(Vector Number)*4
Table 6.2-2 Exception Model
Interrupt Number
(Bit In Interrupt
Registers)
Vector
Number
Interrupt Name Interrupt Description
0 ~ 15
16
-
-
System exceptions
0
1
BOD_OUT
IRC_INT
Brown-Out low voltage detected interrupt
IRC TRIM interrupt
17
Clock controller interrupt for chip wake-up from power down
state
18
2
PWRWU_INT
19
20
3
4
SRAMF
CLKF
SRAM parity check fail
Clock detection fail
June 16, 2016
Page 146 of 228
Rev 1.09
NUC442
21
5
-
Reserved
22
6
RTC_INT
TAMPER
EINT0
Real time clock interrupt
23
7
TAMPER interrupt
24
8
External signal interrupt from PA.0 pin
External signal interrupt from PB.0 pin
External signal interrupt from PC.0 pin
External signal interrupt from PD.0 pin
External signal interrupt from PE.0 pin
External signal interrupt from PF.0 pin
External signal interrupt from PG.0 pin
External signal interrupt from PH.0 pin
External signal interrupt from PI.0 pin
External signal interrupt from PA[15:1]
External signal interrupt from PB[15:1]
External signal interrupt from PC[15:1]
External signal interrupt from PD[15:1]
External signal interrupt from PE[15:1]
External signal interrupt from PF[15:1]
External signal interrupt from PG[15:1]
External signal interrupt from PH[15:1]
External signal interrupt from PI[15:1]
Reserved
25
9
EINT1
26
10
EINT2
27
11
EINT3
28
12
EINT4
29
13
EINT5
30
14
EINT6
31
15
EINT7
32
16
GPA_INT
GPB_INT
GPC_INT
GPD_INT
GPE_INT
GPF_INT
GPG_INT
GPH_INT
GPI_INT
GPJ_INT
-
33
17
34
18
35
19
36
20
37
21
38
22
39
23
40
24
41
25
42 ~ 47
48
26 ~ 31
32
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
-
Timer 0 interrupt
49
33
Timer 1 interrupt
50
34
Timer 2 interrupt
51
35
Timer 3 interrupt
52 ~ 55
56
36 ~ 39
40
Reserved
PDMA_INT
-
PDMA interrupt
57
41
Reserved
58
42
ADC_INT
-
ADC interrupt
59 ~ 61
62
43 ~ 45
46
Reserved
WDT_INT
WWDG_INT
EADC0
EADC1
Watchdog Timer interrupt
63
47
Window Watchdog Timer interrupt
Enhanced ADC 0 interrupt
Enhanced ADC 1 interrupt
64
48
65
49
June 16, 2016
Page 147 of 228
Rev 1.09
NUC442
66
50
EADC2
Enhanced ADC 2 interrupt
Enhanced ADC 3 interrupt
Reserved
67
51
EADC3
68 ~ 71
72
52 ~ 55
56
-
ACMP_INT
-
Analog Comparator-0 or Comaprator-1 interrupt
Reserved
73 ~ 75
76
57 ~ 59
60
OPA0_INT
OPA1_INT
ICAP0
Analog OP0 interrupt
Analog OP1 interrupt
Internal Capture 0 interrupt
Internal Capture 1 interrupt
Internal Capture 1 interruptPWM0_0 interrupt
PWM0_1 interrupt
PWM0_2 interrupt
PWM0_3 interrupt
PWM0_4 interrupt
PWM0_5 interrupt
PWMA BRK interrupt
QEI0 interrupt
77
61
78
62
79
63
ICAP1
80
64
PWM0_0_INT
PWM0_1_INT
PWM0_2_INT
PWM0_3_INT
PWM0_4_INT
PWM0_5_INT
PWMABRK
QEI0
81
65
82
66
83
67
84
68
85
69
86
70
87
71
88
72
PWM1_0_INT
PWM1_1_INT
PWM1_2_INT
PWM1_3_INT
PWM1_4_INT
PWM1_5_INT
PWMBBRK
QEI1
PWM1_0 interrupt
PWM1_1 interrupt
PWM1_2 interrupt
PWM1_3 interrupt
PWM1_4 interrupt
PWM1_5 interrupt
PWMB BRK interrupt
QEI1 interrupt
89
73
90
74
91
75
92
76
93
77
94
78
95
79
96
80
EPWMA_INT
EPWMABRK
EPWMB_INT
EPWMBBRK
-
EPWMA interrupt
97
81
EPWMA brake interrupt
EPWMB interrupt
98
82
99
83
EPWMB brake interrupt
Reserved
100 ~ 103
104
105
106
107 ~ 111
112
84 ~ 87
88
UDC_INT
UHC_INT
OTG_INT
-
USB device interrupt
USB host interrupt
89
90
USB OTG interrupt
Reserved
91 ~ 95
96
SPI0_INT
SPI0 interrupt
June 16, 2016
Page 148 of 228
Rev 1.09
NUC442
113
97
SPI1_INT
SPI2_INT
SPI3_INT
-
SPI1 interrupt
114
98
SPI2 interrupt
115
99
SPI3 interrupt
116 ~ 119
120
100 ~ 103
104
Reserved
UART0_INT
UART1_INT
UART2_INT
UART3_INT
UART4_INT
UART5_INT
-
UART0 interrupt
UART1 interrupt
UART2 interrupt
UART3 interrupt
UART4 interrupt
UART5 interrupt
Reserved
121
105
122
106
123
107
124
108
125
109
126 ~ 127
128
110 ~ 111
112
I2C0_INT
I2C1_INT
I2C2_INT
I2C3_INT
I2C4_INT
-
I2C0 interrupt
129
113
I2C1 interrupt
130
114
I2C2 interrupt
131
115
I2C3 interrupt
132
116
I2C4 interrupt
133 ~ 135
136
117 ~ 119
120
Reserved
SC0
Smartcard 0 interrupt
Smartcard 1 interrupt
Smartcard 2 interrupt
Smartcard 3 interrupt
Smartcard 4 interrupt
Smartcard 5 interrupt
Reserved
137
121
SC1
138
122
SC2
139
123
SC3
140
124
SC4
141
125
SC5
142 ~ 143
144
126 ~ 127
128
-
CAN0_INT
CAN1_INT
-
CAN0 interrupt
CAN1 interrupt
Reserved
145
129
146 ~ 147
148
130 ~ 131
132
I2S_INT
I2S1_INT
-
I2S interrupt
149
133
I2S1 interrupt
150 ~ 151
152
134 ~ 135
136
Reserved
SDHOST
-
SD host interrupt
Reserved
153
137
154
138
PS2_INT
CAP
PS/2 interrupt
155
139
Image capture interface interrupt
Crypto interrupt
156
140
CRYPTO
June 16, 2016
Page 149 of 228
Rev 1.09
NUC442
Table 6.2-3 Interrupt Number Table
June 16, 2016
Page 150 of 228
Rev 1.09
NUC442
6.2.7.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in the section 6.2.7.3 of TRM.
June 16, 2016
Page 151 of 228
Rev 1.09
NUC442
6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the power-down enable bit (PWR_DOWN_EN) and
Cortex® -M4 core executes the WFI/WFE instruction. After that, chip enters Power-down mode
and wait for wake-up interrupt source triggered to leave Power-down mode. In Power-down
mode, the clock controller turns off the 4~24 MHz external high-speed crystal (HXT) and 22.1184
MHz internal high-speed oscillator (HIRC) to reduce the overall system power consumption. The
following figures show the clock generator and the overview of the clock source control.
The clock generator consists of 6 clock sources as listed below:
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from 4~24
MHz external high speed crystal (HXT) or 22.1184 MHz internal high speed oscillator
(HIRC) ) (PLLFOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
32.768 kHz external low speed crystal oscillator (LXT)
USB PHY’s PLL output clock frequency (PLL2FOUT)
June 16, 2016
Page 152 of 228
Rev 1.09
NUC442
LXTEN (CLK_PWRCTL[1])
X32I
LXT
External 32.768
kHz Crystal
X32O
XT_IN
HXTEN (CLK_PWRCTL[0])
HXT
External 4~24
MHz Crystal
PLLSRC (CLK_PLLCTL[19])
0
1
PLLFOUT
XT_OUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal
22.1184 MHz
Oscillator
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
PLL2CKEN (CLK_PLL2CTL[8])
PLL480M
USB PLL
480Mhz
(OTG PHY)
PLL2FOUT
1/(2*(PLL2DIV+1))
HXT
Legend:
HXT = 4~24 MHz external high speed crystal oscillator (for USBD application, HXT
should be 12 MHz or 24 MHz and be decided in the OTG_PHYCTL[8])
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6.3-1 Clock Generator Block Diagram
June 16, 2016
Page 153 of 228
Rev 1.09
NUC442
HIRC
111
CPUCLK
HCLK
CPU
EBI
PLL2FOUT
LIRC
100
011
010
1/(HCLKDIV+1)
PDMA
PLLFOUT
LXT
ACMP
PCLK
SEL
I2C 0~1
001
000
PCLK
HXT
CAN
HIRC
PCLK
LXT
CLK_CLKSEL0[2:0]
111
010
001
000
TMR 0
TMR 1
TMR 2
TMR 3
HIRC
HXT
1
PLLFOUT
HXT
0
HIRC
CLK_PLLCTL[19]
HIRC
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
PS2
FMC
SYST_CSR[2]
CPUCLK
1/2
1/2
1/2
111
011
010
001
000
HCLK
HXT
LXT
1
0
SysTick
SPI 0
SPI 1
SPI 2
SPI 3
PCLK
1
LIRC
111
HXT
PLLFOUT
0
HIRC
011
PCLK
010
CLK_CLKSEL0[5:3]
HIRC
CLK_CLKSEL1[4:7]
PWM1CH45
PWM1CH23
PWM1CH01
LXT
001
11
HXT
000
PCLK
10
01
00
CLK_CLKSEL2[22:20]
PWM0CH45
PWM0CH23
PWM0CH01
LXT
HXT
CLK_CLKSEL2[14:12]
CLK_CLKSEL2[6:4]
CLK_CLKSEL2[18:16]
CLK_CLKSEL2[10:8]
CLK_CLKSEL2[2:0]
CLKODIV
RTC
CLK_CLKSEL1[29:28]
LIRC
0
LXT
1
HIRC
PCLK
11
10
01
00
CLK_PWRCTL[1]
I2S
PLLFOUT
HXT
LIRC
BOD
11
10
PCLK
LXT
CLK_CLKSEL2[1:0]
1/2048
WDT
01
LIRC
HIRC
PCLK
11
10
11
10
01
00
WWDT
CLK_CLKSEL1[1:0]
PCLK/2048
PLLFOUT
HXT
CLK_CLKSEL1[31:30]
ADC
1/(ADCDIV+1)
USBD
USBH
PLL480M
PLL2FOUT
PLLFOUT
CLK_CLKSEL1[3:2]
0
1
1/(USBHDIV+1)
HIRC
PLLFOUT
HXT
11
01
00
CLK_CLKSEL0[8]
1/(UARTDIV+1)
UART 0-5
Legend:
HXT
LXT
HIRC
LIRC
= 4~24 MHz external high speed crystal oscillator
= 32.768 kHz external low speed crystal oscillator
= 22.1184 MHz internal high speed RC oscillator
= 10 kHz internal low speed RC oscillator
CLK_CLKSEL1[25:24]
Note: Before clock switching, both the pre-selected and newly selected clock
sources must be turned on and stable.
Figure 6.3-2 Clock Generator Global View Diagram
June 16, 2016
Page 154 of 228
Rev 1.09
NUC442
6.3.2 System Clock and SysTick Clock
The system clock has 6 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0 [2:0]). The block diagram
is shown in the following figure.
HCLKSEL (CLK_CLKSEL0[2:0])
HIRC (22.1184 MHz)
111
PLL2FOUT
100
011
010
CPUCLK
HCLK
LIRC (10 kHz)
PLLFOUT
CPU
AHB
1/(HCLKDIV+1)
PCLK
LXT (32.768 kHz)
HXT (4~24 MHz)
HCLKDIV (CLK_CLKDIV[3:0])
001
000
APB
1/(PCLKSEL+1)
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
LXT = 32.768 kHz external low speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and
newly selected clock sources must be turned on and stable.
Figure 6.3-2 System Clock Block Diagram
6.3.3 Clock Monitor
The system clock has auto clock switch function to prevent system clock from being stopped.
There are two clock detectors to monitor CPUCLK and HIRC and they have individual enable and
interrupt control. The clock switch procedure is shown in the following figure. When any one
detector is enabled, the LXT clock is enabled automatically. When the HIRC clock detector is
enabled, the HIRC clock is enabled automatically.
June 16, 2016
Page 155 of 228
Rev 1.09
NUC442
Set SYS_DET_EN
(CLK_CLKDCTL[0])
To enable system
clock detector
SYS_F
(CLK_CLKDCTL[2])
is asserted by detector?
YES
IRC_DET_EN
(CLK_CLKDCTL[8])
Is enable?
Switch system clock to
22.1184MHz
NO
YES
IRC_F
(CLK_CLKDCTL[10])
is asserted by detector?
NO
YES
Switch system clock to
10KHz
Figure 6.3-3 System Clock Switch Procedure
The clock source of SysTick in Cortex® -M4 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in the following figure.
HIRC
1/2
1/2
1/2
111
011
010
001
000
HCLK
HXT
LXT
CPUCLK
1
0
SysTick
SYST_CSR[2]
Legend:
HXT
LXT
HIRC
LIRC
HXT
= 4~24 MHz external high speed crystal oscillator
= 32.768 kHz external low speed crystal oscillator
= 22.1184 MHz internal high speed RC oscillator
= 10 kHz internal low speed RC oscillator
CLK_CLKSEL0[5:3]
Note: Before clock switching, both the pre-selected and newly selected clock
sources must be turned on and stable.
Figure 6.3-4 SysTick Clock Control Block Diagram
June 16, 2016
Page 156 of 228
Rev 1.09
NUC442
6.3.4 Peripherals Clock
The peripherals clock had different clock source switch setting, which depends on the different
peripheral. Please refer the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.7.
6.3.5 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources, and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
10 kHz internal low-speed oscillator(LIRC) clock
32.768 kHz external low-speed crystal (LXT)clock
Peripherals Clock (When these IP adopt 32.768 kHz external or 10 kHz low-speed
oscillator as clock source)
6.3.6 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (CLK_CLKOCTL[3:0]).
When writing 1 to FDIVEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing
0 to FDIVEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches
low state and stay in low state.
CLKOSEL
(CLK_CLKSEL1[29:28])
FDIVCKEN(CLK_APBCLK0[6])
HIRC
(22.1184Mhz)
11
FRQDIV_CLK
HCLK
10
01
00
LXT (32.768 kHz)
HXT (4~24 MHz)
Legend:
HXT
LXT
HIRC
LIRC
= 4~24 MHz external high speed crystal oscillator
= 32.768 kHz external low speed crystal oscillator
= 22.1184 MHz internal high speed RC oscillator
= 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected
clock sources must be turned on and stable.
Figure 6.3-5 Clock Source of Frequency Divider
June 16, 2016
Page 157 of 228
Rev 1.09
NUC442
DIVIDER_EN
(CLK_CLKOCTL[4])
Enable
divide-by-2 counter
FSEL
(CLK_CLKOCTL[3:0])
16 chained
divide-by-2 counter
FRQDIV_CLK
1/22
1/23
…...
1/215 1/216
DIVIDER1*
(CLK_CLKOCTL[5])
1/2
000
000
0
1
:
16 to 1
MUX
0
:
CKO
111
111
1
0
1
Figure 6.3-6 Block Diagram of Frequency Divider
June 16, 2016
Page 158 of 228
Rev 1.09
NUC442
6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NUC442 is equipped with 256/512 Kbytes on-chip embedded flash for application program
memory (APROM) and data flash that can be updated through ISP procedure. In-System-
Programming (ISP) and In-Application-Programming (IAP) enables user to update chip embedded
flash when chip is soldered on PCB. After chip is powered on, Cortex® -M4 CPU fetches code from
APROM or LDROM decided by boot select (CBS) in Config0. By the way, the NUC442 also
provides Data Flash for user to store some application dependent data before chip is powered off.
The NUC442 supports another flexible feature: configurable data flash size. The data flash size is
decided by data flash enable (DFEN) in Config0 and data flash base address (DFBADR) in
Config1. When DFEN is set to 1, the data flash size is zero. When DFEN is set to 0, the APROM
and data flash share 256/512 Kbytes continuous address and the start address of data flash is
defined by (DFBADR) in Config1.
6.4.2 Features
Runs up to 84 MHz with zero wait state for continuous address read access
256/512 Kbytes application program memory (APROM) and data flash
16 Kbytes in system programming (ISP) loader program memory (LDROM)
Configurable Data flash size with 2 Kbytes page erase unit
Flash write protect size with 16 Kbytes per block unit
User Configuration memory with CRC checking
In System Program (ISP) /In Application Program (IAP) to update on chip Flash
June 16, 2016
Page 159 of 228
Rev 1.09
NUC442
6.5 External Bus Interface (EBI)
6.5.1 Overview
The NUC442 series is equipped with an external bus interface (EBI) for external device use. To
minimize the connections between external device and this chip, EBI supports address bus and
data bus multiplex mode. Also, the address latch enable (ALE) signal supported differentiate the
address and data cycle.
In consideration of pin resource, address and Data separate mode can improve the EBI
performance and save the address latch.
6.5.2 Features
External Bus Interface has the following functions:
Four chip selects (nCS[0]~nCS[3])
External devices with max. 32M-byte (8-bit data width)/64M-byte (16-bit data width)
addressable space supported for each chip select (nCS[x])
Variable external bus base clock (MCLK)
8-bit or 16-bit data width are supported for each chip select (nCS[x])
Variable data access time (tACC), address latch enable time (tALE) and address hold
time (tAHD) supported for each chip select (nCS[x])
Address bus and data bus multiplex mode supported to save the address pins
Address bus and data bus separate mode supported to have better performance
Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R) and Read-to-Write(R2W)
June 16, 2016
Page 160 of 228
Rev 1.09
NUC442
6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NUC442 series has up to 114 General Purpose I/O pins shared with other function pins
depending on the chip configuration. These 114 pins are arranged in 8 ports named GPIOA,
GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH. GPIO has 16 pins on echo port.
Each one of the 114 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or quasi-bidirectional mode. After reset, the I/O type of all pins stay in quasi-bidirectional
mode and port data register Px_DOUT[15:0] resets to 0x0000_FFFF. Each I/O pin has a very
weak individual pull-up resistor which is about 110 K~300 K for VDD is from 5.0 V to 2.5 V.
6.6.2 Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Driver and High Sink IO mode
June 16, 2016
Page 161 of 228
Rev 1.09
NUC442
6.7 PDMA Controller (PDMA)
6.7.1 Overview
The direct memory access (PDMA) controller is used to provide high-speed data transfer. The
PDMA controller can module transfers data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controllers have a total of 16 channels and each channel can
perform transfer between memory and peripherals or between memory and memory.
6.7.2 Features
Supports 16 independently configurable channels.
Selectable 2 level of priority (fixed priority or round-robin priority).
Data size of 8, 16, and 32 bits.
Source and destination address increment size by byte, half-word, word or no
increment.
Supports software or peripheral request, and the request type can be single or burst.
Supports Scatter-Gather mode to perform sophisticated transfer through the use of
the descriptor link list table.
June 16, 2016
Page 162 of 228
Rev 1.09
NUC442
6.8 Timer Controller (TIMER)
6.8.1 Overview
The Timer Controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.8.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * CMPDAT
(TIMERx_CMP[23:0])
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TIMERx_CNT (Timer Data Register)
Supports event counting function to count the event from external pin (TM0~TM3)
Supports external capture pin (TM0_EXT~TM3_EXT) for interval measurement
Supports external capture pin (TM0_EXT~TM3_EXT) to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
June 16, 2016
Page 163 of 228
Rev 1.09
NUC442
6.9
PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The NUC442 has two PWM generators － PWM0 and PWM1. PWM0 supports 6 channels PWM
output or 6 channels input capture, and these two functions share the same pins (PWM0_CH0/
PWM0_CH1/PWM0_CH2/PWM0_CH3/PWM0_CH4/PWM0_CH5). PWM1 also supports
6
channels PWM output or 6 channels input capture, and these two functions share the same pins
(PWM1_CH0/PWM1_CH1/PWM1_CH2/ PWM1_CH3/PWM1_CH4/PWM1_CH5).
The PWM generator has 16-bit PWM counter and comparator, and the PWM counter supports
edge-aligned or center-aligned operating types. The PWM generator supports two standard PWM
output modes: Independent output mode and Complementary output mode with 8-bit Dead-zone
generator. In addition, PWM generator supports two special output mode: Synchronize mode and
Group mode. It also has 8-bit prescaler and clock divider with 5 divided frequencies (1, 1/2, 1/4,
1/8, 1/16) to support wide range clock frequency of PWM counter. For PWM output control unit, it
supports polarity output function, independent pin mask function and brake function. PWM
generator can send ADC start trigger signal if one of the following conditions happened: PWM
counter period point, PWM counter center point, PWM output rising edge and PWM output falling
edge.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
6.9.2 Features
6.9.2.1 PWM function features
Supports 12 PWM output channels with 16-bit resolution
Supports 8-bit prescaler and clock divider
Supports period point, center point and edge point PWM Interrupt
Supports One-shot or Auto-reload PWM counter operation mode
Supports Edge-aligned or Center-aligned PWM counter type
Supports 8-bit dead zone with maximum divided 16 prescaler
Supports brake function source from pin or comparator output
Supports mask function for each PWM pin
Supports independent, complementary, synchronized and group PWM output mode
Supports trigger ADC start conversion at PWM counter period point, PWM counter
center point, PWM output rising edge and PWM output falling edge
6.9.2.2 Capture Function Features
Supports 12 Capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports capture interrupt
June 16, 2016
Page 164 of 228
Rev 1.09
NUC442
6.10 Enhanced PWM Generator (EPWM)
6.10.1 Overview
This device is built in two PWM units with the same architecture which function is specially designed
for driving motor control applications. Using the PWM, input capture module and QEI controller with
proper control flow by software can easily drive the 3-phase Brushless DC motor, 3-phase AC
induction motor and DC motor.
6.10.2 Features
Each unit supports the features below:
Three independent 16-bit PWM duty control units with maximum 6 port pins:
3 independent PWM output:
EPWM0_CH0, EPWM0_CH2 and EPWM0_CH4 for Unit 0
EPWM1_CH0, EPWM1_CH2 and EPWM1_CH4 for Unit 1
3 complementary PWM pairs, with each pin in a pair mutually complement to each
other and capable of programmable dead-time insertion:
(EPWMx_CH0, EPWMx_CH1), (EPWM_CMPDAT2, EPWMx_CH3) and
(EPWMx_CH4, EPWMx_CH5) where x=0~1.
3 synchronous PWM pairs, with each pin in a pair in-phase:
(EPWMx_CH0, EPWMx_CH1), (EPWMx_CH2, EPWMx_CH3) and (EPWMx_CH4,
EPWMx_CH5) where x=0~1
Group control bits:
EPWMx_CH2 and EPWMx_CH4 are synchronized with EPWMx_CH0
Supports Edge aligned mode and Center aligned mode
Programmable dead-time insertion between complementary paired PWMs
Each pin of EPWMx_CH0 to EPWMx_CH5 has independent polarity setting control
Mask output control for Electrically Commutated Motor operation
Tri-state output at reset and brake state
Hardware brake protection
Two Interrupt Sources:
Interrupt is synchronously requested at PWM frequency when up/down counter
comparison matched (edge and center aligned modes) or underflow (center aligned
mode).
Interrupt is requested when external brake pins asserted
PWM signals before polarity control stage are defined in the view of positive logic. The PWM
ports is active high or active low are controlled by polarity control register.
High Source/Sink current.
After CPU reset the internal output of the each PWM channels depends on the polarity setting. The
interval between successive outputs is controlled by a 16–bit up/down counter which uses a software
selectable clock source with configurable internal clock pre-scalar as its input. The PWM counter clock
has the frequency as the clock source FPWM = EPWMx_CLK/Pre-scalar; Here the EPWMx_CLK
synchronized with CPU clock HCLK.
June 16, 2016
Page 165 of 228
Rev 1.09
NUC442
PWM Generator
PWM_CH0 & PWM_CH1
Set complementary &
Dead-time insertion
EPWM_CH0
EPWM_CH1
PWM_CH0
Freq/Duty
PWM
timebase
control
PWM_CH2 & PWM_CH3
Set complementary &
Dead-time insertion
EPWM_CH2
EPWM_CH3
Polarity
&
3-state
Control
Mask
&
Brake
Control
PWM_CH2
Freq/Duty
PWM
control
logic
EPWM_CH4
EPWM_CH5
PWM_CH4 & PWM_CH5
Set complementary &
Dead-time insertion
PWM_CH4
Freq/Duty
Brake
control
Brake Condition
Figure 6.10-1 PWM Block Diagram
June 16, 2016
Page 166 of 228
Rev 1.09
NUC442
6.11 Enhanced Input Capture Timer
6.11.1 Overview
This device provides up to two units of Input Capture Timer/Counter which capture function can detect
the digital edge changed signal at channel inputs. Each unit has three input capture channels. The
timer/counter is equipped with up counting, reload and compare-match capabilities.
6.11.2 Features
Up to two Input Capture Timer/Counter Units, Input Capture 0 and Input Capture 1.
Each unit has own interrupt vector.
24-bit Input Capture up-counting timer/counter
With noise filter in front end of input ports.
Edge detector with three options:
Rising edge detection
Falling edge detection
Both edge detection
Each input channel is supported one capture counter hold register.
Captured event reset/reload capture counter option.
Supports compare-match function.
June 16, 2016
Page 167 of 228
Rev 1.09
NUC442
6.12 Quadrature Encoder Interface (QEI)
6.12.1 Overview
There are two QEI controllers in this device. The Quadrature Encoder Interface (QEI) decodes speed
of rotation and motion sensor information. It can be used in any application that uses a quadrature
encoder for feedback.
6.12.2 Features
Up to two QEI controllers, QEI0 and QEI1.
Two QEI phase inputs, QEA and QEB; One Index input.
One QEI control register (QEI_CTL) and one QEI Status Register (QEI_STATUS)
Four Quadrature encoder pulse counter operation modes:
Mode0: x4 free-counting mode
Mode1: x2 free-counting mode
Mode2: x4 compare-counting mode
Mode3: x2 compare-counting mode
Encoder Pulse Width measurement mode
June 16, 2016
Page 168 of 228
Rev 1.09
NUC442
6.13 Watchdog Timer (WDT)
6.13.1 Overview
The Watchdog Timer is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer
supports the function to wake-up system from Idle/Power-down mode.
6.13.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) and the time-out interval is 104 ms ~ 26.3168 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period, including (1024+2)、(128+2) 、
(16+2) or (1+2) WDT_CLK reset delay period.
Supports force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(Config0[31] watchdog enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function when WDT clock source is selected as
10 kHz low-speed oscillator.
June 16, 2016
Page 169 of 228
Rev 1.09
NUC442
6.14 Window Watchdog Timer (WWDT)
6.14.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period
to prevent software run to uncontrollable status by any unpredictable condition.
6.14.2 Features
6-bit down counter (WWDT_CNT[5:0]) and 6-bit compare value (WWDT_CTL[21:16]) to
make the window period flexible
Selectable maximum 11-bit WWDT clock prescale (WWDT_CTL[11:8]) to make WWDT
time-out interval variable
June 16, 2016
Page 170 of 228
Rev 1.09
NUC442
6.15 Real Time Clock (RTC)
6.15.1 Overview
The Real Time Clock (RTC) controller provides the real time clock and calendar information. The
clock source of RTC controller is from an external 32.768 kHz low-speed crystal which connected
at pins X32I and X32O (refer to pin Description) or from an external 32.768 kHz low-speed
oscillator output fed at pin X32I. The RTC controller provides the real time clock (hour, minute,
second) in RTC_TIME (RTC Time Loading Register) as well as calendar information (year,
month, day) in RTC_CAL (RTC Calendar Loading Register). It also offers RTC alarm function that
user can preset the alarm time in RTC_TALM (RTC Time Alarm Register) and alarm calendar in
RTC_CALM (RTC Calendar Alarm Register). The data format of RTC time and calendar message
are all expressed in BCD (Binary Coded Decimal) format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic
RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1
second which are selected by RTC_TICK (RTC_TICK[2:0] Time Tick Register). When real time
and calendar message in RTC_TIME and RTC_CAL are equal to alarm time and calendar
settings in RTC_TALM and RTC_CALM, the ALMIF (RTC_INTSTS [0] RTC Alarm Interrupt Flag)
is set to 1 and the RTC alarm interrupt signal is generated if the ALMIEN (RTC_INTEN [0] Alarm
Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or
Power-down mode if the corresponding interrupt enable bit (ALMIEN or TICKIEN) is set to 1
before chip enters Idle or Power-down mode.
6.15.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counter in RTC_WEEKDAY register
Frequency of RTC clock source compensated by the RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
Supports 96 bytes spare registers to store user’s important information
Supports a tamper detect function to detect the transition of tamper detect pin
June 16, 2016
Page 171 of 228
Rev 1.09
NUC442
6.16 UART Interface Controller (UART)
The NUC442 provides up to six channels of Universal Asynchronous Receiver/Transmitters
(UART). UART0 supports High-speed UART and UART1~5 perform Normal Speed UART,
besides, all the UART channels support flow control function.
6.16.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR Function, LIN
master/slave mode function and RS-485 mode functions. Each UART channel supports seven
types of interrupts including transmitter FIFO empty interrupt (INT_THRE), receiver threshold
level reaching interrupt (INT_RDA), line status interrupt (parity error or framing error or break
interrupt) (INT_RLS), receiver buffer time-out interrupt (INT_TOUT), MODEM/Wake-up status
interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR) and LIN interrupt (INT_LIN).
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART1~2 are
equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well
as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur
while receiving data. The UART includes a programmable baud rate generator that is capable of
dividing clock input by divisors to produce the serial clock that transmitter and receiver need.
All of the controllers support auto-flow control function that uses two low-level signals, /CTS
(clear-to-send) and /RTS (request-to-send), to control the flow of data transfer between the UART
and external devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to receive
data until the UART asserts /RTS to external device. When the number of bytes in the RX FIFO
equals the value of RTSTRGLV (UART_FIFO [19:16]), the /RTS is de-asserted. The UART sends
data out when UART controller detects /CTS is asserted from external device. If a valid asserted
/CTS is not detected the UART controller will not send data out.
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UART_FUNCSEL[1]) to enable IrDA function). The SIR specification defines a short-
range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop
bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer
delay between transmission and reception. This delay feature must be implemented by software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN
mode is selected by setting the LIN_EN bit (UART_FUNCSEL[0]). In LIN mode, one start bit and
8-bit data format with 1-bit stop bit are required in accordance with the LIN standard.
For the NUC442 series, another alternate function of UART controllers is RS-485 9-bit mode
function, and direction control provided by RTS pin to implement the function by software. The
RS-485 mode is selected by setting the UART_FUNCSEL register to select RS-485 function. The
RS-485 driver control is implemented using the RTS control signal from an asynchronous serial
port to enable the RS-485 driver. In RS-485 mode, many characteristics of the RX and TX are the
same as UART.
6.16.2 Features
Full duplex, asynchronous communications
Separate receive / transmit 64/16 bytes (UART0/UART1~5) entry FIFO for data payloads
June 16, 2016
Page 172 of 228
Rev 1.09
NUC442
Supports hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function
Supports 8-bit receiver buffer time-out detection function
UART0~5 can be served by the DMA controller
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Support for 3-/16-bit duration
Supports LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
Supports master identifier field parity generation and slave identifier field parity check
function
Supports LIN slave header reception function
Supports LIN slave automatic resynchronization function
Supports LIN slave header error detect function
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by RTS pin
June 16, 2016
Page 173 of 228
Rev 1.09
NUC442
6.17 Smart Card Host Interface (SC)
6.17.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.17.2 Features
ISO-7816-3 T = 0, T = 1 compliant.
EMV2000 compliant
Up to six ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads.
Programmable transmission clock frequency.
Programmable receiver buffer trigger level.
Programmable guard time selection (11 ETU ~ 267 ETU).
A 24-bit and two 8 bit counters for Answer to Request (ATR) and waiting times
processing.
Supports auto inverse convention function.
Supports transmitter and receiver error retry and error number limitation function.
Supports hardware activation sequence process.
Supports hardware warm reset sequence process.
Supports hardware deactivation sequence process.
Supports hardware auto deactivation sequence when detected the card removal.
Supports UART mode
Full duplex, asynchronous communications.
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
Supports programmable baud rate generator for each channel.
Supports programmable receiver buffer trigger level.
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SC_EGT register.
Programmable even, odd or no parity bit generation and detection.
Programmable stop bit, 1 or 2 stop bit generation
June 16, 2016
Page 174 of 228
Rev 1.09
NUC442
6.18 PS/2 Device Controller (PS2D)
6.18.1 Overview
The PS/2 device controller provides basic timing control for PS/2 communication. All
communication between the device and the host is managed through the CLK and DATA pins.
Unlike PS/2 keyboard or mouse device controller, the received/transmit code needs to be
translated as meaningful code by firmware. The device controller generates the CLK signal after
receiving a request to send, but host has ultimate control over communication. DATA sent from
the host to the device is read on the rising edge and DATA sent from device to the host is change
after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software can select 1 to
16 bytes for a continuous transmission.
6.18.2 Features
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
June 16, 2016
Page 175 of 228
Rev 1.09
NUC442
6.19 I2C Serial Interface Controller (Master/Slave)
6.19.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the
following figure for more details about I2C Bus Timing.
Repeated
START
STOP START
STOP
SDA
SCL
Figure 6.19-1 I2C Bus Timing
The device on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit
I2CEN (I2C_CTL[6]) should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA
and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O
pins are used as I2C port, user must set the pins function to I2C in advance.
June 16, 2016
Page 176 of 228
Rev 1.09
NUC442
6.19.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus are:
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to stretch and
un-stretch serial transfer
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up
and time-out counter overflows.
Programmable divider allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Supports address match wakeup function
June 16, 2016
Page 177 of 228
Rev 1.09
NUC442
6.20 Serial Peripheral Interface (SPI)
6.20.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NUC442 series contains up to four sets of SPI controllers performing a
serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial
conversion on data transmitted to a peripheral device. Each controller can be configured as a
master or a slave device.
The SPI controller supports 2-bit Transfer mode to connect 2 off-chip slave devices at the same
time. This controller also supports the PDMA function to access the data buffer and also supports
Dual and Quad I/O Transfer mode.
6.20.2 Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports byte reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
June 16, 2016
Page 178 of 228
Rev 1.09
NUC442
6.21 I2S Controller (I2S)
6.21.1 Overview
The I2S controller consists of IIS protocol to interface with external audio CODEC. Two 8 word
deep FIFO for read path and write path respectively and is capable of handling 8/16/24/32 bits
word sizes. DMA controller handles the data movement between FIFO and memory.
6.21.2 Features
Operates as either Master or Slave
Capable of handling 8, 16, 24 and 32 bits word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Two DMA requests, one for transmitting and the other for receiving
June 16, 2016
Page 179 of 228
Rev 1.09
NUC442
6.22 USB 2.0 Device Controller (USBD)
6.22.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control
endpoint. These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device
controller has a built-in DMA to relieve the load of CPU.
6.22.2 Features
USB Specification reversion 2.0 compliant
Supports 12 configurable endpoints in addition to Control Endpoint
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction
Three different operation modes of an in-endpoint － Auto Validation mode, Manual
Validation mode, Fly mode
Supports DMA operation
4092 Bytes Configurable RAM used as endpoint buffer
Supports Endpoint Maximum Packet Size up to 1024 bytes
June 16, 2016
Page 180 of 228
Rev 1.09
NUC442
6.23 USB 1.1 Host Controller (USBH)
6.23.1 Overview
The Universal Serial Bus (USB) is a low-cost, low-to-middle-speed peripheral interface standard
intended for modem, scanners, PDAs, keyboards, mice, and other devices that do not require a
high-bandwidth parallel interface. The USB is a 4-wire serial cable bus that supports serial data
exchange between a Host Controller and one or several peripheral devices. The attached
peripherals share USB bandwidth through a host-scheduled, token-based protocol. Peripherals
may be attached, configured, used, and detached, while the host and other peripherals continue
operation (i.e. hot plug and unplug is supported).
A major design goal of the USB standard is to allow flexible, plug-and-play networks of USB
devices. In any USB network, there will be only one host, but there can be many devices and
hubs.
6.23.2 Features
Fully compliant with USB Revision 1.1 specification.
Open Host Controller Interface (OHCI) Revision 1.0 compatible.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports two USB host ports:
USB Host port 1 is shared with USB device (OTG function).
USB Host port 2 is an independent host port. The port 2 host function can work
even port1 functioned used as an USB device.
Built-in DMA for real-time data transfer.
Multiple low power modes for efficient power management.
June 16, 2016
Page 181 of 228
Rev 1.09
NUC442
6.24 USB OTG Controller
6.24.1 Overview
The USB OTG controller is used to interface USB OTG PHY and USB controller, either USB host
controller or USB device controller. The USB OTG controller supports the HNP and SRP protocols
defined in the On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3 Specification.
Combining USB host controller, USB device controller and USB OTG controller can act as Host-only,
Device-only, ID-dependent or OTG Device through setting. Host-only mode can support both full-
speed and low-speed. Device-only mode only supports high-speed. ID-dependent mode and OTG
Device mode supporting speed is dependent on current role.
6.24.2 Features
Built-in OTG PHY to support protocols defined in On-The-GO Supplement Rev 1.3 Specification,
Including:
HNP: Host Negotiation Protocol
SRP: Session Request Protocol
Configurable to operate as:
Host-only
Device-only
ID dependent device
OTG device: A-device or B-device, depending on the ID pin status.
June 16, 2016
Page 182 of 228
Rev 1.09
NUC442
6.25 Controller Area Network (CAN)
6.25.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version
2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to
the physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the
Message RAM. All functions concerning the handling of messages are implemented in the
Message Handler. These functions include acceptance filtering, the transfer of messages
between the CAN Core and the Message RAM, and the handling of transmission requests as well
as the generation of the module interrupt.
The register set of the C_CAN can be accessed directly by the software through the module
interface. These registers are used to control/configure the CAN Core and the Message Handler
and to access the Message RAM.
6.25.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
June 16, 2016
Page 183 of 228
Rev 1.09
NUC442
6.26 Secure Digital Host Controller
6.26.1 Overview
The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit
provides a DMA (Direct Memory Access) function for SD to exchange data between system
memory and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The
SDHOST controller can support SD/SDHC and cooperated with DMAC to provide a fast data
transfer between system memory and cards.
6.26.2 Features
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Supports single DMA channel.
Supports hardware Scatter-Gather function.
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC card.
Completely asynchronous design for Secure Digital with two clock domains, HCLK and
Engine clock, note that frequency of HCLK should be higher than the frequency of
peripheral clock.
June 16, 2016
Page 184 of 228
Rev 1.09
NUC442
6.27 Cryptographic Accelerator
6.27.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator
(PRNG) core and supports AES, DES/TDES, and SHA algorithms.
The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation.
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB,
OFB, CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode.
The DES/TDES accelerator is an implementation fully compliant with the DES and Triple DES
encryption/decryption algorithm. The DES/TDES accelerator supports ECB, CBC, CFB, OFB, and
CTR mode.
The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224 and SHA-
256.
6.27.2 Features
PRNG
Supports 64 bits, 128 bits , 192 bits, and 256 bits random number generation
AES
Supports FIPS NIST 197
Supports SP800-38A and addendum
Supports 128, 192, and 256 bits key
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB , CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode
Supports key expander
DES
TDES
Supports FIPS 46-3
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB, and CTR mode
Supports FIPS NIST 800-67
Implemented according to the X9.52 standard
Supports two keys or three keys mode
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB, and CTR mode
SHA
Supports FIPS NIST 180, 180-2
Supports SHA-160, SHA-224, and SHA-256
June 16, 2016
Page 185 of 228
Rev 1.09
NUC442
6.28 Image Capture Interface (ICAP)
6.28.1 Overview
The Image Capture Interface is designed to capture image data from a sensor. After capturing or
fetching image data, it will process the image data, and then FIFO outputs them into a frame buffer.
6.28.2 Features
8-bit RGB565 sensor
8-bit YUV422 sensor
Supports CCIR601 YCbCr color range scale to full YUV color range
Supports 4 packaging format for packet data output: YUYV, Y only, RGB565, RGB555
Supports YUV422 planar data output
Supports the CROP function to crop input image to the required size for digital
application.
Supports the down scaling function to scale input image to the required size for digital
application.
Supports frame rate control
Supports field detection and even/odd field skip mechanism
Supports packet output dual buffer control through hardware buffer controller
Supports negative/sepia/posterization color effect
Supports two independent capture interfaces
June 16, 2016
Page 186 of 228
Rev 1.09
NUC442
6.29 CRC Controller
6.29.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable
polynomial settings.
6.29.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
June 16, 2016
Page 187 of 228
Rev 1.09
NUC442
6.30 Analog-to-Digital Converter (ADC)
6.30.1 Overview
The NUC442 contains one 12-bit successive approximation analog-to-digital converters (SAR A/D
converter) with 12 external input channels. The A/D converter supports three operation modes －
Single Mode, Single-cycle Scan Mode and Continuous Scan Mode. The A/D converters can be
started by software, external pin (STADC) or PWM trigger.
6.30.2 Features
Analog input voltage range: 0~Analog Supply Voltage from AVDD
12-bit resolution and 10-bit accuracy is guaranteed
Up to 12 single-end analog input channels or 6 differential analog input channels.
Supports conversion rate 400 kSPS while VREF is between 2.5V~5.5V and up to 800
kSPS while VREF is between 4.5V~5.5V in single-end mode.
Supports conversion rate 800 kSPS while VREF is between 2.5V~5.5V and up to 1 MSPS
while VREF is between 3.0V~5.5V in differential mode.
Three operation modes
Single Mode: A/D conversion is performed one time on a specified channel
Single-cycle Scan Mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
Continuous Scan Mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion
An A/D conversion can be started by
Software write 1 to A/D conversion start bit (ADST)
External pin (STADC)
PWM trigger with optional start delay period
Conversion results are held in data registers for each channel with valid and overrun
indicators
Conversion result can be compared with specified value and user can select whether to
generate an interrupt when conversion result is larger than, smaller than or equal to the
compare register setting
Supports internal source: internal band-gap voltage, and internal temperature sensor
output voltage
Supports PDMA transfer
June 16, 2016
Page 188 of 228
Rev 1.09
NUC442
6.31 12-bit Analog-to-Digital Converter (Enhanced ADC)
6.31.1 Overview
The NUC442 series contains two 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 16 external input channels and 5 internal channels.
The two A/D converters ADC0 and ADC1 can be sampled with simultaneous or single
sampling mode. The A/D converters can be started by software, PWM triggers, timer0~3
overflow pulse triggers, ADINT0, ADINT1 interrupt EOC pulse trigger and external pin
(STADC) input signal.
6.31.2 Features
Enhanced ADC mode with dual ADC
Analog input voltage range: 0~Analog Supply Voltage from AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Two SAR ADC converters, including ADC0 and ADC1
Up to 16 single-end analog external input channels
Up to 5 internal channels; ADC0 supports four internal channels, including temperature
sensor, band-gap voltage, analog ground and OP amplifier 0; ADC1 supports only OP
amplifier 1
Four ADC interrupts with individual interrupt vectors
Supports conversion rate 400 kSPS while VREF is between 2.5V~5.5V and up to 800 kSPS
while VREF is between 4.5V~5.5V in single-end mode.
Double buffer for channel 0~3 of each ADC0 and ADC1
Two operating modes:
Single sampling mode: two ADC converters run at normal operation.
Simultaneous sampling mode: Allow two ADC converters can be sampled
simultaneously.
An A/D conversion can be started by:
Software write 1 to A/D start conversion bit (SWTRGx, x = 0~15)
External pin (STADC)
Timer0~3 overflow pulse triggers
ADINT0 and ADINT1 interrupt EOC pulse triggers
PWM triggers
Conversion results are held in 16 data registers with valid and overrun indicators.
Each of SAMPLE00~SAMPLE07 ADC control logic modules configurable for ADC0
converter channel ADC0_CH0~ADC0_CH7 and trigger source.
Each of SAMPLE10~SAMPLE17 ADC control logic modules configurable for ADC1
converter channel ADC1_CH0~ADC1_CH7 and trigger source.
ADC0 channel 8, 9, 10, 11 input sources as band-gap voltage, temperature sensor, analog
ground and OP amplify 0.
ADC1 channel 8 as OP amplify 1.
June 16, 2016
Page 189 of 228
Rev 1.09
NUC442
Note: if user configures bit 8 of VREFCR register to 1, the NUC442 ADC becomes Enhanced
ADC mode with dual ADC, if user configure bit 8 of VREFCR register to 0, the NUC442 ADC
become basic ADC mode with single ADC
June 16, 2016
Page 190 of 228
Rev 1.09
NUC442
6.32 Analog Comparator Controller (ACMP)
6.32.1 Overview
The NUC442 contains three comparators which can be used in a number of different
configurations. The comparator output is a logical one when positive input is greater than negative
input; otherwise, the output is zero. Each comparator can be configured to cause an interrupt
when the comparator output value changes. The block diagram is shown below.
6.32.2 Features
Analog input voltage range: 0 ~ AVDD
Supports hysteresis function
Selectable input sources of positive input and negative input
One ACMP interrupt vector for all comparators
June 16, 2016
Page 191 of 228
Rev 1.09
NUC442
6.33 OP Amplifier
6.33.1 Overview
This device integrated two operational amplifiers. It can be enabled through OPENx (OPA_CTL[1:0])
bits. User can measure the outputs of the OP amplifier as the OP amplifier output to the integrated
EADC channel EADC0_11 and EADC1_8, where digital results can be taken.
6.33.2 Features
Analog input voltage range: 0~AVDD.
Two analog OP amplifiers
Software enabled to connect OP amplifier 0,1 outputs to A/D converter channel AINA[B], AINB[8]
respectively
Schmitt trigger buffer outputs of OP amplifier0, 1 can be as one of the comparator interrupt
sources.
OP amplifier 0 output can be an optional input source of integrated comparator 0 positive input
OP amplifier 1 output can be an optional input source of integrated comparator 1 positive input
June 16, 2016
Page 192 of 228
Rev 1.09
NUC442
7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Symbol Parameter
Min
-0.3
Max
+7.0
Unit
V
DC Power Supply
Battery Power Supply
Input Voltage
VDD VSS
VBAT
+2.4
+5.0
V
VIN
VSS - 0.3
VDD + 0.3
V
1/tCLCL
TA
Oscillator Frequency
4
24
MHz
Operating Temperature
-40
+105
TST
IDD
ISS
Storage Temperature
-55
+150
400
400
35
Maximum Current into VDD
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by an I/O pin
Maximum Current sourced by an I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
IIO
240
240
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the
life and reliability of the device.
June 16, 2016
Page 193 of 228
Rev 1.09
NUC442
7.2 DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25 )
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VDD
Operation voltage
2.5
-
5.5
V
VDD = 2.5 V ~ 5.5 V up to 84 MHz
VSS / AVSS
Power Ground
-0.3
1.62
1.22
-
-
V
1.8
1.98
1.28
VLDO
LDO Output Voltage
V
V
VDD ≥ 2.5 V
1.25
VDD = 2.5 V ~ 5.5 V, TA = 25
VBG
Band-gap Voltage
Allowed Voltage
VDD = 2.5 V ~ 5.5 V,
1.18
-0.3
1.25
0
1.32
0.3
V
V
TA = -40 ~105
VDD-AVDD Difference for VDD
and AVDD
-
VDD
HXT
HIRC
PLL
5.5V
12 MHz
Disable
Enabled
Enabled
IDD1
-
-
-
116
-
-
-
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5V
12 MHz
Disabled
Enabled
Disabled
Operating Current
Normal Run Mode
HCLK = 84 MHz
while(1){}
IDD2
52
All digital
modules
Executed from Flash
VDD
HXT
HIRC
PLL
3.3V
12 MHz
Disable
Enabled
Enabled
IDD3
112
All digital
modules
June 16, 2016
Page 194 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
3.3 V
12 MHz
Disabled
Enabled
Disabled
IDD4
IDD5
IDD6
-
-
-
50
32
13
-
-
-
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5V
Disabled
Enabled
Disabled
Enabled
All digital
modules
.
VDD
HXT
HIRC
PLL
5.5V
Disabled
Enabled
Disabled
Disabled
All digital
modules
Operating Current
Normal Run Mode
HCLK =22.1184
MHz
while(1){}
Executed from Flash
VDD
HXT
HIRC
PLL
3.3V
Disabled
Enabled
Disabled
Enabled
IDD7
-
32
-
mA
All digital
modules
VDD
HXT
HIRC
PLL
3.3V
Disabled
Enabled
Disabled
Disabled
IDD8
-
13
-
mA
All digital
modules
June 16, 2016
Page 195 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
5.5 V
12 MHz
Disabled
Disabled
Enabled
IDD9
IDD10
IDD11
IDD12
-
-
-
-
21
10
19
8.5
-
-
-
-
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5 V
12 MHz
Disabled
Disabled
Disabled
mA
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
All digital
modules
VDD
HXT
HIRC
PLL
3.3 V
Executed from Flash
12 MHz
Disabled
Disabled
Enabled
mA
All digital
modules
VDD
HXT
HIRC
PLL
3.3 V
12 MHz
Disabled
Disabled
Disabled
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5 V
4 MHz
Disabled
Disabled
Enabled
IDD13
-
9
-
mA
All digital
modules
Operating Current
Normal Run Mode
HCLK =4 MHz
while(1){}
Executed from Flash
VDD
HXT
HIRC
PLL
5.5 V
4 MHz
Disabled
Disabled
Disabled
IDD14
-
5
-
mA
All digital
modules
June 16, 2016
Page 196 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
3.3 V
4 MHz
Disabled
Disabled
Enabled
IDD15
-
7.5
-
mA
All digital
modules
VDD
HXT
HIRC
PLL
3.3 V
4 MHz
Disabled
Disabled
Disabled
IDD16
-
3.5
-
mA
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
5.5 V
Disabled
Disabled
Enabled
Disabled
Enabled
IDD17
-
364
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
Executed from Flash
VDD
HXT
HIRC
LIRC
PLL
5.5 V
Disabled
Disabled
Enabled
Disabled
Disabled
IDD18
-
354
-
μA
All digital
modules
June 16, 2016
Page 197 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
LIRC
PLL
3.3 V
Disabled
Disabled
Enabled
Disabled
Enabled
IDD19
-
206
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
HIRC
LIRC
PLL
3.3 V
Disabled
Disabled
Enabled
Disabled
Disabled
IDD20
-
196
-
μA
All digital
modules
VDD
HXT
HIRC
PLL
5.5V
12 MHz
Disable
Enabled
Enabled
IIDLE1
-
-
-
89
22
87
-
-
-
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5V
12 MHz
Disabled
Enabled
Disabled
Operating Current
Idle Mode
HCLK = 84 MHz
IIDLE2
All digital
modules
VDD
HXT
HIRC
PLL
3.3V
12 MHz
Disable
Enabled
Enabled
IIDLE3
All digital
modules
June 16, 2016
Page 198 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
3.3V
12 MHz
Disabled
Enabled
Disabled
IIDLE4
IIDLE5
IIDLE6
-
-
-
21
-
-
-
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5V
Disabled
Enabled
Disabled
Enabled
24
All digital
modules
.
VDD
HXT
HIRC
PLL
5.5V
Disabled
Enabled
Disabled
Disabled
5.5
All digital
modules
Operating Current
Idle Mode
HCLK =22.1184
MHz
VDD
HXT
HIRC
PLL
3.3V
Disabled
Enabled
Disabled
Enabled
IIDLE7
-
23.7
-
mA
All digital
modules
VDD
HXT
HIRC
PLL
3.3V
Disabled
Enabled
Disabled
Disabled
IIDLE8
-
5.3
-
mA
All digital
modules
June 16, 2016
Page 199 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
5.5 V
12 MHz
Disabled
Disabled
Enabled
IIDLE9
IIDLE10
IIDLE11
IIDLE12
-
-
-
-
16.7
5.4
15
-
-
-
-
mA
mA
mA
mA
All digital
modules
VDD
HXT
HIRC
PLL
5.5 V
12 MHz
Disabled
Disabled
Disabled
All digital
modules
Operating Current
Idle Mode
HCLK =12 MHz
VDD
HXT
HIRC
PLL
3.3 V
12 MHz
Disabled
Disabled
Enabled
All digital
modules
VDD
HXT
HIRC
PLL
3.3 V
12 MHz
Disabled
Disabled
Disabled
3.8
All digital
modules
VDD
HXT
HIRC
PLL
5.5 V
4 MHz
Disabled
Disabled
Enabled
IIDLE13
-
7.5
-
mA
All digital
modules
Operating Current
Idle Mode
HCLK =4 MHz
VDD
HXT
HIRC
PLL
5.5 V
4 MHz
Disabled
Disabled
Disabled
IIDLE14
-
3.5
-
mA
All digital
modules
June 16, 2016
Page 200 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
PLL
3.3 V
4 MHz
Disabled
Disabled
Enabled
IIDLE15
-
6
-
mA
All digital
modules
VDD
HXT
HIRC
PLL
3.3 V
4 MHz
Disabled
Disabled
Disabled
IIDLE16
-
2
-
mA
All digital
modules
VDD
HXT
HIRC
LIRC
PLL
5.5 V
Disabled
Disabled
Enabled
Disabled
Enabled
IIDLE17
-
360
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
Operating Current
Idle Mode
at 10 kHz
VDD
HXT
HIRC
LIRC
PLL
5.5 V
Disabled
Disabled
Enabled
Disabled
Disabled
IIDLE18
-
350
-
μA
All digital
modules
June 16, 2016
Page 201 of 228
Rev 1.09
NUC442
VDD
HXT
HIRC
LIRC
PLL
3.3 V
Disabled
Disabled
Enabled
Disabled
Enabled
IIDLE19
-
202
-
μA
All digital
modules
Only enable modules which support 10
kHz LIRC clock source
VDD
HXT
HIRC
LIRC
PLL
3.3 V
Disabled
Disabled
Enabled
Disabled
Disabled
IIDLE20
-
192
-
μA
All digital
modules
VDD = 5.5 V, All oscillators and analog
blocks turned off.
IPWD1
IPWD2
-
-
60
55
100
95
Standby Current
Power-down Mode
(Deep Sleep Mode)
A
A
VDD = 3.3 V, All oscillators and analog
blocks turned off.
Logic 0 Input Current
(Quasi-bidirectional
Mode)
IIL
-
-65
-
VDD = 5.5 V, VIN = 0V
A
A
Logic 1 to 0
Transition Current
(Quasi-bidirectional
Mode) [*3]
ITL
-
-690
-
-750
+2
VDD = 5.5 V, VIN = 2.0V
VDD = 5.5 V, 0 < VIN < VDD
Open-drain or input only mode
Input Leakage
Current
ILK
-2
A
-0.3
-0.3
2.0
1.5
0
-
-
-
-
-
-
-
-
0.8
0.6
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
VDD = 4.5 V
VDD = 2.5 V
VDD = 5.5 V
VDD = 3.0 V
Input Low Voltage
(TTL Input)
VIL1
VIH1
VIL3
VIH3
V
VDD + 0.3
VDD + 0.3
0.8
Input High Voltage /4
(TTL Input)
V
V
Input Low Voltage
XTAL1[*2]
0
0.4
3.5
2.4
VDD + 0.3
VDD + 0.3
V
V
Input High Voltage
XTAL1[*2]
Negative-going
Threshold
(Schmitt Input),
nRST
VILS
-0.3
-
-
0.2 VDD
-
Positive-going
Threshold
(Schmitt Input),
nRST
VIHS
0.7 VDD
40
VDD + 0.3
150
V
-
Internal nRST Pin
Pull-up Resistor
RRST
kΩ
-
June 16, 2016
Page 202 of 228
Rev 1.09
NUC442
Negative-going
Threshold
VILS
-0.3
-
0.3 VDD
V
-
(Schmitt input)
Positive-going
Threshold
(Schmitt input)
VIHS
ISR11
0.7 VDD
-300
-
VDD + 0.3
-
V
-
-370
VDD = 4.5 V, VS = 2.4 V
A
Source Current
(Quasi-bidirectional
Mode)
ISR12
ISR13
ISR21
-50
-40
-20
-70
-60
-25
-
-
-
VDD = 2.7 V, VS = 2.2 V
VDD = 2.5 V, VS = 2.0 V
A
A
mA VDD = 4.5 V, VS = 2.4 V
mA VDD = 2.7 V, VS = 2.2 V
mA VDD = 2.5 V, VS = 2.0 V
Source Current
(Push-pull Mode)
ISR22
-3
-5
-
-
ISR23
ISK11
ISK12
-2.5
-4.5
10
6
15
9
-
-
-
mA VDD = 4.5 V, VS = 0.45 V
mA VDD = 2.7 V, VS = 0.45 V
mA VDD = 2.5 V, VS = 0.45 V
Sink Current (Quasi-
bidirectional, Open-
Drain and Push-pull
Mode)
ISK13
5
8
Notes:
1. nRST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins can source a transition current when they are being externally driven from 1 to 0. In the condition of
VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V.
June 16, 2016
Page 203 of 228
Rev 1.09
NUC442
7.3 AC Electrical Characteristics
7.3.1 External Input Clock
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
tCHCX
tCLCX
tCLCH
tCHCL
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
10
10
2
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
-
15
15
2
7.3.2 External 4~24 MHz High Speed Crystal (HXT)
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Condition
-
-
-
-
TA
℃
2.6
1.3
-
mA
mA
MHz
12 MHz, VDD = 5.5V
IHXT
Operating Current
Clock Frequency
-
-
12 MHz, VDD = 3.3V
-
fHXT
4
24
June 16, 2016
Page 204 of 228
Rev 1.09
NUC442
7.3.3 Typical Crystal Application Circuits
Crystal
C1
C2
4 MHz ~ 24 MHz
10~20 pF
10~20 pF
XTAL1
XTAL2
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 7.3-1 NUC442 Typical Crystal Application Circuit
7.3.4 External 32 kHz Low Speed Crystal (LXT)
Symbol
VLXT
TA
Parameter
Min.
2.5
-40
-
Typ.
Max
5.5
85
-
Unit
V
Test Condition
Operation Voltage
Temperature
-
-
-
℃
-
ILXT
Operating Current
Clock Frequency
1.6
32768
uA
Hz
VBAT = 3.3V
-
FLXT
-
-
7.3.5 22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VHRC
Supply Voltage
1.62
-
1.8
1.98
-
V
-
-
Center Frequency
22.1184
MHz
TA = 25℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40 ~ 105
-2
-
-
+2
-
%
VDD = 2.5 V ~ 5.5 V
TA = 25℃,VDD = 3.3 V
μA
IHRC
Operating Current
655
June 16, 2016
Page 205 of 228
Rev 1.09
NUC442
7.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VLRC
Supply Voltage
2.5
-
-
5.5
-
V
-
-
Center Frequency
10
kHz
VDD = 2.5 V ~ 5.5 V
-25
-40
-
-
+25
+40
%
%
TA = 25
fLRC
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40 ~ +105
7.3.7 Input/Output AC Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VDD = 5 V, TA = 25
CL=30p
GPIOx_HS = 0[1]
-
7[2]
-
ns
Output High to Low Level
Fall Time
TfIO
VDD = 5 V, TA = 25
CL=30p
5[2]
7[2]
6[2]
-
-
-
ns
ns
ns
-
-
-
GPIOx_HS = 1[1]
VDD = 5 V, TA = 25
CL=30p
GPIOx_HS = 0[1]
Output Low to High Level
Rise Time
TrIO
VDD = 5 V, TA = 25
CL=30p
GPIOx_HS = 1[1]
Notes:
1. The I/O speed is configured using the GPIOx_HS bits. Refer to the TRM for a description of GPIO Port
configuration register.
2. Guaranteed by design, and not tested in production.
June 16, 2016
Page 206 of 228
Rev 1.09
NUC442
7.4 Analog Characteristics
7.4.1 12-bit SAR ADC
Symbol Parameter
Min
Typ
Max
12
Unit
Bit
Test Condition
-
DNL
INL
EO
EG
EA
-
Resolution
-
-
-
-
-
-
-
-
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
±1
-1~+4
±4
LSB
LSB
LSB
LSB
LSB
-
-
±2
-
2
4
-
Gain Error (Transfer Gain)
Absolute Error
-2
-4
-
3
4
-
Monotonic
Guaranteed
-
-
-
-
-
-
-
16
8
AVDD = 4.5~5.5 V
FADC
ADC Clock Frequency
MHz
AVDD = 2.5~5.5 V
-
800
400
kSPS
kSPS
1/FADC
1/FADC
V
AVDD = 4.5~5.5 V
FS
Sample Rate (FADC/TCONV)
-
AVDD = 2.5~5.5 V
TACQ
TCONV
AVDD
IDDA
VIN
7
20
-
-
Acquisition Time (Sample Stage)
Total Conversion Time
Supply Voltage
-
2.5
5.5
-
-
0
-
2.9
-
-
mA
AVDD = 5 V
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
Input Load
AVDD
V
-
-
-
CIN
7
6
-
-
pF
RIN
-
kΩ
June 16, 2016
Page 207 of 228
Rev 1.09
NUC442
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated
transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the
offset and gain error from the actual transfer curve.
June 16, 2016
Page 208 of 228
Rev 1.09
NUC442
7.4.2 LDO and Power Management
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Capacitor
Min
2.5
1.62
-40
-
Typ
-
Max
5.5
1.98
105
-
Unit
V
Test Condition
-
VLDO
TA
1.8
25
1
V
-
℃
-
RESR = 1Ω
CLDO
μF
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the
device.
2. For ensuring power stability, a 1μF or higher capacitor must be connected between LDO_CAP pin and
the closest VSS pin of the device.
7.4.3 Low Voltage Reset
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-40
-
25
105
5
-
ILVR
Quiescent Current
1
AVDD = 5.5 V
TA = 25℃
TA = -40℃
TA = 105℃
1.9
1.7
2.00
2.00
1.90
2.20
2.10
2.10
2.45
VLVR
Threshold Voltage
V
V
June 16, 2016
Page 209 of 228
Rev 1.09
NUC442
7.4.4 Brown-out Detector
Symbol
AVDD
TA
Parameter
Min
0
Typ
Max
5.5
105
-
Unit
V
Test Condition
-
Supply Voltage
Temperature
-
℃
μA
V
-40
-
25
-
IBOD
Quiescent Current
120
4.4
3.7
2.7
2.2
4.5
3.8
2.7
2.2
AVDD = 5.5 V
4.2
3.5
2.5
2.0
4.3
3.6
2.5
2.0
4.6
3.9
2.9
2.4
4.8
3.9
2.9
2.4
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
V
Brown-out Voltage
(Falling edge)
VBOD
V
V
V
V
Brown-out Voltage
(Rising edge)
VBOD
V
V
7.4.5 Power-on Reset
Symbol
TA
Parameter
Min
-40
-
Typ
25
Max
105
-
Unit
℃
Test Condition
Temperature
Reset Voltage
-
VPOR
2.0
V
V+
VDD Start Voltage to Ensure
Power-on Reset
VPOR
-
-
-
100
-
mV
-
-
VDD Raising Rate to Ensure
Power-on Reset
RRVDD
0.025
V/ms
Minimum Time for VDD
Stays at VPOR to Ensure
Power-on Reset
tPOR
0.5
-
-
ms
-
June 16, 2016
Page 210 of 228
Rev 1.09
NUC442
VDD
tPOR
RRVDD
VPOR
Time
Figure 7.4-1 Power-up Ramp Condition
June 16, 2016
Page 211 of 228
Rev 1.09
NUC442
7.4.6 Temperature Sensor
Symbol
Parameter
Min
1.62
-40
Typ
1.8
-
Max
1.98
105
-
Unit
V
Test Condition
VTEMP
Supply Voltage
Temperature
Current Consumption
Gain
TA
℃
ITEMP
-
3
μA
-
-
mV/℃
-1.65
760
-1.66
762
-1.68
766
Offset
mV
TA = 0℃
Note:
The temperature sensor formula for the output voltage (Vtemp) is as below equation.
Vtemp (mV) = Gain (mV/ ) x Temperature ( ) + Offset (mV)
7.4.7 Comparator
Symbol
VCMP
TA
Parameter
Supply Voltage
Min
2.5
-40
-
Typ
Max
Unit
V
Test Condition
5.5
℃
Temperature
25
35
10
-
105
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
70
20
μA
mV
V
AVDD = 5 V
-
-
-
-
0.1
0.35
40
AVDD - 0.1
AVDD - 0.3
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
200
-
ns
VHYS
TSTB
Hysteresis
Stable time
-
-
±40
-
±60
1
mV
μs
7.4.8 OP Amplifier
PARAMETER
CONDITION
MIN.
3.0
-
TYP.
MAX.
5.5
UNIT
AVDD
-
-
3.3
V
Input offset voltage
Input offset average drift
Output swing
2
-
5
mV
uV/℃
-
1
-
-
0.1
0.1
-
VDD-0.1
VDD-1.2
V
V
Input common mode range
-
June 16, 2016
Page 212 of 228
Rev 1.09
NUC442
PARAMETER
DC gain
CONDITION
MIN.
TYP.
80
MAX.
UNIT
-
-
-
-
-
-
-
5
-
dB
MHz
°
Unity gain freq.
Phase margin
PSRR+
AVDD=5V
-
50°
90
AVDD=5V
AVDD=5V
-
dB
dB
CMRR
90
-
AVDD=5V, RLOAD=33K,
CLOAD=50p
Slew rate
6.0
-
-
V/us
Wake up time
-
-
-
1
-
us
Quiescent current
600
uA
7.4.9 Internal Voltage Reference
SYMBOL
VVREF
PARAMETER
CONDITION
-
MIN.
TYP.
MAX. UNIT
AVDD
2.4
5.5
V
V
V
V
V
Vref1
Vref2
Vref3
Vref4
VREF(2.56V)
VREF(2.048V)
VREF(3.072V)
VREF(4.096V)
AVDD >= 2.9V
AVDD >= 2.4V
AVDD >= 3.4V
AVDD >= 4.5V
2.483
2.56
2.637
2.109
3.164
4.219
1.986 2.048
2.98 3.072
3.973 4.096
June 16, 2016
Page 213 of 228
Rev 1.09
NUC442
7.4.10 USB PHY Specification
7.4.10.1 Low-/full-Speed DC Electrical Specifications
SYMBOL
VIH
PARAMETER
Input High (driven)
CONDITIONS
MIN.
TYP.
MAX. UNIT
2.0
V
V
V
VIL
VDI
Input Low
0.8
Differential Input Sensitivity
|PADP-PADM|
0.2
0.8
0.8
Differential
VCM
VSE
Includes VDI range
2.5
2.0
V
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
V
mV
V
200
VOL
Output Low (driven)
0
0.3
3.6
VOH
VCRS
RPU
ZDRV
CIN
Output High (driven)
2.8
V
Output Signal Cross Voltage
Pull-up Resistor
1.3
2.0
V
1.425
1.575
kΩ
Ω
Driver Output Resistance
Transceiver Capacitance
Steady state drive*
Pin to GND
10
20
pF
*Driver output resistance doesn’t include series resistor resistance.
7.4.10.2 High-Speed DC Electrical Specifications
SYMBOL
VHSDI
PARAMETER
High-speed differential Input level
High-speed SQ detection threshold
High-speed Common-mode Range
High-speed Output Low
High-speed Output High
Chirp J level
CONDITIONS
|PADP-PADM|
|PADP-PADM|
MIN.
150
100
-50
TYP.
MAX. UNIT
mV
VHSSQ
150
500
10
mV
mV
mV
mV
mV
mV
VHSCM
VHSOL
-10
VHSOH
360
700
-900
440
1100
-500
VCHIRPJ
VCHIRPK
Chirp K level
High-speed Driver Output
Resistance
45Ω±10%
ZHSDRV
40.5
49.5
Ω
June 16, 2016
Page 214 of 228
Rev 1.09
NUC442
7.4.10.3 USB Full-Speed Driver Electrical Characteristics
SYMBOL
TFR
PARAMETER
CONDITIONS
CL=50p
MIN.
4
TYP.
MAX. UNIT
Rise Time
Fall Time
20
20
ns
ns
%
TFF
CL=50p
4
TFRFF
Rise and Fall Time Matching
TFRFF=TFR/TFF
90
111.11
7.4.10.4 USB High-Speed Driver Electrical Characteristics
SYMBOL
THSR
PARAMETER
CONDITIONS
MIN.
500
TYP.
MAX. UNIT
ZHSDRV=45Ω
Rise Time
Fall Time
900
900
ps
ps
ZHSDRV=45Ω
THSF
500
7.4.10.5 USB Power Dissipation
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VBUS Current
(Steady State)
IVBUS
Standby
TBD
μA
7.4.10.6 USB LDO Specification
SYMBOL
VBUS
PARAMETER
CONDITIONS
MIN.
4.0
TYP.
5.0
MAX. UNIT
VBUS Pin Input Voltage
LDO Output Voltage
5.5
3.63
-
V
V
VDD33
Cbp
2.97
3.3
External Bypass Capacitor
1.0
uF
June 16, 2016
Page 215 of 228
Rev 1.09
NUC442
7.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Data Retention
Page Erase Time
Program Time
Endurance
Min
1.62
100
20
Typ
Max
Unit
V
Test Condition
[1]
VFLA
1.8
1.98
TA = 25
TRET
TERASE
TPROG
-
-
-
-
year
ms
-
-
40
us
20000
times
Notes:
1. VFLA is source from chip LDO output voltage.
2. Guaranteed by design, and not tested in production.
June 16, 2016
Page 216 of 228
Rev 1.09
NUC442
7.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
tLOW
SCL low period
4.7
4
1.2
0.6
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
1.2
0.6
4
0.6
4.7[3]
250
0[4]
1.2[3]
100
tSU;DAT
tHD;DAT
tr
Data setup time
Data hold time
3.45[5]
1000
300
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
Cb
Capacitive load for each bus line
400
Notes:
1.
2.
Guaranteed by design, not tested in production.
HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3.
4.
I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 7.6-1 I2C Timing Diagram
June 16, 2016
Page 217 of 228
Rev 1.09
NUC442
7.7 SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI Master Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
tDS
tDH
tV
Data hold time
Data output valid time
1
2
SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
Data setup time
0
ns
ns
ns
tDS
tDH
tV
Data hold time
4.5
Data output valid time
2
4
SPI Slave Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
Data setup time
0
3.5
-
-
-
-
-
ns
ns
ns
tDS
tDH
tV
Data hold time
Data output valid time
16
22
SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
Data setup time
0
ns
ns
ns
tDS
tDH
tV
Data hold time
4.5
Data output valid time
18
24
CLKP=0
SPICLK
CLKP=1
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Data Valid
Figure 7.7-1 SPI Master Mode Timing Diagram
June 16, 2016
Page 218 of 228
Rev 1.09
NUC442
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 7.7-2 SPI Slave Mode Timing Diagram
June 16, 2016
Page 219 of 228
Rev 1.09
NUC442
7.8 I2S Dynamic Characteristics
Symbol
Parameter
Conditions
Min
Max Unit
I2S clock high
time
tw(CKH)
42
37
7
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
I2S clock low
time
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
WS valid time
WS hold time
Master mode
Master mode
-
ns
1
-
-
-
WS setup time Slave mode
34
0
WS hold time
Slave mode
Slave mode
I2S slave input
clock duty
cycle
DuCy(SCK)
25
75
%
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
Master receiver
0
0
0
0
-
-
-
Data input
setup time
Slave receiver
Master receiver
-
Data input hold
time
Slave receiver
-
ns
Data output
valid time
Data output
hold time
Data output
valid time
Data output
hold time
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
32
-
16
-
5
-
0
June 16, 2016
Page 220 of 228
Rev 1.09
NUC442
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.8-1 I2S Master Mode Timing Diagram
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.8-2 I2S Slave Mode Timing Diagram
June 16, 2016
Page 221 of 228
Rev 1.09
NUC442
8
PACKAGE DIMENSIONS
8.1 LQFP 64L (10x10x1.4 mm footprint 2.0 mm)
June 16, 2016
Page 222 of 228
Rev 1.09
NUC442
8.2 LQFP 100L (14x14x1.4 mm footprint 2.0 mm)
June 16, 2016
Page 223 of 228
Rev 1.09
NUC442
8.3 LQFP 128L (14x14x1.4 mm footprint 2.0 mm)
June 16, 2016
Page 224 of 228
Rev 1.09
NUC442
8.4 LQFP 144L (20x20x1.4 mm footprint 2.0 mm)
June 16, 2016
Page 225 of 228
Rev 1.09
NUC442
June 16, 2016
Page 226 of 228
Rev 1.09
NUC442
9
REVISION HISTORY
Date
Revision
1.01
Description
2013.11.01
2013.11.15
1.
1.
Preliminary version.
1.02
1.03
Editorial changes.
1.
2.
Updated the Clock Generator Global View Diagram.
Updated the LQFP 64L package dimension.
2014.01.29
2014.04.16
2014.05.23
1.04
1.05
1.
1.
1.
Modified the pin description table.
Added the I2C, SPI and I2S Dynamic Characteristics.
Modified the Section 4.2 Pin Configuration and Section 4.3 Pin
Description.
2014.07.21
2015.04.15
1.06
1.07
2.
3.
1.
2.
Modified the SPI Features.
Added SRAM origination and description.
Added the clock switch note in all clock source blocks.
Updated the Section 4.2 Pin Configuration and Section 4.3 Pin
Description for the NUC442-LQFP64.
3.
4.
1.
Added the note description for VREF and LDO_CAP pins.
Updated the Clock Generator Global View Diagram.
Removed the Serial Wire Viewer (SWV) in the Section 2.1
Features.
2016.03.10
2016.06.16
1.08
1.09
2.
Corrected some EBI_ADxx description typo in the Section 4.3
Pin Description.
3.
1.
Corrected the Figure 6.3-1 and Figure 6.3-2.
Removed the PDMA time-out function description in the
Section 2.1 and Section 6.7.
June 16, 2016
Page 227 of 228
Rev 1.09
NUC442
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
June 16, 2016
Page 228 of 228
Rev 1.09
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明