NUC505-DF1G [NUVOTON]
ARM® Cortex®-M4 32-bit Microcontroller;
| 型号： | NUC505-DF1G |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M4 32-bit Microcontroller 微控制器 |
| 文件： | 总130页 (文件大小：3244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC505
ARM® Cortex® -M4
32-bit Microcontroller
NuMicro® Family
NUC505 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
July. 26, 2018
Page 1 of 130
Rev.1.08
NUC505
TABLE OF CONTENTS
1
2
GENERAL DESCRIPTION .............................................................. 8
FEATURES ................................................................................ 9
2.1 NUC505 Features.......................................................................... 9
ABBREVIATIONS....................................................................... 14
3.1 Abbreviations...............................................................................14
PARTS INFORMATION LIST AND PIN CONFIGURATION..................... 15
4.1 Selection Guide............................................................................15
3
4
4.1.1
4.1.2
NuMicro® NUC505 Base Series Selection Guide ......................................15
NuMicro® NUC505 Base Series Naming Rule..........................................16
4.2 Pin Configuration ..........................................................................17
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
NuMicro® NUC505DLA LQFP 48-pin ....................................................17
NuMicro® NUC505DL13Y LQFP 48-pin .................................................18
NuMicro® NUC505YLA QFN 48-pin......................................................19
NuMicro® NUC505YLA2Y QFN 48-pin ..................................................20
NuMicro® NUC505DSA LQFP 64-pin ....................................................21
NuMicro® NUC505DS13Y LQFP 64-pn..................................................22
NuMicro® NUC505YO13Y QFN 88-pin ..................................................23
4.3 Pin Description.............................................................................24
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
NuMicro® NUC505DLA LQFP 48-pin Description......................................24
NuMicro® NUC505DL13Y LQFP 48-pin Description...................................28
NuMicro® NUC505YLA QFN 48-pin Description .......................................33
NuMicro® NUC505YLA2Y QFN 48-pin Description....................................37
NuMicro® NUC505DSA LQFP 64-pin Description .....................................42
NuMicro® NUC505DS13Y LQFP 64-pin Description ..................................48
NuMicro® NUC505YO13Y QFN 88-pin Description ...................................54
Summary GPIO Multi-function Pin Description .........................................62
GPIO Multi-function Pin Summary........................................................64
5
6
BLOCK DIAGRAM ...................................................................... 68
5.1 NuMicro® NUC505 Series Block Diagram.............................................68
FUNCTIONAL DESCRIPTION........................................................ 69
6.1 ARM® Cortex® -M4 Core ..................................................................69
6.2 System Manager ..........................................................................72
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6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview......................................................................................72
System Reset ................................................................................72
System Power-on Setting ..................................................................73
System Power Distribution.................................................................73
System Memory Mapping..................................................................74
SRAM Memory Organization ..............................................................76
AHB Bus Arbitration.........................................................................78
System Timer (Systick).....................................................................80
Nested Vectored Interrupt Control (NVIC)...............................................81
6.3 Clock Controller............................................................................84
6.3.1
6.3.2
6.3.3
6.3.4
Overview......................................................................................84
Clock Diagram ...............................................................................85
Clock Generator .............................................................................86
Power-down Mode Clock ..................................................................87
6.4 General Purpose I/O (GPIO) ............................................................88
6.4.1
6.4.2
Overview......................................................................................88
Features ......................................................................................88
6.5 Timer Controller (TIMER) ................................................................90
6.5.1
6.5.2
Overview......................................................................................90
Features ......................................................................................90
6.6 PWM Generator and Capture Timer (PWM)..........................................91
6.6.1
6.6.2
Overview......................................................................................91
Features ......................................................................................91
6.7 Watchdog Timer (WDT) ..................................................................92
6.7.1
6.7.2
Overview......................................................................................92
Features ......................................................................................92
6.8 Window Watchdog Timer (WWDT).....................................................92
6.8.1
6.8.2
Overview......................................................................................92
Features ......................................................................................92
6.9 Real Time Clock (RTC)...................................................................93
6.9.1
6.9.2
Overview......................................................................................93
Features ......................................................................................93
6.10 UART Interface Controller (UART) .....................................................94
6.10.1 Overview......................................................................................94
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6.10.2 Features ......................................................................................94
6.11 I2C Serial Interface Controller (Master/Slave) ........................................95
6.11.1 Overview......................................................................................95
6.11.2 Features ......................................................................................96
6.12 Serial Peripheral Interface (SPI) ........................................................97
6.12.1 Overview......................................................................................97
6.12.2 Features ......................................................................................97
6.13 SPI Memory Interface Controller (SPIM) ..............................................98
6.13.1 Overview......................................................................................98
6.13.2 Features ......................................................................................98
6.14 I2S Controller with Internal Audio CODEC (I2S) ......................................99
6.14.1 Overview......................................................................................99
6.14.2 Features ......................................................................................99
6.15 USB 2.0 Device Controller (USBD)...................................................100
6.15.1 Overview.................................................................................... 100
6.15.2 Features .................................................................................... 100
6.16 USB 1.1 Host Controller (USBH) .....................................................101
6.16.1 Overview.................................................................................... 101
6.16.2 Features .................................................................................... 101
6.17 Secure-Digital Host Controller (SDHC) ..............................................102
6.17.1 Overview.................................................................................... 102
6.17.2 Features .................................................................................... 102
6.18 12-bit Analog-to-Digital Converter (ADC)............................................103
6.18.1 Overview.................................................................................... 103
6.18.2 Features .................................................................................... 103
7
ELECTRICAL CHARACTERISTICS ................................................104
7.1 Absolute Maximum Ratings............................................................104
7.2 DC Characteristics ......................................................................105
7.3 AC Electrical Characteristics ..........................................................108
7.3.1
7.3.2
7.3.3
7.3.4
External 12 MHz Crystal ................................................................. 108
External 12 MHz High Speed Oscillator ............................................... 108
Typical Crystal Application Circuits..................................................... 108
Internal 32 kHz Low Speed Oscillator.................................................. 109
7.4 Analog Characteristics..................................................................110
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7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
Specifications of 12-bit SARADC ....................................................... 110
Specifications of 24-bit Delta-Sigma CODEC......................................... 112
Specification of LDO ...................................................................... 113
Specification of Low Voltage Reset .................................................... 114
Specifications of Power-on Reset ...................................................... 114
USB PHY Specifications ................................................................. 116
I2C Dynamic Characteristics............................................................. 118
SPI Dynamic Characteristics ............................................................ 119
I2S Dynamic Characteristics ............................................................. 121
8
9
APPLICATION CIRCUIT..............................................................123
PACKAGE DIMENSIONS ............................................................124
9.1 LQFP 48L (7x7x1.4mm footprint 2.0mm)............................................124
9.2 QFN 48 (7x7x0.8mm)...................................................................125
9.3 LQFP 64L (7x7x1.4mm footprint 2.0mm)............................................126
9.4 QFN 88 (10x10x0.9mm)................................................................127
10 REVISION HISTORY..................................................................129
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List of Figures
Figure 4.1-1 NuMicro® NUC505 Base Series Selection Code....................................................... 16
Figure 4.2-1 NuMicro® NUC505DLA LQFP 48-pin Diagram.......................................................... 17
Figure 4.2-2 NuMicro® NUC505DL13Y LQFP 48-pin Diagram...................................................... 18
Figure 4.2-3 NuMicro® NUC505YLA QFN 48-pin Diagram............................................................ 19
Figure 4.2-4 NuMicro® NUC505YLA2Y QFN 48-pin Diagram ....................................................... 20
Figure 4.2-5 NuMicro® NUC505DSA LQFP 64-pin Diagram ......................................................... 21
Figure 4.2-6 NuMicro® NUC505DS13Y LQFP 64-pin Diagram ..................................................... 22
Figure 4.2-7 NuMicro® NUC505YO13Y QFN 88-pin Diagram....................................................... 23
Figure 5.1-1 NuMicro® NUC505 Block Diagram ............................................................................ 68
Figure 6.1-1 Cortex® -M4 Block Diagram........................................................................................ 69
Figure 6.2-1 NuMicro® NUC505 Power Distribution Diagram........................................................ 74
Figure 6.2-2 SRAM Block Diagram................................................................................................ 76
Figure 6.2-3 SRAM Memory Organization..................................................................................... 77
Figure 6.2-4 Vector Map Module Block.......................................................................................... 78
Figure 6.3-1 Clock Generator Global View Diagram...................................................................... 85
Figure 6.3-2 Clock Generator Block Diagram ................................................................................ 86
Figure 6.3-3 Crystal Oscillator Circuit ............................................................................................ 87
Figure 6.4-1 I/O Pin Block Diagram ............................................................................................... 88
Figure 6.11-1 I2C Bus Timing......................................................................................................... 95
Figure 7.3-1 Typical Crystal Application Circuit ........................................................................... 109
Figure 7.4-1 Power-up Ramp Condition ...................................................................................... 115
Figure 7.4-2 I2C Timing Diagram ................................................................................................. 118
Figure 7.4-3 SPI Master Mode Timing Diagram .......................................................................... 119
Figure 7.4-4 SPI Slave Mode Timing Diagram ............................................................................ 120
Figure 7.4-5 I2S Master Mode Timing Diagram........................................................................... 122
Figure 7.4-6 I2S Slave Mode Timing Diagram.............................................................................. 122
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List of Tables
Table 3.1-1 List of Abbreviations.................................................................................................... 14
Table 4.1-1 NuMicro® NUC505 Base Series Selection Guide....................................................... 15
Table 4.3-1 NUC505 GPIO Multi-function Table............................................................................ 67
Table 6.2-1 System Power-on Setting Guide................................................................................. 73
Table 6.2-2 Address Space Assignments for On-Chip Controllers................................................ 75
Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode........................................................... 79
Table 6.2-4 Exception Model....................................................................................................... 82
Table 6.2-5 Interrupt Number Table............................................................................................... 83
Table 6.3-1 Recommended Load Capacitance Values and Resistance Values. .......................... 87
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1
GENERAL DESCRIPTION
The NuMicro® NUC505 series 32-bit microcontrollers are embedded with ARM® Cortex® -M4F
core for consumer and industrial applications which need high computing power and rich
communication interfaces.
The ARM® Cortex® -M4F core within NuMicro® NUC505 series can run up to 100 MHz and support
DSP extensions and Floating Point Unit (FPU) function. The NuMicro® NUC505 series supports
128 Kbytes embedded SRAM with zero-wait state and 512 KB/ 2 Mbytes embedded SPI Flash
memory, and is equipped with plenty of high performance peripheral devices, such as 24-bit
Audio CODEC, USB2.0 High-speed Device, USB2.0 Full-speed Host, and other peripheral.
The NuMicro® NUC505 series is suitable for a wide range of applications such as:
Audio and Wireless Audio Applications
Thermal printerDid not find any incorrect format
GPS Tracker / VTDR (Vehicle Travelling Data Recorder)
Others high performance or data intensive computing applications
Key Features:
Core
I2S
─ ARM® Cortex®-M4F core running up to
100 MHz (with DSP and FPU)
─ Supports Master or Slave mode
operation
─ Supports PCM mode A, PCM mode B,
I2S and MSB justified data format
─ Supports DMA mode
Memory
─ 128 KB of SRAM with zero-wait state
─ 512 KB/ 2 MB of SPI Flash
Audio CODEC
Security for code protection
─ 128-bit key for code protection against
pirating
─ Embedded Stereo 24-bit Sigma-Delta
CODEC
─ MIC/LINE-In-THDN: -80 dB, Dynamic
Range SNR: 90 dB (A-Weighted)
─ Headphone Output-THDN:-60dB,
Dynamic Range SNR: 93 dB (A-
Weighted)
─ Up to 15 times programming the key
Clock Control
─ 12 MHz crystal oscillator input
─ Up to two PLLs for system clock and
Audio
─ Sample Rate: 8 kHz to 96 kHz
Up to 12 Communication interfaces
─ USB 2.0 HS Device interface
─ Up to two USB 2.0 FS Host interfaces
─ Up to three UARTs
12-bit ADC
─ Analog input voltage range: 0~ AVDD
─ Supports single 12-bit SAR ADC
conversion
─ Up to three SPIs
─ Up to two I²C interfaces (up to 1 MHz)
─ SD Host
─ Up to 8 channels
─ Up to 1 MSPS conversion with
ADC_CH1, and up to 200 kSPS with
other channels (except ADC_CH0).
GPIO
─ Supports up to 25/35/52 GPIOs for
QFN88/LQFP64/LQFP48 respectively
Built-in LDO with operating voltage 3.3V
Low Voltage Detector (LVD)
─ With 2 levels: 2.8V / 2.6V
Timer
─ Supports four sets of 32-bit timers
─ Supports two watchdog timers
(Independent and Window)
Low Voltage Reset (LVR)
─ Threshold voltage level: 2.4 V
Packages
RTC
─ LQFP48, LQFP64, QFN88
─ Temperature range: -40℃~+85℃
─ Supports external power pin VBAT
─ 32 bytes spare registers
─ Internal 32.768 kHz RC with calibration
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2
FEATURES
2.1 NUC505 Features
Core
─
─
─
─
─
─
─
─
ARM® Cortex® -M4F core running up to 100 MHz
Supports DSP extension with hardware divider
Supports IEEE 754 compliant Floating Point Unit (FPU)
Supports Memory Protection Unit (MPU)
One 24-bit system timer
Supports Power-down mode by WFI and WFE instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
─
─
Supports programmable mask-able interrupts
Boots from SPI Flash Memory or USB Device
SRAM Memory
─
─
128 KB embedded SRAM with zero-wait state
Supports byte-, half-word- and word-access
SPI Memory Interface Controller
─
─
─
─
─
─
Supports external SPI Flash memory
Supports code protection
Supports DMA mode for code transfer from SPI Flash memory to SRAM
Supports CPU direct read from SPI Flash memory.
Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode
Supports general SPI master interface protocol
Embedded SPI Flash
─
─
─
─
─
─
─
512 KB/ 2 MB SPI Flash
Configurable program code/data allocation
Supports 2-wired ICP update through SWD/ICE interface
Supports ISP update
Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode
Supports 100 MHz clock for standard I/O transfer mode
Supports 80 MHz clock for dual and quad I/O transfer mode
Security for code protection
─
─
128-bit key for code protection against pirating
Up to 15 times programming of the key
Clock Control
─
Built-in 32.768 kHz internal low speed RC oscillator (LIRC) for RTC function,
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Watchdog timer and wake-up operation
─
─
─
Supports 32.768 kHz external low speed crystal oscillator (LXT) for RTC function
and low-power system operation
Supports 12 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Supports one PLL up to 240 MHz for high performance system operation. The
external high speed crystal oscillator (HXT) is used as the clock source for the
PLL.
I2S
─
─
─
─
─
─
Supports Master or Slave mode operation
Internal PLL for frequency adjustment
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports Mono and Stereo audio data
Supports PCM mode A, PCM mode B, I2S and MSB justified data format
Each provides two 16-word FIFO data buffers, one for transmitting and the other
for receiving
─
─
─
Generates interrupt requests when buffer levels cross a programmable boundary
Supports DMA mode
Interface with internal or external audio CODEC
Audio CODEC
─
─
─
─
Embedded Stereo 24-bit Sigma-Delta CODEC output
ADC-THDN: -80 dB, Dynamic Range SNR: 90 dB (A-Weighted)
Headphone Output-THDN:-60dB, Dynamic Range SNR: 93 dB (A-Weighted)
Sample Rate: 8 kHz to 96 kHz
USB 2.0 High-speed device
─
12 programmable endpoints for Control, Bulk IN/OUT, Interrupt and Isochronous
transfers
─
─
─
2K-byte buffer
Auto suspend function
Remote wake-up capability
USB 2.0 Full-speed host
─
─
─
─
Fully compliant with USB revision 1.1 specification
Open Host Controller Interface (OHCI) revision 1.0 compatible
Full-speed (12Mbps) and Low-speed (1.5Mbps) device supported
Control, Bulk, Interrupt and Isochronous transfers supported
SD Host Interface
─
─
Supports SD (Secure Digital) card and SD_HOST interface
Compliant with SD Memory Card Specification Version 2.0
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─
Supports 1 and 4-bit modes
─
─
Supports 50 MHz to achieve 200 Mbps at 3.3V operation
Supports DMA master
Timer
─
─
─
─
─
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides One-shot, periodic, toggle and continuous counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Watchdog Timer
─
─
─
Supports multiple clock sources from LIRC (default selection), HXT and LXT
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
─
Supports multiple clock sources from LIRC (default selection), HXT and LXT
─
─
Window set by 6-bit counter with 11-bit prescale
Interrupt or reset selectable on time-out
GPIO
─
─
─
─
Four I/O modes
CMOS/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge trigger setting
Supports 5V-tolerance function (except PA.7~PA.0 and PD.4~PD.2 only support
3.3 V)
─
Supports up to 52/35(34)/25(18) GPIOs for QFN88/LQFP64/LQFP48 respectively
UART
─
Supports up to three UARTs – UART0, UART1 and UART2
Supports 16-byte FIFOs with programmable level trigger with UART0
Supports 64-byte FIFOs with programmable level trigger with UART1 and UART2
Supports auto flow control (nCTS and nRTS) with UART1 and UART2
Supports IrDA (SIR) function
─
─
─
─
─
Supports RS-485 9-bit mode and direction control
─
UART1 and UART2 support LIN function
─
─
Programmable baud-rate generator up to 1/16 system clock
Supports nCTS and data wake-up function
SPI
─
─
Supports two sets of SPI controller – SPI0 and SPI1
Supports Master or Slave mode operation
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─
─
─
─
─
─
─
─
Supports 1-bit Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wired, no slave select signal, bi-direction interface
Supports up to 50 MHz
I2C
─
─
─
─
─
Supports up to two sets of I2C devices
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
─
─
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer
─
─
─
─
─
Programmable clocks allow versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports SMBus and PMBus
Supports speed up to 1Mbps
Supports multi-address Power-down wake-up function
PWM
─
Four 16-bit timers
─
Programmable duty control of output waveform (PWM)
Auto reload mode or one-shot pulse mode
Capture and compare function
─
─
RTC
─
─
─
Supports external power pin RTC_VDD33
Supports 32.768 kHz crystal oscillation circuit
Supports RTC counter (second, minute, hour) and calendar counter (day, month,
year)
─
─
─
─
Supports Alarm registers (second, minute, hour, day, month, year)
Supports 32 bytes spare registers
Wake up from Deep Power-down mode or from Power-down mode
Supports wake up from Power-down mode by input pin
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─
─
Supports chip Power-off by register setting
Supports Power-on time-out for low battery protection
Analog to Digital Converter
─
─
─
─
Analog input voltage range: 0~ AVDD
Supports single 12-bit SAR ADC conversion
12-bit resolution and 10-bit accuracy is guaranteed
Up to 1MSPS conversion with ADC_CH1, and up to 200 kSPS with others (except
ADC_CH0).
─
─
─
Up to 8 external single-ended analog input channels
Supports single ADC interrupt
An A/D conversion can be triggered by software control
Built-in LDO with operating voltage 3.3V
Low Voltage Detector (LVD)
─
With 2 levels: 2.8V / 2.6V
Low Voltage Reset (LVR)
─
Threshold voltage level: 2.4 V
Power Management
─
Advanced power management including Deep Power-down, Power-down, Idle and
Normal Operating modes
─
Normal Operating mode
CPU runs normally and all clocks on; the current consumption is around 46 mA
(at 96 MHz CPU clock)
─
─
Idle mode
CPU clock stop, and all other clocks on
Power-down mode
All clocks stop, except LXT and LIRC, with SRAM retention; the current
consumption is around 700 uA
─
Deep Power-down mode
All clocks stop, except LXT and LIRC, without SRAM retention; the current
consumption is around 7 uA
Operating Temperature: -40℃~+85℃
Packages
─
─
─
─
─
All Green package (RoHS)
QFN 88-pin (10mm x 10mm)
LQFP 64-pin (7mm x 7mm)
LQFP 48-pin (7mm x 7mm)
QFN 48-pin (7mm x 7mm)
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3
ABBREVIATIONS
3.1 Abbreviations
Acronym
ADC
APB
Description
Analog-to-Digital Converter
Advanced Peripheral Bus
Advanced High-Performance Bus
Direct Memory Access
AHB
DMA
FIFO
FPU
GPIO
HCLK
HXT
First In, First Out
Floating Point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
12 MHz External High Speed Crystal Oscillator
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
32.768 kHz Internal Low Speed RC Oscillator
32.768 kHz External Low Speed Crystal Oscillator
Low Voltage Detection
LIRC
LXT
LVD
MPU
NVIC
PCLK
PLL
Memory Protection Unit
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Phase-Locked Loop
PWM
SD
Pulse Width Modulation
Secure Digital
SPI
Serial Peripheral Interface
Serial Master Interface Controller
Samples per Second
SPIM
SPS
TMR
UART
USB
WDT
WWDT
Timer Controller
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
Watchdog Timer
Window Watchdog Timer
Table 3.1-1 List of Abbreviations
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4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 Selection Guide
4.1.1 NuMicro® NUC505 Base Series Selection Guide
[1]: *√ marked in the table means that only NUC505DS13Y supports Headphone Out.
[2]: The packages are not pin-to-pin compatible even though they are the same packages.
LQFP64*: 7x7mm
Connectivity
NUC505DLA
NUC505DL13Y
NUC505YLA
512
128
8
8
8
8
8
8
8
18
25
18
25
34
35
52
4
4
4
4
4
4
4
2
2
2
2
2
2
2
-
2
3
2
3
3
3
3
2
3
2
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
√
-
1
1
1
1
1
1
1
5CH
5CH
5CH
5CH
5CH
8CH
8CH
-
√
-
√
√
√
√
√
√
√
LQFP48
LQFP48
QFN48
QFN48
2048 128
1
-
1
-
4
-
512
512
512
128
128
128
√
-
NUC505YLA2Y
NUC505DSA
1
1
1
1
1
1
1
2
4
4
4
4
√
-
√
√*
√
LQFP64*
LQFP64*
QFN88
NUC505DS13Y
NUC505YO13Y
2048 128
2048 128
√
√
Table 4.1-1 NuMicro® NUC505 Base Series Selection Guide
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NUC505
4.1.2 NuMicro® NUC505 Base Series Naming Rule
A: 512KByte
Figure 4.1-1 NuMicro® NUC505 Base Series Selection Code
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NUC505
4.2 Pin Configuration
4.2.1 NuMicro® NUC505DLA LQFP 48-pin
37
24
23
22
21
20
19
18
17
16
15
14
13
PD.4
PB.5
38
AVDDADC
PB.4
39
AVSSADC
PB.3
40
PA.0
PB.2
41
PA.1
PB.1
42
PB.0
PA.2
43
LQFP 48-pin
VDD
PA.3
PA.4
44
45
46
47
48
PA.11
PA.10
PA.9
VDD12
VDD
LDO_CAP
VSS
PA.8
USB_REXT
Figure 4.2-1 NuMicro® NUC505DLA LQFP 48-pin Diagram
July. 26, 2018
Page 17 of 130
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NUC505
4.2.2 NuMicro® NUC505DL13Y LQFP 48-pin
37
24
23
22
21
20
19
18
17
16
15
14
13
PA.1
PB.2
38
PA.2
PB.1
39
PA.3
PB.0
40
PA.4
VDD
41
VDD12
PA.11
42
PB.10
PA.10
43
PB.11
PB.12
VDD
LQFP 48-pin
PA.9
44
45
46
47
48
PA.8
RTC_nRWAKE
RTC_RPWR
VBAT
VDD
LDO_CAP
VSS
USB_REXT
Figure 4.2-2 NuMicro® NUC505DL13Y LQFP 48-pin Diagram
July. 26, 2018
Page 18 of 130
Rev.1.08
NUC505
4.2.3 NuMicro® NUC505YLA QFN 48-pin
37
24
23
22
21
20
19
18
17
16
15
14
13
PD.4
PB.5
38
AVDDADC
PB.4
39
AVSSADC
PB.3
40
PA.0
PB.2
41
PA.1
PB.1
42
PB.0
PA.2
43
QFN 48-pin
VDD
PA.3
PA.4
44
45
46
47
48
PA.11
PA.10
PA.9
VDD12
VDD
LDO_CAP
VSS
PA.8
USB_REXT
Note: The thermal pad (EPD) should be connected to GND.
Figure 4.2-3 NuMicro® NUC505YLA QFN 48-pin Diagram
July. 26, 2018
Page 19 of 130
Rev.1.08
NUC505
4.2.4 NuMicro® NUC505YLA2Y QFN 48-pin
37
24
23
22
21
20
19
18
17
16
15
14
13
PA.1
PB.2
38
PA.2
PB.1
39
PA.3
PB.0
40
PA.4
VDD
41
VDD12
PA.11
42
PB.10
PA.10
43
QFN 48-pin
PB.11
PB.12
VDD
PA.9
44
45
46
47
48
PA.8
RTC_nRWAKE
RTC_RPWR
VBAT
VDD
LDO_CAP
VSS
USB_REXT
Note: The thermal pad (EPD) should be connected to GND.
Figure 4.2-4 NuMicro® NUC505YLA2Y QFN 48-pin Diagram
July. 26, 2018
Page 20 of 130
Rev.1.08
NUC505
4.2.5 NuMicro® NUC505DSA LQFP 64-pin
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.3
PB.2
AVSSADC
50
PA.0
51
PB.1
PA.1
52
PB.0
PA.2
53
VDD
PA.3
54
PC.10
PC.9
PA.4
55
VDD12
56
PC.8
PB.10
LQFP 64-pin
57
58
59
60
61
62
63
64
PB.11
PB.12
VDD
PA.15
PA.14
PA.13
PA.12
PA.11
PA.10
PA.9
PA.8
PC.11
PC.12
VDD
LDO_CAP
VSS
Figure 4.2-5 NuMicro® NUC505DSA LQFP 64-pin Diagram
July. 26, 2018
Page 21 of 130
Rev.1.08
NUC505
4.2.6 NuMicro® NUC505DS13Y LQFP 64-pn
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PA.0
PB.3
50
PA.1
PB.2
51
PA.2
PB.1
52
PA.3
PB.0
53
PA.4
VDD
54
PA.5
PA.15
PA.14
PA.13
PA.12
PA.11
PA.10
PA.9
55
PA.6
56
PA.7
LQFP 64-pin
57
58
59
60
61
62
63
64
VDD12
PB.10
PB.11
PB.12
VDD
PA.8
VDD
RTC_nRWAKE
RTC_RPWR
VBAT
LDO_CAP
VSS
Figure 4.2-6 NuMicro® NUC505DS13Y LQFP 64-pin Diagram
July. 26, 2018
Page 22 of 130
Rev.1.08
NUC505
4.2.7 NuMicro® NUC505YO13Y QFN 88-pin
67
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
AVDDADC
PB.3
68
AVSSADC
PB.2
69
PA.0
PB.1
70
PA.1
PB.0
71
PA.2
VDD
72
PA.3
PC.10
PC.8
73
PA.4
74
PA.5
PC.8
75
PA.6
PC.7
76
PA.7
PA.15
PA.14
PA.13
PA.12
PA.11
PA.10
PA.9
77
VDD12
QFN 88-pin
78
79
80
81
82
83
84
85
86
87
88
PB.10
PB.11
PB.12
VDD
PC.11
PC.12
PC.13
PC.14
VDD
PA.8
X32_OUT
X32_IN
RTC_nRWAKE
RTC_RPWR
VBAT
LDO_CAP
VSS
Note: The thermal pad (EPD) should be connected to GND.
Figure 4.2-7 NuMicro® NUC505YO13Y QFN 88-pin Diagram
July. 26, 2018
Page 23 of 130
Rev.1.08
NUC505
4.3 Pin Description
4.3.1 NuMicro® NUC505DLA LQFP 48-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP*
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
5
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I/O
O
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.14
General purpose digital I/O pin.
USB host-lite 1differential signal D+.
I2C1 clock pin.
USBH1_D+
I2C1_SCL
PB.15
I/O
I/O
I/O
A
General purpose digital I/O pin.
USB host-lite 1 differential signal D-.
I2C1 data input/output pin.
USBH1_D-
I2C1_SDA
VDD
6
7
Power supply for I/O ports, DC 3.3V.
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
XT1_IN
I
8
XT1_OUT
VDD12
O
9
A
10
11
12
13
USB_D-
USB_D+
AVDDUSB
USB_REXT
A
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
A
July. 26, 2018
Page 24 of 130
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NUC505
14
PA.8
I/O
O
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
General purpose digital I/O pin.
SPIM slave select pin.
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
I/O
O
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
15
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
SPIM MOSI (Master Out, Slave In) pin.
I2C1 clock pin.
I
16
I/O
I/O
O
SPIM_MOSI
I2C1_SCL
SD_CLK
O
SD/SDH mode - clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
SPIM MISO (Master In, Slave Out) pin.
I2C1 data input/output pin.
17
I/O
I/O
I/O
I
SPIM_MISO
I2C1_SDA
SD_CMD
VDD
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
18
19
A
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
I/O
I/O
I/O
I
20
I2C0_SDA
UART0_RXD
SD_DAT3
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
I/O
July. 26, 2018
Page 25 of 130
Rev.1.08
NUC505
21
22
PB.2
I/O
O
I
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
SD_CMD
PB.3
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
I/O
O
O
I
SPI0_CLK
SD_CLK
SYSCFG[2]
PB.4
SD/SDH mode – clock.
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
23
24
I/O
O
I
SPI0_MOSI
SYSCFG[3]
PB.5
I/O
I
SPI0_MISO
SD_nCD
USB_VBUS33
VSS
I
25
26
27
28
29
30
31
32
33
34
35
36
37
I
Detects whether USB is plug-in.
Ground
A
A
A
A
A
A
A
A
A
A
A
I/O
A
AVDDHP
Power supply for analog CODEC headphone, DC 3.3V.
Headphone left channel output pin.
Headphone right channel output pin.
Ground for analog CODEC headphone.
Headphone reference power.
LHPOUT
RHPOUT
AVSSHP
VMID
AVDDCODEC
MIC0_P
MIC0_N
MIC_BIAS
VDD12
Power supply for analog CODEC, DC 3.3V.
Microphone 0 positive input.
Microphone 0 negative input.
CODEC left line-in channel or Microphone bias.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
CODEC right line-in channel.
PD.4
RLINEIN
July. 26, 2018
Page 26 of 130
Rev.1.08
NUC505
38
39
40
AVDDADC
AVSSADC
PA.0
A
A
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP0
MFP0
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
I/O
A
ADC_CH0
PA.1
41
42
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
I/O
A
43
44
ADC_CH3
I2S_DI
PA.4
I
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
VDD12
O
A
45
46
47
48
Power supply for I/O ports, DC 1.2V
Power supply, DC 3.3V.
VDD
A
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
July. 26, 2018
Page 27 of 130
Rev.1.08
NUC505
4.3.2 NuMicro® NUC505DL13Y LQFP 48-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP*
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0_SCL
ICE_DAT
PD.1
I2C0 clock pin.
I/O
I/O
I/O
I/O
I
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0_SDA
PB.13
I2C0 data input/output pin.
General purpose digital I/O pin.
SPI1_MISO
USBH1_D-
UART2_nRTS
PWM_CH3
VDD
SPI1 MISO (Master In, Slave Out) pin.
USB host-lite 1 differential signal D-.
Request to Send output pin for UART2.
PWM channel3 output/capture input.
Power supply for I/O ports, DC 3.3V.
Ground.
I/O
O
I/O
A
5
6
VSS
A
7
XT1_IN
I
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
8
XT1_OUT
VDD12
O
9
A
10
11
12
13
14
USB_D-
USB_D+
AVDDUSB
USB_REXT
VBAT
A
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
Power supply by batteries for RTC, DC 3.3V.
A
A
July. 26, 2018
Page 28 of 130
Rev.1.08
NUC505
15
16
17
RTC_RPWR
RTC_nRWAKE
PA.8
O
I
MFP0
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
Enable external power control source when active high.
System power enable trigger when active low.
General purpose digital I/O pin.
SPIM slave select pin.
I/O
O
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
I/O
O
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
18
19
20
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
SPIM MOSI (Master Out, Slave In) pin.
I2C1 clock pin.
I
I/O
I/O
O
SPIM_MOSI
I2C1_SCL
SD_CLK
O
SD/SDH mode - clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
SPIM MISO (Master In, Slave Out) pin.
I2C1 data input/output pin.
I/O
I/O
I/O
I
SPIM_MISO
I2C1_SDA
SD_CMD
VDD
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
21
22
A
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
I/O
I/O
I/O
23
I2C0_SDA
July. 26, 2018
Page 29 of 130
Rev.1.08
NUC505
UART0_RXD
SD_DAT3
PB.2
I
MFP3
MFP4
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP3
MFP4
MFP0
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
I/O
I/O
O
24
25
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
SD_CMD
PB.3
I
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
I/O
O
SPI0_CLK
SD_CLK
O
SD/SDH mode – clock.
SYSCFG[2]
PB.4
I
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
26
27
28
29
I/O
O
SPI0_MOSI
SYSCFG[3]
PB.5
I
I/O
I
SPI0_MISO
SD_nCD
I
PB.6
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SD/SDH mode data line bit 0.
UART1_TXD
SD_DAT0
PB.7
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SD/SDH mode data line bit 1.
UART1_RXD
SD_DAT1
USB_VBUS33
PB.8
I/O
I
30
31
Detects whether USB is plug-in.
General purpose digital I/O pin.
USB host mode to control an external overcurrent source.
Timer1 event counter input/toggle output.
Clear to Send input pin for UART1.
SD/SDH mode data line bit 2.
I/O
O
USBH_PWEN
TM1_CNT_OUT
UART1_nCTS
SD_DAT2
I/O
I
I/O
July. 26, 2018
Page 30 of 130
Rev.1.08
NUC505
32
PB.9
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
USB host bus power over voltage detector.
Timer1 external capture input.
Request to Send output pin for UART1.
SD/SDH mode data line bit 3.
Ground
USBH_OVD
TM1_EXT
UART1_nRTS
SD_DAT3
VSS
I
O
I/O
A
33
34
35
36
AVDDADC
AVSSADC
PA.0
A
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
A
I/O
A
ADC_CH0
PA.1
37
38
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
39
40
I/O
A
ADC_CH3
I2S_DI
I
PA.4
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
VDD12
O
41
42
A
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
SPI1 slave select pin.
PB.10
I/O
O
SPI1_SS
I2C1_SCL
UART2_TXD
PWM_CH0
O
I2C1 clock pin.
O
Data transmitter output pin for UART2.
PWM channel0 output/capture input.
I/O
July. 26, 2018
Page 31 of 130
Rev.1.08
NUC505
43
PB.11
I/O
O
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
I2C1_SDA
UART2_RXD
PWM_CH1
PB.12
I/O
I
I2C1 data input/output pin.
Data receiver input pin for UART2.
PWM channel1 output/capture input.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
USB host-lite 1 differential signal D+
Clear to send input pin for UART2.
PWM channel2 output/capture input.
Power supply for I/O ports, DC 3.3V.
Power supply, DC 3.3V.
I/O
I/O
O
44
SPI1_MOSI
USBH1_D+
UART2_nCTS
PWM_CH2
VDD
I/O
I
I/O
A
45
46
47
48
VDD
A
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
July. 26, 2018
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4.3.3 NuMicro® NUC505YLA QFN 48-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP*
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
5
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I/O
O
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.14
General purpose digital I/O pin.
USB host-lite 1differential signal D+.
I2C1 clock pin.
USBH1_D+
I2C1_SCL
PB.15
I/O
I/O
I/O
A
General purpose digital I/O pin.
USB host-lite 1 differential signal D-.
I2C1 data input/output pin.
USBH1_D-
I2C1_SDA
VDD
6
7
Power supply for I/O ports, DC 3.3V.
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
XT1_IN
XT1_OUT
VDD12
I
8
O
9
A
10
11
12
13
14
USB_D-
USB_D+
AVDDUSB
USB_REXT
PA.8
A
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
General purpose digital I/O pin.
A
I/O
July. 26, 2018
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NUC505
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
O
I/O
O
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
SPIM slave select pin.
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
15
16
17
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
SPIM MOSI (Master Out, Slave In) pin.
I2C1 clock pin.
I
I/O
I/O
O
SPIM_MOSI
I2C1_SCL
SD_CLK
O
SD/SDH mode - clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
SPIM MISO (Master In, Slave Out) pin.
I2C1 data input/output pin.
I/O
I/O
I/O
I
SPIM_MISO
I2C1_SDA
SD_CMD
VDD
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
18
19
A
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
I/O
I/O
I/O
I
20
I2C0_SDA
UART0_RXD
SD_DAT3
PB.2
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
General purpose digital I/O pin.
I/O
I/O
21
July. 26, 2018
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NUC505
SPI0_SS
SD_CMD
PB.3
O
I
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP0
SPI0 slave select pin.
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
22
I/O
O
O
I
SPI0_CLK
SD_CLK
SYSCFG[2]
PB.4
SD/SDH mode – clock.
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
23
24
I/O
O
I
SPI0_MOSI
SYSCFG[3]
PB.5
I/O
I
SPI0_MISO
SD_nCD
USB_VBUS33
VSS
I
25
26
27
28
29
30
31
32
33
34
35
36
37
I
Detects whether USB is plug-in.
Ground
A
A
A
A
A
A
A
A
A
A
A
I/O
A
A
AVDDHP
Power supply for analog CODEC headphone, DC 3.3V.
Headphone left channel output pin.
Headphone right channel output pin.
Ground for analog CODEC headphone.
Headphone reference power.
LHPOUT
RHPOUT
AVSSHP
VMID
AVDDCODEC
MIC0_P
MIC0_N
MIC_BIAS
VDD12
Power supply for analog CODEC, DC 3.3V.
Microphone 0 positive input.
Microphone 0 negative input.
CODEC left line-in channel or Microphone bias.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
CODEC right line-in channel.
PD.4
RLINEIN
AVDDADC
38
Power supply for analog SAR-ADC, DC 3.3V.
July. 26, 2018
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39
40
AVSSADC
PA.0
A
I/O
A
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP0
MFP0
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
ADC_CH0
PA.1
41
42
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
43
44
I/O
A
ADC_CH3
I2S_DI
PA.4
I
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
VDD12
O
45
46
47
48
A
Power supply for I/O ports, DC 1.2V
Power supply, DC 3.3V.
LDO output pin.
VDD
A
LDO_CAP
VSS
A
A
Ground.
Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND.
July. 26, 2018
Page 36 of 130
Rev.1.08
NUC505
4.3.4 NuMicro® NUC505YLA2Y QFN 48-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP*
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0_SCL
ICE_DAT
PD.1
I2C0 clock pin.
I/O
I/O
I/O
I/O
I
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0_SDA
PB.13
I2C0 data input/output pin.
General purpose digital I/O pin.
SPI1_MISO
USBH1_D-
UART2_nRTS
PWM_CH3
VDD
SPI1 MISO (Master In, Slave Out) pin.
USB host-lite 1 differential signal D-.
Request to Send output pin for UART2.
PWM channel3 output/capture input.
Power supply for I/O ports, DC 3.3V.
Ground.
I/O
O
I/O
A
5
6
VSS
A
7
XT1_IN
I
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
8
XT1_OUT
VDD12
O
9
A
10
11
12
13
14
USB_D-
USB_D+
AVDDUSB
USB_REXT
VBAT
A
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
Power supply by batteries for RTC, DC 3.3V.
A
A
July. 26, 2018
Page 37 of 130
Rev.1.08
NUC505
15
16
17
RTC_RPWR
RTC_nRWAKE
PA.8
O
I
MFP0
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP1
MFP2
MFP4
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
Enable external power control source when active high.
System power enable trigger when active low.
General purpose digital I/O pin.
SPIM slave select pin.
I/O
O
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
I/O
O
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
18
19
20
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
SPIM MOSI (Master Out, Slave In) pin.
I2C1 clock pin.
I
I/O
I/O
O
SPIM_MOSI
I2C1_SCL
SD_CLK
O
SD/SDH mode - clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
SPIM MISO (Master In, Slave Out) pin.
I2C1 data input/output pin.
I/O
I/O
I/O
I
SPIM_MISO
I2C1_SDA
SD_CMD
VDD
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
21
22
A
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
I/O
I/O
I/O
23
I2C0_SDA
July. 26, 2018
Page 38 of 130
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NUC505
UART0_RXD
SD_DAT3
PB.2
I
MFP3
MFP4
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP3
MFP4
MFP0
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
I/O
I/O
O
24
25
General purpose digital I/O pin.
SPI0 slave select pin.
SPI0_SS
SD_CMD
PB.3
I
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
I/O
O
SPI0_CLK
SD_CLK
O
SD/SDH mode – clock.
SYSCFG[2]
PB.4
I
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
26
27
28
29
I/O
O
SPI0_MOSI
SYSCFG[3]
PB.5
I
I/O
I
SPI0_MISO
SD_nCD
I
PB.6
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SD/SDH mode data line bit 0.
UART1_TXD
SD_DAT0
PB.7
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SD/SDH mode data line bit 1.
UART1_RXD
SD_DAT1
USB_VBUS33
PB.8
I/O
I
30
31
Detects whether USB is plug-in.
General purpose digital I/O pin.
USB host mode to control an external overcurrent source.
Timer1 event counter input/toggle output.
Clear to Send input pin for UART1.
SD/SDH mode data line bit 2.
I/O
O
USBH_PWEN
TM1_CNT_OUT
UART1_nCTS
SD_DAT2
I/O
I
I/O
July. 26, 2018
Page 39 of 130
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32
PB.9
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
USB host bus power over voltage detector.
Timer1 external capture input.
Request to Send output pin for UART1.
SD/SDH mode data line bit 3.
Ground
USBH_OVD
TM1_EXT
UART1_nRTS
SD_DAT3
VSS
I
O
I/O
A
33
34
35
36
AVDDADC
AVSSADC
PA.0
A
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
A
I/O
A
ADC_CH0
PA.1
37
38
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
39
40
I/O
A
ADC_CH3
I2S_DI
I
PA.4
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
VDD12
O
41
42
A
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
SPI1 slave select pin.
PB.10
I/O
O
SPI1_SS
I2C1_SCL
UART2_TXD
PWM_CH0
O
I2C1 clock pin.
O
Data transmitter output pin for UART2.
PWM channel0 output/capture input.
I/O
July. 26, 2018
Page 40 of 130
Rev.1.08
NUC505
43
PB.11
I/O
O
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
General purpose digital I/O pin.
SPI1 serial clock pin.
SPI1_CLK
I2C1_SDA
UART2_RXD
PWM_CH1
PB.12
I/O
I
I2C1 data input/output pin.
Data receiver input pin for UART2.
PWM channel1 output/capture input.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
USB host-lite 1 differential signal D+
Clear to send input pin for UART2.
PWM channel2 output/capture input.
Power supply for I/O ports, DC 3.3V.
Power supply, DC 3.3V.
I/O
I/O
O
44
SPI1_MOSI
USBH1_D+
UART2_nCTS
PWM_CH2
VDD
I/O
I
I/O
A
45
46
47
48
VDD
A
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND.
July. 26, 2018
Page 41 of 130
Rev.1.08
NUC505
4.3.5 NuMicro® NUC505DSA LQFP 64-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.13
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
USB host-lite 1 differential signal D-.
Request to Send output pin for UART2.
PWM channel3 output/capture input.
General purpose digital I/O pin.
USB host-lite 1 differential signal D+.
I2C1 clock pin.
SPI1_MISO
USBH1_D-
UART2_nRTS
PWM_CH3
PB.14
I/O
O
I/O
I/O
I/O
O
5
6
7
USBH1_D+
I2C1_SCL
PB.15
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
USB host-lite 1differential signal D-.
I2C1 data input/output pin.
USBH1_D-
I2C1_SDA
PC.0
General purpose digital I/O pin.
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
Ground
SD_CMD
VDD
8
9
A
VSS
A
July. 26, 2018
Page 42 of 130
Rev.1.08
NUC505
10
11
12
13
14
15
16
17
XT1_IN
I
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
XT1_OUT
VDD12
O
A
USB_D-
A
USB_D+
AVDDUSB
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
General purpose digital I/O pin.
SPIM slave select pin.
USB_REXT
PA.8
A
I/O
O
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
I/O
O
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
18
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
I
19
I/O
I/O
SPIM_MOSI
SPIM MOSI (Master Out, Slave In) pin.
(Data 0 pin for Quad Mode I/O).
I2C1_SCL
SD_CLK
O
O
MFP2
MFP4
MFP0
MFP0
MFP1
I2C1 clock pin.
SD/SDH mode – clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
20
I/O
I/O
SPIM_MISO
SPIM MISO (Master In, Slave Out) pin.
(Data 1 pin for Quad Mode I/O).
I2C1_SDA
SD_CMD
PA.12
I/O
I
MFP2
MFP4
MFP0
I2C1 data input/output pin.
SD/SDH mode – command/response.
General purpose digital I/O pin.
21
I/O
July. 26, 2018
Page 43 of 130
Rev.1.08
NUC505
SPIM_D2
TM0_CNT_OUT
PA.13
I/O
I
MFP1
MFP2
MFP0
MFP1
MFP2
MFP4
MFP0
MFP2
MFP4
MFP0
MFP2
MFP4
MFP0
MFP1
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP2
MFP3
MFP4
SPIM data 2 pin for Quad Mode I/O.
Timer0 event counter input/toggle output.
General purpose digital I/O pin.
SPIM data 3 pin for Quad Mode I/O.
Timer0 external capture input.
SD/SDH mode – card detect.
General purpose digital I/O pin.
I2C0 clock pin.
22
I/O
I/O
I
SPIM_D3
TM0_EXT
SD_nCD
PA.14
I
23
24
I/O
O
I2C0_SCL
SD_DAT0
PA.15
I/O
I/O
I/O
I/O
I/O
O
SD/SDH mode data line bit 0.
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
SD_DAT1
PC.8
SD/SDH mode data line bit 1.
General purpose digital I/O pin.
I2S master clock output pin.
General purpose digital I/O pin.
I2S data input.
25
26
I2S_MCLK
PC.9
I/O
I
I2S_DI
TM2_CNT_OUT
PWM_CH0
PC.10
I/O
I/O
I/O
O
Timer2 event counter input/toggle output.
PWM channel0 output/capture input.
General purpose digital I/O pin.
I2S data output.
27
I2S_DO
TM2_EXT
PWM_CH1
VDD
I
Timer2 external capture input.
PWM channel1 output/capture input.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
I/O
A
28
29
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
I/O
July. 26, 2018
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30
PB.1
I/O
I/O
I
MFP0
MFP2
MFP3
MFP4
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP0
VDD
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
UART0_RXD
SD_DAT3
PB.2
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
General purpose digital I/O pin.
SPI0 slave select pin.
I/O
I/O
O
I
31
32
SPI0_SS
SD_CMD
PB.3
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
I/O
O
O
I
SPI0_CLK
SD_CLK
SYSCFG[2]
PB.4
SD/SDH mode – clock.
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
33
34
I/O
O
I
SPI0_MOSI
SYSCFG[3]
PB.5
I/O
I
SPI0_MISO
SD_nCD
USB_VBUS33
VSS
I
35
36
37
38
39
40
41
42
43
44
I
Power supply from USB host or HUB.
Ground.
A
AVDDHP
AP
A
Power supply for analog CODEC headphone, DC 3.3V.
Headphone left channel output pin.
Headphone right channel output pin.
Ground for analog CODEC headphone.
Headphone reference power.
Power supply for analog CODEC, DC 3.3V.
Microphone 0 positive input.
LHPOUT
RHPOUT
AVSSHP
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
A
A
VMID
A
AVDDCODEC
MIC0_P
MIC0_N
A
A
A
Microphone 0 negative input.
July. 26, 2018
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45
46
47
MIC_BIAS
VDD12
A
A
MFP0
MFP0
MFP0
MFP1
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
CODEC left line-in channel or Microphone bias.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
CODEC right line-in channel.
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
PD.4
I/O
A
RLINEIN
AVDDADC
AVSSADC
PA.0
48
49
50
A
A
I/O
A
ADC_CH0
PA.1
51
52
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
53
54
I/O
A
ADC_CH3
I2S_DI
I
PA.4
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
VDD12
O
55
56
A
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
SPI1 slave select pin.
PB.10
I/O
O
SPI1_SS
I2C1_SCL
UART2_TXD
PWM_CH0
PB.11
O
I2C1 clock pin.
O
Data transmitter output pin for UART2.
PWM channel0 output/capture input.
General purpose digital I/O pin.
SPI1 serial clock pin.
I/O
I/O
O
57
SPI1_CLK
July. 26, 2018
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NUC505
I2C1_SDA
UART2_RXD
PWM_CH1
PB.12
I/O
I
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP0
I2C1 data input/output pin.
Data receiver input pin for UART2.
PWM channel1 output/capture input.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
USB host-lite 1 differential signal D+
Clear to Send input pin for UART2.
PWM channel2 output/capture input.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2S left right channel clock.
I/O
I/O
O
58
SPI1_MOSI
USBH1_D+
UART2_nCTS
PWM_CH2
VDD
I/O
I
I/O
A
59
60
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I
I2S_LRCLK
TM3_CNT_OUT
PWM_CH2
PC.12
Timer3 event counter input/toggle output.
PWM channel2 output/capture input.
General purpose digital I/O pin.
I2S bit clock pin.
61
I2S_BCLK
TM3_EXT
PWM_CH3
VDD
Timer3 external capture input.
PWM channel3 output/capture input.
Power supply, DC 3.3V.
I/O
A
62
63
64
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
July. 26, 2018
Page 47 of 130
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4.3.6 NuMicro® NUC505DS13Y LQFP 64-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP0
MFP0
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.13
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
USB host-lite 1 differential signal D-.
Request to Send output pin for UART2.
PWM channel3 output/capture input.
General purpose digital I/O pin.
USB host-lite 1 differential signal D+.
I2C1 clock pin.
SPI1_MISO
USBH1_D-
UART2_nRTS
PWM_CH3
PB.14
I/O
O
I/O
I/O
I/O
O
5
6
7
USBH1_D+
I2C1_SCL
PB.15
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
USB host-lite 1differential signal D-.
I2C1 data input/output pin.
USBH1_D-
I2C1_SDA
PC.0
General purpose digital I/O pin.
SD/SDH mode – command/response.
Power supply for I/O ports, DC 3.3V.
Ground
SD_CMD
VDD
8
9
A
VSS
A
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10
11
12
13
14
15
16
17
18
19
20
XT1_IN
I
O
A
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
XT1_OUT
VDD12
USB_D-
A
USB_D+
AVDDUSB
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
Power supply by batteries for RTC, DC 3.3V.
Enable external power control source when active high.
System power enable trigger when active low.
General purpose digital I/O pin.
USB_REXT
VBAT
A
A
RTC_RPWR
RTC_nRWAKE
PA.8
O
I
I/O
O
I/O
O
I/O
O
I/O
I
SPIM_SS
I2S_LRCLK
UART1_TXD
PA.9
SPIM slave select pin.
I2S left right channel clock.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
21
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
SPIM serial clock pin.
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
I
22
I/O
I/O
SPIM_MOSI
SPIM MOSI (Master Out, Slave In) pin.
(Data 0 pin for Quad Mode I/O).
I2C1_SCL
SD_CLK
O
O
MFP2
MFP4
MFP0
MFP0
MFP1
I2C1 clock pin.
SD/SDH mode – clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
23
I/O
I/O
SPIM_MISO
SPIM MISO (Master In, Slave Out) pin.
(Data 1 pin for Quad Mode I/O).
July. 26, 2018
Page 49 of 130
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I2C1_SDA
SD_CMD
PA.12
I/O
I
MFP2
MFP4
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP4
MFP0
MFP2
MFP4
MFP0
MFP2
MFP4
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
MFP2
MFP3
MFP4
MFP0
MFP1
MFP4
I2C1 data input/output pin.
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPIM data 2 pin for Quad Mode I/O.
Timer0 event counter input/toggle output.
General purpose digital I/O pin.
SPIM data 3 pin for Quad Mode I/O.
Timer0 external capture input.
SD/SDH mode – card detect.
General purpose digital I/O pin.
I2C0 clock pin.
24
25
I/O
I/O
I
SPIM_D2
TM0_CNT_OUT
PA.13
I/O
I/O
I
SPIM_D3
TM0_EXT
SD_nCD
PA.14
I
26
27
I/O
O
I2C0_SCL
SD_DAT0
PA.15
I/O
I/O
I/O
I/O
A
SD/SDH mode data line bit 0.
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
SD_DAT1
VDD
SD/SDH mode data line bit 1.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
28
29
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
I/O
I/O
I/O
I
30
I2C0_SDA
UART0_RXD
SD_DAT3
PB.2
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
General purpose digital I/O pin.
SPI0 slave select pin.
I/O
I/O
O
31
SPI0_SS
SD_CMD
I
SD/SDH mode – command/response.
July. 26, 2018
Page 50 of 130
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32
PB.3
I/O
O
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP3
MFP4
MFP0
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
SD_CLK
O
SD/SDH mode – clock.
SYSCFG[2]
PB.4
I
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
33
34
35
36
I/O
O
SPI0_MOSI
SYSCFG[3]
PB.5
I
I/O
I
SPI0_MISO
SD_nCD
I
PB.6
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SD/SDH mode data line bit 0.
UART1_TXD
SD_DAT0
PB.7
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SD/SDH mode data line bit 1.
UART1_RXD
SD_DAT1
USB_VBUS33
PB.8
I/O
I
37
38
Detects whether USB is plug-in.
General purpose digital I/O pin.
USB host mode to control an external overcurrent source.
Timer1 event counter input/toggle output.
Clear to Send input pin for UART1.
SD/SDH mode data line bit 2.
I/O
O
USBH_PWEN
TM1_CNT_OUT
UART1_nCTS
SD_DAT2
PB.9
I/O
I
I/O
I/O
I
39
General purpose digital I/O pin.
USB host bus power over voltage detector.
Timer1 external capture input.
USBH_OVD
TM1_EXT
UART1_nRTS
SD_DAT3
I
O
Request to Send output pin for UART1.
SD/SDH mode data line bit 3.
I/O
July. 26, 2018
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40
41
42
43
44
45
46
47
48
49
VSS
A
AP
A
MFP0
VDD
Ground.
AVDDHP
LHPOUT
RHPOUT
AVSSHP
Power supply for analog CODEC headphone, DC 3.3V.
Headphone left channel output pin.
Headphone right channel output pin.
Ground for analog CODEC headphone.
Headphone reference power.
Power supply for analog CODEC, DC 3.3V.
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
General purpose digital I/O pin.
ADC channel 1 analog input.
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP0
MFP1
MFP0
A
A
VMID
A
AVDDCODEC
AVDDADC
AVSSADC
PA.0
A
A
A
I/O
A
ADC_CH0
PA.1
50
51
I/O
A
ADC_CH1
PA.2
I/O
A
ADC_CH2
I2S_MCLK
PA.3
O
52
53
I/O
A
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
ADC_CH3
I2S_DI
I
PA.4
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
PA.5
O
54
55
56
I/O
A
General purpose digital I/O pin.
ADC channel 5 analog input.
General purpose digital I/O pin.
ADC channel 6 analog input.
General purpose digital I/O pin.
ADC_CH5
PA.6
I/O
A
ADC_CH6
PA.7
I/O
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ADC_CH7
VDD12
A
A
MFP1
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
ADC channel 7 analog input.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
SPI1 slave select pin.
57
58
PB.10
I/O
O
SPI1_SS
I2C1_SCL
UART2_TXD
PWM_CH0
PB.11
O
I2C1 clock pin.
O
Data transmitter output pin for UART2.
PWM channel0 output/capture input.
General purpose digital I/O pin.
SPI1 serial clock pin.
I/O
I/O
O
59
SPI1_CLK
I2C1_SDA
UART2_RXD
PWM_CH1
PB.12
I/O
I
I2C1 data input/output pin.
Data receiver input pin for UART2.
PWM channel1 output/capture input.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
USB host-lite 1 differential signal D+
Clear to Send input pin for UART2.
PWM channel2 output/capture input.
Power supply for I/O ports, DC 3.3V.
Power supply, DC 3.3V.
I/O
I/O
O
60
SPI1_MOSI
USBH1_D+
UART2_nCTS
PWM_CH2
VDD
I/O
I
I/O
A
61
62
63
64
VDD
A
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
July. 26, 2018
Page 53 of 130
Rev.1.08
NUC505
4.3.7 NuMicro® NUC505YO13Y QFN 88-pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Pin No.
Pin Name
Type
MFP
Description
1
nRESET
I
MFP0
External reset input: active LOW, with an internal pull-up. Set
this pin low reset to initial state.
2
3
4
ICE_CLK
PD.0
O
I/O
O
MFP0
MFP0
MFP2
MFP0
MFP0
MFP2
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP0
MFP1
Serial wired debugger clock pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I
Serial wired debugger data pin. (In ICE mode)
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.13
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
USB host-lite 1 differential signal D-.
Request to Send output pin for UART2.
PWM channel3 output/capture input.
General purpose digital I/O pin.
USB host-lite 1differential signal D+.
I2C1 clock pin.
SPI1_MISO
USBH1_D-
UART2_nRTS
PWM_CH3
PB.14
I/O
O
I/O
I/O
I/O
O
5
6
USBH1_D+
I2C1_SCL
PB.15
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
USB host-lite 1 differential signal D-.
I2C1 data input/output pin.
USBH1_D-
I2C1_SDA
PC.0
7
8
General purpose digital I/O pin.
SD/SDH mode – command/response.
General purpose digital I/O pin.
SD/SDH mode – clock.
SD_CMD
PC.1
I/O
O
SD_CLK
July. 26, 2018
Page 54 of 130
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NUC505
Pin No.
Pin Name
PC.2
Type
I/O
I
MFP
Description
9
MFP0
MFP1
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP2
General purpose digital I/O pin.
SD_nCD
VDD
SD/SDH mode – card detect.
10
11
12
A
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
PC.3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
PC.4
General purpose digital I/O pin.
SD_DAT0
PC.5
SD/SDH mode data line bit 0.
13
14
General purpose digital I/O pin.
SD_DAT1
PC.6
SD/SDH mode data line bit 1.
General purpose digital I/O pin.
SD_DAT2
VDD12
SD/SDH mode data line bit 2.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Power supply for I/O ports, DC 1.2V
External 12 MHz (high speed) crystal input pin.
External 12 MHz (high speed) crystal output pin.
Power supply for I/O ports, DC 1.2V
USB differential signal D-.
XT1_IN
XT1_OUT
VDD12
I
O
A
USB_D-
USB_D+
AVDDUSB
USB_REXT
VBAT
A
A
USB differential signal D+.
A
Power supply for analog USB, DC 3.3V.
12.1 KΩ used internally for USB circuitry.
Power supply by batteries for RTC, DC 3.3V.
Enable external power control source when active high.
System power enable trigger when active low.
External 32.768 kHz (low speed) crystal input pin.
External 32.768 kHz (low speed) crystal output pin.
General purpose digital I/O pin.
A
A
RTC_RPWR
RTC_nRWAKE
X32_IN
X32_OUT
PA.8
O
I
I
O
I/O
O
SPIM_SS
I2S_LRCLK
SPIM slave select pin.
I/O
I2S left right channel clock.
July. 26, 2018
Page 55 of 130
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Pin No.
Pin Name
UART1_TXD
PA.9
Type
O
MFP
Description
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP1
Data transmitter output pin for UART1.
General purpose digital I/O pin.
SPIM serial clock pin.
29
I/O
O
SPIM_CLK
I2S_BCLK
UART1_RXD
SYSCFG[0]
PA.10
I/O
I
I2S bit clock pin.
Data receiver input pin for UART1.
System configuration setting bit 0.
General purpose digital I/O pin.
I
30
I/O
I/O
SPIM_MOSI
SPIM MOSI (Master Out, Slave In) pin.
(Data 0 pin for Quad Mode I/O).
I2C1_SCL
SD_CLK
O
O
MFP2
MFP4
MFP0
MFP0
MFP1
I2C1 clock pin.
SD/SDH mode – clock.
SYSCFG[1]
PA.11
I
System configuration setting bit 1.
General purpose digital I/O pin.
31
I/O
I/O
SPIM_MISO
SPIM MISO (Master In, Slave Out) pin.
(Data 1 pin for Quad Mode I/O).
I2C1_SDA
SD_CMD
PA.12
I/O
I
MFP2
MFP4
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP4
MFP0
MFP2
MFP4
I2C1 data input/output pin.
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPIM data 2 pin for Quad Mode I/O.
Timer0 event counter input/toggle output.
General purpose digital I/O pin.
SPIM data 3 pin for Quad Mode I/O.
Timer0 external capture input.
SD/SDH mode – card detect.
General purpose digital I/O pin.
I2C0 clock pin.
32
33
I/O
I/O
I/O
I/O
I/O
I
SPIM_D2
TM0_CNT_OUT
PA.13
SPIM_D3
TM0_EXT
SD_nCD
PA.14
I
34
I/O
O
I2C0_SCL
SD_DAT0
I/O
SD/SDH mode data line bit 0.
July. 26, 2018
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Pin No.
Pin Name
PA.15
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
MFP
Description
35
MFP0
MFP2
MFP4
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP0
MFP2
MFP3
MFP4
MFP0
FMP2
FMP3
MFP4
MFP0
MFP1
General purpose digital I/O pin.
I2C0 data input/output pin.
SD/SDH mode data line bit 1.
General purpose digital I/O pin.
SD/SDH mode data line bit 3.
General purpose digital I/O pin.
I2S master clock output pin.
General purpose digital I/O pin.
I2S data input.
I2C0_SDA
SD_DAT1
PC.7
36
37
38
SD_DAT3
PC.8
I2S_MCLK
PC.9
I/O
I
I2S_DI
TM2_CNT_OUT
PWM_CH0
PC.10
I/O
I/O
I/O
O
Timer2 event counter input/toggle output.
PWM channel0 output/capture input.
General purpose digital I/O pin.
I2S data output.
39
I2S_DO
TM2_EXT
PWM_CH1
VDD
I
Timer2 external capture input.
PWM channel1 output/capture input.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2C0 clock pin.
I/O
A
40
41
PB.0
I/O
O
I2C0_SCL
UART0_TXD
SD_DAT2
PB.1
O
Data transmitter output pin for UART0.
SD/SDH mode data line bit 2.
General purpose digital I/O pin.
I2C0 data input/output pin.
Data receiver input pin for UART0.
SD/SDH mode data line bit 3.
General purpose digital I/O pin.
SPI0 slave select pin.
I/O
I/O
I/O
I
42
I2C0_SDA
UART0_RXD
SD_DAT3
PB.2
I/O
I/O
O
43
SPI0_SS
July. 26, 2018
Page 57 of 130
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Pin No.
Pin Name
SD_CMD
PB.3
Type
I
MFP
Description
MFP4
MFP0
MFP1
MFP4
MFP0
MFP0
MFP1
MFP0
MFP0
MFP1
MFP4
MFP0
MFP3
MFP4
MFP0
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
SD/SDH mode – command/response.
General purpose digital I/O pin.
SPI0 serial clock pin.
44
I/O
O
SPI0_CLK
SD_CLK
O
SD/SDH mode – clock.
SYSCFG[2]
PB.4
I
System configuration setting bit 2.
General purpose digital I/O pin.
SPI0 MOSI (Master Out, Slave In) pin.
System configuration setting bit 3.
General purpose digital I/O pin.
SPI0 MISO (Master In, Slave Out) pin.
SD/SDH mode – card detect.
45
46
47
48
I/O
O
SPI0_MOSI
SYSCFG[3]
PB.5
I
I/O
I
SPI0_MISO
SD_nCD
I
PB.6
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SD/SDH mode data line bit 0.
UART1_TXD
SD_DAT0
PB.7
I/O
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SD/SDH mode data line bit 1.
UART1_RXD
SD_DAT1
USB_VBUS33
PB.8
I/O
I
49
50
Detects whether USB is plug-in.
General purpose digital I/O pin.
USB host mode to control an external overcurrent source.
Timer1 event counter input/toggle output.
Clear to Send input pin for UART1.
SD/SDH mode data line bit 2.
I/O
O
USBH_PWEN
TM1_CNT_OUT
UART1_nCTS
SD_DAT2
PB.9
I/O
I
I/O
I/O
I
51
General purpose digital I/O pin.
USB host bus power over voltage detector.
Timer1 external capture input.
USBH_VOD
TM1_EXT
I
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Page 58 of 130
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Pin No.
Pin Name
UART1_nRTS
SD_DAT3
VDD
Type
O
MFP
Description
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP0
MFP0
MFP0
MFP1
MFP0
MFP1
Request to Send output pin for UART1.
SD/SDH mode data line bit 3.
I/O
A
52
53
54
55
56
57
58
59
60
61
62
63
64
Power supply for I/O ports, DC 3.3V.
Power supply for analog CODEC headphone, DC 3.3V.
Headphone left channel output pin.
Internal CODEC function, keep floating.
Headphone right channel output pin.
Ground for analog CODEC headphone.
Headphone reference power.
AVDDHP
A
LHPOUT
VCMBF
RHPOUT
AVSSHP
A
A
A
A
VMID
A
AVDDCODEC
MIC0_P
MIC0_N
MIC_BIAS
VDD12
A
Power supply for analog CODEC, DC 3.3V.
Microphone 0 positive input.
A
A
Microphone 0 negative input.
A
CODEC left line-in channel or Microphone bias.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
Microphone 1 positive input.
A
PD.2
I/O
A
MIC1_P
PD.3
65
66
I/O
A
General purpose digital I/O pin.
Microphone 1 negative input.
MIC1_N
PD.4
I/O
A
General purpose digital I/O pin.
CODEC right line-in channel.
RLINEIN
AVDDADC
AVSSADC
PA.0
67
68
69
A
Power supply for analog SAR-ADC, DC 3.3V.
Ground pin for analog SAR-ADC.
General purpose digital I/O pin.
ADC channel 0 analog input.
A
I/O
A
ADC_CH0
PA.1
70
I/O
A
General purpose digital I/O pin.
ADC channel 1 analog input.
ADC_CH1
July. 26, 2018
Page 59 of 130
Rev.1.08
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Pin No.
Pin Name
PA.2
Type
I/O
A
MFP
Description
71
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP2
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP0
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
ADC channel 2 analog input.
I2S master clock output pin.
General purpose digital I/O pin.
ADC channel 3 analog input.
I2S data input.
ADC_CH2
I2S_MCLK
PA.3
O
72
73
I/O
A
ADC_CH3
I2S_DI
I
PA.4
I/O
A
General purpose digital I/O pin.
ADC channel 4 analog input.
I2S data output.
ADC_CH4
I2S_DO
PA.5
O
74
75
76
I/O
A
General purpose digital I/O pin.
ADC channel 5 analog input.
General purpose digital I/O pin.
ADC channel 6 analog input.
General purpose digital I/O pin.
ADC channel 7 analog input.
Power supply for I/O ports, DC 1.2V
General purpose digital I/O pin.
SPI1 slave select pin.
ADC_CH5
PA.6
I/O
A
ADC_CH6
PA.7
I/O
A
ADC_CH7
VDD12
77
78
A
PB.10
I/O
O
SPI1_SS
I2C1_SCL
UART2_TXD
PWM_CH0
PB.11
O
I2C1 clock pin.
O
Data transmitter output pin for UART2.
PWM channel0 output/capture input.
General purpose digital I/O pin.
SPI1 serial clock pin.
I/O
I/O
O
79
SPI1_CLK
I2C1_SDA
URAT2_RXD
PWM_CH1
I/O
I
I2C1 data input/output pin.
Data receiver input pin for UART2.
PWM channel1 output/capture input.
I/O
July. 26, 2018
Page 60 of 130
Rev.1.08
NUC505
Pin No.
Pin Name
PB.12
Type
I/O
O
MFP
Description
80
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP0
MFP1
MFP0
MFP0
MFP0
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
USB host-lite 1 differential signal D+.
Clear to Send input pin for UART2.
PWM channel2 output/capture input.
Power supply for I/O ports, DC 3.3V.
General purpose digital I/O pin.
I2S left right channel clock.
SPI1_MOSI
USBH1_D+
UART2_nCTS
PWM_CH2
VDD
I/O
I
I/O
A
81
82
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I
I2S_LRCLK
TM3_CNT_OUT
PWM_CH2
PC.12
Timer3 event counter input/toggle output.
PWM channel2 output/capture input.
General purpose digital I/O pin.
I2S bit clock pin.
83
I2S_BCLK
TM3_EXT
PWM_CH3
PC.13
Timer3 external capture input.
PWM channel3 output/capture input.
General purpose digital I/O pin.
USB host-lite 2 differential signal D+.
General purpose digital I/O pin.
USB host-lite 2 differential signal D-.
Power supply, DC 3.3V.
I/O
I/O
I/O
I/O
I/O
A
84
85
USBH2_D+
PC.14
USBH2_D-
VDD
86
87
88
LDO_CAP
VSS
A
LDO output pin.
A
Ground.
Note: The thermal pad (EPD) on the bottom of QFN package should be connected to GND.
July. 26, 2018
Page 61 of 130
Rev.1.08
NUC505
4.3.8 Summary GPIO Multi-function Pin Description
MPF0
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PA.8
PA.9
PA.10
PA.11
PA.12
PA.13
PA.14
PA.15
PB.0
PB.1
PB.2
PB.3
PB.4
PB.5
PB.6
PB.7
PB.8
PB.9
PB.10
PB.11
PB.12
PB.13
PB.14
PB.15
MPF1
ADC_CH0
ADC_CH 1
ADC_CH 2
ADC_CH 3
ADC_CH 4
ADC_CH 5
ADC_CH 6
ADC_CH 7
SPIM_SS
MPF2
MPF3
MPF4
Other
Driving
2~16mA
2~16mA
2~16mA
2~16mA
2~16mA
2~16mA
2~16mA
2~16mA
8mA
I2S_LRCLK
I2S_BCLK
I2C1_SCL
I2C1_SDA
TM0_CNT_OUT
TM0_EXT
UART1_TXD
UART1_RXD
SPIM_CLK
SPIM_MOSI
SPIM_MISO
SPIM_D2
SYSCFG[0]
SYSCFG[1]
8mA
SD_CLK
SD_CMD
8mA
8mA
8mA
SPIM_D3
SD_nCD
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
SD_CMD
SD_CLK
8mA
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
4mA
4mA
UART0_TXD
UART0_RXD
4mA
4mA
SPI0_SS
4mA
SPI0_CLK
SPI0_MOSI
SPI0_MISO
SYSCFG[2]
SYSCFG[3]
4mA
4mA
SD_nCD
4mA
UART1_TXD
UART1_RXD
UART1_nCTS
UART1_nRTS
UART2_TXD
UART2_RXD
UART2_nCTS
UART2_nRST
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
PWM_CH0
PWM_CH1
PWM_CH2
PWM_CH3
4mA
4mA
USBH_PWEN
USBH_OVD
SPI1_SS
TM1_CNT_OUT
TM1_EXT
4mA
4mA
I2C1_SCL
I2C1_SDA
USBH1_D+
USBH1_D-
I2C1_SCL
I2C1_SDA
4mA
SPI1_CLK
4mA
SPI1_MOSI
SPI1_MISO
USBH1_D+
USBH1_D-
8mA
8mA
8mA
8mA
July. 26, 2018
Page 62 of 130
Rev.1.08
NUC505
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PC.6
PC.7
PC.8
PC.9
SD_CMD
SD_CLK
SD_nCD
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
4mA
4mA
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
I2S_MCLK
I2S_DI
TM2_CNT_OUT
TM2_EXT
PWM_CH0
PWM_CH1
PWM_CH2
PWM_CH3
PC.10
PC.11
PC.12
I2S_DO
4mA
4mA
4mA
I2S_LRCLK
I2S_BCLK
TM3_CNT_OUT
TM3_EXT
PC.13
PC.14
PD.0
PD.1
PD.2
PD.3
PD.4
USBH2_D+
USBH2_D-
8mA
8mA
I2C0_SCL
I2C0_SDA
ICE_CLK
ICE_DAT
MIC1_P
MIC1_N
RLINEIN
4mA
4mA
2~16mA
2~16mA
2~16mA
July. 26, 2018
Page 63 of 130
Rev.1.08
NUC505
4.3.9 GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[2:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[6:4]=0x5.
Group
Pin Name
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC_CH7
MIC1_P
GPIO
PA.0
PA.1
PA.2
PA.3
PA.4
PA.5
PA.6
PA.7
PD.2
PD.3
PD.4
PA.14
PB.0
PD.0
PA.15
PB.1
PD.1
PA.10
PB.10
PB.14
PA.11
PB.11
PB.15
PA.2
PC.8
PA.9
PC.12
PA.8
PC.11
MFP*
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP1
MFP2
MFP1
MFP2
MFP1
Type
A
Description
ADC0 analog input.
A
ADC1 analog input.
A
ADC2 analog input.
A
ADC3 analog input.
ADC
A
ADC4 analog input.
A
ADC5 analog input.
A
ADC6 analog input.
A
ADC7 analog input.
A
Audio MIC1 analog positive input pin
Audio MIC1 analog negative input pin
Audio right line-in analog pin.
I2C0 clock pin.
CODEC
MIC1_N
A
RLINEIN
A
I2C0_SCL
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C0_SDA
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SDA
I2C1_SDA
I2S_MCLK
I2S_MCLK
I2S_BCLK
I2S_BCLK
I2S_LRCLK
I2S_LRCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I2C0 clock pin.
I2C0 clock pin.
I2C0
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C1 clock pin.
I2C1 clock pin.
I2C1 clock pin.
I2C1
I2C1 data input/output pin.
I2C1 data input/output pin.
I2C1 data input/output pin.
I2S master clock output pin.
I2S master clock output pin.
I2S bit clock pin.
O
I/O
I/O
I/O
I/O
I2S
I2S bit clock pin.
I2S left right channel pin.
I2S left right channel pin.
July. 26, 2018
Page 64 of 130
Rev.1.08
NUC505
Group
Pin Name
I2S_DO
GPIO
PA.4
MFP*
MFP2
MFP1
MFP2
MFP1
MFP0
MFP0
MFP4
MFP3
MFP4
MFP3
MFP4
MFP3
MFP4
MFP3
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP2
MFP2
MFP2
MFP2
MFP2
Type
O
Description
I2S data output.
I2S_DO
PC.10
PA.3
O
I2S data output.
I2S_DI
I
I2S data input.
I2S_DI
PC.9
I
I2S data input.
ICE_CLK
PD.0
I
Serial wired debugger clock pin
Serial wired debugger data pin
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
PWM output/capture input.
SPIM slave select pin.
ICE
ICE_DAT
PD.1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PWM_CH0
PWM_CH0
PWM_CH1
PWM_CH1
PWM_CH2
PWM_CH2
PWM_CH3
PWM_CH3
SPIM_SS
PB.10
PC.9
PB.11
PC.10
PB.12
PC.11
PB.13
PC.12
PA.8
PWM
SPIM_CLK
SPIM_MOSI
SPIM_MISO
SPIM_D2
PA.9
O
SPIM serial clock pin.
PA.10
PA.11
PA.12
PA.13
PB.2
I/O
I/O
I/O
I/O
O
SPIM MOSI (Master Out, Slave In) pin.
SPIM MISO (Master In, Slave Out) pin.
SPIM data-2 bit in quad mode.
SPIM data-3 bit in quad mode.
SPI0 slave select pin.
SPIM
SPIM_D3
SPI0_SS
SPI0_CLK
SPI0_MOSI
SPI0_MISO
SPI1_SS
PB.3
O
SPI0 serial clock pin.
SPI0
SPI1
PB.4
I/O
I/O
O
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 MISO (Master In, Slave Out) pin.
SPI1 slave select pin.
PB.5
PB.10
PB.11
PB.12
PB.13
PA.12
PA.13
PB.8
SPI1_CLK
SPI1_MOSI
SPI1_MISO
TM0_CNT_OUT
TM0_EXT
TM1_CNT_OUT
TM1_EXT
TM2_CNT_OUT
O
SPI1 serial clock pin.
I/O
I/O
I/O
I
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
Timer0 event counter input / toggle output.
Timer0 external counter input
Timer1 event counter input / toggle output.
Timer1 external counter input
Timer2 event counter input / toggle output.
Timer
I/O
I
PB.9
PC.9
I/O
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Group
Pin Name
GPIO
PC.10
PC.11
PC.12
PB.1
MFP*
MFP2
MFP2
MFP2
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP1
Type
Description
TM2_EXT
I
I/O
I
Timer2 external counter input
TM3_CNT_OUT
TM3_EXT
Timer3 event counter input / toggle output.
Timer3 external counter input
UART0_RXD
UART0_TXD
UART1_RXD
UART1_RXD
UART1_TXD
UART1_TXD
UART1_nCTS
UART1_nRTS
UART2_RXD
UART2_TXD
UART2_nCTS
UART2_nRTS
USBH_PWEN
I
Data receiver input pin for UART0.
Data transmitter output pin for UART0.
Data receiver input pin for UART1.
Data receiver input pin for UART1.
Data transmitter output pin for UART1.
Data transmitter output pin for UART1.
Clear to Send input pin for UART1.
Request to Send output pin for UART1.
Data receiver input pin for UART2.
Data transmitter output pin for UART2.
Clear to Send input pin for UART2.
Request to Send output pin for UART2.
UART0
UART1
PB.0
O
I
PA.9
PB.7
I
PA.8
O
O
I
PB.6
PB.8
PB.9
O
I
PB.11
PB.10
PB.12
PB.13
PB.8
O
I
UART2
O
O
USB host to control an external overcurrent
source.
USBH_VOD
USBH2_D+
USBH2_D-
USBH1_D+
USBH1_D+
USBH1_D-
USBH1_D-
SD_CLK
PB.9
MFP1
MFP1
MFP1
MFP2
MFP1
MFP2
MFP1
MFP4
MFP4
MFP1
MFP4
MFP4
MFP1
MFP4
MFP4
MFP1
MFP4
I
A
A
A
A
A
A
O
O
O
O
O
O
I
USB host lite over voltage detector
USB host lite 2 differential signal D+.
USB host lite 2 differential signal D-.
USB host lite 1 differential signal D+.
USB host lite 1 differential signal D+.
USB host lite 1 differential signal D-.
USB host lite 1 differential signal D-.
SD/SDH mode - clock
PC.13
PC.14
PB.12
PB.14
PB.13
PB.15
PA.10
PB.3
USB Host Lite
SD_CLK
SD/SDH mode – clock
SD_CLK
PC.1
SD/SDH mode – clock
SD_CMD
SD_CMD
SD_CMD
SD_nCD
PA.11
PB.2
SD/SDH mode – command/response
SD/SDH mode – command/response
SD/SDH mode – command/response
SD/SDH mode – card detect.
SDH
PC.0
PA.13
PB.5
SD_nCD
I
SD/SDH mode – card detect.
SD_nCD
PC.2
I
SD/SDH mode – card detect.
SD_DAT0
PA.14
I/O
SD/SDH mode data line bit 0.
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Group
Pin Name
SD_DAT0
SD_DAT0
SD_DAT1
SD_DAT1
SD_DAT1
SD_DAT2
SD_DAT2
SD_DAT2
SD_DAT3
SD_DAT3
SD_DAT3
GPIO
PB.6
PC.4
PA.15
PB.7
PC.5
PB.0
PB.8
PC.6
PB.1
PB.9
PC.7
MFP*
MFP4
MFP1
MFP4
MFP4
MFP1
MFP4
MFP4
MFP1
MFP4
MFP4
MFP1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
SD/SDH mode data line bit 0.
SD/SDH mode data line bit 0.
SD/SDH mode data line bit 1.
SD/SDH mode data line bit 1.
SD/SDH mode data line bit 1.
SD/SDH mode data line bit 2.
SD/SDH mode data line bit 2.
SD/SDH mode data line bit 2.
SD/SDH mode data line bit 3.
SD/SDH mode data line bit 3.
SD/SDH mode data line bit 3.
Table 4.3-1 NUC505 GPIO Multi-function Table
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5
BLOCK DIAGRAM
5.1 NuMicro® NUC505 Series Block Diagram
Memory
Power Control
Timer / PWM
ADC/AUDIO/OTP
32-bit Timer
4-ch
12-bit ADC
with 8-ch
LDO 1.2V
ARM Cortex® _M4
(DSP & FPU)
100 MHz
RTC
(RTC_VDD33)
24-bit
Audio Codec
SRAM
128 KB
Watchdog
Timers
I²S
POR,
LVR, LVD
PWM
4-ch
Multi-entry OTP
AHB Bus
APB Bus
Clock Control
Connectivity
Connectivity
System PLL
Audio PLL
SPIM
I²C X 2
SD Host
SPI X 2
UART X 3
HS Ext. Crystal Osc.
12 MHz
USB 2.0 Full Speed Host
USB 2.0 High Speed Device
LIRC / LS Ext.
Crystal Osc. 32.768 kHz
General Purpose I/O
Figure 5.1-1 NuMicro® NUC505 Block Diagram
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6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M4 Core
The Cortex® -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes a NVIC component. The processor
has optional hardware debug functionality, which can execute Thumb code, and is compatible
with other Cortex® -M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
an exception return. The Cortex® -M4F is a processor with the same capability as the Cortex® -M4
processor and includes floating point arithmetic functionality. The NUC505 is embedded with
Cortex® -M4F processor. Throughout this document the name Cortex® -M4 refers to both Cortex® -
M4 and Cortex® -M4F processors. The following figure shows the functional controller of the
processor.
Figure 6.1-1 Cortex® -M4 Block Diagram
Cortex® -M4 processor features:
A low gate count processor core, with low latency interrupt processing that has:
─
A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual.
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─
─
─
─
─
Banked Stack Pointer (SP).
Hardware integer divide instructions, SDIV and UDIV.
Handler and Thread modes.
Thumb and Debug states.
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency.
─
Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit.
─
─
Support for ARMv6 big-endian byte-invariant or little-endian accesses.
Support for ARMv6 unaligned accesses.
Floating Point Unit (FPU) in the Cortex® -M4F processor providing:
─
─
32-bit instructions for single-precision (C float) data-processing operations.
Combined Multiply and Accumulate instructions for increased precision (Fused
MAC).
─
Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root.
─
─
Hardware support for denormals and all IEEE rounding modes.
32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers.
─
Decoupled three-stage pipeline.
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to
achieve low latency interrupt processing. Features include:
─
External interrupts. Configurable from 1 to 240; the NUC505 has been configured
with 32 interrupts.
─
─
─
Bits of priority, configurable from bit 3 to bit 7.
Dynamic reprioritization of interrupts.
Supports priority grouping which enables selection of preempting interrupt levels
and non-preempting interrupt levels.
─
Supports tril-chaining and late arrival of interrupts, which enables back-to- back
interrupt processing without the overhead of state saving and restoration between
interrupts.
─
─
Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead.
Supports Wake-up Interrupt Controller (WIC) with Power-down mode.
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
─
─
─
Eight memory regions.
Sub Region Disable (SRD), enabling efficient use of memory regions.
The ability to enable a background region that implements the default memory
map attributes.
Low-cost debug solution that features:
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─
Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is asserted.
─
─
─
─
Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)
debug access. But NUC505 only supports SW-DP.
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
code patches.
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling.
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,
and System bus interfaces.
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface.
─
─
─
─
─
Bit-band support that includes atomic bit-band write and read operations.
Memory access alignment.
Write buffer for buffering of write data.
Exclusive access transfers for multiprocessor systems.
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6.2 System Manager
6.2.1 Overview
The following functions are included in system manager section
System reset
System memory map
Bus arbitration algorithm
Global control registers
System Timer (Systick)
Nested Vectored Interrupt Control (NVIC)
System control register map and description
6.2.2 System Reset
Hardware Reset
─
─
─
─
Power-on Reset (POR)
Low level on the nRESET Pin (nRST)
Watchdog time-out reset (WDT)
Low voltage reset (LVR)
Software Reset
─
─
─
SYSRESETREQ (AIRCR[2])
CPU Reset (SYS_IPRST0[0])
CHIPRST (SYS_IPRST0 [1])
Note1: SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset
SPIM function, vector map module parameter setting, and PA.8~PA.15 multi-function setting.
Note2: CPU Rest (SYS_IPRST0[0]) only resets the CPU function.
Note3: CHIPRST (SYS_IPRST0[1]) reset the whole chip including all peripherals.
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6.2.3 System Power-on Setting
The power-on setting is used to configure the chip to enter the specified state when the chip is
powered up or reset. Since each pin of power-on setting has an internal pulled-up resistor during
reset period, if the application needs to set the configuration to “0”, the proper pull-down must be
added for the corresponding configuration pins.
PB.4
PB.3
PA.10
PA.9 Description
Register Mapping
SYS_BOOTSET[3:0]
SYS_BOOTSET[3:0]
SYS_BOOTSET[3:0]
SYS_BOOTSET[3:0]
SYS_BOOTSET[3:0]
SYS_BOOTSET[3:0]
1
1
1
1
0
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
0
Boot from Internal MCP SPI Flash
Boot from USB
Boot from External SPI Flash
Boot from ICP Mode
SWD/ICE Mode with Internal SPI Flash
SWD/ICE Mode with External SPI Flash
Table 6.2-1 System Power-on Setting Guide
6.2.4 System Power Distribution
In this chip, power distribution is divided into five segments:
Audio CODEC power from AVDDCODEC, AVDDHP, and AVSSHP provides the power for
audio CODEC operation.
Analog-to-Digital converter (ADC) power from AVDDADC and AVSSADC provides the
power for ADC operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.2 V power for digital operation and I/O pins.
USB transceiver power from AVDDUSB offers the power for operating the USB
transceiver.
RTC power from VBAT provides the power for RTC and 80 bytes backup registers.
The outputs of internal voltage regulators, LDO and VDD, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDDCODEC and AVDDADC) should
be the same voltage level of the digital power (VDD). The following figure shows the power
distribution of the NuMicro® NUC505.
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32.768 kHz
crystal
oscillator
3.3V
3.3V
USB_D+
USB_D-
USB
Transceiver
AVDDCODEC
12-bit ADC
3.3V
24-bit Audio
CODEC
32 bytes
backup
register
AVDDHP
AVSSHP
RTC
AVDDUSB
3.3V
1.2V
LDO_CAP
4.7uF
PLL
POR12
SRAM
Digital Logic
XT1_OUT
XT1_IN
12 MHz crystal
oscillator
3.3V à 1.2V
Power On
Control
GPIO
POR33
IO Cell
LDO
3.3V
Low
Voltage
Detector
Low
Voltage
Reset
NUC505 power distribution
Figure 6.2-1 NuMicro® NUC505 Power Distribution Diagram
6.2.5 System Memory Mapping
The NUC505 provides a 4G-byte address space for programmers. The memory locations assigned to
each on-chip modules are shown in Table 6.2-2. The detailed registers and memory addressing or
programming will be described in the following sections for individual on-chip modules. The NUC505
only supports little-endian data format.
Address Space
Token
Modules
Memory Space
0x1FFF_0000 – 0x1FFF_7FFF
IBR_BA
Internal Boot ROM (IBR) Memory Space
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0x2000_0000 – 0x2000_7FFF
0x2000_8000 – 0x2000_FFFF
0x2001_0000 – 0x2001_7FFF
0x2001_8000 – 0x2001_FFFF
0x0000_0000 – 0x0FFF_FFFF
SRAM1_BA
SRAM2_BA
SRAM3_BA
SRAM4_BA
FLASH_BA
SRAM1 Memory Space (32K Bytes)
SRAM2 Memory Space (32K Bytes)
SRAM3 Memory Space (32K Bytes)
SRAM4 Memory Space (32K Bytes)
SPI Flash/ROM Memory Space
AHB Controllers Space (0x4000_0000 ~0x4000FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_7000 – 0x4000_7FFF
0x4000_9000 – 0x4000_9FFF
0x4000_A000 – 0x4000_AFFF
0x4000_B000 – 0x4000_BFFF
GCR_BA
CLK_BA
Global Control Registers
Clock Control Registers
SPIM Control Register
SPIM_BA
USBD_BA
SDH_BA
USBH_BA
USB Device Controller Registers
SDH Control Register
USB Host Controller Registers
APB Controllers Space (0x400E_0000~0x400E_FFFF)
0x400E_1000 – 0x400E_1FFF
0x400E_2000 – 0x400E_2FFF
0x400E_3000 – 0x400E_3FFF
0x400E_4000 – 0x400E_4FFF
0x400E_5000 – 0x400E_5FFF
0x400E_6000 – 0x400E_6FFF
0x400E_7000 – 0x400E_7FFF
0x400E_8000 – 0x400E_8FFF
0x400E_9000 – 0x400E_9FFF
0x400E_A000 – 0x400E_AFFF
0x400E_B000 – 0x400E_BFFF
0x400E_C000 – 0x400E_CFFF
0x400E_D000 – 0x400E_DFFF
0x400E_E000 – 0x400E_EFFF
0x400E_F000 – 0x400E_FFFF
SPI1_BA
ADC_BA
SPI1 Master/Slave Controller Registers (SPI1)
ADC Controller Registers
GPIO_BA
I2C0_BA
GPIO Controller Registers
I2C0 Interface Control Registers
I2C1 Interface Control Registers
PWM Controller Registers
I2C1_BA
PWM_BA
RTC_BA
Real Time Clock (RTC) Control Register
Inter-IC Sound (I2S) Control Register
SPI0 Master/Slave Controller Registers (SPI0)
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
UART0 Control Registers (Normal Speed)
UART1 Control Registers (High Speed)
UART2 Control Registers (High Speed)
WDT Interface Control Registers
I2S_BA
SPI0_BA
Timer01_BA
Timer23_BA
UART0_BA
UART1_BA
UART2_BA
WDT_BA
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6.2-2 Address Space Assignments for On-Chip Controllers
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6.2.6 SRAM Memory Organization
The NUC505 supports embedded SRAM with a total of 128 Kbytes and the SRAM organization is
separated to four banks: SRAM bank0, SRAM bank1, SRAM bank2, and SRAM bank3. Each of these
four banks has 32 Kbytes address space and can be accessed simultaneously.
Supports a total of 128 Kbytes SRAM
Supports byte / half word / word write
Supports fixed 32 Kbytes SRAM banks for independent access
Supports remap address to 0x1FF0_0000
Supports remap arbitrary memory block of 128 Kbytes SRAM to 0x0000_0000 by using
vector map module
AHB interface
controller
SRAM decoder
SRAM decoder
SRAM decoder
SRAM bank0
SRAM bank1
SRAM bank2
AHB interface
controller
AHB interface
controller
AHB interface
controller
SRAM bank3
SRAM decoder
Figure 6.2-2 SRAM Block Diagram
Figure 6.2-3 shows the SRAM organization of NUC505. There are four SRAM banks in NUC505 and
each bank is addressed to 32 Kbytes. The bank0 address space is from 0x2000_0000 to
0x2000_7FFF. The bank1 address space is from 0x2000_8000 to 0x2000_FFFF. The bank2 address
space is from 0x2001_0000 to 0x2001_7FFF. The bank3 address space is from 0x2001_8000 to
0x2001_FFFF.
The address of each bank is remapping from 0x2000_0000 to 0x1FF0_0000. CPU can access SRAM
bank0 through 0x2000_0000 to 0x2000_7FFF or 0x1FF0_0000 to 0x1FF0_7FFF, SRAM bank1
through 0x2000_8000 to 0x2000_FFFF or 0x1FF0_8000 to 0x1FF0_FFFF, SRAM bank2 through
0x2001_0000 to 0x2001_7FFF or 0x1FF1_0000 to 0x1FF1_7FFF, and SRAM bank3 through
0x2001_8000 to 0x2001_FFFF or 0x1FF1_8000 to 0x1FF1_FFFF.
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0x3FFF_FFFF
Reserved
0x2002_0000
0x2001_FFFF
0x1FF1_FFFF
32K byte
SRAM bank3
32K byte
remapping
SRAM bank3
0x2001_8000
0x2001_7FFF
0x1FF1_8000
0x1FF1_7FFF
32K byte
SRAM bank2
32K byte
SRAM bank2
remapping
remapping
remapping
0x2001_0000
0x2000_FFFF
0x1FF1_0000
0x1FF0_FFFF
32K byte
SRAM bank1
32K byte
SRAM bank1
0x2000_8000
0x2000_7FFF
0x1FF0_8000
0x1FF0_7FFF
32K byte
SRAM bank0
32K byte
SRAM bank0
0x2000_0000
0x1FF0_0000
128K byte device
128K byte device
Figure 6.2-3 SRAM Memory Organization
Figure 6.2-4 shows the vector map module diagram. Arbitrary memory block in 128 Kbytes SRAM
can be remapped to the SPI flash block and its start address is 0x0000_0000. The location and
size with the memory block are controlled by the register SYS_RVMPADDR[31:0] and the register
SYS_RVMPLEN[31:24]. The SYS_RVMPADDR indicates the start address of the memory block
and SYS_RVMPLEN describes about the size of the memory block (the unit is 1 Kbyte).
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0x001F_FFFF
Example:
SYS_RVMPADDR[31:0] = 0x2000_AB00
SYS_RVMPLEN[31:24] = 0x02
SPI
Flash
0x2001_FFFF
0x2000_B2FF
2 Kbytes
Vector
0x2000_AB00
mapping
0x0000_0800
0x0000_07FF
2 Kbytes
0x0000_0000
0x2000_0000
Figure 6.2-4 Vector Map Module Block
6.2.7 AHB Bus Arbitration
The internal bus of NUC505 is an AHB-Compliant Bus and supports to connect with the standard AHB
master or slave. The NUC505 AHB arbiter provides a choice of two arbitration algorithms for
simultaneous requests. These two arbitration algorithms are the Fixed-priority mode and the Round-
robin- priority (rotate) mode. The selection of modes and types is determined in the PRISEL field of
the SYS_AHBCTL control register.
6.2.7.1 Fixed Priority Mode
Fixed priority mode is selected if PRISEL = 0. The order of priorities on the AHB mastership among
the on-chip master modules are listed in Table 6.2-3.
Priority Sequence
AHB Bus Priority
(PRISEL = 0)
1 (Lowest)
Cortex-M4 I
Cortex-M4 D
Cortex-M4 System
SPIM
2
3
4
5
USBD
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6
6
USBH
SDH
I2S
8 (Highest)
Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode If two or more master modules request to
access AHB bus at the same time, the higher priority request will get the permission to access AHB
bus.
Priority Sequence
AHB Bus Priority
(PRISEL = 0)
1 (Lowest)
Cortex-M4 I
Cortex-M4 D
Cortex-M4 System
SPIM
2
3
4
5
USBD
6
6
USBH
SDH
8 (Highest)
I2S
Table 6.2-3 AHB Bus Priority Order in Fixed Priority Mode
The SPI flash controller normally has the lowest priority (except CPU interface) under the fixed priority
mode. The NUC505 provides a mechanism to raise the priority of CPU request to the highest. If the
CPUHPRI bit (bit-4 of SYS_AHBCTL control register) is set to 1, the PRISTS bit (bit-5 of
SYS_AHBCTL control register) will be automatically set to 1 while an unmasked external IRQ occurs.
Under this circumstance, the ARM core will become the highest priority to access AHB bus.
The programmer can recover the original priority order by directly writing “1” to clear the PRISTS bit.
For example, this can be done that at the end of an interrupt service routine. Note that PRISTS only
can be automatically set to 1 by an external interrupt when CPUHPRI = 1. It will not take effect for a
programmer to directly write 1 to PRISTS to raise ARM core’s AHB priority.
6.2.7.2 Round Robin Priority Mode
Round-robin priority mode is selected if PRISEL = 1. The AHB bus arbiter uses a round robin
arbitration scheme for every master module to gain the bus ownership in turn. That is the requestor
having the highest priority becomes the lowest-priority requestor after it has been granted access.
6.2.7.3 Rotate rule Example
In the default sequence of AHB Master Bus, the priority is I2S>SDH > USBH > USBD >SPIM >M4(S) >
M4(D) > M4(I).
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6.2.8 System Timer (Systick)
The Cortex® -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be
used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value Register
(SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, and then decrement on subsequent clocks. When the counter
transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than
an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M4 Technical Reference Manual”
and “ARM® v6-M Architecture Reference Manual”.
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6.2.9 Nested Vectored Interrupt Control (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the
stacked, or nested, interrupts to enable tail-chaining of interrupts. Users can only fully access the
NVIC from privileged mode, but this may cause interrupts to enter a pending state in user mode if
enabling the Configuration and Control Register. Any other user mode access causes a bus fault.
Users can access all NVIC registers using byte, halfword, and word accesses unless otherwise stated.
NVIC registers are located within the SCS (System Control Space). All NVIC registers and system
debug registers are little-endian regardless of the endianness state of the processor.
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-16 for each interrupts. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC, providing Power-down mode support.
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead. This provides low latency exception handling.
6.2.9.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NUC505 series. Software can set 16 levels
of priority on some of these exceptions as well as on all interrupts. The highest user-configurable
priority is denoted as “0x00” and the lowest priority is denoted as “0xF0” (The 4-LSB always 0). The
default priority of all the user-configurable interrupts is “0x00”. Note that priority “0” is treated as the
fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. On system reset, the vector table is fixed
at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start
address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
The vector table contains the initialization value for the stack pointer on reset, and the entry point
addresses for all exception handlers. The vector number on previous page defines the order of entries
in the vector table associated with exception handler entry as illustrated in previous section.
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Exception Type
Reset
Vector Number
Vector Address
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
Priority
1
-3
NMI
2
-2
Hard Fault
Memory Manager Fault
Bus Fault
3
-1
4
Configurable
Configurable
Configurable
Reserved
Configurable
Configurable
Reserved
Configurable
Configurable
5
Usage Fault
Reserved
6
7 ~ 10
11
12
13
14
15
SVCall
0x0000002C
0x00000030
Debug Monitor
Reserved
PendSV
0x00000038
0x0000003C
SysTick
0x00000000 +
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Configurable
(Vector Number)*4
Table 6.2-4 Exception Model
Vector
Number
Interrupt Number
Interrupt Name
Interrupt Description
(Bit in Interrupt
Registers)
0 ~ 15
16
-
-
System exceptions
Power On Interrupt
Watch Dog Timer interrupt
Reserved
0
PWR_INT
WDT_INT
Reserved
I2S_INT
17
1
18
2
19
3
I2S interrupt
20
4
EINT0_INT
EINT1_INT
EINT2_INT
EINT3_INT
SPIM_INT
USBD_INT
TM0_INT
TM1_INT
TM2_INT
External GPIO Group 0 interrupt
External GPIO Group 1 interrupt
External GPIO Group 2 interrupt
External GPIO Group 3 interrupt
SPIM interrupt
21
5
22
6
23
7
24
8
25
9
USB Device 20 interrupt
Timer0 interrupt
26
10
11
12
27
Timer1 interrupt
28
Timer2 interrupt
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29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TM3_INT
Timer3 interrupt
SDH interrupt
SDH_INT
PWM0_INT
PWM1_INT
PWM2_INT
PWM3_INT
RTC_INT
PWM0 interrupt
PWM1 interrupt
PWM2 interrupt
PWM3 interrupt
Real Time Clock interrupt
SPI0 interrupt
SPI0_INT
I2C1_INT
I2C0_INT
UART0_INT
UART1_INT
ADC_INT
wwdt_INT
USBH_INT
UART2_INT
LVD_INT
I2C1 interrupt
I2C0 interrupt
UART0 interrupt
UART1 interrupt
ADC interrupt
Window Watch Dog Timer interrupt
USB Host 1.1 interrupt
UART2 interrupt
Low Voltage Detection interrupt
SPI1 interrupt
SPI1_INT
Reserved
Reserved
Table 6.2-5 Interrupt Number Table
6.2.9.2 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-Enable or
Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-1-to-clear
policy, both registers reading back the current enabled state of the corresponding interrupts. When an
interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the
interrupt will not activate. If an interrupt is Active when it is disabled, it remains in its Active state until
cleared by reset or an exception return. Clearing the enable bit prevents new activations of the
associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to
enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading
back the current pended state of the corresponding interrupts. The Clear-Pending Register has no
effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts, and each interrupt uses MSB 4 bits of the 8-bit field).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip. The clocks include AHB, APB and
engine clocks for all of devices like USB device, USB host, UART and so on. There are two PLL
clocks, PLL and APLL, derived from external HXT clock input. The PLL clock allows the processor
to operate at a high internal clock frequency. Also, the APLL is used to generate more accuracy
frequency for audio CODEC. They also implement the power control function, include the
individually clock on or off control register, clock source selector and divider. These functions
minimize the extra power consumption and the chip runs on the just right condition. In Power-
down mode, the controller turns off the crystal oscillator to minimize the chip power consumption.
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6.3.2 Clock Diagram
CPUCLK
HCLK
CPU
SPIM
PLL_FOUT
1
0
12 MHz
1/(SYSCLK_N+1)
SRAM01
SRAM23
12 MHz
External
32.768
kHz
CLKDIV0[7]
12 MHz
1/(PCLKDIV_N+1)
PCLK
I2C0
I2C1
PLL_FOUT
Internal
32.768
kHz
Internal 32.768 kHz
1
0
12 MHz
RTC_32K
RTC
APLL_FOUT
External 32.768 kHz
RTC_CLKSRC[0]
PLL_FOUT
12MHz
PLL_FOUT
1
0
1/(USBHDIV+1)
USBH
1/(SDHDIV+1)
SDHC
CLKDIV1[30]
CPUCLK
PLL_FOUT
12MHz
1
1
0
SysTick
ADC
1/(USBDDIV+1)
USBD
12MHz
1/(STICKDIV+1)
SYST_CSR[2]
0
CLKDIV0[23]
PLL_FOUT
12MHz
PLL_FOUT
12MHz
1
1
0
1/(ADCDIV+1)
SPI0
SPI1
1/(SPI0_CLKDIV+1)
1/(SPI1_CLKDIV+1)
0
CLKDIV1[28]
CLKDIV2[28]
PLL_FOUT
12MHz
PLL_FOUT
12MHz
1
0
1
0
UART0
1/(UART0DIV+1)
CLKDIV3[4]
CLKDIV2[29]
PLL_FOUT
12MHz
APLL_FOUT
Reserved
PLL_FOUT
12MHz
1
0
11
10
1/(UART1DIV+1)
1/(UART2DIV+1)
1/(TMR3DIV+1)
UART1
UART2
TMR 3
1/(I2SDIV+1)
I2S
01
00
CLKDIV3[12]
PLL_FOUT
12MHz
1
0
CLKDIV2[25:24]
CLKDIV3[20]
RTC_32K
12MHz
1
0
RTC_32K
12MHz
1/(TMR0DIV+1)
1/(TMR1DIV+1)
1/(TMR2DIV+1)
TMR0
TMR1
TMR2
1
0
CLKDIV4[24]
CLKDIV5[24]
RTC_32K
12MHz
1
0
RTC_32K
12MHz
1
0
1/(WDGCLK_N+1)
1/(PWMDIV+1)
WDT
PWM
CLKDIV4[25]
CLKDIV5[25]
RTC_32K
12MHz
1
0
PLL_FOUT
12MHz
1
0
CLKDIV4[26]
CLKDIV5[26]
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.3 Clock Generator
The clock generator consists of 4 clock sources, which are listed below:
Real-time clock (RTC_CLK) source can be selected from external 32.768 kHz
external low speed crystal oscillator (LXT) or 32.768 kHz internal low speed RC
oscillator (LIRC)
12 MHz external high speed crystal oscillator (HXT)
Programmable System PLL output clock frequency (PLL_FOUT)
Programmable Audio PLL output clock frequency (APLL_FOUT)
Internal 32.768
kHz Oscillator
RTC_CLKSRC[0]
(LIRC)
LIRC
LXT
RTC_CLK
1
0
X32_IN
External 32.768
kHz Crystal
(LXT)
X32_OUT
XT1_IN
HXTEN (CLK_PWRCTL[0])
HXT
External 12
MHz Crystal
(HXT)
PLL_FOUT
XT1_OUT
PLL
APLL_FOUT
APLL
Figure 6.3-2 Clock Generator Block Diagram
The external crystal oscillator and two capacitors are connected to the pad “XT1_IN / X32_IN” and pad
“XT1_OUT / X32_OUT”. The capacitance value of the two capacitors may be changed for differential
crystal oscillator from different vender. The load capacitance values and resistance values must be
adjusted according to the selected oscillator. The recommended load capacitance values and
resistance values as
Crystal Oscillator
Capacitance Values
Resistance Values
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12 MHz
20pF
33pF
1 MΩ
32.768 kHz
10 MΩ
Table 6.3-1 Recommended Load Capacitance Values and Resistance Values.
BOARD
CHIP
C1
XT_IN /
X32_IN
CLOCK_OUT
External
Crystal
R
crystal
C2
XT_OUT /
X32_OUT
Figure 6.3-3 Crystal Oscillator Circuit
6.3.4 Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral clocks
are disabled. Some clock sources and peripherals clock are still active in Power-down mode.
The clocks which still keep active are listed below:
Clock Generator
32.768 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock
In Power-down mode, If the woke-up even occurred, the disabled clocks will be regenerated after
PDWKPSC (CLK_PWRCTL[23:8]) x 256 HXT cycle.
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6.4 General Purpose I/O (GPIO)
6.4.1 Overview
The NUC505 series has up to 52 General Purpose I/O pins to be shared with other function pins
depending on the chip configuration. The 52 pins are arranged in 4 ports named as PA, PB, PC,
and PD. PA and PB have 16 pins on port, PC has 15 pins on port, and PD has 5 pins on port.
Each of the 52 pins is independent and has the corresponding register bits to control the pin
mode function and data.
The I/O type of each I/O pins can be configured by software individually as Input or Push-pull
output mode. After the chip is reset, the I/O mode of all pins is input mode with no pull-up and
pull-down enable (except PB.2, it is pull-up enable). Each I/O pin has an individual pull-up and
pull-down resistor which is about 40 k ~ 50 k for VDD and Vss. User can set Px_PUEN to
control I/O pins to pull-up or pull-down.
PIN[n]
(Px_PIN)
PULLSEL[0]
(Px_PUEN)
DOUT[n]
(Px_DOUT)
PAD
MODE[n]
(Px_MODE)
PULLSEL[1]
(Px_PUEN)
Note: Px_ means PA_, PB_, PC_, or PD_
Figure 6.4-1 I/O Pin Block Diagram
6.4.2 Features
Two I/O modes:
Push-Pull Output mode
Input only with high impendence mode
CMOS/Schmitt trigger input selectable (refers SYS_GPAIBE register on TRM)
I/O pin can be configured as interrupt source with edge setting
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I/O pin has individual internal pull-up resistor and pull-down resistor
Enabling the pin interrupt function will also enable the wake-up function
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6.5 Timer Controller (TIMER)
6.5.1 Overview
The Timer Controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.5.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Time-out period = (Period of timer clock input) * (8-bit prescale counter+1) * CMPDAT
(TIMERx_CMP[23:0])
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TIMERx_CNT (Timer Data Register)
Supports event counting function to count the event from external pin
(TM0_CNT_OUT~TM3_CNT_OUT)
Supports external capture pin (TM0_EXT~TM3_EXT) for interval measurement
Supports external capture pin (TM0_EXT~TM3_EXT) to reset 24-bit up counter
Supports chip wake-up from Idle mode, Power-down mode and Deep Power-down mode, if
a timer interrupt signal is generated.
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6.6 PWM Generator and Capture Timer (PWM)
6.6.1 Overview
The NUC505 series has one PWM generator that can support four channels PWM output or four
channels input capture sharing the same pins (PWM_CH0/ PWM_CH1/PWM_CH2/PWM_CH3).
The PWM generator has a 16-bit PWM counter and comparator, and the PWM generator
supports two standard PWM output modes: Independent output mode and Complementary output
mode with 8-bit Dead-time generator. Each mode can be used as a timer and issues interrupt
independently. In addition, It also has an 8-bit prescaler and clock divider with 5 divided
frequencies (1, 1/2, 1/4, 1/8, 1/16) to support wide range clock frequency of PWM counter. For
PWM output control unit, it supports polarity output function.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened.
After the capture feature is enabled, the capture always latches PWM-counter to RCAPDATn
when input channel has a rising transition and latched PWM-counter to FCAPDATn when input
channel has a falling transition. Capture channel 0 interrupt is programmable by setting CRLIEN0
(PWM_CAPCTL01[1]) (Rising latch Interrupt enable) and CFLIEN0 (PWM_CAPCTL01[2]) (Falling
latch Interrupt enable) to determine the condition of interrupt occur. Capture channel 1 has the
same feature by setting CRLIEN1 (PWM_CAPCTL01[17]) and CFLIEN1 (PWM_CAPCTL01[18]).
The capture channel
2
&
3
has the same feature by setting CRLIEN2
(PWM_CAPCTL23[1]),CFLIEN2 (PWM_CAPCTL23[2]) and CRLIEN3 (PWM_CAPCTL23[17]),
CFLIEN3 (PWM_CAPCTL23[18]) respectively. Whenever Capture issues Interrupt 0/1/2/3, the
PWM counter 0/1/2/3 will be reload at this moment.
There are only four interrupts from PWM. PWM 0 and Capture 0 share the same interrupt; PWM 1
and Capture 1 share the same interrupt and so on. Therefore, PWM function and Capture
function in the same channel cannot be used at the same time.
6.6.2 Features
6.6.2.1 PWM function features
Supports 4 PWM output channels with 16-bit resolution
Supports 8-bit prescaler and clock divider
Supports 4 PWM interrupts
Supports One-shot or Auto-reload PWM counter operation mode
Supports 8-bit Dead-time
6.6.2.2 Capture function features
Supports 4 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports 4 Capture interrupts
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6.7 Watchdog Timer (WDT)
6.7.1 Overview
The Watchdog Timer is used to perform a system reset when system runs into an unknown state.
This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer
supports the function to wake up system from Power-down mode.
6.7.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period is
32.5 ms ~ 8.224 s if WDT_CLK = 32 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period, including 1026、130 、18 or 3
WDT_CLK reset delay period.
Supports Watchdog Timer time-out wake-up function when Watchdog Timer clock source is
selected as 32 kHz low-speed oscillator.
6.8 Window Watchdog Timer (WWDT)
6.8.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period
to prevent software run to uncontrollable status by any unpredictable condition.
6.8.2 Features
6-bit down counter CNTDAT (WWDT_CNT[5:0]) and 6-bit compare value CMPDAT
(WWDT_CTL[21:16]) to make the window period flexible
Selectable maximum 11-bit WWDT clock prescale PSCSEL (WWDT_CTL[11:8]) to make
WWDT time-out interval variable
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6.9 Real Time Clock (RTC)
6.9.1 Overview
The Real Time Clock (RTC) block can be operated by independent power supply while the
system power is off. The RTC uses a 32.768 kHz external crystal (LXT) or internal oscillator
(LIRC), and offers programmable time tick and alarm match interrupts. The data format of time
and calendar messages are expressed in BCD format. A digital frequency compensation feature
is available to compensate the frequency accuracy of external crystal oscillator (LXT) or internal
oscillator (LIRC).
The RTC controller also offers 32 bytes spare registers to store user’s important information.
The wake-up signal is used to wake the system from Idle mode, Power-down mode and Deep
Power-down mode.
6.9.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counter in RTC_WEEKDAY register
Frequency of RTC clock source compensate by RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle mode, Power-down mode and Deep Power-down mode
while a RTC interrupt signal is generated
Supports 32 bytes spare registers and these registers values are preserved when RTC
power domain is existed
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6.10 UART Interface Controller (UART)
6.10.1 Overview
The NUC505 series provides three channels of Universal Asynchronous Receiver/Transmitters
(UART). The UART Controller performs a serial-to-parallel conversion on data received from the
peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART
Controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR,
RS-485, auto-flow control function and auto-baud rate measuring function.
6.10.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16(UART0) / 64/64(UART1 and UART2) bytes entry
FIFO for data payloads
Supports hardware auto-flow control ( nCTS and nRTS) with UART1 and UART2
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS and data wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface features
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART1 /UART2 with LIN function)
Supports LIN Master/Slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
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6.11 I2C Serial Interface Controller (Master/Slave)
6.11.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the
following figure for more details about I2C Bus Timing.
Repeated
START
STOP START
STOP
SDA
SCL
Figure 6.11-1 I2C Bus Timing
The device on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit
I2CEN (I2C_CTL[6]) should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA
and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O
pins are used as I2C port, user must set the pins function to I2C in advance.
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6.11.2 Features
The NUC505 series provides two channels of I2C. The I2C bus uses two wires (SDA and SCL) to
transfer information between devices connected to the bus. The main features of the bus include:
Master/Slave mode and General Call Mode
Bidirectional data transfer between masters and slaves
Multi-master bus
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to stretch and
un-stretch serial transfer
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up
and time-out counter overflows.
Programmable divider allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
Supports address match wake-up function
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6.12 Serial Peripheral Interface (SPI)
6.12.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NUC505 series contains one set of SPI controller performing a serial-to-
parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion
on data transmitted to a peripheral device. Also, the SPI controller can be configured as a master
or a slave device.
6.12.2 Features
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wire, no slave select signal, bi-direction interface
Up to 2 sets of SPI controllers
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6.13 SPI Memory Interface Controller (SPIM)
6.13.1 Overview
The SPI Memory Interface Controller performs a serial-to-parallel conversion on data received
from the peripheral, and a parallel-to-serial conversion on data received from CPU. This controller
can drive up to 2 external peripherals (embedded SPI Flash or external SPI Flash) and act as a
SPI master. It can generate an interrupt signal when data transfer is finished and can be cleared
by writing 1 to the interrupt flag. The active level of device/slave select signal can be chosen to
low active or high active, which depends on the peripheral. Writing a divisor into the SPIM_CTL1
register can program the frequency of serial clock output to the peripheral. This controller contains
four 32-bit transmit/receive buffers, and can provide 1 to 4 burst mode operation. The number of
bits in each transaction can be 8, 16, 24, or 32; data can be transmitted/received up to four
successive transactions in one transfer.
6.13.2 Features
Supports SPI master mode
Supports DMA mode (DMA Write and DMA Read), Direct Memory Map (DMM) mode, and
I/O mode
8-, 16-, 24-, and 32-bit length of transaction
Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode
Provides burst mode operation, which can transmit/receive data up to four successive
transactions in one transfer
Two slave/device select lines (embedded SPI Flash or external SPI Flash)
Fully static synchronous design with one clock domain
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6.14 I2S Controller with Internal Audio CODEC (I2S)
6.14.1 Overview
The I2S controller consists of I2S protocol interface to internal audio CODEC and supports to use
external audio CODEC. The I2S controller includes two 16 words FIFO for transfer path and
receiver path respectively and is capable of handling 8, 16, 24, or 32 bits word sizes sample.
The structure of internal audio CODEC is a delta-sigma 24-bit CODEC with microphone input,
audio line-in input, and headphone output.
6.14.2 Features
I2S Controller
Supports Master mode and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes sample
Supports Mono and Stereo audio data
Supports I2S and most significant bit (MSB) justified data format
Supports PCM-A and PCM-B data format
Provides two 16 words FIFO, one for transmitting and the other for receiving
Generates interrupt requests when FIFO levels cross a programmable boundary
Supports TX DMA function for transmitting and RX DMA function receiving
Supports RX Data Power Measurement
Supports connecting to external audio CODEC
Internal CODEC
Supports mono microphone input and stereo audio line-in input
Supports stereo headphone output
Supports stereo and mono mode
Features of ADC
─
─
Total-Harmonic-Distortion with Noise (THD+N): -80 dB
Dynamic-Range (DR) and Signal-to-Noise ratio (SNR): 90 dB (A-Weighted)
Features of DAC (headphone out with 32Ω loading)
─
─
Total-Harmonic-Distortion with Noise (THD+N): -60 dB
Dynamic-Range (DR) and Signal-to-Noise ratio (SNR): 93 dB (A-Weighted)
Supports sampling rate with 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32
kHz, 44.1 kHz, 48 kHz, and 96 kHz
July. 26, 2018
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6.15 USB 2.0 Device Controller (USBD)
6.15.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller
contains both the AHB master interface and AHB slave interface. CPU programs the USB
controller registers through the AHB slave interface. For IN or OUT transfer, the USB device
controller needs to write data to memory or read data from memory through the AHB master
interface. The USB device controller is complaint with USB 2.0 specification and it contains 12
configurable endpoints in addition to control endpoint. These endpoints could be configured to
BULK, INTERRUPT or ISO. The USB device controller has a built-in DMA to relieve the load of
CPU.
6.15.2 Features
USB Specification reversion 2.0 compliant
Supports 12 configurable endpoints in addition to Control Endpoint
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction
Three different operation modes of an in-endpoint － Auto Validation mode, Manual
Validation mode, Fly mode
Supports DMA operation
2048 Bytes Configurable RAM used as endpoint buffer
Supports Endpoint Maximum Packet Size up to 1024 bytes
July. 26, 2018
Page 100 of 130
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6.16 USB 1.1 Host Controller (USBH)
6.16.1 Overview
The NUC505 series is equipped with one USB 1.1 Host Controller (USBH) that supports Open
Host Controller Interface (OpenHCI, OHCI) Specification and register-level description of a host
controller to manage the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port overcurrent detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing
data transfer, collecting status and activity of USB bus, providing power control and detecting
overcurrent of attached USB devices.
6.16.2 Features
Supports Universal Serial Bus (USB) Specification Revision 1.1.
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports an integrated Root Hub.
Supports one USB host port in LQFP48 or LQFP64 and two USB host ports in QFN88
Supports port power control and port overcurrent detection.
Supports DMA for real-time data transfer.
July. 26, 2018
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6.17 Secure-Digital Host Controller (SDHC)
6.17.1 Overview
The Secure-Digital Host Controller (SDH Controller) includes a DMAC (Direct Memory Access
Controller) unit and a SD unit. The DMAC unit provides a DMA (Direct Memory Access) function
for SD to exchange data between system memory and shared buffer (128 bytes), and the SD unit
controls the interface of SD/SDHC/MMC. The SD HOST controller can support SD/SDHC/MMC
with DMAC to provide a fast data transfer between system memory and cards.
6.17.2 Features
Supports single DMA channel.
Supports hardware Scatter-Gather function.
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC/MMC card.
The frequency of HCLK should be higher than the frequency of peripheral clock.
July. 26, 2018
Page 102 of 130
Rev.1.08
NUC505
6.18 12-bit Analog-to-Digital Converter (ADC)
6.18.1 Overview
The NUC505 series contains one 12-bit successive approximation analog-to-digital converter
(ADC) with 8 single-end external input channels (ADC_CH0, ADC_CH1, … ADC_CH7). The
ADC_CH0 has an internal 10 kΩ resistor divider for battery detection. The ADC_CH2 also
supports key pad comparator function. User can control the A/D conversion by setting the
SWTRG (ADC_CTL[0]).
6.18.2 Features
Analog input voltage range: 0~AVDDADC
.
12-bit resolution and 10-bit accuracy guaranteed.
Up to 8 single-end analog input channels.
ADC clock frequency up to 16 MHz.
Up to 1 MSPS conversion rate when using in ADC_CH1 channel.
Up to 200 kSPS conversion rate when using in ADC_CH2, …ADC_CH7 channels.
Configurable ADC internal sampling time.
Supports key pad comparator (ADC_CH2).
Built-in 10 kΩ resistor divider for battery detection (ADC_CH0).
July. 26, 2018
Page 103 of 130
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
-0.3
Max
+4.0
Unit
V
DC Power Supply
Input Voltage
VSS - 0.3
VDD + 0.3
12
V
1/tCLCL
TA
Oscillator Frequency
MHz
Operating Temperature
-40
-55
-
+85
℃
TST
Storage Temperature
+150
IDD
Maximum Current into VDD
160
mA
mA
mA
mA
mA
mA
ISS
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
160
I/O pin[*2, 3, 4]
I/O pin[*2, 3, 4]
100
IIO
100
Note:
1.
2.
3.
4.
Exposure to conditions beyond those listed under absolute maximum ratings may adversely
affect the lift and reliability of the device.
4mA: PA.14, PA.15, PB.0, PB.1, PB.2, PB.3, PB.4, PB.5, PB.6, PB.7, PB.8, PB.9, PB.10,
PB.11, PC.8, PC.9, PC.10, PC.11, PC.12, PD.0, PD.1
8mA: PA.8, PA.9, PA.10, PA.11, PA.12, PA.13, PB.12, PB.13, PB.14, PB.15, PC.0, PC.1,
PC.2, PC.3, PC.4, PC.5, PC.6, PC.7, PC.13, PC.14
Can setting strength for 2mA, 6.5mA, 8.7mA, 13mA, 15.2mA, 19.5mA, 21.7mA, 26.1mA:
PA.0, PA.1, PA.2, PA.3, PA.4, PA.5, PA.6, PA.7, PD.2, PD.3, PD.4
July. 26, 2018
Page 104 of 130
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7.2 DC Characteristics
(VDD - VSS = 3 ~ 3.6 V, TA = 25C)
SPECIFICATION
SYMBOL
PARAMETER
Operation Voltage
Power Ground
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
3
3.3
3.6
V
VSS
-0.3
1.08
2
-
1.2
-
-
1.32
3.6
-
V
V
AVSS
Core Logic and I/O
Buffer Pre-Driver
Voltage
VDD12
VBAT
IBAT_EX
IBAT_IN
FINT_RC
VOH
RTC Power
Supply
V
External crystal
RTC Supply
Current
-
4
uA
uA
Khz
V
Internal RC RTC
Supply Current
0.1
15
2.4
-
0.6
32
-
0.9
90
-
Internal RC
frequency
High Level Output
Voltage
Low Level Output
Voltage
VOL
-
0.4
-
V
VIH
Input High Voltage
Input Low Voltage
Switch Threshold
2.0
-
-
V
VIL
-
0.8
V
Schmitt-falling-trigger
Schmitt-rising-trigger
0.87
1.65
1.05
1.9
1.2
2.1
V
V
VTH
Input Pull-up
Resist
32
53
120
kΩ VIN = Vss
RPU
July. 26, 2018
Page 105 of 130
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SPECIFICATION
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input Pull-down
Resistance
37
49
120
kΩ VIN = VDD
RPD
Input Leakage
Current
-10
-10
-
-
10
10
uA
uA
IL
Tri-State Output
Leakage Current
IOZ
4
8
-
-
-
-
mA
mA
IOL1
IOL2
2、6.5、
8.7、
13、
Low level sink
current [*1]
VOL = 0.4V
15.2、
19.5、
21.7、
26.1
-
-
mA
IOL3
4
8
-
-
-
-
mA
mA
IOH1
IOH2
2、6.5、
8.7、
13、
High level source
current [*2]
VOH = 2.4V
15.2、
19.5、
21.7、
26.1
-
-
mA
IOH3
All
PLL
HXT
digital Code
module
LXT
96Mhz
12Mhz
-
18.83
-
IDD1
SPI
SPI
✔
✕
✕
✔
✔
✕
✔
-
-
-
-
-
27.33
25.38
32.13
4.53
-
-
-
✔
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
VDD= 3.3V,
Operating current
Normal Run Mode
while(1){}
executed from SPI
flash or RAM
✔
✔
✔
✔
✔
✔
✕
✕
✕
✕
✕
✕
✔
✔
✕
✕
✕
✕
✕
✔
✕
✔
✕
✔
RAM
RAM
SPI
mA
6.47
SPI
5.23
RAM
RAM
5.94
July. 26, 2018
Page 106 of 130
Rev.1.08
NUC505
SPECIFICATION
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital
module
HXT RTC
PLL
VDD= 3.3V,
-
3.87
-
IIDLE1
Operating Current
Idle Mode at 12
MHz
mA
✔
✔
✕
✕
✕
✕
✔
-
3.74
-
-
-
IIDLE2
✕
VDD =3.3V,
Standby current
Power-down
HXT RTC
PLL RAM retention
700
uA
IPWD
(Deep Sleep)mode
✕
✕
✕
✔
Note:
1.
2.
3.
4mA: PA.14, PA.15, PB.0, PB.1, PB.2, PB.3, PB.4, PB.5, PB.6, PB.7, PB.8, PB.9, PB.10, PB.11,
PC.8, PC.9, PC.10, PC.11, PC.12, PD.0, PD.1
8mA: PA.8, PA.9, PA.10, PA.11, PA.12, PA.13, PB.12, PB.13, PB.14, PB.15, PC.0, PC.1, PC.2, PC.3,
PC.4, PC.5, PC.6, PC.7, PC.13, PC.14
Can setting strength for 2mA, 6.5mA, 8.7mA, 13mA, 15.2mA, 19.5mA, 21.7mA, 26.1mA: PA.0, PA.1,
PA.2, PA.3, PA.4, PA.5, PA.6, PA.7, PD.2, PD.3, PD.4
July. 26, 2018
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NUC505
7.3 AC Electrical Characteristics
7.3.1 External 12 MHz Crystal
t
CLCL
t
t
CLCH
CLCX
t
t
CHCL
CHCX
Note: Duty cycle is 50%.
CONDITIO
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
N
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
tCHCX
tCLCX
tCLCH
tCHCL
-
-
-
-
41.6
-
nS
nS
nS
nS
41.6
-
-
-
25
25
7.3.2 External 12 MHz High Speed Oscillator
SYMBOL
PARAMETER
CONDITION
MIN.
TYP. MAX.
UNIT
fHXT
Input clock frequency
External crystal for XIN
12
MHz
TA
℃
V
Temperature
VDD
-
-40
-
-
3.3
3
85
-
VHXT
IHXT
-
Operating current
12 MHz@ VDD = 3.3V
mA
7.3.3 Typical Crystal Application Circuits
Crystal Oscillator
12 MHz
Capacitance Values
20pF
33pF
Resistance Values
1 MΩ
32.768 kHz
10 MΩ
July. 26, 2018
Page 108 of 130
Rev.1.08
NUC505
20p
XT1_IN
1M
20p
33p
XT1_OUT
XT32_IN
12 MHz
crystal
10M
33p
XT32_OUT
32.768 Khz
crystal
Figure 7.3-1 Typical Crystal Application Circuit
7.3.4 Internal 32 kHz Low Speed Oscillator
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Supply voltage
Center Frequency
Operating current
-
3
-
-
3.6
V
-
32
0.5
-
-
kHz
uA
VDD =3.3V
-
July. 26, 2018
Page 109 of 130
Rev.1.08
NUC505
7.4 Analog Characteristics
7.4.1 Specifications of 12-bit SARADC
SPECIFICATIONS
Symbol
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AVDD_ADC Operating Voltage
2.7
3.3
3.6
V
RADC
VREF
VIN
Resolution
-
-
-
-
12
bit
V
AVDD_ADC
VREF
Reference Voltage
ADC input Voltage
Analog input impedance
2
0
2
V
RIN
MΩ
ADC Clock = 16MHz
-
-
-
1M
Hz
Hz
Free Running
Conversion(ADC_CH1)
ADC Clock = 3.2MHz
FSPS
Sampling Rate
Free Running
Conversion(ADC_CH2,
ADC_CH3, ADC_CH4,
ADC_CH5, ADC_CH6,
ADC_CH7)
-
200k
EQ
EA
Gain Error (Transfer Gain )
Absolute Error
-
-
-2
3
-4
LSB
LSB
LSB
LSB
LSB
dB
-
±3
-
INL
DNL
EO
Integral Non-linearity Error
Differential Non-linearity Error
Offset Error
-
-
+1.5
±3
-
-1
±1
62
62
SNR
-
S/N
-
-
Total Harmonic Distortion
-
dB
Note:
1.
2.
The performance measurement is in ADC only condition (all other module are in reset statue).
Design by guarantee, no test in production.
July. 26, 2018
Page 110 of 130
Rev.1.08
NUC505
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain
error from the actual transfer curve.
July. 26, 2018
Page 111 of 130
Rev.1.08
NUC505
7.4.2 Specifications of 24-bit Delta-Sigma CODEC
Specifications
Symbol Parameter
Test Conditions
Min.
Typ
Max.
Unit
Reference
0.5*AVDD_CO
DEC
VMID
-
-
V
Microphone Bias
0.75*AVDD_C
ODEC
Bias Voltage
-
-
V
Maximum Output
Current
-
-
-
-
3
mA
pF
Capacitive Load
50
Line Input
THD
Resolution
-
-
24
-
Bit
dB
Total Harmonic
Distortion
-80
-70
-60dB input,
DR
Dynamic Range
80
90
-
dB
A-Weighted
SNR
S/N
80
-
90
100
0.2
-
-
-
dB
dB
dB
Channel Separation
Channel Matching
-
VFS
Full Scale Output
Voltage
0.93*AVDD_C
ODEC/3.3
-
-
Vrms
Input Impedance
Input Capacitor
10
-
-
-
-
kΩ
10
pF
Headphone Output
RL = 0 Ω,
Total Harmonic
Distortion
THD
-
-80
-
dB
Po = 10mW
RL = 32 Ω,
Total Harmonic
Distortion
THD
SNR
-
-60
93
-
-
dB
dB
Po = 10mW
S/N
90
A-Weighted
Power Supply Current (No PLL, No Loading)
AVDD_CODEC
AVDD_HP
-
-
8
4
-
-
mA
mA
July. 26, 2018
Page 112 of 130
Rev.1.08
NUC505
Note: The performance measurement is in CODEC only condition (All other module are in reset statue).
7.4.3 Specification of LDO
Symbol
Parameter
Input Voltage
Min.
Typ
Max.
Unit
Note
VDD
VLDO
TA
1.62
-10%
-40
-
3.3
1.2
25
3.6
+10%
85
V
V
AVDD_LDO input voltage
Output Voltage
Temperature
μF
ECAP
External Capacitor
4.7
-
Notes:
1.
It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin
of the device.
2.
For ensuring power stability, a 4.7μF or higher capacitor must be connected between LDO_CAP
pin and the closest VSS pin of the device.
July. 26, 2018
Page 113 of 130
Rev.1.08
NUC505
7.4.4 Specification of Low Voltage Reset
Test Condition
Symbol
VDD
Parameter
Supply Voltage
Temperature
Min.
0
Typ
-
Max.
3.6
85
Unit
V
TA
-40
-
25
25
Quiescent
Current
ILVR
40
uA
V
VDD=3.3V
Threshold
Voltage
TA=-45 ~ 85
VLVR
2.16
2.4
2.64
7.4.5 Specifications of Power-on Reset
Symbol
TA
Parameter
Min.
-40
-
Typ
25
33
2
Max.
85
Unit
Test Condition
Temperature
Quiescent
Current
IPOR
50
uA
V
VDD>Reset voltage
TA=-40 ~ 85
VPOR
Reset Voltage
1.6
2.4
VDD Start
Voltage to
Ensure Power-
on Reset
VPOR
-
-
-
100
mV
VDD Raising
Rate to Ensure
Power-on
Reset
RPVDD
0.025
-
V/ms
Minimum Time
for VDD Stays
at VPOR to
tPOR
0.5
-
-
ms
Ensure Power-
on Reset
July. 26, 2018
Page 114 of 130
Rev.1.08
NUC505
VDD
tPOR
RRVDD
VPOR
Time
Figure 7.4-1 Power-up Ramp Condition
July. 26, 2018
Page 115 of 130
Rev.1.08
NUC505
7.4.6 USB PHY Specifications
7.4.6.1 USB DC Electrical Characteristics
Symbol
Parameter
Conditions
Min.
2.0
-
Typ
Max.
Unit
V
Input high (driven)
-
-
-
-
0.8
-
VIH
VIL
Input low
V
Differential input sensitivity
USB_DP-USB_DM
Includes VDI range
0.2
V
VDI
Differential
0.8
0.8
-
-
2.5
2.0
V
V
VCM
common-mode range
Single-ended receiver threshold
Receiver hysteresis
Output low (driven)
-
VSE
400
-
mV
V
0
-
-
-
-
-
-
-
-
0.3
VOL
VOH
VCRS
RPU
VTRM
ZDRV
CIN
Output high (driven)
Output signal cross voltage
Pull-up resistor
2.8
1.3
1.425
14.25
3.0
28
3.6
V
2.0
V
1.575
15.75
3.6
kΩ
kΩ
V
Pull-down resistor
Termination Voltage for upstream
port pull up (RPU)
Driver output resistance
Transceiver capacitance
Steady state drive*
Pin to VSS
49.5
20
Ω
-
pF
VIH
Note: Driver output resistance does not include series resistor resistance.
July. 26, 2018
Page 116 of 130
Rev.1.08
NUC505
7.4.6.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Conditions
CL = 50p
CL = 50p
Min.
4
Typ
Max.
20
Unit
ns
Rising time
Falling time
-
-
-
TFR
TFF
4
20
ns
Rising and falling time matching TFRFF = TFR / TFF
90
111.11
%
TFRFF
7.4.6.3 USB High-Speed Driver Electrical Characteristics
Symbol
Parameter
Conditions
Min.
500
500
90
Typ
Max.
Unit
ns
Rising time
Falling time
CL = 5p
CL = 5p
TFR
TFF
ns
Rising and falling time matching TFRFF = TFR / TFF
111
%
TFRFF
July. 26, 2018
Page 117 of 130
Rev.1.08
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7.4.7 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
4
Max.
Min.
1.2
Max.
-
-
-
-
-
-
uS
uS
uS
tLOW
tHIGH
SCL low period
0.6
SCL high period
Repeated START condition
setup time
4.7
1.2
tSU; STA
4
-
0.6
-
-
uS
uS
uS
nS
uS
nS
nS
pF
tHD; STA
tSU; STO
tBUF
START condition hold time
STOP condition setup time
Bus free time
4
-
-
0.6
4.7[3]
1.2[3]
-
250
-
100
-
tSU;DAT
tHD;DAT
tr
Data setup time
0[4]
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
Data hold time
-
-
-
20+0.1Cb
SCL/SDA rise time
SCL/SDA fall time
-
-
tf
Capacitive load for each bus
line
Cb
Notes:
1.
2.
Guaranteed by design, not tested in production.
HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 8 MHz to achieve the maximum fast mode I2C frequency.
3.
4.
I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL.
5.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the
low period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 7.4-2 I2C Timing Diagram
July. 26, 2018
Page 118 of 130
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NUC505
7.4.8 SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
tDS
tDH
tV
Data hold time
Data output valid time
2
4
SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
tDS
tDH
tV
Data hold time
Data output valid time
18
24
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 7.4-3 SPI Master Mode Timing Diagram
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CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 7.4-4 SPI Slave Mode Timing Diagram
July. 26, 2018
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7.4.9 I2S Dynamic Characteristics
Min.
Max.
Unit
Symbol
th(WS)
Parameter
I2S clock high time
I2S clock low time
LRCLK valid time
Test Conditions
42
37
7
-
-
Master fPCLK = 12.288 MHz, data: 24
bits, audio frequency = 48 kHz
tsu(WS)
th(WS)
-
Master mode
ns
DuCy(SCK) LRCLK hold time
tsu(SD_MR) LRCLK setup time
tsu(SD_SR) LRCLK hold time
1
-
Master mode
34
0
-
Slave mode
-
Slave mode
I2S slave input clock
duty cycle
th(SD_MR)
25
0
75
-
%
Slave mode
th(SD_SR)
Master receiver
Data input setup time
tv(SD_ST)
0
-
Slave receiver
th(SD_ST)
0
-
Master receiver
Data input hold time
tv(SD_MT)
0
-
Slave receiver
ns
th(SD_MT)
Data output valid time
Data output hold time
Data output valid time
Data output hold time
-
32
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
th(WS)
16
-
tsu(WS)
5
-
th(WS)
0
July. 26, 2018
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NUC505
tw(CKH)
BCLK output
tw(CKL)
th(LRCLK)
tv(LRCLK)
LRCLK output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.4-5 I2S Master Mode Timing Diagram
BCLK input
tw(CKH)
tw(CKL)
th(LRCLK)
LRCLK input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(LRCLK)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 7.4-6 I2S Slave Mode Timing Diagram
July. 26, 2018
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NUC505
8
APPLICATION CIRCUIT
USB_D-
USB_D+
USB_VBUS
AVCC
AVDDADC
AVDDCODE
AVDDHP
VBAT
USB Device
DVCC
FB
FB
USB_VDD33_CAP
VDD
1uF
AVDDUSB
DVCC
Power
0.1uF
0.1uF
VSS
VDD
SPI1_SS
SPI1_CLK
SPI1_MISO
SPI1_MOSI
CS
CLK
MISO
MOSI
SPI Device
AVSSADC
LDO_AVSS
AVSSHP
VSS
DVCC
4.7K
DVCC
VDD
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
4.7K
NUC505
Series
20p
I2C1_SCL
I2C1_SDA
CLK
VDD
VSS
I2C Device
XT1_IN
DATA
1M
20p
33p
5VCC
XT1_OUT
X32_IN
12 MHz
crystal
Crystal
Curret
Protect
IC
GPIO
10M
33p
USBH_D-
USBH_D+
X32_OUT
USB HOST
32.768kHz
crystal
DVCC
AUDIO_R_IN
AUDIO_L_IN
Line In
Reset
Circuit
RHP_OUT
LHP_OUT
10K
Speaker
nRESET
10uF/10V
PC COM Port
RS 232 Transceiver
ROUT RIN
RXD
TXD
UART
LDO_CAP
TIN
TOUT
4.7 uF
LDO
July. 26, 2018
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9
PACKAGE DIMENSIONS
9.1 LQFP 48L (7x7x1.4mm footprint 2.0mm)
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9.2 QFN 48 (7x7x0.8mm)
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9.3 LQFP 64L (7x7x1.4mm footprint 2.0mm)
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9.4 QFN 88 (10x10x0.9mm)
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July. 26, 2018
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10 REVISION HISTORY
Date
Revision
Description
2014.04.23
1.01
Preliminary version
1. Added new part number: NUC505DLA, NUC505YLA, and NUC505DSA in
Chapter 4.
2015.05.28
2015.11.04
1.02
1.04
2. Updated embedded SPI Flash memory size to 512 KB for new part number.
1. Added a note to indicate that NUC505DS13Y only supports Headphone Out in
section 4.1.1.
2. Added a note to indicate the packages are not pin-to-pin compatible in section
4.1.1.
3. Added section 9.2 QFN 48 (7x7x0.8mm) package specification.
4. Added part number NUC505YLA2Y in section 4.1.1, 4.2.4, and 4.3.4.
5. Replaced power mode name of Sleep mode and Deep-sleep mode with Idle
mode and Power-down mode respectively.
2016.05.09
2016.12.02
1.05
1.06
1. Added a note to Pin Diagram and Pin Description for QFN 48/88-pin packages.
1. Corrected the typo in the Pin Configuration section 4.2.4/4.2.5/4.2.6 and Pin
Description section 4.3.5.
2. Modified section 4.1.1 NUC505DLA and NUC505YLA SPI should be two.
3. Modified pin name from VBUS to VBUS33.
1. Modified VBUS33 pin description.
2. Modified USB transceiver power description in section 6.2.4.
3. Modified USB Host clock source only from PLL in section 6.3.2.
4. Modified VCMBF pin description in section 4.3.7.
5. Fixed VFS unit typo in section 7.4.2.
2017.08.15
2018.07.26
1.07
1.08
1. Revised the SWD interface in chapter 8.
2. Fixed idle mode operating current in section 7.2.
July. 26, 2018
Page 129 of 130
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NUC505
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
July. 26, 2018
Page 130 of 130
Rev.1.08
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