NUC52-VB1E [NUVOTON]
ARM® Cortex®-M 32-bit Microcontroller;
| 型号： | NUC52-VB1E |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortex®-M 32-bit Microcontroller 微控制器 |
| 文件： | 总107页 (文件大小：1886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC100/120xxxDN
ARM® Cortex® -M
32-bit Microcontroller
NuMicro® NUC100 Series
NUC100/120xxxDN
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Mar. 21, 2019
Page 1 of 107
Rev 1.03
NUC100/120xxxDN
Table of Contents
1
2
GENERAL DESCRIPTION .............................................................. 8
FEATURES ................................................................................ 9
2.1
2.2
NuMicro® NUC100 Features – Advanced Line........................................... 9
NuMicro® NUC120 Features – USB Line ................................................13
ABBREVIATIONS....................................................................... 17
PARTS INFORMATION LIST AND PIN CONFIGURATION ..................... 19
NuMicro® NUC100/120xxxDN Selection Guide.........................................19
3
4
4.1
4.1.1
4.1.2
NuMicro® NUC100 Advanced Line Selection Guide ..........................................19
NuMicro® NUC120 USB Line Selection Guide.................................................19
Pin Configuration.............................................................................21
NuMicro® NUC100 Pin Diagram..................................................................21
NuMicro® NUC120 Pin Diagram..................................................................24
Pin Description ...............................................................................27
NuMicro® NUC100 Pin Description ..............................................................27
NuMicro® NUC120 Pin Description ..............................................................34
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
5
6
BLOCK DIAGRAM ...................................................................... 41
NuMicro® NUC100 Block Diagram........................................................41
NuMicro® NUC120 Block Diagram........................................................42
FUNCTIONAL DESCRIPTION........................................................ 43
ARM® Cortex® -M0 Core.....................................................................43
System Manager.............................................................................45
5.1
5.2
6.1
6.2
6.2.1
6.2.2
Overview .............................................................................................45
System Reset........................................................................................45
Power Modes and Wake-up Sources............................................................51
System Power Distribution ........................................................................53
System Memory Map...............................................................................56
System Timer (SysTick) ...........................................................................58
Nested Vectored Interrupt Controller (NVIC) ...................................................59
Clock Controller ..............................................................................60
Overview .............................................................................................60
Clock Generator.....................................................................................62
System Clock and SysTick Clock ................................................................63
Peripherals Clock ...................................................................................64
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.3
6.3.1
6.3.2
6.3.3
6.3.4
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6.3.5
6.3.6
Power-down Mode Clock ..........................................................................64
Frequency Divider Output .........................................................................64
FLASH MEMORY CONTROLLER (FMC) ...............................................66
Overview .............................................................................................66
Features..............................................................................................66
External Bus Interface (EBI) ...............................................................67
Overview .............................................................................................67
Features..............................................................................................67
General Purpose I/O (GPIO)...............................................................68
Overview .............................................................................................68
Features..............................................................................................68
PDMA Controller (PDMA) ..................................................................69
Overview .............................................................................................69
Features..............................................................................................69
Timer Controller (TMR) .....................................................................70
Overview .............................................................................................70
Features..............................................................................................70
PWM Generator and Capture Timer (PWM) ............................................71
Overview .............................................................................................71
Features..............................................................................................72
Watchdog Timer (WDT).....................................................................73
Overview ..........................................................................................73
Features ...........................................................................................73
Window Watchdog Timer (WWDT) .......................................................74
Overview ..........................................................................................74
Features ...........................................................................................74
Real Time Clock (RTC) .....................................................................75
Overview ..........................................................................................75
Features ...........................................................................................75
UART Interface Controller (UART)........................................................76
Overview ..........................................................................................76
Features ...........................................................................................78
Smart Card Host Interface (SC) ...........................................................80
Overview ..........................................................................................80
Features ...........................................................................................80
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.9
6.9.1
6.9.2
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.13
6.13.1
6.13.2
6.14
6.14.1
6.14.2
6.15
6.15.1
6.15.2
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6.16
PS/2 Device Controller (PS2D)............................................................81
6.16.1
6.16.2
Overview ..........................................................................................81
Features ...........................................................................................81
I2C Serial Interface Controller (I2C) .......................................................82
Overview ..........................................................................................82
Features ...........................................................................................83
Serial Peripheral Interface (SPI)...........................................................84
Overview ..........................................................................................84
Features ...........................................................................................84
I2S Controller (I2S) ...........................................................................85
Overview ..........................................................................................85
Features ...........................................................................................85
USB Device Controller (USB)..............................................................86
Overview ..........................................................................................86
Features ...........................................................................................86
Analog-to-Digital Converter (ADC)........................................................87
Overview ..........................................................................................87
Features ...........................................................................................87
Analog Comparator (ACMP) ...............................................................88
Overview ..........................................................................................88
Features ...........................................................................................88
6.17
6.17.1
6.17.2
6.18
6.18.1
6.18.2
6.19
6.19.1
6.19.2
6.20
6.20.1
6.20.2
6.21
6.21.1
6.21.2
6.22
6.22.1
6.22.2
7
8
APPLICATION CIRCUIT............................................................... 89
ELECTRICAL CHARACTERISTICS ................................................. 90
Absolute Maximum Ratings ................................................................90
DC Electrical Characteristics...............................................................91
AC Electrical Characteristics...............................................................95
8.1
8.2
8.3
8.3.1
8.3.2
External 4~24 MHz High Speed Oscillator .....................................................95
External 4~24 MHz High Speed Crystal ........................................................95
External 32.768 kHz Low Speed Crystal Oscillator ...........................................96
Internal 22.1184 MHz High Speed Oscillator...................................................96
Internal 10 kHz Low Speed Oscillator ...........................................................96
Analog Characteristics ......................................................................97
12-bit SARADC Specification .....................................................................97
LDO and Power Management Specification....................................................97
Low Voltage Reset Specification .................................................................98
8.3.3
8.3.4
8.3.5
8.4
8.4.1
8.4.2
8.4.3
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8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
Brown-out Detector Specification ................................................................98
Power-on Reset Specification ....................................................................98
Temperature Sensor Specification...............................................................99
Comparator Specification..........................................................................99
USB PHY Specification ..........................................................................100
Flash DC Electrical Characteristics .....................................................102
8.5
9
PACKAGE DIMENSIONS ............................................................103
100-pin LQFP (14x14x1.4 mm footprint 2.0 mm).....................................103
64-pin LQFP (10x10x1.4 mm footprint 2.0 mm) ......................................104
48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) .........................................105
9.1
9.2
9.3
10 REVISION HISTORY..................................................................106
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List of Figures
Figure 4-1 NuMicro® NUC100 Series Selection Code ................................................................... 20
Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram ...................................................... 21
Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram ........................................................ 22
Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram......................................................... 23
Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram ...................................................... 24
Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram ........................................................ 25
Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram......................................................... 26
Figure 5-1 NuMicro® NUC100 Block Diagram ............................................................................... 41
Figure 5-2 NuMicro® NUC120 Block Diagram ............................................................................... 42
Figure 6-1 Functional Controller Diagram...................................................................................... 43
Figure 6-2 System Reset Resources ............................................................................................. 46
Figure 6-3 nRESET Reset Waveform............................................................................................ 48
Figure 6-4 Power-on Reset (POR) Waveform ............................................................................... 48
Figure 6-5 Low Voltage Reset (LVR) Waveform............................................................................ 49
Figure 6-6 Brown-Out Detector (BOD) Waveform ......................................................................... 50
Figure 6-7 Power Mode State Machine ......................................................................................... 51
Figure 6-8 NuMicro® NUC100 Power Distribution Diagram........................................................... 54
Figure 6-9 NuMicro® NUC120 Power Distribution Diagram........................................................... 55
Figure 6-10 Clock Generator Global View Diagram....................................................................... 61
Figure 6-11 Clock Generator Block Diagram ................................................................................. 62
Figure 6-12 System Clock Block Diagram ..................................................................................... 63
Figure 6-13 SysTick Clock Control Block Diagram........................................................................ 63
Figure 6-14 Clock Source of Frequency Divider............................................................................ 64
Figure 6-15 Frequency Divider Block Diagram .............................................................................. 65
Figure 6-16 UART nRTS Auto-Flow Control Trigger Level............................................................ 77
Figure 6-17 I2C Bus Timing............................................................................................................ 82
Figure 8-1 Typical Crystal Application Circuit ................................................................................ 96
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List of Tables
Table 1-1 NuMicro® NUC100 Series Connectivity Support Table ................................................... 8
Table 3-1 List of Abbreviations....................................................................................................... 18
Table 6-1 Reset Value of Registers ............................................................................................... 47
Table 6-2 Power Mode Difference Table ....................................................................................... 51
Table 6-3 Clocks in Power Modes ................................................................................................. 52
Table 6-4 Condition of Entering Power-down Mode Again............................................................ 53
Table 6-5 Address Space Assignments for On-Chip Controllers................................................... 57
Table 6-6 UART Baud Rate Equation............................................................................................ 76
Table 6-7 UART Baud Rate Setting Table..................................................................................... 77
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1 GENERAL DESCRIPTION
The NuMicro® NUC100 series 32-bit microcontroller (MCU) is embedded with the ARM® Cortex® -
M0 core with the cost equivalent to traditional 8-bit MCU. The NUC100 series can be used in
consumer electronics, industrial control and applications which requiring rich communication
interfaces such as industrial automation, alarm system, energy system and power system.
The NuMicro® NUC100 Advanced Line and NUC120 USB Line are embedded with the Cortex® -
M0 core running up to 50 MHz and features 32/64/128 Kbytes Flash, 4/8/16 Kbytes embedded
SRAM and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V ~ 5.5V
and temperature range of -40℃ ~ +85℃. The NUC100 series is also provided with plenty of
peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with
CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, PS/2, EBI, Smart Card Host, 12-bit
ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out Detector. Additionally,
the NUC120 USB Line is equipped with a USB 2.0 Full-speed Device. These peripherals have
been incorporated into the NUC100 series to reduce component count, board space and system
cost.
The NUC100 series is equipped with ISP (In-System Programming), IAP (In-Application-
Programming) and ICP (In-Circuit Programming) functions, which allows the user to update the
program under software control through the on-chip connectivity interface, such as SWD, UART
and USB.
Product Line
NUC100xxxDN
NUC120xxxDN
UART
SPI
4
I2C
2
USB
PS/2
I2S
1
SC
3
3
-
1
3
4
2
1
1
1
3
Table 1-1 NuMicro® NUC100 Series Connectivity Support Table
Mar. 21, 2019
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2 FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 NuMicro® NUC100 Features – Advanced Line
ARM® Cortex® -M0 core
–
Runs up to 50 MHz
–
–
–
–
–
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
–
–
–
32/64/128 Kbytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
–
–
512 byte page erase for flash
Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash
for the 32 KB and 64 KB system
–
–
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
SRAM Memory
–
–
4/8/16 Kbytes embedded SRAM
Supports PDMA mode
PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
–
Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-
16 and CRC-32
Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
–
–
–
–
Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
Supports one PLL, up to 50 MHz, for high performance system operation
External 4~24 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–
–
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level setting
Timer
Mar. 21, 2019
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NUC100/120xxxDN
–
–
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function
Supports input capture function
Watchdog Timer
–
–
–
–
Multiple clock sources
8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
Wake-up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
6-bit down counter with 11-bit prescale for wide range window selected
RTC
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
–
–
–
–
–
Supports wake-up function
PWM/Capture
–
–
–
–
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
Supports Capture interrupt
UART
–
–
–
–
–
–
–
–
Up to three UART controllers
UART ports with flow control (TXD, RXD, CTS and RTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
SPI
–
–
Up to four sets of SPI controllers
SPI clock rate of Master can be up to 36 MHz (chip working at 5V); SPI clock rate of
Slave can be up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
–
–
–
–
–
–
–
–
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
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–
I2C
Supports three wire, no slave select signal, bi-direction interface
–
–
–
–
–
Up to two sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
–
–
–
I2S
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
–
–
–
–
–
–
–
–
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
–
–
–
–
–
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
EBI (External bus interface)
–
–
–
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
ADC
–
–
–
–
–
–
–
–
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Supports PDMA mode
Analog Comparator
–
Up to two analog comparators
–
–
–
External input or internal Band-gap voltage selectable at negative node
Interrupt when compare results change
Supports Power-down wake-up
Smart Card Host (SC)
–
Compliant to ISO-7816-3 T=0, T=1
–
Supports up to three ISO-7816-3 ports
Mar. 21, 2019
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–
–
–
–
–
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
–
–
–
–
–
–
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card is removal
96-bit unique ID (UID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
–
–
With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 85℃
Packages:
–
All Green package (RoHS)
LQFP 100-pin
LQFP 64-pin
–
–
–
LQFP 48-pin
Mar. 21, 2019
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2.2 NuMicro® NUC120 Features – USB Line
ARM® Cortex® -M0 core
–
Runs up to 50 MHz
–
–
–
–
–
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
–
–
–
32/64/128 Kbytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
–
–
512 byte page erase for flash
Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash
for the 32 KB and 64 KB system
–
–
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
SRAM Memory
–
–
4/8/16 Kbytes embedded SRAM
Supports PDMA mode
PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
–
Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-
16 and CRC-32
Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
–
–
–
–
Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
Supports one PLL, up to 50 MHz, for high performance system operation
External 4~24 MHz high speed crystal input for USB and precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–
–
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level setting
Timer
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Mar. 21, 2019
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NUC100/120xxxDN
–
–
Supports event counting function
Supports input capture function
Watchdog Timer
–
–
–
–
Multiple clock sources
8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
Wake-up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
6-bit down counter with 11-bit prescale for wide range window selected
RTC
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
–
–
–
–
–
Supports wake-up function
PWM/Capture
–
–
–
–
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
Supports Capture interrupt
UART
–
–
–
–
–
–
–
–
Up to three UART controllers
UART ports with flow control (TXD, RXD, CTS and RTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
SPI
–
–
–
–
–
–
–
–
–
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
–
–
–
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
I2C
Mar. 21, 2019
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NUC100/120xxxDN
–
–
–
–
–
Up to two sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
–
–
–
I2S
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
–
–
–
–
–
–
–
–
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
–
–
–
–
–
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
EBI (External bus interface)
–
–
–
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
USB 2.0 Full-Speed Device
–
One set of USB 2.0 FS Device 12 Mbps
–
–
–
–
–
–
–
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 6 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
ADC
–
–
–
–
–
–
–
–
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Supports PDMA mode
Analog Comparator
Mar. 21, 2019
Page 15 of 107
Rev 1.03
NUC100/120xxxDN
–
–
–
–
Up to two analog comparators
External input or internal Band-gap voltage selectable at negative node
Interrupt when compare results change
Supports Power-down wake-up
Smart Card Host (SC)
–
Compliant to ISO-7816-3 T=0, T=1
–
–
–
–
–
–
Supports up to three ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
–
–
–
–
–
–
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
96-bit unique ID (UID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
–
–
With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 85℃
Packages:
–
All Green package (RoHS)
LQFP 100-pin
LQFP 64-pin
–
–
–
LQFP48-pin
Mar. 21, 2019
Page 16 of 107
Rev 1.03
NUC100/120xxxDN
3 ABBREVIATIONS
Acronym
ACMP
ADC
AES
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
APB
AHB
BOD
CAN
DAP
DES
EBI
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
GPIO
HCLK
HIRC
HXT
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital Input/Output
Serial Peripheral Interface
SDIO
SPI
Mar. 21, 2019
Page 17 of 107
Rev 1.03
NUC100/120xxxDN
SPS
Samples per Second
TDES
TMR
Triple Data Encryption Standard
Timer Controller
UART
UCID
USB
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
Mar. 21, 2019
Page 18 of 107
Rev 1.03
NUC100/120xxxDN
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC100/120xxxDN Selection Guide
4.1.1
NuMicro® NUC100 Advanced Line Selection Guide
Connectivity
ISP
Data
Flash
Co
mp.
ISP
ICP
Part Number APROM RAM
Loader I/O Timer
ROM
I2S SC
PWM ADC RTC EBI
Package
UART SPI I2C USB LIN CAN
up to 4x32-
8x12-
bit
NUC100LC1DN 32 KB 4 KB 4 KB 4 KB
2
2
2
3
3
3
3
3
1
1
1
2
2
2
2
4
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
1
1
1
2
2
2
2
2
6
6
6
6
6
6
6
8
v
v
v
v
v
v
v
v
-
-
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP64
LQFP100
37
bit
up to 4x32-
37 bit
8x12-
bit
NUC100LD2DN 64 KB 8 KB 4 KB 4 KB
Defin
v
up to 4x32-
37 bit
8x12-
bit
NUC100LE3DN 128 KB 16 KB
4 KB
-
v
able
up to 4x32-
51 bit
8x12-
bit
NUC100RC1DN 32 KB 4 KB 4 KB 4 KB
NUC100RD1DN 64 KB 4 KB 4 KB 4 KB
v
v
v
v
v
v
up to 4x32-
51 bit
8x12-
bit
v
up to 4x32-
51 bit
8x12-
bit
NUC100RD2DN 64 KB 8 KB 4 KB 4 KB
Defin
v
up to 4x32-
51 bit
8x12-
bit
NUC100RE3DN 128 KB 16 KB
4 KB
v
able
Defin
able
up to 4x32-
84 bit
8x12-
bit
NUC100VE3DN 128 KB 16 KB
4 KB
v
4.1.2
NuMicro® NUC120 USB Line Selection Guide
Connectivity
UART SPI I2C USB LIN CAN
ISP
Data
Flash
Co
mp.
ISP
ICP
Part Number APROM RAM
Loader I/O Timer
ROM
I2S SC
PWM ADC RTC EBI
Package
up to 4x32-
8x12-
bit
NUC120LC1DN 32 KB 4 KB 4 KB 4 KB
2
2
2
2
2
2
2
3
1
1
1
2
2
2
2
4
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
1
1
1
2
2
2
2
2
4
4
4
6
6
6
6
8
v
v
v
v
v
v
v
v
-
-
v
v
v
v
v
v
v
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP64
LQFP100
33
bit
up to 4x32-
33 bit
8x12-
bit
NUC120LD2DN 64 KB 8 KB 4 KB 4 KB
Defin
up to 4x32-
33 bit
8x12-
bit
NUC120LE3DN 128 KB 16 KB
4 KB
-
able
up to 4x32-
47 bit
8x12-
bit
NUC120RC1DN 32 KB 4 KB 4 KB 4 KB
NUC120RD1DN 64 KB 4 KB 4 KB 4 KB
v
v
v
v
v
up to 4x32-
47 bit
8x12-
bit
up to 4x32-
47 bit
8x12-
bit
NUC120RD2DN 64 KB 8 KB 4 KB 4 KB
Defin
up to 4x32-
47 bit
8x12-
bit
NUC120RE3DN 128 KB 16 KB
4 KB
able
Defin
able
up to 4x32-
80 bit
8x12-
bit
NUC120VE3DN 128 KB 16 KB
4 KB
Mar. 21, 2019
Page 19 of 107
Rev 1.03
NUC100/120xxxDN
NUC 1 0 0 - X X X X X
ARM-Based
32-bit Microcontroller
Temperature
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
CPU core
1/2: Cortex-M0
5/7: ARM7
9: ARM9
Reserve
RAM Size
1: 4 KB
2: 8 KB
Function
0: Advanced Line
2: USB Line
3: Automotive Line
4: Connectivity Line
3: 16 KB
APROM Size
A: 8 KB
Package Type
Y: QFN 36
L: LQFP 48
R: LQFP 64
V: LQFP 100
B: 16 KB
C: 32 KB
D: 64 KB
E: 128 KB
Figure 4-1 NuMicro® NUC100 Series Selection Code
Mar. 21, 2019
Page 20 of 107
Rev 1.03
NUC100/120xxxDN
4.2 Pin Configuration
4.2.1
NuMicro® NUC100 Pin Diagram
4.2.1.1 NuMicro® NUC100VxxDN LQFP 100 pin
SC1RST/AD8/ADC5/PA.5
SC1CLK/AD7/ADC6/PA.6
SC1DAT/AD6/ADC7/SPISS21/PA.7
VREF
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM0/SPISS11
PB.10/TM1/SPISS01
PB.11/TM2/PWM4
PE.5/T1EX/PWM5
PE.6
AVDD
SPISS20/PD.0
SPICLK2/PD.1
MISO20/PD.2
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PC.4/MISO01
PC.5/MOSI01
PD.15/TXD2
MOSI20/PD.3
MISO21/PD.4
MOSI21/PD.5
SC1CD/AD5/CPN0/PC.7
SC0CD/AD4/CPP0/PC.6
AD3/CPN1/PC.15
AD2/CPP1/PC.14
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC100VxxDN
LQFP 100-pin
PD.14/RXD2
PD.7
PD.6
PB.3/CTS0/T3EX/nWRH/SC2CD
PB.2/RTS0/T2EX/nWRL
PB.1/TXD0
/RESET
PB.0/RXD0
VSS
PE.7
VDD
PE.8
PS2DAT/PF.2
PE.9
PS2CLK/PF.3
PE.10
PVSS
PE.11
TM0/STADC/PB.8
PE.12
Figure 4-2 NuMicro® NUC100VxxDN LQFP 100-pin Diagram
Mar. 21, 2019
Page 21 of 107
Rev 1.03
NUC100/120xxxDN
4.2.1.2 NuMicro® NUC100RxxDN LQFP 64 pin
SC1RST/AD8/ADC5/PA.5
SC1CLK/AD7/ADC6/PA.6
SC1DAT/AD6/ADC7/PA.7
AVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
PB.11/TM3/PWM4
PE.5/T1EX/PWM5
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PD.15/TXD2
SC1CD/AD5/CPN0/PC.7
SC0CD/AD4/CPP0/PC.6
AD3/CPN1/PC.15
AD2/CPP1/PC.14
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC100RxxDN
LQFP 64-pin
PD.14/RXD2
PD.7
/RESET
PD.6
VSS
PB.3/CTS0/T3EX/nWRH/SC2CD
PB.2/RTS0/T2EX/nWRL
PB.1/TXD0
VDD
PVSS
TM0/STADC/PB.8
PB.0/RXD0
Figure 4-3 NuMicro® NUC100RxxDN LQFP 64-pin Diagram
Mar. 21, 2019
Page 22 of 107
Rev 1.03
NUC100/120xxxDN
4.2.1.3 NuMicro® NUC100LxxDN LQFP 48 pin
SC1RST/ADC5/PA.5
SC1CLK/ADC6/PA.6
SC1DAT/ADC7/PA.7
AVDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PB.9/TM1
PB.10/TM2
PB.11/TM3/PWM4
PE.5/T1EX/PWM5
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PB.3/CTS0/T3EX/SC2CD
PB.2/RTS0/T2EX
PB.1/TXD0
SC1CD/CPN0/PC.7
SC0CD/CPP0/PC.6
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC100LxxDN
LQFP 48-pin
/RESET
PVSS
TM0/STADC/PB.8
PB.0/RXD0
Figure 4-4 NuMicro® NUC100LxxDN LQFP 48-pin Diagram
Mar. 21, 2019
Page 23 of 107
Rev 1.03
NUC100/120xxxDN
4.2.2
4.2.2.1 NuMicro® NUC120VxxDN LQFP 100 pin
NuMicro® NUC120 Pin Diagram
SC1RST/AD8/ADC5/PA.5
SC1CLK/AD7/ADC6/PA.6
SC1DAT/AD6/ADC7/SPISS21/PA.7
VREF
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM1/SPISS11
PB.10/TM2/SPISS01
PB.11/TM3/PWM4
PE.5/T1EX/PWM5
PE.6
AVDD
SPISS20/PD.0
SPICLK2/PD.1
MISO20/PD.2
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PC.4/MISO01
PC.5/MOSI01
PD.15/TXD2
PD.14/RXD2
PD.7
MOSI20/PD.3
MISO21/PD.4
MOSI21/PD.5
SC1CD/AD5/CPN0/PC.7
SC0CD/AD4/CPP0/PC.6
AD3/CPN1/PC.15
AD2/CPP1/PC.14
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC120VxxDN
LQFP 100-pin
PD.6
PB.3/CTS0/T3EX/nWRH/SC2CD
PB.2/RTS0/T2EX/nWRL
PB.1/TXD0
/RESET
PB.0/RXD0
VSS
D+
VDD
D-
PS2DAT/PF.2
VDD33
PS2CLK/PF.3
VBUS
PVSS
PE.7
TM0/STADC/PB.8
PE.8
Figure 4-5 NuMicro® NUC120VxxDN LQFP 100-pin Diagram
Mar. 21, 2019
Page 24 of 107
Rev 1.03
NUC100/120xxxDN
4.2.2.2 NuMicro® NUC120RxxDN LQFP 64 pin
SC1RST/AD8/ADC5/PA.5
SC1CLK/AD7/ADC6/PA.6
SC1DAT/AD6/ADC7/PA.7
AVDD
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
PB.11/TM3/PWM4
PE.5/T1EX/PWM5
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PB.3/CTS0/T3EX/nWRH/SC2CD
PB.2/RTS0/T2EX/nWRL
PB.1/TXD0
SC1CD/AD5/CPN0/PC.7
SC0CD/AD4/CPP0/PC.6
AD3/CPN1/PC.15
AD2/CPP1/PC.14
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC120RxxDN
LQFP 64-pin
/RESET
PB.0/RXD0
VSS
D+
VDD
D-
PVSS
VDD33
TM0/STADC/PB.8
VBUS
Figure 4-6 NuMicro® NUC120RxxDN LQFP 64-pin Diagram
Mar. 21, 2019
Page 25 of 107
Rev 1.03
NUC100/120xxxDN
4.2.2.3 NuMicro® NUC120LxxDN LQFP 48 pin
SC1RST/ADC5/PA.5
SC1CLK/ADC6/PA.6
SC1DAT/ADC7/PA.7
AVDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPISS00/I2SLRCLK
PC.1/SPICLK0/I2SBCLK
PC.2/MISO00/I2SDI
PC.3/MOSI00/I2SDO
PB.3/CTS0/T3EX/SC2CD
PB.2/RTS0/T2EX
PB.1/TXD0
SC1CD/CPN0/PC.7
SC0CD/CPP0/PC.6
T0EX/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC120LxxDN
LQFP 48-pin
PB.0/RXD0
D+
/RESET
D-
PVSS
VDD33
TM0/STADC/PB.8
VBUS
Figure 4-7 NuMicro® NUC120LxxDN LQFP 48-pin Diagram
Mar. 21, 2019
Page 26 of 107
Rev 1.03
NUC100/120xxxDN
4.3 Pin Description
NuMicro® NUC100 Pin Description
4.3.1
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
1
2
3
PE.15
PE.14
PE.13
PB.14
/INT0
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
External interrupt0 input pin.
2nd SPI3 slave select pin.
1
2
3
4
5
SPISS31
PB.13
CPO1
AD1
I/O
I/O
O
General purpose digital I/O pin.
Comparator1 output pin.
I/O
I/O
O
EBI Address/Data bus bit1
General purpose digital I/O pin.
Comparator0 output pin
PB.12
CPO0
CLKO
AD0
1
6
O
Frequency Divider output pin
EBI Address/Data bus bit0
I/O
O
7
8
4
5
2
3
X32O
External 32.768 kHz low speed crystal output pin
External 32.768 kHz low speed crystal input pin
General purpose digital I/O pin.
I2C1 clock pin.
X32I
I
PA.11
I2C1SCL
nRD
I/O
I/O
O
4
9
6
7
EBI read enable output pin
General purpose digital I/O pin.
I2C1 data input/output pin.
PA.10
I2C1SDA
nWR
I/O
I/O
O
5
10
EBI write enable output pin
General purpose digital I/O pin.
I2C0 clock pin.
PA.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11
12
13
8
9
6
7
I2C0SCL
PA.8
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0SDA
PD.8
General purpose digital I/O pin.
1st SPI3 slave select pin.
SPISS30
PD.9
General purpose digital I/O pin.
SPI3 serial clock pin.
14
15
SPICLK3
PD.10
General purpose digital I/O pin.
Mar. 21, 2019
Page 27 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
MISO30
PD.11
MOSI30
PD.12
MISO31
PD.13
MOSI31
PB.4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1st SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Request to Send output pin for UART1.
EBI address latch enable output pin
General purpose digital I/O pin.
Clear to Send input pin for UART1.
EBI chip select enable output pin
LDO output pin
16
17
18
19
20
10
11
8
9
RXD1
PB.5
I/O
O
TXD1
PB.6
I/O
O
21
22
12
13
RTS1
ALE
O
PB.7
I/O
I
CTS1
nCS
O
23
24
14
15
16
10
11
12
LDO
P
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
P
25
26
27
28
29
30
31
VSS
P
Ground pin for digital circuit.
PE.12
PE.11
PE.10
PE.9
PE.8
PE.7
PB.0
RXD0
PB.1
TXD0
PB.2
RTS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Request to Send output pin for UART0.
32
33
34
17
18
19
13
14
15
I/O
O
I/O
O
Mar. 21, 2019
Page 28 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
T2EX
nWRL
PB.3
I
O
I/O
I
Timer2 external capture input pin.
EBI low byte write enable output pin
General purpose digital I/O pin.
Clear to Send input pin for UART0.
Timer3 external capture input pin.
CTS0
T3EX
16
I
35
20
SC2CD
I
SmartCard2 card detect pin.
nWRH
PD.6
O
EBI high byte write enable output pin
General purpose digital I/O pin.
General purpose digital I/O pin.
36
37
21
22
I/O
I/O
PD.7
PD.14
RXD2
I/O
I
General purpose digital I/O pin.
38
23
24
Data receiver input pin for UART2.
PD.15
TXD2
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART2.
General purpose digital I/O pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I2S data output.
39
40
41
PC.5
I/O
I/O
I/O
I/O
I/O
I/O
O
MOSI01
PC.4
MISO01
PC.3
42
43
44
25
26
27
17
18
19
MOSI00
I2SDO
PC.2
I/O
I/O
I
General purpose digital I/O pin.
1st SPI0 MISO (Master In, Slave Out) pin.
I2S data input.
MISO00
I2SDI
PC.1
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
SPI0 serial clock pin.
SPICLK0
I2SBCLK
PC.0
I2S bit clock pin.
General purpose digital I/O pin.
45
28
20
21
SPISS00
I/O
1st SPI0 slave select pin.
I2SLRCLK
PE.6
I/O
I/O
I/O
I/O
I2S left right channel clock.
46
47
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM5 output/Capture input.
PE.5
29
PWM5
Mar. 21, 2019
Page 29 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
T1EX
PB.11
TM3
I
Timer1 external capture input pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
Timer3 event counter input / toggle output.
PWM4 output/Capture input.
48
49
50
30
31
22
23
PWM4
PB.10
TM2
General purpose digital I/O pin.
Timer2 event counter input / toggle output.
2nd SPI0 slave select pin.
SPISS01
PB.9
General purpose digital I/O pin.
Timer1 event counter input / toggle output.
2nd SPI1 slave select pin.
32
24
TM1
SPISS11
PE.4
51
52
53
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PE.3
PE.2
PE.1
I/O
General purpose digital I/O pin.
54
PWM7
PE.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM7 output/Capture input.
General purpose digital I/O pin.
PWM6 output/Capture input.
55
56
57
58
59
PWM6
PC.13
MOSI11
PC.12
MISO11
PC.11
MOSI10
PC.10
MISO10
PC.9
General purpose digital I/O pin.
2nd SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
33
34
60
35
SPICLK1
I/O
SPI1 serial clock pin.
PC.8
I/O
I/O
O
General purpose digital I/O pin.
1st SPI1 slave select pin.
61
62
36
37
SPISS10
MCLK
PA.15
PWM3
EBI external clock output pin
General purpose digital I/O pin.
PWM output/Capture input.
I/O
I/O
25
Mar. 21, 2019
Page 30 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
I2SMCLK
SC2PWR
PA.14
O
O
I2S master clock output pin.
SmartCard2 power pin.
I/O
I/O
O
General purpose digital I/O pin.
PWM2 output/Capture input.
SmartCard2 reset pin.
26
27
28
PWM2
63
64
65
38
39
40
SC2RST
AD15
I/O
I/O
I/O
O
EBI Address/Data bus bit15
General purpose digital I/O pin.
PWM1 output/Capture input.
SmartCard2 clock pin.
PA.13
PWM1
SC2CLK
AD14
I/O
I/O
I/O
O
EBI Address/Data bus bit14
General purpose digital I/O pin.
PWM0 output/Capture input.
SmartCard2 data pin.
PA.12
PWM0
SC2DAT
AD13
I/O
I/O
I
EBI Address/Data bus bit13
Serial Wire Debugger Data pin
Serial Wire Debugger Clock pin
66
67
41
42
29
30
ICE_DAT
ICE_CLK
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
68
VDD
P
69
70
VSS
P
AP
I/O
AI
Ground pin for digital circuit.
Ground pin for analog circuit.
General purpose digital I/O pin.
ADC0 analog input.
43
44
31
32
AVSS
PA.0
71
ADC0
SC0PWR
PA.1
O
SmartCard0 power pin.
I/O
AI
General purpose digital I/O pin.
ADC1 analog input.
33
ADC1
SC0RST
AD12
PA.2
72
45
O
SmartCard0 reset pin.
I/O
I/O
AI
EBI Address/Data bus bit12
General purpose digital I/O pin.
ADC2 analog input.
34
35
ADC2
SC0CLK
AD11
PA.3
73
74
46
47
O
SmartCard0 clock pin.
I/O
I/O
AI
EBI Address/Data bus bit11
General purpose digital I/O pin.
ADC3 analog input.
ADC3
Mar. 21, 2019
Page 31 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
SC0DAT
AD10
O
SmartCard0 data pin.
I/O
I/O
AI
EBI Address/Data bus bit10
General purpose digital I/O pin.
ADC4 analog input.
PA.4
36
37
38
ADC4
SC1PWR
AD9
75
76
77
48
49
50
O
SmartCard1 power pin.
I/O
I/O
AI
EBI Address/Data bus bit9
General purpose digital I/O pin.
ADC5 analog input.
PA.5
ADC5
SC1RST
AD8
O
SmartCard1 reset pin.
I/O
I/O
AI
EBI Address/Data bus bit8
General purpose digital I/O pin.
ADC6 analog input.
PA.6
ADC6
SC1CLK
AD7
I/O
I/O
I/O
AI
SmartCard1 clock pin.
EBI Address/Data bus bit7
General purpose digital I/O pin.
ADC7 analog input.
PA.7
ADC7
SC1DAT
SPISS21
AD6
39
78
51
52
O
SmartCard1 data pin.
I/O
I/O
AP
AP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2nd SPI2 slave select pin.
EBI Address/Data bus bit6
Voltage reference input for ADC.
Power supply for internal analog circuit.
General purpose digital I/O pin.
1st SPI2 slave select pin.
79
80
VREF
40
AVDD
PD.0
81
82
83
84
85
86
SPISS20
PD.1
General purpose digital I/O pin.
SPI2 serial clock pin.
SPICLK2
PD.2
General purpose digital I/O pin.
1st SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI2 MOSI (Master Out, Slave In) pin.
MISO20
PD.3
MOSI20
PD.4
MISO21
PD.5
MOSI21
Mar. 21, 2019
Page 32 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PC.7
I/O
AI
I
General purpose digital I/O pin.
41
42
CPN0
SC1CD
AD5
Comparator0 negative input pin.
SmartCard1 card detect pin.
EBI Address/Data bus bit5
87
88
53
54
I/O
I/O
AI
I
PC.6
General purpose digital I/O pin.
Comparator0 positive input pin.
SmartCard0 card detect pin.
EBI Address/Data bus bit4
CPP0
SC0CD
AD4
I/O
I/O
AI
I/O
I/O
AI
I/O
I/O
I
PC.15
CPN1
AD3
General purpose digital I/O pin.
Comparator1 negative input pin.
EBI Address/Data bus bit3
89
90
91
55
56
57
PC.14
CPP1
AD2
General purpose digital I/O pin.
Comparator1 positive input pin.
EBI Address/Data bus bit2
PB.15
/INT1
T0EX
PF.0
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external capture input pin.
General purpose digital I/O pin.
43
44
I
I/O
O
92
93
58
59
XT1_OUT
PF.1
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
I/O
I
45
46
XT1_IN
/RESET
VSS
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up. Set this
Ground pin for digital circuit.
94
95
96
60
61
62
I
P
P
Power supply for I/O ports and LDO source for internal PLL and
VDD
PF.2
I/O
I/O
I/O
I/O
P
General purpose digital I/O pin.
97
PS2DAT
PF.3
PS/2 data pin.
General purpose digital I/O pin.
PS/2 clock pin.
98
99
PS2CLK
PVSS
63
64
47
48
PLL ground.
PB.8
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
Timer0 event counter input / toggle output.
100
STADC
TM0
I/O
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
Mar. 21, 2019
Page 33 of 107
Rev 1.03
NUC100/120xxxDN
4.3.2
NuMicro® NUC120 Pin Description
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
1
2
3
PE.15
PE.14
PE.13
PB.14
/INT0
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
External interrupt0 input pin.
2nd SPI3 slave select pin.
1
2
3
4
5
SPISS31
PB.13
CPO1
AD1
I/O
I/O
O
General purpose digital I/O pin.
Comparator1 output pin.
I/O
I/O
O
EBI Address/Data bus bit1
General purpose digital I/O pin.
Comparator0 output pin
PB.12
CPO0
CLKO
AD0
1
6
O
Frequency Divider output pin
EBI Address/Data bus bit0
I/O
O
7
8
4
5
2
3
X32O
External 32.768 kHz low speed crystal output pin
External 32.768 kHz low speed crystal input pin
General purpose digital I/O pin.
I2C1 clock pin.
X32I
I
PA.11
I2C1SCL
nRD
I/O
I/O
O
4
9
6
7
EBI read enable output pin
PA.10
I2C1SDA
nWR
I/O
I/O
O
General purpose digital I/O pin.
I2C1 data input/output pin.
5
10
EBI write enable output pin
PA.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
I2C0 clock pin.
11
12
13
14
8
9
6
7
I2C0SCL
PA.8
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0SDA
PD.8
General purpose digital I/O pin.
1st SPI3 slave select pin.
SPISS30
PD.9
General purpose digital I/O pin.
SPI3 serial clock pin.
SPICLK3
PD.10
MISO30
PD.11
General purpose digital I/O pin.
1st SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
15
16
Mar. 21, 2019
Page 34 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
MOSI30
PD.12
MISO31
PD.13
MOSI31
PB.4
I/O
I/O
I/O
I/O
I/O
I/O
I
1st SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Request to Send output pin for UART1.
EBI address latch enable output pin
General purpose digital I/O pin.
Clear to Send input pin for UART1.
EBI chip select enable output pin
LDO output pin
17
18
19
20
10
11
8
9
RXD1
PB.5
I/O
O
TXD1
PB.6
I/O
O
21
22
12
13
RTS1
ALE
O
PB.7
I/O
I
CTS1
nCS
O
23
24
14
15
16
10
11
12
LDO
P
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
P
25
26
27
28
29
30
31
VSS
P
I/O
I/O
USB
USB
USB
USB
I/O
I
Ground pin for digital circuit.
PE.8
PE.7
VBUS
VDD33
D-
General purpose digital I/O pin.
General purpose digital I/O pin.
Power supply from USB host or HUB.
Internal power regulator output 3.3V decoupling pin.
USB differential signal D-.
17
18
19
20
13
14
15
16
D+
USB differential signal D+.
PB.0
RXD0
PB.1
TXD0
PB.2
RTS0
T2EX
nWRL
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external capture input pin.
EBI low byte write enable output pin
32
33
21
22
17
18
I/O
O
I/O
O
29
34
23
I
O
Mar. 21, 2019
Page 35 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PB.3
I/O
General purpose digital I/O pin.
CTS0
T3EX
I
I
Clear to Send input pin for UART0.
Timer3 external capture input pin.
SmartCard2 card detect pin.
20
35
24
SC2CD
I
nWRH
PD.6
O
EBI high byte write enable output pin
General purpose digital I/O pin.
General purpose digital I/O pin.
36
37
I/O
I/O
PD.7
PD.14
RXD2
I/O
I
General purpose digital I/O pin.
38
Data receiver input pin for UART2.
PD.15
TXD2
I/O
O
General purpose digital I/O pin.
Data transmitter output pin for UART2.
General purpose digital I/O pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I2S data output.
39
40
41
PC.5
I/O
I/O
I/O
I/O
I/O
I/O
O
MOSI01
PC.4
MISO01
PC.3
42
43
44
25
26
27
21
22
23
MOSI00
I2SDO
PC.2
I/O
I/O
I
General purpose digital I/O pin.
1st SPI0 MISO (Master In, Slave Out) pin.
I2S data input.
MISO00
I2SDI
PC.1
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
SPI0 serial clock pin.
SPICLK0
I2SBCLK
PC.0
I2S bit clock pin.
General purpose digital I/O pin.
45
28
24
SPISS00
I/O
1st SPI0 slave select pin.
I2SLRCLK
PE.6
I/O
I/O
I/O
I/O
I
I2S left right channel clock.
46
47
48
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM5 output/Capture input.
Timer1 external capture input pin.
General purpose digital I/O pin.
PE.5
PWM5
T1EX
29
30
PB.11
I/O
Mar. 21, 2019
Page 36 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
TM3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Timer3 event counter input / toggle output.
PWM4
PB.10
TM2
PWM4 output/Capture input.
General purpose digital I/O pin.
Timer2 event counter input / toggle output.
2nd SPI0 slave select pin.
31
32
49
50
SPISS01
PB.9
General purpose digital I/O pin.
Timer1 event counter input / toggle output.
2nd SPI1 slave select pin.
TM1
SPISS11
PE.4
51
52
53
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PE.3
PE.2
PE.1
I/O
General purpose digital I/O pin.
54
PWM7
PE.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PWM7 output/Capture input.
General purpose digital I/O pin.
PWM6 output/Capture input.
55
56
57
58
59
PWM6
PC.13
MOSI11
PC.12
MISO11
PC.11
MOSI10
PC.10
MISO10
PC.9
General purpose digital I/O pin.
2nd SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
33
34
60
61
35
36
SPICLK1
I/O
SPI1 serial clock pin.
PC.8
I/O
I/O
O
General purpose digital I/O pin.
1st SPI1 slave select pin.
SPISS10
MCLK
EBI external clock output pin
General purpose digital I/O pin.
PWM output/Capture input.
I2S master clock output pin.
PA.15
I/O
I/O
O
PWM3
I2SMCLK
62
37
25
SC2PWR
O
SmartCard2 power pin.
Mar. 21, 2019
Page 37 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PA.14
I/O
I/O
O
General purpose digital I/O pin.
26
27
28
PWM2
SC2RST
AD15
PWM2 output/Capture input.
SmartCard2 reset pin.
63
64
65
38
39
40
I/O
I/O
I/O
O
EBI Address/Data bus bit15
General purpose digital I/O pin.
PWM1 output/Capture input.
SmartCard2 clock pin.
PA.13
PWM1
SC2CLK
AD14
I/O
I/O
I/O
O
EBI Address/Data bus bit14
General purpose digital I/O pin.
PWM0 output/Capture input.
SmartCard2 data pin.
PA.12
PWM0
SC2DAT
AD13
I/O
I/O
I
EBI Address/Data bus bit13
Serial Wire Debugger Data pin
Serial Wire Debugger Clock pin
66
67
41
42
29
30
ICE_DAT
ICE_CLK
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
68
VDD
P
69
70
VSS
P
AP
I/O
AI
Ground pin for digital circuit.
Ground pin for analog circuit.
General purpose digital I/O pin.
ADC0 analog input.
43
44
31
32
AVSS
PA.0
71
72
ADC0
SC0PWR
PA.1
O
SmartCard0 power pin.
General purpose digital I/O pin.
ADC1 analog input.
I/O
AI
33
34
35
ADC1
SC0RST
AD12
PA.2
45
46
47
O
SmartCard0 reset pin.
I/O
I/O
AI
EBI Address/Data bus bit12
General purpose digital I/O pin.
ADC2 analog input.
ADC2
SC0CLK
AD11
PA.3
73
74
O
SmartCard0 clock pin.
I/O
I/O
AI
EBI Address/Data bus bit11
General purpose digital I/O pin.
ADC3 analog input.
ADC3
SC0DAT
AD10
O
SmartCard0 data pin.
I/O
EBI Address/Data bus bit10
Mar. 21, 2019
Page 38 of 107
Rev 1.03
NUC100/120xxxDN
Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PA.4
I/O
AI
General purpose digital I/O pin.
36
37
38
ADC4
SC1PWR
AD9
ADC4 analog input.
75
76
77
48
49
50
O
SmartCard1 power pin.
I/O
I/O
AI
EBI Address/Data bus bit9
General purpose digital I/O pin.
ADC5 analog input.
PA.5
ADC5
SC1RST
AD8
O
SmartCard1 reset pin.
I/O
I/O
AI
EBI Address/Data bus bit8
General purpose digital I/O pin.
ADC6 analog input.
PA.6
ADC6
SC1CLK
AD7
I/O
I/O
I/O
AI
SmartCard1 clock pin.
EBI Address/Data bus bit7
General purpose digital I/O pin.
ADC7 analog input.
PA.7
ADC7
SC1DAT
SPISS21
AD6
39
78
51
52
O
SmartCard1 data pin.
I/O
I/O
AP
AP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AI
2nd SPI2 slave select pin.
EBI Address/Data bus bit6
Voltage reference input for ADC.
Power supply for internal analog circuit.
General purpose digital I/O pin.
1st SPI2 slave select pin.
79
80
VREF
40
AVDD
PD.0
81
82
83
84
85
86
87
SPISS20
PD.1
General purpose digital I/O pin.
SPI2 serial clock pin.
SPICLK2
PD.2
General purpose digital I/O pin.
1st SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Comparator0 negative input pin.
MISO20
PD.3
MOSI20
PD.4
MISO21
PD.5
MOSI21
PC.7
53
41
CPN0
Mar. 21, 2019
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Pin No.
Pin Name
Pin Type Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
SC1CD
AD5
I
SmartCard1 card detect pin.
I/O
I/O
AI
I
EBI Address/Data bus bit5
PC.6
General purpose digital I/O pin.
Comparator0 positive input pin.
SmartCard0 card detect pin.
EBI Address/Data bus bit4
42
CPP0
SC0CD
AD4
88
54
I/O
I/O
AI
I/O
I/O
AI
I/O
I/O
I
PC.15
CPN1
AD3
General purpose digital I/O pin.
Comparator1 negative input pin.
EBI Address/Data bus bit3
89
90
91
55
56
57
PC.14
CPP1
AD2
General purpose digital I/O pin.
Comparator1 positive input pin.
EBI Address/Data bus bit2
PB.15
/INT1
T0EX
PF.0
General purpose digital I/O pin.
External interrupt1 input pin.
Timer0 external capture input pin.
General purpose digital I/O pin.
43
44
I
I/O
O
92
93
58
59
XT1_OUT
PF.1
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
I/O
I
45
46
XT1_IN
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up. Set this
pin low reset chip to initial state.
94
95
96
60
61
62
/RESET
VSS
I
P
P
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
PF.2
I/O
I/O
I/O
I/O
P
General purpose digital I/O pin.
PS/2 data pin.
97
PS2DAT
PF.3
General purpose digital I/O pin.
PS/2 clock pin.
98
99
PS2CLK
PVSS
63
64
47
48
PLL ground.
PB.8
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
Timer0 event counter input / toggle output.
100
STADC
TM0
I/O
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
Mar. 21, 2019
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5 BLOCK DIAGRAM
5.1 NuMicro® NUC100 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
LDROM
4 KB
APROM
128/64/32 KB
RTC
ARM
Cortex-M0
50MHz
PDM
A
EBI
Analog
Comparator x2
Watchdog Timer
SRAM
16/8/4 KB
DataFlash
4 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
SPI x 4
I/O Ports
General Purpose
I/O
LDO
External
Interrupt
Power On Reset
LVR
High Speed
Oscillator
22.1184 MHz
High Speed
Crystal Osc.
4 ~ 24 MHz
I2C x 2
I2S
Reset Pin
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
PS/2
SC x3
Brownout
Detection
Figure 5-1 NuMicro® NUC100 Block Diagram
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5.2 NuMicro® NUC120 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
APROM
128/64/32 KB
LDROM
4 KB
RTC
ARM
Cortex-M0
50MHz
PDM
A
USB PHY
EBI
Watchdog Timer
Analog
Comparator x2
DataFlash
4 KB
SRAM
16/8/4 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
I/O Ports
General Purpose
I/O
LDO
Power On Reset
LVR
SPI x 4
I2C x 2
I2S
External
Interrupt
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
22.1184 MHz
Reset Pin
PS/2
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
SC x3
USB
Brownout
Detection
Figure 5-2 NuMicro® NUC120 Block Diagram
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6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex® -M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
Cortex® -M0 Components
Cortex® -M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex® -M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
–
–
–
–
–
–
–
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
–
–
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
Mar. 21, 2019
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NUC100/120xxxDN
–
–
–
–
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
–
–
–
–
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
–
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
–
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for
System Reset
System Power Architecture
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from RSTSRC register to determine the reset source. Hardware reset can reset chip through
peripheral reset signals. Software reset can trigger reset through control registers.
Hardware Reset Sources
–
–
–
–
–
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
Software Reset Sources
–
–
CHIP Reset will reset whole chip by writing 1 to CHIP_RST (IPRSTC1[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM
by writing 1 to SYSRESETREQ (AIRCR[2])
–
CPU Reset for Cortex® -M0 core Only by writing 1 to CPU_RST (IPRSTC1[1])
Power-on Reset or CHIP_RST (IPRSTC1[0]) reset the whole chip including all peripherals,
external crystal circuit and BS (ISPCON[1]) bit.
SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset
external crystal circuit and BS (ISPCON[1]) bit.
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Glitch Filter
36 us
nRESET
~50k ohm
@5v
POR_DIS_CODE(PORCR[15:0])
Power-on
Reset
VDD
LVR_EN(BODCR[7])
Reset Pulse Width
3.2ms
Low Voltage
Reset
AVDD
BOD_RSTEN(BODCR[3])
Brown-out
Reset
System Reset
WDT/WWDT
Reset
Reset Pulse Width
64 WDT clocks
CHIP Reset
CHIP_RST(IPRSTC1[0])
MCU Reset
SYSRESETREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPU_RST(IPRSTC1[1])
Figure 6-2 System Reset Resources
There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex® -M0 only; the other reset sources will reset Cortex® -M0 and all peripherals. However,
there are small differences between each reset source and they are listed in Table 6-1.
Reset Sources
POR
nRESET
WDT
LVR
BOD
CHIP
MCU
CPU
Register
RSTSRC
Bit 0 = 1
0x0
Bit 1 = 1
-
Bit 2 = 1
-
Bit 3 = 1
-
Bit 4 = 1
-
Bit 0 = 1
-
Bit 5 = 1
-
Bit 7 = 1
-
CHIP_RST
(IPRSTC1[0])
BOD_EN
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
-
Reload
from
CONFIG0
Reload
from
CONFIG0
-
(BODCR[0])
BOD_VL
(BODCR[2:1])
BOD_RSTEN
(BODCR[3])
XTL12M_EN
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
-
(PWRCON[0])
WDT_EN
0x1
-
0x1
-
-
0x1
-
-
-
(APBCLK[0])
HCLK_S
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
(CLKSEL0[2:0])
WDT_S
0x3
0x3
-
-
-
-
-
-
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(CLKSEL1[1:0])
XTL12M_STB
0x0
0x0
0x0
0x0
0x0
0x0
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLKSTATUS[0])
XTL32K_STB
-
-
-
-
-
-
(CLKSTATUS[1])
PLL_STB
-
-
-
-
-
-
(CLKSTATUS[2])
OSC10K_STB
-
-
-
-
-
-
(CLKSTATUS[3])
OSC22M_STB
-
-
-
-
-
-
(CLKSTATUS[4])
CLK_SW_FAIL
0x0
0x0
0x0
0x0
0x0
0x0
-
(CLKSTATUS[7])
WTE
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
(WTCR[7])
WTCR
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
0x0700
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WTCRALT
WWDTRLD
WWDTCR
WWDTSR
WWDTCVR
BS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
(ISPCON[1])
DFBADR
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
Reload
from
CONFIG1
-
-
-
-
-
-
-
CBS
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
Reload
from
CONFIG0
(ISPSTA[2:1))
VECMAP
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
Reload
base on
CONFIG0
(ISPSTA[20:9])
Other Peripheral
Registers
Reset Value
Reset Value
FMC Registers
Note: ‘-‘ means that the value of register keeps original setting.
Table 6-1 Reset Value of Registers
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6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will
be set to 1 if the previous reset source is nRESET reset. Figure 6-3 shows the nRESET reset
waveform.
nRESET
0.7 VDD
0.2 VDD
36 us
SS
36 us
nRESET Reset
SS
Figure 6-3 nRESET Reset Waveform
6.2.2.2 Power-On Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be
set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared
by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset.
VPOR
0.1V
VDD
Power On
Reset
Figure 6-4 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit
LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
Mar. 21, 2019
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AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles),
chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises
above VLVR and the state keeps longer than De-glitch time. The RSTS_RESET (RSTSRC[1]) will
be set to 1 if the previous reset source is nRESET reset. Figure 6-5 shows the Low Voltage Reset
waveform.
AVDD
VLVR
T1
T2
(<De-glitch time)
(=De-glitch time)
T3
(=De-glitch time)
Low Voltage Reset
LVR_EN
100 us
Delay for LVR stable
Figure 6-5 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BOD_EN (BODCR[0]), Brown-Out Detector function will detect AVDD during system operation.
When the AVDD voltage is lower than VBOD which is decided by BOD_EN (BODCR[0]) and
BOD_VL (BODCR[2:1]) and the state keeps longer than De-glitch time (Max(20*HCLK cycles,
1*LIRC cycle)), chip will be reset. The BOD reset will control the chip in reset state until the AVDD
voltage rises above VBOD and the state keeps longer than De-glitch time. The default value of
BOD_EN, BOD_VL and BOD_RSTEN is set by flash controller user configuration register
CBODEN (CONFIG0[23]), CBOV1-0 (CONFIG0[22:21]) and CBORST (CONFIG0[20])
respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure
6-6 shows the Brown-Out Detector waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< de-glitch time) (= de-glitch time)
BODOUT
T3
(= de-glitch time)
BODRSTEN
Brown-out
Reset
Figure 6-6 Brown-Out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
RSTS_WDT (RSTSRC[2]).
6.2.2.6 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M0 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPU Reset CPU_RST (IPRSTC1[1]) to 1 to assert the
CPU Reset signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS
(ISPCON[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIP Reset
CHIP_RST (IPRSTC1[0]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS (ISPCON[1]) will not be
reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or
LDROM. User can set the MCU Reset SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
Mar. 21, 2019
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6.2.3 Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state
and all clocks stop
except LXT and LIRC.
SRAM content
retended.
Entry Condition
Chip is in normal
mode after system
reset released
CPU executes WFI
instruction.
CPU sets sleep mode
enable and power
down enable and
executes WFI
instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C,
Timer, UART, BOD,
USB and GPIO
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal
mode
CPU back to normal
mode
Table 6-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, LXT, HIRC, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SLEEPDEEP(SCR[2]) = 1
2. PWR_DOWN_EN (PWRCON[7]) = 1
PD_WAIT_CPU (PWRCON[8]) = 1
3. CPU executes WFI
Wake-up events
occur
Idle Mode
Power-down Mode
CPU Clock OFF
HXT, LXT, HIRC, LIRC, HCLK, PCLK ON
Flash Halt
CPU Clock OFF
HIRC, HCLK, PCLK OFF
LXT, LIRC ON
HXT,
Flash Halt
Figure 6-7 Power Mode State Machine
1. LXT (32 kHz XTL) ON or OFF depends on S/W setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
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3. If TIMER clock source is selected as LXT/LIRC and LXT/LIRC is on.
4. If PWM clock source is selected as LXT and LXT is on.
5. If WDT clock source is selected as LXT/LIRC and LXT/LIRC is on.
6. If RTC clock source LXT is on.
Normal Mode
Idle Mode
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Power-down Mode
HXT (4~20 MHz XTL)
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Halt
Halt
HIRC (12/16 MHz OSC)
LXT (32 kHz XTL)
ON/OFF1
ON/OFF2
Halt
LIRC (10 kHz OSC)
PLL
LDO
ON
CPU
Halt
HCLK/PCLK
SRAM retention
FLASH
EBI
Halt
ON
Halt
Halt
GPIO
Halt
PDMA
TIMER
PWM
Halt
ON/OFF3
ON/OFF4
ON/OFF5
Halt
WDT
WWDT
RTC
ON/OFF6
Halt
UART
SC
Halt
PS/2
Halt
I2C
Halt
SPI
Halt
I2S
Halt
USB
Halt
ADC
Halt
ACMP
Halt
Table 6-3 Clocks in Power Modes
Wake-up sources in Power-down mode:
WDT, I²C, Timer, RTC, UART, BOD, GPIO and USB
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After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Wake-Up
Source
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
BOD
GPIO
TIMER
WDT
Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]).
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the ISRC[n] bit.
After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]).
After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect).
After software writes 1 to clear AIF (RIIR[0]).
WDT Interrupt
RTC
Alarm Interrupt
Time Tick Interrupt
nCTS wake-up
After software writes 1 to clear TIF (RIIR[1]).
UART
I2C
After software writes 1 to clear DCTSF (UA_MSR[0]).
After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]).
After software writes 1 to clear BUS_STS (USBD_INTSTS[0]).
Addressing I2C device
Remote Wake-up
USB
*User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-down mode.
Table 6-4*User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-
down mode.
Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear BOD_INTF (BODCR[4]).
GPIO
TIMER
WDT
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the ISRC[n] bit.
After software writes 1 to clear TWF (TISRx[1]) and TIF (TISRx[0]).
After software writes 1 to clear WTWKF (WTCR[5]) (Write Protect).
After software writes 1 to clear AIF (RIIR[0]).
WDT Interrupt
RTC
Alarm Interrupt
Time Tick Interrupt
nCTS wake-up
After software writes 1 to clear TIF (RIIR[1]).
UART
I2C
After software writes 1 to clear DCTSF (UA_MSR[0]).
After software writes 1 to clear WKUPIF (I2CWKUPSTS[0]).
After software writes 1 to clear BUS_STS (USBD_INTSTS[0]).
Addressing I2C device
Remote Wake-up
USB
*User needs to wait this condition before setting PWR_DOWN_EN (PWRCON[7]) and execute WFI to enter Power-down mode.
Table 6-4 Condition of Entering Power-down Mode Again
6.2.4
System Power Distribution
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
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USB transceiver power from VBUS offers the power for operating the USB transceiver.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level of the digital power (VDD). Figure 6-8 shows the power distribution of NuMicro®
NUC100. Figure 6-9 shows the power distribution of NuMicro® NUC120.
NUC100 Power Distribution
Brown
Out
Detector
Low
Voltage
Reset
AVDD
AVSS
12-bit
SAR-ADC
Analog
Comparator
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO
1uF
1.8V
POR18
POR50
External
32.768 kHz
Crystal
PLL
LDO
IO cell
GPIO
Figure 6-8 NuMicro® NUC100 Power Distribution Diagram
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AVDD
AVSS
D+
D-
12-bit
SAR-ADC
USB 1.1
Tranceiver
NUC120
Power
Distribution
Analog Comparator
VDD33
1uF
3.3V
Low
Voltage
Reset
Brown
Out
Detector
5V to 3.3V LDO
VBUS
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO
1uF
1.8V
POR18
POR50
External
32.768 kHz
Crystal
PLL
LDO
IO cell
GPIO
Figure 6-9 NuMicro® NUC120 Power Distribution Diagram
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6.2.5
System Memory Map
The NuMicro® NUC100 series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register
definition, memory space, and programming detailed will be described in the following sections for
each on-chip peripheral. The NuMicro® NUC100 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128 KB)
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
0x5000_C000 – 0x5000_FFFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
FMC_BA
Peripheral DMA Control Registers
Flash Memory Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_FFFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
TMR01_BA
I2C0_BA
I2C0 Interface Control Registers
SPI0_BA
SPI1_BA
PWMA_BA
UART0_BA
USBD_BA
ACMP_BA
ADC_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
UART0 Control Registers
USB 2.0 FS device Controller Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4010_0000 – 0x4010_3FFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4013_0000 – 0x4013_3FFF
0x4013_4000 – 0x4013_7FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
PS2_BA
PS/2 Interface Control Registers
TMR23_BA
I2C1_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
SPI2_BA
SPI3_BA
PWMB_BA
UART1_BA
SPI2 with master/slave function Control Registers
SPI3 with master/slave function Control Registers
PWM4/5/6/7 Control Registers
UART1 Control Registers
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0x4015_4000 – 0x4015_7FFF
0x4019_0000 – 0x4019_3FFF
0x4019_4000 – 0x4019_7FFF
0x4019_8000 – 0x4019_BFFF
0x401A_0000 – 0x401A_3FFF
UART2_BA
SC0_BA
SC1_BA
SC2_BA
I2S_BA
UART2 Control Registers
SC0 Control Registers
SC1 Control Registers
SC2 Control Registers
I2S Interface Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6-5 Address Space Assignments for On-Chip Controllers
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6.2.6
System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.7
Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex® -M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to
leave Power-down mode. In the Power-down mode, the clock controller turns off the external
4~24 MHz high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the
overall system power consumption.
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22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
4~24
MHz
EBI
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PDMA
32.768
kHz
ACMP
PCLK
I2C 0~1
22.1184 MHz
10 kHz
111
101
011
010
001
000
10 kHz
CLKSEL0[2:0]
TMR 3
TMR 2
TMR 1
TMR 0
External trigger
HCLK
22.1184 MHz
4~24 MHz
1
PLLFOUT
32.768 kHz
4~24 MHz
0
PLLCON[19]
22.1184 MHz
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
FMC
CPUCLK
22.1184 MHz
HCLK
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
SYST_CSR[2]
4~24 MHz
32.768 kHz
4~24 MHz
10 kHz
111
22.1184 MHz
011
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
HCLK
010
32.768 kHz
001
CLKSEL0[5:3]
4~24 MHz
000
CLKSEL2[17:16]
10 kHz
22.1184 MHz
11
10
01
00
11
10
HCLK
WWDT
CLKSEL2[11:4]
CLKSEL1[31:28]
PLLFOUT
4~24 MHz
10 kHz
11
10
01
HCLK
1/2048
WDT
PS2
I2S
32.768 kHz
CLKSEL2[1:0]
22.1184 MHz
CLKSEL1[1:0]
22.1184 MHz
PLLFOUT
11
01
00
CPUCLK
1
0
4~24 MHz
SPI0-3
CLKSEL1[25:24]
SYST_CSR[2]
1/(UART_N+1)
1/(ADC_N+1)
UART 0-2
22.1184 MHz
HCLK
11
10
01
00
ADC
BOD
FDIV
PLLFOUT
4~24 MHz
22.1184 MHz
HCLK
10 kHz
11
10
01
00
32.768 kHz
4~24 MHz
CLKSEL1[3:2]
32.768 kHz
22.1184 MHz
HCLK
RTC
11
10
01
00
CLKSEL2[3:2]
1/(SC2_N+1)
SC 2
SC 1
SC 0
PLLFOUT
4~24 MHz
1/(SC1_N+1)
1/(SC0_N+1)
CLKSEL3[5:4]
CLKSEL3[3:2]
CLKSEL3[1:0]
PLLFOUT
1/(USB_N+1)
USB
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-10 Clock Generator Global View Diagram
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6.3.2
Clock Generator
The clock generator consists of 5 clock sources as listed below:
One external 32.768 kHz low speed crystal
One external 4~24 MHz high speed crystal
One programmable PLL FOUT (PLL source consists of external 4~24 MHz high
speed crystal and internal 22.1184 MHz high speed oscillator)
One internal 22.1184 MHz high speed oscillator
One internal 10 kHz low speed oscillator
XTL32K_EN (PWRCON[1])
X32I
External
32.768 kHz
32.768 kHz
Crystal
X32O
XTL12M_EN (PWRCON[0])
4~24 MHz
XT_IN
External
4~24 MHz
PLL_SRC (PLLCON[19])
Crystal
XT_OUT
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
Internal
22.1184 MHz
Oscillator
22.1184 MHz
10 kHz
OSC10K_EN(PWRCON[3])
Internal
10 kHz
Oscillator
Figure 6-11 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-12.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011
010
001
000
CPUCLK
HCLK
CPU
AHB
APB
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PCLK
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-12 System Clock Block Diagram
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-13.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-13 SysTick Clock Control Block Diagram
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6.3.4
Peripherals Clock
The peripherals clock can be selected as different clock source depends on the clock source
select control registers (CLKSEL1, CLKSEL2 and CLKSEL3).
6.3.5
Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
Internal 10 kHz low speed oscillator clock
External 32.768 kHz low speed crystal clock
Peripherals Clock (when IP adopt external 32.768 kHz low speed crystal oscillator or
10 kHz low speed oscillator as clock source)
6.3.6
Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
22.1184 MHz
11
FRQDIV_CLK
HCLK
10
01
00
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 6-14 Clock Source of Frequency Divider
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DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
16 chained
divide-by-2 counter
FRQDIV_CLK
1/22 1/23
1/215 1/216
…...
1/2
0000
0001
CLKO
16 to 1
MUX
:
:
1110
1111
FSEL
(FRQDIV[3:0])
Figure 6-15 Frequency Divider Block Diagram
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6.4 FLASH MEMORY CONTROLLER (FMC)
6.4.1 Overview
The NuMicro® NUC100 series has 128/64/32 Kbytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-System-
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex® -M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in Config0. By the way, the NuMicro® NUC100 series also provides
additional DATA Flash for user to store some application dependent data. For 128 Kbytes
APROM device, the Data Flash is shared with original 128K program memory and its start
address is configurable in Config1. For 64/32 Kbytes APROM device, the Data Flash is fixed at
4K.
6.4.2
Features
Runs up to 50 MHz with zero wait state for continuous address read access
All embedded flash memory supports 512 bytes page erase
128/64/32 KB application program memory (APROM)
4 KB In-System-Programming (ISP) loader program memory (LDROM)
4KB Data Flash for 64/32 KB APROM device
Configurable Data Flash size for 128KB APROM device
Configurable or fixed 4 KB Data Flash with 512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
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6.5 External Bus Interface (EBI)
6.5.1 Overview
The NuMicro® NUC100 series LQFP-64 and LQFP-100 package is equipped with an external bus
interface (EBI) for accessing an external device.
To save the connections between external device and this chip, EBI supports address bus and
data bus multiplex mode. And, address latch enable (ALE) signal is used to differentiate the
address and data cycle.
6.5.2
Features
External Bus Interface has the following functions:
Supports external devices with max. 64 KB size (8-bit data width)/128 KB (16-bit data
width)
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Supports address bus and data bus multiplex mode to save the address pins
Supports configurable idle cycle for different access condition: Write command finish
(W2X), Read-to-Read (R2R)
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6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NuMicro® NUC100 series has up to 84 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named
as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the
maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 84 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V.
6.6.2
Features
Four I/O modes:
–
–
–
–
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
–
–
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
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6.7 PDMA Controller (PDMA)
6.7.1 Overview
The NuMicro® NUC100 series DMA contains nine-channel peripheral direct memory access
(PDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA
PDMA_CSRx[PDMACEN]. The CPU can recognize the completion of a PDMA operation by
software polling or when it receives an internal PDMA interrupt. The PDMA controller can
increase source or destination address or fixed them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and DMA transfer mode.
6.7.2
Features
Supports nine PDMA channels and one CRC channel. Each PDMA channel can support
a unidirectional transfer
AMBA AHB master/slave interface compatible, for data transfer and register read/write
Hardware round robin priority scheme. DMA channel 0 has the highest priority and
channel 8 has the lowest priority
PDMA operation
– Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
– Supports word/half-word/byte transfer data width from/to peripheral
– Supports address direction: increment, fixed.
Cyclic Redundancy Check (CRC)
– Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
– Supports programmable CRC seed value.
– Supports programmable order reverse setting for input data and CRC checksum.
– Supports programmable 1’s complement setting for input data and CRC checksum.
– Supports CPU PIO mode or DMA transfer mode.
– Supports the follows write data length in CPU PIO mode
8-bit write mode (byte): 1-AHB clock cycle operation.
16-bit write mode (half-word): 2-AHB clock cycle operation.
32-bit write mode (word): 4-AHB clock cycle operation.
– Supports byte alignment transfer data length and word alignment transfer source
address in CRC DMA mode.
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6.8 Timer Controller (TMR)
6.8.1 Overview
The timer controller includes four 32-bit timers, TIMER0~TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, event counting, interval measurement, clock generation, and delay timing. The
timer can generate an interrupt signal upon time-out, or provide the current value during
operation.
6.8.2
Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external pin
Supports external pin capture function for interval measurement
Supports external pin capture function for reset timer counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
(TIF set to 1)
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6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The NuMicro® NUC100 series has 2 sets of PWM groups supporting a total of 4 sets of PWM
generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6,
PWM7) with 4 programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-
shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
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So the maximum capture frequency will be 1/900ns = 1000 kHz
6.9.2
Features
6.9.2.1 PWM Function:
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4
complementary PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting one
8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator and two
PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Edge-aligned type or Center-aligned type option
6.9.2.2 Capture Function:
Timing control logic shared with PWM Generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) and the time-out interval is 104 ms ~ 26.3168 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period, it includes (1024+2)、(128+2) 、
(16+2) or (1+2) WDT_CLK reset delay period.
Supports force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(Config0[31] watchdog enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function when WDT clock source is selected to
10 kHz low speed oscillator.
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6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter (WWDTVAL[5:0]) and 6-bit compare value (WWDTCR[21:16] – WINCMP
value) to make the window period flexible
Selectable maximum 11-bit WWDT clock prescale (WWDTCR[11:8] – PERIODSEL value) to
make WWDT time-out interval variable
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6.13 Real Time Clock (RTC)
6.13.1 Overview
The Real Time Clock (RTC) controller provides user with the real time and calendar message.
The clock source of RTC controller is from an external 32.768 kHz low speed crystal which
connected at pins X32I and X32O (refer to pin Description) or from an external 32.768 kHz low
speed oscillator output fed at pin X32I. The RTC controller provides the real time message (hour,
minute, second) in TLR (RTC Time Loading Register) as well as calendar message (year, month,
day) in CLR (RTC Calendar Loading Register). It also offers RTC alarm function that user can
preset the alarm time in TAR (RTC Time Alarm Register) and alarm calendar in CAR (RTC
Calendar Alarm Register). The data format of RTC time and calendar message are all expressed
in BCD format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic
RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1
second which are selected by TTR (TTR[2:0] Time Tick Register). When real time and calendar
message in TLR and CLR are equal to alarm time and calendar settings in TAR and CAR, the AIF
(RIIR [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC alarm interrupt signal is generated if
the AIER (RIER [0] Alarm Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or
Power-down mode if the correlate interrupt enable bit (AIER or TIER) is set to 1 before chip
enters Idle or Power-down mode.
6.13.2 Features
Supports real time counter in TLR (hour, minute, second) and calendar counter in CLR (year,
month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in TAR
and CAR
Selectable 12-hour or 24-hour time scale in TSSR register
Supports Leap Year indication in LIR register
Supports Day of the Week counter in DWR register
Frequency of RTC clock source compensate by FCR register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
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6.14 UART Interface Controller (UART)
The NuMicro® NUC100 series provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART. Besides, only UART0 and UART1 support the flow control function.
6.14.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR, LIN master/slave mode
and RS-485 mode functions. Each UART channel supports seven types of interrupts including:
Transmitter FIFO empty interrupt (INT_THRE)
Receiver threshold level reached interrupt (INT_RDA),
Line status interrupt (parity error or frame error or break interrupt) (INT_RLS),
Receiver buffer time-out interrupt (INT_TOUT),
MODEM/Wake-up status interrupt (INT_MODEM),
Buffer error interrupt (INT_BUF_ERR)
LIN interrupt (INT_LIN)
Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt
number 13 (vector number is 29) only supports UART1 interrupt. Refer to the Nested Vectored
Interrupt Controller chapter for System Interrupt Map.
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU. The UART1~2 are
equipped with 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The
CPU can read the status of the UART at any time during the operation. The reported status
information includes the type and condition of the transfer operations being performed by the
UART, as well as 4 error conditions (parity error, frame error, break interrupt and buffer error)
probably occur while receiving data. The UART includes a programmable baud rate generator
that is capable of dividing clock input by divisors to produce the serial clock that transmitter and
receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and
BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 6-6 lists the equations in the
various conditions and Table 6-7 lists the UART baud rate setting table.
Mode
DIV_X_EN
DIV_X_ONE
Divider X
Don’t care
B
BRD Baud Rate Equation
0
1
2
0
1
1
0
0
1
A
A
A
UART_CLK / [16 * (A+2)]
UART_CLK / [(B+1) * (A+2)] , B must >= 8
UART_CLK / (A+2), A must >=3
Don’t care
Table 6-6 UART Baud Rate Equation
System Clock = Internal 22.1184 MHz High Speed Oscillator
Mode 0
Register
Mode 1
Register
0x2B00_0000
Mode 2
Register
0x3000_0016
Baud Rate
Parameter
Parameter
Parameter
921600
x
x
A=0,B=11
A=22
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0x2F00_0001
0x2B00_0002
A=1,B=15
A=2,B=11
460800
230400
A=1
A=4
0x0000_0001
0x0000_0004
A=46
A=94
0x3000_002E
0x3000_005E
0x2F00_0004
0x2B00_0006
A=4,B=15
A=6,B=11
0x2F00_000A
0x2B00_000E
A=10,B=15
A=14,B=11
115200
57600
A=10
A=22
0x0000_000A
0x0000_0016
A=190
A=382
0x3000_00BE
0x3000_017E
A=22,B=15
A=30,B=11
0x2F00_0016
0x2B00_001E
A=62,B=8
A=46,B=11
A=34,B=15
0x2800_003E
0x2B00_002E
0x2F00_0022
38400
19200
A=34
A=70
0x0000_0022
0x0000_0046
A=574
0x3000_023E
0x3000_047E
A=126,B=8
A=94,B=11
A=70,B=15
0x2800_007E
0x2B00_005E
0x2F00_0046
A=1150
0x2800_00FE
0x2B00_00BE
0x2F00_008E
A=254,B=8
A=190,B=11
A=142,B=15
9600
4800
A=142
A=286
0x0000_008E
0x0000_011E
A=2302
A=4606
0x3000_08FE
0x3000_11FE
0x2800_01FE
0x2B00_017E
0x2F00_011E
A=510,B=8
A=382,B=11
A=286,B=15
Table 6-7 UART Baud Rate Setting Table
The UART0 and UART1 controllers support the auto-flow control function that uses two low-level
signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer
between the chip and external devices (e.g. Modem). When auto-flow is enabled, the UART is not
allowed to receive data until the UART asserts /RTS to external device. When the number of
bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is de-
asserted. The UART sends data out when UART controller detects /CTS is asserted from external
device. If a valid asserted /CTS is not detected the UART controller will not send data out.
UART Mode : MCR[LEV_RTS] = 1
MCR [RTS]
MCR [RTS_ST]
UART Mode : MCR[LEV_RTS] = 0
MCR [RTS]
MCR [RTS_ST]
Figure 6-16 UART nRTS Auto-Flow Control Trigger Level
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range
infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. The
maximum data rate supports up to 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA
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SIR Protocol encoder/decoder. The IrDA SIR Protocol encoder/decoder is half-duplex only. So it
cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a
minimum 10ms transfer delay between transmission and reception, and this delay feature must
be implemented by software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN
mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, 1 start bit and 8 data bits
format with 1 stop bit are required in accordance with the LIN standard.
For NuMicro® NUC100 series, another alternate function of UART controllers is RS-485 9-bit
mode, and direction control provided by /RTS pin or can program GPIO (PB.2 for UART0_nRTS
and PB.6 for UART1_nRTS) to implement the function by software. The RS-485 mode is selected
by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 transceiver control is
implemented using the /RTS control signal from an asynchronous serial port to enable the RS-
485 transceiver. In RS-485 mode, many characteristics of the receiving and transmitting are same
as UART.
6.14.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data
payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function (UART0 and UART1 support)
Supports 7-bit receiver buffer time-out detection function
UART0/UART1 can through DMA channels to receive/transmit data
Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
–
–
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
–
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
–
–
–
–
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode.
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–
–
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by RTS pin
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6.15 Smart Card Host Interface (SC)
6.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.15.2 Features
ISO7816-3 T=0, T=1 compliant
EMV2000 compliant
Supports up to three ISO7816-3 ports
Separates receive/ transmit 4 byte entry buffer for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error retry number limitation function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
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6.16 PS/2 Device Controller (PS2D)
6.16.1 Overview
The PS/2 device controller provides a basic timing control for PS/2 communication. All
communication between the device and the host is managed through the CLK and DATA pins.
Unlike PS/2 keyboard or mouse device controller, the receive/transmit code needs to be
translated as meaningful code by firmware. The device controller generates the CLK signal after
receiving a “Request to Send” state, but host has ultimate control over communication. Data of
DATA line sent from the host to the device is read on the rising edge and sent from the device to
the host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention.
Software can select 1 to 16 bytes for a continuous transmission.
6.16.2 Features
Host communication inhibit and Request to Send state detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
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6.17 I2C Serial Interface Controller (I2C)
6.17.1 Overview
I2C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines
are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock
pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each
transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may
be changed only during the low period of SCL and must be held stable during the high period of
SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 6-17 for more detailed I2C BUS Timing.
Repeated
START
STOP START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
Figure 6-17 I2C Bus Timing
The device’s on-chip I2C logic provides a serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1
in I2CON should be set to '1'. The I2C hardware interfaces to the I2C bus via two pins: SDA and
SCL. Pull-up resistor is needed for I2C operation as the SDA and SCL are open drain pins. When
I/O pins are used as I2C ports, user must set the pins function to I2C in advance.
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6.17.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus include:
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
A built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows
External pull-up resistors needed for high output
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
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6.18 Serial Peripheral Interface (SPI)
6.18.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® NUC100 series contains up to four sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable serial clock function for special applications and 2-bit
Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports
the PDMA function to access the data buffer and also supports Dual I/O Transfer mode.
6.18.2 Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Two slave select lines in Master mode
Supports the byte reorder function
Supports Byte or Word Suspend mode
Variable output serial clock frequency in Master mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
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6.19 I2S Controller (I2S)
6.19.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word
deep FIFO for read path and write path respectively and is capable of handling 8-, 16-, 24- and
32-bit word sizes. PDMA controller handles the data movement between FIFO and memory.
6.19.2 Features
Operated as either Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Two PDMA requests, one for transmitting and the other for receiving
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6.20 USB Device Controller (USB)
6.20.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1
6.20.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature list of this USB.
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
Mar. 21, 2019
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6.21 Analog-to-Digital Converter (ADC)
6.21.1 Overview
The NuMicro® NUC100 series contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM Center-aligned trigger and external STADC pin.
6.21.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 8 single-end analog input channels or 4 differential analog input channels
Up to 760 kSPS conversion rate as ADC clock frequency is 16 MHz (chip working at 5V)
Three operating modes
–Single mode: A/D conversion is performed one time on a specified channel
–Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
–Continuous scan mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion
An A/D conversion can be started by:
–Writing 1 to ADST bit through software
–PWM Center-aligned trigger
–External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators
Conversion result can be compared with specify value and user can select whether to
generate an interrupt when conversion result matches the compare register setting
Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage,
and internal temperature sensor output
Mar. 21, 2019
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6.22 Analog Comparator (ACMP)
6.22.1 Overview
The NuMicro® NUC100 series contains two comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input voltage is greater
than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to
cause an interrupt when the comparator output value changes.
6.22.2 Features
Analog input voltage range: 0~ VDDA
Supports Hysteresis function
Supports optional internal reference voltage input at negative end for each comparator
Mar. 21, 2019
Page 88 of 107
Rev 1.03
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7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
SPISS00
SPICLK0
MISO00
AVDD
CS
CLK
MISO
MOSI
VDD
SPI Device
FB
DVCC
VDD
VSS
Power
MOSI00
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
FB
AVSS
4.7K
CLK
DIO
I2C0SCL
I2C0SDA
VDD
I2C Device
VDD
VSS
ICE_CLK
ICE_DAT
SWD
Interface
/RESET
VSS
Smart Card
VCC
20p
20p
USB PORT
XT1_IN
NUC1xx
Series
VBUS
D+
33
33
Crystal
4~24 MHz
crystal
D-
XT1_OUT
VSS
DVCC
10K
Reset
Circuit
/RESET
10uF/25V
PC COM Port
RS232 Transceiver
ROUT RIN
RXD
TXD
UART
TIN
TOUT
LDO
1uF
LDO
Note: For the SPI device, the chip supply voltage
must be equal to SPI device working voltage. For
example, when the SPI Flash working voltage is
3.3 V, the NUC1xx chip supply voltage must also
be 3.3V.
Mar. 21, 2019
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8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
VDDVSS
VIN
MIN.
-0.3
VSS-0.3
4
MAX
UNIT
V
DC Power Supply
+7.0
VDD+0.3
24
Input Voltage
V
Oscillator Frequency
Operating Temperature
1/tCLCL
TA
MHz
C
-40
+85
+150
120
120
35
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
Mar. 21, 2019
Page 90 of 107
Rev 1.03
NUC100/120xxxDN
8.2 DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Operation Voltage
VDD
2.5
5.5
V
V
V
VDD = 2.5V ~ 5.5V up to 50 MHz
VSS
Power Ground
-0.3
AVSS
LDO Output Voltage
VLDO
1.62
1.8
1.98
VDD > 2.5V
When system used analog
function, please refer to chapter 8.4
for corresponding analog operating
voltage
Analog Operating Voltage
AVDD
VDD
V
VDD
XTAL
PLL
V
All IP
IDD1
34
mA
5.5V 12 MHz
5.5V 12 MHz
3.3V 12 MHz
3.3V 12 MHz
V
X
Operating Current
Normal Run Mode
at 50 MHz
IDD2
IDD3
IDD4
15
32
14
mA
mA
mA
V
V
V
V
X
VDD
XTAL
PLL
X
All IP
V
IDD5
8.5
mA
5.5V 12 MHz
5.5V 12 MHz
3.3V 12 MHz
3.3V 12 MHz
Operating Current
Normal Run Mode
at 12 MHz
IDD6
IDD7
IDD8
3.6
7.5
2.6
mA
mA
mA
X
X
X
V
X
X
VDD
5.5V
5.5V
3.3V
3.3V
VDD
XTAL
4 MHz
4 MHz
4 MHz
4 MHz
XTAL
PLL
X
All IP
V
IDD9
3.6
mA
Operating Current
Normal Run Mode
at 4 MHz
IDD10
IDD11
IDD12
2
mA
mA
mA
X
X
2.8
1.2
X
V
X
X
PLL
All IP
IDD13
141
A
32.768
kHz
5.5V
5.5V
3.3V
X
X
X
V
X
V
Operating Current
Normal Run Mode
at 32.768 kHz
32.768
kHz
IDD14
129
138
A
A
32.768
kHz
IDD15
Mar. 21, 2019
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Rev 1.03
NUC100/120xxxDN
SPECIFICATION
PARAMETER
SYM.
IDD16
IDD17
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
32.768
kHz
125
3.3V
VDD
X
X
A
A
LIRC
PLL
X
All IP
125
5.5V 10 kHz
5.5V 10 kHz
3.3V 10 kHz
3.3V 10 kHz
V
X
Operating Current
Normal Run Mode
at 10 kHz
IDD18
IDD19
IDD20
120
125
120
X
A
A
A
X
V
X
X
VDD
XTAL
PLL
V
All IP
V
IIDLE1
28
mA
5.5V 12 MHz
5.5V 12 MHz
3.3V 12 MHz
3.3V 12 MHz
Operating Current
Idle Mode
IIDLE2
IIDLE3
IIDLE4
10
27
9
mA
mA
mA
V
X
at 50 MHz
V
V
V
X
VDD
XTAL
PLL
X
All IP
V
IIDLE5
7.5
mA
5.5V 12 MHz
5.5V 12 MHz
3.3V 12 MHz
Operating Current
Idle Mode
IIDLE6
IIDLE7
IIDLE8
2.4
6.5
1.5
mA
mA
mA
X
X
at 12 MHz
X
V
3.3V 12 MHz
X
X
VDD
5.5V
5.5V
3.3V
XTAL
4 MHz
4 MHz
4 MHz
PLL
X
All IP
IIDLE9
3.3
mA
V
X
V
Operating Current
Idle Mode
IIDLE10
IIDLE11
IIDLE12
1.7
2.4
0.8
mA
mA
mA
X
at 4 MHz
X
3.3V
VDD
4 MHz
XTAL
X
X
PLL
All IP
IIDLE13
133
A
32.768
kHz
5.5V
5.5V
3.3V
X
X
X
V
X
V
Operating Current
Idle Mode
32.768
kHz
IIDLE14
120
133
A
A
at 32.768 kHz
32.768
kHz
IIDLE15
32.768
kHz
IIDLE16
IIDLE13
120
122
3.3V
VDD
X
X
A
A
Operating Current
LIRC
PLL
All IP
Mar. 21, 2019
Page 92 of 107
Rev 1.03
NUC100/120xxxDN
SPECIFICATION
PARAMETER
Idle Mode
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
5.5V 10 kHz
X
V
X
V
at 10 kHz
IIDLE14
IIDLE15
IIDLE16
118
122
118
5.5V 10 kHz
3.3V 10 kHz
3.3V 10 kHz
X
X
X
A
A
A
X
VDD
5.5V
5.5V
3.3V
3.3V
RTC
X
BOD function
IPWD1
15
A
X
X
X
X
Standby Current
Power-down Mode
(Deep Sleep Mode)
IPWD2
IPWD3
IPWD4
15
17
17
X
A
A
A
X
X
Input Current PA, PB, PC,
PD, PE, PF (Quasi-
bidirectional mode)
VDD = 5.5V, VIN = 0V or VIN=VDD
IIN1
-50
-60
A
Input Current at /RESET[1]
VDD = 3.3V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
IIN2
ILK
-55
-2
-45
-
-30
+2
A
A
Input Leakage Current PA,
PB, PC, PD, PE, PF
Logic 1 to 0 Transition Current
PA~PF (Quasi-bidirectional
mode)
[3]
VDD = 5.5V, VIN<2.0V
ITL
-650
-
-200
A
VDD = 4.5V
VDD = 2.5V
-0.3
-0.3
-
-
0.8
0.6
Input Low Voltage PA, PB,
PC, PD, PE, PF (TTL input)
VIL1
V
VDD
+0.2
VDD = 5.5V
VDD =3.0V
2.0
1.5
-
-
Input High Voltage PA, PB,
PC, PD, PE, PF (TTL input)
VIH1
V
VDD
+0.2
Input Low Voltage PA, PB,
PC, PD, PE, PF (Schmitt
input)
VIL2
VIH2
VHY
VIL3
-0.3
-
-
0.3VDD
V
V
V
Input High Voltage PA, PB,
PC, PD, PE, PF (Schmitt
input)
VDD
+0.2
0.7VDD
Hysteresis voltage of PA, PB,
PC, PD,PE, PF (Schmitt
input)
0.2VDD
VDD = 4.5V
VDD = 3.0V
0
0
-
-
0.8
0.4
Input Low Voltage XT1_IN[*2]
V
V
VDD
+0.2
VDD = 5.5V
VDD = 3.0V
3.5
2.4
-
-
Input High Voltage XT1_IN[*2]
VIH3
VDD
+0.2
Mar. 21, 2019
Page 93 of 107
Rev 1.03
NUC100/120xxxDN
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Input Low Voltage X32I[*2]
Input High Voltage X32I[*2]
VIL4
VIH4
0
-
0.4
1.8
v
1.2
V
Negative going threshold
(Schmitt input), /RESET
0.2VDD
-0.2
VILS
-0.5
-
-
V
V
Positive going threshold
(Schmitt input), /RESET
VDD
+0.5
VIHS 0.7VDD
VDD = 4.5V, VS = 2.4V
ISR11
ISR12
ISR12
ISR21
ISR22
ISR22
ISK1
-300
-50
-40
-24
-4
-370
-70
-60
-28
-6
-450
-90
-80
-32
-8
A
A
Source Current PA, PB, PC,
PD, PE, PF (Quasi-
bidirectional Mode)
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
VDD = 4.5V, VS = 0.45V
VDD = 2.7V, VS = 0.45V
VDD = 2.5V, VS = 0.45V
A
mA
mA
mA
mA
mA
mA
Source Current PA, PB, PC,
PD, PE, PF (Push-pull Mode)
-3
-5
-7
10
7
16
10
9
20
Sink Current PA, PB, PC, PD,
PE, PF (Quasi-bidirectional
and Push-pull Mode)
ISK1
13
ISK1
6
12
Brown-out Voltage with
BOD_VL [1:0] = 00b
VBO2.2
VBO2.7
VBO3.7
VBO4.4
2.1
2.6
3.5
4.2
2.2
2.7
3.7
4.4
2.3
2.8
3.9
4.6
V
V
V
V
Brown-out Voltage with
BOD_VL [1:0] = 01b
Brown-out voltage with
BOD_VL [1:0] = 10b
Brown-out Voltage with
BOD_VL [1:0] = 11b
Hysteresis range of BOD
voltage
VDD = 2.5V~5.5V
VBH
30
-
150
mV
Band-gap voltage
VDD = 2.5V - 5.5V
VBG
1.175
1.20
1.225
V
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from 1 to 0. In
the condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
Mar. 21, 2019
Page 94 of 107
Rev 1.03
NUC100/120xxxDN
8.3 AC Electrical Characteristics
8.3.1 External 4~24 MHz High Speed Oscillator
tCLCL
tCLCH
90%
10%
0.7 VDD
tCLCX
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
CONDITION
MIN.
TYP.
MAX. UNIT
10
10
2
-
-
-
-
-
nS
nS
nS
nS
tCLCX
Clock Low Time
Clock Rise Time
Clock Fall Time
-
tCLCH
15
15
tCHCL
2
8.3.2 External 4~24 MHz High Speed Crystal
PARAMETER
Operation Voltage VDD
Temperature
CONDITION
MIN.
2.5
-40
-
TYP..
MAX. UNIT
-
-
-
-
5.5
85
-
V
℃
Operating Current
Clock Frequency
12 MHz at VDD = 5V
External crystal
1
mA
MHz
4
24
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4 MHz ~ 24 MHz
10~20pF
10~20pF
without
Mar. 21, 2019
Page 95 of 107
Rev 1.03
NUC100/120xxxDN
XT1_OUT
XT1_IN
R
C1
C2
Figure 8-1 Typical Crystal Application Circuit
8.3.3 External 32.768 kHz Low Speed Crystal Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
TYP.
MAX. UNIT
-
-
-
-
5.5
85
V
℃
Operation Temperature
Operation Current
Clock Frequency
-40
32.768KHz at VDD=5V
External crystal
1.5
A
-
32.768
-
kHz
8.3.4 Internal 22.1184 MHz High Speed Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
-
TYP.
MAX. UNIT
-
-
5.5
V
MHz
%
Center Frequency
-
22.1184
-
-
+25℃; VDD =5 V
-1
+1
Calibrated Internal Oscillator Frequency
Operation Current
-40℃~+85℃;
-3
-
-
+3
-
%
VDD=2.5 V~5.5 V
VDD =5 V
500
uA
8.3.5 Internal 10 kHz Low Speed Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
-
TYP.
MAX. UNIT
-
-
10
-
5.5
-
V
kHz
%
Center Frequency
-
+25℃; VDD =5 V
Calibrated Internal Oscillator Frequency
-30
+30
Mar. 21, 2019
Page 96 of 107
Rev 1.03
NUC100/120xxxDN
-40℃~+85℃;
-50
-
+50
%
VDD=2.5 V~5.5 V
8.4 Analog Characteristics
8.4.1 12-bit SARADC Specification
SYMBOL
-
PARAMETER
MIN.
TYP.
MAX. UNIT
Resolution
-
-
-
-
-
-
12
-1~4
±4
Bit
LSB
LSB
LSB
-
DNL
INL
EO
Differential nonlinearity error
Integral nonlinearity error
Offset error
-1~2
±2
±1
10
EG
Gain error (Transfer gain)
Monotonic
1
1.005
-
Guaranteed
FADC
FS
ADC clock frequency (AVDD = 5V/3V)
Sample rate
-
-
-
-
16/8
760
5.5
-
MHz
kSPS
V
VDDA
IDD
Supply voltage
3
-
-
0.5
1.5
mA
mA
V
Supply current (Avg.)
IDDA
VREF
IREF
VIN
-
-
Reference voltage
Reference current (Avg.)
Input voltage
3
-
VDDA
-
1
-
mA
V
0
VREF
8.4.2 LDO and Power Management Specification
PARAMETER
Input Voltage VDD
MIN.
2.5
TYP.
MAX. UNIT
NOTE
VDD input voltage
VDD > 2.5 V
5.5
V
V
Output Voltage
1.62
1.8
1.98
℃
F
Operating Temperature
-40
-
25
1
85
-
Cbp
RESR = 1 Ω
Note:
1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between VDD and the
closest VSS pin of the device.
2. To ensure power stability, a 1 F must be connected between LDO_CAP pin and the closest VSS pin of the device.
Mar. 21, 2019
Page 97 of 107
Rev 1.03
NUC100/120xxxDN
8.4.3 Low Voltage Reset Specification
PARAMETER
Operation Voltage
CONDITION
MIN.
TYP.
MAX. UNIT
-
0
-
5.5
5
V
-
1
Quiescent Current
VDD=5.5 V
-
A
℃
Operation Temperature
-40
25
85
Temperature=-40~85℃
Threshold Voltage
Hysteresis
1.7
0
2.0
0
2.3
0
V
V
-
8.4.4 Brown-out Detector Specification
PARAMETER
Operation Voltage
Temperature
CONDITION
MIN.
0
TYP.
-
MAX. UNIT
-
5.5
85
V
℃
μA
V
-
-40
-
25
-
Quiescent Current
AVDD=5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
125
4.6
3.9
2.8
2.3
150
4.2
3.5
2.6
2.1
30
4.4
3.7
2.7
2.2
-
V
Brown-out Voltage
V
V
Hysteresis
mV
8.4.5 Power-on Reset Specification
PARAMETER
Operation Temperature
Reset Voltage
CONDITION
MIN.
TYP.
25
2
MAX. UNIT
℃
V
-
V+
-40
85
-
-
-
Quiescent Current
Vin > reset voltage
1
-
nA
Mar. 21, 2019
Page 98 of 107
Rev 1.03
NUC100/120xxxDN
8.4.6 Temperature Sensor Specification
PARAMETER
Operation Voltage[1]
Operation Temperature
Current Consumption
Gain
CONDITIONS
MIN.
2.5
TYP.
MAX. UNIT
-
-
5.5
85
V
℃
-40
6.4
-
10.5
μA
mV/℃
mV
-1.76
720
Temp=0 ℃
Offset Voltage
Note: Internal operation voltage comes from internal LDO.
8.4.7 Comparator Specification
PARAMETER
Operation Voltage AVDD
Operation Temperature
Operation Current
CONDITION
MIN.
2.5
-40
-
TYP.
MAX. UNIT
-
5.5
85
V
℃
μA
mV
V
-
25
20
5
VDD=3.0 V
40
Input Offset Voltage
Output Swing
-
-
-
-
-
15
0.1
0.1
-
-
VDD-0.1
VDD-0.1
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCM=1.2 V and
VDIFF=0.1 V
Propagation Delay
-
200
20
-
ns
20 mV at VCM=1 V
50 mV at VCM=0.1 V
50 mV at VCM=VDD-1.2
10 mV for non-hysteresis
Comparison Voltage
10
-
mV
Hysteresis
VCM=0.4 V ~ VDD-1.2 V
-
-
±10
-
-
mV
CINP=1.3 V
CINN=1.2 V
Stable Time
2
μs
Mar. 21, 2019
Page 99 of 107
Rev 1.03
NUC100/120xxxDN
8.4.8 USB PHY Specification
8.4.8.1 USB DC Electrical Characteristics
SYMBOL
VIH
PARAMETER
Input High (driven)
CONDITIONS
MIN.
TYP.
MAX. UNIT
2.0
V
VIL
VDI
Input Low
0.8
V
V
Differential Input Sensitivity
|PADP-PADM|
0.2
0.8
0.8
Differential
VCM
VSE
Includes VDI range
2.5
2.0
V
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
V
mV
V
200
VOL
Output Low (driven)
0
0.3
3.6
VOH
VCRS
RPU
Output High (driven)
2.8
V
Output Signal Cross Voltage
Pull-up Resistor
1.3
2.0
V
1.425
1.575
kΩ
Termination Voltage for Upstream
Port Pull-up (RPU)
VTRM
3.0
3.6
20
V
ZDRV
CIN
Driver Output Resistance
Transceiver Capacitance
Steady state drive*
Pin to GND
10
Ω
pF
*Driver output resistance doesn’t include series resistor resistance.
8.4.8.2 USB Full-Speed Driver Electrical Characteristics
SYMBOL
TFR
PARAMETER
CONDITIONS
CL=50p
MIN.
4
TYP.
MAX. UNIT
Rise Time
Fall Time
20
20
ns
ns
%
TFF
CL=50p
4
TFRFF
Rise and Fall Time Matching
TFRFF=TFR/TFF
90
111.11
8.4.8.3 USB Power Dissipation
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VBUS Current
(Steady State)
IVBUS
Standby
50
μA
Mar. 21, 2019
Page 100 of 107
Rev 1.03
NUC100/120xxxDN
8.4.8.4 USB LDO Specification
SYMBOL
VBUS
PARAMETER
CONDITIONS
MIN.
4.0
TYP.
MAX. UNIT
VBUS Pin Input Voltage
LDO Output Voltage
5.0
3.3
1.0
5.5
3.6
-
V
V
VDD33
Cbp
3.0
External Bypass Capacitor
uF
Mar. 21, 2019
Page 101 of 107
Rev 1.03
NUC100/120xxxDN
8.5 Flash DC Electrical Characteristics
SYMBOL
VDD
PARAMETER
Supply Voltage
CONDITIONS
MIN.
1.62
10
TYP.
MAX. UNIT
1.8
1.98
V[1]
year
ms
At 85℃
TRET
Data Retention
Page Erase Time
Mass Erase Time
Program Time
TERASE
TMER
2
10
20
ms
TPROG
μs
mA/MH
z
IDD1
Read Current
-
-
0.15
0.5
IDD2
IPD
Program/Erase Current
Power Down Current
7
mA
1
20
μA
1. VDD is source from chip LDO output voltage.
2. This table is guaranteed by design, not test in production.
Mar. 21, 2019
Page 102 of 107
Rev 1.03
NUC100/120xxxDN
9 PACKAGE DIMENSIONS
9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm)
H
D
D
A
A2
7
A1
51
7
50
H
E E
100
26
L1
L
1
25
c
e
b
Y
Controlling Dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
A
Min Nom
Max
Min Nom
Max
1.60
0.063
A1
A
b
0.002
0.05
1.45
0.27
0.053 0.055 0.057
1.35
0.17
0.10
1.40
0.22
0.011
0.008
0.009
0.006
0.007
0.004
0.547
0.547
c
0.15
0.20
D
E
14.00
0.551
0.551
0.020
14.10
13.90
13.90
0.556
0.556
14.00 14.10
0.50
e
H D
16.00
16.20
16.20
16.00
15.80
15.80
0.45
0.622
0.638
0.638
0.030
0.630
H E
L
0.622 0.630
0.60
1.00
0.75
0.024
0.039
0.018
L1
y
0.10
7
0.004
7
0
0
Mar. 21, 2019
Page 103 of 107
Rev 1.03
NUC100/120xxxDN
9.2 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm)
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.063
Max
1.60
A
0.002
1
0.05
0.15
1.45
0.27
0.20
0.006
A
2
0.053 0.055 0.057 1.35
1.40
0.20
A
0.007
0.004
0.17
0.09
0.008 0.011
0.008
b
c
10.00
10.00
0.50
0.393
D
E
e
H
E
H
0.393
0.020
D
12.00
12.00
0.60
0.472
0.472
0.030
7
0.024
0.039
0.75
7
0.45
0
0.018
0
L
L
y
1.00
1
0.10
3.5
0.004
3.5
0
Mar. 21, 2019
Page 104 of 107
Rev 1.03
NUC100/120xxxDN
9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Max
Min
Max Min
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.45
0.25
0.20
7.10
7.10
0.65
9.10
1.40
0.20
A
0.006
0.004
0.272
0.272
0.014
0.350
0.350
0.018
0.15
0.008 0.010
b
c
D
0.006
0.276
0.276
0.020
0.10 0.15
0.008
0.280
0.280
0.026
0.358
7.00
7.00
6.90
6.90
0.35
8.90
E
0.50
9.00
e
H
D
0.354
0.358
0.030
8.90
0.45
9.00
0.60
1.00
9.10
0.75
0.354
0.024
E
H
L
0.039
1
L
Y
0.004
7
0.10
7
0
0
0
Mar. 21, 2019
Page 105 of 107
Rev 1.03
NUC100/120xxxDN
10 REVISION HISTORY
Date
Revision
Description
1. Preliminary version.
Reorganized the chapter sequence.
2014.05.13
1.00
1.
2.
Added a note in all clock source block diagrams of all peripheral sections
that “Before clock switching, both the pre-selected and newly selected
clock sources must be turned on and stable.”
2015.08.31
1.01
3.
Revised package size of 64-pin LQFP (10x10x1.4 mm footprint 2.0 mm)
in section 9.2.
1.
2.
3.
Updated section 4.1 NuMicro® NUC100/120xxxDN Selection Guide.
Updated Low Voltage Reset Specification in section 8.4.3.
Updated Comparator Specification in section 8.4.7.
2017.03.02
2019.03.21
1.02
1.03
1.
Updated external capacitor value for LDO Specification note in section
8.4.7
Mar. 21, 2019
Page 106 of 107
Rev 1.03
NUC100/120xxxDN
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Mar. 21, 2019
Page 107 of 107
Rev 1.03
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