NUC7401-LD1C [NUVOTON]
Arm Cortex®-M0 32-bit Microcontroller;
| 型号： | NUC7401-LD1C |
| 厂家： | 
NUVOTON |
| 描述： | Arm Cortex®-M0 32-bit Microcontroller 微控制器 |
| 文件： | 总82页 (文件大小：1635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC2201
Arm Cortex® -M0
32-bit Microcontroller
NuMicro® Family
NUC2201 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Aug. 24, 2018
Page 1 of 82
Rev 1.00
NUC2201
TABLE OF CONTENTS
1 GENERAL DESCRIPTION.....................................................................................7
1.1 Key Features Support Table..................................................................... 7
2 FEATURES ............................................................................................................8
2.1 NuMicro® NUC2201 Features – USB Line .................................................... 8
3 ABBREVIATIONS ................................................................................................11
4 PARTS INFORMATION LIST AND PIN CONFIGURATION................................13
4.1 NuMicro® NUC2201xxxAE Selection Guide .................................................13
4.1.1 NuMicro® NUC2201 Naming Rule ..................................................................13
4.1.2 NuMicro® NUC2201 USB Line Selection Guide ..................................................14
4.2 Pin Configuration .................................................................................15
4.2.1 NuMicro® NUC2201 Pin Diagram ...................................................................15
4.3 Pin Description....................................................................................17
4.3.1 NuMicro® NUC2201 Pin Description................................................................17
5 BLOCK DIAGRAM...............................................................................................22
5.1 NuMicro® NUC2201 Block Diagram...........................................................22
6 FUNCTIONAL DESCRIPTION.............................................................................23
6.1 Arm® Cortex® -M0 Core ..........................................................................23
6.2 System Manager .................................................................................25
6.2.1 Overview ................................................................................................25
6.2.2 System Reset ..........................................................................................25
6.2.3 System Power Distribution ...........................................................................26
6.2.4 System Memory Map .................................................................................27
6.2.5 Register Lock...........................................................................................28
6.2.6 Auto Trim................................................................................................29
6.2.7 System Timer (SysTick) ..............................................................................31
6.2.8 Nested Vectored Interrupt Controller (NVIC)......................................................32
6.2.9 System Control.........................................................................................36
6.3 Clock Controller...................................................................................37
6.3.1 Overview ................................................................................................37
6.3.2 System Clock and SysTick Clock ...................................................................40
6.3.3 Power-down Mode Clock.............................................................................41
6.3.4 Frequency Divider Output ............................................................................41
6.4 Flash Memory Controller (FMC) ...............................................................43
6.4.1 Overview ................................................................................................43
Aug. 24, 2018
Page 2 of 82
Rev 1.00
NUC2201
6.4.2 Features.................................................................................................43
6.5 External Bus Interface (EBI)....................................................................44
6.5.1 Overview ................................................................................................44
6.5.2 Features.................................................................................................44
6.6 General Purpose I/O (GPIO) ...................................................................45
6.6.1 Overview ................................................................................................45
6.6.2 Features.................................................................................................45
6.7 PDMA Controller (PDMA).......................................................................46
6.7.1 Overview ................................................................................................46
6.7.2 Features.................................................................................................46
6.8 Timer Controller (TIMER) .......................................................................48
6.8.1 Overview ................................................................................................48
6.8.2 Features.................................................................................................48
6.9 PWM Generator and Capture Timer (PWM) .................................................49
6.9.1 Overview ................................................................................................49
6.9.2 Features.................................................................................................50
6.10Watchdog Timer (WDT) .........................................................................51
6.10.1 Overview ................................................................................................51
6.10.2 Features.................................................................................................51
6.11Window Watchdog Timer (WWDT)............................................................52
6.11.1 Overview ................................................................................................52
6.11.2 Features.................................................................................................52
6.12Real Time Clock (RTC)..........................................................................53
6.12.1 Overview ................................................................................................53
6.12.2 Features.................................................................................................53
6.13UART Interface Controller (UART) ............................................................54
6.13.1 Overview ................................................................................................54
6.13.2 Features.................................................................................................54
6.14I2C Serial Interface Controller (I2C)............................................................55
6.14.1 Overview ................................................................................................55
6.14.2 Features.................................................................................................55
6.15Serial Peripheral Interface (SPI) ...............................................................56
6.15.1 Overview ................................................................................................56
6.15.2 Features.................................................................................................56
6.16USB Device Controller (USBD) ................................................................57
Aug. 24, 2018
Page 3 of 82
Rev 1.00
NUC2201
6.16.1 Overview ................................................................................................57
6.16.2 Features.................................................................................................57
6.17Analog-to-Digital Converter (ADC) ............................................................58
6.17.1 Overview ................................................................................................58
6.17.2 Features.................................................................................................58
7 APPLICATION CIRCUIT......................................................................................59
8 ELECTRICAL CHARACTERISTICS....................................................................60
8.1 Absolute Maximum Ratings.....................................................................60
8.1.1 EMC characteristics ...................................................................................61
8.2 DC Electrical Characteristics ...................................................................62
8.3 AC Electrical Characteristics ...................................................................67
8.3.1 External 4~24 MHz High Speed Oscillator ........................................................67
8.3.2 External 4~24 MHz High Speed Crystal ...........................................................67
8.3.3 32.768 kHz External Low Speed Crystal Oscillator (LXT).......................................68
8.3.4 Internal 22.1184 MHz High Speed Oscillator .....................................................69
8.3.5 Internal 48 MHz High Speed Oscillator ............................................................69
8.3.6 Internal 10 kHz Low Speed Oscillator ..............................................................70
8.3.7 PLL characteristics ....................................................................................70
8.4 Analog Characteristics...........................................................................71
8.4.1 12-bit SARADC Specification........................................................................71
8.4.2 LDO and Power Management.......................................................................72
8.4.3 Low Voltage Reset Specification....................................................................73
8.4.4 Brown-out Detector Specification ...................................................................73
8.4.5 Power-on Reset Specification .......................................................................73
8.4.6 Temperature Sensor ..................................................................................74
8.4.7 USB PHY ...............................................................................................75
8.5 Flash DC Electrical Characteristics............................................................76
8.6 I2C Dynamic Characteristics....................................................................77
8.7 SPI Dynamic Characteristics ...................................................................78
9 PACKAGE DIMENSIONS ....................................................................................80
9.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................80
9.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................81
10REVISION HISTORY............................................................................................82
Aug. 24, 2018
Page 4 of 82
Rev 1.00
NUC2201
List of Figures
Figure 4-1 NuMicro® NUC2201 Series Selection Code................................................................. 13
Figure 4-2 NuMicro® NUC2201SxxAE LQFP 64-pin Diagram....................................................... 15
Figure 4-3 NuMicro® NUC2201LxxAE LQFP 48-pin Diagram ....................................................... 16
Figure 5-1 NuMicro® NUC2201 Block Diagram ............................................................................. 22
Figure 6-1 Functional Controller Diagram...................................................................................... 23
Figure 6-2 NuMicro® NUC2201 Power Distribution Diagram......................................................... 26
Figure 6-3 Clock Generator Block Diagram................................................................................... 38
Figure 6-4 Clock Generator Global View Diagram......................................................................... 39
Figure 6-5 System Clock Block Diagram ....................................................................................... 40
Figure 6-6 SysTick Clock Control Block Diagram.......................................................................... 40
Figure 6-7 Clock Source of Frequency Divider .............................................................................. 41
Figure 6-8 Frequency Divider Block Diagram ................................................................................ 42
Figure 8-1 Typical Crystal Application Circuit ................................................................................ 68
Figure 8.3-2 Typical Crystal Application Circuit ............................................................................. 69
Figure 8-3 Power-up Ramp Condition............................................................................................ 74
Figure 8-4 I2C Timing Diagram ...................................................................................................... 77
Figure 8-5 SPI Master Mode Timing Diagram ............................................................................... 78
Figure 8-6 SPI Slave Mode Timing Diagram ................................................................................. 79
Aug. 24, 2018
Page 5 of 82
Rev 1.00
NUC2201
List of Tables
Table 1.1-1 NuMicro® NUC2201 Series Connectivity Support Table .............................................. 7
Table 3-1 List of Abbreviations....................................................................................................... 12
Table 6-1 Address Space Assignments for On-Chip Controllers................................................... 28
Table 6-2 Exception Model ............................................................................................................ 33
Table 6-3 System Interrupt Map..................................................................................................... 34
Table 6-4 Vector Table Format ...................................................................................................... 35
Aug. 24, 2018
Page 6 of 82
Rev 1.00
NUC2201
1
GENERAL DESCRIPTION
The NuMicro® NUC2201 series 32-bit microcontrollers are embedded with the Arm® Cortex® -M0
core with a cost equivalent to traditional 8-bit MCU for industrial control and applications requiring
rich communication interfaces.
The NuMicro® NUC2201 USB Line with USB 2.0 full-speed functions is embedded with the
Cortex® -M0 core running up to 72 MHz and features 128K bytes flash, 16K bytes embedded
SRAM and 8 Kbytes loader ROM for the ISP. It is also equipped with plenty of peripheral devices,
such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation
unit, UART, SPI, I2C, PWM Timer, GPIO, LIN, USB 2.0 FS Device, 12-bit ADC, Low Voltage
Reset Controller and Brown-out Detector.
1.1 Key Features Support Table
Product Line
NUC2201L
NUC2201S
UART
SPI
I2C
2
Timer
PWM
ADC
10
USB
Package
LQFP48
LQFP64
2
3
1
4
4
4
6
1
1
2
2
12
Table 1.1-1 NuMicro® NUC2201 Series Connectivity Support Table
Aug. 24, 2018
Page 7 of 82
Rev 1.00
NUC2201
2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 NuMicro® NUC2201 Features – USB Line
Arm® Cortex® -M0 core
– Runs up to 72 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
– 128K bytes Flash for program code
– 8 KB flash for ISP loader
– Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for flash
– Configurable Data Flash address and size for 128 KB system
– Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
– 16K bytes embedded SRAM
– Supports PDMA mode
PDMA (Peripheral DMA)
– Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals
– Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and
CRC-32
Clock Control
– Flexible selection for different applications
– Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±3 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 48 MHz internal high speed RC oscillator (HIRC) for USB device operation
(Frequency variation < 2% at -40oC ~ +105oC)
Dynamically calibrating the HIRC OSC to 48 MHz ±0.25% from -40℃ to 105℃ by
external 32.768K crystal oscillator (LXT) or internal USB synchronous mode
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL, up to 72 MHz, for high performance system operation
– External 4~24 MHz high speed crystal input for USB and precise timing operation
– External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
– Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level setting
Timer
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
Aug. 24, 2018
Page 8 of 82
Rev 1.00
NUC2201
Watchdog Timer
– Multiple clock sources
– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
– Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK)
Window Watchdog Timer
– 6-bit down counter with 11-bit prescale for wide range window selected
RTC
– Supports software compensation by setting frequency compensate register (FCR)
– Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
– Supports Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4,
1/2 and 1 second
– Supports battery power pin (VBAT
– Supports wake-up function
PWM/Capture
)
– Up to three built-in 16-bit PWM generators providing six PWM outputs or three
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM
– Supports One-shot or Auto-reload mode
– Up to six 16-bit digital capture timers (shared with PWM timers) providing six rising/falling
capture inputs
– Supports Capture interrupt
UART
– Up to three UART controllers
– UART ports with flow control (TXD, RXD, nCTS and nRTS)
– UART0 with 64-byte FIFO is for high speed
– UART1/2(optional) with 16-byte FIFO for standard device
– Supports IrDA (SIR) and LIN function
– Supports RS-485 9-bit mode and direction control
– Programmable baud-rate generator up to 1/16 system clock
– Supports CTS wake-up function (UART0 and UART1 support)
– Supports PDMA mode
SPI
– Up to two sets of SPI controllers
– The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
– The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
– Supports SPI Master/Slave mode
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 8 to 32 bits
– MSB or LSB first data transfer
– Rx and Tx on both rising or falling edge of serial clock independently
– Two slave/device select lines in Master mode, and one slave/device select line in Slave
mode
– Supports Byte Suspend mode in 32-bit transmission
– Supports PDMA mode
– Supports three wire, no slave select signal, bi-direction interface
I2C
– Up to two sets of I2C devices
– Master/Slave mode
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master)
Aug. 24, 2018
Page 9 of 82
Rev 1.00
NUC2201
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
– Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
– Programmable clocks allowing for versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports wake-up function
USB 2.0 Full-Speed Device
– One set of USB 2.0 FS Device 12 Mbps
– On-chip USB Transceiver
– Provides 1 interrupt source with 4 interrupt events
– Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
– Auto suspend function when no bus signaling for 3 ms
– Provides 8 programmable endpoints
– Includes 512 Bytes internal SRAM as USB buffer
– Provides remote wake-up capability
– Supports Crystal-less function
ADC
– 12-bit SAR ADC with 1 MSPS(chip working at 5V)
– Up to 12-ch single-end input or 5-ch differential input
– Single scan/single cycle scan/continuous scan
– Each channel with individual result register
– Scan on enabled channels
– Threshold voltage detection
– Conversion started by software programming, external input or PWM Center-aligned trigger
– Supports PDMA mode
EBI (External bus interface)
– Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
– Supports 8-/16-bit data width
– Supports byte write in 16-bit data width mode
96-bit unique ID (UID)
128-bit unique customer ID(UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 105℃
Packages:
– All Green package (RoHS)
– LQFP 64-pin / 48-pin
Aug. 24, 2018
Page 10 of 82
Rev 1.00
NUC2201
3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
AES
APB
AHB
BOD
CAN
DAP
DES
EBI
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
IAP
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital Input/Output
Serial Peripheral Interface
SDIO
SPI
Aug. 24, 2018
Page 11 of 82
Rev 1.00
NUC2201
SPS
Samples per Second
TDES
TMR
Triple Data Encryption Standard
Timer Controller
UART
UCID
USB
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
Aug. 24, 2018
Page 12 of 82
Rev 1.00
NUC2201
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® NUC2201xxxAE Selection Guide
4.1.1 NuMicro® NUC2201 Naming Rule
NUC 2 2 01 - X X X X X
ARM-Based
32-bit Microcontroller
Temperature
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
CPU core
1/2: Cortex-M0
5/7: ARM7
9: ARM9
Reserved
RAM Size
1: 4KB
2: 8KB
Function
0: Advanced Line
2: USB Line
3: Automotive Line
4: Connectivity Line
3: 16KB
APROM Size
C: 32KB
D: 64KB
E: 128KB
Package Type
L: LQFP 48
S: LQFP 64
Figure 4-1 NuMicro® NUC2201 Series Selection Code
Aug. 24, 2018
Page 13 of 82
Rev 1.00
NUC2201
4.1.2 NuMicro® NUC2201 USB Line Selection Guide
Connectivity
NUC2201LE3AE 128 16 Config.
NUC2201SE3AE 128 16 Config.
8
8
31
45
4
4
2
3
1
2
2
2
1
1
2
3
-
-
-
-
-
-
-
-
6
6
10
12
v
v
-
v
v
LQFP48
LQFP64
v
Aug. 24, 2018
Page 14 of 82
Rev 1.00
NUC2201
4.2 Pin Configuration
4.2.1 NuMicro® NUC2201 Pin Diagram
4.2.1.1 NuMicro® NUC2201SxxAE LQFP 64 pin (7 mm * 7mm)
AD8/ADC5/PA.5
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1/UART2_TXD
PB.10/TM2/UART2_RXD
PB.11/TM3/PWM4
AD7/ADC6/PA.6
VREF
AVDD
PE.5/TM1_EXT/TM1/PWM5
PC.0/SPI0_SS0
AD5/ADC7/PC.7
AD4/ADC8/PC.6
PC.1/SPI0_CLK
AD3/ADC9/PC.15
PC.2/SPI0_MISO0
NUC2201SxxAE
LQFP 64-pin
AD2/ADC10/PC.14
PC.3/SPI0_MOSI0
AD6/ADC11/TM0/TM0_EXT/INT1/PB.15
PB.3/UART0_nCTS/TM3_EXT/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/TM2/nWRL
PB.1/UART0_TXD
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
PB.0/UART0_RXD
VSS
USB_D+
VDD
PVSS
USB_D-
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
USB_VBUS
Figure 4-2 NuMicro® NUC2201SxxAE LQFP 64-pin Diagram
Aug. 24, 2018
Page 15 of 82
Rev 1.00
NUC2201
4.2.1.2 NuMicro® NUC2201LxxAE LQFP 48 pin (7 mm * 7mm)
ADC5/PA.5
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPI0_SS0
PC.1/SPI0_CLK
PC.2/SPI0_MISO0
PC.3/SPI0_MOSI0
ADC6/PA.6
VREF
AVDD
ADC7/PC.7
PB.3/UART0_nCTS/TM3_EXT/TM3
PB.2/UART0_nRTS/TM2_EXT/TM2
PB.1/UART0_TXD
PB.0/UART0_RXD
USB_D+
NUC2201LxxAE
LQFP 48-pin
ADC8/PC.6
ADC11/TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
USB_D-
PVSS
USB_VDD33_CAP
USB_VBUS
CLKO/TM0/STADC/PB.8
Figure 4-3 NuMicro® NUC2201LxxAE LQFP 48-pin Diagram
Aug. 24, 2018
Page 16 of 82
Rev 1.00
NUC2201
4.3 Pin Description
4.3.1 NuMicro® NUC2201 Pin Description
Pin
Type
Pin No.
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
PB.14
I/O
I
General purpose digital I/O pin.
External interrupt0 input pin.
EBI Address/Data bus bit0
1
INT0
AD0
I/O
I/O
I/O
P
PB.13
General purpose digital I/O pin.
EBI Address/Data bus bit1
2
AD1
3
4
5
1
2
3
VBAT
Power supply by batteries for RTC.
External 32.768 kHz (low speed) crystal output pin.
External 32.768 kHz (low speed) crystal input pin.
General purpose digital I/O pin.
I2C1 clock pin.
X32_OUT
X32_IN
PA.11
O
I
I/O
I/O
O
4
6
7
I2C1_SCL
nRD
EBI read enable output pin
PA.10
I/O
I/O
O
General purpose digital I/O pin.
I2C1 data input/output pin.
5
I2C1_SDA
nWR
EBI write enable output pin
PA.9
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
I2C0 clock pin.
8
9
6
7
8
9
I2C0_SCL
PA.8
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PB.4
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Request to Send output pin for UART1.
EBI address latch enable output pin
General purpose digital I/O pin.
Clear to Send input pin for UART1.
EBI chip select enable output pin
LDO output pin.
10
11
UART1_RXD
PB.5
I/O
O
UART1_TXD
PB.6
I/O
O
12
UART1_nRTS
ALE
O
PB.7
I/O
I
13
14
UART1_nCTS
nCS
O
10
LDO_CAP
P
Aug. 24, 2018
Page 17 of 82
Rev 1.00
NUC2201
Pin
Type
Pin No.
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
15
16
17
11
12
13
VDD
P
P
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
Ground pin for digital circuit.
VSS
USB_VBUS
USB Power supply from USB host or HUB.
USB_VDD33_C
AP
18
14
USB Internal power regulator output 3.3V decoupling pin.
19
20
15
16
USB_D-
USB_D+
PB.0
USB USB differential signal D-.
USB USB differential signal D+.
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external capture input pin.
Timer2 toggle output pin.
21
22
17
18
UART0_RXD
PB.1
I/O
O
UART0_TXD
PB.2
I/O
O
UART0_nRTS
TM2_EXT
TM2
19
23
I
O
nWRL
O
EBI low byte write enable output pin
General purpose digital I/O pin.
Clear to Send input pin for UART0.
Timer3 external capture input pin.
Timer3 toggle output pin.
PB.3
I/O
I
UART0_nCTS
TM3_EXT
TM3
20
24
I
O
nWRH
O
EBI high byte write enable output pin
General purpose digital I/O pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
PC.3
I/O
I/O
I/O
25
26
21
22
SPI0_MOSI0
PC.2
SPI0_MISO0
I/O
1st SPI0 MISO (Master In, Slave Out) pin.
PC.1
I/O
I/O
I/O
I/O
General purpose digital I/O pin.
SPI0 serial clock pin.
27
28
23
24
SPI0_CLK
PC.0
General purpose digital I/O pin.
1st SPI0 slave select pin.
SPI0_SS0
PE.5
I/O
General purpose digital I/O pin.
29
PWM5
I/O
I
PWM5 output/Capture input.
TM1_EXT
Timer1 external capture input pin.
Aug. 24, 2018
Page 18 of 82
Rev 1.00
NUC2201
Pin
Type
Pin No.
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
TM1
O
Timer1 toggle output pin.
PB.11
I/O
General purpose digital I/O pin.
30
TM3
I/O
Timer3 event counter input / toggle output.
PWM4
I/O
I/O
I/O
I
PWM4 output/Capture input.
General purpose digital I/O pin.
Timer2 event counter input / toggle output.
Data receiver input pin for UART2.
General purpose digital I/O pin.
Timer1 event counter input / toggle output.
Data transmitter output pin for UART2.
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
PB.10
31
32
TM2
UART2_RXD
PB.9
I/O
I/O
O
TM1
UART2_TXD
PC.11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
33
34
35
SPI1_MOSI0
PC.10
SPI1_MISO0
PC.9
SPI1_CLK
PC.8
General purpose digital I/O pin.
1st SPI1 slave select pin.
36
37
38
SPI1_SS0
MCLK
EBI clock output
PA.15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin.
PWM3 output/Capture input.
General purpose digital I/O pin.
PWM2 output/Capture input.
EBI Address/Data bus bit15
25
26
PWM3
PA.14
PWM2
AD15
PA.13
General purpose digital I/O pin.
PWM1 output/Capture input.
EBI Address/Data bus bit14
27
28
39
40
PWM1
AD14
PA.12
General purpose digital I/O pin.
PWM0 output/Capture input.
EBI Address/Data bus bit13
PWM0
AD13
41
42
29
30
ICE_DAT
ICE_CLK
Serial wire debugger data pin.
Serial wire debugger clock pin.
Aug. 24, 2018
Page 19 of 82
Rev 1.00
NUC2201
Pin
Type
Pin No.
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
43
31
32
AVSS
PA.0
ADC0
PA.1
ADC1
AD12
PA.2
ADC2
AD11
PA.3
ADC3
AD10
PA.4
ADC4
AD9
AP
I/O
AI
Ground pin for analog circuit.
General purpose digital I/O pin.
ADC0 analog input.
44
45
I/O
AI
General purpose digital I/O pin.
ADC1 analog input.
33
34
35
36
37
38
I/O
I/O
AI
EBI Address/Data bus bit12
General purpose digital I/O pin.
ADC2 analog input.
46
47
48
49
50
I/O
I/O
AI
EBI Address/Data bus bit11
General purpose digital I/O pin.
ADC3 analog input.
I/O
I/O
AI
EBI Address/Data bus bit10
General purpose digital I/O pin.
ADC4 analog input.
I/O
I/O
AI
EBI Address/Data bus bit9
General purpose digital I/O pin.
ADC5 analog input.
PA.5
ADC5
AD8
I/O
I/O
AI
EBI Address/Data bus bit8
General purpose digital I/O pin.
ADC6 analog input.
PA.6
ADC6
AD7
I/O
AP
AP
I/O
AI
EBI Address/Data bus bit7
Voltage reference input for ADC.
Power supply for internal analog circuit.
General purpose digital I/O pin.
ADC7 analog input.
51
52
39
40
VREF
AVDD
PC.7
ADC7
AD5
41
53
54
55
I/O
I/O
AI
EBI Address/Data bus bit5
General purpose digital I/O pin.
ADC8 analog input.
PC.6
ADC8
AD4
42
I/O
I/O
AI
EBI Address/Data bus bit4
General purpose digital I/O pin.
ADC9 analog input.
PC.15
ADC9
AD3
I/O
EBI Address/Data bus bit3
Aug. 24, 2018
Page 20 of 82
Rev 1.00
NUC2201
Pin
Type
Pin No.
Pin Name
Description
LQFP
LQFP
64-pin
48-pin
PC.14
ADC10
AD2
I/O
AI
I/O
I/O
I
General purpose digital I/O pin.
ADC10 analog input.
56
EBI Address/Data bus bit2
PB.15
INT1
General purpose digital I/O pin.
External interrupt1 input pin.
43
TM0_EXT
TM0
I
Timer 0 external capture input pin.
Timer0 event counter input / toggle output.
ADC11 analog input.
57
58
I/O
AI
I/O
I/O
O
ADC11
AD6
EBI Address/Data bus bit6
PF.0
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal input pin.
44
XT1_OUT
PF.1
I/O
I
59
60
45
46
XT1_IN
External reset input: active LOW, with an internal pull-up. Set this pin low reset
chip to initial state.
nRESET
I
61
62
63
VSS
P
P
Ground pin for digital circuit.
VDD
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
PLL ground.
47
48
PVSS
PB.8
STADC
TM0
P
I/O
I
General purpose digital I/O pin.
ADC external trigger input.
64
I/O
O
Timer0 event counter input / toggle output.
Frequency divider clock output pin.
CLKO
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
Aug. 24, 2018
Page 21 of 82
Rev 1.00
NUC2201
5
BLOCK DIAGRAM
5.1 NuMicro® NUC2201 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 12
32-bit Timer x 4
APROM
128 KB
LDROM
8 KB
RTC
ARM
Cortex-M0
72MHz
USB PHY
PDMA
Watchdog Timer
DataFlash
Configurable
SRAM
16 KB
PWM/Capture
Timer x 6
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
I/O Ports
General Purpose
I/O
LDO
Power On Reset
LVR
High Speed
Oscillator
48 MHz
High Speed
Crystal Osc.
4 ~ 24 MHz
External Interrupt
Reset Pin
SPI x 2
I2C x 2
USB
High Speed
Oscillator
22.1184 MHz
Low Speed
Crystal Osc.
32.768 KHz
Low Speed
Oscillator
10 kHz
Brownout
Detection
Figure 5-1 NuMicro® NUC2201 Block Diagram
Aug. 24, 2018
Page 22 of 82
Rev 1.00
NUC2201
6
FUNCTIONAL DESCRIPTION
6.1 Arm® Cortex® -M0 Core
The Cortex® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
Cortex® -M0 Components
CortexTM-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
Cortex® -M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
-
-
-
-
-
-
-
Armv6-M Thumb® instruction set
Thumb-2 technology
Armv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the Armv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
Aug. 24, 2018
Page 23 of 82
Rev 1.00
NUC2201
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
Aug. 24, 2018
Page 24 of 82
Rev 1.00
NUC2201
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset
Low Voltage Reset
Brown-out Detector Reset
CPU Reset
System Reset
System Reset and Power-on Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-on Reset is external crystal circuit and BS
(ISPCON[1]) bit. System Reset does not reset external crystal circuit and BS (ISPCON[1]) bit, but
Power-on Reset does.
Aug. 24, 2018
Page 25 of 82
Rev 1.00
NUC2201
6.2.3 System Power Distribution
In this chip, the power distribution is divided into four segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
Battery power from VBAT supplies the RTC and external 32.768 kHz crystal.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level with the digital power (VDD). Figure 6-2 shows the NuMicro® NUC2201 power
distribution.
AVDD
USB_D+
USB_D-
12-bit
SAR-ADC
USB 1.1
Tranceiver
AVSS
NUC2201
Power
Distribution
USB_VDD33_CAP
1uF
Analog Comparator
3.3V
Low
Voltage
Reset
Brown-
out
Detector
5V to 3.3V LDO
USB_VBUS
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
External
32.768 kHz
Crystal
ULDO
RTC
PLL
LDO
IO cell
GPIO
Figure 6-2 NuMicro® NUC2201 Power Distribution Diagram
Aug. 24, 2018
Page 26 of 82
Rev 1.00
NUC2201
6.2.4 System Memory Map
The NuMicro® NUC2201 provides 4G-byte addressing space. The memory locations assigned to each
on-chip controllers are shown in the following table. The detailed register definition, memory space,
and programming detailed will be described in the following sections for each on-chip peripheral. The
NuMicro® NUC2201 only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128 KB)
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
Peripheral DMA Control Registers
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
FMC_BA
EBI_BA
Flash Memory Control Registers
External Bus Interface Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x400E_0000 – 0x400E_FFFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
TMR01_BA
I2C0_BA
I2C0 Interface Control Registers
SPI0_BA
SPI1_BA
PWMA_BA
UART0_BA
USBD_BA
ADC_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
UART0 Control Registers
USB 2.0 FS device Controller Registers
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x4015_4000 – 0x4015_7FFF
TMR23_BA
I2C1_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
PWM4/5 Control Registers
UART1 Control Registers
PWMB_BA
UART1_BA
UART2_BA
UART2 Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
Aug. 24, 2018
Page 27 of 82
Rev 1.00
NUC2201
0xE000_ED00 – 0xE000_ED8F
SCS_BA
System Control Registers
Table 6-1 Address Space Assignments for On-Chip Controllers
6.2.5 Register Lock
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register REGWRPROT address at 0x5000_0100
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
After the protection is disabled, user can check the protection disable bit at address 0x5000_0100 bit0,
1 is protection disable, and 0 is protection enable. Then user can update the target protected register
value and then write any data to the address “0x5000_0100” to enable register protection.
The protected registers are listed as following table.
Register
IPRSTC1
IPRSTC1
IPRSTC1
IPRSTC1
BODCR
Bit
Description
[3] EBI_RST
EBI Controller Reset (Write-protection Bit)
PDMA Controller Reset (Write Protect)
[2] PDMA_RST
[1] CPU_RST
CPU Kernel One-Shot Reset (Write Protect)
CHIP One-Shot Reset (Write Protect)
[0] CHIP_RST
[7] LVR_EN
Low Voltage Reset Enable Bit (Write Protect)
Brown-Out Detector Low Power Mode (Write Protect)
Brown-Out Reset Enable Bit (Write Protect)
Brown-Out Detector Threshold Voltage Selection (Write Protect)
Brown-Out Detector Enable Bit (Write Protect)
Power-On-Reset Enable Bit (Write Protect)
Register Write-Protection Code (Write Only)
Register Write-Protection Disable Index (Read Only)
NMI Interrupt Enable Bit (Write Protect)
BODCR
[5] BOD_LPM
BODCR
[3] BOD_RSTEN
[2:1] BOD_VL
BODCR
BODCR
[0] BOD_EN
PORCR
[15:0] POR_DIS_CODE
[7:0] REGWRPROT
[0] REGPROTDIS
[8] NMI_EN
REGWRPROT
REGWRPROT
NMI_SEL
PWRCON
PWRCON
PWRCON
PWRCON
PWRCON
[8] PD_WAIT_CPU
[7] PWR_DOWN_EN
[5] PD_WU_INT_EN
[4] PD_WU_DLY
[3] OSC10K_EN
Power-Down Entry Condition Control (Write Protect)
System Power-Down Enable Bit (Write Protect)
Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
Wake-Up Delay Counter Enable Bit (Write Protect)
10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Bit (Write
Protect)
PWRCON
[2] OSC22M_EN
[1] XTL32K_EN
22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Bit
(Write Protect)
PWRCON
32.768 KHz External Low Speed Crystal Oscillator (LXT) Enable Bit
Aug. 24, 2018
Page 28 of 82
Rev 1.00
NUC2201
(Write Protect)
PWRCON
[0] XTL12M_EN
4~24 MHz External High Speed Crystal Oscillator (HXT) Enable Bit
(Write Protect)
APBCLK
CLKSEL0
CLKSEL0
CLKSEL1
ISPCON
ISPCON
ISPCON
ISPCON
ISPCON
ISPCON
ISPTRG
FATCON
ISPSTA
TCSR0
[0] WDT_EN
[5:3] STCLK_S
[2:0] HCLK_S
[1:0] WDT_S
[6] ISPFF
Watchdog Timer Clock Enable Bit (Write Protect)
Cortex™-M0 SysTick Clock Source Select (Write Protect)
HCLK Clock Source Select (Write Protect)
Watchdog Timer Clock Source Select (Write Protect)
ISP Fail Flag (Write Protect)
[5] LDUEN
LDROM Update Enable Bit (Write Protect)
[4] CFGUEN
[3] APUEN
Enable Config Update By ISP (Write Protect)
APROM Update Enable Bit (Write Protect)
[1] BS
Boot Select (Write Protect )
[0] ISPEN
ISP Enable Bit (Write Protect )
[0] ISPGO
ISP Start Trigger (Write-Protection Bit)
[4] FOMSEL0
[6] ISPFF
Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)
ISP Fail Flag (Write-Protection Bit)
[31] DBGACK_TMR
[31] DBGACK_TMR
[31] DBGACK_TMR
[31] DBGACK_TMR
[31] DBGACK_WDT
[10:8] WTIS
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
ICE Debug Mode Acknowledge Disable Bit (Write Protect)
Watchdog Timer Time-Out Interval Selection (Write Protect)
Watchdog Timer Enable Bit (Write Protect)
TCSR1
TCSR2
TCSR3
WTCR
WTCR
WTCR
[7] WTE
WTCR
[6] WTIE
Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)
WTCR
[4] WTWKE
Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)
Watchdog Timer Reset Enable Bit (Write Protect)
WTCR
[1] WTRE
WTCRALT
[1:0] WTRDSEL
Watchdog Timer Reset Delay Selection (Write Protect)
6.2.6 Auto Trim
This chip supports auto-trim function: the HIRC trim (48 MHz and 22.1184 MHz RC oscillator),
according to the accurate LXT (32.768 kHz crystal oscillator) or internal USB synchronous mode,
automatically gets accurate HIRC output frequency, 0.25 % deviation within all temperature ranges.
For instance, the system needs an accurate 22.1184 MHz clock. In such case, if users do not want to
use PLL as the system clock source, they need to solder 32.768 kHz crystal in system, and set
FREQSEL (SYS_IRCTCTL[1:0] trim frequency selection) to “01”, and the auto-trim function will be
enabled. Interrupt status bit FREQ_LOCK (SYS_IRCTSTS[0] HIRC frequency lock status) “1”
indicates the HIRC output frequency is accurate within 0.25% deviation. To get better results, it is
recommended to set both TRIM_LOOP (SYS_IRCTCTL[5:4]) Trim Calculation Loop and
Aug. 24, 2018
Page 29 of 82
Rev 1.00
NUC2201
TRIM_RETRY_CNT (SYS_IRCTCTL[7:6] Trim Value Update Limitation Count) to “11”.
Another example is that the system needs an accurate 48 MHz clock for USB application. In such
case, if neither using use PLL as the system clock source, user has to set FREQSEL
(SYS_HIRCTCTL1[1:0] trim frequency selection) to “01”, and the auto-trim function will be enabled.
Status bit FREQLOCK (SYS_HIRCTISTS[8] HIRC Frequency Lock Status) “1” indicates the HIRC48
output frequency is accurate within 0.25% deviation.
Aug. 24, 2018
Page 30 of 82
Rev 1.00
NUC2201
6.2.7 System Timer (SysTick)
The Cortex® -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference
Manual” and “Arm® v6-M Architecture Reference Manual”.
Aug. 24, 2018
Page 31 of 82
Rev 1.00
NUC2201
6.2.8 Nested Vectored Interrupt Controller (NVIC)
The Cortex® -M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor kernel
and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference
Manual” and “Arm® v6-M Architecture Reference Manual”
Aug. 24, 2018
Page 32 of 82
Rev 1.00
NUC2201
6.2.8.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro® NUC2201. Software can set
four levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority
of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
3
-1
4 ~ 10
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
11
Reserved
12 ~ 13
PendSV
14
SysTick
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 6-2 Exception Model
Interrupt Number
Vector
Number
Source
Module
Interrupt Name
Interrupt Description
(Bit In Interrupt
Registers)
1 ~ 15
16
-
-
-
System exceptions
0
1
2
3
BOD_INT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
17
WDT
GPIO
GPIO
Watchdog Timer interrupt
18
External signal interrupt from PB.14 pin
External signal interrupt from PB.15 pin
19
EINT1
External signal interrupt from
PA[6:0]/PA[15:8]/PB[11:0]/PB[15:13]
20
21
4
5
GPAB_INT
GPIO
GPIO
External interrupt from
PC[3:0]/PC[11:6]/PC[15:14]/PE[5]/PF[1:0]
GPCEF_INT
22
23
24
25
26
27
28
29
6
7
PWMA_INT
PWMB_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
PWM0~3
PWM4~7
TMR0
PWM0, PWM1, PWM2 and PWM3 interrupt
PWM4 and PWM5 interrupt
Timer 0 interrupt
8
9
TMR1
Timer 1 interrupt
10
11
12
13
TMR2
Timer 2 interrupt
TMR3
Timer 3 interrupt
UART0/2
UART1
UART0 and UART2 interrupt
UART1 interrupt
Aug. 24, 2018
Page 33 of 82
Rev 1.00
NUC2201
30
31
32
33
34
35
36
37
38
39
40
41
42
43
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SPI0_INT
SPI0
SPI0 interrupt
SPI1 interrupt
Reserved
SPI1_INT
SPI1
-
-
-
-
Reserved
I2C0_INT
I2C0
I2C0 interrupt
I2C1 interrupt
Reserved
I2C1_INT
I2C1
-
-
-
-
Reserved
-
-
Reserved
USB_INT
USBD
USB 2.0 FS Device interrupt
Reserved
-
-
-
-
PDMA
-
Reserved
PDMA_INT
-
PDMA interrupt
Reserved
Clock controller interrupt for chip wake-up from Power-
down state
44
28
PWRWU_INT
CLKC
45
46
47
29
30
31
ADC_INT
IRC_INT
RTC_INT
ADC
IRC
ADC interrupt
IRC TRIM interrupt
Real Time Clock interrupt
RTC
Table 6-3 System Interrupt Map
Aug. 24, 2018
Page 34 of 82
Rev 1.00
NUC2201
6.2.8.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For Armv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 6-4 Vector Table Format
Vector Number
6.2.8.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
Aug. 24, 2018
Page 35 of 82
Rev 1.00
NUC2201
6.2.9 System Control
The Cortex® -M0 status and operating mode control are managed by System Control Registers.
Including CPUID, Cortex™-M0 interrupt priority and Cortex® -M0 power management can be
controlled through these system control registers.
For more detailed information, please refer to the “Arm® Cortex® -M0 Technical Reference
Manual” and “Arm® v6-M Architecture Reference Manual”.
Aug. 24, 2018
Page 36 of 82
Rev 1.00
NUC2201
6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex® -M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave
Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal oscillator and 22.1184/48 MHz internal high speed RC oscillator to reduce the
overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
The clock generator consists of 6 clock sources as listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from external
4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high
speed RC oscillator (HIRC)) (PLL FOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
48 MHz internal high speed RC oscillator (HIRC48)
10 kHz internal low speed RC oscillator (LIRC)
Aug. 24, 2018
Page 37 of 82
Rev 1.00
NUC2201
XTL32K_EN (PWRCON[1])
X32_OUT
X32_IN
LXT
HXT
32.768 kHz
LXT
XTL12M_EN (PWRCON[0])
XT1_OUT
XT1_IN
4~24 MHz
HXT
PLL_SRC (PLLCON[19])
PLL
0
1
PLL FOUT
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
OSC48M_EN(PWRCON[12])
HIRC48
48 MHz
HIRC48
Legend:
LXT = 32.768 kHz external low speed crystal oscillator
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
HIRC48 = 48 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6-3 Clock Generator Block Diagram
Aug. 24, 2018
Page 38 of 82
Rev 1.00
NUC2201
22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
PDMA
I2C 0~1
4~24
MHz
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
32.768
kHz
PCLK
22.1184 MHz
10 kHz
111
101
011
010
001
000
10 kHz
CLKSEL0[2:0]
TMR 3
TMR 2
TMR 1
TMR 0
External trigger
HCLK
22.1184 MHz
4~24 MHz
1
PLLFOUT
32.768 kHz
4~24 MHz
0
PLLCON[19]
22.1184 MHz
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
FMC
CPUCLK
22.1184 MHz
HCLK
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
SYST_CSR[2]
4~24 MHz
32.768 kHz
4~24 MHz
10 kHz
111
22.1184 MHz
011
PWM 4-5
PWM 2-3
PWM 0-1
HCLK
010
32.768 kHz
001
CLKSEL0[5:3]
4~24 MHz
000
CLKSEL2[17:16]
10 kHz
11
10
WWDT
WDT
CLKSEL2[5:4]
CLKSEL1[31:28]
10 kHz
11
10
01
HCLK
1/2048
32.768 kHz
22.1184 MHz
11
01
00
PLLFOUT
4~24 MHz
CLKSEL1[1:0]
HCLK
1
0
SPI0-1
PLLFOUT
CLKSEL1[25:24]
CLK_SEL1[5:4]
1/(UART_N+1)
1/(ADC_N+1)
UART 0-2
22.1184 MHz
HCLK
11
10
01
00
ADC
BOD
PLLFOUT
4~24 MHz
22.1184 MHz
HCLK
10 kHz
11
10
01
00
FDIV
RTC
32.768 kHz
4~24 MHz
CLKSEL1[3:2]
10 kHz
1
0
32.768 kHz
CLKSEL2[3:2]
CLKSEL2[18]
1/(USB_N+1)
HIRC48
1
0
USB
PLLFOUT
CLKSEL0[8]
Figure 6-4 Clock Generator Global View Diagram
Aug. 24, 2018
Page 39 of 82
Rev 1.00
NUC2201
6.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-5.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011
010
001
000
CPUCLK
HCLK
CPU
AHB
APB
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PCLK
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6-5 System Clock Block Diagram
The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-6.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly selected
clock sources must be turned on and stable.
Figure 6-6 SysTick Clock Control Block Diagram
Aug. 24, 2018
Page 40 of 82
Rev 1.00
NUC2201
6.3.3 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
-
-
10 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator clock
RTC/WDT/Timer/PWM Peripherals Clock (when 32.768 kHz external low speed
crystal oscillator or 10 kHz intertnal low speed RC oscillator is adopted as clock
source)
6.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
22.1184 MHz
11
FRQDIV_CLK
HCLK
10
01
00
32.768 kHz
4~24 MHz
Note: Before clock switching, both the pre-selected and newly selected
clock sources must be turned on and stable.
Figure 6-7 Clock Source of Frequency Divider
Aug. 24, 2018
Page 41 of 82
Rev 1.00
NUC2201
DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FSEL
(FRQDIV[3:0])
16 chained
divide-by-2 counter
FRQDIV_CLK
DIVIDER1
(FRQDIV[5])
1/2
1/22 1/23
…... 1/215 1/216
CLKO_1HZ_EN
(FRQDIV[6])
0000
0001
16 to 1
MUX
:
:
0
1
CLKO
0
1
1110
1111
RTC_SEL_10K
(CLKSEL2[18])
32.768 kHz
10 kHz
0
1
1Hz clock from RTC
/32768
Figure 6-8 Frequency Divider Block Diagram
Aug. 24, 2018
Page 42 of 82
Rev 1.00
NUC2201
6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NuMicro® NUC2201 has 128K bytes on-chip embedded Flash for application program
memory (APROM) that can be updated through ISP procedure. The In-System-Programming
(ISP) function enables user to update program memory when chip is soldered on PCB. After chip
is powered on, Cortex® -M0 CPU fetches code from APROM or LDROM decided by boot select
(CBS) in CONFIG0. By the way, the NuMicro® NUC2201 supports another flexible feature:
configurable Data Flash size. The Data Flash size is decided by Data Flash enable (DFEN) in
Config0 and Data Flash base address (DFBADR) in Config1. When DFEN is set to 1, the Data
Flash size is zero and the APROM size is 128K bytes. When DFEN is set to 0, the APROM and
Data Flash share 128K bytes continuous address and the start address of Data Flash is defined
by (DFBADR) in Config1.
6.4.2 Features
Runs up to 50 MHz with zero wait cycle for continuous address read access and runs
up to 72 MHz with one wait cycle for continuous address read.
All embedded flash memory supports 512 bytes page erase
128 KB application program memory (APROM)
8 KB In-System-Programming (ISP) loader program memory (LDROM)
Configurable Data Flash size with 512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
Aug. 24, 2018
Page 43 of 82
Rev 1.00
NUC2201
6.5 External Bus Interface (EBI)
6.5.1 Overview
The NuMicro® NUC2201 series LQFP-64 package equips an external bus interface (EBI) for
access external device.
To save the connections between external device and this chip, EBI supports address bus and
data bus multiplex mode. And, address latch enable (ALE) signal is used to differentiate the
address and data cycle.
6.5.2 Features
External Bus Interface has the following functions:
Supports external devices with max. 64 KB size (8-bit data width)/128 KB (16-bit data
width)
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Supports address bus and data bus multiplex mode to save the address pins
Supports configurable idle cycle for different access condition: Write command finish
(W2X), Read-to-Read (R2R)
Aug. 24, 2018
Page 44 of 82
Rev 1.00
NUC2201
6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NuMicro® NUC2201 series has up to 45 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 45 pins are arranged in 5 ports named
as GPIOA, GPIOB, GPIOC, GPIOE and GPIOF. The GPIOA/B/C/E port has the maximum of 15
pins and GPIOF port has the maximum of 2 pins. Each of the 45 pins is independent and has the
corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V.
6.6.2 Features
Four I/O modes:
Quasi-bidirectional
-
-
-
-
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
-
-
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
Aug. 24, 2018
Page 45 of 82
Rev 1.00
NUC2201
6.7 PDMA Controller (PDMA)
6.7.1 Overview
The NuMicro® NUC2201 series DMA contains nine-channel peripheral direct memory access
(PDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA
PDMACEN (PDMA_CSRx[0]). The CPU can recognize the completion of a PDMA operation by
software polling or when it receives an internal PDMA interrupt. The PDMA controller can
increase source or destination address or fixed them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and DMA transfer mode.
6.7.2 Features
Supports nine PDMA channels and one CRC channel. Each PDMA channel can
support a unidirectional transfer
AMBA AHB master/slave interface compatible, for data transfer and register
read/write
Hardware round robin priority scheme. DMA channel 0 has the highest priority and
channel 8 has the lowest priority
PDMA operation
-
-
-
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed.
Cyclic Redundancy Check (CRC)
-
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 +
X2 + X + 1
-
-
-
Supports programmable CRC seed value.
Supports programmable order reverse setting for input data and CRC checksum.
Supports programmable 1’s complement setting for input data and CRC
checksum.
-
-
Supports CPU PIO mode or DMA transfer mode.
Supports the follows write data length in CPU PIO mode
8-bit write mode (byte): 1-AHB clock cycle operation.
16-bit write mode (half-word): 2-AHB clock cycle operation.
Aug. 24, 2018
Page 46 of 82
Rev 1.00
NUC2201
32-bit write mode (word): 4-AHB clock cycle operation.
-
Supports byte alignment transfer data length and word alignment transfer source
address in CRC DMA mode.
Aug. 24, 2018
Page 47 of 82
Rev 1.00
NUC2201
6.8 Timer Controller (TIMER)
6.8.1 Overview
The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.8.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external counter pin
(TM0~TM3)
Supports external pin capture (TM0_EXT~TM3_EXT) for interval measurement
Supports external pin capture (TM0_EXT~TM3_EXT) for reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Aug. 24, 2018
Page 48 of 82
Rev 1.00
NUC2201
6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The NuMicro® NUC2201 series has 2 sets of PWM group supporting a total of 3 sets of PWM
generators that can be configured as 6 independent PWM outputs, PWM0~PWM5, or as 3
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3) and (PWM4, PWM5) with 3
programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 3
sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;
the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3) and (PWM4, PWM5)
are controlled by PWM2 and PWM4 timers and Dead-zone generator 2 and 4, respectively. Refer
from 錯誤! 找不到參照來源。 to 錯誤! 找不到參照來源。 for the architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-
shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0
(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture
channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). And
capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
example:
Aug. 24, 2018
Page 49 of 82
Rev 1.00
NUC2201
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will be 1/900ns ≈ 1000 kHz
6.9.2 Features
6.9.2.1 PWM Function:
Up to 2 PWM groups (PWMA/PWMB) to support 6 PWM channels or 3
complementary PWM paired channels
PWM group A has two PWM generators and PWM group B has one PWM generator
with each PWM generator supporting one 8-bit prescaler, two clock dividers, two
PWM-timers, one Dead-zone generator and two PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode
Edge-aligned type or Center-aligned type option
PWM trigger ADC start-to-conversion
6.9.2.2 Capture Function:
Timing control logic shared with PWM Generators
Supports 6 Capture input channels shared with 6 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)
Aug. 24, 2018
Page 50 of 82
Rev 1.00
NUC2201
6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period
is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer reset delay period
-
Selectable it includes (1026、130、18 or 3) * WDT_CLK reset delay period.
Supports to force Watchdog Timer enabled after chip powered on or reset while
CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
Aug. 24, 2018
Page 51 of 82
Rev 1.00
NUC2201
6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer is used to perform a system reset within a specified window period
to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter value (WWDTVAL[5:0]) and 6-bit compare window value
(WWDTCR[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of
WWDT counter
Aug. 24, 2018
Page 52 of 82
Rev 1.00
NUC2201
6.12 Real Time Clock (RTC)
6.12.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
The RTC controller also offers 80 bytes spare registers to store user’s important information.
6.12.2 Features
Supports real time counter in Time Loading Register (TLR) (hour, minute, second)
and calendar counter in Calendar Loading Register (CLR) (year, month, day) for RTC
time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings
in Time Alarm Register (TAR) and Calendar Alarm Register (CAR) register
Selectable 12-hour or 24-hour time scale in Time Scale Selection Register (TSSR)
register
Supports Leap Year indication in Leap Year Indicator Register (LIR) register
Supports Day of the Week counter in Day of the Week Register (DWR) register
Frequency of RTC clock source compensate by RTC Frequency Compensation
Register (FCR) register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
Supports 80 bytes spare registers
Aug. 24, 2018
Page 53 of 82
Rev 1.00
NUC2201
6.13 UART Interface Controller (UART)
6.13.1 Overview
The NuMicro® NUC2201 series provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART. Besides, only UART0 and UART1 support the flow control function. The
UART Controller performs a serial-to-parallel conversion on data received from the peripheral,
and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also
supports IrDA SIR Function, LIN master/slave function and RS-485 function mode. Each UART
Controller channel supports seven types of interrupts.
6.13.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for
data payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and
programmable RTS flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function (UART0 and UART1 support)
Supports 7-bit receiver buffer time-out detection function
UART0/UART1 can through DMA channels to receive/transmit data
Programmable transmitting data delay time between the last stop and the next start bit
by setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow
detect function
Fully programmable serial-interface characteristics
-
-
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
-
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
-
-
-
-
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode.
-
-
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by RTS pin
(UART0 and UART1 support)
Aug. 24, 2018
Page 54 of 82
Rev 1.00
NUC2201
6.14 I2C Serial Interface Controller (I2C)
6.14.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
6.14.2 Features
The I2C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices
connected to the bus. The main features of the I2C bus include:
Supports up to two I2C serial interface controller
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Aug. 24, 2018
Page 55 of 82
Rev 1.00
NUC2201
6.15 Serial Peripheral Interface (SPI)
6.15.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® NUC2201 series contains up to two sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable bus clock function for special applications. This controller
also supports the PDMA function to access the data buffer and also supports Dual I/O Transfer
mode.
6.15.2 Features
Up to two sets of SPI controllers
Supports Master or Slave mode operation
Supports Dual I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32 bits
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Two slave select lines in Master mode
Supports the Byte Reorder function
Supports Byte or Word Suspend mode
Variable output bus clock frequency in Master mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
Aug. 24, 2018
Page 56 of 82
Rev 1.00
NUC2201
6.16 USB Device Controller (USBD)
6.16.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types, and use High Internal RC Oscillator (HIRC48M) obtain to crystal-less
option.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, and BUS events. Any event will cause an interrupt, and
users just need to check the related event flags in interrupt event status register (USB_INTSTS)
to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status
Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If DRVSE0 (USB_DRVSE0[0]) is set to 1, the USB
controller will force the output of USB_D+ and USB_D- to level low. After DRVSE0 bit is cleared
to 0, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1 for details.
6.16.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
Supports Crystal-less
Aug. 24, 2018
Page 57 of 82
Rev 1.00
NUC2201
6.17 Analog-to-Digital Converter (ADC)
6.17.1 Overview
The NuMicro® NUC2201 series contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 12 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM Center-aligned trigger and external STADC pin.
6.17.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 12 single-end analog input channels or 5 differential analog input channels
Up to 1 MSPS conversion rate (chip working at 5V)
Three operating modes
-
-
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
-
Continuous scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion
An A/D conversion can be started by:
-
-
-
Writing 1 to ADST bit (ADCR[11])through software
PWM Center-aligned trigger
External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators
Supports two set digital comparators. The conversion result can be compared with
specify value and user can select whether to generate an interrupt when conversion
result matches the compare register setting
Channel 7 supports 3 input sources: external analog voltage, internal Band-gap
voltage, and internal temperature sensor output
Aug. 24, 2018
Page 58 of 82
Rev 1.00
NUC2201
7
APPLICATION CIRCUIT
AVCC
VREF
AVDD
FB
DVCC
USB_VBUS
USB_D-
USB_D+
33R
33R
VDD
USB OTG Slot
VBAT
0.1uF 1uF
10uF 0.1uF
Power
USB_VDD33_CAP
VSS
1uF
FB
DVCC
AVSS
[2]
DVCC
[1]
100K
100K
SPI_SS
SPI_CLK
SPI_MISO
CS
CLK
MISO
MOSI
VDD
VSS
VDD
SPI Device
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
NUC2201xE3AE
SPI_MOSI
20p
XT1_IN
4~ 24 MHz
crystal
20p
20p
DVCC
4.7K
DVCC
XT1_OUT
X32_IN
4.7K
Crystal
CLK
DIO
I2C_SCL
I2C_SDA
VDD
VSS
I2C Device
32.768kHz
crystal
20p
X32_OUT
DVCC
Reset
Circuit
10K
nRST
PC COM Port
RS 232 Transceiver
ROUT RIN
10uF/10V
RXD
TXD
UART
TIN
TOUT
LDO CAP
_
LDO
1uF
Note1: For the SPI device, the chip supply voltage must
be equal to SPI device working voltage. For example,
when the SPI Flash working voltage is 3.3 V, the chip
supply voltage must also be 3.3V.
Note2: It is recommended to use pull-up resistor on both
ICE_DAT and ICE_CLK pin if CIOINI(Config0[10]) is set
to 0.
Aug. 24, 2018
Page 59 of 82
Rev 1.00
NUC2201
8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
-0.3
VSS-0.3
4
MAX
+7.0
VDD+0.3
24
UNIT
DC Power Supply
V
V
VDDVSS
VIN
Input Voltage
Oscillator Frequency
1/tCLCL
TA
MHz
C
Operating Temperature
Junction temperature
-40
+105
+125
+150
120
TJ
-40
C
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
120
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
Aug. 24, 2018
Page 60 of 82
Rev 1.00
NUC2201
8.1.1 EMC characteristics
Maximum
value
Symbol
Parameter
Conditions
Unit
1.
2.
Fast transient voltage burst limits to be
applied through 0.1 uF + 10 uF on VDD and
VSS pins to induce a functional disturbance
VDD = 3.3 V, LQFP64, TA = +25
°C, fHCLK = 72 MHz
VEFTB
4.4
kV
to be applied through 1 uF on LDO_Pin and
VSS pins
Note: Guaranteed by characterization results, not tested in production.
Maximum
value
Symbol
Ratings
Conditions
Unit
8
4
TA = +25 °C, excepte X32_IN pin
TA = +25 °C
Electrostatic discharge voltage (human
body model)
V
V
ESD(HBM)
kV
1
TA = +25 °C, excepte X32_IN pin
TA = +25 °C
Electrostatic discharge voltage (charge
device model)
ESD(CDM)
0.5
Note: Guaranteed by characterization results, not tested in production.
Symbol
Parameter
Static latch-up class
Conditions
Value
300
Unit
LU
mA
T
+25 °C
A
Note: Guaranteed by characterization results, not tested in production.
Aug. 24, 2018
Page 61 of 82
Rev 1.00
NUC2201
8.2 DC Electrical Characteristics
(VDD-VSS = 5.5 V, TA = 25C, FOSC = 72 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
VDD
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Operation Voltage
2.5
5.5
5.5
0.3
V
V
V
VDD = 2.5V ~ 5.5V up to 72 MHz
RTC Operation
voltage for
PF.0~PF.2
VBAT
2.5
-
VSS
Power Ground
-0.3
0
AVSS
LDO Output Voltage
VLDO
1.62
1.21
-0.3
1.8
1.98
1.29
0.3
V
V
V
VDD ≥ 2.5V
Band-gap Voltage
VBG
-
-
VDD = 2.5 V ~ 5.5 V, TA = -40C~105C
Allowed voltage
difference for VDD
and AVDD
VDD
-
AVDD
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
at 72 MHz
IDD1
24
mA
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
X
V
X
V
X
V
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
16
mA
mA
mA
mA
mA
mA
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
while(1){} executed
from flash
22.5
14.5
18
VLDO =1.8 V
Operating Current
Normal Run Mode
at 50 MHz
12.5
16.5
while(1){} executed
from flash
IDD8
11
mA
3.3V
VLDO =1.8 V
12 MHz
X
V
V
V
V
X
X
X
X
V
X
V
Operating Current
Normal Run Mode
at 22.1184 MHz
IDD9
IDD10
IDD11
-
-
-
9
4.5
9
-
-
-
mA
mA
mA
5.5V
5.5V
3.3V
X
X
X
while(1){} executed
from flash
IDD12
-
4.5
-
mA
3.3V
VLDO =1.8 V
X
V
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
X
V
Operating Current
Normal Run Mode
at 12 MHz
IDD13
IDD14
IDD15
IDD16
IDD17
5.5
4.5
4
mA
mA
mA
mA
mA
5.5V
5.5V
3.3V
3.3V
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
while(1){} executed
from flash
3
VLDO =1.8 V
Operating Current
3
Aug. 24, 2018
Page 62 of 82
Rev 1.00
NUC2201
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
2.5
MAX. UNIT
Normal Run Mode
at 4 MHz
IDD18
IDD19
mA
mA
5.5V
3.3V
4 MHz
X
X
X
X
X
V
1.7
4 MHz
4 MHz
while(1){} executed
from flash
IDD20
1.3
mA
3.3V
VDD
X
X
X
VLDO =1.8 V
LXT
All digital
modules
HIRC
PLL
(kHz)
IDD21
133
uA
Operating Current
HCLK = 32.768 kHz
while(1){}
5.5V
5.5V
3.3V
3.3V
32.768
32.768
32.768
32.768
X
X
X
X
X
X
X
X
V
X
V
X
uA
uA
uA
IDD22
IDD23
IDD24
130
119
116
executed from flash
All digital
module
VDD
HXT/LXT LIRC (kHz)
PLL
Operating Current
Normal Run Mode
at 10 kHz
IDD25
127
A
5.5V
5.5V
3.3V
3.3V
X
X
X
X
10
10
10
10
X
X
X
X
V
X
V
X
IDD26
IDD27
IDD28
126
113
112
A
A
A
while(1){} executed
from flash
VLDO =1.8 V
All digital
module
VDD
HXT
HIRC
PLL
IIDLE1
17
mA
Operating Current
Idle Mode
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
12 MHz
X
X
X
X
V
V
V
V
V
V
V
V
X
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
V
X
V
X
X
X
V
X
X
X
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
9
15.5
7.5
13
7.5
11.5
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
12 MHz
at 72 MHz
VLDO =1.8 V
12 MHz
12 MHz
X
Operating Current
Idle Mode
X
at 50 MHz
X
VLDO =1.8 V
X
-
-
-
-
6.5
2
-
-
-
-
X
Operating Current
Idle Mode
X
X
at 22.1184 MHz
VLDO =1.8 V
6.5
2
X
4.3
3
12 MHz
12 MHz
Operating Current
Idle Mode
at 12 MHz
IIDLE15
IIDLE16
2.9
1.6
mA
mA
3.3V
3.3V
12 MHz
12 MHz
X
X
X
X
V
X
VLDO =1.8 V
Aug. 24, 2018
Page 63 of 82
Rev 1.00
NUC2201
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
2.6
MAX. UNIT
IIDLE17
IIDLE18
IIDLE19
IIDLE20
mA
mA
5.5V
5.5V
4 MHz
X
X
X
X
V
X
Operating Current
Idle Mode
2.2
4 MHz
4 MHz
4 MHz
at 4 MHz
1.4
0.9
mA
mA
3.3V
3.3V
X
X
X
X
V
X
VLDO =1.8 V
LXT
All digital
modules
VDD
HIRC
PLL
(kHz)
IIDLE21
130
A
5.5V
5.5V
3.3V
3.3V
32.768
32.768
32.768
32.768
X
X
X
X
X
X
X
X
V
X
V
X
Operating Current
Idle Mode
IIDLE22
IIDLE23
IIDLE24
126
116
113
A
A
A
at 32.768 kHz
All digital
module
VDD
HXT/LXT LIRC (kHz)
PLL
X
IIDLE25
126
A
5.5V
5.5V
X
X
X
X
10
10
10
10
V
X
V
X
Operating Current
Idle Mode
IIDLE26
IIDLE27
IIDLE28
125
112
111
A
A
A
X
at 10 kHz
3.3V
3.3V
X
X
HXT/HIRC
PLL
RAM
retension
VDD
LXT (kHz)
RTC
IPWD1
13
A
Standby Current
Power-down Mode
(Deep Sleep Mode)
VLDO =1.6 V
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
V
X
V
V
V
V
V
IPWD2
IPWD3
IPWD4
15
11
13
A
A
A
32.768
X
32.768
VBAT = 5.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power domain
OFF.
2
2
A
A
RTC Operating
Current
IVBAT
VBAT = 3.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power domain
OFF.
Input Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
mode)
IIN1
-67
-
-75
+1
VDD = VBAT = 5.5V, VIN = 0V or VIN=VDD
A
A
Input Leakage
Current PA, PB, PC,
PD, PE, PF
VDD = VBAT = 5.5V, 0<VIN<VDD
ILK
-1
Open-drain or input only mode.
Aug. 24, 2018
Page 64 of 82
Rev 1.00
NUC2201
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Logic 1 to 0
Transition Current
PA~PF (Quasi-
[3]
ITL
-610
-650
VDD = 5.5V, VIN=2.0V
A
bidirectional mode)
Input Low Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
-0.3
-0.3
-
-
0.8
0.6
VDD = VBAT = 4.5 V
VDD = VBAT = 2.5 V
VIL1
VIH1
VIL3
VIH3
V
VDD
+0.2
2.0
1.5
-
-
VDD = VBAT = 5.5V
VDD = VBAT =3.0V
Input High Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
V
VDD
+0.2
0
0
-
-
0.8
0.4
VDD = VBAT = 4.5V
VDD = VBAT = 3.0V
Input Low Voltage
XT1_IN[*2]
V
V
VDD
+0.3
3.5
-
-
VDD = VBAT = 5.5V
VDD = VBAT = 3.0V
Input High Voltage
XT1_IN[*2]
VDD
+0.3
2.4
0.6
0
X32 Output Pin
VXOUT
0.9
V
Input Low Voltage
X32I[*4]
VXOUT -
0.3
VIL4
-
V
Input High Voltage
X32I[*4]
VXOUT
+0.3
VIH4
1.8
V
V
Negative going
threshold
VILS
-0.3
-
-
0.2VDD
(Schmitt input),
nRESET
Positive going
threshold
VDD
+0.3
VIHS
0.7 VDD
V
(Schmitt input),
nRESET
Internal nRESET pin
pull up resistor
RRST
40
150
kΩ
Negative going
threshold
0.3
VDD
VILS
-0.3
-
-
V
(Schmitt input),
Positive going
threshold
VDD
+0.3
VIHS
0.7 VDD
V
(Schmitt input),
ISR11
ISR12
ISR12
ISR21
ISR22
-300
-50
-40
-30
-3
-400
-80
VDD = VBAT = 4.5V, VS = 2.4V
VDD = VBAT = 2.7V, VS = 2.2V
VDD = VBAT = 2.5V, VS = 2.0V
A
A
A
Source Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
Mode)
-73
-65
mA VDD = VBAT = 4.5V, VS = 2.4V
mA VDD = VBAT = 2.7V, VS = 2.2V
Source Current PA,
PB, PC, PD, PE, PF
(Push-pull Mode)
-5.2
Aug. 24, 2018
Page 65 of 82
Rev 1.00
NUC2201
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
-2.5
9
TYP.
-5
MAX. UNIT
ISR22
ISK1
ISK1
ISK1
mA VDD = VBAT = 2.5V, VS = 2.0V
13
9
mA VDD = VBAT = 4.5V, VS = 0.45V
mA VDD = VBAT = 2.7V, VS = 0.45V
mA VDD = VBAT = 2.5V, VS = 0.45V
Sink Current PA, PB,
PC, PD, PE, PF
(Quasi-bidirectional
and Push-pull Mode)
6
4
8
Note:
1. nRESET pin is a Schmitt trigger input.
2. XT1_IN is a CMOS input.
3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
4. If X32I is as external clock input, the input high voltage should be lower than 1.8V to avoid chip damage.
Aug. 24, 2018
Page 66 of 82
Rev 1.00
NUC2201
8.3 AC Electrical Characteristics
8.3.1 External 4~24 MHz High Speed Oscillator
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
Parameter
Min
10
10
2
Typ
Max
-
Unit
Test Condition
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
ns
ns
ns
ns
-
-
-
-
tCLCX
-
tCLCH
15
15
tCHCL
2
8.3.2 External 4~24 MHz High Speed Crystal
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
-
-
-
-
TA
℃
2
mA
mA
MHz
12 MHz, VDD = 5.5V
IHXT
Operating Current
Clock Frequency
-
0.8
-
-
12 MHz, VDD = 3.3V
-
fHXT
4
24
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
10~20pF
C2
10~20pF
R
4 MHz ~ 24 MHz
without
Aug. 24, 2018
Page 67 of 82
Rev 1.00
NUC2201
XT1_OUT
XT1_IN
R
C1
C2
Figure 8-1 Typical Crystal Application Circuit
8.3.3 32.768 kHz External Low Speed Crystal Oscillator (LXT)
tCLCL
tCLCH
90%
10%
Xin_VIH
tCLCX
Xin_VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
PARAMETER
CONDITION
MIN.
2.5
TYP.
MAX.
5.5
UNIT
Operation Voltage VDD
Operation Temperature
Operation Current
-
-
-
-
V
℃
-40
105
32.768KHz at VDD=5V
External crystal
1.6
A
Clock Frequency
-
32.768
-
kHz
8.3.3.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
10~20 pF
32.768 kHz
10~20 pF
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Aug. 24, 2018
Page 68 of 82
Rev 1.00
NUC2201
Figure 8.3-2 Typical Crystal Application Circuit
8.3.4 Internal 22.1184 MHz High Speed Oscillator
Symbol
Parameter
Supply Voltage
Center Frequency
Min
1.62
-
Typ
1.8
Max
Unit
V
Test Conditions
VHRC
1.98
-
-
22.1184
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40 ℃ ~ 105 ℃
-3
-
+3
%
VDD = 2.5 V ~ 5 .5 V
TA = 25 ℃,VDD = 5 V
IHRC
Operating Current
-
1200
-
μA
8.3.5 Internal 48 MHz High Speed Oscillator
Symbol
Parameter
Supply Voltage
Center Frequency
Min
1.62
-
Typ
1.8
48
Max
Unit
V
Test Conditions
VHRC
1.98
-
-
MHz
TA = 25 ℃
-1
-
+1
%
fHRC
VDD = 5 V
Calibrated Internal
Oscillator Frequency
TA = -40 ℃ ~ 105 ℃
-2
-
+2
%
VDD = 2.5 V ~ 5 .5 V
TA = 25 ℃,VDD = 5 V
IHRC
Operating Current
-
640
-
μA
Aug. 24, 2018
Page 69 of 82
Rev 1.00
NUC2201
8.3.6 Internal 10 kHz Low Speed Oscillator
Symbol
Parameter
Supply Voltage
Center Frequency
Min
2.5
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
VLRC
-
-
10
kHz
VDD = 2.5 V ~ 5.5 V
-10
-50
-
-
+10
+50
%
%
TA = 25℃
fLRC
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40℃ ~ +105℃
8.3.7 PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4
24
fPLL_IN
fPLL_OUT
TS
PLL input clock
MHz
MHz
µs
50
500
200
350
PLL multiplier output clock
PLL stable time[*1]
100
Jitter
200
ps
Cycle-to-cycle Jitter[*2]
Peak to peak @ 480M
Note: Guaranteed by characterization and design results, not tested in production.
Aug. 24, 2018
Page 70 of 82
Rev 1.00
NUC2201
8.4 Analog Characteristics
8.4.1 12-bit SARADC Specification
Symbol
-
Parameter
Min
Typ
Max
Unit
Bit
Test Condition
Resolution
12
-
-
-
-
-
-
-
DNL
INL
EO
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
-
-
-
-
-
-
±3
±4
-
LSB
LSB
LSB
LSB
LSB
-
-
3
EG
Gain Error (Transfer Gain)
Absolute Error
-2
-
EA
4
-
-
Monotonic
Guaranteed
FADC
FS
ADC Clock Frequency
-
-
-
21
MHz
kSPS
1/FADC
1/FADC
V
Sample Rate (FADC/TCONV
)
-
2~9
16~23
-
1000
TACQ
TCONV
AVDD
IDDA
VIN
Acquisition Time (Sample Stage)
Total Conversion Time
Supply Voltage
-
-
2.5
5.5
-
Supply Current (Avg.)
Analog Input Voltage
Input Capacitance
-
0
-
2.8
-
-
mA
AVDD = 5 V
AVDD
V
-
-
-
CIN
6
-
-
pF
RIN
Input Load
-
6.5
kΩ
Note: The condition is that the error in a conversion started after ADC enable is less than ±0.5 LSB. The
reference and input signal are already settled.
Aug. 24, 2018
Page 71 of 82
Rev 1.00
NUC2201
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve
and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from
the actual transfer curve.
8.4.2 LDO and Power Management
Symbol
VDD
Parameter
DC Power Supply
Output Voltage
Temperature
Min
2.5
Typ
-
Max
5.5
Unit
V
Test Condition
-
-
VLDO
1.62
-40
1.8
25
1.98
105
V
℃
TA
Notes:
1. It is recommended that a 0.1 uF or higher capacitor is connected between VDD and the closest VSS pin of
the device.
2. To ensure power stability, a 1uF or higher capacitor must be connected between LDO pin and the closest
VSS pin of the device.
Aug. 24, 2018
Page 72 of 82
Rev 1.00
NUC2201
8.4.3 Low Voltage Reset Specification
Symbol
VDD
Parameter
Supply Voltage
Temperature
Min
0
Typ
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
TA
-40
-
25
1
105
5
-
ILVR
Quiescent Current
VDD = 5.5 V
TA = 25 ℃
TA = -40 ℃
TA = 105 ℃
1.90
1.70
2.00
2.00
1.90
2.20
2.10
2.10
2.45
VLVR
Threshold Voltage
V
V
8.4.4 Brown-out Detector Specification
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-40
-
25
105
140
4.6
-
IBOD
Quiescent Current
-
AVDD = 5.5 V
4.2
3.5
2.55
2.05
4.3
3.6
2.6
2.1
4.4
3.7
2.7
2.2
4.5
3.8
2.75
2.25
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
3.9
V
Brown-out Voltage
VBOD
(Falling edge)
2.85
2.35
4.7
V
V
V
4.0
V
Brown-out Voltage
VBOD
(Rising edge)
2.9
V
2.4
V
8.4.5 Power-on Reset Specification
Symbol
TA
Parameter
Temperature
Reset Voltage
Min
-40
1.6
Typ
25
2
Max
105
2.4
Unit
℃
Test Condition
-
-
VPOR
V
VDD Start Voltage to Ensure
VPOR
RRVDD
tPOR
-
-
-
-
100
mV
V/ms
ms
Power-on Reset
VDD Raising Rate to Ensure
0.025
0.5
-
-
Power-on Reset
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
Note: Guaranteed by characterization results, not tested in production.
Aug. 24, 2018
Page 73 of 82
Rev 1.00
NUC2201
VDD
tPOR
RRVDD
VPOR
Time
Figure 8-3 Power-up Ramp Condition
8.4.6
Temperature Sensor
Symbol
Parameter
Temperature
Current Consumption
Gain
Min
-40
-
Typ
-
Max
105
-
Unit
Test Condition
℃
μA
TA
ITEMP
16
mV/℃
-
-
-1.55
735
-1.672
748
-1.75
755
TA = 0 ℃
Offset
mV
Note:
1. Guaranteed by design, not tested in production.
2. VTEMP (mV) = Tc (mV/°C) x Temperature (°C) + Vos (mV)
Aug. 24, 2018
Page 74 of 82
Rev 1.00
NUC2201
8.4.7 USB PHY
8.4.7.1 Low-/full-Speed DC Electrical Specifications
Symbol
Parameter
Input High (driven)
Min.
2.0
-
Typ.
Max.
Unit
V
Test Conditions
VIH
VIL
VDI
-
-
-
-
Input Low
0.8
V
-
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
VSE
0.8
-
2.5
2.0
V
Includes VDI range
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
0.8
-
V
mV
V
-
-
0
200
-
VOL
VOH
VCRS
RPU
ZDRV
CIN
Output Low (driven)
-
-
0.3
3.6
2.0
1.575
-
-
Output High (driven)
2.8
1.3
1.425
-
V
-
Output Signal Cross Voltage
Pull-up Resistor
-
V
-
-
-
kΩ
Ω
Driver Output Resistance
Transceiver Capacitance
10
-
Steady state drive*
Pin to GND
-
20
pF
*Driver output resistance doesn’t include series resistor resistance.
8.4.7.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Min.
4
Typ.
Max.
20
Unit
ns
Test Conditions
CL=50p
TFR
TFF
Rise Time
Fall Time
-
-
-
4
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
111.11
%
TFRFF=TFR/TFF
8.4.7.3 USB LDO Specification
Symbol
VBUS
Parameter
VBUS Pin Input Voltage
LDO Output Voltage
Min.
4.0
2.97
-
Typ.
5.0
Max.
5.5
3.63
-
Unit
V
Test Conditions
-
-
-
VDD33
Cbp
3.3
V
External Bypass Capacitor
1.0
uF
Aug. 24, 2018
Page 75 of 82
Rev 1.00
NUC2201
8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
1.62
Typ
Max
Unit
V
Test Condition
[2]
VFLA
1.8
1.98
-
NENDUR
20,000
100
-
-
cycles[1]
year
-
TA = 25℃
-
TRET
Data Retention
TA = 85℃
10
20
60
-
year
ms
TERASE
TPROG
IDD1
Page Erase Time
Program Time
Read Current
-
-
-
-
-
-
-
-
-
-
us
9
8
mA
mA
mA
IDD2
Program Current
Erase Current
-
IDD3
-
12
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
Aug. 24, 2018
Page 76 of 82
Rev 1.00
NUC2201
8.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
Max.
-
Min.
Max.
-
tLOW
SCL low period
1.2
0.6
1.2
uS
uS
uS
tHIGH
SCL high period
4
-
-
-
-
tSU; STA
Repeated START condition setup
time
4.7
tHD; STA
tSU; STO
tBUF
START condition hold time
STOP condition setup time
Bus free time
4
-
-
0.6
-
-
uS
uS
uS
nS
uS
nS
nS
pF
4
4.7[3]
250
0[4]
-
0.6
-
1.2[3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
-
-
-
Cb
Capacitive load for each bus line
-
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8-4 I2C Timing Diagram
Aug. 24, 2018
Page 77 of 82
Rev 1.00
NUC2201
8.7 SPI Dynamic Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
SPI Master Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
1
2
SPI Master Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
2
4
SPI Slave Mode (VDD = 4.5 V ~ 5.5 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
3.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
16
22
SPI Slave Mode (VDD = 3.0 V ~ 3.6 V, 0 pF loading Capacitor)
tDS
tDH
tV
Data setup time
0
4.5
-
-
-
-
-
ns
ns
ns
Data hold time
Data output valid time
18
24
CLKP=0
CLKP=1
SPICLK
tV
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
Figure 8-5 SPI Master Mode Timing Diagram
Aug. 24, 2018
Page 78 of 82
Rev 1.00
NUC2201
CLKP=0
CLKP=1
SPICLK
tDS
tDH
Data Valid
Data Valid
MOSI
MISO
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tv
Data Valid
tDS
tDH
Data Valid
Data Valid
Data Valid
MOSI
MISO
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tv
Data Valid
Figure 8-6 SPI Slave Mode Timing Diagram
Aug. 24, 2018
Page 79 of 82
Rev 1.00
NUC2201
9
PACKAGE DIMENSIONS
9.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Aug. 24, 2018
Page 80 of 82
Rev 1.00
NUC2201
9.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Aug. 24, 2018
Page 81 of 82
Rev 1.00
NUC2201
10 REVISION HISTORY
Date
Revision
Description
2018.08.24
1.00
1. Initial version
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Aug. 24, 2018
Page 82 of 82
Rev 1.00
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明