NUC930-SC3C [NUVOTON]
ARM® Cortexâ¢-M0 core;
| 型号： | NUC930-SC3C |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortexâ¢-M0 core |
| 文件： | 总97页 (文件大小：2971K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NuMicro NUC230/240 Datasheet
NuMicro™ NUC230/240 Series
DataSheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicroTM microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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TABLE OF CONTENTS
LIST OF FIGURES .....................................................................................................6
LIST OF TABLES.......................................................................................................7
1 GENERAL DESCRIPTION.....................................................................................8
2 FEATURES ............................................................................................................9
2.1 NuMicro NUC230 Features – Automotive Line............................................ 9
2.2 NuMicro NUC240 Features – Connectivity Line..........................................13
3 ABBREVIATIONS................................................................................................17
4 PARTS INFORMATION LIST AND PIN CONFIGURATION................................19
4.1 NuMicro NUC230/240xxxAE Selection Guide ............................................19
4.1.1 NuMicro NUC230 Automotive Line Selection Guide ......................................... 19
4.1.2 NuMicro NUC240 Connectivity Line Selection Guide ........................................ 19
4.2 Pin Configuration................................................................................21
4.2.1 NuMicro NUC230 Pin Diagram.................................................................. 21
4.2.2 NuMicro NUC240 Pin Diagram.................................................................. 24
4.3 Pin Description ..................................................................................27
4.3.1 NuMicro NUC230 Pin Description............................................................... 27
4.3.2 NuMicro NUC240 Pin Description............................................................... 35
5 BLOCK DIAGRAM...............................................................................................43
5.1 NuMicro NUC230 Block Diagram...........................................................43
5.2 NuMicro NUC240 Block Diagram...........................................................44
6 FUNCTIONAL DESCRIPTION.............................................................................45
6.1 ARM® Cortex™-M0 Core......................................................................45
6.2 System Manager ................................................................................47
6.2.1 Overview.............................................................................................. 47
6.2.2 System Reset ........................................................................................ 47
6.2.3 System Power Distribution ......................................................................... 48
6.2.4 System Memory Map ............................................................................... 50
6.2.5 System Timer (SysTick) ............................................................................ 52
6.2.6 Nested Vectored Interrupt Controller (NVIC) .................................................... 53
6.2.7 System Control....................................................................................... 56
6.3 Clock Controller .................................................................................57
6.3.1 Overview.............................................................................................. 57
6.3.2 System Clock and SysTick Clock ................................................................. 60
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6.3.3 Power-down Mode Clock........................................................................... 61
6.3.4 Frequency Divider Output .......................................................................... 62
6.4 Flash Memory Controller (FMC) ..............................................................63
6.4.1 Overview.............................................................................................. 63
6.4.2 Features .............................................................................................. 63
6.5 External Bus Interface (EBI)...................................................................64
6.5.1 Overview.............................................................................................. 64
6.5.2 Features .............................................................................................. 64
6.6 General Purpose I/O (GPIO) ..................................................................65
6.6.1 Overview.............................................................................................. 65
6.6.2 Features .............................................................................................. 65
6.7 PDMA Controller (PDMA)......................................................................65
6.7.1 Overview.............................................................................................. 65
6.7.2 Features .............................................................................................. 66
6.8 Timer Controller (TIMER) ......................................................................66
6.8.1 Overview.............................................................................................. 66
6.8.2 Features .............................................................................................. 67
6.9 PWM Generator and Capture Timer (PWM) ................................................68
6.9.1 Overview.............................................................................................. 68
6.9.2 Features .............................................................................................. 69
6.10Watchdog Timer (WDT)........................................................................70
6.10.1 Overview.............................................................................................. 70
6.10.2 Features .............................................................................................. 70
6.11Window Watchdog Timer (WWDT)...........................................................71
6.11.1 Overview.............................................................................................. 71
6.11.2 Features .............................................................................................. 71
6.12Real Time Clock (RTC) ........................................................................71
6.12.1 Overview.............................................................................................. 71
6.12.2 Features .............................................................................................. 71
6.13UART Interface Controller (UART) ...........................................................72
6.13.1 Overview.............................................................................................. 72
6.13.2 Features .............................................................................................. 72
6.14Smart Card Host Interface (SC)...............................................................73
6.14.1 Overview.............................................................................................. 73
6.14.2 Features .............................................................................................. 73
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6.15PS/2 Device Controller (PS2D) ...............................................................74
6.15.1 Overview.............................................................................................. 74
6.15.2 Features .............................................................................................. 74
6.16I2C Serial Interface Controller (I2C)...........................................................75
6.16.1 Overview.............................................................................................. 75
6.16.2 Features .............................................................................................. 75
6.17Serial Peripheral Interface (SPI) ..............................................................75
6.17.1 Overview.............................................................................................. 75
6.17.2 Features .............................................................................................. 76
6.18I2S Controller (I2S) ..............................................................................76
6.18.1 Overview.............................................................................................. 76
6.18.2 Features .............................................................................................. 76
6.19USB Device Controller (USBD) ...............................................................77
6.19.1 Overview.............................................................................................. 77
6.19.2 Features .............................................................................................. 77
6.20Controller Area Network (CAN) ...............................................................78
6.20.1 Overview.............................................................................................. 78
6.20.2 Features .............................................................................................. 78
6.21Analog-to-Digital Converter (ADC) ...........................................................78
6.21.1 Overview.............................................................................................. 78
6.21.2 Features .............................................................................................. 78
6.22Analog Comparator (ACMP)...................................................................79
6.22.1 Overview.............................................................................................. 79
6.22.2 Features .............................................................................................. 79
7 APPLICATION CIRCUIT......................................................................................80
8 ELECTRICAL CHARACTERISTICS....................................................................81
8.1 Absolute Maximum Ratings ...................................................................81
8.2 DC Electrical Characteristics ..................................................................82
8.3 AC Electrical Characteristics ..................................................................87
8.3.1 External 4~24 MHz High Speed Oscillator....................................................... 87
8.3.2 External 4~24 MHz High Speed Crystal.......................................................... 87
8.3.3 External 32.768 kHz Low Speed Crystal Oscillator............................................. 88
8.3.4 Internal 22.1184 MHz High Speed Oscillator.................................................... 88
8.3.5 Internal 10 kHz Low Speed Oscillator ............................................................ 88
8.4 Analog Characteristics .........................................................................89
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8.4.1 12-bit SARADC Specification ...................................................................... 89
8.4.2 LDO and Power Management Specification..................................................... 89
8.4.3 Low Voltage Reset Specification .................................................................. 90
8.4.4 Brown-out Detector Specification ................................................................. 90
8.4.5 Power-on Reset Specification ..................................................................... 90
8.4.6 Temperature Sensor Specification................................................................ 91
8.4.7 Comparator Specification........................................................................... 91
8.4.8 USB PHY Specification ............................................................................. 92
8.5 Flash DC Electrical Characteristics...........................................................93
9 PACKAGE DIMENSIONS ....................................................................................94
9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm)...........................................94
9.2 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ...............................................95
9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ...............................................96
10REVISION HISTORY............................................................................................97
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LIST OF FIGURES
Figure 4-1 NuMicro NUC230/240 Series Selection Code........................................................... 20
Figure 4-2 NuMicro NUC230VxxAE LQFP 100-pin Diagram...................................................... 21
Figure 4-3 NuMicro NUC230SxxAE LQFP 64-pin Diagram........................................................ 22
Figure 4-4 NuMicro NUC230LxxAE LQFP 48-pin Diagram........................................................ 23
Figure 4-5 NuMicro NUC240VxxAE LQFP 100-pin Diagram...................................................... 24
Figure 4-6 NuMicro NUC240SxxAE LQFP 64-pin Diagram........................................................ 25
Figure 4-7 NuMicro NUC240LxxAE LQFP 48-pin Diagram........................................................ 26
Figure 5-1 NuMicro NUC230 Block Diagram .............................................................................. 43
Figure 5-2 NuMicro NUC240 Block Diagram .............................................................................. 44
Figure 6-1 Functional Controller Diagram...................................................................................... 45
Figure 6-2 NuMicro NUC230 Power Distribution Diagram.......................................................... 48
Figure 6-3 NuMicro NUC240 Power Distribution Diagram.......................................................... 49
Figure 6-4 Clock Generator Block Diagram................................................................................... 58
Figure 6-5 Clock Generator Global View Diagram......................................................................... 59
Figure 6-6 System Clock Block Diagram ....................................................................................... 60
Figure 6-7 SysTick Clock Control Block Diagram.......................................................................... 60
Figure 6-8 Clock Source of Frequency Divider.............................................................................. 62
Figure 6-9 Frequency Divider Block Diagram................................................................................ 62
Figure 8-1 Typical Crystal Application Circuit ................................................................................ 88
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LIST OF TABLES
Table 1-1 NuMicro NUC230/240 Series Connectivity Support Table ........................................... 8
Table 3-1 List of Abbreviations....................................................................................................... 18
Table 6-1 Address Space Assignments for On-Chip Controllers................................................... 51
Table 6-2 Exception Model ............................................................................................................ 54
Table 6-3 System Interrupt Map..................................................................................................... 55
Table 6-4 Vector Table Format ...................................................................................................... 56
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1
GENERAL DESCRIPTION
The NuMicro NUC230/240 series 32-bit microcontrollers are embedded with the ARM®
Cortex™-M0 core with a cost equivalent to traditional 8-bit MCU for industrial control and
applications requiring rich communication interfaces. The NuMicro NUC230/240 series includes
NUC230 and NUC240 product lines.
The NuMicro NUC230 CAN Line is embedded with the Cortex™-M0 core running up to 72 MHz
and features 32K/64K/128K bytes flash, 8K/16K bytes embedded SRAM, and 8 Kbytes loader
ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers, Watchdog
Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S,
PWM Timer, GPIO, LIN, CAN, PS/2, Smart Card Host, 12-bit ADC, Analog Comparator, Low
Voltage Reset Controller and Brown-out Detector.
The NuMicro NUC240 Connectivity Line with USB 2.0 full-speed and CAN functions is
embedded with the Cortex™-M0 core running up to 72 MHz and features 32K/64K/128K bytes
flash, 8K/16K bytes embedded SRAM, and 8 Kbytes loader ROM for the ISP. It is also equipped
with plenty of peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer,
RTC, PDMA with CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2,
USB 2.0 FS Device, Smart Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset
Controller and Brown-out Detector.
Product Line
NUC230
UART
●
SPI
●
I2C
●
USB
LIN
●
CAN
●
PS/2
●
I2S
●
●
SC
●
●
●
●
●
●
●
●
●
NUC240
Table 1-1 NuMicro NUC230/240 Series Connectivity Support Table
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2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 NuMicro NUC230 Features – Automotive Line
ARM® Cortex™-M0 core
– Runs up to 72 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
– 32K/64K/128K bytes Flash for program code
– 8 KB flash for ISP loader
– Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for flash
– Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the
32 KB and 64 KB system
– Supports 2-wired ICP update through SWD/ICE interface
– Supports fast parallel programming mode by external programmer
SRAM Memory
– 8K/16K bytes embedded SRAM
– Supports PDMA mode
PDMA (Peripheral DMA)
– Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals
– Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and
CRC-32
Clock Control
– Flexible selection for different applications
– Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±3 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL, up to 72 MHz, for high performance system operation
– External 4~24 MHz high speed crystal input for precise timing operation
– External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
– Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level setting
Timer
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
Watchdog Timer
– Multiple clock sources
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– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
– Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK)
Window Watchdog Timer
– 6-bit down counter with 11-bit prescale for wide range window selected
RTC
– Supports software compensation by setting frequency compensate register (FCR)
– Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
– Supports Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4,
1/2 and 1 second
– Supports battery power pin (VBAT)
– Supports wake-up function
PWM/Capture
– Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM
– Supports One-shot or Auto-reload mode
– Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
– Supports Capture interrupt
UART
– Up to six UART controllers (three UART controllers are shared with SC)
– UART ports with flow control (TXD, RXD, nCTS and nRTS)
– UART0 with 64-byte FIFO is for high speed
– UART1/2(optional) with 16-byte FIFO for standard device
– Supports IrDA (SIR) and LIN function
– Supports RS-485 9-bit mode and direction control
– Programmable baud-rate generator up to 1/16 system clock
– Supports CTS wake-up function (UART0 and UART1 support)
– Supports PDMA mode
Smart Card Host (SC)
– Supports up to three ISO-7816-3 ports
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card is removal
– Supports up to three UART ports
Full duplex, asynchronous communications
Supports receiving / transmitting 4-bytes FIFO
Supports programmable baud rate generator for each channel
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
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SPI
– Up to four sets of SPI controllers
– The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
– The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
– Supports SPI Master/Slave mode
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 8 to 32 bits
– MSB or LSB first data transfer
– Rx and Tx on both rising or falling edge of serial clock independently
– Two slave/device select lines in Master mode, and one slave/device select line in Slave
mode
– Supports Byte Suspend mode in 32-bit transmission
– Supports PDMA mode
– Supports three wire, no slave select signal, bi-direction interface
I2C
– Up to two sets of I2C devices
– Master/Slave mode
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
– Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
– Programmable clocks allowing for versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports wake-up function
I2S
– Interface with external audio CODEC
– Operate as either Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports mono and stereo audio data
– Supports I2S and MSB justified data format
– Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
– Host communication inhibit and request to send detection
– Reception frame error detection
– Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
– Double buffer for data reception
– Software override bus
CAN 2.0
– Supports CAN protocol version 2.0 part A and B
– Bit rates up to 1M bit/s
– 32 Message Objects
– Each Message Object has its own identifier mask
– Programmable FIFO mode (concatenation of Message Object)
– Maskable interrupt
– Disabled Automatic Re-transmission mode for Time Triggered CAN applications
– Support wake-up function
ADC
– 12-bit SAR ADC with 1 MSPS (chip working at 5V)
– Up to 8-ch single-end input or 4-ch differential input
– Single scan/single cycle scan/continuous scan
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– Each channel with individual result register
– Scan on enabled channels
– Threshold voltage detection
– Conversion started by software programming, external input or PWM Center-aligned trigger
– Supports PDMA mode
Analog Comparator
– Up to two analog comparators
– External input or internal Band-gap voltage selectable at negative node
– Interrupt when compare result change
– Supports Power-down wake-up
EBI (External bus interface)
– Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
– Supports 8-/16-bit data width
– Supports byte write in 16-bit data width mode
96-bit unique ID (UID)
128-bit unique customer ID(UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 105℃
Packages:
– All Green package (RoHS)
– LQFP 100-pin / 64-pin / 48-pin
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2.2 NuMicro NUC240 Features – Connectivity Line
ARM® Cortex™-M0 core
– Runs up to 72 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
– 32K/64K/128K bytes Flash for program code
– 8 KB flash for ISP loader
– Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for flash
– Configurable Data Flash address and size for 128 KB system, fixed 4 KB Data Flash for the
32 KB and 64 KB system
– Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
– 8K/16K bytes embedded SRAM
– Supports PDMA mode
PDMA (Peripheral DMA)
– Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals
– Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and
CRC-32
Clock Control
– Flexible selection for different applications
– Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃ and VDD = 5 V
Trimmed to ±3 % at -40 ℃ ~ +105 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL, up to 72 MHz, for high performance system operation
– External 4~24 MHz high speed crystal input for USB and precise timing operation
– External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
– Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level setting
Timer
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
Watchdog Timer
– Multiple clock sources
– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
– Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK)
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Window Watchdog Timer
– 6-bit down counter with 11-bit prescale for wide range window selected
RTC
– Supports software compensation by setting frequency compensate register (FCR)
– Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
– Supports Alarm registers (second, minute, hour, day, month, year)
– Selectable 12-hour or 24-hour mode
– Automatic leap year recognition
– Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4,
1/2 and 1 second
– Supports battery power pin (VBAT)
– Supports wake-up function
PWM/Capture
– Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM
– Supports One-shot or Auto-reload mode
– Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
– Supports Capture interrupt
UART
– Up to six UART controllers (three UART controllers are shared with SC)
– UART ports with flow control (TXD, RXD, nCTS and nRTS)
– UART0 with 64-byte FIFO is for high speed
– UART1/2(optional) with 16-byte FIFO for standard device
– Supports IrDA (SIR) and LIN function
– Supports RS-485 9-bit mode and direction control
– Programmable baud-rate generator up to 1/16 system clock
– Supports CTS wake-up function (UART0 and UART1 support)
– Supports PDMA mode
Smart Card Host (SC)
– Supports up to three ISO-7816-3 ports
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card is removal
– Supports up to three UART ports
Full duplex, asynchronous communications
Supports receiving / transmitting 4-bytes FIFO
Supports programmable baud rate generator for each channel
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1 or 2 stop bit generation
SPI
– Up to four sets of SPI controllers
– The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
– The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
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– Supports SPI Master/Slave mode
– Full duplex synchronous serial data transfer
– Variable length of transfer data from 8 to 32 bits
– MSB or LSB first data transfer
– Rx and Tx on both rising or falling edge of serial clock independently
– Two slave/device select lines in Master mode, and one slave/device select line in Slave
mode
– Supports Byte Suspend mode in 32-bit transmission
– Supports PDMA mode
– Supports three wire, no slave select signal, bi-direction interface
I2C
– Up to two sets of I2C devices
– Master/Slave mode
– Bidirectional data transfer between masters and slaves
– Multi-master bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
– Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
– Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
– Programmable clocks allowing for versatile rate control
– Supports multiple address recognition (four slave address with mask option)
– Supports wake-up function
I2S
– Interface with external audio CODEC
– Operate as either Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports mono and stereo audio data
– Supports I2S and MSB justified data format
– Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
– Host communication inhibit and request to send detection
– Reception frame error detection
– Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
– Double buffer for data reception
– Software override bus
CAN 2.0
– Supports CAN protocol version 2.0 part A and B
– Bit rates up to 1M bit/s
– 32 Message Objects
– Each Message Object has its own identifier mask
– Programmable FIFO mode (concatenation of Message Object)
– Maskable interrupt
– Disabled Automatic Re-transmission mode for Time Triggered CAN applications
– Supports Power-down wake-up function
USB 2.0 Full-Speed Device
– One set of USB 2.0 FS Device 12 Mbps
– On-chip USB Transceiver
– Provides 1 interrupt source with 4 interrupt events
– Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
– Auto suspend function when no bus signaling for 3 ms
– Provides 8 programmable endpoints
– Includes 512 Bytes internal SRAM as USB buffer
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NuMicro NUC230/240 Datasheet
– Provides remote wake-up capability
ADC
– 12-bit SAR ADC with 1 MSPS(chip working at 5V)
– Up to 8-ch single-end input or 4-ch differential input
– Single scan/single cycle scan/continuous scan
– Each channel with individual result register
– Scan on enabled channels
– Threshold voltage detection
– Conversion started by software programming, external input or PWM Center-aligned trigger
– Supports PDMA mode
Analog Comparator
– Up to two analog comparators
– External input or internal Band-gap voltage selectable at negative node
– Interrupt when compare result change
– Supports Power-down wake-up
EBI (External bus interface)
– Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
– Supports 8-/16-bit data width
– Supports byte write in 16-bit data width mode
96-bit unique ID (UID)
128-bit unique customer ID(UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 105℃
Packages:
– All Green package (RoHS)
– LQFP 100-pin / 64-pin / 48-pin
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3
ABBREVIATIONS
Acronym
Description
ACMP
ADC
AES
APB
AHB
BOD
CAN
DAP
DES
EBI
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
IAP
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~24 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital Input/Output
Serial Peripheral Interface
SDIO
SPI
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SPS
Samples per Second
TDES
TMR
Triple Data Encryption Standard
Timer Controller
UART
UCID
USB
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
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4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro NUC230/240xxxAE Selection Guide
4.1.1 NuMicro NUC230 Automotive Line Selection Guide
Connectivity
NUC230LC2AE 32
NUC230LD2AE 64
8
8
4
4
8
8
8
8
8
8
8
35
35
35
49
49
49
83
4
4
4
4
4
4
4
5
5
5
5
5
5
6
1
1
1
2
2
2
4
2
2
2
2
2
2
2
-
-
-
-
-
-
-
3
3
3
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
2
2
2
2
2
2
3
1
1
1
2
2
2
2
4
4
4
6
6
6
8
7
7
7
7
7
7
8
v
v
v
v
v
v
v
-
-
v
v
v
v
v
v
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP100
NUC230LE3AE 128 16 Config.
-
NUC230SC2AE 32
NUC230SD2AE 64
8
8
4
4
v
v
v
v
NUC230SE3AE 128 16 Config.
NUC230VE3AE 128 16 Config.
4.1.2 NuMicro NUC240 Connectivity Line Selection Guide
Connectivity
NUC240LC2AE 32
NUC240LD2AE 64
8
8
4
4
8
8
8
8
8
8
8
31
31
31
45
45
45
79
4
4
4
4
4
4
4
4
4
4
5
5
5
6
1
1
1
2
2
2
4
2
2
2
2
2
2
2
1
1
1
1
1
1
1
2
2
2
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
2
2
2
2
4
4
4
4
4
4
8
7
7
7
7
7
7
8
v
v
v
v
v
v
v
-
-
v
v
v
v
v
v
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP100
NUC240LE3AE 128 16 Config.
-
NUC240SC2AE 32
NUC240SD2AE 64
8
8
4
4
v
v
v
v
NUC240SE3AE 128 16 Config.
NUC240VE3AE 128 16 Config.
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NuMicro NUC230/240 Datasheet
NUC 2 X 0 - X X X X X
ARM-Based
32-bit Microcontroller
Temperature
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
CPU core
1/2: Cortex-M0
5/7: ARM7
9: ARM9
Reserve
RAM Size
2: 8 KB
3: 16 KB
Function
3: Automotive Line
4: Connectivity Line
APROM Size
C: 32 KB
D: 64 KB
E: 128 KB
Package Type
L: LQFP 48
S: LQFP 64
V: LQFP 100
Figure 4-1 NuMicro NUC230/240 Series Selection Code
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4.2 Pin Configuration
4.2.1 NuMicro NUC230 Pin Diagram
4.2.1.1 NuMicro NUC230VxxAE LQFP 100 pin
SC1_RST/AD8/ADC5/PA.5
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM1/SPI1_SS1
PB.10/TM2/SPI0_SS1
PB.11/TM3/PWM4
UART4_TXD/SC1_CLK/AD7/ADC6/PA.6
UART4_RXD/SC1_DAT/AD6/ADC7/SPI2_SS1/PA.7
VREF
PE.5/TM1_EXT/PWM5/TM1
PE.6
AVDD
SPI2_SS0/PD.0
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PC.4/SPI0_MISO1
SPI2_CLK/PD.1
SPI2_MISO0/PD.2
SPI2_MOSI0/PD.3
SPI2_MISO1/PD.4
SPI2_MOSI1/PD.5
SC1_CD/AD5/ACMP0_N/PC.7
SC0_CD/AD4/ACMP0_P/PC.6
AD3/ACMP1_N/PC.15
AD2/ACMP1_P/PC.14
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
PC.5/SPI0_MOSI1
PD.15/UART2_TXD/CAN1_TXD
PD.14/UART2_RXD/CAN1_RXD
PD.7/CAN0_TXD
NUC230VxxAE
LQFP 100-pin
PD.6/CAN0_RXD
PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL
PB.1/UART0_TXD
XT1_IN/PF.1
nRESET
PB.0/UART0_RXD
PE.7
VSS
VDD
PE.8
PS2_DAT/PF.2
PE.9
PS2_CLK/PF.3
PE.10
PVSS
PE.11
CLKO/TM0/STADC/PB.8
PE.12
Figure 4-2 NuMicro NUC230VxxAE LQFP 100-pin Diagram
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4.2.1.2 NuMicro NUC230SxxAE LQFP 64 pin
AD8/ADC5/PA.5
AD7/ADC6/PA.6
VREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
PB.11/TM3/PWM4
AVDD
PE.5/TM1_EXT/PWM5/TM1
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PD.15/UART2_TXD/CAN1_TXD
PD.14/UART2_RXD/CAN1_RXD
PD.7/CAN0_TXD
AD5/ACMP0_N/PC.7
SC0_CD/AD4/ACMP0_P/PC.6
AD3/ACMP1_N/PC.15
AD2/ACMP1_P/PC.14
AD6/TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC230SxxAE
LQFP 64-pin
nRESET
PD.6/CAN0_RXD
VSS
PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL
PB.1/UART0_TXD
VDD
PVSS
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 4-3 NuMicro NUC230SxxAE LQFP 64-pin Diagram
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4.2.1.3 NuMicro NUC230LxxAE LQFP 48 pin
ADC5/PA.5
ADC6/PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PD.15/UART2_TXD/CAN1_TXD
PD.14/UART2_RXD/CAN1_RXD
PD.7/CAN0_TXD
VREF
AVDD
ACMP0_N/PC.7
SC0_CD/ACMP0_P/PC.6
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC230LxxAE
LQFP 48-pin
PD.6/CAN0_RXD
PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3
PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2
PB.1/UART0_TXD
nRESET
PVSS
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 4-4 NuMicro NUC230LxxAE LQFP 48-pin Diagram
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4.2.2 NuMicro NUC240 Pin Diagram
4.2.2.1 NuMicro NUC240VxxAE LQFP 100 pin
SC1_RST/AD8/ADC5/PA.5
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM1/SPI1_SS1
PB.10/TM2/SPI0_SS1
PB.11/TM3/PWM4
UART4_TXD/SC1_CLK/AD7/ADC6/PA.6
UART4_RXD/SC1_DAT/AD6/ADC7/SPI2_SS1/PA.7
VREF
PE.5/TM1_EXT/PWM5/TM1
PE.6
AVDD
SPI2_SS0/PD.0
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PC.4/SPI0_MISO1
SPI2_CLK/PD.1
SPI2_MISO0/PD.2
SPI2_MOSI0/PD.3
SPI2_MISO1/PD.4
SPI2_MOSI1/PD.5
SC1_CD/AD5/ACMP0_N/PC.7
SC0_CD/AD4/ACMP0_P/PC.6
AD3/ACMP1_N/PC.15
AD2/ACMP1_P/PC.14
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
PC.5/SPI0_MOSI1
PD.15/UART2_TXD/CAN1_TXD
PD.14/UART2_RXD/CAN1_RXD
PD.7/CAN0_TXD
NUC240VxxAE
LQFP 100-pin
PD.6/CAN0_RXD
PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL
PB.1/UART0_TXD
XT1_IN/PF.1
nRESET
PB.0/UART0_RXD
VSS
USB_D+
VDD
USB_D-
PS2_DAT/PF.2
USB_VDD33_CAP
PS2_CLK/PF.3
USB_VBUS
PVSS
PE.7
CLKO/TM0/STADC/PB.8
PE.8
Figure 4-5 NuMicro NUC240VxxAE LQFP 100-pin Diagram
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4.2.2.2 NuMicro NUC240SxxAE LQFP 64 pin
AD8/ADC5/PA.5
AD7/ADC6/PA.6
VREF
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PD.15/UART2_TXD/CAN1_TXD
PD.14/UART2_RXD/CAN1_RXD
PD.7/CAN0_TXD
AVDD
AD5/ACMP0_N/PC.7
SC0_CD/AD4/ACMP0_P/PC.6
AD3/ACMP1_N/PC.15
AD2/ACMP1_P/PC.14
AD6/TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC240SxxAE
LQFP 64-pin
PD.6/CAN0_RXD
PB.3/UART0_nCTS/TM3_EXT/SC2_CD/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/ACMP0_O/TM2/nWRL
PB.1/UART0_TXD
nRESET
PB.0/UART0_RXD
VSS
USB_D+
VDD
USB_D-
PVSS
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
USB_VBUS
Figure 4-6 NuMicro NUC240SxxAE LQFP 64-pin Diagram
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4.2.2.3 NuMicro NUC240LxxAE LQFP 48 pin
ADC5/PA.5
ADC6/PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPI0_SS0/I2S_LRCLK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PD.7/CAN0_TXD
VREF
AVDD
ACMP0_N/PC.7
SC0_CD/ACMP0_P/PC.6
TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC240LxxAE
LQFP 48-pin
PD.6/CAN0_RXD
PB.1/UART0_TXD
PB.0/UART0_RXD
USB_D+
nRESET
USB_D-
PVSS
USB_VDD33_CAP
USB_VBUS
CLKO/TM0/STADC/PB.8
Figure 4-7 NuMicro NUC240LxxAE LQFP 48-pin Diagram
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4.3 Pin Description
4.3.1 NuMicro NUC230 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin 64-pin 48-pin
1
2
3
PE.15
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O EBI Address/Data bus bit0
PE.14
PE.13
PB.14
1
AD0
4
INT0
I
External interrupt0 input pin.
SPI3_SS1
PB.13
I/O 2nd SPI3 slave select pin.
I/O General purpose digital I/O pin.
I/O EBI Address/Data bus bit1
5
2
AD1
ACMP1_O
VBAT
O
P
O
I
Comparator1 output pin.
6
7
8
3
4
5
1
2
3
Power supply by batteries for RTC.
X32_OUT
X32_IN
PA.11
External 32.768 kHz (low speed) crystal output pin.
External 32.768 kHz (low speed) crystal input pin.
I/O General purpose digital I/O pin.
I/O I2C1 clock pin.
4
I2C1_SCL
CAN1_RXD
nRD
9
6
7
I
Data receiver input pin for CAN1.
EBI read enable output pin
O
PA.10
I/O General purpose digital I/O pin.
I/O I2C1 data input/output pin.
5
I2C1_SDA
CAN1_TXD
nWR
10
O
O
Data transmitter output pin for CAN1.
EBI write enable output pin
PA.9
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
11
12
13
8
9
6
7
I2C0_SCL
PA.8
I/O General purpose digital I/O pin.
I/O I2C0 data input/output pin.
I/O General purpose digital I/O pin.
I/O 1st SPI3 slave select pin.
I/O General purpose digital I/O pin.
I/O SPI3 serial clock pin.
I2C0_SDA
PD.8
SPI3_SS0
PD.9
14
15
SPI3_CLK
PD.10
I/O General purpose digital I/O pin.
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Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
SPI3_MISO0
PD.11
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
16
17
18
SPI3_MOSI0
PD.12
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
SPI3_MISO1
PD.13
I/O 2nd SPI3 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
SPI3_MOSI1
PB.4
I/O 2nd SPI3 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
19
20
10
11
8
9
UART1_RXD
PB.5
I
Data receiver input pin for UART1.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART1.
I/O General purpose digital I/O pin.
UART1_TXD
PB.6
O
21
22
12
13
ALE
O
O
EBI address latch enable output pin
UART1_nRTS
PB.7
Request to Send output pin for UART1.
I/O General purpose digital I/O pin.
nCS
O
I
EBI chip select enable output pin
Clear to Send input pin for UART1.
LDO output pin.
UART1_nCTS
LDO_CAP
23
24
14
15
16
10
11
12
P
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
P
P
25
26
27
28
29
30
31
VSS
Ground pin for digital circuit.
PE.12
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PE.11
PE.10
PE.9
PE.8
PE.7
PB.0
32
33
34
17
18
19
13
14
15
UART0_RXD
PB.1
I
Data receiver input pin for UART0.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART0.
I/O General purpose digital I/O pin.
Request to Send output pin for UART0.
UART0_TXD
PB.2
O
UART0_nRTS
O
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NuMicro NUC230/240 Datasheet
Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
TM2_EXT
ACMP0_O
nWRL
I
Timer2 external capture input pin.
Comparator0 output pin.
O
O
EBI low byte write enable output pin
PB.3
I/O General purpose digital I/O pin.
UART0_nCTS
TM3_EXT
SC2_CD
nWRH
I
I
Clear to Send input pin for UART0.
Timer3 external capture input pin.
SmartCard2 card detect pin.
16
35
20
I
O
EBI high byte write enable output pin
PD.6
I/O General purpose digital I/O pin.
Data receiver input pin for CAN0.
I/O General purpose digital I/O pin.
Data transmitter output pin for CAN0.
I/O General purpose digital I/O pin.
36
37
21
22
17
18
CAN0_RXD
PD.7
I
CAN0_TXD
O
PD.14
38
39
23
24
19
20
UART2_RXD
CAN1_RXD
I
I
Data receiver input pin for UART2.
Data receiver input pin for CAN1.
PD.15
I/O General purpose digital I/O pin.
UART2_TXD
CAN1_TXD
PC.5
O
O
Data transmitter output pin for UART2.
Data transmitter output pin for CAN1.
I/O General purpose digital I/O pin.
40
41
SPI0_MOSI1
PC.4
I/O 2nd SPI0 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
SPI0_MISO1
PC.3
I/O 2nd SPI0 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
42
43
25
26
21
22
SPI0_MOSI0
I2S_DO
PC.2
I/O 1st SPI0 MOSI (Master Out, Slave In) pin.
O
I2S data output.
I/O General purpose digital I/O pin.
SPI0_MISO0
I2S_DI
I/O 1st SPI0 MISO (Master In, Slave Out) pin.
I
I2S data input.
PC.1
I/O General purpose digital I/O pin.
I/O SPI0 serial clock pin.
44
45
27
28
23
24
SPI0_CLK
I2S_BCLK
PC.0
I/O I2S bit clock pin.
I/O General purpose digital I/O pin.
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Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
SPI0_SS0
I/O 1st SPI0 slave select pin.
I2S_LRCLK
PE.6
I/O I2S left right channel clock.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O PWM5 output/Capture input.
46
PE.5
PWM5
47
29
TM1_EXT
I
Timer1 external capture input pin.
Timer1 toggle output pin.
TM1
O
PB.11
I/O General purpose digital I/O pin.
I/O Timer3 event counter input / toggle output.
I/O PWM4 output/Capture input.
48
49
50
30
31
TM3
PWM4
PB.10
TM2
I/O General purpose digital I/O pin.
I/O Timer2 event counter input / toggle output.
I/O 2nd SPI0 slave select pin.
SPI0_SS1
PB.9
I/O General purpose digital I/O pin.
I/O Timer1 event counter input / toggle output.
I/O 2nd SPI1 slave select pin.
32
TM1
SPI1_SS1
PE.4
51
52
53
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PE.3
PE.2
PE.1
I/O General purpose digital I/O pin.
54
PWM7
I/O PWM7 output/Capture input.
PE.0
I/O General purpose digital I/O pin.
I/O PWM6 output/Capture input.
55
56
57
58
PWM6
PC.13
I/O General purpose digital I/O pin.
I/O 2nd SPI1 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI1 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI1 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI1 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
SPI1_MOSI1
PC.12
SPI1_MISO1
PC.11
33
SPI1_MOSI0
PC.10
59
60
34
35
SPI1_MISO0
PC.9
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NuMicro NUC230/240 Datasheet
Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
SPI1_CLK
I/O SPI1 serial clock pin.
PC.8
I/O General purpose digital I/O pin.
61
62
36
37
MCLK
O
EBI clock output
SPI1_SS0
PA.15
I/O 1st SPI1 slave select pin.
I/O General purpose digital I/O pin.
I/O PWM output/Capture input.
PWM3
25
26
I2S_MCLK
SC2_PWR
PA.14
O
O
I2S master clock output pin.
SmartCard2 power pin.
I/O General purpose digital I/O pin.
I/O PWM2 output/Capture input.
PWM2
63
38
SC2_RST
AD15
O
SmartCard2 reset pin.
I/O EBI Address/Data bus bit15
I/O General purpose digital I/O pin.
I/O PWM1 output/Capture input.
PA.13
PWM1
27
64
39
SC2_CLK
UART5_TXD
AD14
O
O
SmartCard2 clock pin.
Data transmitter output pin for UART5.
I/O EBI Address/Data bus bit14
I/O General purpose digital I/O pin.
I/O PWM0 output/Capture input.
PA.12
PWM0
28
65
40
SC2_DAT
UART5_RXD
AD13
O
I
SmartCard2 data pin.
Data receiver input pin for UART5.
I/O EBI Address/Data bus bit13
I/O Serial wire debugger data pin.
66
67
41
42
29
30
ICE_DAT
ICE_CLK
I
Serial wire debugger clock pin.
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
68
VDD
P
P
69
70
VSS
Ground pin for digital circuit.
43
44
31
32
AVSS
AP Ground pin for analog circuit.
I/O General purpose digital I/O pin.
AI ADC0 analog input.
PA.0
71
72
ADC0
SC0_PWR
PA.1
O
SmartCard0 power pin.
I/O General purpose digital I/O pin.
AI ADC1 analog input.
45
33
ADC1
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NuMicro NUC230/240 Datasheet
Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
SC0_RST
AD12
O
SmartCard0 reset pin.
I/O EBI Address/Data bus bit12
I/O General purpose digital I/O pin.
AI ADC2 analog input.
PA.2
ADC2
34
73
46
SC0_CLK
UART3_TXD
AD11
O
O
SmartCard0 clock pin.
Data transmitter output pin for UART3.
I/O EBI Address/Data bus bit11
I/O General purpose digital I/O pin.
AI ADC3 analog input.
PA.3
ADC3
35
36
37
38
74
47
48
49
50
SC0_DAT
UART3_RXD
AD10
O
I
SmartCard0 data pin.
Data receiver input pin for UART3.
I/O EBI Address/Data bus bit10
I/O General purpose digital I/O pin.
AI ADC4 analog input.
PA.4
ADC4
75
76
AD9
I/O EBI Address/Data bus bit9
SC1_PWR
PA.5
O
SmartCard1 power pin.
I/O General purpose digital I/O pin.
AI ADC5 analog input.
ADC5
AD8
I/O EBI Address/Data bus bit8
SC1_RST
PA.6
O
SmartCard1 reset pin.
I/O General purpose digital I/O pin.
AI ADC6 analog input.
ADC6
77
AD7
I/O EBI Address/Data bus bit7
I/O SmartCard1 clock pin.
SC1_CLK
UART4_TXD
PA.7
O
Data transmitter output pin for UART4.
I/O General purpose digital I/O pin.
AI ADC7 analog input.
ADC7
AD6
I/O EBI Address/Data bus bit6
78
SC1_DAT
UART4_RXD
SPI2_SS1
VREF
O
I
SmartCard1 data pin.
Data receiver input pin for UART4.
I/O 2nd SPI2 slave select pin.
79
80
51
52
39
40
AP Voltage reference input for ADC.
AP Power supply for internal analog circuit.
AVDD
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NuMicro NUC230/240 Datasheet
Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
PD.0
I/O General purpose digital I/O pin.
I/O 1st SPI2 slave select pin.
81
SPI2_SS0
PD.1
I/O General purpose digital I/O pin.
I/O SPI2 serial clock pin.
82
83
84
85
86
SPI2_CLK
PD.2
I/O General purpose digital I/O pin.
I/O 1st SPI2 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI2 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI2 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
AI Comparator0 negative input pin.
I/O EBI Address/Data bus bit5
SPI2_MISO0
PD.3
SPI2_MOSI0
PD.4
SPI2_MISO1
PD.5
SPI2_MOSI1
PC.7
41
53
CMP0_N
AD5
87
SC1_CD
PC.6
I
SmartCard1 card detect pin.
I/O General purpose digital I/O pin.
AI Comparator0 positive input pin.
42
ACMP0_P
SC0_CD
AD4
88
54
I
SmartCard0 card detect pin.
I/O EBI Address/Data bus bit4
I/O General purpose digital I/O pin.
I/O EBI Address/Data bus bit3
AI Comparator1 negative input pin.
I/O General purpose digital I/O pin.
I/O EBI Address/Data bus bit2
AI Comparator1 positive input pin.
I/O General purpose digital I/O pin.
PC.15
89
90
55
56
AD3
ACMP1_N
PC.14
AD2
ACMP1_P
PB.15
INT1
I
I
External interrupt1 input pin.
43
44
91
57
58
TM0_EXT
Timer0 external capture input pin.
TM0
AD6
O
Timer0 toggle output pin.
I/O EBI Address/Data bus bit6
PF.0
I/O General purpose digital I/O pin.
92
XT1_OUT
O
External 4~24 MHz (high speed) crystal output pin.
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
LQFP
Pin
Type
Pin Name
Description
LQFP
LQFP
100-pin 64-pin 48-pin
PF.1
I/O General purpose digital I/O pin.
93
59
45
46
XT1_IN
I
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up. Set this
pin low reset chip to initial state.
94
95
96
60
61
62
nRESET
VSS
I
P
P
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
PF.2
I/O General purpose digital I/O pin.
I/O PS2 data pin.
97
PS2_DAT
PF.3
I/O General purpose digital I/O pin.
I/O PS2 clock pin.
98
99
PS2_CLK
PVSS
63
64
47
48
P
PLL ground.
I/O General purpose digital I/O pin.
ADC external trigger input.
I/O Timer0 event counter input / toggle output.
Frequency divider clock output pin.
PB.8
STADC
TM0
I
100
CLKO
O
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
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Page 34 of 97
Revision 1.01
NuMicro NUC230/240 Datasheet
4.3.2 NuMicro NUC240 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
1
2
3
PE.15
PE.14
PE.13
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PB.14
AD0
EBI Address/Data bus bit0
1
2
I/O
I
4
5
INT0
External interrupt0 input pin.
SPI3_SS1
I/O 2nd SPI3 slave select pin.
PB.13
AD1
I/O General purpose digital I/O pin.
I/O EBI Address/Data bus bit1
ACMP1_O
VBAT
O
P
O
I
Comparator1 output pin.
6
7
8
3
4
5
1
2
3
Power supply by batteries for RTC.
X32_OUT
X32_IN
PA.11
External 32.768 kHz (low speed) crystal output pin.
External 32.768 kHz (low speed) crystal input pin.
I/O General purpose digital I/O pin.
I/O I2C1 clock pin.
4
I2C1_SCL
9
6
7
CAN1_RXD
nRD
I
Data receiver input pin for CAN1.
EBI read enable output pin
O
PA.10
I/O General purpose digital I/O pin.
I/O I2C1 data input/output pin.
5
I2C1_SDA
10
CAN1_TXD
nWR
O
O
Data transmitter output pin for CAN1.
EBI write enable output pin
PA.9
I/O General purpose digital I/O pin.
I/O I2C0 clock pin.
11
12
13
14
15
8
9
6
7
I2C0_SCL
PA.8
I/O General purpose digital I/O pin.
I/O I2C0 data input/output pin.
I/O General purpose digital I/O pin.
I/O 1st SPI3 slave select pin.
I2C0_SDA
PD.8
SPI3_SS0
PD.9
I/O General purpose digital I/O pin.
I/O SPI3 serial clock pin.
SPI3_CLK
PD.10
I/O General purpose digital I/O pin.
I/O 1st SPI3 MISO (Master In, Slave Out) pin.
SPI3_MISO0
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PD.11
I/O General purpose digital I/O pin.
16
17
18
19
20
SPI3_MOSI0
PD.12
I/O 1st SPI3 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
SPI3_MISO1
PD.13
I/O 2nd SPI3 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
SPI3_MOSI1
PB.4
I/O 2nd SPI3 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
10
11
8
9
UART1_RXD
PB.5
I
Data receiver input pin for UART1.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART1.
I/O General purpose digital I/O pin.
UART1_TXD
O
PB.6
ALE
O
O
EBI address latch enable output pin
21
22
12
13
UART1_nRTS
Request to Send output pin for UART1.
PB.7
nCS
I/O General purpose digital I/O pin.
O
EBI chip select enable output pin
UART1_nCTS
LDO_CAP
I
Clear to Send input pin for UART1.
LDO output pin.
23
24
14
15
16
10
11
12
P
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
P
P
25
26
27
28
29
30
31
VSS
Ground pin for digital circuit.
PE.8
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
USB Power supply from USB host or HUB.
PE.7
17
18
19
20
13
14
15
16
USB_VBUS
USB_VDD33_CAP USB Internal power regulator output 3.3V decoupling pin.
USB_D-
USB_D+
PB.0
USB USB differential signal D-.
USB USB differential signal D+.
I/O General purpose digital I/O pin.
32
33
21
22
17
18
UART0_RXD
PB.1
I
Data receiver input pin for UART0.
I/O General purpose digital I/O pin.
Data transmitter output pin for UART0.
I/O General purpose digital I/O pin.
UART0_TXD
O
PB.2
nWRL
O
O
EBI low byte write enable output pin
Request to Send output pin for UART0.
34
23
UART0_nRTS
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
TM2_EXT
TM2
I
Timer2 external capture input pin.
Timer2 toggle output pin.
O
O
ACMP0_O
Comparator0 output pin.
PB.3
I/O General purpose digital I/O pin.
UART0_nCTS
I
O
I
Clear to Send input pin for UART0.
EBI high byte write enable output pin
nWRH
35
24
TM3_EXT
TM3
Timer3 external capture input pin.
Timer3 toggle output pin.
O
I
SC2_CD
PD.6
SmartCard2 card detect pin.
I/O General purpose digital I/O pin.
Data receiver input pin for CAN0.
I/O General purpose digital I/O pin.
Data transmitter output pin for CAN0.
I/O General purpose digital I/O pin.
36
37
25
26
19
20
CAN0_RXD
PD.7
I
CAN0_TXD
O
PD.14
38
39
27
28
UART2_RXD
CAN1_RXD
I
I
Data receiver input pin for UART2.
Data receiver input pin for CAN1.
PD.15
I/O General purpose digital I/O pin.
UART2_TXD
CAN1_TXD
PC.5
O
O
Data transmitter output pin for UART2.
Data transmitter output pin for CAN1.
I/O General purpose digital I/O pin.
40
41
SPI0_MOSI1
PC.4
I/O 2nd SPI0 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
SPI0_MISO1
PC.3
I/O 2nd SPI0 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
42
43
29
30
21
22
SPI0_MOSI0
I2S_DO
I/O 1st SPI0 MOSI (Master Out, Slave In) pin.
O
I2S data output.
PC.2
I/O General purpose digital I/O pin.
SPI0_MISO0
I/O 1st SPI0 MISO (Master In, Slave Out) pin.
I2S_DI
PC.1
I
I2S data input.
I/O General purpose digital I/O pin.
I/O SPI0 serial clock pin.
SPI0_CLK
44
31
23
I2S_BCLK
I/O I2S bit clock pin.
Dec. 30, 2014
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PC.0
I/O General purpose digital I/O pin.
I/O 1st SPI0 slave select pin.
45
46
32
24
SPI0_SS0
I2S_LRCLK
PE.6
I/O I2S left right channel clock.
I/O General purpose digital I/O pin.
PE.5
I/O General purpose digital I/O pin.
I/O PWM5 output/Capture input.
PWM5
TM1_EXT
TM1
47
48
I
Timer1 external capture input pin.
Timer1 toggle output pin.
O
PB.11
I/O General purpose digital I/O pin.
TM3
I/O Timer3 event counter input / toggle output.
PWM4
PB.10
TM2
I/O PWM4 output/Capture input.
I/O General purpose digital I/O pin.
I/O Timer2 event counter input / toggle output.
I/O 2nd SPI0 slave select pin.
49
50
SPI0_SS1
PB.9
I/O General purpose digital I/O pin.
I/O Timer1 event counter input / toggle output.
I/O 2nd SPI1 slave select pin.
TM1
SPI1_SS1
PE.4
51
52
53
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
I/O General purpose digital I/O pin.
PE.3
PE.2
PE.1
I/O General purpose digital I/O pin.
54
PWM7
I/O PWM7 output/Capture input.
PE.0
I/O General purpose digital I/O pin.
I/O PWM6 output/Capture input.
55
56
57
58
59
PWM6
PC.13
I/O General purpose digital I/O pin.
I/O 2nd SPI1MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI1 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI1 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI1 MISO (Master In, Slave Out) pin.
SPI1_MOSI1
PC.12
SPI1_MISO1
PC.11
33
34
SPI1_MOSI0
PC.10
SPI1_MISO0
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PC.9
I/O General purpose digital I/O pin.
I/O SPI1 serial clock pin.
60
61
35
36
SPI1_CLK
PC.8
I/O General purpose digital I/O pin.
MCLK
O
EBI clock output
SPI1_SS0
PA.15
I/O 1st SPI1 slave select pin.
I/O General purpose digital I/O pin.
I/O PWM3 output/Capture input.
25
26
PWM3
62
63
37
38
I2S_MCLK
SC2_PWR
PA.14
O
O
I2S master clock output pin.
SmartCard2 power pin.
I/O General purpose digital I/O pin.
PWM2
AD15
I/O PWM2 output/Capture input.
I/O EBI Address/Data bus bit15
SC2_RST
PA.13
O
SmartCard2 reset pin.
I/O General purpose digital I/O pin.
27
PWM1
AD14
I/O PWM1 output/Capture input.
I/O EBI Address/Data bus bit14
64
39
SC2_CLK
UART5_TXD
PA.12
O
O
SmartCard2 clock pin.
27
28
Data transmitter output pin for UART5.
I/O General purpose digital I/O pin.
PWM0
AD13
I/O PWM0 output/Capture input.
I/O EBI Address/Data bus bit13
65
40
SC2_DAT
UART5_RXD
ICE_DAT
O
I
SmartCard2 data pin.
28
29
30
Data receiver input pin for UART5.
66
67
41
42
I/O Serial wire debugger data pin.
ICE_CLK
I
Serial wire debugger clock pin.
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
68
VDD
P
P
69
70
VSS
Ground pin for digital circuit.
43
44
45
31
32
33
AVSS
AP Ground pin for analog circuit.
I/O General purpose digital I/O pin.
PA.0
71
72
ADC0
SC0_PWR
PA.1
AI
O
ADC0 analog input.
SmartCard0 power pin.
I/O General purpose digital I/O pin.
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Revision 1.01
NuMicro NUC230/240 Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
ADC1
AI
O
ADC1 analog input.
SC0_RST
AD12
SmartCard0 reset pin.
I/O EBI Address/Data bus bit12
PA.2
I/O General purpose digital I/O pin.
ADC2
AI
O
ADC2 analog input.
34
SC0_CLK
SmartCard0 clock pin.
73
46
UART3_TXD
AD11
O
Data transmitter output pin for UART3.
EBI Address/Data bus bit11
I/O
PA.3
I/O General purpose digital I/O pin.
ADC3
AI
O
ADC3 analog input.
35
36
37
38
SC0_DAT
UART3_RXD
AD10
SmartCard0 data pin.
74
47
48
49
50
I
Data receiver input pin for UART3.
EBI Address/Data bus bit10
I/O
PA.4
I/O General purpose digital I/O pin.
ADC4
AI
ADC4 analog input.
75
76
I/O
AD9
EBI Address/Data bus bit9
SmartCard1 power pin.
SC1_PWR
PA.5
O
I/O General purpose digital I/O pin.
ADC5
AI
ADC5 analog input.
I/O
AD8
EBI Address/Data bus bit8
SmartCard1 reset pin.
SC1_RST
PA.6
O
I/O General purpose digital I/O pin.
ADC6
AI
ADC6 analog input.
I/O
77
AD7
EBI Address/Data bus bit7
SC1_CLK
UART4_TXD
PA.7
I/O SmartCard1 clock pin.
Data transmitter output pin for UART4.
I/O General purpose digital I/O pin.
O
ADC7
AD6
AI
ADC7 analog input.
I/O
EBI Address/Data bus bit6
SmartCard1 data pin.
78
SC1_DAT
O
I
UART4_RXD
SPI2_SS1
Data receiver input pin for UART4.
I/O 2nd SPI2 slave select pin.
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Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
79
80
51
52
39
40
VREF
AP Voltage reference input for ADC.
AP Power supply for internal analog circuit.
I/O General purpose digital I/O pin.
I/O 1st SPI2 slave select pin.
AVDD
PD.0
81
82
83
84
85
86
SPI2_SS0
PD.1
I/O General purpose digital I/O pin.
I/O SPI2 serial clock pin.
SPI2_CLK
PD.2
I/O General purpose digital I/O pin.
I/O 1st SPI2 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 1st SPI2 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI2 MISO (Master In, Slave Out) pin.
I/O General purpose digital I/O pin.
I/O 2nd SPI2 MOSI (Master Out, Slave In) pin.
I/O General purpose digital I/O pin.
SPI2_MISO0
PD.3
SPI2_MOSI0
PD.4
SPI2_MISO1
PD.5
SPI2_MOSI1
PC.7
41
ACMP0_N
AD5
AI
Comparator0 negative input pin.
EBI Address/Data bus bit5
SmartCard1 card detect pin.
53
87
88
I/O
SC1_CD
PC.6
I
I/O General purpose digital I/O pin.
42
ACMP0_P
AI
Comparator0 positive input pin.
SmartCard0 card detect pin.
EBI Address/Data bus bit4
54
SC0_CD
AD4
I
I/O
PC.15
AD3
I/O General purpose digital I/O pin.
I/O
AI
89
90
55
56
EBI Address/Data bus bit3
ACMP1_N
Comparator1 negative input pin.
PC.14
AD2
I/O General purpose digital I/O pin.
I/O
AI
EBI Address/Data bus bit2
ACMP1_P
PB.15
Comparator1 positive input pin.
I/O General purpose digital I/O pin.
INT1
I
I
External interrupt1 input pin.
Timer 0 external capture input pin.
Timer0 toggle output pin.
43
TM0_EXT
91
57
TM0
AD6
O
I/O EBI Address/Data bus bit6
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Pin No.
Pin
Type
Pin Name
Description
LQFP
LQFP
LQFP
100-pin
64-pin
48-pin
PF.0
I/O General purpose digital I/O pin.
External 4~24 MHz (high speed) crystal output pin.
I/O General purpose digital I/O pin.
92
93
58
59
44
XT1_OUT
PF.1
O
45
46
XT1_IN
I
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up. Set this
pin low reset chip to initial state.
94
95
96
60
61
62
nRESET
VSS
I
P
P
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal PLL and
digital circuit.
VDD
PF.2
I/O General purpose digital I/O pin.
I/O PS/2 data pin.
97
PS2_DAT
PF.3
I/O General purpose digital I/O pin.
I/O PS/2 clock pin.
98
99
PS2_CLK
PVSS
63
64
47
48
P
PLL ground.
I/O General purpose digital I/O pin.
ADC external trigger input.
I/O Timer0 event counter input / toggle output.
Frequency divider clock output pin.
PB.8
STADC
TM0
I
100
CLKO
O
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power
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5
BLOCK DIAGRAM
5.1 NuMicro NUC230 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
LDROM
8 KB
APROM
RTC
128/64/32 KB
ARM
Cortex-M0
72MHz
PDMA
Analog
Comparator x2
Watchdog Timer
DataFlash
Configurable/
4 KB
SRAM
16/8 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
I/O Ports
General Purpose
I/O
LDO
SPI x 4
I2C x 2
External
Interrupt
Power On Reset
LVR
High Speed
High Speed
Oscillator
22.1184 MHz
Crystal Osc.
4 ~ 24 MHz
I2S x 1
Reset Pin
PS/2 x 1
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
SC (UART) x 3
CAN x 2
Brownout
Detection
Figure 5-1 NuMicro NUC230 Block Diagram
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5.2 NuMicro NUC240 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
APROM
128/64/32 KB
LDROM
8 KB
RTC
ARM
Cortex-M0
72MHz
USB PHY
PDMA
Watchdog Timer
Analog
Comparator x2
DataFlash
Configurable/
4 KB
SRAM
16/8 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
SPI x 4
I/O Ports
General Purpose
I/O
LDO
Power On Reset
LVR
I2C x 2
External
Interrupt
I2S x 1
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
22.1184 MHz
PS/2 x 1
SC (UART) x 3
USB
Reset Pin
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
Brownout
Detection
CAN x 2
Figure 5-2 NuMicro NUC240 Block Diagram
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6
FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex™-M0 Core
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 6-1 shows the functional controller of processor.
CortexTM-M0 Components
CortexTM-M0 processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
CortexTM-M0
Processor
Core
Debug
Access
Port
Wakeup
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 6-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
-
-
-
-
-
-
-
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
-
-
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
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NVIC:
-
-
-
-
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support
-
-
-
-
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
-
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
-
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2 System Manager
6.2.1 Overview
System management includes the following sections:
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset
Low Voltage Reset
Brown-out Detector Reset
CPU Reset
System Reset
System Reset and Power-on Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-on Reset is external crystal circuit and
BS(ISPCON[1]) bit. System Reset does not reset external crystal circuit and BS(ISPCON[1]) bit,
but Power-on Reset does.
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6.2.3 System Power Distribution
In this chip, the power distribution is divided into three segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VBUS offers the power for operating the USB transceiver.
Battery power from VBAT supplies the RTC and external 32.768 kHz crystal.
The outputs of internal voltage regulators, LDO and VDD33, require an external capacitor which
should be located close to the corresponding pin. Analog power (AVDD) should be the same
voltage level with the digital power (VDD). 錯誤! 找不到參照來源。Figure 6-2 shows the NuMicro
NUC230 power distribution, and Figure 6-3 shows the NuMicro NUC240 power distribution.
NUC230 Power Distribution
Brown-
out
Detector
Low
Voltage
Reset
AVDD
AVSS
12-bit
SAR-ADC
Analog
Comparator
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
External
32.768 kHz
Crystal
ULDO
RTC
PLL
LDO
IO cell
GPIO
Figure 6-2 NuMicro NUC230 Power Distribution Diagram
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AVDD
AVSS
USB_D+
USB 1.1
12-bit
SAR-ADC
Tranceiver
USB_D-
NUC240
Power
Distribution
USB_VDD33_CAP
1uF
Analog Comparator
3.3V
Low
Voltage
Reset
Brown-
out
Detector
5V to 3.3V LDO
USB_VBUS
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
External
32.768 kHz
Crystal
ULDO
RTC
PLL
LDO
IO cell
GPIO
Figure 6-3 NuMicro NUC240 Power Distribution Diagram
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6.2.4 System Memory Map
The NuMicro NUC230/240 series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register definition,
memory space, and programming detailed will be described in the following sections for each on-chip
peripheral. The NuMicro NUC230/240 series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x2000_0000 – 0x2000_3FFF
FLASH_BA
SRAM_BA
FLASH Memory Space (128 KB)
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
0x5000_0200 – 0x5000_02FF
0x5000_0300 – 0x5000_03FF
0x5000_4000 – 0x5000_7FFF
0x5000_8000 – 0x5000_BFFF
GCR_BA
CLK_BA
INT_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
GPIO_BA
PDMA_BA
Peripheral DMA Control Registers
0x5000_C000 – 0x5000_FFFF
0x5001_0000 – 0x5001_03FF
FMC_BA
EBI_BA
Flash Memory Control Registers
External Bus Interface Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4000_4000 – 0x4000_7FFF
0x4000_8000 – 0x4000_BFFF
0x4001_0000 – 0x4001_3FFF
0x4002_0000 – 0x4002_3FFF
0x4003_0000 – 0x4003_3FFF
0x4003_4000 – 0x4003_7FFF
0x4004_0000 – 0x4004_3FFF
0x4005_0000 – 0x4005_3FFF
0x4006_0000 – 0x4006_3FFF
0x400D_0000 – 0x400D_3FFF
0x400E_0000 – 0x400E_FFFF
WDT_BA
RTC_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
TMR01_BA
I2C0_BA
I2C0 Interface Control Registers
SPI0_BA
SPI1_BA
PWMA_BA
UART0_BA
USBD_BA
ACMP_BA
ADC_BA
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
UART0 Control Registers
USB 2.0 FS device Controller Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4010_0000 – 0x4010_3FFF
0x4011_0000 – 0x4011_3FFF
0x4012_0000 – 0x4012_3FFF
0x4013_0000 – 0x4013_3FFF
0x4013_4000 – 0x4013_7FFF
PS2_BA
PS/2 Interface Control Registers
TMR23_BA
I2C1_BA
SPI2_BA
SPI3_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
SPI2 with master/slave function Control Registers
SPI3 with master/slave function Control Registers
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0x4014_0000 – 0x4014_3FFF
0x4015_0000 – 0x4015_3FFF
0x4015_4000 – 0x4015_7FFF
0x4018_0000 – 0x4018_3FFF
0x4018_4000 – 0x4018_7FFF
0x4019_0000 – 0x4019_3FFF
0x4019_4000 – 0x4019_7FFF
0x4019_8000 – 0x4019_BFFF
0x401A_0000 – 0x401A_3FFF
PWMB_BA
UART1_BA
UART2_BA
CAN0_BA
CAN1_BA
SC0_BA
PWM4/5/6/7 Control Registers
UART1 Control Registers
UART2 Control Registers
CAN0 Bus Control Registers
CAN1 Bus Control Registers
SC0 Control Registers
SC1_BA
SC1 Control Registers
SC2_BA
SC2 Control Registers
I2S_BA
I2S Interface Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6-1 Address Space Assignments for On-Chip Controllers
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6.2.5 System Timer (SysTick)
The Cortex™-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.6 Nested Vectored Interrupt Controller (NVIC)
The Cortex™-M0 provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor kernel and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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6.2.6.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro NUC230/240 series.
Software can set four levels of priority on some of these exceptions as well as on all interrupts.
The highest user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”.
The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as
the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
NMI
2
-2
Hard Fault
Reserved
3
-1
4 ~ 10
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
11
Reserved
12 ~ 13
PendSV
14
SysTick
15
16 ~ 47
Interrupt (IRQ0 ~ IRQ31)
Table 6-2 Exception Model
Interrupt Number
Vector
Number
Source
Module
Interrupt Name
Interrupt Description
(Bit In Interrupt
Registers)
1 ~ 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
-
0
-
-
System exceptions
BOD_INT
WDT_INT
EINT0
Brown-out Brown-out low voltage detected interrupt
1
WDT
GPIO
Watchdog Timer interrupt
2
External signal interrupt from PB.14 pin
External signal interrupt from PB.15 pin
External signal interrupt from PA[15:0]/PB[13:0]
External interrupt from PC[15:0]/PD[15:0]/PE[15:0]/PF[3:0]
PWM0, PWM1, PWM2 and PWM3 interrupt
PWM4, PWM5, PWM6 and PWM7 interrupt
Timer 0 interrupt
3
EINT1
GPIO
4
GPAB_INT
GPCDEF_INT
PWMA_INT
PWMB_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
UART02_INT
UART1_INT
SPI0_INT
GPIO
5
GPIO
6
PWM0~3
PWM4~7
TMR0
7
8
9
TMR1
Timer 1 interrupt
10
11
12
13
14
TMR2
Timer 2 interrupt
TMR3
Timer 3 interrupt
UART0/2
UART1
SPI0
UART0 and UART2 interrupt
UART1 interrupt
SPI0 interrupt
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31
32
33
34
35
36
37
38
39
40
41
42
43
15
16
17
18
19
20
21
22
23
24
25
26
27
SPI1_INT
SPI2_INT
SPI3_INT
I2C0_INT
I2C1_INT
-
SPI1
SPI2
SPI3
I2C0
I2C1
-
SPI1 interrupt
SPI2 interrupt
SPI3 interrupt
I2C0 interrupt
I2C1 interrupt
Reserved
-
-
Reserved
SC012_INT
USB_INT
PS2_INT
ACMP_INT
PDMA_INT
I2S_INT
SC0/1/2
USBD
PS/2
SC0, SC1 and SC2 interrupt
USB 2.0 FS Device interrupt
PS/2 interrupt
ACMP
PDMA
I2S
Analog Comparator interrupt
PDMA interrupt
I2S interrupt
Clock controller interrupt for chip wake-up from Power-
down state
44
28
PWRWU_INT
CLKC
45
46
47
29
30
31
ADC_INT
IRC_INT
RTC_INT
ADC
IRC
ADC interrupt
IRC TRIM interrupt
Real Time Clock interrupt
RTC
Table 6-3 System Interrupt Map
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6.2.6.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
Description
0
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 6-4 Vector Table Format
Vector Number
6.2.6.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
6.2.7 System Control
The Cortex™-M0 status and operating mode control are managed by System Control Registers.
Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be
controlled through these system control registers.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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NuMicro NUC230/240 Datasheet
6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex™-M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave
Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external
high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the
overall system power consumption. The following figures show the clock generator and the
overview of the clock source control.
The clock generator consists of 5 clock sources as listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~24 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLL source can be selected from external
4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high
speed RC oscillator (HIRC)) (PLL FOUT)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
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XTL32K_EN (PWRCON[1])
X32_OUT
X32_IN
LXT
32.768 kHz
LXT
XTL12M_EN (PWRCON[0])
HXT
XT1_OUT
XT1_IN
4~24 MHz
HXT
PLL_SRC (PLLCON[19])
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
22.1184 MHz
HIRC
HIRC
LIRC
OSC10K_EN(PWRCON[3])
10 kHz
LIRC
Legend:
LXT = 32.768 kHz external low speed crystal oscillator
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Figure 6-4 Clock Generator Block Diagram
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22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
4~24
MHz
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PDMA
32.768
kHz
ACMP
I2C 0~1
CAN 0~1
PCLK
22.1184 MHz
10 kHz
111
101
011
010
001
000
10 kHz
CLKSEL0[2:0]
TMR 3
TMR 2
TMR 1
TMR 0
External trigger
HCLK
22.1184 MHz
4~24 MHz
1
PLLFOUT
32.768 kHz
4~24 MHz
0
PLLCON[19]
22.1184 MHz
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
FMC
CPUCLK
22.1184 MHz
HCLK
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
SYST_CSR[2]
4~24 MHz
32.768 kHz
4~24 MHz
10 kHz
111
22.1184 MHz
011
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
HCLK
010
32.768 kHz
001
CLKSEL0[5:3]
4~24 MHz
000
CLKSEL2[17:16]
10 kHz
22.1184 MHz
11
10
01
00
11
10
HCLK
WWDT
CLKSEL2[11:4]
CLKSEL1[31:28]
PLLFOUT
4~24 MHz
10 kHz
11
10
01
HCLK
1/2048
WDT
PS2
I2S
32.768 kHz
CLKSEL2[1:0]
22.1184 MHz
CLKSEL1[1:0]
22.1184 MHz
PLLFOUT
11
01
00
HCLK
1
0
4~24 MHz
SPI0-3
PLLFOUT
CLKSEL1[25:24]
CLK_SEL1[7:4]
1/(UART_N+1)
1/(ADC_N+1)
UART 0-2
22.1184 MHz
HCLK
11
10
01
00
ADC
BOD
PLLFOUT
4~24 MHz
22.1184 MHz
HCLK
10 kHz
11
10
01
00
FDIV
RTC
32.768 kHz
4~24 MHz
CLKSEL1[3:2]
10 kHz
1
0
32.768 kHz
22.1184 MHz
HCLK
11
10
01
00
CLKSEL2[3:2]
CLKSEL2[18]
1/(SC2_N+1)
SC 2
SC 1
SC 0
PLLFOUT
4~24 MHz
1/(SC1_N+1)
1/(SC0_N+1)
CLKSEL3[5:4]
CLKSEL3[3:2]
CLKSEL3[1:0]
PLLFOUT
1/(USB_N+1)
USB
Figure 6-5 Clock Generator Global View Diagram
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6.3.2 System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 6-6.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011
010
001
000
CPUCLK
HCLK
CPU
AHB
APB
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PCLK
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
Figure 6-6 System Clock Block Diagram
The clock source of SysTick in Cortex™-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 6-7.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Figure 6-7 SysTick Clock Control Block Diagram
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6.3.3 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
-
-
10 kHz internal low speed RC oscillator clock
32.768 kHz external low speed crystal oscillator clock
RTC/WDT/Timer/PWM Peripherals Clock (when 32.768 kHz external low speed
crystal oscillator or 10 kHz intertnal low speed RC oscillator is adopted as clock
source)
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6.3.4 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
22.1184 MHz
11
FRQDIV_CLK
HCLK
10
01
00
32.768 kHz
4~24 MHz
Figure 6-8 Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FSEL
(FRQDIV[3:0])
16 chained
divide-by-2 counter
FRQDIV_CLK
DIVIDER1
(FRQDIV[5])
1/2
1/22 1/23
…... 1/215 1/216
0000
0001
16 to 1
MUX
:
:
CLKO
0
1
1110
1111
Figure 6-9 Frequency Divider Block Diagram
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6.4 Flash Memory Controller (FMC)
6.4.1 Overview
The NuMicro NUC230/240 series has 128/64/32K bytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-System-
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex™-M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in CONFIG0. By the way, the NuMicro NUC230/240 series also provides
additional Data Flash for user to store some application dependent data. For 128K bytes APROM
device, the Data Flash is shared with original 128K program memory and its start address is
configurable in CONFIG1. For 64K/32K bytes APROM device, the Data Flash is fixed at 4KB.
6.4.2 Features
Runs up to 50 MHz with zero wait cycle for continuous address read access and runs
up to 72MHz with one wait cycle for continuous address read.
All embedded flash memory supports 512 bytes page erase
128/64/32 KB application program memory (APROM)
8KB In-System-Programming (ISP) loader program memory (LDROM)
4KB Data Flash for 64/32 KB APROM device
Configurable Data Flash size for 128KB APROM device
Configurable or fixed 4 KB Data Flash with 512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
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6.5 External Bus Interface (EBI)
6.5.1 Overview
The NuMicro NUC100 series LQFP-64 and LQFP-100 package equips an external bus interface
(EBI) for access external device.
To save the connections between external device and this chip, EBI supports address bus and
data bus multiplex mode. And, address latch enable (ALE) signal is used to differentiate the
address and data cycle.
6.5.2 Features
External Bus Interface has the following functions:
Supports external devices with max. 64 KB size (8-bit data width)/128 KB (16-bit data
width)
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width
Supports variable data access time (tACC), address latch enable time (tALE) and
address hold time (tAHD)
Supports address bus and data bus multiplex mode to save the address pins
Supports configurable idle cycle for different access condition: Write command finish
(W2X), Read-to-Read (R2R)
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6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NuMicro NUC230/240 series has up to 84 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 84 pins are arranged in 6 ports named
as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the
maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 84 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V.
6.6.2 Features
Four I/O modes:
-
-
-
-
Quasi-bidirectional
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
-
-
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
6.7 PDMA Controller (PDMA)
6.7.1 Overview
The NuMicro NUC230/240 series DMA contains nine-channel peripheral direct memory access
(PDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA
PDMACEN (PDMA_CSRx[0]). The CPU can recognize the completion of a PDMA operation by
software polling or when it receives an internal PDMA interrupt. The PDMA controller can
increase source or destination address or fixed them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and DMA transfer mode.
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6.7.2 Features
Supports nine PDMA channels and one CRC channel. Each PDMA channel can
support a unidirectional transfer
AMBA AHB master/slave interface compatible, for data transfer and register
read/write
Hardware round robin priority scheme. DMA channel 0 has the highest priority and
channel 8 has the lowest priority
PDMA operation
-
-
-
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
Supports word/half-word/byte transfer data width from/to peripheral
Supports address direction: increment, fixed.
Cyclic Redundancy Check (CRC)
-
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 +
X2 + X + 1
-
-
-
Supports programmable CRC seed value.
Supports programmable order reverse setting for input data and CRC checksum.
Supports programmable 1’s complement setting for input data and CRC
checksum.
-
-
Supports CPU PIO mode or DMA transfer mode.
Supports the follows write data length in CPU PIO mode
8-bit write mode (byte): 1-AHB clock cycle operation.
16-bit write mode (half-word): 2-AHB clock cycle operation.
32-bit write mode (word): 4-AHB clock cycle operation.
-
Supports byte alignment transfer data length and word alignment transfer source
address in CRC DMA mode.
6.8 Timer Controller (TIMER)
6.8.1 Overview
The timer controller includes four 32-bit timers, TIMER0 ~ TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
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6.8.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides four timer counting modes: one-shot, periodic, toggle and continuous
counting
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit
TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external counter pin
(TM0~TM3)
Supports external pin capture (TM0_EXT~TM3_EXT) for interval measurement
Supports external pin capture (TM0_EXT~TM3_EXT) for reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
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6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The NuMicro NUC230/240 series has 2 sets of PWM group supporting a total of 4 sets of PWM
generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6,
PWM7) with 4 programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When DZEN01 (PCR[4]) is set, PWM0 and PWM1 perform complementary PWM paired function;
the paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for the
architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-
shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CRL_IE0 (CCR0[1]) (Rising latch Interrupt enable) and CFL_IE0
(CCR0[2]) (Falling latch Interrupt enable) to decide the condition of interrupt occur. Capture
channel 1 has the same feature by setting CRL_IE1 (CCR0[17]) and CFL_IE1 (CCR0[18]). And
capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
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example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will be 1/900ns ≈ 1000 kHz
6.9.2 Features
6.9.2.1 PWM Function:
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4
complementary PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting one
8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator and two
PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode
Edge-aligned type or Center-aligned type option
PWM trigger ADC start-to-conversion
6.9.2.2 Capture Function:
Timing control logic shared with PWM Generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) WDT_CLK cycle and the time-out interval period
is 104 ms ~ 26.3168 s if WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports Watchdog Timer reset delay period
-
Selectable it includes (1026、130、18 or 3) * WDT_CLK reset delay period.
Supports to force Watchdog Timer enabled after chip powered on or reset while
CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function only if WDT clock source is
selected as 10 kHz
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6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer is used is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter value (WWDTVAL[5:0]) and 6-bit compare window value
(WWDTCR[21:16]) to make the WWDT time-out window period flexible
Supports 4-bit value to programmable maximum 11-bit prescale counter period of
WWDT counter
6.12 Real Time Clock (RTC)
6.12.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
The RTC controller also offers 80 bytes spare registers to store user’s important information.
6.12.2 Features
Supports real time counter in Time Loading Register (TLR) (hour, minute, second)
and calendar counter in Calendar Loading Register (CLR) (year, month, day) for RTC
time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings
in Time Alarm Register (TAR) and Calendar Alarm Register (CAR) register
Selectable 12-hour or 24-hour time scale in Time Scale Selection Register (TSSR)
register
Supports Leap Year indication in Leap Year Indicator Register (LIR) register
Supports Day of the Week counter in Day of the Week Register (DWR) register
Frequency of RTC clock source compensate by RTC Frequency Compensation
Register (FCR) register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
Supports 80 bytes spare registers
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6.13 UART Interface Controller (UART)
6.13.1 Overview
The NuMicro NUC230/240 series provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART. Besides, only UART0 and UART1 support the flow control function. The
UART Controller performs a serial-to-parallel conversion on data received from the peripheral,
and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also
supports IrDA SIR Function, LIN master/slave function and RS-485 function mode. Each UART
Controller channel supports seven types of interrupts.
6.13.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for
data payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and
programmable RTS flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function (UART0 and UART1 support)
Supports 7-bit receiver buffer time-out detection function
UART0/UART1 can through DMA channels to receive/transmit data
Programmable transmitting data delay time between the last stop and the next start bit
by setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow
detect function
Fully programmable serial-interface characteristics
-
-
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
-
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
-
-
-
-
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode.
-
-
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by RTS pin
(UART0 and UART1 support)
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6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal. It also
support UART mode for full duplex asynchronous communications.
6.14.2 Features
Supports up to three ISO7816-3 ports (SC0, SC1 and SC2)
-
-
-
-
-
-
-
ISO7816-3 T=0, T=1 compliant
EMV2000 compliant
Separates receive/ transmit 4 byte entry FIFO for data payloads.
Programmable transmission clock frequency.
Programmable receiver buffer trigger level.
Programmable guard time selection (11 ETU ~ 267 ETU).
A 24-bit and two 8-bit times for Answer to Request (ATR) and waiting times
processing.
-
-
-
Supports auto inverse convention function.
Supports transmitter and receiver error retry and error number limiting function.
Supports hardware activation sequence, hardware warm reset sequence and
hardware deactivation sequence process.
-
Supports hardware auto deactivation sequence when detecting the card
removal.
Supports up to three UART ports (UART3, UART4, UART5)
-
-
-
-
-
-
Full duplex, asynchronous communications.
Programmable data bit length, 5-, 6-, 7-, 8-bit character.
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
Supports programmable baud rate generator for each channel.
Supports programmable receiver buffer trigger level.
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SCx_EGTR [EGT] register.
-
-
Programmable even, odd or no parity bit generation and detection.
Programmable stop bit, 1 or 2 stop bit generation.
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6.15 PS/2 Device Controller (PS2D)
6.15.1 Overview
PS/2 device controller provides a basic timing control for PS/2 communication. All communication
between the device and the host is managed through the PS2_CLK and PS2_DATA pins. Unlike
PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as
meaningful code by firmware. The device controller generates the PS2_CLK signal after receiving
a “Request to Send” state, but host has ultimate control over communication. Data of PS2_DATA
line sent from the host to the device is read on the rising edge and sent from the device to the
host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software
can select 1 to 16 bytes for a continuous transmission.
6.15.2 Features
Host communication inhibit and "Request-to-Send" state detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
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6.16 I2C Serial Interface Controller (I2C)
6.16.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange
between devices. The I2C standard is a true multi-master bus including collision detection and
arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
6.16.2 Features
The I2C bus uses two wires (I2Cn_SDA and I2Cn_SCL) to transfer information between devices
connected to the bus. The main features of the I2C bus include:
Supports up to two I2C serial interface controller
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in a 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
6.17 Serial Peripheral Interface (SPI)
6.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro NUC230/240 series contains up to four sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable bus clock function for special applications and 2-bit
Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports
the PDMA function to access the data buffer and also supports Dual I/O Transfer mode.
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6.17.2 Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32 bits
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Two slave select lines in Master mode
Supports the Byte Reorder function
Supports Byte or Word Suspend mode
Variable output bus clock frequency in Master mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
6.18 I2S Controller (I2S)
6.18.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word
depth FIFO for reading path and writing path respectively and is capable of handling 8-, 16-, 24-
and 32-bit word sizes. PDMA controller handles the data movement between FIFO and memory.
6.18.2 Features
Supports Master mode and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports monaural and stereo audio data
Supports I2S and MSB justified data format
Provides two 8-word FIFO data buffers, one for transmitting and the other for
receiving
Supports PDMA transfer
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6.19 USB Device Controller (USBD)
6.19.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, and BUS events. Any event will cause an interrupt, and
users just need to check the related event flags in interrupt event status register (USB_INTSTS)
to acknowledge what kind of interrupt occurring, and then check the related USB Endpoint Status
Register (USB_EPSTS) to acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If DRVSE0 (USB_DRVSE0[0]) is set to 1, the USB
controller will force the output of USB_D+ and USB_D- to level low. After DRVSE0 bit is cleared
to 0, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1 for details.
6.19.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
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6.20 Controller Area Network (CAN)
6.20.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface (Refer 錯誤! 找不到參照來源。). The CAN Core performs communication
according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to
values up to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is
required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the
Message RAM. All functions concerning the handling of messages are implemented in the
Message Handler. These functions include acceptance filtering, the transfer of messages
between the CAN Core and the Message RAM, and the handling of transmission requests as well
as the generation of the module interrupt.
The register set of the C_CAN can be accessed directly by the software through the module
interface. These registers are used to control/configure the CAN Core and the Message Handler
and to access the Message RAM.
6.20.2 Features
Supports CAN protocol version 2.0 part A and B.
Bit rates up to 1 MBit/s.
32 Message Objects.
Each Message Object has its own identifier mask.
Programmable FIFO mode (concatenation of Message Objects).
Maskable interrupt.
Disabled Automatic Re-transmission mode for Time Triggered CAN applications.
Programmable loop-back mode for self-test operation.
16-bit module interfaces to the AMBA APB bus.
Supports wake-up function
6.21 Analog-to-Digital Converter (ADC)
6.21.1 Overview
The NuMicro NUC230/240 series contains one 12-bit successive approximation analog-to-
digital converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM Center-aligned trigger and external STADC pin.
6.21.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 8 single-end analog input channels or 4 differential analog input channels
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Up to 1 MSPS conversion rate (chip working at 5V)
Three operating modes
-
-
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
-
Continuous scan mode: A/D converter continuously performs Single-cycle scan
mode until software stops A/D conversion
An A/D conversion can be started by:
-
-
-
Writing 1 to ADST bit (ADCR[11])through software
PWM Center-aligned trigger
External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators
Supports two set digital comparators. The conversion result can be compared with
specify value and user can select whether to generate an interrupt when conversion
result matches the compare register setting
Channel 7 supports 3 input sources: external analog voltage, internal Band-gap
voltage, and internal temperature sensor output
6.22 Analog Comparator (ACMP)
6.22.1 Overview
The NuMicro NUC230/240 series contains two comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input voltage is greater
than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to
generate interrupt request when the comparator output value changes. The block diagram is
shown in 錯誤! 找不到參照來源。.
6.22.2 Features
Analog input voltage range: 0~ VDDA (Voltage of AVDD pin)
Supports Hysteresis function
Optional internal reference voltage source for each comparator negative input
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7
APPLICATION CIRCUIT
DVCC
[1]
AVCC
SPISS0
SPICLK0
MISO_0
AVDD
CS
VDD
CLK
MISO
MOSI
SPI Device
FB
DVCC
VDD
VSS
Power
MOSI_0
0.1uF
0.1uF
VSS
DVCC
4.7K
DVCC
FB
AVSS
4.7K
CLK
DIO
SCL0
SDA0
VDD
I2C Device
VDD
VSS
ICE_CLK
ICE_DAT
SWD
Interface
nRST
VSS
Smart Card
VCC
20p
20p
XTAL1
XTAL2
NUC2xx
Series
SC_PWR
Crystal
4~24 MHz
crystal
SC_RST
SC_CLK
Smart Card Slot
SC_DAT
SC_Detect
DVCC
ODB Port
CAN Transceiver
CAN_TX
CAN_RX
D
R
CAN_H
CAN_L
10K
Reset
Circuit
CAN
nRST
10uF/25V
PC COM Port
RS232 Transceiver
ROUT RIN
RXD
TXD
UART
TIN
TOUT
LDO_CAP
1uF
LDO
Note: For the SPI device, the chip supply voltage
must be equal to SPI device working voltage. For
example, when the SPI Flash working voltage is
3.3 V, the M05xx chip supply voltage must also
be 3.3V.
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8
ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
-0.3
+2.4
VSS-0.3
4
MAX
+7.0
+5.0
VDD+0.3
24
UNIT
V
DC Power Supply
VDDVSS
VBAT
VIN
Battery Power Supply
V
Input Voltage
V
Oscillator Frequency
1/tCLCL
TA
MHz
C
Operating Temperature
-40
+105
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
Maximum Current out of VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
mA
mA
mA
mA
mA
mA
120
35
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
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8.2 DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
Operation Voltage
Power Ground
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD
2.5
5.5
V
V
V
V
V
V
VDD = 2.5V ~ 5.5V up to 72 MHz
VSS
-0.3
1.62
1.22
AVSS
LDO Output Voltage
Band-gap Voltage
VLDO
1.8
1.25
VDD
1.98
1.28
VDD > 2.5V
VBG
VDD = 2.5 V ~ 5.5 V, TA = 25C
When system used analog function, please refer to
NUC230/240 Series Technical Reference Manual chapter
6.5 for corresponding analog operating voltage
Analog Operating
Voltage
AVDD
RTC Operating
Voltage
VBAT
2.5
5.5
All digital
module
VDD
HXT
HIRC
PLL
Operating Current
Normal Run Mode
at 72 MHz
IDD1
50
mA
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
V
V
V
V
V
X
V
X
IDD2
IDD3
IDD4
IDD5
20
48
18
34
mA
mA
mA
mA
5.5V
3.3V
3.3V
5.5V
while(1){} executed
from flash
VLDO =1.8 V
Operating Current
Normal Run Mode
at 50 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
4 MHz
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
X
X
X
X
X
X
X
X
V
X
V
X
V
X
V
X
V
X
V
X
IDD6
IDD7
15
32
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
while(1){} executed
from flash
IDD8
14
VLDO =1.8 V
Operating Current
Normal Run Mode
at 12 MHz
IDD9
8.5
3.6
7.5
2.6
3.6
2
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
while(1){} executed
from flash
VLDO =1.8 V
Operating Current
Normal Run Mode
at 4 MHz
4 MHz
while(1){} executed
from flash
2.8
1.2
4 MHz
4 MHz
VLDO =1.8 V
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
All digital
module
VDD
LXT (kHz)
HIRC
PLL
Operating Current
Normal Run Mode
at 32.768 kHz
IDD17
141
A
5.5V
5.5V
3.3V
3.3V
32.768
32.768
32.768
32.768
X
X
X
X
X
X
X
X
V
X
V
X
IDD18
IDD19
IDD20
129
138
125
A
A
A
while(1){} executed
from flash
VLDO =1.8 V
All digital
module
VDD
HXT/LXT LIRC (kHz)
PLL
Operating Current
Normal Run Mode
at 10 kHz
IDD21
125
A
5.5V
5.5V
3.3V
3.3V
X
X
X
X
10
10
10
10
X
X
X
X
V
X
V
X
IDD22
IDD23
IDD24
120
125
120
A
A
A
while(1){} executed
from flash
VLDO =1.8 V
All digital
module
VDD
HXT
HIRC
PLL
IIDLE1
42
mA
Operating Current
Idle Mode
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
V
X
X
V
X
V
X
V
X
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
11
41
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
at 72 MHz
VLDO =1.8 V
28
10
27
9
Operating Current
Idle Mode
at 50 MHz
VLDO =1.8 V
7.5
2.4
Operating Current
Idle Mode
at 12 MHz
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
IIDLE16
6.5
1.5
mA
mA
3.3V
3.3V
12 MHz
X
X
V
VLDO =1.8 V
12 MHz
4 MHz
4 MHz
X
X
X
X
X
X
X
V
X
3.3
1.7
mA
mA
5.5V
5.5V
Operating Current
Idle Mode
at 4 MHz
2.4
0.8
mA
mA
3.3V
3.3V
4 MHz
4 MHz
X
X
X
X
V
X
VLDO =1.8 V
All digital
module
VDD
LXT (kHz)
32.768
HIRC
X
PLL
X
Operating Current
Idle Mode
IIDLE17
133
120
A
A
5.5V
5.5V
V
X
at 32.768 kHz
VLDO =1.8 V
IIDLE18
32.768
X
X
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
IIDLE19
IIDLE20
133
3.3V
3.3V
A
A
32.768
32.768
X
X
X
X
V
X
120
122
All digital
module
VDD
HXT/LXT LIRC (kHz)
PLL
X
IIDLE21
A
5.5V
5.5V
X
X
X
X
10
10
10
10
V
X
V
X
Operating Current
Idle Mode
IIDLE22
IIDLE23
IIDLE24
118
122
118
A
A
A
X
at 10 kHz
3.3V
3.3V
X
X
HXT/HIRC
PLL
RAM
retension
VDD
LXT (kHz)
RTC
IPWD1
15
A
Standby Current
Power-down Mode
(Deep Sleep Mode)
VLDO =1.6 V
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
X
V
V
V
V
V
V
IPWD2
IPWD3
IPWD4
15
17
17
A
A
A
X
32.768
32.768
RTC Operating
Current
IVBAT
1.6
-50
VBAT= 3.0V, RTC enabled
A
Input Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
mode)
IIN1
-60
VDD = 5.5V, VIN = 0V or VIN=VDD
A
Input Current at
/RESET[1]
IIN2
-55
-2
-45
-
-30
+2
VDD = 3.3V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
A
A
Input Leakage
Current PA, PB, PC,
PD, PE, PF
ILK
Logic 1 to 0
Transition Current
PA~PF (Quasi-
bidirectional mode)
[3]
ITL
-650
-
-200
VDD = 5.5V, VIN<2.0V
A
Input Low Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
-0.3
-0.3
-
-
0.8
0.6
VDD = 4.5V
VDD = 2.5V
VIL1
V
VDD
+0.2
2.0
1.5
-
-
VDD = 5.5V
VDD =3.0V
Input High Voltage
PA, PB, PC, PD, PE,
PF (TTL input)
VIH1
V
VDD
+0.2
Input Low Voltage
PA, PB, PC, PD, PE,
PF (Schmitt input)
VIL2
-0.3
-
-
0.3VDD
V
V
Input High Voltage
PA, PB, PC, PD, PE,
PF (Schmitt input)
VDD
+0.2
VIH2
0.7VDD
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SPECIFICATION
PARAMETER
SYM.
VHY
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Hysteresis voltage of
PA, PB, PC, PD,PE,
PF (Schmitt input)
0.2VDD
V
0
0
-
-
0.8
0.4
VDD = 4.5V
V
Input Low Voltage
XT1_IN[*2]
VIL3
VDD = 3.0V
VDD
+0.2
3.5
2.4
0
-
-
-
V
VDD = 5.5V
VDD = 3.0V
Input High Voltage
XT1_IN[*2]
VIH3
VDD
+0.2
Input Low Voltage
X32I[*2]
VIL4
0.4
1.8
v
Input High Voltage
X32I[*2]
VIH4
1.2
V
Negative going
threshold
0.2VDD
-0.2
VILS
-0.5
-
-
V
V
(Schmitt input),
/RESET
Positive going
threshold
VDD
+0.5
VIHS
0.7VDD
(Schmitt input),
/RESET
ISR11
ISR12
ISR12
ISR21
ISR22
-300
-50
-40
-24
-4
-370
-70
-60
-28
-6
-450
-90
-80
-32
-8
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
A
A
A
Source Current PA,
PB, PC, PD, PE, PF
(Quasi-bidirectional
Mode)
mA VDD = 4.5V, VS = 2.4V
mA VDD = 2.7V, VS = 2.2V
Source Current PA,
PB, PC, PD, PE, PF
(Push-pull Mode)
ISR22
ISK1
ISK1
ISK1
-3
10
7
-5
16
10
9
-7
20
13
12
mA VDD = 2.5V, VS = 2.0V
mA VDD = 4.5V, VS = 0.45V
mA VDD = 2.7V, VS = 0.45V
mA VDD = 2.5V, VS = 0.45V
Sink Current PA, PB,
PC, PD, PE, PF
(Quasi-bidirectional
and Push-pull Mode)
6
Brown-out Voltage
with
BOD_VL [1:0] = 00b
VBO2.2
VBO2.7
VBO3.7
VBO4.4
2.1
2.6
3.5
4.2
2.2
2.7
3.7
4.4
2.3
2.8
3.9
4.6
V
V
V
V
Brown-out Voltage
with
BOD_VL [1:0] = 01b
Brown-out voltage
with
BOD_VL [1:0] = 10b
Brown-out Voltage
with
BOD_VL [1:0] = 11b
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Hysteresis range of
BOD voltage
VBH
30
-
150
mV VDD = 2.5V~5.5V
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from 1 to 0. In the
condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates to 2 V.
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8.3 AC Electrical Characteristics
8.3.1 External 4~24 MHz High Speed Oscillator
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
CONDITION
MIN.
10
10
2
TYP.
MAX.
UNIT
nS
-
-
-
-
-
tCLCX
-
nS
tCLCH
15
15
nS
tCHCL
2
nS
8.3.2 External 4~24 MHz High Speed Crystal
PARAMETER
Operation Voltage VDD
Temperature
CONDITION
MIN.
2.5
-40
-
TYP..
MAX.
5.5
105
-
UNIT
V
-
-
-
-
℃
Operating Current
Clock Frequency
12 MHz at VDD = 5V
External crystal
2
mA
MHz
4
24
8.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4 MHz ~ 24 MHz
10~20pF
10~20pF
without
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
XT1_OUT
XT1_IN
R
C1
C2
Figure 8-1 Typical Crystal Application Circuit
8.3.3 External 32.768 kHz Low Speed Crystal Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
TYP.
MAX.
5.5
UNIT
V
-
-
-
-
℃
Operation Temperature
Operation Current
Clock Frequency
-40
105
32.768KHz at VDD=5V
External crystal
1.6
A
-
32.768
-
kHz
8.3.4 Internal 22.1184 MHz High Speed Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
-
TYP.
MAX.
5.5
-
UNIT
V
-
-
Center Frequency
-
22.1184
-
MHz
%
+25℃; VDD =5 V
-1
+1
Calibrated Internal Oscillator Frequency
Operation Current
-40℃~+105℃;
-3
-
-
+3
-
%
VDD=2.5 V~5.5 V
VDD =5 V
800
uA
8.3.5 Internal 10 kHz Low Speed Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
-
TYP.
MAX.
5.5
-
UNIT
V
-
-
10
-
Center Frequency
-
kHz
%
+25℃; VDD =5 V
-20
+20
Calibrated Internal Oscillator Frequency
-40℃~+105℃;
-50
-
+50
%
VDD=2.5 V~5.5 V
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
8.4 Analog Characteristics
8.4.1 12-bit SARADC Specification
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
12
UNIT
Bit
-
Resolution
-
-
-
-
-
-
DNL
INL
EO
EG
-
Differential nonlinearity error
Integral nonlinearity error
Offset error
-1~2
-1~4
±4
LSB
LSB
LSB
-
±2
2
4
Gain error (Transfer gain)
Monotonic
-2
-4
Guaranteed
FADC
FS
ADC clock frequency (AVDD = 5V/3V)
Sample rate
-
-
-
-
16/8
1
MHz
MSPS
VDDA
Supply voltage
3
-
5.5
V
IDDA
VREF
VIN
Supply current (Avg.)
Reference voltage
Input voltage
2.9
mA
V
3
0
VDDA
VREF
-
V
8.4.2 LDO and Power Management Specification
PARAMETER
MIN.
2.5
TYP.
MAX.
5.5
UNIT
V
NOTE
Input Voltage VDD
Output Voltage
VDD input voltage
VDD > 2.5 V
1.62
1.8
1.98
V
℃
Operating Temperature
-40
-
25
1
105
-
Cbp
RESR = 1 Ω
F
Note:
1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between VDD and the
closest VSS pin of the device.
2. To ensure power stability, an 1 F or higher capacitor must be connected between LDO_CAP pin and the closest VSS pin of
the device.
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
8.4.3 Low Voltage Reset Specification
PARAMETER
Operation Voltage
CONDITION
MIN.
0
TYP.
MAX.
5.5
5
UNIT
V
-
-
Quiescent Current
AVDD=5.5 V
-
-
1
A
℃
Operation Temperature
-40
25
105
Threshold Voltage
Hysteresis
-
-
1.6
0
2.0
0
2.4
0
V
V
8.4.4 Brown-out Detector Specification
PARAMETER
Operation Voltage
CONDITION
MIN.
0
TYP.
-
MAX.
5.5
UNIT
V
-
℃
μA
V
Temperature
-
-40
-
25
-
105
125
4.6
Quiescent Current
AVDD=5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
4.2
3.5
2.6
2.1
30
4.4
3.7
2.7
2.2
-
3.9
V
Brown-out Voltage
2.8
V
2.3
V
Hysteresis
150
mV
8.4.5 Power-on Reset Specification
PARAMETER
Operation Temperature
Reset Voltage
CONDITION
MIN.
TYP.
25
2
MAX.
UNIT
℃
-
V+
-40
105
-
-
-
-
V
Quiescent Current
Vin > reset voltage
1
nA
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
8.4.6 Temperature Sensor Specification
PARAMETER
Operation Voltage[1]
Operation Temperature
Current Consumption
Gain
CONDITIONS
MIN.
2.5
TYP.
-
MAX.
5.5
UNIT
V
℃
-40
-
105
16
μA
mV/℃
mV
-1.55
735
-1.65
745
-1.75
755
Temp=0 ℃
Offset Voltage
Note: Internal operation voltage comes from internal LDO.
8.4.7 Comparator Specification
PARAMETER
Operation Voltage AVDD
CONDITION
MIN.
2.5
-40
-
TYP.
MAX.
5.5
UNIT
V
-
℃
Operation Temperature
Operation Current
Input Offset Voltage
Output Swing
-
25
20
10
-
105
40
VDD=3.0 V
μA
mV
V
-
-
20
-
0.1
0.1
-
VDD-0.1
VDD-1.2
-
Input Common Mode Range
DC Gain
-
-
V
-
70
200
dB
ns
Propagation Delay
VCM=1.2 V and VDIFF=0.1 V
-
-
20 mV at VCM=1 V
50 mV at VCM=0.1 V
50 mV at VCM=VDD-1.2
10 mV for non-hysteresis
Comparison Voltage
10
20
-
mV
Hysteresis
VCM=0.4 V ~ VDD-1.2 V
-
-
±10
-
-
mV
CINP=1.3 V
CINN=1.2 V
Wake-up Time
2
μs
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
8.4.8 USB PHY Specification
8.4.8.1 USB DC Electrical Characteristics
SYMBOL
PARAMETER
Input High (driven)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIH
VIL
VDI
2.0
V
V
V
Input Low
0.8
Differential Input Sensitivity
|PADP-PADM|
0.2
0.8
0.8
Differential
VCM
VSE
Includes VDI range
2.5
2.0
V
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
V
mV
V
200
VOL
Output Low (driven)
0
0.3
3.6
VOH
VCRS
RPU
Output High (driven)
2.8
V
Output Signal Cross Voltage
Pull-up Resistor
1.3
2.0
V
1.425
1.575
kΩ
Termination Voltage for Upstream Port
Pull-up (RPU)
VTRM
3.0
3.6
V
ZDRV
CIN
Driver Output Resistance
Transceiver Capacitance
Steady state drive*
Pin to GND
10
Ω
20
pF
*Driver output resistance doesn’t include series resistor resistance.
8.4.8.2 USB Full-Speed Driver Electrical Characteristics
SYMBOL
PARAMETER
CONDITIONS
CL=50p
MIN.
4
TYP.
MAX.
20
UNIT
ns
TFR
TFF
Rise Time
Fall Time
CL=50p
4
20
ns
TFRFF
Rise and Fall Time Matching
TFRFF=TFR/TFF
90
111.11
%
8.4.8.3 USB Power Dissipation
SYMBOL
IVBUS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VBUS Current
(Steady State)
Standby
50
μA
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
8.4.8.4 USB LDO Specification
SYMBOL
VBUS
PARAMETER
CONDITIONS
MIN.
4.0
TYP.
5.0
MAX.
5.5
3.6
-
UNIT
V
VBUS Pin Input Voltage
LDO Output Voltage
VDD33
Cbp
3.0
3.3
V
External Bypass Capacitor
1.0
uF
8.5 Flash DC Electrical Characteristics
SYMBOL
VDD
NENDUR
TRET
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V[2]
Supply Voltage
1.62
10000
100
1.8
1.98
Endurance
cycles[1]
year
ms
At 25℃
Data Retention
Page Erase Time
Mass Erase Time
Program Time
TERASE
TMER
TPROG
IDD1
20
40
ms
40
μs
Read Current
-
0.15
0.5
7
mA/MHz
mA
IDD2
Program/Erase Current
1. Number of program/erase cycles.
2. VDD is source from chip LDO output voltage.
This table is guaranteed by design, not test in production.
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
9
PACKAGE DIMENSIONS
9.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm)
H
D
D
A
A2
7
A1
51
7
50
H
E E
100
26
L1
L
1
25
c
e
b
Y
Controlling Dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
A
Min Nom
Max
Min Nom
Max
1.60
0.063
A1
A
0.002
0.05
1.45
0.27
0.053 0.055 0.057
1.35
0.17
0.10
1.40
0.22
b
0.011
0.008
0.009
0.006
0.007
0.004
0.547
0.547
c
0.15
0.20
D
E
14.00
0.551
0.551
0.020
14.10
13.90
13.90
0.556
0.556
14.00 14.10
0.50
e
H D
16.00
16.20
16.20
16.00
15.80
15.80
0.45
0.622
0.638
0.638
0.030
0.630
H E
L
0.622 0.630
0.60
1.00
0.75
0.024
0.039
0.018
L1
y
0.10
7
0.004
7
0
0
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
9.2 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Dec. 30, 2014
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NuMicro NUC230/240 Datasheet
9.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Max
Min
Max Min
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.45
0.25
0.20
7.10
7.10
0.65
9.10
1.40
0.20
A
0.006
0.004
0.272
0.272
0.014
0.350
0.350
0.018
0.15
0.008 0.010
b
c
D
0.006
0.276
0.276
0.020
0.10 0.15
0.008
0.280
0.280
0.026
0.358
7.00
7.00
6.90
6.90
0.35
8.90
E
0.50
9.00
e
H
D
0.354
0.358
0.030
8.90
0.45
9.00
0.60
1.00
9.10
0.75
0.354
0.024
E
H
L
0.039
1
L
Y
0.004
7
0.10
7
0
0
0
Dec. 30, 2014
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Revision 1.01
NuMicro NUC230/240 Datasheet
10 REVISION HISTORY
REVISION
DATE
DESCRIPTION
1.00
May 12, 2014
Preliminary version
1, Added EBI function
1.01
Dec. 30,2014
2, Rearranged the chepter sequence.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Dec. 30, 2014
Page 97 of 97
Revision 1.01
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