NUC940-SC1N [NUVOTON]
ARM® Cortexâ¢-M0 core;
| 型号： | NUC940-SC1N |
| 厂家： | 
NUVOTON |
| 描述： | ARM® Cortexâ¢-M0 core |
| 文件： | 总100页 (文件大小：1834K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NuMicro NUC200/220 Series Datasheet
NuMicro™ NUC200/220 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicroTM microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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NuMicro NUC200/220 Series Datasheet
Table of Contents
LIST OF FIGURES.................................................................................................................................. 5
LIST OF TABLES .................................................................................................................................... 6
1
2
GENERAL DESCRIPTION ......................................................................................................... 7
FEATURES ................................................................................................................................. 8
2.1
2.2
NuMicro NUC200 Features – Advanced Line.............................................................. 8
NuMicro NUC220 Features – USB Line .................................................................... 12
3
PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 16
3.1
3.2
3.3
NuMicro NUC200/220xxxAN Selection Guide........................................................... 16
3.1.1 NuMicro NUC200 Advanced Line Selection Guide......................................................16
3.1.2 NuMicro NUC220 USB Line Selection Guide ..............................................................16
Pin Configuration .......................................................................................................... 18
3.2.1 NuMicro NUC200 Pin Diagram....................................................................................18
3.2.2 NuMicro NUC220 Pin Diagram....................................................................................21
Pin Description.............................................................................................................. 24
3.3.1 NuMicro NUC200 Pin Description................................................................................24
3.3.2 NuMicro NUC220 Pin Description................................................................................31
4
5
BLOCK DIAGRAM .................................................................................................................... 38
4.1
4.2
NuMicro NUC200 Block Diagram .............................................................................. 38
NuMicro NUC220 Block Diagram .............................................................................. 39
FUNCTIONAL DESCRIPTION.................................................................................................. 40
5.1
5.2
ARM® Cortex™-M0 Core.............................................................................................. 40
System Manager........................................................................................................... 42
5.2.1 Overview ........................................................................................................................42
5.2.2 System Reset.................................................................................................................42
5.2.3 System Power Distribution .............................................................................................43
5.2.4 System Memory Map......................................................................................................45
5.2.5 System Timer (SysTick) .................................................................................................47
5.2.6 Nested Vectored Interrupt Controller (NVIC)..................................................................48
5.2.7 System Control (SCS) ....................................................................................................54
Clock Controller ............................................................................................................ 54
5.3
5.3.1 Overview ........................................................................................................................54
5.3.2 Clock Generator .............................................................................................................57
5.3.3 System Clock and SysTick Clock ...................................................................................58
5.3.4 Peripherals Clock ...........................................................................................................59
5.3.5 Power-down Mode Clock................................................................................................59
5.3.6 Frequency Divider Output...............................................................................................60
USB Device Controller (USB)....................................................................................... 61
5.4
5.5
5.4.1 Overview ........................................................................................................................61
5.4.2 Features .........................................................................................................................61
General Purpose I/O (GPIO) ........................................................................................ 62
5.5.1 Overview ........................................................................................................................62
5.5.2 Features .........................................................................................................................62
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5.6
5.7
5.8
5.9
I2C Serial Interface Controller (I2C)............................................................................... 63
5.6.1 Overview ........................................................................................................................63
5.6.2 Features .........................................................................................................................64
PWM Generator and Capture Timer (PWM) ................................................................ 65
5.7.1 Overview ........................................................................................................................65
5.7.2 Features .........................................................................................................................66
Real Time Clock (RTC)................................................................................................. 67
5.8.1 Overview ........................................................................................................................67
5.8.2 Features .........................................................................................................................67
Serial Peripheral Interface (SPI)................................................................................... 68
5.9.1 Overview ........................................................................................................................68
5.9.2 Features .........................................................................................................................68
5.10 Timer Controller (TMR)................................................................................................. 69
5.10.1 Overview ......................................................................................................................69
5.10.2 Features .......................................................................................................................69
5.11 Watchdog Timer (WDT)................................................................................................ 70
5.11.1 Overview ......................................................................................................................70
5.11.2 Features .......................................................................................................................70
5.12 Window Watchdog Timer (WWDT)............................................................................... 70
5.12.1 Overview ......................................................................................................................70
5.12.2 Features .......................................................................................................................70
5.13 UART Interface Controller (UART) ............................................................................... 71
5.13.1 Overview ......................................................................................................................71
5.13.2 Features .......................................................................................................................73
5.14 PS/2 Device Controller (PS2D)..................................................................................... 74
5.14.1 Overview ......................................................................................................................74
5.14.2 Features .......................................................................................................................74
5.15 I2S Controller (I2S)......................................................................................................... 75
5.15.1 Overview ......................................................................................................................75
5.15.2 Features .......................................................................................................................75
5.16 Analog-to-Digital Converter (ADC) ............................................................................... 76
5.16.1 Overview ......................................................................................................................76
5.16.2 Features .......................................................................................................................76
5.17 Analog Comparator (ACMP)......................................................................................... 77
5.17.1 Overview ......................................................................................................................77
5.17.2 Features .......................................................................................................................77
5.18 PDMA Controller (PDMA) ............................................................................................. 78
5.18.1 Overview ......................................................................................................................78
5.18.2 Features .......................................................................................................................78
5.19 Smart Card Host Interface (SC).................................................................................... 79
5.19.1 Overview ......................................................................................................................79
5.19.2 Features .......................................................................................................................79
5.20 FLASH MEMORY CONTROLLER (FMC) .................................................................... 80
5.20.1 Overview ......................................................................................................................80
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5.20.2 Features .......................................................................................................................80
APPLICATION CIRCUIT........................................................................................................... 81
ELECTRICAL CHARACTERISTICS......................................................................................... 82
6
7
7.1
7.2
7.3
Absolute Maximum Ratings.......................................................................................... 82
DC Electrical Characteristics ........................................................................................ 83
AC Electrical Characteristics ........................................................................................ 88
7.3.1 External 4~24 MHz High Speed Oscillator .....................................................................88
7.3.2 External 4~24 MHz High Speed Crystal .........................................................................88
7.3.3 External 32.768 kHz Low Speed Crystal Oscillator ........................................................89
7.3.4 Internal 22.1184 MHz High Speed Oscillator..................................................................89
7.3.5 Internal 10 kHz Low Speed Oscillator.............................................................................90
Analog Characteristics.................................................................................................. 90
7.4
7.4.1 12-bit SARADC Specification .........................................................................................90
7.4.2 LDO and Power Management Specification...................................................................90
7.4.3 Low Voltage Reset Specification ....................................................................................92
7.4.4 Brown-out Detector Specification ...................................................................................92
7.4.5 Power-on Reset Specification ........................................................................................92
7.4.6 Temperature Sensor Specification .................................................................................93
7.4.7 Comparator Specification ...............................................................................................93
7.4.8 USB PHY Specification ..................................................................................................94
Flash DC Electrical Characteristics .............................................................................. 96
7.5
8
9
PACKAGE DIMENSIONS......................................................................................................... 97
8.1
8.2
8.3
100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) ......................................................... 97
64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................................... 98
48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................................... 99
REVISION HISTORY.............................................................................................................. 100
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List of Figures
Figure 3-1 NuMicro NUC200 Series Selection Code.................................................................. 17
Figure 3-2 NuMicro NUC200VxxAN LQFP 100-pin Diagram ..................................................... 18
Figure 3-3 NuMicro NUC200SxxAN LQFP 64-pin Diagram ....................................................... 19
Figure 3-4 NuMicro NUC200LxxAN LQFP 48-pin Diagram........................................................ 20
Figure 3-5 NuMicro NUC220VxxAN LQFP 100-pin Diagram ..................................................... 21
Figure 3-6 NuMicro NUC220SxxAN LQFP 64-pin Diagram ....................................................... 22
Figure 3-7 NuMicro NUC220LxxAN LQFP 48-pin Diagram........................................................ 23
Figure 4-1 NuMicro NUC200 Block Diagram .............................................................................. 38
Figure 4-2 NuMicro NUC220 Block Diagram .............................................................................. 39
Figure 5-1 Functional Controller Diagram...................................................................................... 40
Figure 5-2 NuMicro NUC200 Power Distribution Diagram.......................................................... 43
Figure 5-3 NuMicro NUC220 Power Distribution Diagram.......................................................... 44
Figure 5-4 Clock Generator Global View Diagram......................................................................... 55
Figure 5-5 Clock Generator Block Diagram................................................................................... 57
Figure 5-6 System Clock Block Diagram ....................................................................................... 58
Figure 5-7 SysTick Clock Control Block Diagram.......................................................................... 58
Figure 5-8 Clock Source of Frequency Divider .............................................................................. 60
Figure 5-9 Frequency Divider Block Diagram ................................................................................ 60
Figure 5-18 I2C Bus Timing............................................................................................................ 63
Figure 6-1 Typical Crystal Application Circuit ................................................................................ 89
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List of Tables
Table 1-1 Connectivity Support Table.............................................................................................. 7
Table 5-1 Address Space Assignments for On-Chip Controllers................................................... 46
Table 5-2 Exception Model ............................................................................................................ 49
Table 5-3 System Interrupt Map..................................................................................................... 50
Table 5-4 Vector Table Format ...................................................................................................... 51
Table 5-9 UART Baud Rate Equation............................................................................................ 71
Table 5-10 UART Baud Rate Setting Table................................................................................... 72
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1
GENERAL DESCRIPTION
The NuMicro NUC200 Series 32-bit microcontrollers is embedded with the newest ARM®
Cortex™-M0 core with a cost equivalent to traditional 8-bit MCU for industrial control and
applications requiring rich communication interfaces. The NuMicro NUC200 Series includes
NUC200 and NUC220 product lines.
The NuMicro NUC200 Advanced Line is embedded with the Cortex™-M0 core running up to 50
MHz and features 32K/64K/128K bytes flash, 8K/16K bytes embedded SRAM, and 4 Kbytes
loader ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers,
Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI,
I2C, I2S, PWM Timer, GPIO, PS/2, Smart Card Host, 12-bit ADC, Analog Comparator, Low
Voltage Reset Controller and Brown-out Detector.
The NuMicro NUC220 USB Line with USB 2.0 full-speed function is embedded with the
Cortex™-M0 core running up to 50 MHz and features 32K/64K/128K bytes flash, 8K/16K bytes
embedded SRAM, and 4 Kbytes loader ROM for the ISP. It is also equipped with plenty of
peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with
CRC calculation unit, UART, SPI, I2C, I2S, PWM Timer, GPIO, PS/2, USB 2.0 FS Device, Smart
Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out
Detector.
Product Line
NUC200
UART
SPI
●
I2C
●
USB
LIN
CAN
PS/2
I2S
●
SC
●
●
●
●
●
NUC220
●
●
●
●
●
Table 1-1 Connectivity Support Table
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2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1 NuMicro NUC200 Features – Advanced Line
ARM® Cortex™-M0 core
–
Runs up to 50 MHz
–
–
–
–
–
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
–
–
–
32K/64K/128K bytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
–
–
512 byte page erase for flash
Configurable data flash address and size for 128 KB system, fixed 4 KB data flash for
the 32 KB and 64 KB system
–
–
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
SRAM Memory
–
–
8K/16K bytes embedded SRAM
Supports PDMA mode
PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
–
Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-
16 and CRC-32
Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to
1 % at +25 ℃ and VDD = 5 V
Trimmed to
3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
–
–
–
–
Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
Supports one PLL, up to 50 MHz, for high performance system operation
External 4~24 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–
–
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level setting
Timer
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–
–
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Supports event counting function
Supports input capture function
Watchdog Timer
–
–
–
–
Multiple clock sources
8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
Wake-up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
6-bit down counter with 11-bit prescale for wide range window selected
RTC
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
–
–
–
–
–
–
Supports battery power pin (VBAT
Supports wake-up function
)
PWM/Capture
–
–
–
–
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
Supports Capture interrupt
UART
–
–
–
–
–
–
–
–
Up to three UART controllers
UART ports with flow control (TXD, RXD, nCTS and nRTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
SPI
–
–
–
–
–
–
–
–
–
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
–
Supports Byte Suspend mode in 32-bit transmission
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–
–
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
I2C
–
–
–
–
–
Up to two sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
–
–
–
I2S
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
–
–
–
–
–
–
–
–
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
–
–
–
–
–
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
ADC
–
–
–
–
–
–
–
–
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Supports PDMA mode
Analog Comparator
–
Up to two analog comparators
–
–
–
External input or internal Band-gap voltage selectable at negative node
Interrupt when compare result change
Supports Power-down wake-up
Smart Card Host (SC)
–
Compliant to ISO-7816-3 T=0, T=1
–
–
–
Supports up to three ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
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–
–
–
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
–
–
–
–
–
–
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
96-bit unique ID (UID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
–
–
With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 85℃
Packages:
–
–
All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin
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NuMicro NUC200/220 Series Datasheet
2.2 NuMicro NUC220 Features – USB Line
ARM® Cortex™-M0 core
–
Runs up to 50 MHz
–
–
–
–
–
One 24-bit system timer
Supports low power sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
–
–
–
32K/64K/128K bytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
–
–
512 byte page erase for flash
Configurable data flash address and size for 128 KB system, fixed 4 KB data flash for
the 32 KB and 64 KB system
–
–
Supports 2-wired ICP update through SWD/ICE interface
Supports fast parallel programming mode by external programmer
SRAM Memory
–
–
8K/16K bytes embedded SRAM
Supports PDMA mode
PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
–
Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-
16 and CRC-32
Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to
1 % at +25 ℃ and VDD = 5 V
Trimmed to
3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
–
–
–
–
Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
Supports one PLL, up to 50 MHz, for high performance system operation
External 4~24 MHz high speed crystal input for USB and precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–
–
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level setting
Timer
–
–
–
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
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NuMicro NUC200/220 Series Datasheet
–
–
Supports event counting function
Supports input capture function
Watchdog Timer
–
–
–
–
Multiple clock sources
8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
Wake-up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
–
6-bit down counter with 11-bit prescale for wide range window selected
RTC
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
–
–
–
–
–
–
–
Supports battery power pin (VBAT
Supports wake-up function
)
PWM/Capture
–
–
–
–
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
Supports Capture interrupt
UART
–
–
–
–
–
–
–
–
Up to three UART controllers
UART ports with flow control (TXD, RXD, nCTS and nRTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
SPI
–
–
–
–
–
–
–
–
–
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
–
–
–
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
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I2C
–
Up to two sets of I2C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
–
–
–
–
–
–
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
–
–
–
I2S
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
–
–
–
–
–
–
–
–
Interface with external audio CODEC
Operate as either Master or Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Supports two DMA requests, one for transmitting and the other for receiving
PS/2 Device
–
–
–
–
–
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
USB 2.0 Full-Speed Device
–
One set of USB 2.0 FS Device 12 Mbps
–
–
–
–
–
–
–
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 6 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
ADC
–
–
–
–
–
–
–
–
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Supports PDMA mode
Analog Comparator
–
Up to two analog comparators
–
External input or internal Band-gap voltage selectable at negative node
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NuMicro NUC200/220 Series Datasheet
–
–
Interrupt when compare result change
Supports Power-down wake-up
Smart Card Host (SC)
–
Compliant to ISO-7816-3 T=0, T=1
–
–
–
–
–
–
Supports up to three ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
–
–
–
–
–
–
Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
96-bit unique ID (UID)
One built-in temperature sensor with 1℃ resolution
Brown-out Detector
–
–
With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage level: 2.0 V
Operating Temperature: -40℃ ~ 85℃
Packages:
–
–
All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
3
PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro NUC200/220xxxAN Selection Guide
3.1.1 NuMicro NUC200 Advanced Line Selection Guide
Connectivity
ISP
Data
Flash
I2S
SC Comp. PWM ADC RTC
Package
ISP
ICP
IAP
Part number APROM RAM
Loader
ROM
I/O
Timer
UART SPI I2C USB LIN CAN
2
2
2
2
2
2
3
NUC200LC2AN 32 KB 8 KB
NUC200LD2AN 64 KB 8 KB
4 KB
4KB
4 KB up to 35 4x32-bit
4 KB up to 35 4x32-bit
2
2
2
3
3
3
3
1
1
1
2
2
2
4
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
2
2
2
2
6
6
6
6
6
6
8
7x12-bit
7x12-bit
7x12-bit
7x12-bit
7x12-bit
7x12-bit
8x12-bit
v
v
v
v
v
v
v
v
v
v
v
v
v
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP100
NUC200LE3AN 128 KB 16 KB Definable 4 KB up to 35 4x32-bit
NUC200SC2AN 32 KB 8 KB
NUC200SD2AN 64 KB 8 KB
4 KB
4KB
4 KB up to 49 4x32-bit
4 KB up to 49 4x32-bit
NUC200SE3AN 128 KB 16 KB Definable 4 KB up to 49 4x32-bit
NUC200VE3AN 128 KB 16 KB Definable 4 KB up to 83 4x32-bit
3.1.2 NuMicro NUC220 USB Line Selection Guide
Connectivity
ISP
Loader
ROM
ISP
Data
Flash
Part number APROM RAM
I/O
Timer
I2S
SC Comp. PWM ADC RTC ICP Package
IAP
UART SPI I2C USB LIN CAN
2
2
2
2
2
2
3
NUC220LC2AN 32 KB 8 KB
NUC220LD2AN 64 KB 8 KB
4 KB
4 KB
4 KB up to 31 4x32-bit
4 KB up to 31 4x32-bit
2
2
2
2
2
2
3
1
1
1
2
2
2
4
2
2
2
2
2
2
2
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
2
2
2
2
4
4
4
6
6
6
8
7x12-bit
7x12-bit
7x12-bit
7x12-bit
7x12-bit
7x12-bit
8x12-bit
v
v
v
v
v
v
v
v
v
v
v
v
v
v
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP100
NUC220LE3AN 128 KB 16 KB Definable 4 KB up to 31 4x32-bit
NUC220SC2AN 32 KB 8 KB
NUC220SD2AN 64 KB 8 KB
4 KB
8 KB
4 KB up to 45 4x32-bit
4 KB up to 45 4x32-bit
NUC220SE3AN 128 KB 16 KB Definable 4 KB up to 45 4x32-bit
NUC220VE3AN 128 KB 16 KB Definable 4 KB up to 79 4x32-bit
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
NUC 2 0 0 - X X X X X
ARM-Based
32-bit Microcontroller
Temperature
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
CPU core
1/2: Cortex-M0
5/7: ARM7
9: ARM9
Reserved
RAM Size
1: 4KB
2: 8KB
Function
0: Advanced Line
2: USB Line
3: Automotive Line
4: Connectivity Line
3: 16KB
APROM Size
C: 32KB
D: 64KB
E: 128KB
Package Type
L: LQFP 48
S: LQFP 64
V: LQFP 100
Figure 3-1 NuMicro NUC200 Series Selection Code
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NuMicro NUC200/220 Series Datasheet
3.2 Pin Configuration
3.2.1 NuMicro NUC200 Pin Diagram
3.2.1.1 NuMicro NUC200VxxAN LQFP 100-pin
SC1_RST/ADC5/PA.5
SC1_CLK/ADC6/PA.6
SC1_DAT/ADC7/SPI2_SS1/PA.7
VREF
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM1/SPI1_SS1
PB.10/TM2/SPI0_SS1
PB.11/TM3/PWM4
PE.5/TM1_EXT/PWM5
PE.6
AVDD
SPI2_SS0/PD.0
SPI2_CLK/PD.1
SPI2_MISO0/PD.2
SPI2_MOSI0/PD.3
SPI2_MISO1/PD.4
SPI2_MOSI1/PD.5
SC1_CD/CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
CMP1_N/PC.15
CMP1_P/PC.14
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PC.4/SPI0_MISO1
PC.5/SPI0_MOSI1
PD.15/UART2_TXD
PD.14/UART2_RXD
PD.7
NUC200VxxAN
LQFP 100-pin
PD.6
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
PB.0/UART0_RXD
PE.7
nRESET
VSS
VDD
PE.8
PS2_DAT/PF.2
PS2_CLK/PF.3
PVSS
PE.9
PE.10
PE.11
CLKO/TM0/STADC/PB.8
PE.12
Figure 3-2 NuMicro NUC200VxxAN LQFP 100-pin Diagram
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
3.2.1.2 NuMicro NUC200RxxAN LQFP 64-pin
ADC5/PA.5
ADC6/PA.6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
VREF
PB.11/TM3/PWM4
AVDD
PE.5/TM1_EXT/PWM5
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PD.15/UART2_TXD
PD.14/UART2_RXD
PD.7
CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
CMP1_N/PC.15
CMP1_P/PC.14
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
NUC200SxxAN
LQFP 64-pin
PD.6
VSS
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
VDD
PVSS
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 3-3 NuMicro NUC200SxxAN LQFP 64-pin Diagram
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
3.2.1.3 NuMicro NUC200LxxAN LQFP 48-pin
ADC5/PA.5
ADC6/PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PB.9/TM1
PB.10/TM2
VREF
PB.11/TM3/PWM4
AVDD
PE.5/TM1_EXT/PWM5
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC200LxxAN
LQFP 48-pin
nRESET
PVSS
CLKO/TM0/STADC/PB.8
PB.0/UART0_RXD
Figure 3-4 NuMicro NUC200LxxAN LQFP 48-pin Diagram
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
3.2.2 NuMicro NUC220 Pin Diagram
3.2.2.1 NuMicro NUC220VxxAN LQFP 100-pin
SC1_RST/ADC5/PA.5
SC1_CLK/ADC6/PA.6
SC1_DAT/ADC7/SPI2_SS1/PA.7
VREF
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PB.9/TM1/SPI1_SS1
PB.10/TM2/SPI0_SS1
PB.11/TM3/PWM4
PE.5/TM1_EXT/PWM5
PE.6
AVDD
SPI2_SS0/PD.0
SPI2_CLK/PD.1
SPI2_MISO0/PD.2
SPI2_MOSI0/PD.3
SPI2_MISO1/PD.4
SPI2_MOSI1/PD.5
SC1_CD/CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
CMP1_N/PC.15
CMP1_P/PC.14
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PC.4/SPI0_MISO1
PC.5/SPI0_MOSI1
PD.15/UART2_TXD
PD.14/UART2_RXD
PD.7
NUC220VxxAN
LQFP 100-pin
PD.6
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
PB.0/UART0_RXD
USB_D+
nRESET
VSS
VDD
USB_D-
PS2_DAT/PF.2
PS2_CLK/PF.3
PVSS
USB_VDD33_CAP
USB_VBUS
PE.7
CLKO/TM0/STADC/PB.8
PE.8
Figure 3-5 NuMicro NUC220VxxAN LQFP 100-pin Diagram
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
3.2.2.2 NuMicro NUC220RxxAN LQFP 64-pin
ADC5/PA.5
ADC6/PA.6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PB.9/TM1
PB.10/TM2
VREF
PB.11/TM3/PWM4
AVDD
PE.5/TM1_EXT/PWM5
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
CMP1_N/PC.15
CMP1_P/PC.14
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
NUC220SxxAN
LQFP 64-pin
PB.0/UART0_RXD
VSS
USB_D+
VDD
USB_D-
PVSS
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
USB_VBUS
Figure 3-6 NuMicro NUC220SxxAN LQFP 64-pin Diagram
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NuMicro NUC200/220 Series Datasheet
3.2.2.3 NuMicro NUC220LxxAN LQFP 48-pin
ADC5/PA.5
ADC6/PA.6
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PC.0/SPI0_SS0/I2S_LRCK
PC.1/SPI0_CLK/I2S_BCLK
PC.2/SPI0_MISO0/I2S_DI
PC.3/SPI0_MOSI0/I2S_DO
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PB.1/UART0_TXD
VREF
AVDD
CMP0_N/PC.7
SC0_CD/CMP0_P/PC.6
TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
NUC220LxxAN
LQFP 48-pin
PB.0/UART0_RXD
USB_D+
nRESET
USB_D-
PVSS
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
USB_VBUS
Figure 3-7 NuMicro NUC220LxxAN LQFP 48-pin Diagram
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
3.3 Pin Description
3.3.1 NuMicro NUC200 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
I/O
I
1
2
3
PE.15
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
External interrupt0 input pin.
2nd SPI3 slave select pin.
PE.14
PE.13
PB.14
1
4
INT0
I/O
I/O
O
SPI3_SS1
PB.13
General purpose digital I/O pin.
Comparator1 output pin.
5
2
CMP1_O
VBAT
P
6
7
8
3
4
5
1
2
3
Power supply by batteries for RTC.
External 32.768 kHz (low speed) crystal output pin.
External 32.768 kHz (low speed) crystal input pin.
General purpose digital I/O pin.
I2C1 clock pin.
O
X32_OUT
X32_IN
PA.11
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
6
7
8
9
4
5
6
7
I2C1_SCL
PA.10
General purpose digital I/O pin.
I2C1 data input/output pin.
10
11
12
13
14
15
16
I2C1_SDA
PA.9
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
PA.8
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PD.8
General purpose digital I/O pin.
1st SPI3 slave select pin.
SPI3_SS0
PD.9
General purpose digital I/O pin.
SPI3 serial clock pin.
SPI3_CLK
PD.10
General purpose digital I/O pin.
1st SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI3 MOSI (Master Out, Slave In) pin.
SPI3_MISO0
PD.11
SPI3_MOSI0
Jan 31, 2019
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
I/O
I/O
I
PD.12
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Request to Send output pin for UART1.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
LDO output pin.
17
18
SPI3_MISO1
PD.13
SPI3_MOSI1
PB.4
19
20
21
22
10
11
12
13
8
9
UART1_RXD
PB.5
I/O
O
UART1_TXD
PB.6
I/O
O
UART1_nRTS
PB.7
I/O
I
UART1_nCTS
LDO_CAP
P
23
24
14
15
16
10
11
12
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
P
VDD
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
25
26
27
28
29
30
31
VSS
Ground pin for digital circuit.
PE.12
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external capture input pin.
Comparator0 output pin.
PE.11
PE.10
PE.9
PE.8
PE.7
PB.0
32
33
17
18
13
14
UART0_RXD
PB.1
I/O
O
UART0_TXD
PB.2
I/O
O
UART0_nRTS
TM2_EXT
CMP0_O
PB.3
34
19
20
15
16
I
O
I/O
35
General purpose digital I/O pin.
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I
UART0_nCTS
TM3_EXT
SC2_CD
PD.6
Clear to Send input pin for UART0.
Timer3 external capture input pin.
SmartCard2 card detect pin.
I
I
I/O
I/O
I/O
36
37
21
22
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PD.7
PD.14
38
23
24
I
UART2_RXD
PD.15
Data receiver input pin for UART2.
General purpose digital I/O pin.
Data transmitter output pin for UART2.
General purpose digital I/O pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I2S data output.
I/O
O
39
40
41
UART2_TXD
PC.5
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI0_MOSI1
PC.4
SPI0_MISO1
PC.3
42
43
44
25
26
27
28
17
18
19
20
SPI0_MOSI0
I2S_DO
PC.2
I/O
I/O
I
General purpose digital I/O pin.
1st SPI0 MISO (Master In, Slave Out) pin.
I2S data input.
SPI0_MISO0
I2S_DI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PC.1
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
I2S_BCLK
PC.0
I2S bit clock pin.
General purpose digital I/O pin.
1st SPI0 slave select pin.
45
46
47
48
SPI0_SS0
I2S_LRCK
PE.6
I2S left right channel clock.
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM5 output/Capture input.
Timer1 external capture input pin.
General purpose digital I/O pin.
PE.5
29
30
21
22
PWM5
TM1_EXT
PB.11
I/O
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TM3
Timer3 event counter input / toggle output.
PWM4 output/Capture input.
PWM4
PB.10
General purpose digital I/O pin.
Timer2 event counter input / toggle output.
2nd SPI0 slave select pin.
31
32
23
24
49
50
TM2
SPI0_SS1
PB.9
General purpose digital I/O pin.
Timer1 event counter input / toggle output.
2nd SPI1 slave select pin.
TM1
SPI1_SS1
PE.4
51
52
53
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM7 output/Capture input.
PE.3
PE.2
PE.1
54
55
56
57
58
59
PWM7
PE.0
General purpose digital I/O pin.
PWM6 output/Capture input.
PWM6
PC.13
General purpose digital I/O pin.
2nd SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
SPI1_MOSI1
PC.12
SPI1_MISO1
PC.11
33
34
SPI1_MOSI0
PC.10
SPI1_MISO0
PC.9
60
61
35
36
I/O
SPI1_CLK
SPI1 serial clock pin.
I/O
I/O
I/O
I/O
O
PC.8
General purpose digital I/O pin.
1st SPI1 slave select pin.
SPI1_SS0
PA.15
General purpose digital I/O pin.
PWM output/Capture input.
I2S master clock output pin.
62
37
25
PWM3
I2S_MCLK
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Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
O
I/O
I/O
O
SC2_PWR
PA.14
SmartCard2 power pin.
General purpose digital I/O pin.
PWM2 output/Capture input.
SmartCard2 reset pin.
63
64
65
38
39
40
26
27
28
PWM2
SC2_RST
PA.13
I/O
I/O
O
General purpose digital I/O pin.
PWM1 output/Capture input.
SmartCard2 clock pin.
PWM1
SC2_CLK
PA.12
I/O
I/O
O
General purpose digital I/O pin.
PWM0 output/Capture input.
SmartCard2 data pin.
PWM0
SC2_DAT
ICE_DAT
ICE_CLK
I/O
I
66
67
41
42
29
30
Serial wire debugger data pin.
Serial wire debugger clock pin.
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
P
68
VDD
P
AP
I/O
AI
O
69
70
VSS
Ground pin for digital circuit.
Ground pin for analog circuit.
General purpose digital I/O pin.
ADC0 analog input.
43
44
31
32
AVSS
PA.0
71
ADC0
SC0_PWR
PA.1
SmartCard0 power pin.
General purpose digital I/O pin.
ADC1 analog input.
I/O
AI
O
72
45
46
33
34
ADC1
SC0_RST
PA.2
SmartCard0 reset pin.
I/O
AI
O
General purpose digital I/O pin.
ADC2 analog input.
73
ADC2
SC0_CLK
PA.3
SmartCard0 clock pin.
I/O
AI
O
General purpose digital I/O pin.
ADC3 analog input.
74
75
47
48
35
36
ADC3
SC0_DAT
PA.4
SmartCard0 data pin.
I/O
AI
O
General purpose digital I/O pin.
ADC4 analog input.
ADC4
SC1_PWR
SmartCard1 power pin.
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
AI
PA.5
General purpose digital I/O pin.
ADC5 analog input.
49
37
76
77
ADC5
O
SC1_RST
PA.6
SmartCard1 reset pin.
I/O
AI
General purpose digital I/O pin.
ADC6 analog input.
50
38
ADC6
I/O
I/O
AI
SC1_CLK
PA.7
SmartCard1 clock pin.
General purpose digital I/O pin.
ADC7 analog input.
ADC7
78
O
SC1_DAT
SPI2_SS1
VREF
SmartCard1 data pin.
2nd SPI2 slave select pin.
I/O
AP
AP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AI
79
80
51
52
39
40
Voltage reference input for ADC.
Power supply for internal analog circuit.
General purpose digital I/O pin.
1st SPI2 slave select pin.
AVDD
PD.0
81
82
83
84
85
86
SPI2_SS0
PD.1
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
PD.2
General purpose digital I/O pin.
1st SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Comparator0 negative input pin.
SmartCard1 card detect pin.
General purpose digital I/O pin.
Comparator0 positive input pin.
SmartCard0 card detect pin.
General purpose digital I/O pin.
SPI2_MISO0
PD.3
SPI2_MOSI0
PD.4
SPI2_MISO1
PD.5
SPI2_MOSI1
PC.7
53
41
42
87
88
CMP0_N
SC1_CD
PC.6
I
I/O
AI
54
55
CMP0_P
SC0_CD
PC.15
I
I/O
89
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
AI
I/O
AI
I/O
I
CMP1_N
PC.14
Comparator1 negative input pin.
General purpose digital I/O pin.
90
91
56
57
CMP1_P
PB.15
Comparator1 positive input pin.
General purpose digital I/O pin.
43
44
INT1
External interrupt1 input pin.
I
TM0_EXT
PF.0
Timer0 external capture input pin.
General purpose digital I/O pin.
I/O
O
92
93
58
59
XT1_OUT
PF.1
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
I/O
I
45
46
XT1_IN
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up.
Set this pin low reset chip to initial state.
I
94
95
96
60
61
62
nRESET
VSS
P
P
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
VDD
I/O
I/O
I/O
I/O
P
PF.2
General purpose digital I/O pin.
PS2 data pin.
97
PS2_DAT
PF.3
General purpose digital I/O pin.
PS2 clock pin.
98
99
PS2_CLK
PVSS
63
64
47
48
PLL ground.
I/O
I
PB.8
General purpose digital I/O pin.
ADC external trigger input.
Timer0 event counter input / toggle output.
Frequency divider clock output pin.
STADC
TM0
100
I/O
O
CLKO
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power.
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NuMicro NUC200/220 Series Datasheet
3.3.2 NuMicro NUC220 Pin Description
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
I/O
I
1
2
3
PE.15
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
External interrupt0 input pin.
PE.14
PE.13
PB.14
1
4
INT0
I/O
I/O
O
SPI3_SS1
PB.13
2nd SPI3 slave select pin.
General purpose digital I/O pin.
Comparator1 output pin.
5
2
CMP1_O
VBAT
P
6
7
8
3
4
5
1
2
3
Power supply by batteries for RTC.
External 32.768 kHz (low speed) crystal output pin.
External 32.768 kHz (low speed) crystal input pin.
General purpose digital I/O pin.
I2C1 clock pin.
O
X32_OUT
X32_IN
PA.11
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
6
7
8
9
4
5
6
7
I2C1_SCL
PA.10
General purpose digital I/O pin.
I2C1 data input/output pin.
10
11
12
13
14
15
16
17
I2C1_SDA
PA.9
General purpose digital I/O pin.
I2C0 clock pin.
I2C0_SCL
PA.8
General purpose digital I/O pin.
I2C0 data input/output pin.
I2C0_SDA
PD.8
General purpose digital I/O pin.
1st SPI3 slave select pin.
SPI3_SS0
PD.9
General purpose digital I/O pin.
SPI3 serial clock pin.
SPI3_CLK
PD.10
General purpose digital I/O pin.
1st SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI3 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
SPI3_MISO0
PD.11
SPI3_MOSI0
PD.12
SPI3_MISO1
PD.13
18
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I
SPI3_MOSI1
PB.4
2nd SPI3 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Data receiver input pin for UART1.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
Request to Send output pin for UART1.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
LDO output pin.
19
20
21
22
10
11
12
13
8
9
UART1_RXD
PB.5
I/O
O
UART1_TXD
PB.6
I/O
O
UART1_nRTS
PB.7
I/O
I
UART1_nCTS
LDO_CAP
P
23
24
14
15
16
10
11
12
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
P
VDD
P
25
26
27
28
VSS
Ground pin for digital circuit.
I/O
PE.8
General purpose digital I/O pin.
General purpose digital I/O pin.
Power supply from USB host or HUB.
I/O
PE.7
USB
17
18
13
14
USB_VBUS
USB_VDD33_
CAP
USB
29
Internal power regulator output 3.3V decoupling pin.
USB
30
31
19
20
15
16
USB_D-
USB differential signal D-.
USB
USB_D+
PB.0
USB differential signal D+.
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
General purpose digital I/O pin.
Data transmitter output pin for UART0.
General purpose digital I/O pin.
Request to Send output pin for UART0.
Timer2 external capture input pin.
Comparator0 output pin.
32
33
21
22
17
18
UART0_RXD
PB.1
I/O
O
I/O
O
I
UART0_TXD
PB.2
UART0_nRTS
TM2_EXT
CMP0_O
PB.3
34
23
24
19
20
O
I/O
I
General purpose digital I/O pin.
Clear to Send input pin for UART0.
Timer3 external capture input pin.
SmartCard2 card detect pin.
UART0_nCTS
TM3_EXT
SC2_CD
35
I
I
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
36
37
PD.6
PD.7
PD.14
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
38
I
UART2_RXD
PD.15
Data receiver input pin for UART2.
General purpose digital I/O pin.
Data transmitter output pin for UART2.
General purpose digital I/O pin.
2nd SPI0 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI0 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI0 MOSI (Master Out, Slave In) pin.
I2S data output.
I/O
O
39
40
41
UART2_TXD
PC.5
I/O
I/O
I/O
I/O
I/O
I/O
O
SPI0_MOSI1
PC.4
SPI0_MISO1
PC.3
42
43
44
25
26
27
28
21
22
23
24
SPI0_MOSI0
I2S_DO
I/O
I/O
I
PC.2
General purpose digital I/O pin.
1st SPI0 MISO (Master In, Slave Out) pin.
I2S data input.
SPI0_MISO0
I2S_DI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PC.1
General purpose digital I/O pin.
SPI0 serial clock pin.
SPI0_CLK
I2S_BCLK
PC.0
I2S bit clock pin.
General purpose digital I/O pin.
1st SPI0 slave select pin.
45
46
SPI0_SS0
I2S_LRCK
PE.6
I2S left right channel clock.
General purpose digital I/O pin.
I/O
PE.5
General purpose digital I/O pin.
47
48
29
I/O
I
PWM5
PWM5 output/Capture input.
Timer1 external capture input pin.
General purpose digital I/O pin.
TM1_EXT
PB.11
I/O
I/O
30
31
TM3
Timer3 event counter input / toggle output.
I/O
I/O
PWM4
PB.10
PWM4 output/Capture input.
General purpose digital I/O pin.
49
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
TM2
Timer2 event counter input / toggle output.
2nd SPI0 slave select pin.
SPI0_SS1
PB.9
General purpose digital I/O pin.
Timer1 event counter input / toggle output.
2nd SPI1 slave select pin.
32
50
TM1
SPI1_SS1
PE.4
51
52
53
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
General purpose digital I/O pin.
PWM7 output/Capture input.
General purpose digital I/O pin.
PWM6 output/Capture input.
General purpose digital I/O pin.
2nd SPI1MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI1 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
1st SPI1 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
SPI1 serial clock pin.
PE.3
PE.2
PE.1
54
55
56
57
PWM7
PE.0
PWM6
PC.13
SPI1_MOSI1
PC.12
SPI1_MISO1
PC.11
58
59
60
61
33
34
35
36
SPI1_MOSI0
PC.10
SPI1_MISO0
PC.9
SPI1_CLK
PC.8
General purpose digital I/O pin.
1st SPI1 slave select pin.
SPI1_SS0
PA.15
General purpose digital I/O pin.
PWM3 output/Capture input.
I2S master clock output pin.
PWM3
62
37
38
25
26
I2S_MCLK
SC2_PWR
PA.14
O
SmartCard2 power pin.
I/O
I/O
O
General purpose digital I/O pin.
PWM2 output/Capture input.
SmartCard2 reset pin.
63
PWM2
SC2_RST
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I/O
I/O
O
PA.13
General purpose digital I/O pin.
PWM1 output/Capture input.
SmartCard2 clock pin.
64
65
39
40
27
28
PWM1
SC2_CLK
PA.12
I/O
I/O
O
General purpose digital I/O pin.
PWM0 output/Capture input.
SmartCard2 data pin.
PWM0
SC2_DAT
ICE_DAT
ICE_CLK
I/O
I
66
67
41
42
29
30
Serial wire debugger data pin.
Serial wire debugger clock pin.
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
P
68
VDD
P
AP
I/O
AI
O
69
70
VSS
Ground pin for digital circuit.
Ground pin for analog circuit.
General purpose digital I/O pin.
ADC0 analog input.
43
44
31
32
AVSS
PA.0
71
72
73
74
75
ADC0
SC0_PWR
PA.1
SmartCard0 power pin.
General purpose digital I/O pin.
ADC1 analog input.
I/O
AI
O
45
46
33
34
ADC1
SC0_RST
PA.2
SmartCard0 reset pin.
I/O
AI
O
General purpose digital I/O pin.
ADC2 analog input.
ADC2
SC0_CLK
PA.3
SmartCard0 clock pin.
I/O
AI
O
General purpose digital I/O pin.
ADC3 analog input.
47
48
35
36
ADC3
SC0_DAT
PA.4
SmartCard0 data pin.
I/O
AI
O
General purpose digital I/O pin.
ADC4 analog input.
ADC4
SC1_PWR
PA.5
SmartCard1 power pin.
General purpose digital I/O pin.
ADC5 analog input.
I/O
AI
O
49
50
37
38
76
77
ADC5
SC1_RST
PA.6
SmartCard1 reset pin.
I/O
General purpose digital I/O pin.
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
AI
I/O
I/O
AI
ADC6
ADC6 analog input.
SC1_CLK
PA.7
SmartCard1 clock pin.
General purpose digital I/O pin.
ADC7 analog input.
ADC7
78
O
SC1_CLK
SPI2_SS1
VREF
SmartCard1 clock pin.
2nd SPI2 slave select pin.
I/O
AP
AP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AI
79
80
51
52
39
40
Voltage reference input for ADC.
Power supply for internal analog circuit.
General purpose digital I/O pin.
1st SPI2 slave select pin.
AVDD
PD.0
81
82
83
84
85
86
SPI2_SS0
PD.1
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
PD.2
General purpose digital I/O pin.
1st SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
1st SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
2nd SPI2 MISO (Master In, Slave Out) pin.
General purpose digital I/O pin.
2nd SPI2 MOSI (Master Out, Slave In) pin.
General purpose digital I/O pin.
Comparator0 negative input pin.
SmartCard1 card detect pin.
General purpose digital I/O pin.
Comparator0 positive input pin.
SmartCard0 card detect pin.
General purpose digital I/O pin.
Comparator1 negative input pin.
General purpose digital I/O pin.
Comparator1 positive input pin.
General purpose digital I/O pin.
SPI2_MISO0
PD.3
SPI2_MOSI0
PD.4
SPI2_MISO1
PD.5
SPI2_MOSI1
PC.7
53
41
42
87
CMP0_N
SC1_CD
PC.6
I
I/O
AI
88
89
54
55
CMP0_P
SC0_CD
PC.15
I
I/O
AI
CMP1_N
PC.14
I/O
AI
90
91
56
57
CMP1_P
PB.15
I/O
43
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NuMicro NUC200/220 Series Datasheet
Pin No.
Pin
Type
Pin Name
Description
LQFP LQFP LQFP
100-pin 64-pin 48-pin
I
I
INT1
External interrupt1 input pin.
TM0_EXT
PF.0
Timer 0 external capture input pin.
General purpose digital I/O pin.
I/O
O
I/O
I
92
93
58
59
44
XT1_OUT
PF.1
External 4~24 MHz (high speed) crystal output pin.
General purpose digital I/O pin.
45
46
XT1_IN
External 4~24 MHz (high speed) crystal input pin.
External reset input: active LOW, with an internal pull-up.
Set this pin low reset chip to initial state.
I
94
95
96
60
61
62
nRESET
VSS
P
P
Ground pin for digital circuit.
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
VDD
I/O
I/O
I/O
I/O
P
PF.2
General purpose digital I/O pin.
PS2 data pin.
97
PS2_DAT
PF.3
General purpose digital I/O pin.
PS2 clock pin.
98
99
PS2_CLK
PVSS
63
64
47
48
PLL ground.
I/O
I
PB.8
General purpose digital I/O pin.
ADC external trigger input.
Timer0 event counter input / toggle output.
Frequency divider clock output pin.
STADC
TM0
100
I/O
O
CLKO
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power.
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NuMicro NUC200/220 Series Datasheet
4
BLOCK DIAGRAM
4.1 NuMicro NUC200 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
LDROM
4 KB
APROM
RTC
128/64/32 KB
ARM
Cortex-M0
50MHz
PDMA
Analog
Comparator x2
Watchdog Timer
SRAM
16/8 KB
DataFlash
4 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
SPI x 4
I/O Ports
General Purpose
I/O
LDO
External
Interrupt
Power On Reset
LVR
High Speed
Oscillator
22.1184 MHz
High Speed
Crystal Osc.
4 ~ 24 MHz
I2C x 2
I2S
Reset Pin
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
PS/2
SC x3
Brownout
Detection
Figure 4-1 NuMicro NUC200 Block Diagram
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4.2 NuMicro NUC220 Block Diagram
Memory
Timer/PWM
Analog Interface
12-bit ADC x 8
32-bit Timer x 4
APROM
128/64/32 KB
LDROM
4 KB
RTC
ARM
Cortex-M0
50MHz
USB PHY
PDMA
Watchdog Timer
Analog
Comparator x2
DataFlash
4 KB
SRAM
16/8 KB
PWM/Capture
Timer x 8
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
PLL
Connectivity
UART x 3
I/O Ports
General Purpose
I/O
LDO
Power On Reset
LVR
SPI x 4
I2C x 2
I2S
External
Interrupt
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
22.1184 MHz
Reset Pin
PS/2
Low Speed
Oscillator
10 kHz
Low Speed
Crystal Osc.
32.768 KHz
SC x3
USB
Brownout
Detection
Figure 4-2 NuMicro NUC220 Block Diagram
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5
FUNCTIONAL DESCRIPTION
5.1 ARM® Cortex™-M0 Core
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 5-1 shows the functional controller of processor.
CortexTM-M0 Components
CortexTM-M0 Processor
Debug
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Breakpoint
and
Watchpoint
Unit
CortexTM-M0
Processor
Core
Debug
Access
Port
Wake-up
Interrupt
Controller
(WIC)
Debugger
Interface
Bus Matrix
(DAP)
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 5-1 Functional Controller Diagram
The implemented device provides the following components and features:
A low gate count processor:
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
NVIC:
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32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port).
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5.2 System Manager
5.2.1 Overview
System management includes the following sections:
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
5.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset
Low Voltage Reset
Brown-out Detector Reset
CPU Reset
System Reset
System Reset and Power-on Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-on Reset is external crystal circuit and ISPCON.BS
bit. System Reset does not reset external crystal circuit and ISPCON.BS bit, but Power-on Reset
does.
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5.2.3 System Power Distribution
In this chip, the power distribution is divided into four segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from USB_VBUS offers the power for operating the USB
transceiver.
Battery power from VBAT supplies the RTC and external 32.768 kHz crystal.
The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external
capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be
the same voltage level of the digital power (VDD). Figure 5-2 shows the power distribution of
NuMicro NUC200; Figure 5-3 shows the power distribution of NuMicro NUC220.
NUC200 Power Distribution
Brown-
out
Detector
Low
Voltage
Reset
AVDD
AVSS
12-bit
SAR-ADC
Analog
Comparator
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
External
32.768 kHz
Crystal
ULDO
RTC
PLL
LDO
IO cell
GPIO
Figure 5-2 NuMicro NUC200 Power Distribution Diagram
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AVDD
AVSS
USB_D+
USB 1.1
12-bit
SAR-ADC
Tranceiver
USB_D-
NUC220
Power
Distribution
USB_VDD33_CAP
1uF
Analog Comparator
3.3V
Low
Voltage
Reset
Brown-
out
Detector
5V to 3.3V LDO
USB_VBUS
Internal
22.1184 MHz & 10 kHz
Oscillator
Temperature
Seneor
FLASH
Digital Logic
LDO_CAP
1uF
1.8V
1.8V
POR18
POR50
External
32.768 kHz
Crystal
ULDO
RTC
PLL
LDO
IO cell
GPIO
Figure 5-3 NuMicro NUC220 Power Distribution Diagram
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5.2.4 System Memory Map
The NuMicro NUC200 Series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register
definition, memory space, and programming detailed will be described in the following sections for
each on-chip peripheral. The NuMicro NUC200 Series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF FLASH_BA
0x2000_0000 – 0x2000_3FFF SRAM_BA
FLASH Memory Space (128 KB)
SRAM Memory Space (16 KB)
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF GCR_BA
0x5000_0200 – 0x5000_02FF CLK_BA
0x5000_0300 – 0x5000_03FF INT_BA
0x5000_4000 – 0x5000_7FFF GPIO_BA
0x5000_8000 – 0x5000_BFFF PDMA_BA
0x5000_C000 – 0x5000_FFFF FMC_BA
System Global Control Registers
Clock Control Registers
Interrupt Multiplexer Control Registers
GPIO Control Registers
Peripheral DMA Control Registers
Flash Memory Control Registers
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
Watchdog Timer Control Registers
0x4000_4000 – 0x4000_7FFF WDT_BA
0x4000_8000 – 0x4000_BFFF RTC_BA
0x4001_0000 – 0x4001_3FFF TMR01_BA
0x4002_0000 – 0x4002_3FFF I2C0_BA
0x4003_0000 – 0x4003_3FFF SPI0_BA
0x4003_4000 – 0x4003_7FFF SPI1_BA
0x4004_0000 – 0x4004_3FFF PWMA_BA
0x4005_0000 – 0x4005_3FFF UART0_BA
0x4006_0000 – 0x4006_3FFF USBD_BA
0x400D_0000 – 0x400D_3FFF ACMP_BA
0x400E_0000 – 0x400E_FFFF ADC_BA
Real Time Clock (RTC) Control Register
Timer0/Timer1 Control Registers
I2C0 Interface Control Registers
SPI0 with master/slave function Control Registers
SPI1 with master/slave function Control Registers
PWM0/1/2/3 Control Registers
UART0 Control Registers
USB 2.0 FS device Controller Registers
Analog Comparator Control Registers
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
0x4010_0000 – 0x4010_3FFF PS2_BA PS/2 Interface Control Registers
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0x4011_0000 – 0x4011_3FFF TMR23_BA
0x4012_0000 – 0x4012_3FFF I2C1_BA
0x4013_0000 – 0x4013_3FFF SPI2_BA
0x4013_4000 – 0x4013_7FFF SPI3_BA
0x4014_0000 – 0x4014_3FFF PWMB_BA
0x4015_0000 – 0x4015_3FFF UART1_BA
0x4015_4000 – 0x4015_7FFF UART2_BA
0x4019_0000 – 0x4019_3FFF SC0_BA
0x4019_4000 – 0x4019_7FFF SC1_BA
0x4019_8000 – 0x4019_BFFF SC2_BA
0x401A_0000 – 0x401A_3FFF I2S_BA
Timer2/Timer3 Control Registers
I2C1 Interface Control Registers
SPI2 with master/slave function Control Registers
SPI3 with master/slave function Control Registers
PWM4/5/6/7 Control Registers
UART1 Control Registers
UART2 Control Registers
SC0 Control Registers
SC1 Control Registers
SC2 Control Registers
I2S Interface Control Registers
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF SYST_BA
0xE000_E100 – 0xE000_ECFF NVIC_BA
0xE000_ED00 – 0xE000_ED8F SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 5-1 Address Space Assignments for On-Chip Controllers
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5.2.5 System Timer (SysTick)
The Cortex™-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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5.2.6 Nested Vectored Interrupt Controller (NVIC)
The Cortex™-M0 provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor kernel and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
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5.2.6.1 Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro NUC200 Series. Software
can set four levels of priority on some of these exceptions as well as on all interrupts. The highest
user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default
priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Reset
Vector Number
Priority
-3
1
2
NMI
-2
Hard Fault
Reserved
3
-1
4 ~ 10
11
Reserved
Configurable
Reserved
Configurable
Configurable
Configurable
SVCall
Reserved
12 ~ 13
14
PendSV
SysTick
15
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Table 5-2 Exception Model
Interrupt
Number
Vector
Number
Interrupt
Name
Source IP Interrupt Description
(Bit in Interrupt
Registers)
-
0 ~ 15
16
-
-
System exceptions
BOD_INT
WDT_INT
EINT0
0
1
2
3
4
Brown-out Brown-out low voltage detected interrupt
17
WDT
GPIO
GPIO
GPIO
Watchdog Timer interrupt
18
External signal interrupt from PB.14 pin
External signal interrupt from PB.15 pin
External signal interrupt from PA[15:0]/PB[13:0]
EINT1
19
GPAB_INT
20
External interrupt from
PC[15:0]/PD[15:0]/PE[15:0]/ PF[3:0]
GPCDEF_INT
21
5
GPIO
PWMA_INT
PWMB_INT
TMR0_INT
TMR1_INT
TMR2_INT
TMR3_INT
22
23
24
25
26
27
6
7
PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt
PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt
8
TMR0
TMR1
TMR2
TMR3
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
9
10
11
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UART02_INT
UART1_INT
SPI0_INT
SPI1_INT
SPI2_INT
SPI3_INT
I2C0_INT
I2C1_INT
Reserved
Reserved
SC012_INT
USB_INT
PS2_INT
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
UART0/2 UART0 and UART2 interrupt
UART1 UART1 interrupt
SPI0
SPI1
SPI2
SPI3
I2C0
I2C1
-
SPI0 interrupt
SPI1 interrupt
SPI2 interrupt
SPI3 interrupt
I2C0 interrupt
I2C1 interrupt
-
-
-
SC0/1/2 SC0, SC1 and SC2 interrupt
USBD
PS/2
USB 2.0 FS Device interrupt
PS/2 interrupt
ACMP_INT
PDMA_INT
I2S_INT
ACMP
PDMA
I2S
Analog Comparator-0 or Comaprator-1 interrupt
PDMA interrupt
I2S interrupt
Clock controller interrupt for chip wake-up from
power-down state
PWRWU_INT
44
28
CLKC
ADC_INT
IRCT_INT
RTC_INT
45
46
47
29
30
31
ADC
IRC
ADC interrupt
IRC TRIM interrupt
Real time clock interrupt
RTC
Table 5-3 System Interrupt Map
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5.2.6.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset Description
0
SP_main – The Main stack pointer
Vector Number
Exception Entry Pointer using that Vector Number
Table 5-4 Vector Table Format
5.2.6.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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5.2.6.4 Interrupt Source Register Map
Besides the interrupt control registers associated with the NVIC, the NuMicro NUC200 Series
also implements some specific control registers to facilitate the interrupt functions, including
“interrupt source identification”, ”NMI source selection” and “interrupt test mode”, which are
described below.
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W Description
Reset Value
INT Base Address:
INT_BA = 0x5000_0300
IRQ0_SRC
IRQ1_SRC
IRQ2_SRC
IRQ3_SRC
IRQ4_SRC
IRQ5_SRC
IRQ6_SRC
IRQ7_SRC
IRQ8_SRC
IRQ9_SRC
INT_BA+0x00
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
IRQ0 (BOD) interrupt source identity
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
INT_BA+0x04
INT_BA+0x08
INT_BA+0x0C
INT_BA+0x10
INT_BA+0x14
INT_BA+0x18
INT_BA+0x1C
INT_BA+0x20
INT_BA+0x24
IRQ1 (WDT) interrupt source identity
IRQ2 (EINT0) interrupt source identity
IRQ3 (EINT1) interrupt source identity
IRQ4 (GPA/GPB) interrupt source identity
IRQ5 (GPC/GPD/GPE/GPF) interrupt source identity
IRQ6 (PWMA) interrupt source identity
IRQ7 (PWMB) interrupt source identity
IRQ8 (TMR0) interrupt source identity
IRQ9 (TMR1) interrupt source identity
IRQ10 (TMR2) interrupt source identity
IRQ11 (TMR3) interrupt source identity
IRQ12 (UART0/UART2) interrupt source identity
IRQ13 (UART1) interrupt source identity
IRQ14 (SPI0) interrupt source identity
IRQ15 (SPI1) interrupt source identity
IRQ16 (SPI2) interrupt source identity
IRQ17 (SPI3) interrupt source identity
IRQ18 (I2C0) interrupt source identity
IRQ19 (I2C1) interrupt source identity
Reserved
IRQ10_SRC INT_BA+0x28
IRQ11_SRC INT_BA+0x2C
IRQ12_SRC INT_BA+0x30
IRQ13_SRC INT_BA+0x34
IRQ14_SRC INT_BA+0x38
IRQ15_SRC INT_BA+0x3C
IRQ16_SRC INT_BA+0x40
IRQ17_SRC INT_BA+0x44
IRQ18_SRC INT_BA+0x48
IRQ19_SRC INT_BA+0x4C
IRQ20_SRC INT_BA+0x50
IRQ21_SRC INT_BA+0x54
IRQ22_SRC INT_BA+0x58
Reserved
IRQ22 (SC0/SC1/SC2) interrupt source identity
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IRQ23_SRC INT_BA+0x5C
IRQ24_SRC INT_BA+0x60
IRQ25_SRC INT_BA+0x64
IRQ26_SRC INT_BA+0x68
IRQ27_SRC INT_BA+0x6C
IRQ28_SRC INT_BA+0x70
IRQ29_SRC INT_BA+0x74
IRQ30_SRC INT_BA+0x78
IRQ31_SRC INT_BA+0x7C
R
R
R
R
R
R
R
R
R
IRQ23 (USB) interrupt source identity
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0x0000_0000
IRQ24 (PS/2) interrupt source identity
IRQ25 (ACMP) interrupt source identity
IRQ26 (PDMA) interrupt source identity
IRQ27 (I2S) interrupt source identity
IRQ28 (PWRWU) interrupt source identity
IRQ29 (ADC) interrupt source identity
IRQ30 (IRCT) interrupt source identity
IRQ31 (RTC) interrupt source identity
NMI_SEL
MCU_IRQ
INT_BA+0x80
INT_BA+0x84
R/W NMI source interrupt select control register
R/W MCU interrupt request source register
0x0000_0000
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5.2.7 System Control (SCS)
The Cortex™-M0 status and operating mode control are managed by System Control Registers.
Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be
controlled through these system control registers
For more detailed information, please refer to the “ARM® Cortex™-M0 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
5.3 Clock Controller
5.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex™-M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit
Power-down mode. In Power-down mode, the clock controller turns off the external 4~24 MHz
high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the overall system
power consumption.
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22.1184
MHz
22.1184 MHz
10 kHz
111
011
010
001
000
CPUCLK
HCLK
CPU
4~24
MHz
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PDMA
32.768
kHz
ACMP
PCLK
I2C 0~1
22.1184 MHz
10 kHz
111
101
011
010
001
000
10 kHz
CLKSEL0[2:0]
TMR 3
TMR 2
TMR 1
TMR 0
External trigger
HCLK
22.1184 MHz
4~24 MHz
1
PLLFOUT
32.768 kHz
4~24 MHz
0
PLLCON[19]
22.1184 MHz
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
FMC
CPUCLK
22.1184 MHz
HCLK
1
0
1/2
1/2
1/2
111
011
010
001
000
SysTick
SYST_CSR[2]
4~24 MHz
32.768 kHz
4~24 MHz
10 kHz
111
22.1184 MHz
011
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
HCLK
010
32.768 kHz
001
CLKSEL0[5:3]
4~24 MHz
000
CLKSEL2[17:16]
10 kHz
22.1184 MHz
11
10
01
00
11
10
HCLK
WWDT
CLKSEL2[11:4]
CLKSEL1[31:28]
PLLFOUT
4~24 MHz
10 kHz
11
10
01
HCLK
1/2048
32.768 kHz
WDT
PS2
I2S
CLKSEL2[1:0]
22.1184 MHz
CLKSEL1[1:0]
22.1184 MHz
PLLFOUT
11
01
00
CPUCLK
1
0
4~24 MHz
SPI0-3
CLKSEL1[25:24]
SYST_CSR[2]
1/(UART_N+1)
1/(ADC_N+1)
UART 0-2
22.1184 MHz
HCLK
11
10
01
00
ADC
BOD
FDIV
PLLFOUT
4~24 MHz
22.1184 MHz
HCLK
10 kHz
11
10
01
00
32.768 kHz
4~24 MHz
CLKSEL1[3:2]
32.768 kHz
22.1184 MHz
HCLK
RTC
11
10
01
00
CLKSEL2[3:2]
1/(SC2_N+1)
SC 2
SC 1
SC 0
PLLFOUT
4~24 MHz
1/(SC1_N+1)
1/(SC0_N+1)
CLKSEL3[5:4]
CLKSEL3[3:2]
CLKSEL3[1:0]
PLLFOUT
1/(USB_N+1)
USB
Figure 5-4 Clock Generator Global View Diagram
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5.3.2 Clock Generator
The clock generator consists of 5 clock sources as listed below:
One external 32.768 kHz low speed crystal
One external 4~24 MHz high speed crystal
One programmable PLL FOUT (PLL source consists of external 4~24 MHz high
speed crystal and internal 22.1184 MHz high speed oscillator)
One internal 22.1184 MHz high speed oscillator
One internal 10 kHz low speed oscillator
XTL32K_EN (PWRCON[1])
X32_IN
External
32.768 kHz
32.768 kHz
Crystal
X32_OUT
XTL12M_EN (PWRCON[0])
4~24 MHz
XT1_IN
External
PLL_SRC (PLLCON[19])
4~24 MHz
Crystal
XT1_OUT
0
1
PLL FOUT
PLL
OSC22M_EN (PWRCON[2])
Internal
22.1184 MHz
Oscillator
22.1184 MHz
10 kHz
OSC10K_EN(PWRCON[3])
Internal
10 kHz
Oscillator
Figure 5-5 Clock Generator Block Diagram
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5.3.3 System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 5-6.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
111
10 kHz
011
010
001
000
CPUCLK
HCLK
CPU
AHB
APB
PLLFOUT
32.768 kHz
4~24 MHz
1/(HCLK_N+1)
PCLK
HCLK_N (CLKDIV[3:0])
CPU in Power Down Mode
Figure 5-6 System Clock Block Diagram
The clock source of SysTick in Cortex™-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 5-7.
STCLK_S (CLKSEL0[5:3])
22.1184 MHz
111
011
010
001
000
1/2
1/2
1/2
HCLK
STCLK
4~24 MHz
32.768 kHz
4~24 MHz
Figure 5-7 SysTick Clock Control Block Diagram
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5.3.4 Peripherals Clock
The peripherals clock can be selected as different clock source depends on the clock source
select control registers (CLKSEL1, CLKSEL2 and CLKSEL3).
5.3.5 Power-down Mode Clock
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
Clock Generator
Internal 10 kHz low speed oscillator clock
External 32.768 kHz low speed crystal clock
Peripherals Clock (when IP adopt external 32.768 kHz low speed crystal oscillator or
10 kHz low speed oscillator as clock source)
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5.3.6 Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
10 kHz
11
FRQDIV_CLK
HCLK
10
01
00
32.768 kHz
4~24 MHz
Figure 5-8 Clock Source of Frequency Divider
DIVIDER_EN
(FRQDIV[4])
Enable
16 chained
divide-by-2 counter
divide-by-2 counter
FRQDIV_CLK
1/22 1/23
1/215 1/216
…...
1/2
0000
0001
CLKO
16 to 1
MUX
:
:
1110
1111
FSEL
(FRQDIV[3:0])
Figure 5-9 Frequency Divider Block Diagram
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5.4 USB Device Controller (USB)
5.4.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device, which is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, e.g. IN ACK, OUT ACK, and BUS events, e.g. suspend
and resume. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1.
5.4.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature list of this USB.
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKE-UP, FLDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
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5.5 General Purpose I/O (GPIO)
5.5.1 Overview
The NuMicro NUC200 series has up to 80 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 80 pins are arranged in 6 ports named
as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the
maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 80 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, open-
drain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V.
5.5.2 Features
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
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5.6 I2C Serial Interface Controller (I2C)
5.6.1 Overview
I2C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines
are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock
pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each
transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may
be changed only during the low period of SCL and must be held stable during the high period of
SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 5-10 for more detailed I2C BUS Timing.
Repeated
START
STOP START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
Figure 5-10 I2C Bus Timing
The device’s on-chip I2C logic provides a serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1
in I2CON should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL.
Pull-up resistor is needed for I2C operation as the SDA and SCL are open drain pins. When I/O
pins are used as I2C ports, user must set the pins function to I2C in advance.
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5.6.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus include:
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
A built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
External pull-up resistors needed for high output
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
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5.7 PWM Generator and Capture Timer (PWM)
5.7.1 Overview
The NuMicro NUC200 series has 2 sets of PWM group supporting a total of 4 sets of PWM
generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6,
PWM7) with 4 programmable Dead-zone generators.
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for the
architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as one-
shot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
example:
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HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will be 1/900ns ≈ 1000 kHz
5.7.2 Features
5.7.2.1 PWM function:
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4
complementary PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting
one 8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator
and two PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Edge-aligned type or Center-aligned type option
5.7.2.2 Capture Function:
Timing control logic shared with PWM generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)
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5.8 Real Time Clock (RTC)
5.8.1 Overview
The Real Time Clock (RTC) controller provides user with the real time and calendar message.
The clock source of RTC controller is from an external 32.768 kHz low speed crystal which
connected at pins X32_IN and X32_OUT (refer to pin Description) or from an external 32.768 kHz
low speed oscillator output fed at pin X32_IN. The RTC controller provides the real time message
(hour, minute, second) in TLR (RTC Time Loading Register) as well as calendar message (year,
month, day) in CLR (RTC Calendar Loading Register). It also offers RTC alarm function that user
can preset the alarm time in TAR (RTC Time Alarm Register) and alarm calendar in CAR (RTC
Calendar Alarm Register). The data format of RTC time and calendar message are all expressed
in BCD format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic
RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1
second which are selected by TTR (TTR[2:0] Time Tick Register). When real time and calendar
message in TLR and CLR are equal to alarm time and calendar settings in TAR and CAR, the AIF
(RIIR [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC alarm interrupt signal is generated if
the AIER (RIER [0] Alarm Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or
Power-down mode if the correlate interrupt enable bit (AIER or TIER) is set to 1 before chip
enters Idle or Power-down mode.
5.8.2 Features
Supports real time counter in TLR (hour, minute, second) and calendar counter in CLR (year,
month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in TAR
and CAR
Selectable 12-hour or 24-hour time scale in TSSR register
Supports Leap Year indication in LIR register
Supports Day of the Week counter in DWR register
Frequency of RTC clock source compensate by FCR register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
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5.9 Serial Peripheral Interface (SPI)
5.9.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro NUC200 series contains up to four sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable serial clock function for special applications and 2-bit
Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports
the PDMA function to access the data buffer and also supports Dual I/O Transfer mode.
5.9.2 Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Two slave select lines in Master mode
Supports the byte reorder function
Supports Byte or Word Suspend mode
Variable output serial clock frequency in Master mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
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5.10 Timer Controller (TMR)
5.10.1 Overview
The timer controller includes four 32-bit timers, TIMER0~TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, event counting, interval measurement, clock generation, and delay timing. The
timer can generate an interrupt signal upon time-out, or provide the current value during
operation.
5.10.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)
Maximum counting cycle time = (1 / T MHz) * (28) * (224), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external pin
Supports external pin capture function for interval measurement
Supports external pin capture function for reset timer counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
(TIF set to 1)
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5.11 Watchdog Timer (WDT)
5.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
5.11.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (24 ~ 218) and the time-out interval is 104 ms ~ 26.3168 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period, it includes (1024+2)、(128+2) 、
(16+2) or (1+2) WDT_CLK reset delay period.
Supports force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(Config0[31] watchdog enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function when WDT clock source is selected to
10 kHz low speed oscillator.
5.12 Window Watchdog Timer (WWDT)
5.12.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
5.12.2 Features
6-bit down counter (WWDTVAL[5:0]) and 6-bit compare value (WWDTCR[21:16] – WINCMP
value) to make the window period flexible
Selectable maximum 11-bit WWDT clock prescale (WWDTCR[11:8] – PERIODSEL value) to
make WWDT time-out interval variable
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5.13 UART Interface Controller (UART)
The NuMicro NUC200 series provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART. Besides, only UART0 and UART1 support the flow control function.
5.13.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR, LIN master/slave mode
and RS-485 mode functions. Each UART channel supports seven types of interrupts including:
Transmitter FIFO empty interrupt (INT_THRE);
Receiver threshold level reached interrupt (INT_RDA);
Line status interrupt (parity error or frame error or break interrupt) (INT_RLS);
Receiver buffer time-out interrupt (INT_TOUT);
MODEM/Wake-up status interrupt (INT_MODEM);
Buffer error interrupt (INT_BUF_ERR);
LIN interrupt (INT_LIN).
Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt
number 13 (vector number is 29) only supports UART1 interrupt. Refer to the Nested Vectored
Interrupt Controller chapter for System Interrupt Map.
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU. The UART1~2 are
equipped with 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The
CPU can read the status of the UART at any time during the operation. The reported status
information includes the type and condition of the transfer operations being performed by the
UART, as well as 4 error conditions (parity error, frame error, break interrupt and buffer error)
probably occur while receiving data. The UART includes a programmable baud rate generator
that is capable of dividing clock input by divisors to produce the serial clock that transmitter and
receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and
BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 5-5 lists the equations in the
various conditions and Table 5-6 lists the UART baud rate setting table.
Mode
DIV_X_EN DIV_X_ONE
Divider X
Don’t care
B
BRD Baud Rate Equation
0
1
2
0
1
1
0
0
1
A
A
A
UART_CLK / [16 * (A+2)]
UART_CLK / [(B+1) * (A+2)] , B must >= 8
UART_CLK / (A+2), A must >=3
Don’t care
Table 5-5 UART Baud Rate Equation
System clock = internal 22.1184 MHz high speed oscillator
Mode 0
Mode 1
Mode 2
Baud Rate
Parameter
Register
Parameter
Register
Parameter
A=22
Register
921600
x
x
A=0,B=11
0x3000_0016
0x2B00_0000
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A=1,B=15
A=2,B=11
0x2F00_0001
0x2B00_0002
460800
230400
115200
57600
A=1
A=4
0x0000_0001
0x0000_0004
0x0000_000A
0x0000_0016
A=46
A=94
0x3000_002E
0x3000_005E
0x3000_00BE
0x3000_017E
A=4,B=15
A=6,B=11
0x2F00_0004
0x2B00_0006
A=10,B=15
A=14,B=11
0x2F00_000A
0x2B00_000E
A=10
A=22
A=190
A=382
A=22,B=15
A=30,B=11
0x2F00_0016
0x2B00_001E
A=62,B=8
0x0000_0022 A=46,B=11
A=34,B=15
0x2800_003E
0x2B00_002E
0x2F00_0022
38400
19200
9600
A=34
A=70
A=574
A=1150
A=2302
A=4606
0x3000_023E
0x3000_047E
0x3000_08FE
0x3000_11FE
A=126,B=8
0x0000_0046 A=94,B=11
A=70,B=15
0x2800_007E
0x2B00_005E
0x2F00_0046
A=254,B=8
0x0000_008E A=190,B=11
A=142,B=15
0x2800_00FE
0x2B00_00BE
0x2F00_008E
A=142
A=286
A=510,B=8
0x0000_011E A=382,B=11
A=286,B=15
0x2800_01FE
0x2B00_017E
0x2F00_011E
4800
Table 5-6 UART Baud Rate Setting Table
The UART0 and UART1 controllers support the auto-flow control function that uses two low-level
signals, nCTS (clear-to-send) and nRTS (request-to-send), to control the flow of data transfer
between the chip and external devices (e.g. Modem). When auto-flow is enabled, the UART is not
allowed to receive data until the UART asserts nRTS to external device. When the number of
bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the nRTS is de-
asserted. The UART sends data out when UART controller detects nCTS is asserted from
external device. If a valid asserted nCTS is not detected the UART controller will not send data
out.
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range
infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. The
maximum data rate supports up to 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA
SIR Protocol encoder/decoder. The IrDA SIR Protocol encoder/decoder is half-duplex only. So it
cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a
minimum 10ms transfer delay between transmission and reception, and this delay feature must
be implemented by software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN
mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, 1 start bit and 8 data bits
format with 1 stop bit are required in accordance with the LIN standard.
For NuMicro NUC200 Series, another alternate function of UART controllers is RS-485 9-bit
mode, and direction control provided by nRTS pin or can program GPIO (PB.2 for UART0_nRTS
and PB.6 for UART1_nRTS) to implement the function by software. The RS-485 mode is selected
by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 transceiver control is
implemented using the nRTS control signal from an asynchronous serial port to enable the RS-
485 transceiver. In RS-485 mode, many characteristics of the receiving and transmitting are same
as UART.
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5.13.2 Features
Full duplex, asynchronous communications
Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data
payloads
Supports hardware auto flow control/flow control function (nCTS, nRTS) and programmable
nRTS flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports nCTS wake-up function (UART0 and UART1 support)
Supports 7-bit receiver buffer time-out detection function
UART0/UART1 can through DMA channels to receive/transmit data
Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode.
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by nRTS pin
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5.14 PS/2 Device Controller (PS2D)
5.14.1 Overview
PS/2 device controller provides a basic timing control for PS/2 communication. All communication
between the device and the host is managed through the PS2_CLK and PS2_DAT pins. Unlike
PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as
meaningful code by firmware. The device controller generates the PS2_CLK signal after receiving
a “Request to Send” state, but host has ultimate control over communication. Data of PS2_DAT
line sent from the host to the device is read on the rising edge and sent from the device to the
host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software
can select 1 to 16 bytes for a continuous transmission.
5.14.2 Features
Host communication inhibit and Request to Send state detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
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5.15 I2S Controller (I2S)
5.15.1 Overview
The I2S controller consists of I2S protocol to interface with external audio CODEC. Two 8-word
deep FIFO for read path and write path respectively and is capable of handling 8-, 16-, 24- and
32-bit word sizes. PDMA controller handles the data movement between FIFO and memory.
5.15.2 Features
Operated as either Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Two PDMA requests, one for transmitting and the other for receiving
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5.16 Analog-to-Digital Converter (ADC)
5.16.1 Overview
The NuMicro NUC200 Series contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM Center-aligned trigger and external STADC pin.
5.16.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 8 single-end analog input channels or 4 differential analog input channels
Up to 760 kSPS conversion rate as ADC clock frequency is 16 MHz (chip working at 5V)
Three operating modes
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
Continuous scan mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion
An A/D conversion can be started by:
Writing 1 to ADST bit through software
PWM Center-aligned trigger
External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators
Conversion result can be compared with specify value and user can select whether to
generate an interrupt when conversion result matches the compare register setting
Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage,
and internal temperature sensor output
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5.17 Analog Comparator (ACMP)
5.17.1 Overview
The NuMicro NUC200 Series contains two comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input voltage is greater
than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to
cause an interrupt when the comparator output value changes. The block diagram is shown in 錯
誤! 找不到參照來源。.
5.17.2 Features
Analog input voltage range: 0~ VDDA
Supports Hysteresis function
Supports optional internal reference voltage input at negative end for each comparator
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5.18 PDMA Controller (PDMA)
5.18.1 Overview
The NuMicro NUC200 series DMA contains nine-channel peripheral direct memory access
(PDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA
PDMA_CSRx[PDMACEN]. The CPU can recognize the completion of a PDMA operation by
software polling or when it receives an internal PDMA interrupt. The PDMA controller can
increase source or destination address or fixed them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and DMA transfer mode.
5.18.2 Features
Supports nine PDMA channels and one CRC channel. Each PDMA channel can support
a unidirectional transfer
AMBA AHB master/slave interface compatible, for data transfer and register read/write
Hardware round robin priority scheme. DMA channel 0 has the highest priority and
channel 8 has the lowest priority
PDMA operation
□ Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
□ Supports word/half-word/byte transfer data width from/to peripheral
□ Supports address direction: increment, fixed.
Cyclic Redundancy Check (CRC)
□ Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
- CRC-CCITT: X16 + X12 + X5 + 1
- CRC-8: X8 + X2 + X + 1
- CRC-16: X16 + X15 + X2 + 1
- CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
□ Supports programmable CRC seed value.
□ Supports programmable order reverse setting for input data and CRC checksum.
□ Supports programmable 1’s complement setting for input data and CRC checksum.
□ Supports CPU PIO mode or DMA transfer mode.
□ Supports the follows write data length in CPU PIO mode
- 8-bit write mode (byte): 1-AHB clock cycle operation.
- 16-bit write mode (half-word): 2-AHB clock cycle operation.
□ - 32-bit write mode (word): 4-AHB clock cycle operation.
□ Supports byte alignment transfer data length and word alignment transfer source
address in CRC DMA mode.
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5.19 Smart Card Host Interface (SC)
5.19.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.19.2 Features
ISO7816-3 T=0, T=1 compliant
EMV2000 compliant
Supports up to three ISO7816-3 ports
Separates receive/ transmit 4 byte entry buffer for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error retry number limitation function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
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5.20 FLASH MEMORY CONTROLLER (FMC)
5.20.1 Overview
The NuMicro NUC200 Series has 128/64/32K bytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-System-
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex™-M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in Config0. By the way, the NuMicro NUC200 Series also provides
additional DATA Flash for user to store some application dependent data. For 128K bytes
APROM device, the data flash is shared with original 128K program memory and its start address
is configurable in Config1. For 64K/32K bytes APROM device, the data flash is fixed at 4K.
5.20.2 Features
Runs up to 50 MHz with zero wait state for continuous address read access
All embedded flash memory supports 512 bytes page erase
128/64/32 KB application program memory (APROM)
4 KB In-System-Programming (ISP) loader program memory (LDROM)
4KB data flash for 64/32 KB APROM device
Configurable data flash size for 128KB APROM device
Configurable or fixed 4 KB data flash with 512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
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6 APPLICATION CIRCUIT
AVCC
VREF
AVDD
USB_VBUS
USB_D-
33R
33R
USB_D+
USB OTG Slot
FB
DVCC
VDD
USB_VDD33_CAP
1uF
0.1uF
1uF
VBAT
VSS
Power
0.1uF
DVCC
FB
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
CS
VDD
VSS
AVSS
CLK
MISO
MOSI
SPI Device
DVCC
100K
DVCC
4.7K
DVCC
100K
[1]
VDD
NUC200/220
Series
ICE_DAT
ICE_CLK
nRESET
VSS
SWD
Interface
4.7K
CLK
DIO
I2C_SCL
I2C_SDA
VDD
VSS
I2C Device
20p
XT1_IN
DVCC
4~ 24 MHz
crystal
20p
20p
XT1_OUT
X32_IN
SC_PWR
Crystal
SC_RST
SC_CLK
Smart Card Slot
SC_DAT
SC_ Detect
32.768kHz
crystal
20p
X32_OUT
PC COM Port
RS 232 Transceiver
DVCC
RXD
TXD
ROUT
TIN
RIN
UART
LDO
TOUT
Reset
Circuit
10K
nRST
LDO_CAP
10uF/10V
1uF
Note1: It is recommended to use pull-up resistor on both ICE_DAT and ICE_CLK pin if CIOINI(Config0[10]) is set to 0.
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7
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
SYMBOL
PARAMETER
VDDVSS
VIN
MIN.
-0.3
VSS-0.3
4
MAX
+7.0
VDD+0.3
24
UNIT
V
DC Power Supply
Input Voltage
V
Oscillator Frequency
Operating Temperature
1/tCLCL
TA
MHz
C
-40
+85
+150
120
Storage Temperature
TST
-55
C
Maximum Current into VDD
-
mA
mA
mA
mA
mA
mA
Maximum Current out of VSS
120
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
35
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
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7.2 DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Operation Voltage
VDD
2.5
5.5
V
V
V
VDD = 2.5V ~ 5.5V up to 50 MHz
VSS
Power Ground
-0.3
AVSS
LDO Output Voltage
VLDO
1.62
1.8
1.98
VDD > 2.5V
When system used analog
function, please refer to chapter 7.4
for corresponding analog operating
voltage
Analog Operating Voltage
AVDD
VDD
V
VDD = 5.5V,
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
34
15
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
Operating Current
Normal Run Mode
at 50 MHz
VDD = 3.3V,
32
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V,
14
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
8.5
3.6
7.5
2.6
mA All IP enabled and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
mA All IP and PLL disabled,
XTAL = 12 MHz
Operating Current
Normal Run Mode
at 12 MHz
VDD = 3.3V,
mA All IP enabled and PLL disabled,
XTAL = 12 MHz
VDD = 3.3V,
mA All IP and PLL disabled,
XTAL = 12 MHz
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD = 5.5V,
IDD9
3.6
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
IDD17
IDD18
IDD19
2
mA All IP and PLL disabled,
XTAL = 4 MHz
Operating Current
Normal Run Mode
at 4 MHz
VDD = 3.3V,
2.8
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
VDD = 3.3V,
1.2
mA All IP and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
141
129
138
125
125
120
125
All IP enabled and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 5.5V,
All IP and PLL disabled,
A
Operating Current
Normal Run Mode
at 32.768 kHz
XTAL = 32.768 kHz
VDD = 3.3V,
All IP enabled and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 3.3V,
All IP and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 5.5V,
All IP enabled and PLL disabled,
A
LIRC10 kHz enabled
VDD = 5.5V,
Operating Current
Normal Run Mode
at 10 kHz
All IP and PLL disabled,
A
LIRC10 kHz enabled
VDD = 3.3V,
All IP enabled and PLL disabled,
A
LIRC10 kHz enabled
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD = 3.3V,
IDD20
120
All IP and PLL disabled,
LIRC10kHz enabled
A
VDD = 5.5V,
IIDLE1
IIDLE2
IIDLE3
28
10
27
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
Operating Current
Idle Mode
at 50 MHz
VDD = 3.3V,
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
9
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
7.5
2.4
6.5
1.5
mA
All IP enabled and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
mA All IP and PLL disabled,
XTAL = 12 MHz
Operating Current
Idle Mode
VDD = 3.3V,
at 12 MHz
mA
All IP enabled and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V,
mA All IP and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
IIDLE9
IIDLE10
IIDLE11
3.3
1.7
2.4
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
Operating Current
Idle Mode
VDD = 5.5V
mA All IP and PLL disabled,
XTAL = 4 MHz
at 4 MHz
VDD = 3.3V,
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD = 3.3V,
IIDLE12
0.8
mA All IP and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
IIDLE13
IIDLE14
IIDLE15
IIDLE16
IIDLE13
IIDLE14
IIDLE15
IIDLE16
133
120
133
120
122
118
122
118
All IP enabled and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 5.5V,
All IP and PLL disabled,
A
Operating Current
XTAL = 32.768 kHz
VDD = 3.3V,
Idle Mode
at 32.768 kHz
All IP enabled and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 3.3V,
All IP and PLL disabled,
A
XTAL = 32.768 kHz
VDD = 5.5V,
All IP enabled and PLL disabled,
A
LIRC10 kHz enabled
VDD = 5.5V,
All IP and PLL disabled,
A
Operating Current
Idle Mode
LIRC10 kHz enabled
VDD = 3.3V,
at 10 kHz
All IP enabled and PLL disabled,
A
LIRC10 kHz enabled
VDD = 3.3V
All IP and PLL disabled,
A
LIRC10 kHz enabled
VDD = 5.5V, RTC disabled,
A
IPWD1
IPWD2
IPWD3
IPWD4
15
15
17
17
When BOD function disabled
VDD = 3.3V, RTC disabled,
A
Standby Current
When BOD function disabled
Power-down Mode
(Deep Sleep Mode)
VDD = 5.5V, RTC enabled ,
A
When BOD function disabled
VDD = 3.3V, RTC enabled ,
A
When BOD function disabled
Input Current PA, PB, PC,
PD, PE, PF (Quasi-
bidirectional mode)
VDD = 5.5V, VIN = 0V or VIN=VDD
IIN1
-50
-60
A
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SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Input Current at nRESET[1]
VDD = 3.3V, VIN = 0.45V
VDD = 5.5V, 0<VIN<VDD
IIN2
ILK
-55
-45
-30
+2
A
A
Input Leakage Current PA,
PB, PC, PD, PE, PF
-2
-
-
Logic 1 to 0 Transition Current
PA~PF (Quasi-bidirectional
mode)
[3]
VDD = 5.5V, VIN<2.0V
ITL
-650
-200
A
VDD = 4.5V
VDD = 2.5V
-0.3
-0.3
-
-
0.8
0.6
Input Low Voltage PA, PB,
PC, PD, PE, PF (TTL input)
VIL1
V
VDD
+0.2
VDD = 5.5V
VDD =3.0V
2.0
1.5
-
-
Input High Voltage PA, PB,
PC, PD, PE, PF (TTL input)
VIH1
V
VDD
+0.2
Input Low Voltage PA, PB,
PC, PD, PE, PF (Schmitt
input)
VIL2
VIH2
VHY
VIL3
-0.3
-
-
0.3VDD
V
V
V
Input High Voltage PA, PB,
PC, PD, PE, PF (Schmitt
input)
VDD
+0.2
0.7VDD
Hysteresis voltage of PA, PB,
PC, PD,PE, PF (Schmitt
input)
0.2VDD
VDD = 4.5V
VDD = 3.0V
0
0
-
-
0.8
0.4
Input Low Voltage XT1_IN[*2]
V
V
VDD
+0.2
VDD = 5.5V
VDD = 3.0V
3.5
2.4
-
Input High Voltage XT1_IN[*2]
VIH3
VDD
+0.2
-
-
Input Low Voltage X32_IN[*2]
Input High Voltage X32_IN[*2]
VIL4
VIH4
0
0.4
1.8
v
1.2
V
Negative going threshold
(Schmitt input), nRESET
0.2VDD
-0.2
VILS
-0.5
-
-
V
V
Positive going threshold
(Schmitt input), nRESET
VDD
+0.5
VIHS 0.7VDD
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
VDD = 4.5V, VS = 2.4V
VDD = 2.7V, VS = 2.2V
VDD = 2.5V, VS = 2.0V
ISR11
ISR12
ISR12
ISR21
ISR22
ISR22
-300
-50
-40
-24
-4
-370
-70
-60
-28
-6
-450
-90
-80
-32
-8
A
A
Source Current PA, PB, PC,
PD, PE, PF (Quasi-
bidirectional Mode)
A
mA
mA
mA
Source Current PA, PB, PC,
PD, PE, PF (Push-pull Mode)
-3
-5
-7
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NuMicro NUC200/220 Series Datasheet
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD = 4.5V, VS = 0.45V
VDD = 2.7V, VS = 0.45V
VDD = 2.5V, VS = 0.45V
ISK1
ISK1
ISK1
10
7
16
10
9
20
13
12
mA
mA
mA
Sink Current PA, PB, PC, PD,
PE, PF (Quasi-bidirectional
and Push-pull Mode)
6
Brown-out Voltage with
BOD_VL [1:0] = 00b
VBO2.2
VBO2.7
VBO3.8
VBO4.5
VBH
2.1
2.6
3.5
4.2
30
2.2
2.7
3.7
4.4
-
2.3
2.8
3.9
4.6
150
V
V
Brown-out Voltage with
BOD_VL [1:0] = 01b
Brown-out voltage with
BOD_VL [1:0] = 10b
V
Brown-out Voltage with
BOD_VL [1:0] = 11b
V
Hysteresis range of BOD
voltage
VDD = 2.5V~5.5V
mV
Note:
1. nRESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
7.3 3. Pins of PA, PB, PC, PD, PE and PF can source a transition current when they are being externally driven from
1 to 0. In the condition of VDD = 5.5 V, the transition current reaches its maximum value when VIN approximates
to 2 V.AC Electrical Characteristics
7.3.1 External 4~24 MHz High Speed Oscillator
tCLCL
tCLCH
90%
10%
0.7 VDD
0.3 VDD
tCLCX
tCHCL
tCHCX
Note: Duty cycle is 50%.
SYMBOL
tCHCX
PARAMETER
Clock High Time
CONDITION
MIN.
10
10
2
TYP. MAX. UNIT
-
-
-
-
-
nS
nS
nS
nS
tCLCX
Clock Low Time
Clock Rise Time
Clock Fall Time
-
tCLCH
15
15
tCHCL
2
7.3.2 External 4~24 MHz High Speed Crystal
PARAMETER
CONDITION
MIN.
TYP.. MAX. UNIT
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
Operation Voltage VDD
Temperature
-
2.5
-40
-
-
-
5.5
85
-
V
℃
-
Operating Current
Clock Frequency
12 MHz at VDD = 5V
External crystal
1
mA
MHz
4
24
7.3.2.1 Typical Crystal Application Circuits
CRYSTAL
C1
C2
R
4 MHz ~ 24 MHz
10~20pF
10~20pF
without
XT1_OUT
XT1_IN
R
C1
C2
Figure 7-1 Typical Crystal Application Circuit
7.3.3 External 32.768 kHz Low Speed Crystal Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
TYP. MAX. UNIT
-
-
-
-
5.5
85
V
℃
Operation Temperature
Operation Current
Clock Frequency
-40
32.768KHz at VDD=5V
External crystal
1.5
A
-
32.768
-
kHz
7.3.4 Internal 22.1184 MHz High Speed Oscillator
PARAMETER
Operation Voltage VDD
CONDITION
MIN.
2.5
-
TYP. MAX. UNIT
-
-
5.5
V
MHz
%
Center Frequency
-
22.1184
-
-
+25℃; VDD =5 V
Calibrated Internal Oscillator Frequency
-1
+1
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
-40℃~+85℃;
-3
-
-
+3
-
%
VDD=2.5 V~5.5 V
VDD =5 V
Operation Current
500
uA
7.3.5 Internal 10 kHz Low Speed Oscillator
PARAMETER
CONDITION
MIN.
2.5
-
TYP. MAX. UNIT
Operation Voltage VDD
-
-
10
-
5.5
-
V
kHz
%
Center Frequency
-
+25℃; VDD =5 V
-30
+30
Calibrated Internal Oscillator Frequency
-40℃~+85℃;
-50
-
+50
%
VDD=2.5 V~5.5 V
7.4 Analog Characteristics
7.4.1 12-bit SARADC Specification
SYMBOL
-
PARAMETER
MIN.
TYP. MAX. UNIT
Resolution
-
-
-
-
-
-
12
-1~4
±4
Bit
LSB
LSB
LSB
-
DNL
INL
EO
Differential nonlinearity error
Integral nonlinearity error
Offset error
-1~2
±2
±1
10
EG
Gain error (Transfer gain)
Monotonic
1
1.005
-
Guaranteed
FADC
FS
ADC clock frequency (AVDD = 5V/3V)
Sample rate
-
-
-
-
16/8
760
5.5
-
MHz
kSPS
V
VDDA
IDD
Supply voltage
3
-
-
0.5
1.5
-
mA
mA
V
Supply current (Avg.)
IDDA
VREF
IREF
VIN
-
-
Reference voltage
Reference current (Avg.)
Input voltage
3
-
VDDA
-
1
mA
V
0
-
VREF
7.4.2 LDO and Power Management Specification
PARAMETER
MIN.
TYP. MAX. UNIT
NOTE
Jan 31, 2019
Page 90 of 100
Revision 1.01
NuMicro NUC200/220 Series Datasheet
Input Voltage VDD
Output Voltage
2.5
5.5
V
V
VDD input voltage
VDD > 2.5 V
1.62
1.8
1.98
℃
F
Operating Temperature
-40
-
25
1
85
-
Cbp
RESR = 1 Ω
Note:
1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between VDD and the
closest VSS pin of the device.
2. To ensure power stability, a 1 F or higher capacitor must be connected between LDO_CAP pin and the closest VSS
pin of the device.
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
7.4.3 Low Voltage Reset Specification
PARAMETER
CONDITION
MIN.
TYP. MAX. UNIT
Operation Voltage
Quiescent Current
Operation Temperature
-
0
-
5.5
5
V
-
1
VDD=5.5 V
-
A
℃
-40
25
85
Temperature=25℃
Temperature=-40℃
1.7
-
2.0
2.4
2.3
-
V
V
Threshold Voltage
Hysteresis
Temperature=85℃
-
1.6
0
-
V
V
-
0
0
7.4.4 Brown-out Detector Specification
PARAMETER
CONDITION
MIN.
0
TYP. MAX. UNIT
Operation Voltage
Operation Temperature
Quiescent Current
-
5.5
85
V
℃
μA
V
-
-
-40
-
25
-
AVDD=5.5 V
BOD_VL[1:0]=11
BOD_VL [1:0]=10
BOD_VL [1:0]=01
BOD_VL [1:0]=00
-
125
4.6
3.9
2.8
2.3
150
4.2
3.5
2.6
2.1
30
4.4
3.7
2.7
2.2
-
V
Brown-out Voltage
Hysteresis
V
V
mV
7.4.5 Power-on Reset Specification
PARAMETER
CONDITION
MIN.
TYP.
25
2
MAX. UNIT
℃
V
Operation Temperature
Reset Voltage
-
V+
-40
85
-
-
-
Quiescent Current
Vin > reset voltage
1
-
nA
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
7.4.6 Temperature Sensor Specification
PARAMETER
CONDITION
MIN.
2.5
TYP. MAX. UNIT
Operation Voltage[1]
Operation Temperature
Current Consumption
Gain
-
-
5.5
85
V
℃
-40
6.4
-
10.5
μA
mV/℃
mV
-1.76
720
Temp=0 ℃
Offset Voltage
Note: Internal operation voltage comes from internal LDO.
7.4.7 Comparator Specification
PARAMETER
CONDITION
MIN.
2.5
-40
-
TYP. MAX. UNIT
Operation Voltage AVDD
-
5.5
V
℃
μA
mV
V
Operation Temperature
Operation Current
Input Offset Voltage
Output Swing
-
25
20
5
85
40
VDD=3.0 V
-
-
-
-
-
15
0.1
0.1
-
-
VDDA-0.1
VDDA-1.2
-
Input Common Mode Range
DC Gain
-
V
70
dB
VCM = 1.2 V and
VDIFF = 0.1 V
Propagation Delay
-
200
20
-
ns
20 mV at VCM=1 V
50 mV at VCM=0.1 V
50 mV at VCM=VDD-1.2
10 mV for non-hysteresis
Comparison Voltage
10
-
mV
Hysteresis
VCM=0.4 V ~ VDD-1.2 V
-
-
±10
-
-
mV
CINP = 1.3 V
CINN = 1.2 V
Wake-up Time
2
μs
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
7.4.8 USB PHY Specification
7.4.8.1 USB DC Electrical Characteristics
SYMBOL
VIH
PARAMETER
Input High (driven)
CONDITION
MIN.
TYP.
MAX. UNIT
2.0
V
VIL
VDI
Input Low
0.8
V
V
Differential Input Sensitivity
|PADP-PADM|
0.2
0.8
0.8
Differential
VCM
VSE
Includes VDI range
2.5
2.0
V
Common-mode Range
Single-ended Receiver Threshold
Receiver Hysteresis
V
mV
V
200
VOL
Output Low (driven)
0
0.3
3.6
VOH
VCRS
RPU
Output High (driven)
2.8
V
Output Signal Cross Voltage
Pull-up Resistor
1.3
2.0
V
1.425
1.575
kΩ
Termination Voltage for Upstream
Port Pull-up (RPU)
VTRM
3.0
3.6
20
V
ZDRV
CIN
Driver Output Resistance
Transceiver Capacitance
Steady state drive*
Pin to GND
10
Ω
pF
*Driver output resistance doesn’t include series resistor resistance.
7.4.8.2 USB Full-Speed Driver Electrical Characteristics
SYMBOL
TFR
PARAMETER
CONDITION
CL=50p
MIN.
4
TYP.
MAX. UNIT
Rise Time
Fall Time
20
20
ns
ns
%
TFF
CL=50p
4
TFRFF
Rise and Fall Time Matching
TFRFF=TFR/TFF
90
111.11
7.4.8.3 USB Power Dissipation
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX. UNIT
USB_VBUS Current
(Steady State)
IVBUS
Standby
50
μA
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
7.4.8.4 USB LDO Specification
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX. UNIT
USB_VBUS USB_VBUS Pin Input Voltage
4.0
5.0
5.5
3.6
-
V
V
USB_VDD33
LDO Output Voltage
_CAP
3.0
3.3
1.0
Cbp
External Bypass Capacitor
uF
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
7.5 Flash DC Electrical Characteristics
SYMBOL
VDD
PARAMETER
Supply Voltage
CONDITION
MIN.
1.62
10
TYP.
MAX. UNIT
1.8
1.98
V[2]
year
ms
At 85℃
TRET
Data Retention
Page Erase Time
Mass Erase Time
Program Time
TERASE
TMER
2
10
20
ms
TPROG
μs
mA/MH
z
IDD1
Read Current
-
-
0.15
0.5
IDD2
IPD
Program/Erase Current
Power Down Current
7
mA
1
20
μA
1. VDD is source from chip LDO output voltage.
2. This table is guaranteed by design, not test in production.
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
8
PACKAGE DIMENSIONS
8.1 100-pin LQFP (14x14x1.4 mm footprint 2.0 mm)
H
D
D
A
A2
7
A1
51
7
50
H
E E
100
26
L1
L
1
25
c
e
b
Y
Controlling Dimension : Millimeters
Dimension in inch
Dimension in mm
Symbol
A
Min Nom
Max
Min Nom
Max
1.60
0.063
A1
A
0.002
0.05
1.45
0.27
0.053 0.055 0.057
1.35
0.17
0.10
1.40
0.22
b
0.011
0.008
0.009
0.006
0.007
0.004
0.547
0.547
c
0.15
0.20
D
E
14.00
0.551
0.551
0.020
14.10
13.90
13.90
0.556
0.556
14.00 14.10
0.50
e
H D
16.00
16.20
16.20
16.00
15.80
15.80
0.45
0.622
0.638
0.638
0.030
0.630
H E
L
0.622 0.630
0.60
1.00
0.75
0.024
0.039
0.018
L1
y
0.10
7
0.004
7
0
0
Jan 31, 2019
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NuMicro NUC200/220 Series Datasheet
8.2 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
Jan 31, 2019
Page 98 of 100
Revision 1.01
NuMicro NUC200/220 Series Datasheet
8.3 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Max
Min
Max Min
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.45
0.25
0.20
7.10
7.10
0.65
9.10
1.40
0.20
A
0.006
0.004
0.272
0.272
0.014
0.350
0.350
0.018
0.15
0.008 0.010
b
c
D
0.006
0.276
0.276
0.020
0.10 0.15
0.008
0.280
0.280
0.026
0.358
7.00
7.00
6.90
6.90
0.35
8.90
E
0.50
9.00
e
H
D
0.354
0.358
0.030
8.90
0.45
9.00
0.60
1.00
9.10
0.75
0.354
0.024
E
H
L
0.039
1
L
Y
0.004
7
0.10
7
0
0
0
Jan 31, 2019
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Revision 1.01
NuMicro NUC200/220 Series Datasheet
9
REVISION HISTORY
Revision
Date
Description
V1.00
June 07, 2012
Jan 31, 2019
Initial release
V1.01
Updated typo error in description.
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Jan 31, 2019
Page 100 of 100
Revision 1.01
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