NUC975-DF61YC [NUVOTON]
ARM® ARM926EJ-S Based 32-bit Microprocessor;
| 型号： | NUC975-DF61YC |
| 厂家： | 
NUVOTON |
| 描述： | ARM® ARM926EJ-S Based 32-bit Microprocessor |
| 文件： | 总91页 (文件大小：3082K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC970
ARM® ARM926EJ-S Based
32-bit Microprocessor
NUC970 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of ARM926EJ-S based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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Table of Contents
List of Figures...........................................................................................6
1 GENERAL DESCRIPTION...................................................................7
2 FEATURES ..........................................................................................8
1.1 NUC970 Series Features ...................................................................... 8
3 PARTS INFORMATION LIST AND PIN CONFIGURATION ..............15
3.1 NUC970 Series Part Number Naming Guide ...............................................15
3.2 NUC970 Series Part Selection Guide........................................................16
3.3 Pin Configuration................................................................................17
3.3.1 NUC972DFxxY Pin Diagram....................................................................... 17
3.3.2 NUC975DKxxY Pin Diagram....................................................................... 18
3.3.3 NUC976DKxxY Pin Diagram....................................................................... 19
3.3.4 NUC977DKxxY Pin Diagram....................................................................... 20
3.3.5 NUC978DKxxY Pin Diagram....................................................................... 21
3.4 Pin Description ..................................................................................22
4 BLOCK DIAGRAM..............................................................................42
4.1 NUC970 Series Block Diagram ...............................................................42
5 FUNCTIONAL DESCRIPTION...........................................................43
5.1 ARM® ARM926EJ-S CPU Core...............................................................43
5.1.1 Overview.............................................................................................. 43
5.2 System Manager ................................................................................44
5.2.1 Overview.............................................................................................. 44
5.3 Clock Controller (CLK_CTL)...................................................................44
5.3.1 Overview.............................................................................................. 44
5.3.2 Features .............................................................................................. 44
5.4 Advanced Interrupt Controller (AIC)..........................................................44
5.4.1 Overview.............................................................................................. 44
5.4.2 Features .............................................................................................. 45
5.5 SDRAM Interface Controller (SDIC)..........................................................45
5.5.1 Overview.............................................................................................. 45
5.5.2 Features .............................................................................................. 46
5.6 MTP Controller (MTP) ..........................................................................46
5.6.1 Overview.............................................................................................. 46
5.6.2 Features .............................................................................................. 46
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5.7 External Bus Interface (EBI)...................................................................46
5.7.1 Overview.............................................................................................. 46
5.7.2 Features .............................................................................................. 46
5.8 General Purpose I/O (GPIO) ..................................................................46
5.8.1 Overview.............................................................................................. 47
5.8.2 Features .............................................................................................. 47
5.9 General DMA Controller (GDMA).............................................................47
5.9.1 Overview.............................................................................................. 47
5.9.2 Features .............................................................................................. 47
5.10Timer Controller (TMR).........................................................................47
5.10.1 Overview.............................................................................................. 48
5.10.2 Features .............................................................................................. 48
5.11Enhance Timer Controller (ETMR) ...........................................................48
5.11.1 Overview.............................................................................................. 48
5.11.2 Features .............................................................................................. 48
5.12Pulse Width Modulation (PWM)...............................................................48
5.12.1 Overview.............................................................................................. 49
5.12.2 Features .............................................................................................. 49
5.13Watchdog Timer (WDT)........................................................................49
5.13.1 Overview.............................................................................................. 49
5.13.2 Features .............................................................................................. 49
5.14Windowed Watchdog Timer (WWDT)........................................................50
5.14.1 Overview.............................................................................................. 50
5.14.2 Features .............................................................................................. 50
5.15Real Time Clock (RTC) ........................................................................51
5.15.1 Overview.............................................................................................. 51
5.15.2 Features .............................................................................................. 51
5.16UART Interface Controller (UART) ...........................................................52
5.16.1 Overview.............................................................................................. 52
5.16.2 Features .............................................................................................. 53
5.17Smart Card Host Interface (SC)...............................................................53
5.17.1 Overview.............................................................................................. 53
5.17.2 Features .............................................................................................. 53
5.18I2C Synchronous Serial Interface Controller (I2C) ..........................................54
5.18.1 Overview.............................................................................................. 54
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5.18.2 Features .............................................................................................. 54
5.19SPI Interface Controller (SPI) .................................................................55
5.19.1 Overview.............................................................................................. 55
5.19.2 Features .............................................................................................. 55
5.20I2S Controller (I2S) ..............................................................................55
5.20.1 Overview.............................................................................................. 55
5.20.2 Features .............................................................................................. 55
5.21Ethernet MAC Controller (EMAC) ............................................................56
5.21.1 Overview.............................................................................................. 56
5.21.2 Features .............................................................................................. 56
5.22USB 2.0 Device Controller (USBD)...........................................................56
5.22.1 Overview.............................................................................................. 56
5.22.2 Features .............................................................................................. 57
5.23USB Host Controller (USBH)..................................................................57
5.23.1 Overview.............................................................................................. 57
5.23.2 Features .............................................................................................. 57
5.24Controller Area Network (CAN) ...............................................................57
5.24.1 Overview.............................................................................................. 57
5.24.2 Features .............................................................................................. 58
5.25Flash Memory Interface (FMI).................................................................58
5.25.1 Overview.............................................................................................. 58
5.25.2 Features:.............................................................................................. 58
5.26Secure Digital Host Controller (SDH) ........................................................59
5.26.1 Overview.............................................................................................. 59
5.26.2 Features .............................................................................................. 59
5.27Cryptographic Accelerator (CRYPTO) .......................................................60
5.27.1 Overview.............................................................................................. 60
5.27.2 Features .............................................................................................. 60
5.282D Graphic Engine (GE2D)....................................................................61
5.28.1 Overview.............................................................................................. 61
5.28.2 Features .............................................................................................. 61
5.29JPEG Codec (JPEG) ...........................................................................62
5.29.1 Overview.............................................................................................. 62
5.29.2 Features .............................................................................................. 62
5.30LCD Display Interface Controller (LCM) .....................................................63
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5.30.1 Overview.............................................................................................. 63
5.30.2 Features .............................................................................................. 63
5.31Capture Sensor Interface Controller (CAP) .................................................63
5.31.1 Overview.............................................................................................. 64
5.31.2 Feature................................................................................................ 64
5.32Analog to Digital Converter (ADC)............................................................64
5.32.1 Overview.............................................................................................. 64
5.32.2 Features .............................................................................................. 64
6 ELECTRICAL CHARACTERISTICS ..................................................66
6.1 Absolute Maximum Ratings ...................................................................66
6.2 DC Electrical Characteristics ..................................................................67
6.2.1 NUC970 Series DC Electrical Characteristics................................................... 67
6.3 AC Electrical Characteristics ..................................................................70
6.3.1 External 4~24 MHz High Speed Oscillator....................................................... 70
6.3.2 External 4~24 MHz High Speed Crystal.......................................................... 71
6.3.3 External 32.768 kHz Low Speed Crystal ......................................................... 72
6.3.4 EBI Timing............................................................................................ 73
6.3.5 I2C Interface Timing ................................................................................. 74
6.3.6 SPI Interface Timing................................................................................. 75
6.3.7 I2S Interface Timing ................................................................................. 76
6.3.8 Ethernet Interface Timing........................................................................... 77
6.3.9 NAND Interface Timing ............................................................................. 79
6.3.10 SD Interface Timing ................................................................................. 80
6.3.11 LCD Display Interface Timing...................................................................... 82
6.3.12 Capture Sensor Interface Timing.................................................................. 83
6.4 Analog Characteristics .........................................................................84
6.4.1 12-bit SARADC ...................................................................................... 84
6.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR) ................................. 85
6.4.3 3.3V Power-On Reset (POR33) ................................................................... 86
6.4.4 1.2V Power-On Reset (POR12) ................................................................... 86
6.4.5 USB 2.0 PHY......................................................................................... 86
7 PACKAGE DIMENSIONS ..................................................................88
7.1 216L LQFP (24x24x1.4mm footprint 2.0mm) ...............................................88
7.2 128L LQFP (14x14x1.4mm footprint 2.0mm) ...............................................89
8 REVISION HISTORY .........................................................................90
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List of Figures
Figure 3-1 NUC970 Series Part Number Naming Guide............................................................... 15
Figure 3.3-1 NUC972DFxxY LQFP 216-pin Pin Diagram.............................................................. 17
Figure 3.3-2 NUC975DKxxY LQFP 128-pin Pin Diagram ............................................................. 18
Figure 3.3-3 NUC976DKxxY LQFP 128-pin Pin Diagram ............................................................. 19
Figure 3.3-4 NUC977DKxxY LQFP 128-pin Pin Diagram ............................................................. 20
Figure 3.3-5 NUC978DKxxY LQFP 128-pin Pin Diagram ............................................................. 21
Figure 66.3-1 External 4~24 MHz High Speed Oscillator Timing Diagram ................................... 70
Figure 6.3-2 Typical HXT Crystal Application Circuit..................................................................... 71
Figure 6.3-3 Typical LXT Crystal Application Circuit...................................................................... 72
Figure 6.3-4 External Bus Interface Timing Diagram..................................................................... 73
Figure 6.3-5 I2C Interface Timing Diagram .................................................................................... 74
Figure 6.3-6 SPI Interface Timing Diagram ................................................................................... 75
Figure 6.3-7 I2S Interface Timing Diagram..................................................................................... 76
Figure 6.3-8 RMII Interface Timing Diagram.................................................................................. 77
Figure 6.3-9 Ethernet PHY Management Interface Timing Diagram............................................. 78
Figure 6.3-10 NAND Interface Timing Diagram............................................................................. 79
Figure 6.3-11 SD Interface Default Mode Timing Diagram............................................................ 80
Figure 6.3-12 SD Interface High-Speed Mode Timing Diagram.................................................... 81
Figure 6.3-13 LCD Display Interface SYNC Type Timing Diagram............................................... 82
Figure 6.3-14 Capture Sensor Interface Timing Diagram.............................................................. 83
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1
GENERAL DESCRIPTION
The NUC970 series targeted for general purpose 32-bit microcontroller embeds an outstanding
CPU core ARM926EJ-S, a RISC processor designed by Advanced RISC Machines Ltd., runs up
to 300 MHz, with 16 KB I-cache, 16 KB D-cache and MMU, 56KB embedded SRAM and 16 KB
IBR (Internal Boot ROM) for booting from USB, NAND and SPI FLASH.
The NUC970 series integrates two 10/100 Mb Ethernet MAC controllers, USB 2.0 HS
HOST/Device controller with HS transceiver embedded, TFT type LCD controller, CMOS sensor
I/F controller, 2D graphics engine, DES/3DES/AES crypto engine, I2S I/F controller,
SD/MMC/NAND FLASH controller, GDMA and 8 channels 12-bit ADC controller with resistance
touch screen functionality. It also integrates UART, SPI/MICROWIRE, I2C, CAN, LIN, PWM,
Timer, WDT/Windowed-WDT, GPIO, Keypad, Smart Card I/F, 32.768 KHz XTL and RTC (Real
Time Clock).
In addition, the NUC970 series integrates a DRAM I/F, that runs up to 150MHz with supporting
DDR or DDR2 type SDRAM, and an External Bus Interface (EBI) that supports SRAM and
external device with DMA request and ack.
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2
FEATURES
1.1 NUC970 Series Features
Core
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ARM® ARM926EJ-S™ processor core runs up to 300 MHz
Support 16 KB instruction cache and 16 KB data cache
Support MMU
Support JTAG Debug interface
External Bus Interface (EBI)
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Support SRAM and external I/O devices
Support 8/16-bit data bus width
Support up to five chip selects for SRAM and external I/O devices
Support programmable access cycle
Support four 32-bit write buffers
DDR SDRAM Controller
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Support LPDDR and DDR2 SDRAM
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Clock speed up to 150 MHz
Support 16-bit data bus width
Memory size depended on embedded SDRAM configuration by different part number.
Embedded SRAM and ROM
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Support 56K bytes embedded SRAM
Support 16K bytes Internal Boot ROM (IBR)
Support up to four booting modes
Boot from USB
Boot from eMMC
Boot from NAND Flash
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Boot from SPI Flash
Clock Control
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Support two PLLs, up to 500 MHz, for high performance system operation
External 12 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low speed clock
source
Ethernet MAC Controller
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Support up to 2 Ethernet MAC controllers
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Support IEEE Std. 802.3 CSMA/CD protocol
Support packet time stamping for IEEE Std. 1588 protocol
Support 10 and 100 Mbps operations
Support Half- and Full-duplex operations
Support RMII interface to Ethernet physical layer PHY
Support Ethernet physical layer PHY management through MDC and MDIO interface
Support flow control in Full-duplex mode to receive, recognize and transmit PAUSE
frame
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Support CAM-like function to recognize 48-bit Ethernet MAC address
Support Wake-On-LAN by detecting Magic Packet
Support 256 bytes transmit FIFO and 256 bytes receive FIFO
Support DMA function
Support internal loop back mode for diagnostic
USB 2.0 Controller
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Support USB Revision 2.0 specification
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Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver
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Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver
Support Control, Bulk, Interrupt, Isochronous and Split transfers
Support USB host function compliant to Enhanced Host Controller Interface (EHCI) 1.0
specification to connect with USB 2.0 High-Speed (HS) device.
Support USB host function compliant to Open Host Controller Interface (OHCI) 1.0
specification to connect with USB 1.1 Full-Speed (FS) and Low-Speed (LS) devices
Support USB High-Speed (HS) and Full-Speed (FS) device function
Support USB device function with 1 endpoint for Control IN/OUT transfers and 12
programmable endpoints for Bulk, Interrupt and Isochronous IN/OUT transfers
Support suspend, resume and remote wake-up capability
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Support DMA function
Support 2048 Bytes internal SRAM for USB host function and 4096 Bytes internal
SRAM for USB device function
Flash Memory Interface
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Support NAND flash interface
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Support 8-bit data bus width
Support SLC and MLC type NAND flash device
Support 512 B, 2 KB, 4 KB and 8 KB page size NAND flash device
Support ECC4, ECC8, ECC12, ECC15 and ECC24 BCH algorithm for ECC code
generation, error detection and error correction.
Support eMMC flash interface
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Support DMA function to accelerate the data transfer between system memory and
NAND and eMMC flash.
I2S Controller
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Support I2S interface
Support both mono and stereo
Support both record and playback
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master and slave mode
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Support PCM interface
Support 2 slots mode to connect 2 device
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master mode
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Support four 8x24 (8 24-bit) buffer for left/right channel record and left/right playback
Support DMA function to accelerate the data transfer between system memory and
internal buffer
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Support 2 buffer address for left/right channel and 2 slots data transfer
LCD Display Controller
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Support 8/9/16/18/24-bit data with to connect with 80/68 series MPU type LCD module
Support resolution up to 1024x768
Support data format conversion from RGB444, RGB565, RGB666, RGB888, YUV422
and YUV444 to RGB444, RGB565, RGB666, RGB888, YUV422 and YUV444 for
display output
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Support CCIR-656 (with VSYNC, HSYNC and data enable sync signal) 8/16-bit YUV
data output to connect with external TV encoder
Support 8/16 bpp OSD data with video overlay function to facilitate the diverse graphic
UI
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Support linear 1X to 8X image scaling up function
Support Picture-In-Picture display function
Support hardware cursor
Capture (CMOS Sensor Interface)
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Support CCIR601 & CCIR656 interfaces to connect with CMOS image sensor
Support resolution up to 3M pixels
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Support YUV422 and RGB565 color format for data output by CMOS image sensor
Support YUV422, RGB565, RGB555 and Y-only color format for data storing to system
memory
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Support planar and packet data format for data storing to system memory
Support image cropping and the cropping window is up to 4096x2048
Support image scaling-down:
Support vertical and horizontal scaling-down for preview mode
Support N/M scaling factor where N is equal to or less than M
Support 2 pairs of configurable 16-bit N and 16-bit M
Support to combine two interlace-fields to a single frame for data output by TV-
decoder.
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Support 3 color processing effects
Negative picture
Sepia picture
Posterization
2D Graphic Engine
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Support 2D Bit Block Transfer (BitBLT) functions defined in Microsoft GDI
Support Host BLT
Support Pattern BLT
Support Color/Font Expanding BLT
Support Transparent BLT
Support Tile BLT
Support Block Move BLT
Support Copy File BLT
Support Color/Font Expansion
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Support Rectangle Fill
Support RGB332/RGB565/RGB888 data format.
Support fore/background colors and all Microsoft 256 ternary raster-operation codes
(ROP)
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Support both inside and outside clipping function
Support alpha-blending for source/destination picture overlaying
Support fast Bresenham line drawing algorithm to draw solid/textured line
Support rectangular border and frame drawing
Support picture re-sizing
Support down-scaling from 1/255 to 254/255
Support up-scaling from 1 to 1.996 (1+254/255)
Support object rotation with different degree
Support L45 (45 degree left rotation) and L90 (90 degree left rotation)
Support R45 (45 degree right rotation) and R90 (90 degree right rotation)
Support M180 (mirror/flop)
Support F180 (up-side-down (flip) and X180 (180 degree rotation)
JPEG Codec
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Support Baseline Sequential mode JPEG codec function compliant with ISO/IEC
10918-1 international JPEG standard
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Planar Format
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only)
format image
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Support to decode YCbCr 4:2:2 transpose format
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes
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Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
Support rotate function in encode mode
Packet Format
Support to encode interleaved YUYV format input image, output bit stream 4:2:2 and
4:2:0 format
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Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image RGB555, RGB565 and RGB888 formats.
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards
Support arbitrary width and height image encode and decode
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for
decode mode
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Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
Crypto Engine
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PRNG
Support 64-bit, 128-bit, 192-bit and 256-bit key generation
DES
Support FIPS 46-3
Support both encryption and decryption
Support ECB, CBC, CFB, OFB and CTR modes
3DES
Support FIPS NIST 800-67
Implements according to the X9.52 standard
Support 112-bit and 168-bit key
Support both encryption and decryption
Support ECB, CBC, CFB, OFB and CTR modes
AES
Support FIPS NIST 197
Support SP800-38A & addendum
Support 128-bit, 192-bit and 256-bit key
Support both encryption and decryption
Support ECB, CBC, CFB, OFB , CTR, CBC-CS1, CBC-CS2 and CBC-CS3 modes
Support Key Expander
SHA/HMAC
Support FIPS NIST 180, 180-1, 180-2
Support SHA-160, SHA-224, SHA-256, SHA-384, SHA-512 and corresponding HMAC
algorithm
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Support 128-bit MTP key
GDMA (General DMA)
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Support 2 channels GDMA for memory-to-memory data transfer without CPU
intervention
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Support increment and decrement for source and destination address calculation
Support 8-bit, 16-bit and 32-bit width data transfer
Support four 8-bit/16-bit/32-bit burst transfer
UART
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Support up to 11 UART controllers
Support 1 UART (UART 1) port with full model function (TXD, RXD, CTS, RTS, CDn,
RIn, DTR and DSR) and 64-byte FIFO
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Support 5 UART (UART 2/4/6/8/10) ports with flow control (TXD, RXD, CTS and RTS)
and 64-byte FIFO
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Support 5 TXD/RXD only UART ports (UART 0/3/5/7/9) with 16-byte FIFO for standard
device
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Support IrDA (SIR) and LIN function
Support RS-485 9-bit mode and direction control
Support programmable baud-rate generator up to 1/16 system clock
C-CAN
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Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Object)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Support power down wake-up function
Smart Card Host (SC)
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Compliant to ISO-7816-3 T=0, T=1
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Supports up to two ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
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Supports auto inverse convention function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
Timer
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Support 5 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Support one-shot, periodic, toggle and continuous operation modes
Enhanced Timer
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Support 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter
Independent clock source for each timer
Support one-shot, periodic, toggle and continuous operation modes
Supports external pin capture for interval measurement
Supports external pin capture for timer counter reset
Watchdog Timer
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Multiple clock sources
8 selectable time out period from 1.333us ~ 14.316sec (depends on clock source)
WDT can wake-up from power down or idle mode
Interrupt or reset selectable on watchdog timer time-out
Windowed-Watchdog Timer
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6-bit down counter with 11-bit pre-scale for wide range window selected
Interrupt on windowed-watchdog timer time-out
Reset on windowed-watchdog timer time out or reload in an unexpected time window
Real Time Clock (RTC)
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Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
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Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
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Supports battery power pin (VBAT)
Supports wake-up function
PWM
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Built-in up to two 16-bit PWM generators provide four PWM outputs
Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit pre-scale, two 16-bit counters, and one Dead-Zone generator
SPI
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Built-in up to two sets of SPI controller
Support SPI master mode
Support single/dual/quad bit data bus width
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Support burst mode operation that transmission and reception can be executed up to
four times in a transfer
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I2C
Support 2 slave/device select lines
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Up to two sets of I2C device
Support master mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
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Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
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Programmable clocks allow versatile rate control
Support software mode to generate I2C signaling
Advanced Interrupt Controller
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Support 58 interrupt sources, including 8 external interrupt sources
Support programmable normal or fast interrupt mode (IRQ, FIQ)
Support programmable edge-triggered or level-sensitive for 8 external interrupt
sources
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Support programmable low-active or high-active for 8 external interrupt sources
Support encoded priority methodology to allow for interrupt daisy-chaining
Support lower priority interrupt automatically mask out for nested interrupt
Support to clear interrupt flag automatically if interrupt source is programmed as edge-
triggered
GPIO
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TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Support pull-up and pull-down control
ADC
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12-bit SAR ADC with 800K/160K SPS
Up to 8-ch single-end input
Oct. 09 2018
Page 13 of 91
Rev 1.46
NUC970
–
–
–
–
–
–
Support up to 800K SPS in channel 1 and up to 160K SPS in others channels.
Support 4-wire or 5-wire resistance touch screen interface
Support touch pressure measurement for 4-wire touch screen application
Support pen down detection
Support battery measurement
Support keypad scan
MTP
–
–
Support 256-bit programmable memory for key of Crypto functionality
Support up to 15 times of programming and erase.
Low Voltage Detect (LVD) and Low Voltage Reset (LVR)
–
Support two, 2.6V and 2.8V, voltage detection levels
Interrupt when low voltage detected
Reset when low voltage detected
–
–
–
Low voltage reset threshold voltage levels: 2.4 V
Power Management
–
Advanced power management including Power Down, Deep Standby, CPU Standby
and Normal Operating modes
–
Normal Operating mode
CPU run normally and all clocks on, the current consumption of CORE_VDD is
around 185 mA (at CPU/DRAM clock is 300/150 MHz CPU).
–
–
CPU Standby mode
CPU clock stop, and all other clocks on.
Deep Standby mode
All clocks stop, except LXT, with SRAM retention, and the current consumption
of CORE_VDD is typicaly 3 mA
Power Down mode
All powers are off except RTC_VDD (3.3V) and the current consumption of
RTC_VDD is typicaly 7uA with RTC functionality on.
Operating Voltage
–
–
1.2V for core logic operating
–
–
1.8V for DDR or DDR2 SDRAM I/O operating
3.3V for normal I/O operating
Operating Temperature: -40℃~85℃
Packages:
–
–
–
All Green package (RoHS)
LQFP 216-pin
LQFP 128-pin
Oct. 09 2018
Page 14 of 91
Rev 1.46
NUC970
3
PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NUC970 Series Part Number Naming Guide
Figure 3-1 NUC970 Series Part Number Naming Guide
Oct. 09 2018
Page 15 of 91
Rev 1.46
NUC970
3.2 NUC970 Series Part Selection Guide
NUC970 Series
Part No.
NUC972DF71YC
NUC972DF61YC
NUC972DF61Y
NUC975DK61Y
NUC975DK41Y
NUC976DK61YC
NUC976DK61Y
NUC976DK41Y
NUC977DK61YC
NUC977DK61Y
NUC977DK41Y
NUC978DK61Y
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
-
√
√
√
√
√
√
√
√
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
300 16 16
128 56
64 56
64 56
64 56
16 56
64 56
64 56
16 56
64 56
64 56
16 56
64 56
24
24
24
24
24
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
24
24
24
-
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
2
2
4
4
4
4
4
4
4
12-bit 8-ch
12-bit 8-ch
12-bit 8-ch
12-bit 4-ch
12-bit 4-ch
12-bit 4-ch
12-bit 4-ch
12-bit 4-ch
-
146 11
146 11
146 11
87 10
87 10
2
2
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
LQFP216 -40 to +85
LQFP216 -40 to +85
LQFP216 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
LQFP128 -40 to +85
-
-
-
-
-
-
-
√
√
√
√
√
√
√
√
√
√
16
16
16
16
16
16
16
80
80
80
87
87
87
86
6
6
6
8
8
8
9
1
-
-
-
1
1
-
24
24
24
24
-
-
-
-
-
√
√
√
√
√
√
√
√
√
√
√
√
√
√
12-bit 5-ch
√
√
-
-
√
√
NUC978DK41Y
300 16 16
16 56
24
2
1
2
1
16
5
4
12-bit 5-ch
86
9
2
2
2
1
LQFP128 -40 to +85
Oct. 09 2018
Page 16 of 91
Rev 1.46
NUC970
3.3 Pin Configuration
3.3.1 NUC972DFxxY Pin Diagram
Figure 3.3-1 NUC972DFxxY LQFP 216-pin Pin Diagram
Oct. 09 2018
Page 17 of 91
Rev 1.46
NUC970
3.3.2 NUC975DKxxY Pin Diagram
Figure 3.3-2 NUC975DKxxY LQFP 128-pin Pin Diagram
Oct. 09 2018
Page 18 of 91
Rev 1.46
NUC970
3.3.3 NUC976DKxxY Pin Diagram
Figure 3.3-3 NUC976DKxxY LQFP 128-pin Pin Diagram
Oct. 09 2018
Page 19 of 91
Rev 1.46
NUC970
3.3.4 NUC977DKxxY Pin Diagram
Figure 3.3-4 NUC977DKxxY LQFP 128-pin Pin Diagram
Oct. 09 2018
Page 20 of 91
Rev 1.46
NUC970
3.3.5 NUC978DKxxY Pin Diagram
Figure 3.3-5 NUC978DKxxY LQFP 128-pin Pin Diagram
Oct. 09 2018
Page 21 of 91
Rev 1.46
NUC970
3.4 Pin Description
NUC972 NUC975 NUC976 NUC977 NUC978
DFxxY(C) DKxxY DKxxY DKxxY DKxxY
Pin
Type
Pin Name
PG.3
Description
I/O
I/O
I/O
O
General purpose digital I/O pin Port G Pin 3.
I2C1 data input/output pin.
1
2
3
4
-
-
-
-
-
-
-
-
I2C1_SDA
PG.2
General purpose digital I/O pin Port G Pin 2.
I2C1 clock pin.
I2C1_SCL
PG.1
I/O
I/O
I/O
O
General purpose digital I/O pin Port G Pin 1.
I2C0 data input/output pin.
2
3
2
3
2
3
2
3
I2C0_SDA
PG.0
General purpose digital I/O pin Port G Pin 0.
I2C0 clock pin.
I2C0_SCL
PG.14
I/O
O
General purpose digital I/O pin Port G Pin 14.
I2S left right channel clock.
I2S_LRCK
UART6_CTS
SC0_CD
CLK_OUT
PG.13
5
4
4
4
4
I
Clear to send input pin for UART6.
SmartCard0 card detect pin.
I
O
Reference Clock Output.
I/O
I
General purpose digital I/O pin Port G Pin 13.
I2S bit clock pin.
I2S_BCLK
UART6_RTS
SC0_PWR
PG.12
6
5
5
5
5
O
Request to send output pin for UART6.
SmartCard0 power pin.
O
I/O
I
General purpose digital I/O pin Port G Pin 12.
I2S data input.
I2S_DI
7
6
6
6
6
UART6_RXD
SC0_DAT
PG.11
I
Data receiver input pin for UART6.
SmartCard0 data pin.
I/O
I/O
O
General purpose digital I/O pin Port G Pin 11.
I2S data output.
I2S_DO
8
9
7
8
7
8
7
8
7
8
UART6_TXD
SC0_CLK
PG.10
O
Data transmitter output pin for UART6.
SmartCard0 clock pin.
O
I/O
O
General purpose digital I/O pin Port G Pin 10.
I2S master clock output pin.
I2S_MCLK
SC0_RST
O
SmartCard0 reset pin.
Oct. 09 2018
Page 22 of 91
Rev 1.46
NUC970
10
11
12
13
14
15
16
17
18
19
20
21
9
-
9
-
9
-
9
-
IO_VDD
CORE_VSS
CORE_VDD
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VDD
CORE_VSS
IO_VDD
CORE_VDD
PF.15
P
P
P
P
P
P
P
P
P
P
P
P
I/O
I
MCU I/O power pin.
MCU internal core ground pin.
MCU internal core power pin.
DDR ground pin.
10
-
10
-
10
-
10
-
11
-
11
-
11
-
11
-
DDR power pin.
DDR ground pin.
11
-
11
-
11
-
11
-
DDR power pin.
DDR ground pin.
12
-
12
-
12
-
12
-
DDR power pin.
MCU internal core ground pin.
MCU I/O power pin.
MCU internal core power pin.
-
-
-
-
13
13
13
13
General purpose digital I/O pin Port F Pin 15.
External interrupt 4 input pin.
-
-
-
-
-
-
-
-
INT4
PF.14
I/O
I
General purpose digital I/O pin Port F Pin 14.
Clear to send input pin for UART2.
Enhanced TIMER capture input pin.
External interrupt 3 input pin.
UART2_CTS
TM3_CAP
INT3
22
14
I
I
PF.13
I/O
O
O
I
General purpose digital I/O pin Port F Pin 13.
Request to send output pin for UART2.
Enhanced TIMER toggle output pin.
External interrupt 2 input pin.
UART2_RTS
TM3_TGL
INT2
23
15
-
-
-
PF.12
I/O
I
General purpose digital I/O pin Port F Pin 12.
Data receiver input pin for UART2.
Enhanced TIMER capture input pin.
External interrupt 1 input pin.
UART2_RXD
TM2_CAP
INT1
24
16
-
-
-
I
I
PF.11
I/O
O
O
I
General purpose digital I/O pin Port F Pin 11.
Data transmitter output pin for UART2.
Enhanced TIMER toggle output pin.
External interrupt 0 input pin.
UART2_TXD
TM2_TGL
INT0
25
26
17
-
-
-
-
14
14
14
PG.9
I/O
General purpose digital I/O pin Port G Pin 9.
Oct. 09 2018
Page 23 of 91
Rev 1.46
NUC970
LCD_DEN
PG.8
O
I/O
O
Data enable or display control signal.
General purpose digital I/O pin Port G Pin 8.
Vertical sync or frame sync.
27
28
29
-
-
-
15
16
17
15
16
17
15
16
17
LCD_VSYNC
PG.7
I/O
O
General purpose digital I/O pin Port G Pin 7.
Horizontal sync or line sync.
LCD_HSYNC
PG.6
I/O
O
General purpose digital I/O pin Port G Pin 6.
Pixel clock output.
LCD_CLK
PD.15
I/O
O
General purpose digital I/O pin Port D Pin 15.
LCD pixel data output bit 23.
LCD_DATA23
UART9_RXD
PWM3
30
18
-
-
-
I
Data receiver input pin for UART9.
PWM3 output pin.
O
EBI_nWAIT
PD.14
I
External I/O wait control.
I/O
O
General purpose digital I/O pin Port D Pin 14.
LCD pixel data output bit 22.
LCD_DATA22
UART9_TXD
PWM2
31
32
33
19
-
-
-
-
-
-
-
-
-
O
Data transmitter output pin for UART9.
PWM2 output pin.
O
EBI_nOE
PD.13
O
External I/O output enable.
I/O
O
General purpose digital I/O pin Port D Pin 13.
LCD pixel data output bit 21.
LCD_DATA21
PWM1
-
O
PWM1 output pin.
EBI_nWE
PD.12
O
External I/O chip write enable.
General purpose digital I/O pin Port D Pin 12.
LCD pixel data output bit 20.
I/O
O
LCD_DATA20
UART9_RXD
PWM0
-
I
Data receiver input pin for UART9.
PWM0 output pin.
O
EBI_nCS4
PD.11
O
External I/O chip select bank 4.
General purpose digital I/O pin Port D Pin 11.
LCD pixel data output bit 19.
I/O
O
LCD_DATA19
UART9_TXD
EBI_nCS3
PD.10
34
35
-
-
-
-
-
-
-
-
O
Data transmitter output pin for UART9.
External I/O chip select bank 3.
General purpose digital I/O pin Port D Pin 10.
O
I/O
Oct. 09 2018
Page 24 of 91
Rev 1.46
NUC970
LCD_DATA18
EBI_nCS2
PD.9
O
O
LCD pixel data output bit 18.
External I/O chip select bank 2.
I/O
O
General purpose digital I/O pin Port D Pin 9.
LCD pixel data output bit 17.
36
37
38
39
40
-
-
-
-
-
-
-
-
LCD_DATA17
EBI_nCS1
PD.8
O
External I/O chip select bank 1.
General purpose digital I/O pin Port D Pin 8.
LCD pixel data output bit 16.
I/O
O
-
-
-
LCD_DATA16
EBI_nCS0
PA.15
O
External I/O chip select bank 0.
General purpose digital I/O pin Port A Pin 15.
LCD pixel data output bit 15.
I/O
O
18
19
20
18
19
20
18
19
20
LCD_DATA15
PWM3
O
PWM3 output pin.
PA.14
I/O
O
General purpose digital I/O pin Port A Pin 14.
LCD pixel data output bit 14.
LCD_DATA14
PWM2
O
PWM2 output pin.
PA.13
I/O
O
General purpose digital I/O pin Port A Pin 13.
LCD pixel data output bit 13.
LCD_DATA13
PWM1
O
PWM1 output pin.
PA.12
I/O
O
General purpose digital I/O pin Port A Pin 12.
LCD pixel data output bit 12.
41
42
-
-
21
22
21
22
21
22
LCD_DATA12
PWM0
O
PWM0 output pin.
PA.11
I/O
O
General purpose digital I/O pin Port A Pin 11.
LCD pixel data output bit 11.
LCD_DATA11
PA.10
I/O
O
General purpose digital I/O pin Port A Pin 10.
LCD pixel data output bit 10.
43
44
-
23
24
23
24
23
24
LCD_DATA10
IO_VDD
20
P
MCU I/O power pin.
PA.9
I/O
O
General purpose digital I/O pin Port A Pin 9.
LCD pixel data output bit 9.
45
46
21
22
25
26
25
26
25
26
LCD_DATA9
PWRON_SET9
PA.8
IU
I/O
O
Power On Setting bit 9.
General purpose digital I/O pin Port A Pin 8.
LCD pixel data output bit 8.
LCD_DATA8
PWRON_SET8
IU
Power On Setting bit 8.
Oct. 09 2018
Page 25 of 91
Rev 1.46
NUC970
PA.7
I/O
O
General purpose digital I/O pin Port A Pin 7.
47
48
49
50
51
52
53
54
23
24
25
26
27
28
29
30
27
28
29
30
31
32
33
34
27
28
29
30
31
32
33
34
27
28
29
30
31
32
33
34
LCD_DATA7
PWRON_SET7
PA.6
LCD pixel data output bit 7.
IU
I/O
O
Power On Setting bit 7.
General purpose digital I/O pin Port A Pin 6.
LCD pixel data output bit 6.
LCD_DATA6
PWRON_SET6
PA.5
IU
I/O
O
Power On Setting bit 6.
General purpose digital I/O pin Port A Pin 5.
LCD pixel data output bit 5.
LCD_DATA5
PWRON_SET5
PA.4
IU
I/O
O
Power On Setting bit 5.
General purpose digital I/O pin Port A Pin 4.
LCD pixel data output bit 4.
LCD_DATA4
PWRON_SET4
PA.3
IU
I/O
O
Power On Setting bit 4.
General purpose digital I/O pin Port A Pin 3.
LCD pixel data output bit 3.
LCD_DATA3
PWRON_SET3
PA.2
IU
I/O
O
Power On Setting bit 3.
General purpose digital I/O pin Port A Pin 2.
LCD pixel data output bit 2.
LCD_DATA2
PWRON_SET2
PA.1
IU
I/O
O
Power On Setting bit 2.
General purpose digital I/O pin Port A Pin 1.
LCD pixel data output bit 1.
LCD_DATA1
PWRON_SET1
PA.0
IU
I/O
O
Power On Setting bit 1.
General purpose digital I/O pin Port A Pin 0.
LCD pixel data output bit 0.
LCD_DATA0
PWRON_SET0
ADC0
IU
AI
Power On Setting bit 0.
55
56
57
58
59
60
61
-
-
-
-
-
-
-
-
-
-
ADC input channel 0 or VBAT.
ADC input channel 6 or XM.
ADC input channel 4 or YM.
Ground pin for analog circuit.
Power supply for internal analog circuit.
ADC input channel 7 or XP.
31
32
33
34
35
36
35
36
37
38
39
40
35
36
37
38
39
40
ADC6
AI
ADC4
AI
AVSS
AP
AP
AI
AVDD
ADC7
ADC5
AI
ADC input channel 5 or YP.
Oct. 09 2018
Page 26 of 91
Rev 1.46
NUC970
62
63
64
65
66
67
68
69
70
-
-
-
-
41
-
ADC1
AI
AI
AI
AI
P
ADC input channel 1.
-
-
-
ADC3
ADC input channel 3 or VSENSE.
ADC input channel 2.
-
-
-
ADC2
37
41
42
43
44
45
46
-
-
VREF
ADC voltage reference pin.
RTC power input. (*. or 3.3V )
38 *.
35
36
37
38
39
42
-
RTC_VDD
SYS_PWREN
SYS_nWAKEUP
X32_IN
RTC wake-up output pin for external DC/DC enable
pin control.
-
-
-
-
O
IU
AI
AO
I/O
O
O
I
-
RTC wake-up interrupt input with internal pull-high.
External 32.768kHz crystal input.
External 32.768kHz crystal output.
General purpose digital I/O pin Port H Pin 4.
Data transmitter output pin for UART1.
External I/O address bus bit 0.
43
44
X32_OUT
PH.4
UART1_TXD
EBI_ADDR0
INT4
71
-
-
-
-
External interrupt 4 input pin.
PH.5
I/O
I
General purpose digital I/O pin Port H Pin 5.
Data receiver input pin for UART1.
External I/O address bus bit 1.
UART1_RXD
EBI_ADDR1
INT5
72
-
-
-
-
O
I
External interrupt 5 input pin.
PH.6
I/O
O
O
O
I
General purpose digital I/O pin Port H Pin 6.
SD/SDIO Port 1 – command/response.
Request to send output pin for UART1.
External I/O address bus bit 2.
SD1_CMD
UART1_RTS
EBI_ADDR2
INT6
73
-
-
-
-
External interrupt 6 input pin.
PH.7
I/O
O
I
General purpose digital I/O pin Port H Pin 7.
SD/SDIO Port 1 – clock.
SD1_CLK
UART1_CTS
EBI_ADDR3
INT7
74
-
-
40
-
Clear to send input pin for UART1.
External I/O address bus bit 3.
O
I
External interrupt 7 input pin.
PH.8
I/O
I/O
O
O
General purpose digital I/O pin Port H Pin 8.
SD/SDIO mode #1 data line bit 0.
Data transmitter output pin for UART4.
External I/O address bus bit 4.
SD1_DAT0
UART4_TXD
EBI_ADDR4
75
-
-
-
-
Oct. 09 2018
Page 27 of 91
Rev 1.46
NUC970
PH.9
I/O
I/O
I
General purpose digital I/O pin Port H Pin 9.
SD1_DAT1
UART4_RXD
EBI_ADDR5
PH.10
SD/SDIO mode #1 data line bit 1.
Data receiver input pin for UART4.
External I/O address bus bit 5.
76
77
78
-
-
-
-
-
-
-
-
-
-
-
-
O
I/O
I/O
O
O
I/O
I/O
I
General purpose digital I/O pin Port H Pin 10.
SD/SDIO mode #1 data line bit 2.
Request to send output pin for UART4.
External I/O address bus bit 6.
SD1_DAT2
UART4_RTS
EBI_ADDR6
PH.11
General purpose digital I/O pin Port H Pin 11.
SD/SDIO mode #1 data line bit 3.
Clear to send input pin for UART4.
External I/O address bus bit 7.
SD1_DAT3
UART4_CTS
EBI_ADDR7
PH.12
O
I/O
I
General purpose digital I/O pin Port H Pin 12.
SD/SDIO mode #1 – card detect.
Data transmitter output pin for UART8.
2nd SPI0 chip select pin.
SD1_nCD
UART8_TXD
SPI0_SS1
EBI_ADDR8
IO_VDD
79
39
-
-
-
O
O
O
P
External I/O address bus bit 8.
80
81
82
-
-
-
-
-
-
-
-
MCU I/O power pin.
CORE_VSS
CORE_VDD
PH.13
P
MCU internal core ground pin.
40
47
41
45
P
MCU internal core power pin.
I/O
O
I
General purpose digital I/O pin Port H Pin 13.
SD/SDIO mode #1 – power enable.
Data receiver input pin for UART8.
2nd SPI1 chip select pin.
SD1_nPWR
UART8_RXD
SPI1_SS1
EBI_ADDR9
PH.14
83
41
-
-
-
O
O
I/O
O
I
External I/O address bus bit 9.
General purpose digital I/O pin Port H Pin 14.
Request to send output pin for UART8.
CAN bus receiver1 input.
UART8_RTS
CAN1_RXD
EBI_nBE0
PH.15
84
85
-
-
-
-
-
-
-
-
O
I/O
I
External I/O low byte enable.
General purpose digital I/O pin Port H Pin 15.
Clear to send input pin for UART8.
UART8_CTS
Oct. 09 2018
Page 28 of 91
Rev 1.46
NUC970
CAN1_TXD
EBI_nBE1
PI.0
O
O
CAN bus transmitter1 output.
External I/O high byte enable.
I/O
I/O
I/O
O
General purpose digital I/O pin Port I Pin 0.
External I/O data bus bit 0.
86
87
-
-
-
-
-
EBI_DATA0
PI.1
General purpose digital I/O pin Port I Pin 1.
NAND flash chip select 0.
NAND_nCS0
UART7_TXD
EBI_DATA1
INT6
42
42
46
O
Data transmitter output pin for UART7.
External I/O data bus bit 1.
I/O
I
External interrupt 6 input pin.
General purpose digital I/O pin Port I Pin 2.
NAND flash srite protect.
PI.2
I/O
O
NAND_nWP
UART7_RXD
EBI_DATA2
INT7
88
43
-
43
47
I
Data receiver input pin for UART7.
External I/O data bus bit 2.
I/O
I
External interrupt 7 input pin.
General purpose digital I/O pin Port I Pin 3.
Sensor interface system clock.
NAND flash address latch enable.
I2C1 clock pin.
PI.3
I/O
O
VCAP_CLKO
NAND_ALE
I2C1_SCL
EBI_DATA3
CAN0_RXD
RTC_TICK
PI.4
O
89
44
48
44
48
O
I/O
I
External I/O data bus bit 3.
CAN bus receiver0 input.
O
RTC tick output
I/O
I
General purpose digital I/O pin Port I Pin 4.
Sensor interface pixel clock.
NAND flash command latch enable.
I2C1 data input/output pin.
VCAP_PCLK
NAND_CLE
I2C1_SDA
EBI_DATA4
CAN0_TX
PI.5
O
90
45
49
45
49
I/O
I/O
O
External I/O data bus bit 4.
CAN bus transmitter0 output.
General purpose digital I/O pin Port I Pin 5.
Sensor interface HSYNC.
I/O
I
VCAP_HSYNC
NAND_nWE
eMMC_CMD
91
46
50
46
50
O
NAND flash write enable.
I/O
eMMC command/Response.
Oct. 09 2018
Page 29 of 91
Rev 1.46
NUC970
EBI_DATA5
SD1_CMD
UART1_TXD
SPI1_SS0
PI.6
I/O
O
External I/O data bus bit 5.
SD/SDIO mode #1 – command/response.
Data transmitter output pin for UART1.
1st SPI1 chip select pin.
O
O
I/O
I
General purpose digital I/O pin Port I Pin 6.
Sensor interface VSYNC.
VCAP_VSYNC
NAND_nRE
eMMC_CLK
SC1_RST
O
NAND flash read enable.
O
eMMC clock output.
92
47
51
47
51
O
SmartCard1 reset pin.
EBI_DATA6
SD1_CLK
I/O
O
External I/O data bus bit 6.
SD/SDIO mode #1– clock.
UART1_RXD
SPI1_CLK
PI.7
I
Data receiver input pin for UART1.
SPI1 serial clock pin.
O
I/O
I
General purpose digital I/O pin Port I Pin 7.
Sensor interface even/odd field indicator.
NAND flash ready/busy channel 0.
eMMC data line bit 3.
VCAP_FIELD
NAND_RDY0
eMMC_DATA3
SC1_CLK
I
I/O
O
SmartCard1 clock pin.
93
48
52
48
52
EBI_DATA7
SD1_DAT0
UART1_RTS
I/O
I/O
O
External I/O data bus bit 7.
SD/SDIO mode #1 data line bit 0.
Request to send output pin for UART1.
SPI1_DO
I
SPI1 Data out pin.
(SPI1_DATA0)
(I/O) (SPI1 data 0 in dual/quad mode.)
PI.8
I/O
I
General purpose digital I/O pin Port I Pin 8.
Sensor interface data bus bit 0.
NAND flash data bus bit 0.
VCAP_DATA0
NAND_DATA0
eMMC_DATA0
SC1_DAT
I/O
I/O
I/O
I/O
I/O
I
eMMC data line bit 0.
94
49
53
49
53
SmartCard1 data pin.
EBI_DATA8
SD1_DAT1
UART1_CTS
External I/O data bus bit 8.
SD/SDIO mode #1 data line bit 1.
Clear to send input pin for UART1.
Oct. 09 2018
Page 30 of 91
Rev 1.46
NUC970
SPI1_DI
I
SPI1 Data input pin.
(SPI1_DATA1)
(I/O) (SPI1 data 1 in dual/quad mode.)
PI.9
I/O
I
General purpose digital I/O pin Port I Pin 9.
VCAP_DATA1
NAND_DATA1
eMMC_DATA1
SC1_PWR
EBI_DATA9
SD1_DAT2
UART4_TXD
PI.10
Sensor interface data bus bit 1.
NAND flash data bus bit 1.
I/O
I/O
O
eMMC data line bit 1.
95
50
54
50
54
SmartCard1 power pin.
I/O
I/O
O
External I/O data bus bit 9.
SD/SDIO mode #1 data line bit 2.
Data transmitter output pin for UART4.
General purpose digital I/O pin Port I Pin 10.
Sensor interface data bus bit 2.
NAND flash data bus bit 2.
I/O
I
VCAP_DATA2
NAND_DATA2
eMMC_DATA2
SC1_CD
I/O
I/O
I
eMMC data line bit 2.
96
51
55
51
55
SmartCard1 card detect pin.
External I/O data bus bit 10.
EBI_DATA10
SD1_DAT3
UART4_RXD
PI.11
I/O
I/O
I
SD/SDIO mode #1 data line bit 3.
Data receiver input pin for UART4.
General purpose digital I/O pin Port I Pin 11.
Sensor interface data bus bit 3.
NAND flash data bus bit 3.
I/O
I
VCAP_DATA3
NAND_DATA3
SC0_RST
97
52
56
52
56
I/O
O
SmartCard0 reset pin.
EBI_DATA11
PI.12
I/O
I/O
I
External I/O data bus bit 11.
General purpose digital I/O pin Port I Pin 12.
Sensor interface data bus bit 4.
NAND flash data bus bit 4.
VCAP_DATA4
NAND_DATA4
UART8_TXD
SC0_CLK
I/O
O
98
53
57
53
57
Data transmitter output pin for UART8.
SmartCard0 clock pin.
O
EBI_DATA12
SD1_nCD
I/O
I
External I/O data bus bit 12.
SD/SDIO mode #1 – card detect.
General purpose digital I/O pin Port I Pin 13.
99
54
58
54
58
PI.13
I/O
Oct. 09 2018
Page 31 of 91
Rev 1.46
NUC970
VCAP_DATA5
NAND_DATA5
UART8_RXD
SC0_DAT
I
I/O
I
Sensor interface data bus bit 5.
NAND flash data bus bit 5.
Data receiver input pin for UART8.
SmartCard0 data pin.
I/O
I/O
O
EBI_DATA13
SD1_nPWR
PI.14
External I/O data bus bit 13.
SD/SDIO mode #1 – power enable.
I/O
I
General purpose digital I/O pin Port I Pin 14.
Sensor interface data bus bit 6.
NAND flash data bus bit 6.
VCAP_DATA6
NAND_DATA6
UART8_RTS
SC0_PWR
EBI_DATA14
PI.15
I/O
O
100
55
59
55
59
Request to send output pin for UART8.
SmartCard0 power pin.
O
I/O
I/O
I
External I/O data bus bit 14.
General purpose digital I/O pin Port I Pin 15.
Sensor interface data bus bit 7.
NAND flash data bus bit 7.
VCAP_DATA7
NAND_DATA7
UART8_CTS
SC0_CD
I/O
I
101
56
60
56
60
Clear to send input pin for UART8.
SmartCard0 card detect pin.
I
EBI_DATA15
CLK_OUT
CORE_VDD
CORE_VSS
IO_VDD
I/O
O
External I/O data bus bit 15.
Clock output pin.
102
103
104
-
-
-
-
-
-
-
-
P
MCU internal core power pin.
MCU internal core ground pin.
MCU I/O power pin.
P
57
61
57
61
P
PG.15
I/O
I
General purpose digital I/O pin Port G Pin 15.
External interrupt 5 input pin.
-
-
-
-
-
-
-
-
-
INT5
PB.0
I/O
O
General purpose digital I/O pin Port B Pin 0.
NAND flash chip select 1.
NAND_nCS1
UART5_TXD
SPI0_SS1
TM1_TGL
105
58
58
59
O
Data transmitter output pin for UART5.
2nd SPI0 chip select pin.
O
O
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port B Pin 1.
NAND flash ready/busy channel 1.
PB.1
I/O
I
106
59
NAND_RDY1
Oct. 09 2018
Page 32 of 91
Rev 1.46
NUC970
UART5_RXD
SPI1_SS1
TM1_CAP
PB.2
I
O
Data receiver input pin for UART5.
2nd SPI1 chip select pin.
I
Enhanced TIMER capture input pin.
I/O
O
General purpose digital I/O pin Port B Pin 2.
Data transmitter output pin for UART6.
PWM0 output pin.
UART6_TXD
PWM0
107
-
62
60
62
O
TM0_TGL
PB.3
O
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port B Pin 3.
Data receiver input pin for UART6.
PWM1 output pin.
I/O
I
UART6_RXD
PWM1
108
109
-
-
63
61
62
63
O
TM0_CAP
PB.4
I
Enhanced TIMER capture input pin.
General purpose digital I/O pin Port B Pin 4.
Request to send output pin for UART6.
General purpose digital I/O pin Port B Pin 5.
Clear to send input pin for UART6.
MCU I/O ground pin.
I/O
O
-
-
UART6_RTS
PB.5
I/O
I
110
-
-
-
-
63
64
65
-
UART6_CTS
IO_VSS
PB.6
64
65
64
65
P
I/O
O
General purpose digital I/O pin Port B Pin 6.
1st SPI0 chip select pin.
111
60
SPI0_SS0
PB.7
I/O
O
General purpose digital I/O pin Port B Pin 7.
SPI0 serial clock pin.
112
113
61
62
66
67
66
67
66
67
SPI0_CLK
PB.8
I/O
General purpose digital I/O pin Port B Pin 8.
SPI0_DO
O
SPI0 Data out pin.
(SPI0_DATA0)
(I/O) (SPI0 data 0 in dual/quad mode.)
PB.9
I/O
I
General purpose digital I/O pin Port B Pin 9.
SPI0 Data input pin.
114
-
63
64
68
-
68
-
68
-
SPI0_DI
(SPI0_DATA1)
(I/O) (SPI0 data 1 in dual/quad mode.)
GND
P
I/O
O
Ground pin for digital.
PB.10
General purpose digital I/O pin Port B Pin 10.
Data transmitter output pin for UART10.
SPI0 data 2 in dual/quad mode.
CAN bus receiver0 input.
UART10_TXD
SPI0_DATA2
CAN0_RXD
115
65
69
69
69
I/O
I
Oct. 09 2018
Page 33 of 91
Rev 1.46
NUC970
PB.11
I/O
I
General purpose digital I/O pin Port B Pin 11.
UART10_RXD
SPI0_DATA3
CAN0_TXD
PB.12
Data receiver input pin for UART10.
SPI0 data 3 in dual/quad mode.
116
66
70
70
70
I/O
O
CAN bus transmitter0 output.
I/O
O
General purpose digital I/O pin Port B Pin 12.
Data transmitter output pin for UART10.
1st SPI1 chip select pin.
117
118
67
68
71
72
71
72
71
72
UART10_TXD
SPI1_SS0
PB.13
O
I/O
I
General purpose digital I/O pin Port B Pin 13.
Data receiver input pin for UART10.
SPI1 serial clock pin.
UART10_RXD
SPI1_CLK
PB.14
O
I/O
O
General purpose digital I/O pin Port B Pin 14.
Request to send output pin for UART10.
UART10_RTS
119
120
121
122
-
73
74
-
73
74
-
73
74
-
SPI1_DO
(SPI1_DATA0)
O
SPI1 Data out pin.
(I/O) (SPI1 data 0 in dual/quad mode.)
PB.15
I/O
I
General purpose digital I/O pin Port B Pin 15.
Clear to send input pin for UART10.
UART10_CTS
-
SPI1_DI
(SPI1_DATA1)
I
SPI1 Data input pin.
(I/O) (SPI1 data 1 in dual/quad mode.)
PG.4
I/O
O
General purpose digital I/O pin Port G Pin 4.
NAND flash chip select 1.
NAND_nCS1
UART7_TXD
SPI1_DATA2
PG.5
69
O
Data transmitter output pin for UART7.
SPI1 data 2 in dual/quad mode.
General purpose digital I/O pin Port G Pin 5.
NAND flash ready/busy channel 1.
Data receiver input pin for UART7.
SPI1 data 3 in dual/quad mode.
General purpose digital I/O pin Port C Pin 0.
NAND flash data bus bit 0.
I/O
I/O
I
NAND_RDY1
UART7_RXD
SPI1_DATA3
PC.0
70
-
-
-
I
I/O
I/O
I/O
I/O
I/O
I/O
123
124
-
-
-
-
-
-
-
-
NAND_DATA0
eMMC_DATA0
PC.1
eMMC data line bit 0.
General purpose digital I/O pin Port C Pin 1.
NAND flash data bus bit 1.
NAND_DATA1
Oct. 09 2018
Page 34 of 91
Rev 1.46
NUC970
eMMC_DATA1
PC.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
eMMC data line bit 1.
General purpose digital I/O pin Port C Pin 2.
NAND flash data bus bit 2.
125
126
127
128
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NAND_DATA2
eMMC_DATA2
PC.3
eMMC data line bit 2.
General purpose digital I/O pin Port C Pin 3.
NAND flash data bus bit 3.
NAND_DATA3
eMMC_DATA3
PC.4
eMMC data line bit 3.
General purpose digital I/O pin Port C Pin 4.
NAND flash data bus bit 4.
NAND_DATA4
eMMC_CMD
PC.5
eMMC command/Response.
General purpose digital I/O pin Port C Pin 5.
NAND flash data bus bit 5.
NAND_DATA5
eMMC_CLK
PC.6
eMMC clock output.
I/O
I/O
O
General purpose digital I/O pin Port C Pin 6.
NAND flash data bus bit 6.
NAND_DATA6
UART10_TXD
TM0_TGL
PC.7
129
130
131
-
-
-
-
-
-
-
-
-
-
-
-
Data transmitter output pin for UART10.
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port C Pin 7.
NAND flash data bus bit 7.
O
I/O
I/O
I
NAND_DATA7
UART10_RXD
TM0_CAP
PC.8
Data receiver input pin for UART10.
Enhanced TIMER capture input pin.
General purpose digital I/O pin Port C Pin 8.
NAND flash chip select 0.
I
I/O
O
NAND_nCS0
UART10_RTS
TM1_TGL
PC.9
O
Request to send output pin for UART10.
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port C Pin 9.
NAND flash address latch enable.
Clear to send input pin for UART10.
Enhanced TIMER capture input pin.
General purpose digital I/O pin Port C Pin 10.
NAND flash command latch enable.
O
I/O
O
NAND_ALE
UART10_CTS
TM1_CAP
PC.10
132
133
-
-
-
-
-
-
-
I
I
I/O
O
71
NAND_CLE
Oct. 09 2018
Page 35 of 91
Rev 1.46
NUC970
UART4_TXD
TM2_TGL
PC.11
O
O
I/O
O
I
Data transmitter output pin for UART4.
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port C Pin 11.
NAND flash write enable.
NAND_nWE
UART4_RXD
TM2_CAP
PC.12
134
72
-
-
-
Data receiver input pin for UART4.
Enhanced TIMER capture input pin.
General purpose digital I/O pin Port C Pin 12.
NAND flash read enable.
I
I/O
O
O
O
I/O
I
NAND_nRE
UART4_RTS
TM3_TGL
PC.13
135
73
-
-
-
Request to send output pin for UART4.
Enhanced TIMER toggle output pin.
General purpose digital I/O pin Port C Pin 13.
NAND flash ready/busy channel 0.
Clear to send input pin for UART4.
Enhanced TIMER capture input pin.
General purpose digital I/O pin Port C Pin 14.
NAND flash write protect.
NAND_RDY0
UART4_CTS
TM3_CAP
PC.14
136
137
74
-
-
-
-
-
-
I
I
I/O
O
O
I/O
O
I/O
O
I/O
O
I/O
I
-
NAND_nWP
PWM0
PWM0 output pin.
PJ.3
General purpose digital I/O pin Port J Pin 3.
JTAG test data out.
138
139
140
141
142
143
75
76
77
78
79
80
75
76
77
78
79
80
75
76
77
78
79
80
75
76
77
78
79
80
JTAG_TDO
PJ.0
General purpose digital I/O pin Port J Pin 0.
JTAG test clock.
JTAG_TCK
PJ.1
General purpose digital I/O pin Port J Pin 1.
JTAG test mode select.
JTAG_TMS
PJ.2
General purpose digital I/O pin Port J Pin 2.
JTAG test data in.
JTAG_TDI
PJ.4
I/O
O
IU
O
P
General purpose digital I/O pin Port J Pin 4.
JTAG Reset.
JTAG_nTRST
nRESET
External reset input: active LOW, with an internal
pull-up. Set this pin low reset to initial state.
Watch dog timer external reset output pin. Open-
drain.
WDT_nRST
IO_VDD
144
145
81
-
81
-
81
-
81
-
MCU I/O power pin.
CORE_VSS
P
MCU internal core ground pin.
Oct. 09 2018
Page 36 of 91
Rev 1.46
NUC970
146
147
148
149
150
151
152
-
82
-
82
-
82
-
82
-
CORE_VDD
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VDD
DDR_VSS
DDR_VDD
DDR_VSS
CORE_VSS
IO_VDD
PD.0
P
P
MCU internal core power pin.
DDR ground pin.
83
-
83
-
83
-
83
-
P
DDR power pin.
P
DDR ground pin.
83
-
83
-
83
-
83
-
P
DDR power pin.
P
DDR ground pin.
84
-
84
-
84
-
84
-
P
DDR power pin.
P
DDR ground pin.
153
154
-
-
-
-
P
MCU internal core ground pin.
MCU I/O power pin.
85
85
85
85
P
I/O
O
General purpose digital I/O pin Port D Pin 0.
SD/SDIO mode #0 command/response.
General purpose digital I/O pin Port D Pin 1.
SD/SDIO mode #0 clock.
155
156
157
158
159
160
161
86
87
88
89
90
91
92
86
87
88
89
90
91
92
86
87
88
89
90
91
92
86
87
88
89
90
91
92
SD0_CMD
PD.1
I/O
O
SD0_CLK
PD.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose digital I/O pin Port D Pin 2.
SD/SDIO mode #0 data line bit 0.
General purpose digital I/O pin Port D Pin 3.
SD/SDIO mode #0 data line bit 1.
General purpose digital I/O pin Port D Pin 4.
SD/SDIO mode #0 data line bit 2.
General purpose digital I/O pin Port D Pin 5.
SD/SDIO mode #0 data line bit 3.
General purpose digital I/O pin Port D Pin 6.
SD/SDIO mode #0 card detect.
SD0_DAT0
PD.3
SD0_DAT1
PD.4
SD0_DAT2
PD.5
SD0_DAT3
PD.6
SD0_nCD
PD.7
162
163
164
165
166
-
93
-
93
94
-
93
94
-
93
94
-
I/O
P
General purpose digital I/O pin Port D Pin 7.
MCU internal core power pin.
CORE_VDD
PLL_VDD
PLL_VSS
CORE_VDD
PH.3
P
PLL power input pin.
94
-
95
-
95
-
95
-
P
PLL ground.
P
MCU internal core power pin.
I/O
I/O
General purpose digital I/O pin Port H Pin 3.
I2C1 data input/output pin.
167
-
-
-
96
I2C1_SDA
Oct. 09 2018
Page 37 of 91
Rev 1.46
NUC970
UART9_RXD
CAN0_TXD
PWM3
I
O
O
I
Data receiver input pin for UART9.
CAN bus transmitter0 output.
PWM3 output pin.
INT3
External interrupt 3 input pin.
PH.2
I/O
O
O
I
General purpose digital I/O pin Port H Pin 2.
I2C1 clock pin.
I2C1_SCL
UART9_TXD
CAN0_RXD
PWM2
Data transmitter output pin for UART9.
CAN bus receiver0 input.
168
-
-
-
97
O
I
PWM2 output pin.
INT2
External interrupt 2 input pin.
PE.13
I/O
I
General purpose digital I/O pin Port E Pin 13.
Clear to send input pin for UART8.
Data receiver input pin for UART3.
Reference Clock Output.
UART8_CTS
UART3_RXD
CLK_OUT
PE.12
169
-
-
-
98
I
O
I/O
O
O
I/O
I
General purpose digital I/O pin Port E Pin 12.
Request to send output pin for UART8.
Data transmitter output pin for UART3.
General purpose digital I/O pin Port E Pin 11.
RMII1 receive data error.
170
171
172
-
-
-
-
-
-
-
-
-
99
UART8_RTS
UART3_TXD
PE.11
-
RMII1_RXERR
UART8_RXD
PE.10
I
Data receiver input pin for UART8.
General purpose digital I/O pin Port E Pin 10.
RMII1 carrier sense / receive data valid.
Data transmitter output pin for UART8.
General purpose digital I/O pin Port E Pin 9.
RMII1 receive data bus bit 1.
I/O
I
-
RMII1_CRSDV
UART8_TXD
PE.9
O
I/O
I
RMII1_RXDATA1
SD1_nPWR
UART1_CD
PE.8
173
-
-
-
-
O
I
SD/SDIO mode #1 power enable.
Carrier detect input pin for UART1.
General purpose digital I/O pin Port E Pin 8.
RMII1 receive data bus bit 0.
I/O
I
RMII1_RXDATA0
SD1_nCD
UART1_RI
174
-
-
-
-
I
SD/SDIO mode #1 card detect.
I
Ring indicator input pin for UART1.
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PE.7
I/O
I
General purpose digital I/O pin Port E Pin 7.
RMII1_REFCLK
SD1_DAT3
UART1_DSR
PE.6
RMII1 reference clock.
175
-
-
-
-
I/O
I
SD/SDIO mode #1 data line bit 3.
Data set ready input pin for UART1.
General purpose digital I/O pin Port E Pin 6.
RMII1 transmit enable.
I/O
O
RMII1_TXEN
SD1_DAT2
UART1_DTR
PE.5
176
-
-
-
-
I/O
O
SD/SDIO mode #1 data line bit 2.
Data terminal ready output pin for UART1.
General purpose digital I/O pin Port E Pin 5.
RMII1 transmit data bus bit 1.
I/O
O
RMII1_TXDATA1
SD1_DAT1
UART1_CTS
CLK_OUT
PE.4
177
95
-
-
-
I/O
I
SD/SDIO mode #1 data line bit 1.
Clear to send input pin for UART1.
Reference Clock Output.
O
I/O
O
General purpose digital I/O pin Port E Pin 4.
RMII1 Transmit Data bus
RMII1_TXDATA0
SD1_DAT0
UART1_RTS
PE.3
178
179
180
96
97
98
-
-
-
-
-
-
-
-
-
I/O
O
SD/SDIO mode #1 ata line bit 0.
Request to send output pin for UART1.
General purpose digital I/O pin Port E Pin 3.
RMII1 Management Data I/O
I/O
I/O
O
RMII1_MDIO
SD1_CLK
UART1_RXD
PE.2
SD/SDIO mode #1 clock.
I
Data receiver input pin for UART1.
General purpose digital I/O pin Port E Pin 2.
RMII1 Management Data Clock
I/O
O
RMII1_MDC
SD1_CMD
UART1_TXD
PE.1
O
SD/SDIO mode #1 command/response.
Data transmitter output pin for UART1.
General purpose digital I/O pin Port E Pin 1.
Data receiver input pin for UART0.
General purpose digital I/O pin Port E Pin 0.
Data transmitter output pin for UART0.
MCU I/O power pin.
O
I/O
I
181
182
99
96
97
96
97
100
101
UART0_RXD
PE.0
I/O
O
100
UART0_TXD
IO_VDD
183
184
101
102
98
99
98
99
102
103
P
XT1_IN
AI
External 12MHz crystal input pin.
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185
186
103
-
100
101
100
101
104
-
XT1_OUT
IO_VSS
AO
P
External 12MHz crystal output pin.
MCU I/O ground pin.
PF.9
I/O
I
General purpose digital I/O pin Port F Pin 9.
RMII0 receive data error.
187
188
189
190
191
192
193
194
195
196
104
105
106
107
108
109
110
111
112
113
102
103
104
105
106
107
108
109
110
111
102
103
104
105
106
107
108
109
110
111
105
106
107
108
109
110
111
112
113
114
RMII0_RXERR
PF.8
I/O
I
General purpose digital I/O pin Port F Pin 8.
RMII0 carrier sense / receive data valid.
General purpose digital I/O pin Port F Pin 7.
RMII0 receive data bus bit 1.
RMII0_CRSDV
PF.7
I/O
I
RMII0_RXDATA1
PF.6
I/O
I
General purpose digital I/O pin Port F Pin 6.
RMII0 receive data bus bit 0.
RMII0_RXDATA0
PF.5
I/O
I
General purpose digital I/O pin Port F Pin 5.
RMII0 reference clock.
RMII0_REFCLK
PF.4
I/O
O
General purpose digital I/O pin Port F Pin 4.
RMII0 transmit enable.
RMII0_TXEN
PF.3
I/O
O
General purpose digital I/O pin Port F Pin 3.
RMII0 transmit data bus bit 1.
RMII0_TXDATA1
PF.2
I/O
O
General purpose digital I/O pin Port F Pin 2.
RMII0 Transmit Data bus bit 0.
RMII0_TXDATA0
PF.1
I/O
I/O
I/O
O
General purpose digital I/O pin Port F Pin 1.
RMII0 Management Data I/O
RMII0_MDIO
PF.0
General purpose digital I/O pin Port F Pin 0.
RMII0 Management Data Clock
RMII0_MDC
PH.1
I/O
I
General purpose digital I/O pin Port H Pin 1.
USB overcurrent
197
198
114
115
112
113
112
113
115
116
USB_OVRCUR
INT1
I
External interrupt 1 input pin.
PH.0
I/O
I
General purpose digital I/O pin Port H Pin 0.
USB0 VBUS valid.
USB0_VBUSVLD
INT0
I
External interrupt 0 input pin.
PF.10
I/O
O
General purpose digital I/O pin Port F Pin 10.
199
200
116
-
114
-
114
-
117
-
USB host output power control pin for LQFP128
package only.
USB_PWREN
PE.15
I/O
General purpose digital I/O pin Port E Pin 15.
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USB1_PWREN
PE.14
O
I/O
O
USB1 host output power control pin.
General purpose digital I/O pin Port E Pin 14.
USB0 host output power control pin.
MCU internal core ground pin.
MCU internal core power pin.
MCU internal core power pin.
USB1 PLL power pin.
201
-
-
-
-
USB0_PWREN
CORE_VSS
CORE_VDD
CORE_VDD
USBPLL1_VDD
USB1_VSS
USB1_DM
202
-
-
-
-
-
P
-
115
116
117
-
115
116
117
-
118
118
118
-
P
203
204
205
206
207
208
209
210
211
212
213
214
215
-
117
118
-
P
P
P
USB1 ground pin.
119
120
121
122
123
-
118
119
120
121
122
123
124
125
126
127
128
1
118
119
120
121
122
123
124
125
126
127
128
1
119
120
121
122
123
-
I/O
I/O
AP
I
USB1 differential signal D-.
USB1 differential signal D+.
USB1 I/O power pin.
USB1_DP
USB1_VDD
USB1_REXT
USBPLL0_VDD
USB0_VSS
USB0_DM
USB1 module reference Resister.
USB0 PLL power pin.
P
P
USB0 ground pin.
124
125
126
127
128
1
124
125
126
127
128
1
I/O
I/O
AP
I
USB0 differential signal D-.
USB0 differential signal D+.
USB0 I/O power pin.
USB0_DP
USB0_VDD
USB0_REXT
IO_VSS
USB0 module reference Resister.
MCU I/O ground pin.
P
216
USB0_ID
IU
USB0 Host/Device select.
Note: Pin Type I=Digital Input, IU=Digital Input with Internal pull high, O=Digital Output, I/O= Digital Bi-direction;
AI=Analog Input, AO=Analog Output; P=Power Pin; AP=Analog Power
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4
BLOCK DIAGRAM
4.1 NUC970 Series Block Diagram
Hardware
Accelerator
ARM926EJ-S
300 MHz
Memory
Storage
Peripherals
I-Cache
16 KB
NAND Flash
Interface
AIC
2D Graphic
Engine
ROM 16KB
Timer X 5
ETimer X 4
WDT/WWDT
PWM X 4
GDMA
2-ch
SRAM 56KB
D-Cache
16 KB
eMMC Flash
Interface
JPEG
DDR2
SDRAM
SD Card
Interface
Cryptographic
MMU
EBI
AHB/APB Bus
Power Control
Clock Control
Connectivity
Human Interface
UART X 11
(IrDA, RS-485)
HS Ext.
Crystal Osc.
12 MHz
Video Capture
Sensor Interface
Ethernet MAC X 2
POR
USB 2.0
High Speed Host
CCAN X 2
LCD Display
Interface
LS Ext.
Crystal Osc.
32.768 kHz
USB 2.0
High Speed Device
LVR
LVD
SPI X 2, PIC
I2C X 2
ADC
(Touch Screen)
I2S
PLL x 2
SDIO
Smart Card X 2
Figure 4.1 NUC970 Series Block Diagram
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5
FUNCTIONAL DESCRIPTION
5.1 ARM® ARM926EJ-S CPU Core
5.1.1 Overview
The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose
microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full
memory management, high performance, and low power are all important.
The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling
the user to choose between high performance and high code density. The ARM926EJ-S CPU
core includes features for efficient execution of Java byte codes, providing Java performance
similar to JIT, but without the associated code overhead.
The ARM926EJ-S processor provides support for external coprocessor enabling floating-point or
other application-specific hardware acceleration to be added. The ARM926EJ-S CPU core
implements ARM architecture version 5TEJ.
The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-
performance processor subsystem, including:
An ARM9EJ-S integer core.
A Memory Management Unit (MMU).
Separate instruction and data cache.
Separate instruction and data AMBA AHB bus interfaces.
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5.2 System Manager
5.2.1 Overview
The system management describes following information and functions.
System Resets
System Power Architecture
System Memory Map
System management registers for Product Identifier (PDID), Power-On Setting,
System Wake-Up, Reset Control for on-chip controllers/peripherals, and multi-function
pin control.
System Control registers
5.3 Clock Controller (CLK_CTL)
5.3.1 Overview
The clock controller generates all clocks for Video, Audio, CPU, AMBA and all the engine modules.
This chip includes two PLL modules. The clock source for each module comes from the PLL, or from
the external crystal input directly. For each clock there is bit on the CLKEN register to control the clock
ON or OFF individually, and the divider setting is on the CLK_DIVCTL register. The register can also
be used to control the clock enable or disable for power control.
5.3.2 Features
Supports two PLLs, up to 500 MHz, for high performance system operation
External 12 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low speed clock source
5.4 Advanced Interrupt Controller (AIC)
5.4.1 Overview
An interrupt temporarily changes the sequence of program execution to react to a particular event
such as power failure, watchdog timer timeout, transmit/receive request from Ethernet MAC Controller,
and so on. The CPU processor provides two modes of interrupt, the Fast Interrupt (FIQ) mode for
critical session and the Interrupt (IRQ) mode for general purpose. The IRQ request is occurred when
the nIRQ input is asserted. Similarly, the FIQ request is occurred when the nFIQ input is asserted. The
FIQ has privilege over the IRQ and can preempt an ongoing IRQ. It is possible to ignore the FIQ and
the IRQ by setting the F and I bits in the current program status register (CPSR).
The Advanced Interrupt Controller (AIC) is capable of processing the interrupt requests up to 64
different sources. Currently, 61 interrupt sources are defined. Each interrupt source is uniquely
assigned to an interrupt channel. For example, the watchdog timer interrupt is assigned to channel 1.
The AIC implements a proprietary eight-level priority scheme that categories the available 61 interrupt
sources into eight priority levels. Interrupt sources within the priority level 0 is the highest priority and
the priority level 7 is the lowest. In order to make this scheme work properly, a certain priority level
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must be specified to each interrupt source during power-on initialization; otherwise, the system shall
behave unexpectedly. Within each priority level, interrupt source that is positioned in a lower channel
has a higher priority. Interrupt source that is active, enabled, and positioned in the lowest channel with
priority level 0 is promoted to the FIQ. Interrupt sources within the priority levels other than 0 are
routed to the IRQ. The IRQ can be preempted by the occurrence of the FIQ. Interrupt nesting is
performed automatically by the AIC.
Though interrupt sources originated from the chip itself are intrinsically high-level sensitive, the AIC
can be configured as either low-level sensitive, high-level sensitive, negative-edge triggered, or
positive-edge triggered to each interrupt source.
5.4.2 Features
AMBA APB bus interface
External interrupts can be programmed as either edge-triggered or level-sensitive
External interrupts can be programmed as either low-active or high-active
Flags to reflect the status of each interrupt source
Individual mask for each interrupt source
Support proprietary 8-level interrupt scheme to employ the priority scheme.
Priority methodology is adopted to allow for interrupt daisy-chaining
Automatically masking out the lower priority interrupt during interrupt nesting
Automatically clearing the interrupt flag when the external interrupt source is programmed to
be edge-triggered
5.5 SDRAM Interface Controller (SDIC)
5.5.1 Overview
The SDRAM Controller support DDR and DDR2 type SDRAM. Only 16-bit data bus width is
supported.
The SDRAM controller interface to three isolated AHB. All these AHB masters can access the memory
independent. Except the memory access, the masters of AHB also could access the SDRAM control
registers.
For performance and function issue, the SDRAM controller also supports the proprietary Enhanced-
AHB. The EAHB add the down-count address mode, byte-enable signal and explicit burst access
number. The explicit access number function is reached by modify the HBURST signal to EHBURST
and it represent the access number. The maximum EAHB access number is 16. The SDRAM
controller also builds a BIST module to test the external memory device.
An internal arbiter is used to schedule the access from the masters and the BIST request, the BIST
request with the highest priority and the then the AHB3 master, AHB2 master and AHB1 master.
The SDRAM controller uses 3 pipe queues to improve the SDRAM command and data bus efficiency.
The request in queue0 is the SDRAM active data access request. Simultaneous, the requests in
queue1 can request the controller to issue the ACTIVE or PRECHARGE command to reduce the
access latency for the later command. The queue1 also can issue the READ or WRITE command to
close the SDRAM command when advance pipe queue
The SDRAM refresh rate is programmable. The Refresh and Power-on control module generate the
refresh request signal and SDRAM power on sequence. The SDRAM controller also supports software
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reset, SDRAM self refresh and auto power down function.
5.5.2 Features
Support DDR and DDR2 SDRAM
Clock speed up to 150 MHz
Support 16-bit data bus width
Memory size depended on embedded SDRAM configuration by different part number.
5.6 MTP Controller (MTP)
5.6.1 Overview
The MTP (Multi-Time Programmable) controller performs an easy way to use and program the
256-bit Key for IP Security Engine. There is a MTP EPROM in this chip, and it can be
programmed 15 times. User can program 256-bit key and 8-bit user defined fields each time. The
256-bit key is program-only, and only can be used by IP Security Engine. User can use the 8-bit
user defined field for special purpose. The MTP also supports a LOCK function to protect the
content of programmed key and user defined field.
5.6.2 Features
Support MTP EPROM programming
256-bit Key and 8-bit user defined data field
Up to 15 times programming
Support LOCK function
5.7 External Bus Interface (EBI)
5.7.1 Overview
This chip supports External Bus Interface (EBI), which controls the access to the external memory
(SRAM) and External I/O devices. The EBI has up to 5 chip select signals to select different devices
with 10-bit address bus. It supports 8-bit and 16-bit external data bus width for each bank.
5.7.2 Features
Support SRAM and external I/O devices.
Support 8/16-bit data bus width.
Support 80 and 68 mode interface signals.
Support up to 5 chip selects for SRAM and external I/O devices.
Support programmable access cycle.
Support four 32-bit write buffers.
5.8 General Purpose I/O (GPIO)
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5.8.1 Overview
The NUC970 series have up to 148 General-Purpose I/O (GPIO) pins and can be shared with other
function pins depending on the chip configuration. These 148 pins are arranged in 10 ports named as
PA, PB, PC, PD, PE, PF, PG, PH, PI and PJ. PA, PB, PD, PE, PF, PG, PH and PI have 16 pins on
port, PC has 15 pins on port and PJ has 5 pins on port. Each of the 148 I/O pins is independent and
can be easily configured by user to meet various system configurations and design requirements.
After reset, all 148 I/O pins are configured in General-Purpose I/O Input mode.
When any of the 148 I/O pins used as a General-Purpose I/O, its I/O type can be configured by user
individually as Input or Output mode. In Input mode, the input buffer type could be selected as CMOS
input buffer or Schmitt trigger input buffer. Each I/O pin also equips a pull-up resistor (45 k ~ 82 k)
and a pull-down resistor (37 k ~ 91 k). The enable of pull-up/pull-down resistor is controllable.
5.8.2 Features
Support input and output mode.
Support CMOS and Schmitt trigger input buffer.
Support controllable pull-up and pull-down resistor.
Support both edge and level interrupt.
Support de-bounce circuit to filter the noise.
5.9 General DMA Controller (GDMA)
5.9.1 Overview
The chip has a two-channel general DMA controller with or without descriptor fetch operation, called
the GDMA. The two-channel GDMA performs the memory-to-memory data transfers without the CPU
intervention:
The on-chip GDMA can be started by the software. Software can also be used to restart the GDMA
operation after it has been stopped. The CPU can recognize the completion of a GDMA operation by
software polling or when it receives an internal GDMA interrupt. The GDMA controller can increment
source or destination address, decrement them as well, and conduct 8-bit (byte), 16-bit (half-word), or
32-bit (word) data transfers.
5.9.2 Features
AMBA AHB compliant
Descriptor and Non-Descriptor based function
Supports 8-data burst mode to boost performance
Provides support for external GDMA device
Demand mode speeds up external GDMA operations
5.10 Timer Controller (TMR)
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5.10.1 Overview
The general timer controller includes five channels, TIMER0, TIMER1, TIMER2, TIMER3, and
TIMER4, which allow user to easily implement a counting scheme or timing control for applications.
The timer can perform functions like frequency measurement, event counting, interval measurement,
pulse generation, delay timing, and so on. The timer possesses features such as adjustable
resolution, programmable counting period, and detailed information. The timer can generate an
interrupt signal upon timeout, or provide the current value of count during operation.
5.10.2 Features
Independent Clock Source for each Timer channel (TMRx_CLK, x= 0, 1, 2, 3, 4).
Five channels with a 24-bit up counter and an interrupt request each.
Internal 8-bit pre-scale counter.
Internal 24-bit up counter is readable through Timer Data Register, TDR (TMR_DR[23:0]).
Supports One-shot, Periodic, and Continuous operation mode.
Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit TCMP
setting value).
ꢀꢆ
(
)
Maximum counting time = ꢀꢁ ꢀꢁ ꢂ ꢃꢄꢅ ꢂ ꢃ ꢇ ꢈ , if TMRx_CLK = 12 MHz.
5.11 Enhance Timer Controller (ETMR)
5.11.1 Overview
This chip is equipped with four enhance timer modules including ETIMER0, ETIMER1, ETIMER2
and ETIMER3, which allow user to easily implement a counting scheme or timing control for
applications. The timer can perform functions like frequency measurement, event counting,
interval measurement, clock generation, delay timing, and so on. The timer can generate an
interrupt signal upon timeout, or provide the current value of count during operation.
5.11.2 Features
Independent Clock Enable Control for each Timer (ECLKetmr0, ECLKetmr1,
ECLKetmr2 and ECLKetmr3)
Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)
Counting cycle time = (1 / ECLKetmr) * (2^8) * (2^24)
Internal 8-bit pre-scale counter
Internal 24-bit up counter is readable through TDR (Timer Data Register)
Supports One-shot, Periodic, Output Toggle and Continuous Counting Operation
mode
Supports external pin capture for interval measurement
Supports external pin capture for timer counter reset
5.12 Pulse Width Modulation (PWM)
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5.12.1 Overview
This chip has one PWM controller, and it has 4 independent PWM outputs, CH0~CH3, or as 2
complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators.
Each PWM pair has one Prescaler, one clock divider, two clock selectors, two 16-bit PWM counters,
two 16-bit comparators, and one Dead-Zone generator. They are all driven by APB system clock
(PCLK) in chip. Each PWM channel can be used as a timer and issue interrupt independently.
Two channels PWM Timers in one pair share the same prescaler. The Clock divider provides each
PWM channel with 5 divided clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock
signal from clock divider which receives clock from 8-bit prescaler. The 16-bit down-counter in each
channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-
bit comparator compares PWM counter value with threshold value in register CMR (PWM_CMR[15:0])
loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM
clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is
enabled, two outputs of the corresponding PWM channel pair will be replaced by the output of Dead-
Zone generator. The Dead-Zone generator is used to control off-chip power device.
To prevent PWM driving output pin with unsteady waveform, 16-bit down-counter and 16-bit
comparator are implemented with double buffering feature. User can feel free to write data to counter
buffer register and comparator buffer register without generating glitch. When 16-bit down-counter
reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches
zero, if counter is set as periodic mode, it is reloaded automatically and start to generate next cycle.
User can set PWM counter as one-shot mode instead of periodic mode. If counter is set as one-shot
mode, counter will stop and generate one interrupt request when it reaches zero. The value of
comparator is used for pulse width modulation. The counter control logic changes the output level
when down-counter value matches the value of compare register.
5.12.2 Features
4 PWM channels with a 16-bit down counter and an interrupt each
2 complementary PWM pairs, (CH0, CH1), (CH2, CH3), with a programmable dead-zone
generator each
Internal 8-bit prescaler and a clock divider for each PWM paired channel
Independent clock source selection for each PWM channel
Internal 16-bit down counter and 16-bit comparator for each independent PWM channel
PWM down-counter supports One-shot or Periodic mode
5.13 Watchdog Timer (WDT)
5.13.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
5.13.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) and the time-out interval is 0.48828125 ms ~ 8 s if
WDT_CLK = 32.768 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
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Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset
delay period
Supports to force WDT enabled after chip powered on or reset by setting WDTON in
PWRON register
Supports WDT time-out wake-up function only if WDT clock source is selected as 32 kHz
5.14 Windowed Watchdog Timer (WWDT)
5.14.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified
window period to prevent software run to uncontrollable status by any unpredictable condition.
5.14.2 Features
6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the
WWDT time-out window period flexible.
Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of
WWDT counter.
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5.15 Real Time Clock (RTC)
5.15.1 Overview
The Real Time Clock (RTC) controller provides the real time clock and calendar information. The clock
source of RTC controller is from an external 32.768 kHz low-speed crystal which connected at pins
X32_IN and X32_OUT (refer to pin Description). The RTC controller provides the real time clock (hour,
minute, second) in RTC_TIME (RTC Time Loading Register) as well as calendar information (year,
month, day) in RTC_CAL (RTC Calendar Loading Register). It also offers RTC alarm function that
user can preset the alarm time in RTC_TALM (RTC Time Alarm Register) and alarm calendar in
RTC_CALM (RTC Calendar Alarm Register). The data format of RTC time and calendar message are
all expressed in BCD (Binary Coded Decimal) format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic RTC
Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second
which are selected by RTC_TICK (RTC_TICK[2:0] Time Tick Register). When real time and calendar
message in RTC_TIME and RTC_CAL are equal to alarm time and calendar settings in RTC_TALM
and RTC_CALM, the ALMIF (RTC_INTSTS [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC
alarm interrupt signal is generated if the ALMIEN (RTC_INTEN [0] Alarm Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or Power-
down mode if the corresponding interrupt enable bit (ALMIEN or TICKIEN) is set to 1 before chip
enters Idle or Power-down mode.
Real Time Clock (RTC) block can operate with independent power supply (RTC_VDD) while the
system power is off.
5.15.2 Features
Supports real time counter and calendar counter for RTC time and calendar check.
Supports time (hour, minute, second) and calendar (year, month, day) alarm and alarm
mask settings.
Selectable 12-hour or 24-hour time scale.
Supports Leap Year indication.
Supports Day of the Week counter.
Supports frequency compensation mechanism for 32.768 kHz clock source.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm match interrupt.
Supports chip wake-up from Idle or Power-down mode while alarm or relative alarm interrupt
is generated.
Supports 64 bytesꢂspareꢂregistersꢂtoꢂstoreꢂuser’sꢂimportantꢂinformation.
Supports power on/off control mechanism to control system core power.
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5.16 UART Interface Controller (UART)
This chip equips up to eleven channels of Universal Asynchronous Receiver/Transmitters (UART).
UART1/2/4/6/8/10 supports High-speed UART and UART0/3/5/7/9 perform Normal Speed UART,
besides, all the UART channels support flow control function. The UART controller also supports IrDA
(SIR), LIN Master/Slave and RS-485 function modes.
5.16.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on
data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the
CPU.
Each UART channel supports seven types of interrupts including (1). transmitter FIFO empty interrupt
(INT_THRE), (2). receiver threshold level reaching interrupt (INT_RDA), (3). line status interrupt (parity
error or framing error or break interrupt) (INT_RLS), (4). receiver buffer time-out interrupt (INT_TOUT),
(5). MODEM/Wake-up status interrupt (INT_MODEM), (6). Buffer error interrupt (INT_BUF_ERR), and
(7). LIN interrupt (INT_LIN).
The UART1/ 2/ 4/ 6/ 8/ 10 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver
FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU and the UART0/ 3/ 5/ 7/
9 are equipped 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU
can read the status of the UART at any time during the operation. The reported status information
includes the type and condition of the transfer operations being performed by the UART, as well as 4
error conditions (parity error, framing error, break interrupt and buffer error) probably occur while
receiving data.
The UART includes a programmable baud rate generator that is capable of dividing clock input by
divisors to produce the serial clock that transmitter and receiver need.
All of the controllers support auto-flow control function that uses two low-level signals, /CTS (clear-to-
send) and /RTS (request-to-send), to control the flow of data transfer between the UART and external
devices (ex: Modem). When auto-flow is enabled, the UART is not allowed to receive data until the
UART asserts /RTS to external device. When the number of bytes in the RX FIFO equals the value of
RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is de-asserted. The UART sends data out when UART
controller detects /CTS is asserted from external device. If a valid asserted /CTS is not detected the
UART controller will not send data out.
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (The IrDA mode is
selected by setting the (FUN_SEL(UA_FUN_SEL[2:0]) = 010) to select IrDA function). The SIR
specification defines a short-range infrared asynchronous serial transmission mode with one start bit,
8 data bits, and 1 stop bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block
contains an IrDA SIR Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it
cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a minimum
10ms transfer delay between transmission and reception. This delay feature must be implemented by
software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN mode
is selected by setting the (FUN_SEL(UA_FUN_SEL[2:0]) = 001) to select LIN mode. In LIN mode, one
start bit and 8-bit data format with 1-bit stop bit are required in accordance with the LIN standard.
For the NUC970 series, another alternate function of UART controllers is RS-485 9-bit mode function,
and direction control provided by RTS pin to implement the function by software. The RS-485 mode is
selected by setting the (FUN_SEL(UA_FUN_SEL[2:0]) = 011) to select RS-485 function. The RS-485
driver control is implemented using the RTS control signal from an asynchronous serial port to enable
the RS-485 driver. In RS-485 mode, many characteristics of the RX and TX are the same as UART.
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5.16.2 Features
Full duplex, asynchronous communications
Separate receive / transmit 64/16 bytes entry FIFO for data payloads
Supports hardware auto flow control/flow control function (CTS, RTS) and programmable
RTS flow control trigger level
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports CTS wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY(UA_TOR[15:8]) register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports LIN function mode
Supports RS-485 function mode
5.17 Smart Card Host Interface (SC)
5.17.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.17.2 Features
ISO-7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Up to two ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
A 24-bit and two 8-bit timers for Answer to Request (ATR) and waiting times
processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error number limiting function
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Supports hardware activation sequence, hardware warm reset sequence and
hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
Full duplex, asynchronous communications
Separates receiving / transmitting 4 bytes entry FIFO for data payloads
Supports programmable baud rate generator for each channel
Supports programmable receiver buffer trigger level
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting EGT (SC_EGT[7:0])
Programmable even, odd or no parity bit generation and detection
Programmable stop bit, 1- or 2- stop bit generation
5.18 I2C Synchronous Serial Interface Controller (I2C)
5.18.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Serial, 8-bit oriented bi-directional data transfers can be up to 100 KBit/s in Standard-mode, 400
KBit/s in the Fast-mode, or 3.4 Mbit/s in the High-speed mode. Only 100kbps and 400kbps modes
are supported directly in this chip.
Data transfer is synchronized to SCL signal between a Master and a Slave with byte-by-byte
basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB
being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled
during the high period of SCL; therefore, the SDA line may be changed only during the low period
of SCL and must be held stable during the high period of SCL. A transition on the SDA line while
SCL is high is interpreted as a command (START or STOP).
5.18.2 Features
Compatible with Philips I2C standard, support master mode
Multi Master Operation.
Clock stretching and wait state generation.
Provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer
Software programmable acknowledge bit.
Arbitration lost interrupt, with automatic transfer cancellation.
Start/Stop/Repeated Start/Acknowledge generation.
Start/Stop/Repeated Start detection.
Bus busy detection.
Supports 7 bit addressing mode.
Fully static synchronous design with one clock domain.
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Software mode I2C.
5.19 SPI Interface Controller (SPI)
5.19.1 Overview
The SPI is a synchronous serial interface performs a serial-to-parallel conversion on data characters
received from the peripheral, and a parallel-to-serial conversion on data characters received from
CPU. This interface can drive up to 2 external peripherals and is seen as the master.
5.19.2 Features
Support master mode
Full duplex synchronous serial data transfer
Variable length of transfer word up to 32 bits
Provide burst mode operation, transmit/receive can be executed up to four times in one transfer
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Support 2 slave/device select lines
Support dual IO and quad mode for SPI flash access
5.20 I2S Controller (I2S)
5.20.1 Overview
The I2S controller consists of I2S and PCM protocols to interface with external audio CODEC. The I2S
and PCM interface supports 8, 16, 18, 20 and 24-bit left/right precision in record and playback. When
operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each
left/right-channel sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding
zeros. When operating in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and
left-channel sample is stored in LSB of a 32-bit word.
The following are the property of the DMA.
When 16-bit precision, the DMA always 8-beat incrementing burst (FIFO_TH = 0) or 4-beat
incrementing burst (FIFO_TH = 1).
When 24/20/18-bit precision, the DMA always 16-beat incrementing burst (FIFO_TH = 0) or
8-beat incrementing burst (FIFO_TH = 1).
Always bus lock when 4-beat or 8-beat or 16-beat incrementing burst.
When reach eighth, quarter, middle and end address of destination address, a DMA_IRQ is
triggered to CPU automatically.
An AHB master port and an AHB slave port are offered in I2S controller.
5.20.2 Features
Support I2S interface record and playback
Left/right channel
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8, 16, 20, 24-bit data precision
Mater and slave mode
Support PCM interface record and playback
Two slots
8, 16, 20, 24-bit data precision
Master mode
Use DMA to playback and record data, with interrupt
Support two addresses for left/right channel data and different slots
5.21 Ethernet MAC Controller (EMAC)
5.21.1 Overview
This chip provides 2 Ethernet MAC Controller (EMAC) for Network application.
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM
function for recognizing Ethernet MAC addresses; Transmit-FIFO, Receive-FIFO, TX/RX state
machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status
controller.
The EMAC supports RMII (Reduced MII) interface to connect with external Ethernet PHY.
5.21.2 Features
Supports IEEE Std. 802.3 CSMA/CD protocol
Supports Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol
Supports both half and full duplex for 10 Mbps or 100 Mbps operation
Supports RMII interface
Supports MII Management function to control external Ethernet PHY
Supports pause and remote pause function for flow control
Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception
Supports 16 entries CAM function for Ethernet MAC address recognition
Supports Magic Packet recognition to wake system up from power-down mode
Supports 256 bytes transmit FIFO and 256 bytes receive FIFO
Supports DMA function
5.22 USB 2.0 Device Controller (USBD)
5.22.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control
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endpoint. These endpoints could be configured to BULK, INTERRUPT or ISO. The USB device
controller has a built-in DMA to relieve the load of CPU.
5.22.2 Features
USB Specification reversion 2.0 compliant
Supports 12 configurable endpoints in addition to Control Endpoint
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction
Three different operation modes of an in-endpoint － Auto Validation mode, Manual
Validation mode, Fly mode
Supports DMA operation
4096 Bytes Configurable RAM used as endpoint buffer
Supports Endpoint Maximum Packet Size up to 1024 bytes
5.23 USB Host Controller (USBH)
5.23.1 Overview
The Universal Serial Bus (USB) is a fast, bi-directional, isochronous, low-cost, dynamically attachable
serial interface standard intended for modem, scanners, PDAs, keyboards, mice, and digital imaging
devices. The USB is a 4-wire serial cable bus that supports serial data exchange between a Host
Controller and a network of peripheral devices. The attached peripherals share USB bandwidth
through a host-scheduled, token-based protocol. Peripherals may be attached, configured, used, and
detached, while the host and other peripherals continue operation (i.e. hot plug and unplug is
supported).
5.23.2 Features
Fully compliant with USB Revision 2.0 specification.
Enhanced Host Controller Interface (EHCI) Revision 1.0 compatible.
Open Host Controller Interface (OHCI) Revision 1.0 compatible.
Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices.
Supports Control, Bulk, Interrupt, Isochronous and Split transfers.
Integrated a port routing logic to route full/low speed device to OHCI controller.
Built-in DMA for real-time data transfer.
5.24 Controller Area Network (CAN)
5.24.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
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Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
5.24.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
5.25 Flash Memory Interface (FMI)
5.25.1 Overview
The Flash Memory Interface (FMI) of this Chip has DMA unit and FMI unit. The DMA unit provides a
DMA (Direct Memory Access) function for FMI to exchange data between system memory (ex.
SDRAM) and shared buffer (128 bytes), and the FMI unit control the interface of eMMC or NAND
flash. The interface controller can support eMMC and NAND-type flash and the FMI is cooperated with
DMAC to provide a fast data transfer between system memory and cards.
5.25.2 Features:
Support single DMA channel and address in non-word boundary.
Support hardware Scatter-Gather function.
Support 128Bytes shared buffer for data exchange between system memory and flash
device. (Separate into two 64 bytes ping-pong FIFO).
Support eMMC Flash device.
Supports SLC and MLC NAND type Flash.
Adjustable NAND page sizes. (512B+spare area, 2048B+spare area, 4096B+spare area
and 8192B+spare area).
Support up to 4bit/8bit/12bit/15bit/24bit hardware ECC calculation circuit to protect data
communication.
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Support programmable NAND timing cycle.
5.26 Secure Digital Host Controller (SDH)
5.26.1 Overview
The Secure-Digital Card Host Controller (SDH) equips DMAC unit and SD unit. The DMAC unit
provides a DMA (Direct Memory Access) function for SD to exchange data between system memory
and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC/SDIO. The SDH
controller supports SD/SDHC/SDIO card and cooperates with DMAC to provide a fast data transfer
between system memory and cards.
5.26.2 Features
Supports single DMA channel
Supports hardware Scatter-Gather functionality.
Supports 128 Bytes shared buffer for data exchange between system memory and cards.
Supports SD, SDHC and SDIO card.
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5.27 Cryptographic Accelerator (CRYPTO)
5.27.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator
(PRNG) core and supports AES, DES/TDES, SHA and HMAC algorithms.
The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation.
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB,
OFB, CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode.
The DES/TDES accelerator is an implementation fully compliant with the DES and Triple DES
encryption/decryption algorithm. The DES/TDES accelerator supports ECB, CBC, CFB, OFB, and
CTR mode.
The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224, SHA-256,
SHA-384, and SHA-512 and corresponding HMAC algorithms.
5.27.2 Features
PRNG
Supports 64 bits, 128 bits , 192 bits, and 256 bits random number generation
AES
Supports FIPS NIST 197
Supports SP800-38A and addendum
Supports 128, 192, and 256 bits key
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB , CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode
Supports key expander
DES
Supports FIPS 46-3
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB, and CTR mode
TDES
Supports FIPS NIST 800-67
Implemented according to the X9.52 standard
Supports two keys or three keys mode
Supports both encryption and decryption
Supports ECB, CBC, CFB, OFB, and CTR mode
SHA
Supports FIPS NIST 180, 180-2
Supports SHA-160, SHA-224, SHA-256, SHA-384, and SHA-512
HMAC
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Supports FIPS NIST 180, 180-2
Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-384, and
HMAC-SHA-512
5.28 2D Graphic Engine (GE2D)
5.28.1 Overview
A 32-bit 2D Graphics Engine (GE2D) is specially designed to improve the performance of graphic
processing. It can accelerate the operation of individual GUI functions such as BitBLTs and
Bresenham Line Draw to operate at all pixel depths including 8/16/32 bit-per-pixel.
A pixel is the smallest addressable screen element as defined in Microsoft Windows, and lines and
pictures are made up by a variety of pixels. GE2D is used to speed up graphic performance in pixel
data moving and line drawing, as well as to accelerate almost all computer graphic Boolean
operations by eliminating the CPU overhead. Meanwhile, the functions of rotation and scaling down
are implemented for some special applications. In image scaling down function, both programmable
horizontal and vertical N/M scaling down factors are provided for resizing the image. For the 2D
rotation, it can rotate left or right 45, 90 or 180 degrees, and also supports the flip/flop, mirror or up-
side-down pictures.
5.28.2 Features
Support 2D Bit Block Transfer (BitBLT) functions defined in Microsoft GDI
Support Host BLT
Support Pattern BLT
Support Color/Font Expanding BLT
Support Transparent BLT
Support Tile BLT
Support Block Move BLT
Support Copy File BLT
Support Color/Font Expansion
Support Rectangle Fill
Support RGB332/RGB565/RGB888 data format.
Support fore/background colors and all Microsoft 256 ternary raster-operation codes (ROP)
Support both inside and outside clipping function
Support alpha-blending for source/destination picture overlaying
Support fast Bresenham line drawing algorithm to draw solid/textured line
Support rectangular border and frame drawing
Support picture re-sizing
Support down-scaling from 1/255 to 254/255
Support up-scaling from 1 to 1.996 (1+254/255)
Support object rotation with different degree
Support L45 (45 degree left rotation) and L90 (90 degree left rotation)
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Support R45 (45 degree right rotation) and R90 (90 degree right rotation)
Support M180 (mirror/flop)
Support F180 (up-side-down (flip) and X180 (180 degree rotation)
5.29 JPEG Codec (JPEG)
5.29.1 Overview
The JPEG Codec supports Baseline Sequential Mode JPEG still image compression and
decompression that is fully compliant with ISO/IEC International Standard 10918-1 (T.81). The
features and capability of the JPEG codec are listed below.
5.29.2 Features
If image data input or output by planar format (PLANAR_ON (JITCR[15])= 1), the features are as
following:
Support to encode interleaved YCbCr 4:2:2/4:2:0 and gray-level (Y only) format image
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0/4:1:1 and gray-level (Y only) format
image
Support to decode YCbCr 4:2:2 transpose format
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards
Support arbitrary width and height image encode and decode (up to 8192x8192)
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function for encode and decode modes(Thumbnail/Primary)
Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
Support rotate function in encode mode
If image data input or output by packet format (PLANAR_ON (JITCR[15])= 0), the feature are as
following:
Support to encode interleaved YUYV format input image, output bitstream 4:2:2 and 4:2:0
format
Support to decode interleaved YCbCr 4:4:4/4:2:2/4:2:0 format image
Support decoded output image YUYV422, RGB555, RGB565, RGB888 format (ORDER= 1).
The encoded JPEG bit-stream format is fully compatible with JFIF and EXIF standards
Support arbitrary width and height image encode and decode(Primary Only)
Support three programmable quantization-tables
Support standard default Huffman-table and programmable Huffman-table for decode
Support arbitrarily 1X~8X image up-scaling function for encode mode
Support down-scaling function 1X~ 16X for Y422 and Y420, 1X~ 8X for Y444 for decode
mode
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Support specified window decode mode
Support quantization-table adjustment for bit-rate and quality control in encode mode
5.30 LCD Display Interface Controller (LCM)
5.30.1 Overview
The main purpose of Display Controller is used to display the video/image data to LCD device or
connect with external TV-encoder. The video/image data source may come from the image
sensor, JPEG decoder and the OSD pattern which have been stored in system memory
(SDRAM). The input data format of the display controller can be packet YUV422, packet YUV444,
packet RGB444, packet RGB565, packet RGB666, and packet RGB888. The OSD (On Screen
Display) function supports packet YUV422 and 8/16/24-bit direct-color mode. The LCD controller
supports both sync-type and MPU-type LCDM. This LCD Controller is a bus master and can
transfer display data from system memory (SDRAM) without CPU intervention.
5.30.2 Features
Input data format
YUV422, YUV444
RGB444, RGB565, RGB666, RGB888
Output format
YUV422, YUV444
RGB444, RGB565, RGB666, RGB888
Input size: Maximum size 1024 * 768
Image resize
Horizontal up-scaling 1~8X in fractional steps
Vertical up-scaling 1~8X in fractional steps
Convert full range YUV to CCIR601
Windowing support for three OSD graphic or text overlay
Support CCIR-656 (with header), CCIR-601(with hsync and vsync) 8/16-bit YUV data output
format to connect with external TV encoder
Support both sync-type and MPU-type LCM (with v-sync or not)
Support the 8/9/16/18/24-bit data output to connect with 80/68 series MPU type LCM module
The LCD Controller includes the following main functions：
Video post-processing
Display & overlay control
Video output control
Hardware cursor control
5.31 Capture Sensor Interface Controller (CAP)
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5.31.1 Overview
The Image Capture Interface is designed to capture image data from a sensor. After capturing or
fetching image data, it will process the image data, and then FIFO output them into frame buffer.
5.31.2 Feature
8-bit RGB565 sensor
8-bit YUV422 sensor
Supports CCIR601 YCbCr color range scale to full YUV color range
Supports 4 packaging format for packet data output: YUYV, Y only, RGB565, RGB555
Supports YUV422 planar data output
Supports the CROP function to crop input image to the required size for digital application.
Supports the down scaling function to scale input image to the required size for digital
application.
Supports frame rate control
Supports field detection and even/odd field skip mechanism
Supports packet output dual buffer control through hardware buffer controller
Supports negative/sepia/posterization color effect
Supports two independent capture interfaces
5.32 Analog to Digital Converter (ADC)
5.32.1 Overview
The NUC9xx series contains one 12-bit Successive Approximation Register analog-to-digital
converter (SAR A/D converter) with eight input channels. The A/D converter supports two
operation modes: 4-wire or 5-wire mode. The ADC is especially suitable to act as touch screen
controller. Battery voltage detection could be easily accomplished by the SAR ADC. It has keypad
interrupt signal generator.
5.32.2 Features
Resolution: 12-bit resolution.
DNL: +/-1.5 LSB, INL: +/-3 LSB.
Dual Data Rates: 800KSPS/160KSPS.
Analog Input Range: VREF to AGND, could be rail-to-rail.
Analog Supply: 2.7-3.6V.
Digital Supply: 1.2V.
8 Single-Ended Analog inputs.
Compatible with 4-wire or 5-wire Touch Screen Interface.
Touch Pressure Measurement for 4-wire touch screen application.
Direct Battery Measurement.
Keypad Interrupt Generator.
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Auto Power Down.
Low Power Consumption: 4850uW(@1MSPS) / 2170uW(@200KSPS), < 1uA
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6
ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN.
MAX
+1.26
+3.63
+1.90
+3.6
24
UNIT
V
Core DC Power Supply
-0.3
VCORE_VDDVCORE_VSS
I/O DC Power Supply
-0.3
V
VIO_VDDVIO_VSS
DDR I/O DC Power Supply
Input Voltage
-0.3
V
VDDR_VDDVDDR_VSS
VIN
1/tCLCL
TA
VIO_VSS-0.3
V
Oscillator Frequency
4
MHz
C
Operating Temperature
-40
+85
+150
200
TST
Storage Temperature
-55
C
IDD
Maximum Current into CORE_VDD
Maximum Current out of CORE_VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
ISS
200
20
30
IIO
200
200
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
Oct. 09 2018
Page 66 of 91
Rev 1.46
NUC970
6.2 DC Electrical Characteristics
6.2.1 NUC970 Series DC Electrical Characteristics
(VDD-VSS=3.3 V, TA = 25C, FOSC = 12 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
Core Operation voltage
I/O Operation Voltage
DDR I/O Operation Voltage
Power Ground
SYM.
VCORE_VDD
VIO_VDD
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.14
1.2
1.26
V
2.97
1.70
-0.3
2.97
0
3.3
1.8
3.63
1.90
V
V
V
V
V
VDDR_VDD
VSS
AVSS
Analog Operating Voltage
Analog Reference Voltage
AVDD
Vref
3.3
3.63
AVDD
ICORE_VDD1
IDDR_VDD1
IUSBPLL_VDD1
IUSB0_VDD1
185
50
15
35
35
100
165
45
15
35
35
100
3
mA Frequency of CPUCLK/DDR_CLK is
300/150 MHz.
mA
The functionalities enabled are GE2D,
LCD, JPEG, Cryptographic Engine,
EMAC, USBD, USBH and UART.
mA
Current Consumption of
Normal Operating Mode 1
mA
mA
uA
IUSB1_VDD1
IRTC_VDD1
ICORE_VDD2
mA Frequency of CPUCLK/DDR_CLK is
264/132 MHz.
IDDR_VDD2
mA
The functionalities enabled are GE2D,
LCD, JPEG, Cryptographic Engine,
EMAC, USBD, USBH and UART.
IUSBPLL_VDD2
IUSB0_VDD2
mA
Current Consumption of
Normal Operating Mode 2
mA
IUSB1_VDD2
mA
IRTC_VDD2
uA
ISTDBY_CORE_VDD
ISTDBY_DDR_VDD
ISTDBY_IO_VDD
ISTDBY_USB0_VDD
ISTDBY_USB1_VDD
ISTDBY_UPLL0_VDD
mA VCORE_VDD = 1.2V
mA VDDR_VDD = 1.8V
6
5
VIO_VDD = 3.3V
A
A
A
A
Current Consumption of
Deep Standby Mode
0
VUSB0_VDD = 3.3V
VUSB1_VDD = 3.3V
VUSBPLL0_VDD = 1.2V
0
5
Oct. 09 2018
Page 67 of 91
Rev 1.46
NUC970
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
5
MAX.
UNIT
A
ISTDBY_UPLL1_VDD
ISTDBY_AVDD
VUSBPLL1_VDD = 1.2V
25
VAVDD = 3.3V
A
ISTDBY_RTC_VDD
100
VRTC_VDD = 3.3V
A
Current Consumption of
Power Down Mode
IPWD_RTC_VDD
10
-
uA VRTC_VDD = 3.3V
Input Leakage Current
VIO_VDD = 3.63V
A
ILK1
-10
40
10
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ
0V < VIN < 3.6V
Input Leakage Current with
Pull-Down Resistor on
ILK2
-
-
160
VIN = VIO_VDD
A
A
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ
Input Leakage Current with
Pull-Up Resistor on
ILK3
-160
40
VIN = 0
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ
Input Low Voltage
VIL1
VIH1
VIL2
VIH2
VHY
-
-
0.8
-
V
V
V
V
V
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ (TTL input)
Input High Voltage
2.0
-
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ (TTL input)
Input Low Voltage
0.9
1.05
1.9
0.85
1.2
2.1
0.9
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ (Schmitt input)
Input High Voltage
1.65
0.75
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ (Schmitt input)
Hysteresis voltage
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ (Schmitt input)
Negative going threshold
(Schmitt input), nRESET
VILS
0.75
1.65
-
-
0.9
2.1
V
V
Positive going threshold
(Schmitt input), nRESET
VIHS
Source Current
ISR21
8
8
-
-
28
18
mA
mA
PA, PB, PC, PD, PE, PF, PH,
PI, PJ (Push-pull Mode)
Sink Current
ISK1
PA, PB, PC, PD, PE (Push-pull
Mode)
Oct. 09 2018
Page 68 of 91
Rev 1.46
NUC970
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input Pull-up Resistance
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ, USB0_ID,
SYS_nWAKEUP
kΩ
RPU
45
53
82
VIN = 0
Input Pull-down Resistance
kΩ
kΩ
RPD
37
45
49
53
91
85
VIN = VIO_VDD
PA, PB, PC, PD, PE, PF, PF,
PH, PI, PJ
Input Pull-up Resistance
nRESET
RRST
Note:
1. nRESET pin is a Schmitt trigger input.
2. Pins of PA, PB, PC, PD, PE, PF, PG, PH, PI and PJ can source a transition current when they are being externally
driven from 1 to 0. In the condition of VDD=3.63 V, the transition current reaches its maximum value when VIN approximates
to 1.5 V.
Oct. 09 2018
Page 69 of 91
Rev 1.46
NUC970
6.3 AC Electrical Characteristics
6.3.1 External 4~24 MHz High Speed Oscillator
Symbol
tCHCX
Parameter
Min
20
20
-
Typ
Max
-
Unit
ns
Test Condition
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
-
-
-
-
tCLCX
-
ns
tCLCH
10
10
ns
tCHCL
-
ns
tCLCL
tCLCH
tCLCX
90%
10%
0.7 VDD
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
Figure 66.3-1 External 4~24 MHz High Speed Oscillator Timing Diagram
Oct. 09 2018
Page 70 of 91
Rev 1.46
NUC970
6.3.2 External 4~24 MHz High Speed Crystal
Symbol
VꢀXT
TA
Parameter
Operation Voltage
Temperature
Min.
2.97
-40
4
Typ.
Max
3.63
85
Unit
V
Test Conditions
3.3
-
-
-
-
-
C
fꢀXT
Clock Frequency
24
MHz
6.3.2.1 Typical Crystal Application Circuits
Crystal
4M ~ 8M
ESR (ohm)
< 100
C1, C2
20 pf
14 pf
8 pf
8M ~ 18M
< 50
18 MHz ~ 24 MHz
< 30
XT1_IN
XT1_OUT
4~24 MHz
Crystal
C1
C2
Vss
Vss
Figure 6.3-2 Typical HXT Crystal Application Circuit
Oct. 09 2018
Page 71 of 91
Rev 1.46
NUC970
6.3.3 External 32.768 kHz Low Speed Crystal
Symbol
VLXT
TA
Parameter
Operation Voltage
Temperature
Min.
2.97
-40
-
Typ.
3.3
Max
3.63
85
Unit
V
Test Conditions
-
-
-
-
C
fLXT
Clock Frequency
32.768
-
kHz
6.3.3.1 Typical Crystal Application Circuits
Crystal
C1
C2
32.768 kHz
20pf
20pf
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Figure 6.3-3 Typical LXT Crystal Application Circuit
Oct. 09 2018
Page 72 of 91
Rev 1.46
NUC970
6.3.4 EBI Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AddressꢂSetupꢂTimeꢂtoꢂEBI_nCSꢂ
FallingꢂEdge
TtACS
0
-
7
TꢀCLK
-
EBI_nCSꢂSetupꢂTimeꢂtoꢂ
EBI_nWEꢂorꢂEBI_nOEꢂFallingꢂ
Edge
TtCOS
0
1
0
1
-
-
-
-
7
23
7
TꢀCLK
TꢀCLK
TꢀCLK
TꢀCLK
-
-
-
-
EBI_nWE or EBI_nOE Active Low
Time
TtACC
EBI_nCSꢂꢀoldꢂTimeꢂfromꢂ
EBI_nWEꢂorꢂEBI_nOEꢂRisingꢂ
Edge
TtCOꢀ
EBI_DATAꢂReadꢂSetupꢂTimeꢂtoꢂ
EBI_nOEꢂRisingꢂEdge
TSU_EBI_RD
-
Note: THCLK is the period of EBI’s operating clock.
EBI_ADDR[9:0]
TtACS
EBI_nCS[4:0]
TtCOS
TtCOH
EBI_nWE,
EBI_nBE[1:0]
TtACC+2
EBI_DATA[15:0
(Write)]
Valid Data
TtCOS
TtCOH
EBI_nOE
TtACC+2
TSU_EBI_RD
EBI_DATA[15:0
(Write)]
Valid Data
Figure 6.3-4 External Bus Interface Timing Diagram
Oct. 09 2018
Page 73 of 91
Rev 1.46
NUC970
6.3.5 I2C Interface Timing
100K
400K
Symbol
Parameter
Unit
Test Condition
Min
4.7
4
Max
Min
1.2
0.6
Max
TLOW
TꢀIGꢀ
I2C_SCLꢂLowꢂPeriod
I2C_SCLꢂꢀighꢂPeriod
-
-
-
-
us
-
-
us
RepeatedꢂSTARTꢂConditionꢂ
SetupꢂTime
TSU_STA
4.7
-
1.2
-
us
-
TꢀD_STA
TSU_STO
TBUF
STARTꢂConditionꢂꢀoldꢂTime
STOPꢂConditionꢂSetupꢂTime
BusꢂFreeꢂTime
4
4
-
0.6
0.6
1.2
0.3
0
-
-
us
us
us
us
us
ns
ns
-
-
-
-
-
-
-
-
-
4.7
2
-
TSU_DAT
TꢀD_DAT
TR
DataꢂSetupꢂTime
-
-
DataꢂꢀoldꢂTime
0
4.2
1000
300
0.8
300
300
I2C_SCL/I2C_SDAꢂRiseꢂTime
I2C_SCL/I2C_SDAꢂFallꢂTime
-
20+0.1Cb
TF
-
-
CapacitiveꢂLoadꢂforꢂEachꢂBusꢂ
Line
Cb
-
400
-
400
pF
-
Repeated
START
STOP
START
STOP
I2C_SDA
TBUF
TLOW
TR
TF
I2C_SCL
THIGH
THD_STA
TSU_STA
TSU_STO
TSU_DAT
THD_DAT
Figure 6.3-5 I2C Interface Timing Diagram
Oct. 09 2018
Page 74 of 91
Rev 1.46
NUC970
6.3.6 SPI Interface Timing
Symbol
TP_SPI_CLK
Tꢀ_SPI_CLK
TL_SPI_CLK
Parameter
Min
56
Typ
Max
Unit
ns
Test Condition
SPI_CLKꢂPeriod
SPI_CLKꢂꢀighꢂTime
SPI_CLK Low Time
-
-
-
-
-
-
-
-
-
28
ns
28
ns
SPI_DIꢂorꢂSPI_DATA[3:0]ꢂSetupꢂ
TimeꢂtoꢂSPI_CLKꢂActiveꢂEdge
TSU_SPI_DI
TꢀD_SPI_DI
TDLY_SPI_DO
TꢀD_SPI_DO
11
1
-
-
-
-
-
ns
ns
ns
ns
-
-
-
SPI_DIꢂorꢂSPI_DATA[3:0]ꢂꢀoldꢂ
TimeꢂfromꢂSPI_CLKꢂActiveꢂEdge
SPI_CLKꢂActiveꢂEdgeꢂtoꢂValidꢂ
SPI_DOꢂorꢂSPI_DATA[3:0]ꢂDelay
-
4
SPI_DOꢂorꢂSPI_DATA[3:0]ꢂꢀoldꢂ
TimeꢂfromꢂSPI_CLKꢂActiveꢂEdge
0.2
TP_SPI_CLK
TL_SPI_CLK
TH_SPI_CLK
SPIx_CLK
TL_SPI_CLK
TH_SPI_CLK
SPIx_DI
SPIx_DATA[3:0]
TSU_SPI_DI
THD_SPI_DI
SPIx_DO
SPIx_DATA[3:0]
TDLY_SPI_DO
THD_SPI_DO
Figure 6.3-6 SPI Interface Timing Diagram
Oct. 09 2018
Page 75 of 91
Rev 1.46
NUC970
6.3.7 I2S Interface Timing
Symbol
Parameter
Min
50
Typ
Max
Unit
ns
Test Condition
TP_I2S_BITCLK
Tꢀ_I2S_BITCLK
TL_I2S_BITCLK
I2S_BITCLKꢂPeriod
I2S_BITCLKꢂꢀighꢂTime
I2S_BITCLK Low Time
-
-
-
-
-
-
-
-
-
25
ns
25
ns
I2S_BITCLKꢂRisingꢂtoꢂValidꢂ
I2S_WSꢂorꢂI2S_DATAOꢂDelay
TDLY_I2S_DO
TꢀD_I2S_DO
TSU_I2S_DI
TꢀD_I2S_DI
-
-
-
-
-
6
-
ns
ns
ns
ns
-
I2S_WSꢂorꢂI2S_DATAOꢂꢀoldꢂTimeꢂ
fromꢂI2S_BITCLKꢂRising
1
5
3
I2S_DATAIꢂSetupꢂTimeꢂtoꢂ
I2S_BITCLKꢂRising
-
-
-
I2S_DATAIꢂꢀoldꢂTimeꢂfromꢂ
I2S_BITCLKꢂRising
-
TP_I2S_BITCLK
TL_I2S_BITCLK TH_I2S_BITCLK
I2S_BITCLK
I2S_DATAI
TSU_I2S_DI
THD_I2S_DI
I2S_WS
I2S_DATAO
TDLY_I2S_DO
THD_I2S_DO
Figure 6.3-7 I2S Interface Timing Diagram
Oct. 09 2018
Page 76 of 91
Rev 1.46
NUC970
6.3.8 Ethernet Interface Timing
6.3.8.1 RMII Interface Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
20.0ꢂ+/-ꢂ50ꢂ
TP_R II_REFCLK
R II_REFCLKꢂPeriod
-
-
ns
-
ppm
Tꢀ_R II_REFCLK
TL_R II_REFCLK
R II_REFCLKꢂꢀighꢂTime
8.0
8.0
10.0
10.0
12.0
12.0
ns
ns
-
-
RMII_REFCLK Low Time
R II_REFCLKꢂRisingꢂtoꢂValidꢂ
R II_TXEN,ꢂR II_TXDATA0ꢂandꢂ
R II_TXDATA1ꢂDelay
TDLY_R II_TX
TSU_R II_RX
TꢀD_R II_RX
-
-
-
-
10
-
ns
ns
ns
-
-
-
R II_CRSDV,ꢂR II_RXDATA0ꢂ
andꢂR II_RXDATA1ꢂSetupꢂTimeꢂtoꢂ
R II_REFCLKꢂRising
5
2
R II_CRSDV,ꢂR II_RXDATA0ꢂ
andꢂR II_RXDATA1ꢂꢀoldꢂTimeꢂ
fromꢂR II_REFCLKꢂRising
-
TP_RMII_REFCLK
TH_RMII_REFCLK TL_RMII_REFCLK
RMIIx_REFCLK
RMIIx_TXEN
RMIIx_TXDATA0
RMIIx_TXDATA1
TDLY_RMII_TX
RMIIx_CRSDV
RMIIx_RXDATA0
RMIIx_RXDATA1
TSU_RMII_RX
THD_RMII_RX
Figure 6.3-8 RMII Interface Timing Diagram
Oct. 09 2018
Page 77 of 91
Rev 1.46
NUC970
6.3.8.2 Ethernet PHY Management Interface Timing
Symbol
TP_R II_ DC
Tꢀ_R II_ DC
TL_R II_ DC
Parameter
Min
400
200
200
Typ
Max
Unit
ns
Test Condition
R II_ DCꢂPeriod
R II_ DCꢂꢀighꢂTime
RMII_MDC Low Time
-
-
-
-
-
-
-
-
-
ns
ns
R II_ DCꢂFallingꢂtoꢂValidꢂ
R II_ DIOꢂDelay
TDLY_R II_ DIOWR
TSU_R II_ DIORD
TꢀD_R II_ DIORD
-
-
-
-
10
-
ns
ns
ns
-
-
-
R II_ DIOꢂSetupꢂTimeꢂtoꢂ
R II_ DCꢂRising
10
10
R II_ DIOꢂꢀoldꢂTimeꢂfromꢂ
R II_ DCꢂRising
-
TP_RMII_MDC
TH_RMII_MDC
TL_RMII_MDC
RMIIx_MDC
RMIIx_MDIO
(Write)
TDLY_RMII_MDIOWR
RMIIx_MDIO
(Read)
TSU_RMII_MDIORD
THD_RMII_MDIORD
Figure 6.3-9 Ethernet PHY Management Interface Timing Diagram
Oct. 09 2018
Page 78 of 91
Rev 1.46
NUC970
6.3.9 NAND Interface Timing
Symbol
Tꢀ_NAND_nWE
TL_NAND_nWE
Parameter
Min
Typ
151
452
Max
Unit
ns
Test Condition
NAND_nWEꢂꢀighꢂTime
NAND_nWE Low Time
-
-
-
-
-
-
ns
NAND_nWEꢂFallingꢂtoꢂValidꢂ
NAND_DATAꢂDelay
TDLY_DATA_OUT
TꢀD_DATA_OUT
TSU_DATA_IN
-
153-
ns
Ns
ns
ns
-
-
-
-
NAND_DATAꢂꢀoldꢂTimeꢂfromꢂ
NAND_nWEꢂRising
7.53
153
7.53
-
-
-
-
-
-
NAND_DATAꢂSetupꢂTimeꢂtoꢂ
NAND_nREꢂRising
NAND_DATAꢂꢀoldꢂTimeꢂfromꢂ
NAND_nREꢂRising
TꢀD_DATA_IN
Note 1: NAND controller operating clock is 132 MHz and HI_WID (FMI_NANDTMCTL[15:8]) is 0x1.
Note 2: NAND controller operating clock is 132 MHz and LO_WID (FMI_NANDTMCTL[7:0]) is 0x5.
Note 2: NAND controller operating clock is 132 MHz
NAND_nCS0
NAND_nCS1
NAND_ALE
NAND_CLE
NAND_nWE
TL_NAND_nWE
TH_NAND_nWE
THD_DATA_OUT
TDLY_DATA_OUT
NAND_DATA[7:0]
(Write)
NAND_nRE
THD_DATA_IN
TSU_DATA_IN
NAND_DATA[7:0]
(Read)
Figure 6.3-10 NAND Interface Timing Diagram
Oct. 09 2018
Page 79 of 91
Rev 1.46
NUC970
6.3.10 SD Interface Timing
6.3.10.1Default Mode Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
SD_CLKꢂPeriod
TP_SD_CLK
40
-
-
ns
-
(DataꢂTransferꢂ ode)
SD_CLKꢂPeriodꢂ
TP_SD_CLK_ID
2,500
-
-
ns
(Identificationꢂ ode)
Tꢀ_SD_CLK
TL_SD_CLK
SD_CLKꢂꢀighꢂTime
-
-
20
20
-
-
ns
ns
-
-
SD_CLK Low Time
SD_DATAꢂSetupꢂTimeꢂto
SD_CLKꢂRising
TSU_SD_IN
5
5
-
-
-
-
-
-
ns
ns
ns
-
-
-
SD_DATAꢂꢀoldꢂTimeꢂfromꢂ
SD_CLKꢂRising
TꢀD_SD_IN
SD_CLKꢂFallingꢂto
TDLY_SD_OUT
14
ValidꢂSD_DATAꢂDelay
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 6.3-11 SD Interface Default Mode Timing Diagram
Oct. 09 2018
Page 80 of 91
Rev 1.46
NUC970
6.3.10.2High-Speed Mode Timing
Symbol
TP_SD_CLK
Tꢀ_SD_CLK
TL_SD_CLK
Parameter
Min
20
7
Typ
Max
Unit
ns
Test Condition
SD_CLKꢂPeriod
SD_CLKꢂꢀighꢂTime
SD_CLK Low Time
-
-
-
-
-
-
-
-
-
ns
7
ns
SD_DATAꢂSetupꢂTimeꢂto
SD_CLKꢂRising
TSU_SD_IN
6
2
-
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
SD_DATAꢂꢀoldꢂTimeꢂfromꢂ
SD_CLKꢂRising
TꢀD_SD_IN
SD_CLKꢂFallingꢂto
TDLY_SD_OUT
-
14
-
ValidꢂSD_DATAꢂDelay
SD_DATAꢂꢀoldꢂTimeꢂfromꢂ
SD_CLKꢂRising
TꢀD_SD_OUT
2.5
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 6.3-12 SD Interface High-Speed Mode Timing Diagram
Oct. 09 2018
Page 81 of 91
Rev 1.46
NUC970
6.3.11 LCD Display Interface Timing
6.3.11.1SYNC Type Timing
Symbol
TP_LCD_CLK
Tꢀ_LCD_CLK
TL_LCD_CLK
Parameter
Min
13
Typ
Max
Unit
ns
Test Condition
LCD_CLKꢂPeriod
LCD_CLKꢂꢀighꢂTime
LCD_CLK Low Time
-
-
-
-
-
-
-
-
-
6.5
6.5
ns
ns
LCD_CLKꢂRisingꢂtoꢂValidꢂ
LCD_ꢀSYNC,ꢂLCD_VSYNC,ꢂ
LCD_DENꢂandꢂLCD_DATAꢂDelay
TDLY_LCD_OUT
-
-
-
6
ns
-
-
LCD_ꢀSYNC,ꢂLCD_VSYNC,ꢂ
LCD_DENꢂandꢂLCD_DATAꢂꢀoldꢂ
TimeꢂfromꢂLCD_CLKꢂRising
TꢀD_LCD_OUT
1
-
ns
TP_LCD_CLK
TL_LCD_CLK
TH_LCD_CLK
LCD_CLK
LCD_HSYNC
LCD_VSYNC
LCD_DEN
LCD_DATA
TDLY_LCD_OUT
THD_LCD_OUT
Figure 6.3-13 LCD Display Interface SYNC Type Timing Diagram
Oct. 09 2018
Page 82 of 91
Rev 1.46
NUC970
6.3.12 Capture Sensor Interface Timing
Symbol
Parameter
Min
Typ
-
Max
Unit
ns
Test Condition
TP_VCAP_PCLK
Tꢀ_VCAP_PCLK
TL_VCAP_PCLK
VCAP_PCLKꢂPeriod
VCAP_PCLKꢂꢀighꢂTime
VCAP_PCLK Low Time
20
-
-
-
-
-
-
-
10.0
10.0
ns
-
ns
VCAP_ꢀSYNC,ꢂVCAP_VSYNC,ꢂ
VCAP_FIELDꢂandꢂVCAP_DATAꢂ
SetupꢂTimeꢂtoꢂVCAP_PCLKꢂRising
TSU_VCAP_IN
4
1
-
-
-
-
ns
-
-
VCAP_ꢀSYNC,ꢂVCAP_VSYNC,ꢂ
VCAP_FIELDꢂandꢂVCAP_DATAꢂ
ꢀoldꢂTimeꢂfromꢂVCAP_PCLKꢂ
Rising
TꢀD_VCAP_IN
ns
TP_VCAP_PCLK
TH_VCAP_PCLK TL_VCAP_PCLK
VCAP_PCLK
VCAP_HSYNC
VCAP_VSYNC
VCAP_FIELD
VCAP_DATA
TSU_VCAP_IN
THD_VCAP_IN
Figure 6.3-14 Capture Sensor Interface Timing Diagram
Oct. 09 2018
Page 83 of 91
Rev 1.46
NUC970
6.4 Analog Characteristics
6.4.1 12-bit SARADC
Symbol
-
Parameter
Resolution
Min.
Typ.
12
Max.
Unit
Test Conditions
-
-
-
-
-
-
-
-
-
-
-
-
Bit
DNL
INL
EO
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
±1
LSB VREF is external AVREF pin
LSB VREF is external AVREF pin
LSB VREF is external AVREF pin
LSB VREF is external AVREF pin
LSB VREF is external AVREF pin
-1.2
+3.7
-6.6
4.2
EG
Gain Error (Transfer Gain)
Absolute Error
EA
-
Monotonic
Guaranteed
FADC
TCAL
TS
ADC Clock Frequency
Calibration Time
Sample Time
-
-
3
16
-
MHz
Clock
Clock
Clock
k SPS
V
-
-
-
17
20
-
-
TADC
FS
Conversion Time
Sample Rate
-
800[1]
3.6
VAVDD
Supply Voltage
2.7
3.3
ADC channel 1 high speed
mode
IDDA1
Supply Current (Avg.)
Supply Current (Avg.)
-
-
1.2
1.0
mA
ADC channel 1 low speed
mode
IDDA2
IDDA3
ILK
mA
Supply Current (Avg.)
Leakage Current
-
-
0.4
mA
uA
V
0.1
-
VREF
VIN
Reference Voltage
Analog Input Voltage
Analog Input Impedance
Capacitance
2
0
-
-
VAVDD
VREF
2
-
-
V
MΩ
pF
RIN
CIN
-
25.6
Note:
1. ADC channel 1 supports sample rate higher than 160k SPS. Other ADC channels support sampel rate up to 160k SPS.
Oct. 09 2018
Page 84 of 91
Rev 1.46
NUC970
6.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR)
Symbol
VDD
Parameter
Min.
Typ.
3.3
21
Max
Unit
V
Test Conditions
Operation Voltage
Operating Current
2.0
3.63
-
-
IDD
uA
LVR_EN (SYS_LVRDCR[0]) = 0,
LVD_EN (SYS_LVRDCR[8]) = 0
ILK
TA
Quiescent Current
Temperature
-
0.1
0.5
uA
-40
-
85
-
C
V
V
V
V
V
V
2.295
2.475
2.115
0.045
0.045
0.045
2.55
2.75
2.35
0.05
0.05
0.05
2.805
3.025
2.585
0.055
0.055
0.055
LVD_SEL (SYS_LVRDCR[9]) = 0
VTꢀ_LVD
VTꢀ_LVR
VꢀY_LVD
VꢀY_LVR
LVD Threshold Voltage
LVR Threshold Voltage
LVD Hysteresis
LVD_SEL (SYS_LVRDCR[9]) = 1
-
LVD_SEL (SYS_LVRDCR[9]) = 0
LVD_SEL (SYS_LVRDCR[9]) = 1
-
LVR Hysteresis
Oct. 09 2018
Page 85 of 91
Rev 1.46
NUC970
6.4.3 3.3V Power-On Reset (POR33)
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
25
125
-
C
AVDDꢂrisingꢂfromꢂ0Vꢂtoꢂ
3.3V
VPOR
ResetꢂVoltage
-
-
1.83
5
-
-
V
IPOR33
Quiescent current
nA
Vin > reset voltage
6.4.4 1.2V Power-On Reset (POR12)
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
25
125
-
C
CORE_VDDꢂrisingꢂfromꢂ
0Vꢂtoꢂ1.2V
VPOR
ResetꢂVoltage
-
-
0.76
10
-
-
V
IPOR12
Quiescent current
nA
Vin > reset voltage
6.4.5 USB 2.0 PHY
6.4.5.1 Low/Full-Speed DC Electrical Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
VOL
OutputꢂLowꢂ(Driven)
-
-
0.3
V
1.5KꢂRPUꢂonꢂDPꢂtoꢂ3.6v
15KꢂRPDꢂonꢂDP,ꢂD ꢂtoꢂ
GND
VOꢀ
Outputꢂꢀighꢂ(Driven)
2.8
-
-
V
VDI
VC
VIL
DifferentialꢂInputꢂSensitivity
DifferentialꢂCommon- odeꢂRange
Single-EndedꢂInputꢂLow
Single-EndedꢂInputꢂꢀigh
Pull-UpꢂResistor
0.2
0.8
-
-
-
2.5
0.8
-
V
V
|VUSB0_DP–VUSB0_D |
-
-
V
-
-
VIꢀ
2.0
1.35
-
V
kΩ
RPU
1.5
1.65
kΩ
kΩ
Ω
RPD_DP
RPD_D
D+ꢂPull-DownꢂResistor
D-ꢂPull-DownꢂResistor
DriverꢂOutputꢂResistance
13.5
13.5
28
15
15
-
16.5
16.5
44
ZDRV
Steadyꢂstateꢂdrive[1]
Note:
1. Driverꢂoutputꢂresistanceꢂdoesn’tꢂincludeꢂseriesꢂresistor resistance.
6.4.5.2 High-Speed DC Electrical Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
ꢀighꢂSpeedꢂDifferentialꢂInputꢂ
SignalꢂLevel
VꢀSDI
150
-
-
mV
|VUSB0_DP–VUSB0_D |
Oct. 09 2018
Page 86 of 91
Rev 1.46
NUC970
ꢀighꢂSpeedꢂSquelchꢂDetectionꢂ
Threshold
VꢀSQ
100
125
150
500
mV
mV
|VUSB0_DP–VUSB0_D |
ꢀighꢂSpeedꢂCommonꢂ odeꢂ
VoltageꢂRange
VꢀSC
-50
-
VꢀSOꢀ
VꢀSOL
VCꢀIRPJ
VCꢀIRPK
ꢀighꢂSpeedꢂDataꢂSignalingꢂꢀigh
ꢀighꢂSpeedꢂDataꢂSignalingꢂLow
ChirpꢂJꢂLevel
300
-10
400
440
10
mV
mV
mV
mV
0
-
700
-900
1100
-500
ChirpꢂKꢂLevel
-
ꢀighꢂSpeedꢂDriverꢂOutputꢂ
Resistance
Ω
RꢀSDRV
40.5
45
49.5
6.4.5.3 USB Low-Speed Driver AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
CL=200pF,ꢂ10%ꢂtoꢂ90%ꢂofꢂ
|VOꢀ-VOL
TLRISE
RiseꢂTime
75
-
300
ns
|
CL=200pF,ꢂ10%ꢂtoꢂ90%ꢂofꢂ
|VOꢀ-VOL
TLFALL
FallꢂTime
75
-
-
300
2.0
ns
V
|
Excludingꢂtheꢂfirstꢂ
transitionꢂfromꢂidleꢂstate
VLCR
CrossoverꢂVoltage
1.3
6.4.5.4 USB Full-Speed Driver AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
CL=50pF,ꢂ10%ꢂtoꢂ90%ꢂofꢂ
VFRISE
RiseꢂTime
4
-
20
ns
|VOꢀ-VOL
|
CL=50pF,ꢂ10%ꢂtoꢂ90%ꢂofꢂ
|VOꢀ-VOL
VFFALL
FallꢂTime
4
-
-
20
ns
V
|
Excludingꢂtheꢂfirstꢂ
transitionꢂfromꢂidleꢂstate
VFCR
CrossoverꢂVoltage
1.3
2.0
6.4.5.5 USB High-Speed Driver AC Electrical Characteristics
Symbol
VꢀRISE
Parameter
Min
500
500
Typ
Max
900
900
Unit
ps
Test Condition
CL<10pF
ꢀighꢂSpeedꢂDriverꢂRiseꢂTime
ꢀighꢂSpeedꢂDriverꢂFallꢂTime
-
-
VꢀFALL
ps
CL<10pF
Oct. 09 2018
Page 87 of 91
Rev 1.46
NUC970
7
PACKAGE DIMENSIONS
7.1 216L LQFP (24x24x1.4mm footprint 2.0mm)
Oct. 09 2018
Page 88 of 91
Rev 1.46
NUC970
7.2 128L LQFP (14x14x1.4mm footprint 2.0mm)
Oct. 09 2018
Page 89 of 91
Rev 1.46
NUC970
8
REVISION HISTORY
Date
Revision
Description
2015, 05,12
2015, 07,13
2015, 07, 29
1.00
1.
1.
Preliminary version.
Revised part no. NUC976DK52Y and
NUC977DK52Y to be NUC976DK51Y and
NUC977DK51Y.
1.10
1.15
1.
Updated pin diagrams and pin descriptions.
1.
2.
Addded NUC978YOxxY part.
Modifying part selection guide, pin diagram, pin
description and updated QFN88 PKG dimension.
2015, 11, 25
1.20
3.
1.
NUC973 series EOL.
Removed NUC978YOxxY series related
information.
2015, 12,15
1.30
2016, 02, 23
2016, 12, 28
1.31
1.40
1.
1.
1.
ADC features and specification updated.
Added NUC975DKxxY part no.
Added NUC972DF71Y and NUC972DF51Y part
no.
2017, 07, 24
2017, 09, 30
1.41
1.42
1.
2.
3.
Added NUC97xDx61Y part no.
Added NUC978DKxxY part no.
Remove KPI. (software instead)
1.
2.
3.
Removed RMII0 support at pin-mux of PA group.
Updated pin diagram & pin description.
Removed NUC97xDK62Y
2017, 12, 07
2018, 04, 10
1.43
1.44
4. I/O type updated for power-on setting pins and
USB0_ID…
5. Added CAN part no. which NUC972DF71YC &
NUC972DF61YC for selection.
2018, 05, 14
2018, 10, 09
1.45
1.46
6. NUC970 series part no. updated in Q4, 2018
Oct. 09 2018
Page 90 of 91
Rev 1.46
NUC970
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Oct. 09 2018
Page 91 of 91
Rev 1.46
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