NUC980DF6YC [NUVOTON]
ARM926EJ-S Based 32-bit Microprocessor;
| 型号： | NUC980DF6YC |
| 厂家： | 
NUVOTON |
| 描述： | ARM926EJ-S Based 32-bit Microprocessor |
| 文件： | 总246页 (文件大小：3221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NUC980
ARM926EJ-S Based
32-bit Microprocessor
NUC980 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microprocessor based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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Table of Contents
1 GENERAL DESCRIPTION ..............................................................................9
2 FEATURES DESCRIPTION...........................................................................10
3 PARTS INFORMATION.................................................................................17
3.1 Package Type .............................................................................................................. 17
3.2 NUC980 Series Part Selection Guide ...................................................................... 18
3.3 NUC980 Series Naming Rule.................................................................................... 19
4 PIN CONFIGURATION ..................................................................................20
4.1 Pin Configuration......................................................................................................... 20
4.1.1 NUC980DRxxY LQFP64-EP Pin Diagram..................................................................20
4.1.2 NUC980DKxxYx LQFP128 Pin Diagram....................................................................21
4.1.3 NUC980DFxxYC LQFP216 Pin Diagram ...................................................................22
4.2 Pin Description............................................................................................................. 23
4.2.1 NUC980 Pin Description ...............................................................................................23
4.2.2 NUC980 Multi-function Summary Table......................................................................47
4.2.3 NUC980 Multi-function Summary Table Sorted by GPIO.........................................64
5 BLOCK DIAGRAM.........................................................................................84
5.1 NUC980 Series Block Diagram................................................................................. 84
6 FUNCTIONAL DESCRIPTION.......................................................................85
6.1 ARM® ARM926EJ-S CPU Core................................................................................. 85
6.1.1 Overview..........................................................................................................................85
6.2 System Manager ......................................................................................................... 86
6.2.1 Overview..........................................................................................................................86
6.2.2 System Reset..................................................................................................................86
6.2.3 System Power Distribution............................................................................................86
6.2.4 System Memory Map.....................................................................................................87
6.2.5 Power-On Setting...........................................................................................................91
6.2.6 Register Map...................................................................................................................93
6.2.7 Register Description.......................................................................................................95
6.3 Clock Controller ......................................................................................................... 142
6.3.1 Overview........................................................................................................................142
6.3.2 Features.........................................................................................................................142
6.3.3 Block Diagram...............................................................................................................143
6.3.4 Functional Description .................................................................................................150
6.3.5 Registers Map...............................................................................................................152
6.3.6 Register Description.....................................................................................................153
6.4 Advanced Interrpt Controller.................................................................................... 180
6.4.1 Overview........................................................................................................................180
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6.4.2 Features.........................................................................................................................180
6.5 SDRAM Interface Controller .................................................................................... 181
6.5.1 Overview........................................................................................................................181
6.5.2 Features.........................................................................................................................181
6.6 External Bus Interface .............................................................................................. 182
6.6.1 Overview........................................................................................................................182
6.6.2 Features.........................................................................................................................182
6.7 General Purpose I/O................................................................................................. 183
6.7.1 Overview........................................................................................................................183
6.7.2 Features.........................................................................................................................183
6.8 Peripheral DMA Controller ....................................................................................... 184
6.8.1 Overview........................................................................................................................184
6.8.2 Features.........................................................................................................................184
6.9 Timer Controller (TMR)............................................................................................. 185
6.9.1 Overview........................................................................................................................185
6.9.2 Features.........................................................................................................................185
6.10 Pulse Width Modulation (PWM) ........................................................................ 186
6.10.1Overview........................................................................................................................186
6.10.2Features.........................................................................................................................186
6.11 Watchdog Timer................................................................................................... 187
6.11.1Overview........................................................................................................................187
6.11.2Features.........................................................................................................................187
6.12 Windowed Watchdog Timer (WWDT)............................................................... 188
6.12.1Overview........................................................................................................................188
6.12.2Features.........................................................................................................................188
6.13 Real Time Clock (RTC)....................................................................................... 189
6.13.1Overview........................................................................................................................189
6.13.2Features.........................................................................................................................189
6.14 UART Interface Controller (UART) ................................................................... 190
6.14.1Overview........................................................................................................................190
6.14.2Features.........................................................................................................................190
6.15 Smart Card Host Interface ................................................................................. 191
6.15.1Overview........................................................................................................................191
6.15.2Features.........................................................................................................................191
6.16 I²C Serial Interface Controller............................................................................ 192
6.16.1Overview........................................................................................................................192
6.16.2Features.........................................................................................................................192
6.17 Serial Peripheral Interface (SPI) ....................................................................... 193
6.17.1Overview........................................................................................................................193
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6.17.2Features.........................................................................................................................193
6.18 Quad Serial Peripheral Interface (QSPI).......................................................... 194
6.18.1Overview........................................................................................................................194
6.18.2Features.........................................................................................................................194
6.19 I²S Controller (I²S) ............................................................................................... 195
6.19.1Overview........................................................................................................................195
6.19.2Features.........................................................................................................................195
6.20 Ethernet MAC Controller (EMAC)..................................................................... 196
6.20.1Overview........................................................................................................................196
6.20.2Features.........................................................................................................................196
6.21 High Speed USB 2.0 Device Controller (HSUSBD)....................................... 197
6.21.1Overview........................................................................................................................197
6.21.2Features.........................................................................................................................197
6.22 USB 2.0 Host Controller (USBH) ...................................................................... 198
6.22.1Overview........................................................................................................................198
6.22.2Features.........................................................................................................................198
6.23 Controller Area Network (CAN) ......................................................................... 199
6.23.1Overview........................................................................................................................199
6.23.2Features.........................................................................................................................199
6.24 Flash Memory Interface (FMI) ........................................................................... 200
6.24.1Overview........................................................................................................................200
6.24.2Features.........................................................................................................................200
6.25 Secure Digital Host Controller (SDH)............................................................... 201
6.25.1Overview........................................................................................................................201
6.25.2Features.........................................................................................................................201
6.26 Cryptographic Accelerator (CRYPTO).............................................................. 202
6.26.1Overview........................................................................................................................202
6.26.2Features.........................................................................................................................202
6.27 Capture Sensor Interface Controller (CAP)..................................................... 204
6.27.1Overview........................................................................................................................204
6.27.2Features.........................................................................................................................204
6.28 Analog to Digitial Converter (ADC)................................................................... 205
6.28.1Overview........................................................................................................................205
6.28.2Features.........................................................................................................................205
7 ELECTRICAL CHARACTERISTICS............................................................206
7.1 Absolute Maximum Ratings..................................................................................... 206
7.2 DC Electrical Characteristics................................................................................... 207
7.2.1 NUC980 Series DC Electrical Characteristics .........................................................207
7.2.2 NUC980 Series GPIO Characteristics.......................................................................209
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7.3 AC Electrical Characteristics ................................................................................... 210
7.3.1 External 12MHz High Speed Crystal.........................................................................210
7.3.2 External 32.768 kHz Low Speed Crystal ..................................................................211
7.3.3 Power Sequence & nRESET Timing .........................................................................212
7.3.4 nRESET PIN characteristics.......................................................................................214
7.3.5 PLL characteristics.......................................................................................................214
7.3.6 EBI Timing .....................................................................................................................215
7.3.7 I2C Interface Timing.....................................................................................................216
7.3.8 SPI Interface Timing.....................................................................................................217
7.3.9 QSPI Interface Timing..................................................................................................220
7.3.10I2S Interface Timing.....................................................................................................223
7.3.11Ethernet Interface Timing............................................................................................224
7.3.12NAND Interface Timing................................................................................................226
7.3.13SD Interface Timing......................................................................................................227
7.3.14Capture Sensor Interface Timing ...............................................................................229
7.4 Analog Characteristics.............................................................................................. 230
7.4.1 12-bit SARADC.............................................................................................................230
7.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR).................................231
7.4.3 3.3V Power-On Reset (POR33).................................................................................231
7.4.4 1.2V Power-On Reset (POR12).................................................................................231
7.4.5 USB 2.0 PHY ................................................................................................................232
8 PACKAGE DIMENSIONS............................................................................234
8.1 LQFP216 (24x24x1.4mm footprint 2.0mm)........................................................... 234
8.2 LQFP128 (14x14x1.4mm footprint 2.0mm)........................................................... 235
8.3 LQFP64-EP (10x10x1.4mm footprint 2.0 mm) ..................................................... 236
8.4 Thermal Characteristics............................................................................................ 238
8.4.1 Thermal Performance of LQFP under Forced Convection.....................................238
8.4.2 Thermal Performance Terminology............................................................................238
8.4.3 Simulation Conditions..................................................................................................239
8.5 PCB Reflow Profile Suggestion............................................................................... 240
8.5.1 Profile Setting Consideration..................................................................................240
8.5.2 Profile Suggestion .....................................................................................................241
8.6 PKG Baking and Vacuumed .................................................................................... 242
9 ABBREVIATIONS........................................................................................243
10REVISION HISTORY ...................................................................................245
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LIST OF FIGURES
Figure 3-1 NUC980 Series Package Type..................................................................................... 17
Figure 3.3-1 NUC980 Series Selection Code ................................................................................ 19
Figure 4.1-1 NUC980DRxxY LQFP 64-pin with EX-PAD Diagram................................................ 20
Figure 4.1-2 NUC980DKxxYx LQFP 128-pin Diagram.................................................................. 21
Figure 4.1-3 NUC980DFxxYC LQFP 216-pin Diagram ................................................................. 22
Figure 5.1-1 NUC980 Series Block Diagram ................................................................................. 84
Figure 6.2-1 NUC980 Series Power Distribution Diagram............................................................. 87
Figure 6.2-2 NUC980 System Memory Map Diagram ................................................................... 88
Figure 6.3-1 Clock Controller Block Diagram............................................................................... 143
Figure 6.3-2 ADC Controller Clock Divider Block Diagram.......................................................... 144
Figure 6.3-3 SD Card Host Controller Clock Divider Block Diagram........................................... 144
Figure 6.3-4 Timer Clock Divider Clock Diagram......................................................................... 145
Figure 6.3-5 Ethernet MAC Controller Clock Divider Block Diagram........................................... 145
Figure 6.3-6 I2S Controller Clock Divider Block Diagram............................................................. 145
Figure 6.3-7 Reference Clock Output Divider Block Diagram ..................................................... 146
Figure 6.3-8 Smart Card Host Controller Clock Divider Block Diagram ...................................... 146
Figure 6.3-9 CMOS Sensor Controller Divider Block Diagram.................................................... 146
Figure 6.3-10 UART Clock Divider Block Diagram ...................................................................... 147
Figure 6.3-11 USB 1.1 Host Controller 48 MHz Clock Divider Block Diagram............................ 147
Figure 6.3-12 Watchdog Timer Clock Divider Block Diagram ..................................................... 147
Figure 6.3-13 Windowed Watchdog Timer Clock Divider Block Diagram ................................... 148
Figure 6.3-14 CPU_HCLK Clock Generator Block Diagram........................................................ 149
Figure 7.3-1 Typical HXT Crystal Application Circuit................................................................... 210
Figure 7.3-2 Typical LXT Crystal Application Circuit.................................................................... 211
Figure 7.3-3 Power up Sequence & nRESET timing Case 1....................................................... 212
Figure 7.3-4 Power up Sequence & nRESET timing Case 2....................................................... 213
Figure 7.3-5 External Bus Interface Timing Diagram................................................................... 215
Figure 7.3-6 I2C Interface Timing Diagram.................................................................................. 216
Figure 7.3-7 SPI Master Mode Timing Diagram .......................................................................... 217
Figure 7.3-8 SPI Slave Mode Timing Diagram ............................................................................ 219
Figure 7.3-9 QSPI Master Mode Timing Diagram........................................................................ 220
Figure 7.3-10 QSPI Slave Mode Timing Diagram........................................................................ 222
Figure 7.3-11 I2S Interface Timing Diagram................................................................................ 223
Figure 7.3-12 RMII Interface Timing Diagram.............................................................................. 224
Figure 7.3-13 Ethernet PHY Management Interface Timing Diagram......................................... 225
Figure 7.3-14 NAND Interface Timing Diagram........................................................................... 226
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Figure 7.3-15 SD Interface Default Mode Timing Diagram.......................................................... 227
Figure 7.3-16 SD Interface High-Speed Mode Timing Diagram.................................................. 228
Figure 7.3-17 Capture Sensor Interface Timing Diagram............................................................ 229
Figure 8.4-1 Junction to Ambient Thermal Resistance................................................................ 238
Figure 8.4-2 Junction to Case Thermal Resistance..................................................................... 239
Figure 8.5-1 PCB Reflow Profile Diagram ................................................................................... 240
Figure 8.5-2 Profile Suggestion for NUC980 series..................................................................... 241
Figure 8.6-1 Cautions for PKG Baking......................................................................................... 242
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LIST OF TABLES
Table 3.2-1 NUC980 Series Part Selection Guide......................................................................... 18
Table 6.2-1 Address Space Assignments for On-Chip Controllers................................................ 90
Table 6.2-2 Power-On Setting Bit Description ............................................................................... 92
Table 6.3-1 The Mapping of N and Fpfd Range ............................................................................ 178
Table 7.3-1 EBI Characteristics ................................................................................................... 215
Table 7.3-2 I2C Interface Characteristics ..................................................................................... 216
Table 7.3-3 SPI Master Mode Characteristics ............................................................................. 217
Table 7.3-4 SPI Slave Mode Characteristics ............................................................................... 218
Table 7.3-5 QSPI Master Mode Characteristics .......................................................................... 220
Table 7.3-6 QSPI Slave Mode Characteristics ............................................................................ 221
Table 7.3-7 I2S Interface Characteristics ..................................................................................... 223
Table 7.3-8 RMII Interface Characteristics .................................................................................. 224
Table 7.3-9 Ethernet PHY Management Interface Characteristics.............................................. 225
Table 7.3-10 NAND Interface Characteristics.............................................................................. 226
Table 7.3-11 SD Interface Default Mode Characteristics ............................................................ 227
Table 7.3-12 SD Interface High-Speed Mode Characteristics..................................................... 228
Table 7.3-13 Capture Sensor Interface Characteristics............................................................... 229
Table 8.4-1 Thermal Performance of LQFP................................................................................. 238
Table 8.4-2 Thermal Characteristics Simulation Conditions........................................................ 239
Table 8.5-1 PCB Reflow Profile Parameters................................................................................ 240
Table 8.5-2 Profile Parameters for NUC980 Series..................................................................... 241
Table 9‑1 List of Abbreviations.................................................................................................... 244
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1 GENERAL DESCRIPTION
The NUC980 series 32-bit microprocessor is powered by the Arm926EJ-S™ processor core with 16
KB I-cache, 16 KB D-cache and MMU running up to 300 MHz. Its SDRAM interface supports
SDR/DDR/DDR2/LPDDR type SDRAM running up to 150 MHz. The NUC980 series supports built-in
16KB embedded SRAM and 16.5 KB IBR (Internal Boot ROM) for booting from USB, NAND,
SD/eMMC and SPI Flash, and industrial operating temperature from -40°C to 85°C. In addition, the
NUC980 series provides built-in SDRAM in LQFP package to ease PCB design and reduce the BOM
cost.
The NUC980 series is equipped with a large number of high speed digital peripherals, such as two
10/100 Mbps Ethernet MAC supporting RMII, a USB 2.0 high speed host/device, a USB 2.0 high
speed host controller, up to six USB 1.1 host lite interfaces, two CMOS sensor interfaces supporting
CCIR601 and CCIR656 type sensor, two SD interfaces supporting SD/SDHC/SDIO card, a NAND
Flash interface supporting SLC and MLC type NAND Flash, an I2S interface supporting I2S and PCM
protocol, Also the NUC980 series offers a built-in hardware cryptography accelerator that supports
RSA, ECC, AES, SHA, HMAC and a random number generator (RNG).
The NUC980 series provides up to ten UART interfaces, two ISO-7816-3 interfaces, a Quad-SPI
interface, two SPI interfaces, up to four I2C interfaces, four CAN 2.0B interfaces, eight channels PWM
output, eight channels 12-bit SAR ADC, six 32-bit timers, WDT (Watchdog Timer), WWDT( Window
Watchdog Timer), 32.768 kHz XTL and RTC (Real Time Clock). The NUC980 series also supports
two 10-channel peripheral DMA (PDMA) for automatic data transfer between memories and
peripherals.
Key Features
Applications
- 300 MHz ARM® ARM926EJ-S™ MPU with
16 KB I-cache, 16 KB D-cache
- Smart Home gateway
- Fingerprint Machine.
- Power concentrator
- Data Collector
- Memory Manager Unit (MMU)
- Built-in 128 MB/64MB /16MB SDRAM Memory
in LQFP package
- Smart Home Appliance
- Serial server
- Supports booting from SPI ROM/SPI NAND
Flash/NAND/eMMC/SD Card and USB device
- 2D/1D Barcode reader
- Barcode printer
- Supports up to 100MHz Quad-SPI
- Dual Ethernet MAC
- Power Distribution Unit
- Ethernet Industrial Control
- SNMP Card
- Four CAN 2.0B interfaces
- Six USB FS Lite hosts
- Two USB High speed hosts
- One USB High speed device
- Two CCIR656/601 Camera interfaces
- Ethernet RTU/ DTU
- Supports PRNG, AES256, SHA, ECC, and
RAS2048
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2 FEATURES DESCRIPTION
Core And System
Factory pre-loaded 16.5 KB mask ROM supporting four booting modes
– Boot from USB
Boot Loader
– Boot from SD/eMMC
– Boot from NAND Flash
– Boot from SPI Flash (SPI-NOR/SPI-NAND)
Arm926EJ-S™ processor core running up to 300 MHz
Built-in 16 KB instruction cache and 16 KB data cache
Built-in Memory Management Unit (MMU)
Supports JTAG debug interface
Arm926EJ-S™
Up to 64 interrupt sources including 4 external interrupts.
Configurable normal (IRQ) or fast interrupt mode (FIQ).
Configurable 8-level interrupt priority scheme.
Advanced Interrupt
Controller
Low Voltage Detect
(LVD)
Two-level LVD with low voltage detect interrupt. (2.8V/2.6V)
LVR with 2.4V threshold voltage level.
Low Voltage Reset
(LVR)
Memories
Built-in 128MB/ 64MB/ 16MB SDRAM Memory in LQFP package
Clock speed up to 150 MHz
SDRAM
Supports 16-bit data width
Up to 16 KB on-chip SRAM
Byte-, half-word- and word-access
PDMA operation
SRAM
Two sets of PDMA with ten independent and configurable channels for
automatic data transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using Scatter-Gather
Transfer mode
Peripheral DMA (PDMA)
Stride function for rectangle image data movement
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Incremental or fixed source and destination address
Clocks
12 MHz High-speed eXternal crystal oscillator (HXT) for precise timing
operation
External Clock Source
32.7688 kHz Low-speed eXternal crystal oscillator (LXT) for RTC function and
low-power system operation
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Two on-chip PLL up to 500 MHz on-chip PLL, sourced from HXT, allows CPU
operation up to the maximim CPU frequency without the need for a high-
frequency crystal
Internal Clock Source
Real-Time Clock with a separate power domain (VBAT33)
The RTC clock source includes Low-speed external crystal oscillator (LXT)
The RTC block includes 64 bytes backup registers
Able to wake up CPU
Supports ±5ppm within 5 seconds software clock accuracy compensation
Supports Alarm registers (second, minute, hour, day, month, year)
Supports RTC Time Tick and Alarm Match interrupt
Selectable 12-hour or 24-hour mode
Real-Time Clock (RTC)
Automatic leap year recognition
Supports 1 Hz clock to be Timer capture source for calibration
Timers
Six sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter
from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pins
32-bit Timer
Supports external capture pin for interval measurement and resetting 24-bit up
counter
Supports internal capture source from RTC 1 Hz clock for interval
measurement resetting 24-bit up counter
Supports chip wake-up function, if a timer interrupt signal is generated
Eight 16-bit down-count counters with four 8-bit prescalar for eight PWM output
channels.
PWM (PWM)
Supports complementary mode for 4 complementary paired PWM output
channels
18-bit free running up counter for WDT time-out interval
Supports multiple clock sources from HXT, HXT/512 (default selection),
PCLK2/4096 or LXT with 8 selectable time-out period
Able to wake up system from Power-down or Idle mode
Time-out event to trigger interrupt or reset system
Watchdog
Supports four WDT reset delay periods, including 1026, 130, 18 or 3
WDT_CLK reset delay period
Configured to force WDT enabled on chip power-on or reset.
Clock sourced from HXT, HXT/512 (default selection), PCLK2/4096 or LXT; the
window set by 6-bit counter with 11-bit prescale
Window Watchdog
Suspended in Idle/Power-down mode
Analog Interfaces
One 12-bit, 9-ch 200k SPS SAR ADC with up to 8 single-ended input channels;
10-bit accuracy is guaranteed.
Analog-to-Digital
Converter (ADC)
One internal channels for band-gap VBG input.
Supports external VREF pin.
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Communication Interfaces
10 sets of UARTs with up to 17.45 MHz baud rate.
Auto-Baud Rate measurement and baud rate compensation function.
Supports low power UART (LPUART): baud rate clock from LXT(32.768 kHz)
with 9600bps in Power-down mode even system clock is stopped.
16-byte FIFOs with programmable level trigger
Auto flow control ( nCTS and nRTS)
Supports IrDA (SIR) function
Supports LIN function on UART0 and UART1
Supports RS-485 9-bit mode and direction control
Low-power UART
Supports nCTS, incoming data, Received Data FIFO reached threshold and
RS-485 Address Match (AAD mode) wake-up function in idle mode.
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports wake-up function
8-bit receiver FIFO time-out detection function
Supports break error, frame error, parity error and receive/transmit FIFO
overflow detection function
PDMA operation.
Two sets of ISO-7816-3 which are compliant with ISO-7816-3 T=0, T=1
Supports full duplex UART function.
4-byte FIFOs with programmable level trigger
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8 bit time-out counters for Answer to Request (ATR) and
waiting times processing
Smart Card Interface
Auto inverse convention function
Stop clock level and clock stop (clock keep) function
Transmitter and receiver error retry function
Supports hardware activation, deactivation and warm reset sequence process
Supports hardware auto deactivation sequence after card removal.
Four sets of I2C devices with Master/Slave mode.
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode
plus (1 Mbps)
Supports 10 bits mode
I2C
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports SMBus and PMBus
Supports multi-address power-down wake-up function
PDMA operation
One set of SPI Quad controller with Master/Slave mode, up to 96 MHz at
2.7V~3.6V stsyem voltage.
Quad SPI
Supports Dual and Quad I/O Transfer mode
Supports one/two data channel half-duplex transfer
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Supports receive-only mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wired, no slave select signal, bi-direction interface
PDMA operation.
Up to two sets of SPI controllers with Master/Slave mode.
SPI provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and
receive FIFO buffers.
Able to communicate at up to 96 Mbit/s
Configurable bit length of a transfer word from 8 to 32-bit.
MSB first or LSB first transfer sequence.
Byte reorder function.
SPI
Supports Byte or Word Suspend mode.
Supports one data channel half-duplex transfer.
Supports receive-only mode.
PDMA operation.
One set of I2S controller with I2S protocol and PCM protocol.
Supports mono and stereo audio data with 8-, 16- and 24-bit word sizes.
Four 8-level 24-bit FIFO data buffers for left/right channel record and left/right
playback.
Built-in DMA function
Supports 2 buffer address for left/right channel and 2 slots data transfer.
I2S Mode
I2S
Supports record and playback.
Supports master and slave mode.
Supports Philips standard and MSB-justified data format.
PCM Mode
Supports record and playback.
Supports master mode.
Supports PCM standard data format.
Four CAN 2.0B interfaces
Each supports 32 Message Objects; each Message Object has its own
identifier mask.
Controller Area Network
(CAN)
Programmable FIFO mode (concatenation of Message Object).
Disabled Automatic Re-transmission mode for Time Triggered CAN
applications.
Supports power-down wake-up function.
Two sets of Secure Digital Host Controllers, compliant with SD Memory Card
Specification Version 2.0.
Secure Digital Host
Controller (SDHC)
Supports 50 MHz to achieve 200 Mbps at 3.3V operation.
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Supports dedicated DMA master with Scatter-Gather function to accelerate the
data transfer between system memory and SD/SDHC/SDIO card.
Supports SLC and MLC type NAND Flash device.
Supports 2KB, 4KB and 8KB page size NAND Flash device.
8-bit data width.
NAND Flash Controller
Supports ECC8, ECC12 and ECC24 BCH algorithm with ECC code
generation, error detection and error correction.
Supports dedicated DMA master with Scatter-Gather function to accelerate the
data transfer between system memory and NAND Flash.
Supports up to three memory banks with individual adjustment of timing
parameter.
Each bank supports dedicated external chip select pin with polarity control and
up to 1 MB addressing space.
8-/16-bit data width.
External Bus Interface
(EBI)
Configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R).
Supports address bus and data bus separate mode.
Supports LCD interface i80 mode.
PDMA operation.
Supports four I/O modes: Bi-direction, Push-Pull output, Open-Drain output and
Input only with high impendence mode.
Selectable TTL/Schmitt trigger input.
GPIO
Configured as interrupt source with edge/level trigger setting.
Supports independent pull-up/pull-down control.
Supports 5V-tolerance function except analog I/O. (Except PB.0 ~ 7; All USB
High Speed PIN.)
Advanced Connectivity
Compliant with USB Revision 2.0 Specification.
Compatible with OHCI (Open Host Controller Interface) Revision 1.0.
Supports full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt, Isochronous and Split transfers.
Supports an integrated Root Hub.
USB 1.1 Host Lite
Up to six USB Host Lite ports.
Built-in DMA.
Apply to USB dongle devices or USB cable length is limited to less than 1
meter.
USB 2.0 High Speed Host/Device
One set of on-chip USB 2.0 high speed dual role transceiver configurable as
host, device or ID-dependent.
One set of on-chip USB 2.0 high speed transceiver with host only.
USB 2.0 High Speed Host Controller
USB 2.0 High Speed
with on-chip transceiver
Compliant with USB Revision 2.0 Specification.
Compatible with EHCI (Enhanced Host Controller Interface) Revision 1.0.
Compatible with OHCI (Open Host Controller Interface) Revision 1.0.
Jan. 28, 2019
Page 14 of 246
Rev 1.00
NUC980
Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed
(1.5Mbps) USB devices.
Integrated with a port routing logic to route full/low speed device to OHCI
controller.
Supports an integrated Root Hub.
Built-in DMA.
USB 2.0 High Speed Device Controller
Compliant with USB Revision 2.0 Specification.
Supports one dedicate control endpoint and 12 configurable endpoints; each
can be Isochronous, Bulk or Interrupt and either IN or OUT direction.
4096 bytes configurable RAM for endpoint buffer and up to 1024 bytes packet
size.
Three different operation modes of an in-endpoint: Auto Validation mode,
Manual Validation mode and Fly mode.
Suspend, resume and remote wake-up capability.
Built-in DMA.
IEEE Std. 802.3 CSMA/CD protocol.
Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol.
Two sets of Ethernet MAC.
Supports both half and full duplex for 10 Mbps or 100 Mbps operation.
RMII (Reduced Media Independent Interface) and serial management interface
(MDC/MDIO).
Ethernet MAC
Pause and remote pause function for flow control.
Long frame (more than 1518 bytes) and short frame (less than 64 bytes)
reception.
CAM function for Ethernet MAC address recognition.
Supports Magic Packet recognition to wake system up from Power-down
mode.
Built-in DMA.
Two sets of CMOS sensor interfaces supporting CCIR601 and CCIR656 type
sensor.
Resolution up to 3M pixels.
Supports YUV422 and RGB565 color format for data output by CMOS image
sensor.
CMOS Sensor Interface
Supports YUV422, RGB565, RGB555 and Y-only color format with planar and
packet data format for data storing to system memory.
Supports image cropping and cropping window up to 4096x2048.
Supports vertical and horizontal scaling-down with N/M scaling factor.
Supports Negative, Sepia and Posterization color effects
Cryptography Accelerator
Hardware RSA accelerator.
Rivest、Shamir and
Adleman Cryptography
Supports both encryption and decryption.
Supports up to 2048 bits.
(RSA)
Hardware ECC accelerator.
Elliptic Curve
Cryptography (ECC)
Supports 192-bit and 256-bit key length.
Jan. 28, 2019
Page 15 of 246
Rev 1.00
NUC980
Supports both prime field GF(p) and binary field GF(2m).
Supports NIST P-192, P-224, P-256, P-384 and P-521 curve sizes.
Supports NIST B-163, B-233, B-283, B-409 and B-571 curve sizes.
Supports NIST K-163, K-233, K-283, K-409 and K-571 curve sizes.
Supports point multiplication, addition and doubling operations in GF(p) and
GF(2m).
Supports modulus division, multiplication, addition and subtraction operations
in GF(p).
Hardware AES accelerator.
Supports 128-bit, 192-bit and 256-bit key length and key expander, and
compliant with FIPS 197.
Advanced Encryption
Standard (AES)
Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2 and CBC-CS3
block cipher modes
Compliant with NIST SP800-38A and addendum.
Hardware SHA accelerator.
Secure Hash Algorithm
(SHA)
Supports SHA-160, SHA-224, SHA-256, SHA-384 and SHA-512.
Compliant with FIPS 180/180-2.
Hardware HMAC accelerator.
keyed-Hash Message
Authentication Code
(HMAC)
Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-
384, and HMAC-SHA-512.
Compliant with FIPS 180/180-2.
PRNG
Supports 64-/128-/192-/256-bit random number generator.
Jan. 28, 2019
Page 16 of 246
Rev 1.00
NUC980
3 PARTS INFORMATION
3.1 Package Type
Part No.
NUC980
LQFP64-EP
NUC980DRxxY
LQFP128
NUC980DKxxY,
LQFP216
NUC980DFxxYC
NUC980DKxxYC
Figure 3-1 NUC980 Series Package Type
Jan. 28, 2019
Page 17 of 246
Rev 1.00
NUC980
3.2
NUC980 Series Part Selection Guide
NUC980
DK41Y
Part Number
DF71YC
DK61YC
DK61Y
DR61Y
DR41Y
16
DDR Size(MB)
I/O
128
64
16
64
104
92
6
40
6
-
32-bit Timer
RTC
6
√
√
UART
10
10
2
8
2
1
2
1
2
ISO-7816
Quad SPI
2
1
1
SPI
3
3
I2S
1
1
I2C
4
4
CAN
4
4
-
-
SDHC/SDIO
PRNG 256
2
2
√
√
√
√
√
√
√
2
√
√
8
2
2
√
√
√
√
√
√
√
-
AES 256
√
RSA 2048
√
ECC
√
HMAC SHA 512
SHA 512
√
√
External Bus Interface
Camera Interface
SPI NAND
√
2
2
-
√
NAND Flash Interface
16-bit PWM
10/100Mb Ethernet MAC
USB 1.1 FS Host Lite
USB 2.0 HS Host
USB 2.0 HS Host / Device
12-bit ADC
√
-
8
5
1
-
2
6
6
-
1
1
-
1
8
1
8
1
2
Package
LQFP216
LQFP 128
LQFP 64 - EP
Table 3.2-1 NUC980 Series Part Selection Guide
Jan. 28, 2019
Page 18 of 246
Rev 1.00
NUC980
3.3
NUC980 Series Naming Rule
Figure 3.3-1 NUC980 Series Selection Code
Jan. 28, 2019
Page 19 of 246
Rev 1.00
NUC980
4 PIN CONFIGURATION
4.1 Pin Configuration
4.1.1
NUC980DRxxY LQFP64-EP Pin Diagram
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PF.7
PF.8
VDD33
VDD12
PC.15
PC.14
PC.13
PC.12
PC.11
PC.10
PC.9
Top transparent view
PF.9
PF.11
PF.12
VDD33
XT_IN
XT_OUT
PE.11
LQFP64-EP
VDD12
PC.8
VUSB1_VDD33
VUSB0_VDD12
USB0_DM
USB0_DP
VUSB0_VDD33
USB0_REXT
PC.6
PC.5
PC.4
VSS
PC.3
AVDD33
PB.4
Figure 4.1-1 NUC980DRxxY LQFP 64-pin with EX-PAD Diagram
Jan. 28, 2019
Page 20 of 246
Rev 1.00
NUC980
4.1.2
NUC980DKxxYx LQFP128 Pin Diagram
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF.8
PF.9
VSS
98
PD.4
PD.3
PD.2
VDDIO
PC.15
PC.14
PC.13
PC.12
PC.11
PC.10
PC.9
PC.8
PC.7
PC.6
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
VDD
99
PF.10
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
PF.11
PF.12
VDDIO
XT_IN
XT_OUT
PE.0
PE.1
PE.2
PE.3
PE.4
PE.5
PE.6
PE.7
LQFP128
PE.8
PE.9
PE.10
PE.11
PE.12
VDD
USB1_DM
USB1_DP
USB1_VDD33
USB1_REXT
USB0_VDD
USB0_DM
USB0_DP
USB0_VDD33
USB0_REXT
VSS
PB.8
X32_OUT
X32_IN
V
BAT33
PB.2
PB.3
PB.1
PB.5
PB.7
AVDDADC
Figure 4.1-2 NUC980DKxxYx LQFP 128-pin Diagram
Jan. 28, 2019
Page 21 of 246
Rev 1.00
NUC980
4.1.3
NUC980DFxxYC LQFP216 Pin Diagram
163
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
PLL_VSS
VSS
PF.7
PF.8
PF.9
USER_ID.3
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
USER_ID.2
USER_ID.1
USER_ID.0
VSS
DRAM_SIZE.2
DRAM_SIZE.1
DRAM_SIZE.0
CRPT_EN
VDDIO
VDD
PF.10
PF.11
VSS
PF.12
VDDIO
XT_IN
XT_OUT
VSS
PE.0
PE.1
PE.2
VDD
PE.3
PE.4
PE.5
PE.6
PE.7
VDDIO
PE.8
PE.9
PE.10
PE.11
PE.12
VSS
CAN_EN
VSS
VSS
VDD
PC.15
PC.14
PC.13
PC.12
PC.11
PC.10
VSS
PC.9
VSS
PC.8
PC.7
PC.6
VSS
PC.5
VSS
PC.4
PC.3
PC.2
PC.1
PC.0
VDD
VSS
VSS
PB.8
VSS
BAT_VSS33
X32_OUT
X32_IN
nWAKEUP
PWREN
VBAT33
AVDDADC
VREF
PB.2
PB.3
PB.1
PB.5
LQFP216
VDD
VSS
VDD
VDD
USB1_VSS
USB1_XTALOUT_U1
USB1_XTALIN_U1
USB1_VSS
USB1_DM
USB1_DP
USB1_VDD33
USB1_VDD33
USB1_REXT
USB0_VDD
USB0_VDD
USB0_VSS
USB0_XTALOUT_U0
USB0_XTALIN_U0
USB0_VSS
USB0_DM
USB0_DP
USB0_VDD33
USB0_VDD33
USB0_REXT
PB.7
AVDDADC
AVSSADC
Figure 4.1-3 NUC980DFxxYC LQFP 216-pin Diagram
Jan. 28, 2019
Page 22 of 246
Rev 1.00
NUC980
4.2 Pin Description
4.2.1
NUC980 Pin Description
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
1
VSS
P
MFP0 Ground pin for digital circuit
1
2
1
2
USB0_ID
IU
-
USB0 Host/Device identification with an internal pull-up
1: Device (default)
0: Host
2
3
PA.0
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin
MFP1 Quad SPI0 slave select 1 pin
MFP3 I2C0 data input/output pin
QSPI0_SS1
I2C0_SDA
UART1_RXD
EINT0
MFP4 UART1 data receiver input pin
MFP5 External interrupt 0 input pin
MFP6 Timer0 event counter input/toggle output pin
MFP7 CAN3 bus receiver input
I
TM0_ECNT
CAN3_RXD
PA.1
I/O
I
3
3
4
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI chip select 2 output pin
MFP2 EBI external clock output pin
MFP3 I2C0 clock pin
EBI_nCS2
EBI_MCLK
I2C0_SCL
UART1_TXD
EINT1
O
I/O
O
MFP4 UART1 data transmitter output pin
MFP5 External interrupt 1 input pin
MFP6 Timer1 event counter input/toggle output pin
MFP7 CAN3 bus transmitter output
MFP0 General purpose digital I/O pin
MFP1 UART6 clear to Send input pin
MFP2 I2S left right channel clock output pin
MFP3 Smart Card 0 card detect pin
MFP4 JTAG1 data output pin
I
TM1_ECNT
CAN3_TXD
PA.2
I/O
O
4
4
5
I/O
I
UART6_CTS
I2S_LRCK
SC0_CD
O
I
JTAG1_TDO
TM2_ECNT
PA.3
O
I/O
I/O
O
MFP6 Timer2 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 UART6 request to Send output pin
MFP2 I2S bit clock output pin
5
5
6
UART6_RTS
I2S_BCLK
SC0_PWR
JTAG1_TCK
O
O
MFP3 Smart Card 0 power pin
I
MFP4 JTAG1 clock input pin
Jan. 28, 2019
Page 23 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
TM3_ECNT
PA.4
I/O
I/O
I
MFP6 Timer3 event counter input/toggle output pin
6
7
8
6
7
MFP0 General purpose digital I/O pin
MFP1 UART6 data receiver input pin
MFP2 I2S data input pin
UART6_RXD
I2S_DI
I
SC0_DAT
JTAG1_TMS
TM4_ECNT
PA.5
I/O
I
MFP3 Smart Card 0 data pin
MFP4 JTAG1 test mode selection input pin
MFP6 Timer4 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 UART6 data transmitter output pin
MFP2 I2S data output pin
I/O
I/O
O
O
O
I
7
8
UART6_TXD
I2S_DO
SC0_CLK
JTAG1_TDI
TM5_ECNT
PA.6
MFP3 Smart Card 0 clock pin
MFP4 JTAG1 data input pin
I/O
I/O
O
O
O
I
MFP6 Timer5 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI chip select 1 output pin
MFP2 I2S master clock output pin
MFP3 Smart Card 0 reset pin
8
9
EBI_nCS1
I2S_MCLK
SC0_RST
JTAG1_nTRST
MFP4 JTAG1 reset input pin
9
9
10 VDD33
11 VSS
P
MFP0 Power supply for I/O power pin
MFP0 Ground pin for digital circuit
MFP0 Power supply for Internal core power pin
MFP0 Ground pin for digital circuit
MFP0 Power supply for Internal core power pin
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
P
10
10
12 VDD12
13 VSS
P
P
14 VDD12
15 VSS
P
P
11
11
16 MVDD
17 VSS
P
P
18 MVDD
19 VSS
P
P
20 MVDD
21 VSS
P
P
12
22 MVDD
23 VSS
P
P
24 MVDD
P
Jan. 28, 2019
Page 24 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
25 VSS
26 VSS
27 VSS
28 VDD12
29 PA.7
P
P
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
P
MFP0 Ground pin for digital circuit
12
13
14
P
MFP0 Power supply for Internal core power pin
MFP0 General purpose digital I/O pin
MFP1 EBI write enable output pin
I/O
O
EBI_nWE
UART2_CTS
TM3_EXT
I
MFP2 UART2 clear to Send input pin
MFP3 Timer3 external capture input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI read enable output pin
I/O
I/O
O
15
16
17
18
19
30 PA.8
EBI_nRE
UART2_RTS
TM3_TGL
O
MFP2 UART2 request to Send output pin
MFP3 Timer3 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI chip select 0 output pin
I/O
I/O
O
31 PA.9
EBI_nCS0
UART2_RXD
TM2_EXT
I
MFP2 UART2 data receiver input pin
MFP3 Timer2 external capture input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 10
I/O
I/O
O
32 PA.10
EBI_ADDR10
UART2_TXD
TM2_TGL
O
MFP2 UART2 data transmitter output pin
MFP3 Timer2 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 9
I/O
I/O
O
33 PA.11
EBI_ADDR9
UART8_RXD
TM4_EXT
I
MFP2 UART8 data receiver input pin
MFP3 Timer4 external capture input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 8
I/O
I/O
O
34 PA.12
EBI_ADDR8
UART8_TXD
TM4_TGL
O
MFP2 UART8 data transmitter output pin
MFP3 Timer4 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 13
I/O
I/O
O
35 PA.13
EBI_ADDR13
I2C1_SDA
I/O
I/O
A
MFP2 I2C1 data input/output pin
TM1_EXT
MFP3 Timer1 external capture input/toggle output pin
MFP4 USB 1.1 host lite port 5 differential signal D-
USBHL5_DM
Jan. 28, 2019
Page 25 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
CAN1_RXD
UART7_TXD
PWM03
I
MFP5 CAN1 bus receiver input
O
MFP6 UART7 data transmitter output pin
MFP7 PWM03 counter synchronous trigger output pin
MFP8 External interrupt 0 input pin
O
EINT0
I
36 PA.14
EBI_ADDR14
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 14
I2C1_SCL
TM1_TGL
USBHL5_DP
CAN1_TXD
UART7_RXD
PWM02
I/O
I/O
A
MFP2 I2C1 clock pin
MFP3 Timer1 event counter input/toggle output pin
MFP4 USB 1.1 host lite port 5 differential signal D+
MFP5 CAN1 bus transmitter output
O
I
MFP6 UART7 data receiver input pin
MFP7 PWM02 counter synchronous trigger output pin
MFP8 External interrupt 1 input pin
O
EINT1
I
37 PA.15
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 19
EBI_ADDR19
I2C0_SDA
TM5_EXT
I/O
I/O
A
MFP2 I2C0 data input/output pin
MFP3 Timer5 external capture input/toggle output pin
MFP4 USB 1.1 host lite port 4 differential signal D-
MFP5 CAN2 bus receiver input
USBHL4_DM
CAN2_RXD
SPI1_SS0
PWM01
I
I/O
O
MFP6 SPI1 slave select 0 pin
MFP7 PWM01 counter synchronous trigger output pin
MFP8 I2S left right channel clock output pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 0
I2S_LRCK
O
38 PG.10
I/O
I/O
I/O
I/O
A
EBI_DATA0
I2C0_SCL
TM5_TGL
USBHL4_DP
CAN2_TXD
SPI1_CLK
PWM00
MFP2 I2C0 clock pin
MFP3 Timer5 event counter input/toggle output pin
MFP4 USB 1.1 host lite port 4 differential signal D+
MFP5 CAN2 bus transmitter output
O
I/O
O
MFP6 SPI1 serial clock pin
MFP7 PWM00 counter synchronous trigger output pin
MFP8 I2S bit clock output pin
I2S_BCLK
O
13
20
21
39 VDD33
40 PG.9
P
MFP0 Power supply for I/O power pin
MFP0 General purpose digital I/O pin
I/O
Jan. 28, 2019
Page 26 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Pin Pin
Type MFP Description
Pin
EBI_ADDR7
UART8_CTS
PWM13
O
I
MFP1 EBI address bus bit 7
MFP2 UART8 clear to Send input pin
O
IU
MFP6 PWM13 counter synchronous trigger output pin
CFG.9_PwrOnSet9
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
22
41 PG.8
EBI_ADDR6
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 6
UART8_RTS
PWM12
O
MFP2 UART8 request to Send output pin
MFP6 PWM12 counter synchronous trigger output pin
O
CFG.8_PwrOnSet8
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
23
42 PG.7
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 5
EBI_ADDR5
UART5_TXD
PWM11
O
MFP2 UART5 data transmitter output pin
MFP6 PWM11 counter synchronous trigger output pin
O
CFG.7_PwrOnSet7
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
24
43 PG.6
I/O
O
I
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 4
EBI_ADDR4
UART5_RXD
PWM10
MFP2 UART5 data receiver input pin
MFP6 PWM10 counter synchronous trigger output pin
O
IU
CFG.6_PwrOnSet6
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
25
44 PG.5
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 12
EBI_ADDR12
UART5_RTS
O
MFP2 UART5 request to Send output pin
CFG.5_PwrOnSet5
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
45 PG.4
I/O
O
I
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 18
EBI_ADDR18
UART5_CTS
MFP2 UART5 clear to Send input pin
CFG.4_PwrOnSet4
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
26
46 PG.3
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 3
EBI_ADDR3
UART2_RTS
O
MFP2 UART2 request to Send output pin
Jan. 28, 2019
Page 27 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
PWM03
O
MFP6 PWM03 counter synchronous trigger output pin
CFG.3_PwrOnSet3
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
47 PG.2
EBI_ADDR2
I/O
O
I
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 2
UART2_CTS
PWM02
MFP2 UART2 clear to Send input pin
MFP6 PWM02 counter synchronous trigger output pin
O
IU
CFG.2_PwrOnSet2
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
14
27
48 PG.1
I/O
O
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 1
EBI_ADDR1
UART2_TXD
PWM01
O
MFP2 UART2 data transmitter output pin
MFP6 PWM01 counter synchronous trigger output pin
O
CFG.1_PwrOnSet1
IU
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
15
28
49 PG.0
I/O
O
I
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 0
EBI_ADDR0
UART2_RXD
CLK_OUT
MFP2 UART2 data receiver input pin
MFP3 Internal clock selection output pin
MFP6 PWM00 counter synchronous trigger output pin
O
O
IU
PWM00
CFG.0_PwrOnSet0
-
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset.
50 VSS
P
P
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 12
51 VSS
29
30
52 PB.0
I/O
O
EBI_ADDR12
UART2_CTS
ADC_AIN0
I
MFP2 UART2 clear to Send input pin
MFP8 ADC channel 0 analog input
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 13
A
16
53 PB.6
I/O
O
EBI_ADDR13
I2C1_SDA
I/O
O
MFP2 I2C1 data input/output pin
I2S_LRCK
MFP3 I2S left right channel clock output pin
MFP4 USB 1.1 host lite port 0 differential signal D-
MFP5 UART7 data transmitter output pin
MFP6 SPI1 slave select 0 pin
USBHL0_DM
UART7_TXD
SPI1_SS0
A
O
I/O
Jan. 28, 2019
Page 28 of 246
Rev 1.00
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64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
ADC_AIN6
54 PB.4
EBI_ADDR14
A
I/O
O
MFP8 ADC channel 6 analog input
17
31
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 14
I2C1_SCL
I/O
O
MFP2 I2C1 clock pin
I2S_BCLK
USBHL0_DP
UART7_RXD
SPI1_CLK
ADC_AIN4
MFP3 I2S bit clock output pin
A
MFP4 USB 1.1 host lite port 0 differential signal D+
MFP5 UART7 data receiver input pin
MFP6 SPI1 serial clock pin
I
I/O
A
MFP8 ADC channel 4 analog input
MFP0 Ground pin for analog SAR-ADC
MFP0 Power supply for analog SAR-ADC, DC3.3V
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 15
32
33
34
55 AVSS
P
18
56 AVDD33
57 PB.7
P
I/O
O
EBI_ADDR15
I2C2_SDA
I2S_DI
I/O
I
MFP2 I2C2 data input/output pin
MFP3 I2S data input pin
USBHL0_DM
UART7_CTS
SPI1_MOSI
ADC_AIN7
A
MFP4 USB 1.1 host lite port 0 differential signal D-
MFP5 UART7 clear to Send input pin
MFP6 SPI1 MOSI (Master Out, Slave In) pin
MFP8 ADC channel 7 analog input
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 16
I
I/O
A
35
58 PB.5
I/O
O
EBI_ADDR16
I2C2_SCL
I/O
O
MFP2 I2C2 clock pin
I2S_DO
MFP3 I2S data output pin
USBHL0_DP
UART7_RTS
SPI1_MISO
ADC_AIN5
A
MFP4 USB 1.1 host lite port 0 differential signal D+
MFP5 UART7 request to Send output pin
MFP6 SPI1 MISO (Master In, Slave Out) pin
MFP8 ADC channel 5 analog input
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 17
O
I/O
A
36
59 PB.1
I/O
O
EBI_ADDR17
I2C3_SDA
I2S_MCLK
CAN2_RXD
TM0_EXT
I/O
O
MFP2 I2C3 data input/output pin
MFP3 I2S master clock output pin
MFP4 CAN2 bus receiver input
I
I/O
MFP5 Timer0 external capture input/toggle output pin
Jan. 28, 2019
Page 29 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
SPI1_SS1
I/O
O
A
MFP6 SPI1 slave select 1 pin
UART9_TXD
ADC_AIN1
MFP7 UART9 data transmitter output pin
MFP8 ADC channel 1 analog input
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 18
37
60 PB.3
EBI_ADDR18
I/O
O
I/O
I
I2C3_SCL
EINT2
MFP2 I2C3 clock pin
MFP3 External interrupt 2 input pin
MFP4 CAN2 bus transmitter output
MFP5 Timer0 event counter input/toggle output pin
MFP6 SPI0 slave select 1 pin
CAN2_TXD
TM0_TGL
SPI0_SS1
UART9_RXD
ADC_AIN3
O
I/O
I/O
I
MFP7 UART9 data receiver input pin
MFP8 ADC channel 3 analog input
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 2
A
38
61 PB.2
I/O
O
O
A
EBI_ADDR2
UART9_RTS
ADC_AIN2
MFP7 UART9 request to Send output pin
MFP8 ADC channel 2 analog input
MFP0 ADC reference voltage input
MFP0 Power supply for analog SAR-ADC, DC 3.3V
MFP0 Power supply by batteries for RTC
No connect
62 AVref
A
63 AVDD33
64 VBAT33
65 NC
P
39
P
-
66 NC
-
No connect
40
41
67 X32_IN
68 X32_OUT
69 VSS
I
MFP0 External 32.768 kHz crystal input pin
MFP0 External 32.768 kHz crystal output pin
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
MFP1 EBI address bus bit 11
O
P
70 VSS
P
42
71 PB.8
I/O
O
I/O
I
EBI_ADDR11
I2C2_SCL
CAN2_RXD
UART8_TXD
SD0_nCD
TM0_EXT
MFP2 I2C2 clock pin
MFP3 CAN2 bus receiver input
O
I
MFP4 UART8 data transmitter output pin
MFP6 SD0 card detect input pin
MFP7 Timer0 external capture input/toggle output pin
MFP0 Ground pin for digital circuit
I/O
P
72 VSS
Jan. 28, 2019
Page 30 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
73 VSS
74 VDD12
75 PC.0
P
P
MFP0 Ground pin for digital circuit
43
44
MFP0 Power supply Internal core power pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 0
I/O
I/O
I/O
O
EBI_DATA0
I2C2_SDA
CAN2_TXD
UART8_RXD
SPI0_SS1
TM0_TGL
MFP2 I2C2 data input/output pin
MFP3 CAN2 bus transmitter output
MFP4 UART8 data receiver input pin
MFP5 SPI0 slave select 1 pin
I
I/O
I/O
I/O
I/O
O
MFP7 Timer0 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 1
45
46
47
76 PC.1
EBI_DATA1
NAND_nCS0
UART7_TXD
MFP3 NAND flash chip enable input
MFP4 UART7 data transmitter output pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 2
O
77 PC.2
I/O
I/O
O
EBI_DATA2
NAND_nWP
UART7_RXD
MFP3 NAND flash write protect input
MFP4 UART7 data receiver input pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 3
I
19
78 PC.3
I/O
I/O
O
EBI_DATA3
VCAP0_CLKO
NAND_ALE
I2C1_SCL
MFP2 Video image interface 0 sensor clock pin
MFP3 NAND flash address latch enable
MFP4 I2C1 clock pin
O
I/O
O
UART3_TXD
CAN0_RXD
MFP5 UART3 data transmitter output pin
MFP7 CAN0 bus receiver input
I
20
48
79 PC.4
I/O
I/O
I
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 4
EBI_DATA4
VCAP0_PCLK
NAND_CLE
I2C1_SDA
MFP2 Video image interface 0 pixel clock pin
MFP3 NAND flash command latch enable
MFP4 I2C1 data input/output pin
O
I/O
I
UART3_RXD
SPI0_MOSI
CAN0_TXD
MFP5 UART3 data receiver input pin
MFP6 SPI0 MOSI (Master Out, Slave In) pin
MFP7 CAN0 bus transmitter outpu
MFP0 Ground pin for digital circuit
I/O
O
80 VSS
P
Jan. 28, 2019
Page 31 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
21
49
81 PC.5
I/O
I/O
I
MFP0 General purpose digital I/O pin
EBI_DATA5
MFP1 EBI data bus bit 5
VCAP0_HSYNC
NAND_nWE
SPI0_SS0
MFP2 Video image interface 0 horizontal sync. Pin
MFP3 NAND flash write enable
MFP5 SPI0 slave select 0 pin
O
I/O
I/O
SD0_CMD/
MFP6 SD0 command/response pin
eMMC0 command/response pin
eMMC0_CMD
UART1_TXD
O
P
MFP7 UART1 data transmitter output pin
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 6
82 VSS
83 PC.6
EBI_DATA6
22
50
51
52
I/O
I/O
I
VCAP0_VSYNC
NAND_nRE
SC1_RST
MFP2 Video image interface 0 vertical sync. Pin
MFP3 NAND flash read enable
MFP4 Smart Card 1 reset pin
O
O
SPI0_CLK
I/O
O
MFP5 SPI0 serial clock pin
SD0_CLK/
MFP6 SD0 clock output pin
eMMC0 clock output pin
eMMC0_CLK
UART1_RXD
I
MFP7 UART1 data receiver input pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 7
84 PC.7
I/O
I/O
I
EBI_DATA7
VCAP0_FIELD
NAND_RDY0
SC1_CLK
MFP2 Video image interface 0 frame sync. Pin
MFP3 NAND flash ready/busy input
MFP4 Smart Card 1 clock pin
I
O
SPI0_MOSI
I/O
I/O
MFP5 SPI0 MOSI (Master Out, Slave In) pin
SD0_DATA0/
MFP6 SD0 data line bit 0
eMMC0 data line bit 0
eMMC0_DATA0
UART1_RTS
O
I/O
I/O
I
MFP7 UART1 request to Send output pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 8
23
85 PC.8
EBI_DATA8
VCAP0_DATA0
NAND_DATA0
SC1_DAT
MFP2 Video image interface 0 data 0 pin
MFP3 NAND flash data bus bit 0
MFP4 Smart Card 1 data pin
I/O
I/O
I/O
SPI0_MISO
MFP5 SPI0 MISO (Master In, Slave Out) pin
Jan. 28, 2019
Page 32 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
SD0_DATA1/
I/O
MFP6 SD0 data line bit 1
eMMC0 data line bit 1
eMMC0_DATA1
UART1_CTS
I
MFP7 UART1 clear to Send input pin
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 9
86 VSS
P
24
53
87 PC.9
I/O
I/O
I
EBI_DATA9
VCAP0_DATA1
NAND_DATA1
SC1_PWR
MFP2 Video image interface 0 data 1 pin
MFP3 NAND flash data bus bit 1
MFP4 Smart Card 1 power pin
I/O
O
SD0_DATA2/
I/O
MFP6 SD0 data line bit 2
eMMC0 data line bit 2
eMMC0_DATA2
UART4_TXD
O
P
MFP7 UART4 data transmitter output pin
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 10
88 VSS
89 PC.10
EBI_DATA10
25
54
I/O
I/O
I
VCAP0_DATA2
NAND_DATA2
SC1_CD
MFP2 Video image interface 0 data 2 pin
MFP3 NAND flash data bus bit 2
MFP4 Smart Card 1 card detect pin
I/O
I
SD0_DATA3/
I/O
MFP6 SD0 data line bit 3
eMMC0 data line bit 3
eMMC0_DATA3
UART4_RXD
I
MFP7 UART4 data receiver input pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 11
26
55
90 PC.11
I/O
I/O
I
EBI_DATA11
VCAP0_DATA3
NAND_DATA3
SC0_RST
MFP2 Video image interface 0 data 3 pin
MFP3 NAND flash data bus bit 3
MFP4 Smart Card 0 reset pin
I/O
O
27
56
91 PC.12
I/O
I/O
I
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 12
EBI_DATA12
VCAP0_DATA4
NAND_DATA4
SC0_CLK
MFP2 Video image interface 0 data 4 pin
MFP3 NAND flash data bus bit 4
MFP4 Smart Card 0 clock pin
I/O
O
SD0_nCD
I
MFP6 SD0 card detect input pin
MFP7 UART8 data transmitter output pin
UART8_TXD
O
Jan. 28, 2019
Page 33 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
28
57
92 PC.13
I/O
I/O
I
MFP0 General purpose digital I/O pin
EBI_DATA13
MFP1 EBI data bus bit 13
MFP2 Video image interface 0 data 5 pin
MFP3 NAND flash data bus bit 5
MFP4 Smart Card 0 data pin
MFP7 UART8 data receiver input pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 14
MFP2 Video image interface 0 data 6 pin
MFP3 NAND flash data bus bit 6
MFP4 Smart Card 0 power pin
MFP5 SPI0 MOSI (Master Out, Slave In) pin
MFP7 UART8 request to Send output pin
MFP0 General purpose digital I/O pin
MFP1 EBI data bus bit 15
MFP2 Video image interface 0 data 7 pin
MFP3 NAND flash date bus bit 7
MFP4 Smart Card 0 card detect pin
MFP7 UART8 clear to Send input pin
MFP0 Power supply for Internal core power pin
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
No connect
VCAP0_DATA5
NAND_DATA5
SC0_DAT
I/O
I/O
I
UART8_RXD
29
58
93 PC.14
I/O
I/O
I
EBI_DATA14
VCAP0_DATA6
NAND_DATA6
SC0_PWR
I/O
O
I/O
O
I/O
I/O
I
SPI0_MOSI
UART8_RTS
30
59
94 PC.15
EBI_DATA15
VCAP0_DATA7
NAND_DATA7
SC0_CD
I/O
I
UART8_CTS
I
31
32
95 VDD12
P
96 VSS
97 VSS
98 NC
99 VDD33
100 NC
101 NC
102 NC
103 NC
104 VSS
105 NC
106 NC
107 NC
108 NC
P
P
-
60
P
MFP0 Power supply for I/O power pin
No connect
-
-
No connect
-
No connect
-
No connect
P
MFP0 Ground pin for digital circuit
No connect
-
-
No connect
-
No connect
-
No connect
Jan. 28, 2019
Page 34 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
109 NC
110 VSS
111 PD.0
-
No connect
P
MFP0 Ground pin for digital circuit
I/O
I/O
O
MFP0 General purpose digital I/O pin
QSPI0_SS1
MFP1 Quad SPI0 slave select 1 pin
UART5_TXD
TM1_TGL
EINT2
MFP2 UART5 data transmitter output pin
MFP3 Timer1 event counter input/toggle output pin
MFP4 External interrupt 2 input pin
I/O
I
112 PD.1
I/O
I/O
I
MFP0 General purpose digital I/O pin
SPI0_SS1
UART5_RXD
TM1_EXT
EINT3
MFP1 SPI0 slave select 1 pin
MFP2 UART5 data receiver input pin
I/O
I
MFP3 Timer1 external capture input/toggle output pin
MFP4 External interrupt 3 input pin
113 PB.9
I/O
O
MFP0 General purpose digital I/O pin
UART3_TXD
PWM13
MFP1 UART3 data transmitter output pin
MFP2 PWM13 counter synchronous trigger output pin
MFP3 Timer0 event counter input/toggle output pin
MFP4 USB 1.1 host lite port 0 differential signal D-
MFP5 SPI1 slave select 0 pin
O
TM0_TGL
USBHL0_DM
SPI1_SS0
I/O
A
I/O
I/O
I
114 PB.10
MFP0 General purpose digital I/O pin
UART3_RXD
PWM12
MFP1 UART3 data receiver input pin
O
MFP2 PWM12 counter synchronous trigger output pin
MFP3 Timer0 external capture input/toggle output pin
MFP4 USB 1.1 host lite port 0 differential signal D+
MFP5 SPI1 serial clock pin
TM0_EXT
USBHL0_DP
SPI1_CLK
I/O
A
I/O
I/O
O
115 PB.11
MFP0 General purpose digital I/O pin
UART3_RTS
PWM11
MFP1 UART3 request to Send output pin
MFP2 PWM11 counter synchronous trigger output pin
MFP3 Timer2 external capture input/toggle output pin
MFP4 USB 1.1 host lite port 5 differential signal D-
MFP5 SPI1 MOSI (Master Out, Slave In) pin
MFP0 General purpose digital I/O pin
O
TM2_EXT
I/O
A
USBHL5_DM
SPI1_MOSI
I/O
I/O
I
116 PB.12
UART3_CTS
PWM10
MFP1 UART3 clear to Send input pin
O
MFP2 PWM10 counter synchronous trigger output pin
Jan. 28, 2019
Page 35 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Pin Pin
Type MFP Description
Pin
TM2_TGL
I/O
A
MFP3 Timer2 event counter input/toggle output pin
USBHL5_DP
SPI1_MISO
MFP4 USB 1.1 host lite port 5 differential signal D+
MFP5 SPI1 MISO (Master In, Slave Out) pin
MFP0 General purpose digital I/O pin
I/O
I/O
I/O
O
33
34
35
61
117 PD.2
QSPI0_SS0
MFP1 Quad SPI0 slave select 0 pin.(booting)
MFP2 UART3 data transmitter output pin
MFP3 Timer4 external capture input/toggle output pin
MFP0 General purpose digital I/O pin
UART3_TXD
TM4_EXT
I/O
I/O
I/O
I
62
118 PD.3
QSPI0_CLK
UART3_RXD
TM4_TGL
MFP1 Quad SPI0 serial clock pin.(booting)
MFP2 UART3 data receiver input pin
I/O
I/O
I/O
MFP3 Timer4 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
63
119 PD.4
QSPI0_MOSI0
MFP1 Quad SPI0 MOSI0 (Master Out, Slave In) pin. Data 0 of quad
mode.(booting)
UART3_RTS
TM5_EXT
O
MFP2 UART3 request to Send output pin
I/O
MFP3 Timer5 external capture input/toggle output pin
64
65
VSS
P
MFP0 Ground pin for digital circuit
MFP0 General purpose digital I/O pin
36
120 PD.5
I/O
QSPI0_MISO0
I/O
MFP1 Quad SPI0 MISO0 (Master In, Slave Out) pin. Data 1 of quad
mode.(booting)
UART3_CTS
TM5_TGL
I
MFP2 UART3 clear to Send input pin
I/O
I/O
I/O
MFP3 Timer5 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
66
67
68
121 PD.6
QSPI0_MOSI1
MFP1 Quad SPI0 MOSI1 (Master Out, Slave In) pin. Data 2 of quad
mode.(booting)
UART2_TXD
TM0_ECNT
CAN0_RXD
O
I/O
I
MFP2 UART2 data transmitter output pin
MFP3 Timer0 event counter input/toggle output pin
MFP4 CAN0 bus receiver input
122 PD.7
I/O
I/O
MFP0 General purpose digital I/O pin
QSPI0_MISO1
MFP1 Quad SPI0 MISO1 (Master In, Slave Out) pin. Data 3 of quad
mode.(booting)
UART2_RXD
TM1_ECNT
CAN0_TXD
I
MFP2 UART2 data receiver input pin
MFP3 Timer1 event counter input/toggle output pin
MFP4 CAN0 bus transmitter output
I/O
O
123 PD.8
I/O
MFP0 General purpose digital I/O pin
Jan. 28, 2019
Page 36 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Pin Pin
Type MFP Description
Pin
SPI0_SS0
I/O
I
MFP1 SPI0 slave select 0 pin
UART6_CTS
TM2_ECNT
MFP2 UART6 clear to Send input pin
MFP3 Timer2 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 SPI0 serial clock pin
I/O
I/O
I/O
O
69
124 PD.9
SPI0_CLK
UART6_RTS
TM3_ECNT
MFP2 UART6 request to Send output pin
MFP3 Timer3 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 SPI0 MOSI (Master Out, Slave In) pin
MFP2 UART6 data transmitter output pin
MFP3 Timer4 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 SPI0 MISO (Master In, Slave Out) pin
MFP2 UART6 data receiver input pin
MFP3 Timer5 event counter input/toggle output pin
MFP0 General purpose digital I/O pin
MFP1 UART4 data transmitter output pin
MFP2 Timer2 event counter input/toggle output pin
MFP4 CAN2 bus receiver input
I/O
I/O
I/O
O
70
125 PD.10
SPI0_MOSI
UART6_TXD
TM4_ECNT
I/O
I/O
I/O
I
71
126 PD.11
SPI0_MISO
UART6_RXD
TM5_ECNT
I/O
I/O
O
72
127 PD.12
UART4_TXD
TM2_TGL
CAN2_RXD
PWM00
I/O
I
O
MFP6 PWM00 counter synchronous trigger output pin
MFP8 EBI data bus bit 1
EBI_DATA1
I/O
P
128 VSS
129 PD.13
UART4_RXD
MFP0 Ground pin for digital circuit
73
I/O
I
MFP0 General purpose digital I/O pin
MFP1 UART4 data receiver input pin
MFP2 Timer2 external capture input/toggle output pin
MFP4 CAN2 bus transmitter output
TM2_EXT
CAN2_TXD
PWM01
I/O
O
O
MFP6 PWM01 counter synchronous trigger output pin
MFP8 EBI data bus bit 2
EBI_DATA2
I/O
I/O
O
74
130 PD.14
MFP0 General purpose digital I/O pin
MFP1 UART4 request to Send output pin
MFP2 Timer3 event counter input/toggle output pin
MFP3 I2C3 clock pin
UART4_RTS
TM3_TGL
I/O
I/O
I
I2C3_SCL
CAN1_RXD
MFP4 CAN1 bus receiver input
Jan. 28, 2019
Page 37 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
USBHL0_DM
PWM02
A
O
MFP5 USB 1.1 host lite port 0 differential signal D-
MFP6 PWM02 counter synchronous trigger output pin
MFP8 EBI data bus bit 3
EBI_DATA3
I/O
I/O
I
75
131 PD.15
UART4_CTS
MFP0 General purpose digital I/O pin
MFP1 UART4 clear to Send input pin
MFP2 Timer3 external capture input/toggle output pin
MFP3 I2C3 data input/output pin
TM3_EXT
I2C3_SDA
CAN1_TXD
USBHL0_DP
PWM03
I/O
I/O
O
MFP4 CAN1 bus transmitter output
A
MFP5 USB 1.1 host lite port 0 differential signal D+
MFP6 PWM03 counter synchronous trigger output pin
MFP8 EBI data bus bit 4
O
EBI_DATA4
I/O
I/O
I/O
I/O
I
76
132 PG.11
MFP0 General purpose digital I/O pin
MFP2 SPI1 slave select 0 pin
SPI1_SS0
TM1_TGL
CAN0_RXD
UART5_CTS
PWM10
MFP3 Timer1 event counter input/toggle output pin
MFP4 CAN0 bus receiver input
I
MFP5 UART5 clear to Send input pin
MFP6 PWM10 counter synchronous trigger output pin
MFP7 JTAG0 data output pin
O
JTAG0_TDO
O
77
133 PG.12
I/O
I/O
I/O
O
MFP0 General purpose digital I/O pin
MFP2 SPI1 serial clock pin
SPI1_CLK
TM1_EXT
CAN0_TXD
UART5_RTS
PWM11
MFP3 Timer1 external capture input/toggle output pin
MFP4 CAN0 bus transmitter output
O
MFP5 UART5 request to Send output pin
MFP6 PWM11 counter synchronous trigger output pin
MFP7 JTAG0 clock input pin
O
JTAG0_TCK
I
78
134 PG.13
I/O
I/O
I
MFP0 General purpose digital I/O pin
MFP2 SPI1 MOSI (Master Out, Slave In) pin
MFP4 CAN1 bus receiver input
SPI1_MOSI
CAN1_RXD
UART5_RXD
PWM12
I
MFP5 UART5 data receiver input pin
MFP6 PWM12 counter synchronous trigger output pin
MFP7 JTAG0 test mode selection input pin
MFP0 General purpose digital I/O pin
MFP2 SPI1 MISO (Master In, Slave Out) pin
O
JTAG0_TMS
I
79
135 PG.14
SPI1_MISO
I/O
I/O
Jan. 28, 2019
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64
128 216 Pin Name
Pin Pin
Type MFP Description
Pin
CAN1_TXD
UART5_TXD
PWM13
O
O
O
I
MFP4 CAN1 bus transmitter output
MFP5 UART5 data transmitter output pin
MFP6 PWM13 counter synchronous trigger output pin
MFP7 JTAG0 data input pin
JTAG0_TDI
80
136 PG.15
SPI0_SS1
I/O
I/O
I/O
I
MFP0 General purpose digital I/O pin
MFP1 SPI0 slave select 1 pin
SPI1_SS1
EINT3
MFP2 SPI1 slave select 1 pin
MFP4 External interrupt 3 input pin
MFP7 JTAG0 reset input pin
JTAG0_nTRST
I
37
81
137 nRESET
IU
MFP0 External reset input: active LOW, with an internal pull-up. Set this pin
low reset to initial state
WDT_nRST
138 VDD33
O
P
MFP1 Watch dog timer reset trigger output
MFP0 Power supply for I/O power pin
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
MFP0 Power supply for internal core power pin
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Power supply for Memory ports
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
MFP0 Ground pin for digital circuit
MFP0 Power supply for I/O power pin
MFP0 General purpose digital I/O pin
MFP1 RMII1 Receive Data Error input pin
139 VSS
140 VSS
141 VDD12
142 MVDD
143 VSS
144 MVDD
145 VSS
146 MVDD
147 VSS
148 MVDD
149 VSS
150 VSS
151 VSS
152 VDD33
153 PF.0
P
P
38
39
82
83
P
P
P
P
P
84
P
P
P
P
P
P
40
41
85
86
P
I/O
I
RMII1_RXERR
SD1_CMD/
I/O
MFP2 SD1 command/response pin
eMMC1 command/response pin
eMMC1_CMD
TM0_ECNT
SC1_RST
I/O
O
MFP3 Timer0 event counter input/toggle output pin
MFP4 Smart Card 1 reset pin
Jan. 28, 2019
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64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
UART7_CTS
USBHL1_DM
EBI_DATA5
I
A
MFP5 UART7 clear to Send input pin
MFP6 USB 1.1 host lite port 1 differential signal D-
MFP8 EBI data bus bit 5
I/O
I/O
I
42
43
44
45
87
154 PF.1
RMII1_CRSDV
MFP0 General purpose digital I/O pin
MFP1 RMII1 Carrier Sense/Receive Data input pin
SD1_CLK/
O
MFP2 SD1 clock output pin
eMMC1 clock output pin
eMMC1_CLK
TM1_ECNT
SC1_CLK
I/O
O
MFP3 Timer1 event counter input/toggle output pin
MFP4 Smart Card 1 clock pin
UART7_RTS
USBHL1_DP
EBI_DATA6
O
MFP5 UART7 request to Send output pin
MFP6 USB 1.1 host lite port 1 differential signal D+
MFP8 EBI data bus bit 6
A
I/O
I/O
I
88
89
90
155 PF.2
MFP0 General purpose digital I/O pin
MFP1 RMII1 Receive Data bus bit 1
RMII1_RXD1
SD1_DATA0/
I/O
MFP2 SD1 data line bit 0
eMMC1 data line bit 0
eMMC1_DATA0
TM2_ECNT
SC1_DAT
I/O
I/O
I
MFP3 Timer2 event counter input/toggle output pin
MFP4 Smart Card 1 data pin
UART7_RXD
USBHL2_DM
EBI_DATA7
MFP5 UART7 data receiver input pin
MFP6 USB 1.1 host lite port 2 differential signal D-
MFP8 EBI data bus bit 7
A
I/O
I/O
I
156 PF.3
MFP0 General purpose digital I/O pin
MFP1 RMII1 Receive Data bus bit 0
RMII1_RXD0
SD1_DATA1/
I/O
MFP2 SD1 data line bit 1
eMMC1 data line bit 1
eMMC1_DATA1
TM3_ECNT
SC1_PWR
I/O
O
MFP3 Timer3 event counter input/toggle output pin
MFP4 Smart Card 1 power pin
UART7_TXD
USBHL2_DP
EBI_DATA8
O
MFP5 UART7 data transmitter output pin
MFP6 USB 1.1 host lite port 2 differential signal D+
MFP8 EBI data bus bit 8
A
I/O
I/O
I
157 PF.4
MFP0 General purpose digital I/O pin
MFP1 RMII1 mode clock input pin
MFP2 SD1 data line bit 2
RMII1_REFCLK
SD1_DATA2/
I/O
eMMC1_DATA2
Jan. 28, 2019
Page 40 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
eMMC1 data line bit 2
TM4_ECNT
SC1_CD
I/O
I
MFP3 Timer4 event counter input/toggle output pin
MFP4 Smart Card 1 card detect pin
UART3_CTS
USBHL3_DM
EBI_DATA9
I
MFP5 UART3 clear to Send input pin
MFP6 USB 1.1 host lite port 3 differential signal D-
MFP8 EBI data bus bit 9
A
I/O
I/O
O
46
91
158 PF.5
RMII1_TXEN
MFP0 General purpose digital I/O pin
MFP1 RMII1 Transmit Enable output pin
SD1_DATA3/
I/O
MFP2 SD1 data line bit 3
eMMC1 data line bit 3
eMMC1_DATA3
TM5_ECNT
PWM00
I/O
O
MFP3 Timer5 event counter input/toggle output pin
MFP4 PWM00 counter synchronous trigger output pin
MFP5 UART3 request to Send output pin
MFP6 USB 1.1 host lite port 3 differential signal D+
MFP8 EBI data bus bit 10
UART3_RTS
USBHL3_DP
EBI_DATA10
O
A
I/O
I/O
O
47
92
159 PF.6
MFP0 General purpose digital I/O pin
RMII1_TXD1
SD1_nCD
MFP1 RMII1 Transmit Data bus bit 1
I
MFP2 SD1 card detect input pin
TM4_EXT
I/O
O
MFP3 Timer4 external capture input/toggle output pin.
MFP4 PWM01 counter synchronous trigger output pin
MFP5 UART3 data receiver input pin
PWM01
UART3_RXD
USBHL4_DM
EBI_DATA11
I
A
MFP6 USB 1.1 host lite port 4 differential signal D-
MFP8 EBI data bus bit 11
I/O
I/O
I
93
160 PB.13
MFP0 General purpose digital I/O pin
EINT2
MFP2 External interrupt 2 input pin
TM4_TGL
PWM02
I/O
O
MFP3 Timer4 event counter input/toggle output pin
MFP4 PWM02 counter synchronous trigger output pin
MFP5 UART3 data transmitter output pin
MFP6 USB 1.1 host lite port 4 differential signal D+
MFP8 EBI data bus bit 0
UART3_TXD
USBHL4_DP
EBI_DATA0
O
A
I/O
P
48
94
161 VDD12
MFP0 Power supply for internal core power pin
MFP0 Power supply for internal core power pin
MFP0 Ground pin for digital circuit
162 VDD12
163 VSS
P
P
Jan. 28, 2019
Page 41 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
95
Pin
164 VSS
165 PF.7
P
I/O
O
MFP0 Ground pin for digital circuit
49
96
MFP0 General purpose digital I/O pin
RMII1_TXD0
MFP1 RMII1 Transmit Data bus bit 0
UART1_CTS
TM5_EXT
I
MFP2 UART1 clear to Send input pin
I/O
O
MFP3 Timer5 external capture input/toggle output pin
MFP4 PWM02 counter synchronous trigger output pin
MFP5 UART3 data transmitter output pin
MFP6 USB 1.1 host lite port 4 differential signal D+
MFP8 EBI data bus bit 12
PWM02
UART3_TXD
USBHL4_DP
EBI_DATA12
O
A
I/O
I/O
I/O
O
50
97
166 PF.8
MFP0 General purpose digital I/O pin
RMII1_MDIO
UART1_RTS
TM1_TGL
MFP1 RMII1 PHY Management Data pin
MFP2 UART1 request to Send output pin
MFP3 Timer1 event counter input/toggle output pin
MFP4 PWM03 counter synchronous trigger output pin
MFP6 USB 1.1 host lite port 5 differential signal D-
MFP8 EBI data bus bit 13
I/O
O
PWM03
USBHL5_DM
EBI_DATA13
A
I/O
I/O
O
51
98
167 PF.9
MFP0 General purpose digital I/O pin
RMII1_MDC
UART1_RXD
TM1_EXT
MFP1 RMII1 PHY Management Clock output pin
MFP2 UART1 data receiver input pin
I
I/O
O
MFP3 Timer1 external capture input/toggle output pin
MFP4 PWM10 counter synchronous trigger output pin
MFP6 USB 1.1 host lite port 5 differential signal D+
MFP8 EBI data bus bit 14
PWM10
USBHL5_DP
EBI_DATA14
A
I/O
P
168 VDD12
169 PF.10
UART1_TXD
MFP0 Power supply for internal core power pin
MFP0 General purpose digital I/O pin
99
I/O
O
MFP2 UART1 data transmitter output pin
MFP3 Timer5 event counter input/toggle output pin
MFP4 PWM11 counter synchronous trigger output pin
MFP7 Video image interface 1 pixel clock pin
MFP8 EBI data bus bit 15
TM5_TGL
I/O
O
PWM11
VCAP1_PCLK
EBI_DATA15
I
I/O
I/O
I
52
100
170 PF.11
UART0_RXD
171 VSS
MFP0 General purpose digital I/O pin
MFP1 UART0 data receiver input pin
P
MFP0 Ground pin for digital circuit
Jan. 28, 2019
Page 42 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
53
101
172 PF.12
I/O
O
P
I
MFP0 General purpose digital I/O pin
UART0_TXD
MFP1 UART0 data transmitter output pin
MFP0 Power supply for I/O power pin
MFP0 External 12 MHz crystal input pin
MFP0 External 12 MHz crystal output pin
MFP0 Ground pin for digital circuit
54
55
56
102
103
104
173 VDD33
174 XT_IN
175 XT_OUT
176 VSS
O
P
I/O
I
105
106
107
177 PE.0
MFP0 General purpose digital I/O pin
MFP1 RMII0 Receive Data Error input pin
MFP2 CAN0 bus receiver input
RMII0_RXERR
CAN0_RXD
I
UART4_CTS
USBHL1_DM
VCAP1_HSYNC
I
MFP5 UART4 clear to Send input pin
MFP6 USB 1.1 host lite port 1 differential signal D-
MFP7 Video image interface 1 horizontal sync. Pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Carrier Sense/Receive Data input pin
MFP2 CAN0 bus transmitter output
A
I
178 PE.1
I/O
I
RMII0_CRSDV
CAN0_TXD
O
O
A
I
UART4_RTS
USBHL1_DP
VCAP1_VSYNC
MFP5 UART4 request to Send output pin
MFP6 USB 1.1 host lite port 1 differential signal D+
MFP7 Video image interface 1 vertical sync. Pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Receive Data bus bit 1
179 PE.2
I/O
I
RMII0_RXD1
CAN1_RXD
I
MFP2 CAN1 bus receiver input
UART4_RXD
USBHL2_DM
VCAP1_DATA0
I
MFP5 UART4 data receiver input pin
MFP6 USB 1.1 host lite port 2 differential signal D-
MFP7 Video image interface 1 data 0 pin
MFP0 Power supply for internal core power pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Receive Data bus bit 0
A
I
180 VDD12
181 PE.3
RMII0_RXD0
P
I/O
I
108
CAN1_TXD
O
O
A
I
MFP2 CAN1 bus transmitter output
UART4_TXD
USBHL2_DP
VCAP1_DATA1
MFP5 UART4 data transmitter output pin
MFP6 USB 1.1 host lite port 2 differential signal D+
MFP7 Video image interface 1 data 1 pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 mode clock input pin
109
182 PE.4
RMII0_REFCLK
I/O
I
Jan. 28, 2019
Page 43 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
CAN2_RXD
I
I
MFP2 CAN2 bus receiver input
UART9_CTS
USBHL3_DM
VCAP1_DATA2
MFP5 UART9 clear to Send input pin
MFP6 USB 1.1 host lite port 3 differential signal D-
MFP7 Video image interface 1 data 2 pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Transmit Enable output pin
MFP2 CAN2 bus transmitter output
A
I
110
183 PE.5
RMII0_TXEN
I/O
O
O
O
A
I
CAN2_TXD
UART9_RTS
USBHL3_DP
VCAP1_DATA3
MFP5 UART9 request to Send output pin
MFP6 USB 1.1 host lite port 3 differential signal D+
MFP7 Video image interface 1 data 3 pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Transmit Data bus bit 1
111
184 PE.6
I/O
O
I
RMII0_TXD1
CAN3_RXD
MFP2 CAN3 bus receiver input
UART9_RXD
USBHL4_DM
VCAP1_DATA4
I
MFP5 UART9 data receiver input pin
A
I
MFP6 USB 1.1 host lite port 4 differential signal D-
MFP7 Video image interface 1 data 4 pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 Transmit Data bus bit 0
112
185 PE.7
I/O
O
O
O
A
I
RMII0_TXD0
CAN3_TXD
MFP2 CAN3 bus transmitter output.
UART9_TXD
USBHL4_DP
VCAP1_DATA5
MFP5 UART9 data transmitter output pin
MFP6 USB 1.1 host lite port 4 differential signal D+
MFP7 Video image interface 1 data 5 pin
MFP0 Power supply for I/O power pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 PHY Management Data pin
MFP5 UART6 data receiver input pin
186 VDD33
187 PE.8
RMII0_MDIO
P
I/O
I/O
I
113
UART6_RXD
USBHL5_DM
VCAP1_DATA6
A
I
MFP6 USB 1.1 host lite port 5 differential signal D-
MFP7 Video image interface 1 data 6 pin
MFP0 General purpose digital I/O pin
MFP1 RMII0 PHY Management Clock output pin
MFP5 UART6 data transmitter output pin
MFP6 USB 1.1 host lite port 5 differential signal D+
MFP7 Video image interface 1 data 7 pin
114
188 PE.9
I/O
O
O
A
I
RMII0_MDC
UART6_TXD
USBHL5_DP
VCAP1_DATA7
Jan. 28, 2019
Page 44 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
115
189 PE.10
I/O
I
MFP0 General purpose digital I/O pin
USB_OVC
MFP1 HSUSB host bus power over voltage detector
MFP2 CAN3 bus receiver input
CAN3_RXD
UART9_RXD
PWM12
I
I
MFP3 UART9 data receiver input pin
MFP4 PWM12 counter synchronous trigger output pin
MFP5 External interrupt 2 input pin
MFP6 I2C0 data input/output pin
O
I
EINT2
I2C0_SDA
VCAP1_FIELD
I/O
I
MFP7 Video image interface 1 frame sync. Pin
MFP0 General purpose digital I/O pin
MFP1 USB0 VBUS vaild indication pin
MFP0 General purpose digital I/O pin
MFP1 HSUSB host power control pin
MFP2 CAN3 bus transmitter output
MFP3 UART9 data transmitter output pin
MFP4 PWM13 counter synchronous trigger output pin
MFP5 External interrupt 3 input pin
MFP6 I2C0 clock pin
57
116
117
190 PE.11
USB0_VBUSVLD
191 PE.12
I/O
I
I/O
O
O
O
O
I
USBH_PWREN
CAN3_TXD
UART9_TXD
PWM13
EINT3
I2C0_SCL
I/O
O
P
P
P
P
P
P
VCAP1_CLKO
MFP7 Video image interface sensor 1 clock pin
MFP0 Ground pin for digital circuit
MFP0 Power supply for internal core power pin
MFP0 Ground pin for digital circuit
MFP0 Power supply for USB1 VDD12
MFP0 Power supply for USB1 VDD12
MFP0 Ground pin for USB1
192 VSS
58
118
193 VDD12
194 VSS
195 VUSB1_VDD12
196 VUSB1_VDD12
197 VUSB1_VSS
198 NC
No connect
199 NC
No connect
200 VUSB1_VSS
201 USB1_DM
202 USB1_DP
203 VUSB1_VDD33
204 VUSB1_VDD33
205 USB1_REXT
206 VUSB0_VDD12
P
A
A
P
P
A
P
MFP0 Ground pin for USB1
119
120
121
MFP0 USB1 differential signal D-
MFP0 USB1 differential signal D+
MFP0 Power supply for USB1 VDD33
MFP0 Power supply for USB1 VDD33
MFP0 USB1 module reference resister (external 12.1K to GND)
MFP0 Power supply for USB0 VDD12
59
60
122
123
Jan. 28, 2019
Page 45 of 246
Rev 1.00
NUC980
64
128 216 Pin Name
Type MFP Description
Pin
Pin
Pin
207 VUSB0_VDD12
208 VUSB0_VSS
209 NC
P
P
MFP0 Power supply for USB0 VDD12
MFP0 Ground pin for USB0
No connect
210 NC
No connect
211 VUSB0_VSS
212 USB0_DM
213 USB0_DP
214 VUSB0_VDD33
215 VUSB0_VDD33
216 USB0_REXT
VSS
P
A
A
P
P
A
P
MFP0 Ground pin for USB0.
61
62
63
124
125
126
MFP0 USB0 differential signal D-
MFP0 USB0 differential signal D+
MFP0 Power supply for USB0 VDD33
MFP0 Power supply for USB0 VDD33
MFP0 USB0 module reference resister (external 12.1K to GND)
MFP0 Ground pin for digital circuit
64
127
EPAD 128
Note: Pin Type:
1.
2.
I = Digital Input;
IU= Digital Input with internal pull high; (Rpu value please refer the GPIO Characteristics of DC Electrical
Characteristics)
3.
4.
5.
6.
7.
O= Digital Output;
I/O= Bi-direction;
A = Analog;
P = Power Pin;
AP = Analog Power
Jan. 28, 2019
Page 46 of 246
Rev 1.00
NUC980
4.2.2
NUC980 Multi-function Summary Table
Group
Pin Name
ADC_AIN0
ADC_AIN1
ADC_AIN2
ADC_AIN3
ADC_AIN4
ADC_AIN5
ADC_AIN6
ADC_AIN7
GPIO
PB.0
MFP
Type
Description
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP7
MFP4
MFP4
MFP2
MFP7
MFP4
MFP4
MFP2
MFP5
MFP4
MFP4
MFP2
MFP5
MFP4
MFP4
MFP2
MFP5
MFP4
MFP3
MFP4
MFP2
MFP5
MFP4
A
A
A
A
A
A
A
A
I
ADC channel 0 analog input
ADC channel 1 analog input
ADC channel 2 analog input
ADC channel 3 analog input
ADC channel 4 analog input
ADC channel 5 analog input
ADC channel 6 analog input
ADC channel 7 analog input
PB.1
PB.2
PB.3
ADC
PB.4
PB.5
PB.6
PB.7
PC.3
PD.6
PG.11
PE.0
I
CAN0_RXD
CAN0_TXD
CAN1_RXD
CAN1_TXD
CAN0 bus receiver input
CAN0 bus transmitter output
CAN1 bus receiver input
CAN1 bus transmitter output
I
I
CAN0
PC.4
PD.7
PG.12
PE.1
O
O
O
O
I
PA.13
PD.14
PG.13
PE.2
I
I
I
CAN1
PA.14
PD.15
PG.14
PE.3
O
O
O
O
I
PA.15
PB.1
I
CAN2_RXD
CAN2_TXD
PB.8
I
CAN2 bus receiver input
CAN2
PD.12
PE.4
I
I
PG.10
PB.3
O
O
CAN2 bus transmitter output
Jan. 28, 2019
Page 47 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PC.0
PD.13
PE.5
MFP
Type
Description
MFP3
MFP4
MFP2
MFP7
MFP2
MFP2
MFP7
MFP2
MFP2
O
O
O
I
PA.0
CAN3_RXD
CAN3_TXD
PE.6
I
CAN3 bus receiver input
PE.10
PA.1
I
CAN3
O
O
O
PE.7
CAN3 bus transmitter output
PE.12
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
CFG.0
CFG.1
CFG.2
CFG.3
CFG.4
CFG.5
CFG.6
CFG.7
CFG.8
CFG.0_PwrOnSet0
CFG.1_PwrOnSet1
CFG.2_PwrOnSet2
CFG.3_PwrOnSet3
CFG.4_PwrOnSet4
CFG.5_PwrOnSet5
CFG.6_PwrOnSet6
CFG.7_PwrOnSet7
CFG.8_PwrOnSet8
CFG.9_PwrOnSet9
PG.0
PG.1
PG.2
PG.3
PG.4
PG.5
PG.6
PG.7
PG.8
PG.9
-
-
-
-
-
-
-
-
-
-
IU
IU
IU
IU
IU
IU
IU
IU
IU
IU
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
System configuration and power on setting with an
internal pull-up. Internal pull-up only active
automatically during reset.
CFG.9
CLK
CLK_OUT
PG.0
PG.0
PG.1
PG.2
PB.2
MFP3
MFP1
MFP1
MFP1
MFP1
O
O
O
O
O
Internal clock selection output pin
EBI address bus bit 0
EBI_ADDR0
EBI_ADDR1
EBI address bus bit 1
EBI
EBI_ADDR2
EBI address bus bit 2
Jan. 28, 2019
Page 48 of 246
Rev 1.00
NUC980
Group
Pin Name
EBI_ADDR3
EBI_ADDR4
EBI_ADDR5
EBI_ADDR6
EBI_ADDR7
EBI_ADDR8
EBI_ADDR9
EBI_ADDR10
EBI_ADDR11
GPIO
PG.3
PG.6
PG.7
PG.8
PG.9
PA.12
PA.11
PA.10
PB.8
MFP
Type
O
Description
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
EBI address bus bit 3
EBI address bus bit 4
EBI address bus bit 5
EBI address bus bit 6
EBI address bus bit 7
EBI address bus bit 8
EBI address bus bit 9
EBI address bus bit 10
EBI address bus bit 11
O
O
O
O
O
O
O
O
PG.5
PB.0
O
EBI_ADDR12
EBI_ADDR13
EBI_ADDR14
EBI address bus bit 12
EBI address bus bit 13
EBI address bus bit 14
O
PA.13
PB.6
O
O
PA.14
PB.4
O
O
EBI_ADDR15
EBI_ADDR16
EBI_ADDR17
PB.7
O
EBI address bus bit 15
EBI address bus bit 16
EBI address bus bit 17
PB.5
O
PB.1
O
PG.4
PB.3
O
EBI_ADDR18
EBI_ADDR19
EBI address bus bit 18
EBI address bus bit 19
O
PA.15
PG.10
PC.0
PB.13
PC.1
PD.12
PC.2
PD.13
PC.3
PD.14
PC.4
PD.15
PC.5
PF.0
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EBI_DATA0
EBI data bus bit 0
EBI_DATA1
EBI_DATA2
EBI_DATA3
EBI_DATA4
EBI_DATA5
EBI data bus bit 1
EBI data bus bit 2
EBI data bus bit 3
EBI data bus bit 4
EBI data bus bit 5
Jan. 28, 2019
Page 49 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PC.6
PF.1
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Description
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP1
MFP8
MFP2
MFP1
MFP1
MFP1
MFP1
MFP1
MFP5
MFP8
MFP5
MFP8
MFP3
MFP4
MFP2
MFP5
EBI_DATA6
EBI data bus bit 6
PC.7
PF.2
EBI_DATA7
EBI_DATA8
EBI_DATA9
EBI_DATA10
EBI_DATA11
EBI_DATA12
EBI_DATA13
EBI_DATA14
EBI_DATA15
EBI data bus bit 7
EBI data bus bit 8
EBI data bus bit 9
EBI data bus bit 10
EBI data bus bit 11
EBI data bus bit 12
EBI data bus bit 13
EBI data bus bit 14
EBI data bus bit 15
PC.8
PF.3
PC.9
PF.4
PC.10
PF.5
PC.11
PF.6
PC.12
PF.7
PC.13
PF.8
PC.14
PF.9
PC.15
PF.10
PA.1
PA.9
PA.6
PA.1
PA.8
PA.7
PA.0
PA.13
PA.1
PA.14
PB.3
PD.0
PB.13
PE.10
EBI_MCLK
EBI_nCS0
EBI_nCS1
EBI_nCS2
EBI_nRE
EBI external clock output pin
EBI chip select 0 output pin
EBI chip select 1 output pin
EBI chip select 2 output pin
EBI read enable output pin
EBI write enable output pin
O
O
O
O
EBI_nWE
O
I
EINT0
EINT1
EINT0
EINT1
External interrupt 0 input pin
External interrupt 1 input pin
I
I
I
I
I
EINT2
EINT2
External interrupt 2 input pin
I
I
Jan. 28, 2019
Page 50 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PD.1
PG.15
PE.12
PA.1
MFP
Type
I
Description
MFP4
MFP4
MFP5
MFP3
MFP2
MFP6
MFP3
MFP2
MFP6
MFP2
MFP2
MFP4
MFP2
MFP2
MFP4
MFP2
MFP2
MFP2
MFP2
MFP2
MFP3
MFP2
MFP3
MFP2
MFP8
MFP3
MFP2
MFP3
MFP2
MFP3
MFP2
MFP8
MFP3
MFP2
EINT3
EINT3
I
External interrupt 3 input pin
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
PG.10
PE.12
PA.0
I2C0 clock pin
I2C0
PA.15
PE.10
PA.14
PB.4
I2C0 data input/output pin
I2C1 clock pin
PC.3
PA.13
PB.6
I2C1
I2C1 data input/output pin
PC.4
PB.5
I2C2_SCL
I2C2_SDA
I2C3_SCL
I2C3_SDA
I2C2 clock pin
PB.8
I2C2
I2C3
PB.7
I2C2 data input/output pin
I2C3 clock pin
PC.0
PB.3
PD.14
PB.1
I2C3 data input/output pin
PD.15
PA.3
I2S_BCLK
PG.10
PB.4
O
I2S_ bit clock output pin
O
PA.4
I
I2S_DI
I2S_ data input pin
I2S_ data output pin
PB.7
I
I2S
PA.5
O
I2S_DO
PB.5
O
PA.2
O
I2S_LRCK
I2S_MCLK
PA.15
PB.6
O
I2S_ left right channel clock output pin
I2S_ master clock output pin
O
PA.6
O
Jan. 28, 2019
Page 51 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PB.1
MFP
Type
O
I
Description
MFP3
MFP7
MFP7
MFP7
MFP7
MFP7
MFP4
MFP4
MFP4
MFP4
MFP4
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP7
MFP6
MFP6
MFP4
MFP7
MFP6
MFP6
MFP4
JTAG0_TCK
JTAG0_TDI
PG.12
PG.14
PG.11
PG.13
PG.15
PA.3
JTAG0 clock input pin
I
JTAG0 data input pin
JTAG0
JTAG0_TDO
JTAG0_TMS
JTAG0_nTRST
JTAG1_TCK
JTAG1_TDI
O
I
JTAG0 data output pin
JTAG0 test mode selection input pin
JTAG0 reset input pin
I
I
JTAG1 clock input pin
PA.5
I
JTAG1 data input pin
JTAG1
JTAG1_TDO
JTAG1_TMS
JTAG1_nTRST
NAND_ALE
PA.2
O
I
JTAG1 data output pin
PA.4
JTAG1 test mode selection input pin
JTAG1 reset input pin
PA.6
I
PC.3
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
NAND Flash address latch enable
NAND Flash command latch enable
NAND Flash data bus bit 0
NAND Flash data bus bit 1
NAND Flash data bus bit 2
NAND Flash data bus bit 3
NAND Flash data bus bit 4
NAND Flash data bus bit 5
NAND Flash data bus bit 6
NAND Flash data bus bit 7
NAND Flash ready/busy pin
NAND Flash chip enable input
NAND Flash read enable
NAND Flash write enable
NAND Flash write protect input.
NAND_CLE
PC.4
NAND_DATA0
NAND_DATA1
NAND_DATA2
NAND_DATA3
NAND_DATA4
NAND_DATA5
NAND_DATA6
NAND_DATA7
NAND_RDY0
NAND_nCS0
NAND_nRE
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PC.7
NAND
PC.1
O
O
O
O
O
O
O
O
O
O
O
O
PC.6
NAND_nWE
NAND_nWP
PC.5
PC.2
PG.10
PG.0
PD.12
PF.5
PWM00
PWM01
PWM00 counter synchronous trigger output pin
PWM0
PA.15
PG.1
PD.13
PF.6
PWM01 counter synchronous trigger output pin
Jan. 28, 2019
Page 52 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PA.14
PG.2
PD.14
PB.13
PF.7
MFP
Type
O
Description
MFP7
MFP6
MFP6
MFP4
MFP4
MFP7
MFP6
MFP6
MFP4
MFP6
MFP2
MFP6
MFP4
MFP6
MFP2
MFP6
MFP4
MFP6
MFP2
MFP6
MFP4
MFP6
MFP2
MFP6
MFP4
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
O
PWM02
O
PWM02 counter synchronous trigger output pin
O
O
PA.13
PG.3
PD.15
PF.8
O
O
PWM03
PWM10
PWM11
PWM12
PWM13
PWM03 counter synchronous trigger output pin
PWM10 counter synchronous trigger output pin
PWM11 counter synchronous trigger output pin
PWM12 counter synchronous trigger output pin
PWM13 counter synchronous trigger output pin
O
O
PG.6
PB.12
PG.11
PF.9
O
O
O
O
PG.7
PB.11
PG.12
PF.10
PG.8
PB.10
PG.13
PE.10
PG.9
PB.9
O
O
O
O
PWM1
O
O
O
O
O
O
PG.14
PE.12
PD.3
O
O
QSPI0_CLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Quad SPI0 serial clock pin
QSPI0_MISO0
QSPI0_MISO1
QSPI0_MOSI0
QSPI0_MOSI1
QSPI0_SS0
PD.5
Quad SPI0 MISO0 (Master In, Slave Out) pin
Quad SPI0 MISO1 (Master In, Slave Out) pin
Quad SPI0 MOSI0 (Master Out, Slave In) pin
Quad SPI0 MOSI1 (Master Out, Slave In) pin
Quad SPI0 slave select 0 pin
PD.7
PD.4
QSPI0
PD.6
PD.2
PA.0
QSPI0_SS1
Quad SPI0 slave select 1 pin
PD.0
RMII0
RMII0_CRSDV
PE.1
RMII0 Carrier Sense/Receive Data input pin
Jan. 28, 2019
Page 53 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PE.9
PE.8
PE.4
PE.3
PE.2
PE.0
PE.7
PE.6
PE.5
PF.1
PF.9
PF.8
PF.4
PF.3
PF.2
PF.0
PF.7
PF.6
PF.5
PA.2
PC.15
PA.5
PC.12
PA.4
PC.13
PA.3
PC.14
PA.6
PC.11
PC.10
PF.4
PC.7
PF.1
PC.8
MFP
Type
Description
RMII0_MDC
RMII0_MDIO
RMII0_REFCLK
RMII0_RXD0
RMII0_RXD1
RMII0_RXERR
RMII0_TXD0
RMII0_TXD1
RMII0_TXEN
RMII1_CRSDV
RMII1_MDC
RMII1_MDIO
RMII1_REFCLK
RMII1_RXD0
RMII1_RXD1
RMII1_RXERR
RMII1_TXD0
RMII1_TXD1
RMII1_TXEN
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP3
MFP4
MFP3
MFP4
MFP3
MFP4
MFP3
MFP4
MFP3
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
O
I/O
I
RMII0 PHY Management Clock output pin
RMII0 PHY Management Data pin
RMII0 mode clock input pin
I
RMII0 Receive Data bus bit 0
RMII0 Receive Data bus bit 1
RMII0 Receive Data Error input pin
RMII0 Transmit Data bus bit 0
RMII0 Transmit Data bus bit 1
RMII0 Transmit Enable output pin
RMII1 Carrier Sense/Receive Data input pin
RMII1 PHY Management Clock output pin
RMII1 PHY Management Data pin
RMII1 mode clock input pin
I
I
O
O
O
I
O
I/O
I
I
RMII1 Receive Data bus bit 0
RMII1 Receive Data bus bit 1
RMII1 Receive Data Error input pin
RMII1 Transmit Data bus bit 0
RMII1 Transmit Data bus bit 1
RMII1 Transmit Enable output pin
RMII1
I
I
O
O
O
I
SC0_CD
Smart Card 0 card detect pin
Smart Card 0 clock pin
Smart Card 0 data pin
I
O
O
I/O
I/O
O
O
O
O
I
SC0_CLK
SC0_DAT
SC0_PWR
SC0_RST
SC1_CD
SC0
Smart Card 0 power pin
Smart Card 0 reset pin
Smart Card 1 card detect pin
I
SC1
O
O
I/O
SC1_CLK
SC1_DAT
Smart Card 1 clock pin
Smart Card 1 data pin
Jan. 28, 2019
Page 54 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PF.2
PC.9
PF.3
PC.6
PF.0
PC.6
PC.5
PC.7
PC.8
PC.9
PC.10
PB.8
PC.12
PF.1
PF.0
PF.2
PF.3
PF.4
PF.5
PF.6
PC.6
PD.9
PC.8
PD.11
PC.4
PC.7
PC.14
PD.10
PC.5
PD.8
PB.3
PC.0
PD.1
PG.15
MFP
Type
I/O
O
Description
MFP4
MFP4
MFP4
MFP4
MFP4
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP5
MFP1
MFP5
MFP1
MFP6
MFP5
MFP5
MFP1
MFP5
MFP1
MFP6
MFP5
MFP1
MFP1
SC1_PWR
SC1_RST
Smart Card 1 power pin
Smart Card 1 reset pin
O
O
O
SD0_CLK
O
SD0 clock output pin
SD0 command/response pin
SD0 data line bit 0
SD0_CMD
I/O
I/O
I/O
I/O
I/O
I
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD0 data line bit 1
SD0
SD0 data line bit 2
SD0 data line bit 3
SD0_nCD
SD0 card detect input pin
I
SD1_CLK
O
SD1 clock output pin
SD1 command/response pin
SD1 data line bit 0
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD1_nCD
I/O
I/O
I/O
I/O
I/O
I
SD1
SD1 data line bit 1
SD1 data line bit 2
SD1 data line bit 3
SD1 card detect input pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI0_CLK
SPI0 serial clock pin
SPI0_MISO
SPI0 MISO (Master In, Slave Out) pin
SPI0_MOSI
SPI0_SS0
SPI0_SS1
SPI0 MOSI (Master Out, Slave In) pin
SPI0 slave select 0 pin
SPI0
SPI0 slave select 1 pin
Jan. 28, 2019
Page 55 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PG.10
PB.4
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP6
MFP6
MFP5
MFP2
MFP6
MFP5
MFP2
MFP6
MFP5
MFP2
MFP6
MFP6
MFP5
MFP2
MFP6
MFP2
MFP5
MFP7
MFP3
MFP6
MFP3
MFP3
MFP5
MFP7
MFP3
MFP3
MFP3
MFP3
MFP3
MFP6
MFP3
MFP3
MFP3
MFP3
SPI1_CLK
SPI1 serial clock pin
PB.10
PG.12
PB.5
SPI1_MISO
SPI1_MOSI
PB.12
PG.14
PB.7
SPI1 MISO (Master In, Slave Out) pin
SPI1 MOSI (Master Out, Slave In) pin
SPI1
PB.11
PG.13
PA.15
PB.6
SPI1_SS0
SPI1 slave select 0 pin
SPI1 slave select 1 pin
PB.9
PG.11
PB.1
SPI1_SS1
TM0_EXT
PG.15
PB.1
PB.8
Timer0 external capture input/toggle output pin
Timer0 event counter input/toggle output pin
Timer0 event counter input/toggle output pin
PB.10
PA.0
TM0
TM0_ECNT
TM0_TGL
PD.6
PF.0
PB.3
PC.0
PB.9
PA.13
PD.1
PG.12
PF.9
TM1_EXT
Timer1 external capture input/toggle output pin
Timer1 event counter input/toggle output pin
TM1
PA.1
TM1_ECNT
TM1_TGL
PD.7
PF.1
PA.14
PD.0
Timer1 event counter input/toggle output pin
Jan. 28, 2019
Page 56 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PG.11
PF.8
MFP
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
MFP3
MFP3
MFP3
MFP3
MFP2
MFP6
MFP3
MFP3
MFP3
MFP3
MFP2
MFP3
MFP2
MFP6
MFP3
MFP3
MFP3
MFP2
MFP3
MFP3
MFP3
MFP6
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP6
MFP3
MFP3
MFP3
PA.9
TM2_EXT
PB.11
PD.13
PA.2
Timer2 external capture input/toggle output pin
Timer2 event counter input/toggle output pin
TM2
TM2_ECNT
PD.8
PF.2
PA.10
PB.12
PD.12
PA.7
TM2_TGL
TM3_EXT
TM3_ECNT
TM3_TGL
TM4_EXT
Timer2 event counter input/toggle output pin
Timer3 external capture input/toggle output pin
Timer3 event counter input/toggle output pin
Timer3 event counter input/toggle output pin
Timer4 external capture input/toggle output pin
PD.15
PA.3
TM3
TM4
TM5
PD.9
PF.3
PA.8
PD.14
PA.11
PD.2
PF.6
PA.4
TM4_ECNT
TM4_TGL
TM5_EXT
PD.10
PF.4
Timer4 event counter input/toggle output pin
Timer4 event counter input/toggle output pin
Timer5 external capture input/toggle output pin
Timer5 event counter input/toggle output pin
PA.12
PD.3
PB.13
PA.15
PD.4
PF.7
PA.5
TM5_ECNT
TM5_TGL
PD.11
PF.5
PG.10
Timer5 event counter input/toggle output pin
Jan. 28, 2019
Page 57 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PD.5
PF.10
PF.11
PF.12
PC.8
PF.7
PC.7
PF.8
PA.0
PC.6
PF.9
PA.1
PC.5
PF.10
PA.7
PG.2
PB.0
PA.8
PG.3
PA.9
PG.0
PD.7
PA.10
PG.1
PD.6
PB.12
PD.5
PF.4
PB.11
PD.4
PF.5
PC.4
PB.10
PD.3
MFP
Type
Description
MFP3
MFP3
MFP1
MFP1
MFP7
MFP2
MFP7
MFP2
MFP4
MFP7
MFP2
MFP4
MFP7
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP1
MFP2
MFP5
MFP1
MFP2
MFP5
MFP5
MFP1
MFP2
I/O
I/O
I
UART0_RXD
UART0_TXD
UART0 data receiver input pin
UART0
O
I
UART0 data transmitter output pin
UART1_CTS
UART1_RTS
UART1 clear to Send input pin
I
O
O
I
UART1 request to Send output pin
UART1
UART1_RXD
UART1_TXD
I
UART1 data receiver input pin
I
O
O
O
I
UART1 data transmitter output pin
UART2_CTS
UART2_RTS
UART2_RXD
I
UART2 clear to Send input pin
UART2 request to Send output pin
UART2 data receiver input pin
I
O
O
I
UART2
I
I
O
O
O
I
UART2_TXD
UART3_CTS
UART3_RTS
UART3_RXD
UART2 data transmitter output pin
UART3 clear to Send input pin
UART3 request to Send output pin
UART3 data receiver input pin
I
I
O
O
O
I
UART3
I
I
Jan. 28, 2019
Page 58 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PF.6
MFP
Type
Description
MFP5
MFP5
MFP1
MFP2
MFP5
MFP5
MFP1
MFP5
MFP1
MFP5
MFP7
MFP1
MFP5
MFP7
MFP1
MFP5
MFP2
MFP5
MFP2
MFP5
MFP2
MFP2
MFP5
MFP2
MFP2
MFP5
MFP1
MFP2
MFP1
MFP2
MFP1
MFP2
MFP5
MFP1
I
PC.3
PB.9
O
O
O
O
O
I
UART3_TXD
PD.2
PB.13
PF.7
UART3 data transmitter output pin
PD.15
PE.0
UART4_CTS
UART4_RTS
UART4 clear to Send input pin
I
PD.14
PE.1
O
O
I
UART4 request to Send output pin
PC.10
PD.13
PE.2
UART4
UART4_RXD
UART4_TXD
I
UART4 data receiver input pin
I
PC.9
PD.12
PE.3
O
O
O
I
UART4 data transmitter output pin
PG.4
PG.11
PG.5
PG.12
PG.6
PD.1
PG.13
PG.7
PD.0
PG.14
PA.2
UART5_CTS
UART5_RTS
UART5 clear to Send input pin
I
O
O
I
UART5 request to Send output pin
UART5
UART5_RXD
UART5_TXD
I
UART5 data receiver input pin
I
O
O
O
I
UART5 data transmitter output pin
UART6_CTS
UART6_RTS
UART6 clear to Send input pin
PD.8
PA.3
I
O
O
I
UART6 request to Send output pin
PD.9
PA.4
UART6
UART6_RXD
UART6_TXD
PD.11
PE.8
I
UART6 data receiver input pin
I
PA.5
O
UART6 data transmitter output pin
Jan. 28, 2019
Page 59 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PD.10
PE.9
MFP
Type
Description
MFP2
MFP5
MFP5
MFP5
MFP5
MFP5
MFP6
MFP5
MFP4
MFP5
MFP6
MFP5
MFP4
MFP5
MFP2
MFP7
MFP2
MFP7
MFP2
MFP4
MFP7
MFP2
MFP4
MFP7
MFP5
MFP7
MFP5
MFP7
MFP5
MFP3
MFP7
MFP5
MFP3
MFP1
O
O
I
PB.7
UART7_CTS
UART7_RTS
UART7 clear to Send input pin
PF.0
I
PB.5
O
O
I
UART7 request to Send output pin
PF.1
PA.14
PB.4
I
UART7
UART7_RXD
UART7_TXD
UART7 data receiver input pin
PC.2
PF.2
I
I
PA.13
PB.6
O
O
O
O
I
UART7 data transmitter output pin
PC.1
PF.3
PG.9
PC.15
PG.8
PC.14
PA.11
PC.0
PC.13
PA.12
PB.8
UART8_CTS
UART8_RTS
UART8 clear to Send input pin
I
O
O
I
UART8 request to Send output pin
UART8
UART8_RXD
UART8_TXD
I
UART8 data receiver input pin
I
O
O
O
I
UART8 data transmitter output pin
PC.12
PE.4
UART9_CTS
UART9_RTS
UART9 clear to Send input pin
PB.2
O
O
I
UART9 request to Send output pin
PE.5
PB.3
UART9
UART9_RXD
PE.6
I
UART9 data receiver input pin
PE.10
PB.1
I
O
O
O
I
UART9_TXD
PE.7
UART9 data transmitter output pin
USB0 VBUS vaild indication pin
PE.12
PE.11
USB0
USB0_VBUSVLD
Jan. 28, 2019
Page 60 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PB.6
PB.7
PB.9
PD.14
PB.4
PB.5
PB.10
PD.15
PF.0
MFP
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Description
MFP4
MFP4
MFP4
MFP5
MFP4
MFP4
MFP4
MFP5
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP4
MFP6
MFP6
MFP4
MFP6
MFP6
MFP6
MFP4
MFP4
MFP6
MFP6
MFP4
MFP4
MFP6
USBHL0_DM
USB 1.1 Host Lite port 0 differential signal D-
USBHL0
USBHL0_DP
USB 1.1 Host Lite port 0 differential signal D+
USBHL1_DM
USBHL1_DP
USBHL2_DM
USBHL2_DP
USBHL3_DM
USBHL3_DP
USB 1.1 Host Lite port 1 differential signal D-
USB 1.1 Host Lite port 1 differential signal D+
USB 1.1 Host Lite port 2 differential signal D-
USB 1.1 Host Lite port 2 differential signal D+
USB 1.1 Host Lite port 3 differential signal D-
USB 1.1 Host Lite port 3 differential signal D+
PE.0
PF.1
USBHL1
USBHL2
USBHL3
PE.1
PF.2
PE.2
PF.3
PE.3
PF.4
PE.4
PF.5
PE.5
PA.15
PF.6
USBHL4_DM
USBHL4_DP
USB 1.1 Host Lite port 4 differential signal D-
USB 1.1 Host Lite port 4 differential signal D+
PE.6
PG.10
PB.13
PF.7
USBHL4
PE.7
PA.13
PB.11
PF.8
USBHL5_DM
USBHL5_DP
USB 1.1 Host Lite port 5 differential signal D-
USB 1.1 Host Lite port 5 differential signal D+
USBHL5
PE.8
PA.14
PB.12
PF.9
Jan. 28, 2019
Page 61 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PE.9
MFP
Type
Description
MFP6
MFP1
MFP1
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP1
MFP6
MFP6
MFP6
MFP6
A
USBH
USB
USBH_PWREN
USB_OVC
PE.12
PE.10
PC.3
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
PC.14
PC.15
PC.7
PC.5
PC.4
PC.6
PE.12
PE.2
O
HSUSB host power control pin
I
USB host bus power over voltage detector
Video image interface 0 sensor clock pin
Video image interface 0 data 0 pin
Video image interface 0 data 1 pin
Video image interface 0 data 2 pin
Video image interface 0 data 3 pin
Video image interface 0 data 4 pin
Video image interface 0 data 5 pin
Video image interface 0 data 6 pin
Video image interface 0 data 7 pin
Video image interface 0 frame sync. Pin
Video image interface 0 horizontal sync. Pin
Video image interface 0 pixel clock pin
Video image interface 0 vertical sync. Pin
Video image interface 1 sensor clock pin
Video image interface 1 data 0 pin
Video image interface 1 data 1 pin
Video image interface 1 data 2 pin
Video image interface 1 data 3 pin
Video image interface 1 data 4 pin
Video image interface 1 data 5 pin
Video image interface 1 data 6 pin
Video image interface 1 data 7 pin
Video image interface 1 frame sync. Pin
Video image interface 1 horizontal sync. Pin
Video image interface 1 pixel clock pin
Video image interface 1 vertical sync. Pin
Watch dog timer reset trigger output
eMMC0 clock output pin
VCAP0_CLKO
VCAP0_DATA0
VCAP0_DATA1
VCAP0_DATA2
VCAP0_DATA3
VCAP0_DATA4
VCAP0_DATA5
VCAP0_DATA6
VCAP0_DATA7
VCAP0_FIELD
VCAP0_HSYNC
VCAP0_PCLK
VCAP0_VSYNC
VCAP1_CLKO
VCAP1_DATA0
VCAP1_DATA1
VCAP1_DATA2
VCAP1_DATA3
VCAP1_DATA4
VCAP1_DATA5
VCAP1_DATA6
VCAP1_DATA7
VCAP1_FIELD
VCAP1_HSYNC
VCAP1_PCLK
VCAP1_VSYNC
WDT_nRST
O
I
I
I
I
I
VCAP0
I
I
I
I
I
I
I
O
I
PE.3
I
PE.4
I
PE.5
I
PE.6
I
VCAP1
PE.7
I
PE.8
I
PE.9
I
PE.10
PE.0
I
I
PF.10
PE.1
I
I
WDT
nRESET
PC.6
PC.5
PC.7
PC.8
O
O
I/O
I/O
I/O
eMMC0_CLK
eMMC0_CMD
eMMC0_DATA0
eMMC0_DATA1
eMMC0 command/response pin
eMMC0
eMMC0 data line bit 0
eMMC0 data line bit 1
Jan. 28, 2019
Page 62 of 246
Rev 1.00
NUC980
Group
Pin Name
GPIO
PC.9
PC.10
PF.1
PF.0
PF.2
PF.3
PF.4
PF.5
MFP
Type
I/O
I/O
O
Description
eMMC0_DATA2
eMMC0_DATA3
eMMC1_CLK
MFP6
MFP6
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
eMMC0 data line bit 2
eMMC0 data line bit 3
eMMC1 clock output pin
eMMC1 command/response pin
eMMC1 data line bit 0
eMMC1 data line bit 1
eMMC1 data line bit 2
eMMC1 data line bit 3
eMMC1_CMD
eMMC1_DATA0
eMMC1_DATA1
eMMC1_DATA2
eMMC1_DATA3
I/O
I/O
I/O
I/O
I/O
eMMC1
Jan. 28, 2019
Page 63 of 246
Rev 1.00
NUC980
4.2.3
NUC980 Multi-function Summary Table Sorted by GPIO
Pin Name
PA.0
Type
I/O
I/O
I/O
I
MFP
Description
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin
Quad SPI0 slave select 1 pin
I2C0 data input/output pin
QSPI0_SS1
I2C0_SDA
UART1_RXD
EINT0
PA.0
UART1 data receiver input pin
External interrupt 0 input pin
Timer0 event counter input/toggle output pin
CAN3 bus receiver input
I
TM0_ECNT
CAN3_RXD
PA.1
I/O
I
I/O
O
General purpose digital I/O pin
EBI chip select 2 output pin
EBI external clock output pin
I2C0 clock pin
EBI_nCS2
EBI_MCLK
I2C0_SCL
UART1_TXD
EINT1
O
I/O
O
PA.1
UART1 data transmitter output pin
External interrupt 1 input pin
Timer1 event counter input/toggle output pin
CAN3 bus transmitter output
General purpose digital I/O pin
UART6 clear to Send input pin
I2S_ left right channel clock output pin
Smart Card 0 card detect pin
JTAG1 data output pin
I
TM1_ECNT
CAN3_TXD
PA.2
I/O
O
I/O
I
UART6_CTS
I2S_LRCK
SC0_CD
O
PA.2
I
JTAG1_TDO
TM2_ECNT
PA.3
O
I/O
I/O
O
Timer2 event counter input/toggle output pin
General purpose digital I/O pin
UART6 request to Send output pin
I2S_ bit clock output pin
UART6_RTS
I2S_BCLK
SC0_PWR
JTAG1_TCK
TM3_ECNT
PA.4
O
PA.3
O
Smart Card 0 power pin
I
JTAG1 clock input pin
I/O
I/O
I
Timer3 event counter input/toggle output pin
General purpose digital I/O pin
UART6 data receiver input pin
I2S_ data input pin
UART6_RXD
I2S_DI
PA.4
I
SC0_DAT
JTAG1_TMS
I/O
I
Smart Card 0 data pin
JTAG1 test mode selection input pin
Jan. 28, 2019
Page 64 of 246
Rev 1.00
NUC980
Pin Name
TM4_ECNT
PA.5
Type
I/O
I/O
O
MFP
Description
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
Timer4 event counter input/toggle output pin
General purpose digital I/O pin
UART6 data transmitter output pin
I2S_ data output pin
UART6_TXD
I2S_DO
O
PA.5
SC0_CLK
JTAG1_TDI
TM5_ECNT
PA.6
O
Smart Card 0 clock pin
I
JTAG1 data input pin
I/O
I/O
O
Timer5 event counter input/toggle output pin
General purpose digital I/O pin
EBI chip select 1 output pin
EBI_nCS1
I2S_MCLK
SC0_RST
JTAG1_nTRST
PA.7
PA.6
O
I2S_ master clock output pin
Smart Card 0 reset pin
O
I
JTAG1 reset input pin
I/O
O
General purpose digital I/O pin
EBI write enable output pin
EBI_nWE
UART2_CTS
TM3_EXT
PA.8
PA.7
PA.8
PA.9
PA.10
I
UART2 clear to Send input pin
Timer3 external capture input/toggle output pin
General purpose digital I/O pin
EBI read enable output pin
I/O
I/O
O
EBI_nRE
UART2_RTS
TM3_TGL
PA.9
O
UART2 request to Send output pin
Timer3 event counter input/toggle output pin
General purpose digital I/O pin
EBI chip select 0 output pin
I/O
I/O
O
EBI_nCS0
UART2_RXD
TM2_EXT
PA.10
I
UART2 data receiver input pin
Timer2 external capture input/toggle output pin
General purpose digital I/O pin
EBI address bus bit 10
I/O
I/O
O
EBI_ADDR10
UART2_TXD
TM2_TGL
PA.11
O
UART2 data transmitter output pin
Timer2 event counter input/toggle output pin
General purpose digital I/O pin
EBI address bus bit 9
I/O
I/O
O
EBI_ADDR9
UART8_RXD
TM4_EXT
PA.12
PA.11
PA.12
I
UART8 data receiver input pin
Timer4 external capture input/toggle output pin
General purpose digital I/O pin
EBI address bus bit 8
I/O
I/O
O
EBI_ADDR8
Jan. 28, 2019
Page 65 of 246
Rev 1.00
NUC980
Pin Name
UART8_TXD
TM4_TGL
PA.13
Type
O
MFP
Description
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP8
MFP0
UART8 data transmitter output pin
Timer4 event counter input/toggle output pin
General purpose digital I/O pin
EBI address bus bit 13
I/O
I/O
O
EBI_ADDR13
I2C1_SDA
TM1_EXT
USBHL5_DM
CAN1_RXD
UART7_TXD
PWM03
I/O
I/O
A
I2C1 data input/output pin
Timer1 external capture input/toggle output pin
USB 1.1 Host Lite port 5 differential signal D-
CAN1 bus receiver input
PA.13
PA.14
PA.15
I
O
UART7 data transmitter output pin
PWM03 counter synchronous trigger output pin
External interrupt 0 input pin
O
EINT0
I
PA.14
I/O
O
General purpose digital I/O pin
EBI address bus bit 14
EBI_ADDR14
I2C1_SCL
TM1_TGL
USBHL5_DP
CAN1_TXD
UART7_RXD
PWM02
I/O
I/O
A
I2C1 clock pin
Timer1 event counter input/toggle output pin
USB 1.1 Host Lite port 5 differential signal D+
CAN1 bus transmitter output
O
I
UART7 data receiver input pin
PWM02 counter synchronous trigger output pin
External interrupt 1 input pin
O
EINT1
I
PA.15
I/O
O
General purpose digital I/O pin
EBI address bus bit 19
EBI_ADDR19
I2C0_SDA
TM5_EXT
USBHL4_DM
CAN2_RXD
SPI1_SS0
PWM01
I/O
I/O
A
I2C0 data input/output pin
Timer5 external capture input/toggle output pin
USB 1.1 Host Lite port 4 differential signal D-
CAN2 bus receiver input
I
I/O
O
SPI1 slave select 0 pin
PWM01 counter synchronous trigger output pin
I2S_ left right channel clock output pin
General purpose digital I/O pin
EBI address bus bit 12
I2S_LRCK
PB.0
O
I/O
O
EBI_ADDR12
UART2_CTS
ADC_AIN0
PB.1
PB.0
PB.1
I
UART2 clear to Send input pin
ADC channel 0 analog input
A
I/O
General purpose digital I/O pin
Jan. 28, 2019
Page 66 of 246
Rev 1.00
NUC980
Pin Name
EBI_ADDR17
I2C3_SDA
I2S_MCLK
CAN2_RXD
TM0_EXT
SPI1_SS1
UART9_TXD
ADC_AIN1
PB.2
Type
O
MFP
Description
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
EBI address bus bit 17
I/O
O
I2C3 data input/output pin
I2S_ master clock output pin
CAN2 bus receiver input
I
I/O
I/O
O
Timer0 external capture input/toggle output pin
SPI1 slave select 1 pin
UART9 data transmitter output pin
ADC channel 1 analog input
General purpose digital I/O pin
EBI address bus bit 2
A
I/O
O
EBI_ADDR2
UART9_RTS
ADC_AIN2
PB.3
PB.2
O
UART9 request to Send output pin
ADC channel 2 analog input
General purpose digital I/O pin
EBI address bus bit 18
A
I/O
O
EBI_ADDR18
I2C3_SCL
EINT2
I/O
I
I2C3 clock pin
External interrupt 2 input pin
CAN2 bus transmitter output
Timer0 event counter input/toggle output pin
SPI0 slave select 1 pin
PB.3
CAN2_TXD
TM0_TGL
SPI0_SS1
UART9_RXD
ADC_AIN3
PB.4
O
I/O
I/O
I
UART9 data receiver input pin
ADC channel 3 analog input
General purpose digital I/O pin
EBI address bus bit 14
A
I/O
O
EBI_ADDR14
I2C1_SCL
I2S_BCLK
USBHL0_DP
UART7_RXD
SPI1_CLK
ADC_AIN4
PB.5
I/O
O
I2C1 clock pin
I2S_ bit clock output pin
PB.4
A
USB 1.1 Host Lite port 0 differential signal D+
UART7 data receiver input pin
SPI1 serial clock pin
I
I/O
A
ADC channel 4 analog input
General purpose digital I/O pin
EBI address bus bit 16
I/O
O
EBI_ADDR16
I2C2_SCL
I2S_DO
PB.5
I/O
O
I2C2 clock pin
I2S_ data output pin
USBHL0_DP
A
USB 1.1 Host Lite port 0 differential signal D+
Jan. 28, 2019
Page 67 of 246
Rev 1.00
NUC980
Pin Name
UART7_RTS
SPI1_MISO
ADC_AIN5
PB.6
Type
O
MFP
Description
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
UART7 request to Send output pin
SPI1 MISO (Master In, Slave Out) pin
ADC channel 5 analog input
I/O
A
I/O
O
General purpose digital I/O pin
EBI address bus bit 13
EBI_ADDR13
I2C1_SDA
I2S_LRCK
USBHL0_DM
UART7_TXD
SPI1_SS0
ADC_AIN6
PB.7
I/O
O
I2C1 data input/output pin
I2S_ left right channel clock output pin
USB 1.1 Host Lite port 0 differential signal D-
UART7 data transmitter output pin
SPI1 slave select 0 pin
PB.6
A
O
I/O
A
ADC channel 6 analog input
I/O
O
General purpose digital I/O pin
EBI address bus bit 15
EBI_ADDR15
I2C2_SDA
I2S_DI
I/O
I
I2C2 data input/output pin
I2S_ data input pin
PB.7
USBHL0_DM
UART7_CTS
SPI1_MOSI
ADC_AIN7
PB.8
A
USB 1.1 Host Lite port 0 differential signal D-
UART7 clear to Send input pin
SPI1 MOSI (Master Out, Slave In) pin
ADC channel 7 analog input
I
I/O
A
I/O
O
General purpose digital I/O pin
EBI address bus bit 11
EBI_ADDR11
I2C2_SCL
CAN2_RXD
UART8_TXD
SD0_nCD
TM0_EXT
PB.9
I/O
I
I2C2 clock pin
PB.8
CAN2 bus receiver input
O
UART8 data transmitter output pin
SD0 card detect input pin
I
I/O
I/O
O
Timer0 external capture input/toggle output pin
General purpose digital I/O pin
UART3 data transmitter output pin
PWM13 counter synchronous trigger output pin
Timer0 event counter input/toggle output pin
USB 1.1 Host Lite port 0 differential signal D-
SPI1 slave select 0 pin
UART3_TXD
PWM13
O
PB.9
TM0_TGL
USBHL0_DM
SPI1_SS0
PB.10
I/O
A
I/O
I/O
I
General purpose digital I/O pin
UART3 data receiver input pin
PB.10
UART3_RXD
Jan. 28, 2019
Page 68 of 246
Rev 1.00
NUC980
Pin Name
PWM12
Type
O
MFP
Description
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP3
MFP4
PWM12 counter synchronous trigger output pin
Timer0 external capture input/toggle output pin
USB 1.1 Host Lite port 0 differential signal D+
SPI1 serial clock pin
TM0_EXT
USBHL0_DP
SPI1_CLK
PB.11
I/O
A
I/O
I/O
O
General purpose digital I/O pin
UART3_RTS
PWM11
UART3 request to Send output pin
PWM11 counter synchronous trigger output pin
Timer2 external capture input/toggle output pin
USB 1.1 Host Lite port 5 differential signal D-
SPI1 MOSI (Master Out, Slave In) pin
General purpose digital I/O pin
O
PB.11
TM2_EXT
USBHL5_DM
SPI1_MOSI
PB.12
I/O
A
I/O
I/O
I
UART3_CTS
PWM10
UART3 clear to Send input pin
O
PWM10 counter synchronous trigger output pin
Timer2 event counter input/toggle output pin
USB 1.1 Host Lite port 5 differential signal D+
SPI1 MISO (Master In, Slave Out) pin
General purpose digital I/O pin
PB.12
TM2_TGL
USBHL5_DP
SPI1_MISO
PB.13
I/O
A
I/O
I/O
I
EINT2
External interrupt 2 input pin
TM4_TGL
PWM02
I/O
O
Timer4 event counter input/toggle output pin
PWM02 counter synchronous trigger output pin
UART3 data transmitter output pin
USB 1.1 Host Lite port 4 differential signal D+
EBI data bus bit 0
PB.13
UART3_TXD
USBHL4_DP
EBI_DATA0
PC.0
O
A
I/O
I/O
I/O
I/O
O
General purpose digital I/O pin
EBI_DATA0
I2C2_SDA
CAN2_TXD
UART8_RXD
SPI0_SS1
TM0_TGL
PC.1
EBI data bus bit 0
I2C2 data input/output pin
PC.0
CAN2 bus transmitter output
I
UART8 data receiver input pin
I/O
I/O
I/O
I/O
O
SPI0 slave select 1 pin
Timer0 event counter input/toggle output pin
General purpose digital I/O pin
EBI_DATA1
NAND_nCS0
UART7_TXD
EBI data bus bit 1
PC.1
NAND Flash chip enable input
O
UART7 data transmitter output pin
Jan. 28, 2019
Page 69 of 246
Rev 1.00
NUC980
Pin Name
PC.2
Type
I/O
I/O
O
MFP
Description
MFP0
MFP1
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP5
MFP6
General purpose digital I/O pin
EBI data bus bit 2
EBI_DATA2
NAND_nWP
UART7_RXD
PC.3
PC.2
NAND Flash write protect input
UART7 data receiver input pin
General purpose digital I/O pin
EBI data bus bit 3
I
I/O
I/O
O
EBI_DATA3
VCAP0_CLKO
NAND_ALE
I2C1_SCL
Video image interface 0 sensor clock pin
NAND Flash address latch enable
I2C1 clock pin
PC.3
O
I/O
O
UART3_TXD
CAN0_RXD
PC.4
UART3 data transmitter output pin
CAN0 bus receiver input
I
I/O
I/O
I
General purpose digital I/O pin
EBI data bus bit 4
EBI_DATA4
VCAP0_PCLK
NAND_CLE
I2C1_SDA
Video image interface 0 pixel clock pin
NAND Flash command latch enable
I2C1 data input/output pin
UART3 data receiver input pin
SPI0 MOSI (Master Out, Slave In) pin
CAN0 bus transmitter output
General purpose digital I/O pin
EBI data bus bit 5
O
PC.4
I/O
I
UART3_RXD
SPI0_MOSI
CAN0_TXD
PC.5
I/O
O
I/O
I/O
I
EBI_DATA5
VCAP0_HSYNC
NAND_nWE
SPI0_SS0
Video image interface 0 horizontal sync. Pin
NAND Flash write enable
O
PC.5
I/O
I/O
SPI0 slave select 0 pin
SD0_CMD/eMMC0_CMD
SD0 command/response pin
eMMC0 command/response pin
UART1_TXD
PC.6
O
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
UART1 data transmitter output pin
General purpose digital I/O pin
EBI data bus bit 6
I/O
I/O
I
EBI_DATA6
VCAP0_VSYNC
NAND_nRE
SC1_RST
Video image interface 0 vertical sync. Pin
NAND Flash read enable
Smart Card 1 reset pin
PC.6
O
O
SPI0_CLK
I/O
O
SPI0 serial clock pin
SD0_CLK/eMMC0_CLK
SD0 clock output pin
Jan. 28, 2019
Page 70 of 246
Rev 1.00
NUC980
Pin Name
Type
MFP
Description
eMMC0 clock output pin
UART1_RXD
PC.7
I
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
UART1 data receiver input pin
General purpose digital I/O pin
EBI data bus bit 7
I/O
I/O
I
EBI_DATA7
VCAP0_FIELD
NAND_RDY0
SC1_CLK
Video image interface 0 frame sync. Pin
NAND Flash ready/busy pin
Smart Card 1 clock pin
I
PC.7
O
I/O
SPI0_MOSI
SPI0 MOSI (Master Out, Slave In) pin
SD0_DATA0/eMMC0_DATA I/O
0
SD0 data line bit 0
eMMC0 data line bit 0
UART1_RTS
PC.8
O
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
UART1 request to Send output pin
General purpose digital I/O pin
EBI data bus bit 8
I/O
I/O
I
EBI_DATA8
VCAP0_DATA0
NAND_DATA0
SC1_DAT
Video image interface 0 data 0 pin
NAND Flash data bus bit 0
Smart Card 1 data pin
I/O
I/O
I/O
PC.8
SPI0_MISO
SPI0 MISO (Master In, Slave Out) pin
SD0_DATA1/eMMC0_DATA I/O
1
SD0 data line bit 1
eMMC0 data line bit 1
UART1_CTS
PC.9
I
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
UART1 clear to Send input pin
General purpose digital I/O pin
EBI data bus bit 9
I/O
I/O
I
EBI_DATA9
VCAP0_DATA1
NAND_DATA1
SC1_PWR
Video image interface 0 data 1 pin
NAND Flash data bus bit 1
Smart Card 1 power pin
I/O
O
PC.9
SD0_DATA2/eMMC0_DATA I/O
2
SD0 data line bit 2
eMMC0 data line bit 2
UART4_TXD
PC.10
O
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
UART4 data transmitter output pin
General purpose digital I/O pin
EBI data bus bit 10
I/O
I/O
I
EBI_DATA10
VCAP0_DATA2
NAND_DATA2
SC1_CD
Video image interface 0 data 2 pin
NAND Flash data bus bit 2
Smart Card 1 card detect pin
SD0 data line bit 3
PC.10
I/O
I
SD0_DATA3/eMMC0_DATA I/O
3
Jan. 28, 2019
Page 71 of 246
Rev 1.00
NUC980
Pin Name
Type
MFP
Description
eMMC0 data line bit 3
UART4_RXD
PC.11
I
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP7
MFP0
UART4 data receiver input pin
General purpose digital I/O pin
EBI data bus bit 11
I/O
I/O
I
EBI_DATA11
VCAP0_DATA3
NAND_DATA3
SC0_RST
PC.11
Video image interface 0 data 3 pin
NAND Flash data bus bit 3
Smart Card 0 reset pin
I/O
O
PC.12
I/O
I/O
I
General purpose digital I/O pin
EBI data bus bit 12
EBI_DATA12
VCAP0_DATA4
NAND_DATA4
SC0_CLK
Video image interface 0 data 4 pin
NAND Flash data bus bit 4
Smart Card 0 clock pin
PC.12
I/O
O
SD0_nCD
I
SD0 card detect input pin
UART8_TXD
PC.13
O
UART8 data transmitter output pin
General purpose digital I/O pin
EBI data bus bit 13
I/O
I/O
I
EBI_DATA13
VCAP0_DATA5
NAND_DATA5
SC0_DAT
Video image interface 0 data 5 pin
NAND Flash data bus bit 5
Smart Card 0 data pin
PC.13
I/O
I/O
I
UART8_RXD
PC.14
UART8 data receiver input pin
General purpose digital I/O pin
EBI data bus bit 14
I/O
I/O
I
EBI_DATA14
VCAP0_DATA6
NAND_DATA6
SC0_PWR
SPI0_MOSI
UART8_RTS
PC.15
Video image interface 0 data 6 pin
NAND Flash data bus bit 6
Smart Card 0 power pin
PC.14
I/O
O
I/O
O
SPI0 MOSI (Master Out, Slave In) pin
UART8 request to Send output pin
General purpose digital I/O pin
EBI data bus bit 15
I/O
I/O
I
EBI_DATA15
VCAP0_DATA7
NAND_DATA7
SC0_CD
Video image interface 0 data 7 pin
NAND Flash data bus bit 7
Smart Card 0 card detect pin
UART8 clear to Send input pin
General purpose digital I/O pin
PC.15
PD.0
I/O
I
UART8_CTS
PD.0
I
I/O
Jan. 28, 2019
Page 72 of 246
Rev 1.00
NUC980
Pin Name
QSPI0_SS1
UART5_TXD
TM1_TGL
EINT2
Type
I/O
O
MFP
Description
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
Quad SPI0 slave select 1 pin
UART5 data transmitter output pin
Timer1 event counter input/toggle output pin
External interrupt 2 input pin
I/O
I
PD.1
I/O
I/O
I
General purpose digital I/O pin
SPI0_SS1
UART5_RXD
TM1_EXT
EINT3
SPI0 slave select 1 pin
PD.1
UART5 data receiver input pin
I/O
I
Timer1 external capture input/toggle output pin
External interrupt 3 input pin
PD.2
I/O
I/O
O
General purpose digital I/O pin
QSPI0_SS0
UART3_TXD
TM4_EXT
PD.3
Quad SPI0 slave select 0 pin
PD.2
PD.3
PD.4
PD.5
UART3 data transmitter output pin
Timer4 external capture input/toggle output pin
General purpose digital I/O pin
I/O
I/O
I/O
I
QSPI0_CLK
UART3_RXD
TM4_TGL
PD.4
Quad SPI0 serial clock pin
UART3 data receiver input pin
I/O
I/O
I/O
O
Timer4 event counter input/toggle output pin
General purpose digital I/O pin
QSPI0_MOSI0
UART3_RTS
TM5_EXT
PD.5
Quad SPI0 MOSI0 (Master Out, Slave In) pin
UART3 request to Send output pin
Timer5 external capture input/toggle output pin
General purpose digital I/O pin
I/O
I/O
I/O
I
QSPI0_MISO0
UART3_CTS
TM5_TGL
PD.6
Quad SPI0 MISO0 (Master In, Slave Out) pin
UART3 clear to Send input pin
I/O
I/O
I/O
O
Timer5 event counter input/toggle output pin
General purpose digital I/O pin
QSPI0_MOSI1
UART2_TXD
TM0_ECNT
CAN0_RXD
PD.7
Quad SPI0 MOSI1 (Master Out, Slave In) pin
UART2 data transmitter output pin
Timer0 event counter input/toggle output pin
CAN0 bus receiver input
PD.6
I/O
I
I/O
I/O
I
General purpose digital I/O pin
QSPI0_MISO1
UART2_RXD
TM1_ECNT
Quad SPI0 MISO1 (Master In, Slave Out) pin
UART2 data receiver input pin
PD.7
I/O
Timer1 event counter input/toggle output pin
Jan. 28, 2019
Page 73 of 246
Rev 1.00
NUC980
Pin Name
CAN0_TXD
PD.8
Type
O
MFP
Description
MFP4
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP3
MFP0
MFP1
MFP2
MFP4
MFP6
MFP8
MFP0
MFP1
MFP2
MFP4
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
CAN0 bus transmitter output
I/O
I/O
I
General purpose digital I/O pin
SPI0 slave select 0 pin
SPI0_SS0
UART6_CTS
TM2_ECNT
PD.9
PD.8
UART6 clear to Send input pin
Timer2 event counter input/toggle output pin
General purpose digital I/O pin
SPI0 serial clock pin
I/O
I/O
I/O
O
SPI0_CLK
UART6_RTS
TM3_ECNT
PD.10
PD.9
UART6 request to Send output pin
Timer3 event counter input/toggle output pin
General purpose digital I/O pin
SPI0 MOSI (Master Out, Slave In) pin
UART6 data transmitter output pin
Timer4 event counter input/toggle output pin
General purpose digital I/O pin
SPI0 MISO (Master In, Slave Out) pin
UART6 data receiver input pin
Timer5 event counter input/toggle output pin
General purpose digital I/O pin
UART4 data transmitter output pin
Timer2 event counter input/toggle output pin
CAN2 bus receiver input
I/O
I/O
I/O
O
SPI0_MOSI
UART6_TXD
TM4_ECNT
PD.11
PD.10
PD.11
I/O
I/O
I/O
I
SPI0_MISO
UART6_RXD
TM5_ECNT
PD.12
I/O
I/O
O
UART4_TXD
TM2_TGL
CAN2_RXD
PWM00
I/O
I
PD.12
O
PWM00 counter synchronous trigger output pin
EBI data bus bit 1
EBI_DATA1
PD.13
I/O
I/O
I
General purpose digital I/O pin
UART4 data receiver input pin
Timer2 external capture input/toggle output pin
CAN2 bus transmitter output
UART4_RXD
TM2_EXT
CAN2_TXD
PWM01
I/O
O
PD.13
O
PWM01 counter synchronous trigger output pin
EBI data bus bit 2
EBI_DATA2
PD.14
I/O
I/O
O
General purpose digital I/O pin
UART4 request to Send output pin
Timer3 event counter input/toggle output pin
I2C3 clock pin
UART4_RTS
TM3_TGL
I2C3_SCL
CAN1_RXD
PD.14
I/O
I/O
I
CAN1 bus receiver input
Jan. 28, 2019
Page 74 of 246
Rev 1.00
NUC980
Pin Name
USBHL0_DM
PWM02
Type
MFP
Description
A
O
I/O
I/O
I
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
USB 1.1 Host Lite port 0 differential signal D-
PWM02 counter synchronous trigger output pin
EBI data bus bit 3
EBI_DATA3
PD.15
General purpose digital I/O pin
UART4_CTS
TM3_EXT
UART4 clear to Send input pin
I/O
I/O
O
A
O
I/O
I/O
I
Timer3 external capture input/toggle output pin
I2C3 data input/output pin
I2C3_SDA
CAN1_TXD
USBHL0_DP
PWM03
PD.15
CAN1 bus transmitter output
USB 1.1 Host Lite port 0 differential signal D+
PWM03 counter synchronous trigger output pin
EBI data bus bit 4
EBI_DATA4
PE.0
General purpose digital I/O pin
RMII0_RXERR
CAN0_RXD
UART4_CTS
USBHL1_DM
VCAP1_HSYNC
PE.1
RMII0 Receive Data Error input pin
CAN0 bus receiver input
I
PE.0
I
UART4 clear to Send input pin
A
I
USB 1.1 Host Lite port 1 differential signal D-
Video image interface 1 horizontal sync. Pin
General purpose digital I/O pin
I/O
I
RMII0_CRSDV
CAN0_TXD
UART4_RTS
USBHL1_DP
VCAP1_VSYNC
PE.2
RMII0 Carrier Sense/Receive Data input pin
CAN0 bus transmitter output
O
O
A
I
PE.1
UART4 request to Send output pin
USB 1.1 Host Lite port 1 differential signal D+
Video image interface 1 vertical sync. Pin
General purpose digital I/O pin
I/O
I
RMII0_RXD1
CAN1_RXD
UART4_RXD
USBHL2_DM
VCAP1_DATA0
PE.3
RMII0 Receive Data bus bit 1
I
CAN1 bus receiver input
PE.2
I
UART4 data receiver input pin
A
I
USB 1.1 Host Lite port 2 differential signal D-
Video image interface 1 data 0 pin
General purpose digital I/O pin
I/O
I
RMII0_RXD0
CAN1_TXD
UART4_TXD
USBHL2_DP
RMII0 Receive Data bus bit 0
PE.3
O
O
A
CAN1 bus transmitter output
UART4 data transmitter output pin
USB 1.1 Host Lite port 2 differential signal D+
Jan. 28, 2019
Page 75 of 246
Rev 1.00
NUC980
Pin Name
VCAP1_DATA1
PE.4
Type
MFP
Description
I
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP5
MFP6
MFP7
MFP0
MFP1
MFP5
MFP6
MFP7
MFP0
MFP1
MFP5
MFP6
Video image interface 1 data 1 pin
General purpose digital I/O pin
RMII0 mode clock input pin
I/O
I
RMII0_REFCLK
CAN2_RXD
UART9_CTS
USBHL3_DM
VCAP1_DATA2
PE.5
I
CAN2 bus receiver input
PE.4
PE.5
PE.6
PE.7
I
UART9 clear to Send input pin
USB 1.1 Host Lite port 3 differential signal D-
Video image interface 1 data 2 pin
General purpose digital I/O pin
RMII0 Transmit Enable output pin
CAN2 bus transmitter output
A
I
I/O
O
O
O
A
I
RMII0_TXEN
CAN2_TXD
UART9_RTS
USBHL3_DP
VCAP1_DATA3
PE.6
UART9 request to Send output pin
USB 1.1 Host Lite port 3 differential signal D+
Video image interface 1 data 3 pin
General purpose digital I/O pin
RMII0 Transmit Data bus bit 1
I/O
O
I
RMII0_TXD1
CAN3_RXD
UART9_RXD
USBHL4_DM
VCAP1_DATA4
PE.7
CAN3 bus receiver input
I
UART9 data receiver input pin
A
I
USB 1.1 Host Lite port 4 differential signal D-
Video image interface 1 data 4 pin
General purpose digital I/O pin
RMII0 Transmit Data bus bit 0
I/O
O
O
O
A
I
RMII0_TXD0
CAN3_TXD
UART9_TXD
USBHL4_DP
VCAP1_DATA5
PE.8
CAN3 bus transmitter output
UART9 data transmitter output pin
USB 1.1 Host Lite port 4 differential signal D+
Video image interface 1 data 5 pin
General purpose digital I/O pin
RMII0 PHY Management Data pin
UART6 data receiver input pin
I/O
I/O
I
RMII0_MDIO
UART6_RXD
USBHL5_DM
VCAP1_DATA6
PE.9
PE.8
A
I
USB 1.1 Host Lite port 5 differential signal D-
Video image interface 1 data 6 pin
General purpose digital I/O pin
RMII0 PHY Management Clock output pin
UART6 data transmitter output pin
USB 1.1 Host Lite port 5 differential signal D+
I/O
O
O
A
RMII0_MDC
UART6_TXD
USBHL5_DP
PE.9
Jan. 28, 2019
Page 76 of 246
Rev 1.00
NUC980
Pin Name
VCAP1_DATA7
PE.10
Type
MFP
Description
1
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
Video image interface 1 ata 7 pin
General purpose digital I/O pin
USB host bus power over voltage detector
CAN3 bus receiver input
I/O
I
USB_OVC
CAN3_RXD
UART9_RXD
PWM12
I
I
UART9 data receiver input pin
PWM12 counter synchronous trigger output pin
External interrupt 2 input pin
PE.10
PE.11
PE.12
O
I
EINT2
I2C0_SDA
VCAP1_FIELD
PE.11
I/O
I
I2C0 data input/output pin
Video image interface 1 frame sync. Pin
General purpose digital I/O pin
USB0 VBUS vaild indication pin
General purpose digital I/O pin
HSUSB host power control pin
CAN3 bus transmitter output
I/O
I
USB0_VBUSVLD
PE.12
I/O
O
O
O
O
I
USBH_PWREN
CAN3_TXD
UART9_TXD
PWM13
UART9 data transmitter output pin
PWM13 counter synchronous trigger output pin
External interrupt 3 input pin
EINT3
I2C0_SCL
I/O
O
I/O
I
I2C0 clock pin
VCAP1_CLKO
PF.0
Video image interface 1 sensor clock pin
General purpose digital I/O pin
RMII1 Receive Data Error input pin
RMII1_RXERR
SD1_CMD/eMMC1_CMD
I/O
SD1 command/response pin
eMMC1 command/response pin
TM0_ECNT
I/O
O
I
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
Timer0 event counter input/toggle output pin
Smart Card 1 reset pin
PF.0
SC1_RST
UART7_CTS
USBHL1_DM
EBI_DATA5
PF.1
UART7 clear to Send input pin
USB 1.1 Host Lite port 1 differential signal D-
EBI data bus bit 5
A
I/O
I/O
I
General purpose digital I/O pin
RMII1 Carrier Sense/Receive Data input pin
RMII1_CRSDV
SD1_CLK/eMMC1_CLK
O
SD1 clock output pin
PF.1
eMMC1 clock output pin
TM1_ECNT
SC1_CLK
I/O
O
MFP3
MFP4
Timer1 event counter input/toggle output pin
Smart Card 1 clock pin
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Pin Name
UART7_RTS
USBHL1_DP
EBI_DATA6
PF.2
Type
O
MFP
Description
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
UART7 request to Send output pin
USB 1.1 Host Lite port 1 differential signal D+
EBI data bus bit 6
A
I/O
I/O
I
General purpose digital I/O pin
RMII1 Receive Data bus bit 1
RMII1_RXD1
SD1_DATA0/eMMC1_DATA I/O
0
SD1 data line bit 0
eMMC1 data line bit 0
TM2_ECNT
SC1_DAT
I/O
I/O
I
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
Timer2 event counter input/toggle output pin
Smart Card 1 data pin
PF.2
UART7_RXD
USBHL2_DM
EBI_DATA7
PF.3
UART7 data receiver input pin
USB 1.1 Host Lite port 2 differential signal D-
EBI data bus bit 7
A
I/O
I/O
I
General purpose digital I/O pin
RMII1 Receive Data bus bit 0
RMII1_RXD0
SD1_DATA1/eMMC1_DATA I/O
1
SD1 data line bit 1
eMMC1 data line bit 1
TM3_ECNT
SC1_PWR
UART7_TXD
USBHL2_DP
EBI_DATA8
PF.4
I/O
O
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
Timer3 event counter input/toggle output pin
Smart Card 1 power pin
PF.3
O
UART7 data transmitter output pin
USB 1.1 Host Lite port 2 differential signal D+
EBI data bus bit 8
A
I/O
I/O
I
General purpose digital I/O pin
RMII1 mode clock input pin
RMII1_REFCLK
SD1_DATA2/eMMC1_DATA I/O
2
SD1 data line bit 2
eMMC1 data line bit 2
TM4_ECNT
SC1_CD
I/O
I
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
Timer4 event counter input/toggle output pin
Smart Card 1 card detect pin
PF.4
UART3_CTS
USBHL3_DM
EBI_DATA9
PF.5
I
UART3 clear to Send input pin
USB 1.1 Host Lite port 3 differential signal D-
EBI data bus bit 9
A
I/O
I/O
O
General purpose digital I/O pin
RMII1 Transmit Enable output pin
RMII1_TXEN
PF.5
SD1_DATA3/eMMC1_DATA I/O
3
SD1 data line bit 3
eMMC1 data line bit 3
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Pin Name
TM5_ECNT
PWM00
Type
I/O
O
MFP
Description
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
Timer5 event counter input/toggle output pin
PWM00 counter synchronous trigger output pin
UART3 request to Send output pin
USB 1.1 Host Lite port 3 differential signal D+
EBI data bus bit 10
UART3_RTS
USBHL3_DP
EBI_DATA10
PF.6
O
A
I/O
I/O
O
General purpose digital I/O pin
RMII1_TXD1
SD1_nCD
TM4_EXT
PWM01
RMII1 Transmit Data bus bit 1
I
SD1 card detect input pin
I/O
O
Timer4 external capture input/toggle output pin
PWM01 counter synchronous trigger output pin
UART3 data receiver input pin
PF.6
UART3_RXD
USBHL4_DM
EBI_DATA11
PF.7
I
A
USB 1.1 Host Lite port 4 differential signal D-
EBI data bus bit 11
I/O
I/O
O
General purpose digital I/O pin
RMII1_TXD0
UART1_CTS
TM5_EXT
PWM02
RMII1 Transmit Data bus bit 0
I
UART1 clear to Send input pin
I/O
O
Timer5 external capture input/toggle output pin
PWM02 counter synchronous trigger output pin
UART3 data transmitter output pin
USB 1.1 Host Lite port 4 differential signal D+
EBI data bus bit 12
PF.7
UART3_TXD
USBHL4_DP
EBI_DATA12
PF.8
O
A
I/O
I/O
I/O
O
General purpose digital I/O pin
RMII1_MDIO
UART1_RTS
TM1_TGL
PWM03
RMII1 PHY Management Data pin
UART1 request to Send output pin
Timer1 event counter input/toggle output pin
PWM03 counter synchronous trigger output pin
USB 1.1 Host Lite port 5 differential signal D-
EBI data bus bit 13
PF.8
I/O
O
USBHL5_DM
EBI_DATA13
PF.9
A
I/O
I/O
O
General purpose digital I/O pin
RMII1_MDC
UART1_RXD
TM1_EXT
PWM10
RMII1 PHY Management Clock output pin
UART1 data receiver input pin
I
PF.9
I/O
O
Timer1 external capture input/toggle output pin
PWM10 counter synchronous trigger output pin
USB 1.1 Host Lite port 5 differential signal D+
USBHL5_DP
A
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Pin Name
EBI_DATA14
PF.10
Type
I/O
I/O
O
MFP
MFP8
MFP0
MFP2
MFP3
MFP4
MFP7
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP3
MFP6
-
Description
EBI data bus bit 14
General purpose digital I/O pin
UART1 data transmitter output pin
Timer5 event counter input/toggle output pin
PWM11 counter synchronous trigger output pin
Video image interface 1 pixel clock pin
EBI data bus bit 15
UART1_TXD
TM5_TGL
PWM11
I/O
O
PF.10
VCAP1_PCLK
EBI_DATA15
PF.11
I
I/O
I/O
I
General purpose digital I/O pin
UART0 data receiver input pin
General purpose digital I/O pin
UART0 data transmitter output pin
General purpose digital I/O pin
EBI address bus bit 0
PF.11
PF.12
UART0_RXD
PF.12
I/O
O
UART0_TXD
PG.0
I/O
O
EBI_ADDR0
UART2_RXD
CLK_OUT
PWM00
I
UART2 data receiver input pin
Internal clock selection output pin
PWM00 counter synchronous trigger output pin
PG.0
O
O
CFG.0_PwrOnSet0
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.1
I/O
O
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 1
EBI_ADDR1
UART2_TXD
PWM01
O
UART2 data transmitter output pin
PWM01 counter synchronous trigger output pin
PG.1
PG.2
PG.3
O
CFG.1_PwrOnSet1
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.2
I/O
O
I
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 2
EBI_ADDR2
UART2_CTS
PWM02
UART2 clear to Send input pin
PWM02 counter synchronous trigger output pin
O
IU
CFG.2_PwrOnSet2
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.3
I/O
O
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 3
EBI_ADDR3
UART2_RTS
PWM03
O
UART2 request to Send output pin
PWM03 counter synchronous trigger output pin
O
CFG.3_PwrOnSet3
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
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Pin Name
PG.4
Type
I/O
O
MFP
MFP0
MFP1
MFP2
-
Description
General purpose digital I/O pin
EBI address bus bit 18
UART5 clear to Send input pin
EBI_ADDR18
UART5_CTS
CFG.4_PwrOnSet4
PG.4
I
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.5
I/O
O
MFP0
MFP1
MFP2
-
General purpose digital I/O pin
EBI address bus bit 12
EBI_ADDR12
UART5_RTS
CFG.5_PwrOnSet5
PG.5
O
UART5 request to Send output pin
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.6
I/O
O
I
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 4
EBI_ADDR4
UART5_RXD
PWM10
UART5 data receiver input pin
PWM10 counter synchronous trigger output pin
PG.6
PG.7
PG.8
O
IU
CFG.6_PwrOnSet6
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.7
I/O
O
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 5
EBI_ADDR5
UART5_TXD
PWM11
O
UART5 data transmitter output pin
PWM11 counter synchronous trigger output pin
O
CFG.7_PwrOnSet7
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.8
I/O
O
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 6
EBI_ADDR6
UART8_RTS
PWM12
O
UART8 request to Send output pin
PWM12 counter synchronous trigger output pin
O
CFG.8_PwrOnSet8
IU
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.9
I/O
O
I
MFP0
MFP1
MFP2
MFP6
-
General purpose digital I/O pin
EBI address bus bit 7
EBI_ADDR7
UART8_CTS
PWM13
UART8 clear to Send input pin
PWM13 counter synchronous trigger output pin
PG.9
O
IU
CFG.9_PwrOnSet9
System configuration and power on setting with an internal pull-up.
Internal pull-up only active automatically during reset
PG.10
I/O
I/O
I/O
MFP0
MFP1
MFP2
General purpose digital I/O pin
EBI data bus bit 0
PG.10
EBI_DATA0
I2C0_SCL
I2C0 clock pin
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Pin Name
TM5_TGL
USBHL4_DP
CAN2_TXD
SPI1_CLK
PWM00
Type
I/O
A
MFP
Description
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP2
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
Timer5 event counter input/toggle output pin
USB 1.1 Host Lite port 4 differential signal D+
CAN2 bus transmitter output
O
I/O
O
SPI1 serial clock pin
PWM00 counter synchronous trigger output pin
I2S_ bit clock output pin
I2S_BCLK
PG.11
O
I/O
I/O
I/O
I
General purpose digital I/O pin
SPI1 slave select 0 pin
SPI1_SS0
TM1_TGL
CAN0_RXD
UART5_CTS
PWM10
Timer1 event counter input/toggle output pin
CAN0 bus receiver input
PG.11
I
UART5 clear to Send input pin
PWM10 counter synchronous trigger output pin
JTAG0 data output pin
O
JTAG0_TDO
PG.12
O
I/O
I/O
I/O
O
General purpose digital I/O pin
SPI1 serial clock pin
SPI1_CLK
TM1_EXT
CAN0_TXD
UART5_RTS
PWM11
Timer1 external capture input/toggle output pin
CAN0 bus transmitter output
PG.12
O
UART5 request to Send output pin
PWM11 counter synchronous trigger output pin
JTAG0 clock input pin
O
JTAG0_TCK
PG.13
I
I/O
I/O
I
General purpose digital I/O pin
SPI1 MOSI (Master Out, Slave In) pin
CAN1 bus receiver input
SPI1_MOSI
CAN1_RXD
UART5_RXD
PWM12
PG.13
I
UART5 data receiver input pin
PWM12 counter synchronous trigger output pin
JTAG0 test mode selection input pin
General purpose digital I/O pin
SPI1 MISO (Master In, Slave Out) pin
CAN1 bus transmitter output
O
JTAG0_TMS
PG.14
I
I/O
I/O
O
SPI1_MISO
CAN1_TXD
UART5_TXD
PWM13
PG.14
PG.15
O
UART5 data transmitter output pin
PWM13 counter synchronous trigger output pin
JTAG0 data input pin
O
JTAG0_TDI
PG.15
I
I/O
I/O
General purpose digital I/O pin
SPI0 slave select 1 pin
SPI0_SS1
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Pin Name
SPI1_SS1
EINT3
Type
MFP
MFP2
MFP4
MFP7
Description
I/O
SPI1 slave select 1 pin
External interrupt 3 input pin
JTAG0 reset input pin
I
I
JTAG0_nTRST
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Page 83 of 246
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NUC980
5 BLOCK DIAGRAM
5.1 NUC980 Series Block Diagram
ARM926EJ-S
300 MHz
Memory
Power Control
Crypto
Phripherals
DMA
Phripherals
Analog
I-Cache
16 KB
AES
SHA/HMAC
RSA
AIC
Timer X 6
WDT/WWDT
PWM X 8
RTC
ROM 16.5 KB
POR
PDMA 0
10-ch
12-bit ADC
9-ch
D-Cache
16 KB
SRAM 16 KB
DDR2
LVR
LVD
ECC
PDMA 1
10-ch
MMU
TRNG
Bridge
AHB Bus
APB Bus
Clock Control
Storage
Connectivity
USB 2.0 HS
Connectivity
Transceivers
HS Ext.
Crystal Osc.
12 MHz
Ethernet MAC
X 2
CMOS Interface
X 2
NAND Flash
Interface
USB 2.0 HS
Dual Role
Transceiver
UART X 10 (IrDA,RS-485)
USB 2.0 HS/FS
Host / Device
EBI
GPIO
LS Ext.
Crystal Osc.
32.768 kHz
SD/eMMC
Interface X 2
CAN X 4
I2C X 4
SPI X 2
USB 1.1 FS
Host Lite X 6
USB 2.0 HS
Host Mode
Transceiver
ISO 7816-3 X 2
I2S X 1
External Interrupt
PLL X 2
Quad SPI X 1
Figure 5.1-1 NUC980 Series Block Diagram
Jan. 28, 2019
Page 84 of 246
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6 FUNCTIONAL DESCRIPTION
6.1 ARM® ARM926EJ-S CPU Core
6.1.1
Overview
The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose microprocessors.
The ARM926EJ-S CPU core is targeted at multi-tasking applications where full memory management,
high performance, and low power are all important.
The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the
user to choose between high performance and high code density. The ARM926EJ-S CPU core
includes features for efficient execution of Java byte codes, providing Java performance similar to JIT,
but without the associated code overhead.
The ARM926EJ-S processor provides support for external coprocessor enabling floating-point or other
application-specific hardware acceleration to be added. The ARM926EJ-S CPU core implements ARM
architecture version 5TEJ.
The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-
performance processor subsystem, including:
An ARM9EJ-S integer core.
A Memory Management Unit (MMU).
Separate instruction and data cache.
Separate instruction and data AMBA AHB bus interfaces.
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6.2 System Manager
6.2.1
Overview
The system management describes the following information and functions.
System Resets
System Power Architecture
System Memory Map
System management registers for Product Identifier (PDID), Power-On Setting, System
Wake-Up, Reset Control for on-chip controllers/peripherals, and multi-function pin control.
System Control registers
6.2.2
System Reset
The system reset can be issued by one of the following listed events. For these reset event flags can
be read by RSTSTS register.
Power-On Reset
Low level on the /RESET pin
Watchdog Time Out Reset
Low Voltage Reset
CPU Reset
System Reset
6.2.3
System Power Distribution
In this chip, the power distribution is divided into six segments.
Analog power from AVDD33 provides 3.3V voltage to analog components operation. These
analog components including POR33, 12-bit SAR-ADC, LVD and LVR.
Digital power from VDD12 provides 1.2V voltage to POR12, APLL, APLL, SRAM (16 kB)
and all digital logic except RTC.
Digital power from VBAT33 provides 3.3V voltage to LXT and RTC logic.
USB PHY power from VUSB0_VDD33, VUSB0_VDD12 provides 3.3V and 1.2 respectively to USB
2.0 PHY 0, while VUSB1_VDD33, VUSB1_VDD12 provides 3.3V and 1.2 respectively to USB 2.0
PHY 1.
I/O power from MVDD provides 1.8V/2.5V to I/O pins used to connect SDRAM.
I/O power from VDD33 provides 3.3V to HXT and I/O pins (PA ~ PG).
Jan. 28, 2019
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Figure 6.2-1 shows the power distribution of the NUC980 series.
MVDD (1.8V)
USB 2.0 PHY 0
USB 2.0 PHY 1
DDR IO Cell
XT_IN
HXT
Ext. Crystal Osc.
12 MHz
SRAM
(16 kB)
POR12
APLL
UPLL
XT_OUT
V
DD12 (1.2V)
ROM
(16.5 kB)
VDD33 (3.3V)
Digital Logic
Normal IO Cell
LXT
Ext. Crystal
Osc.
RTC
with
64B Spare
Register
Low
Voltage
Reset
Low
Voltage
Detection
12-bit
SAR-ADC
AVDD33 (3.3V)
POR33
VBAT33 (3.3V)
32.768 kHz
Figure 6.2-1 NUC980 Series Power Distribution Diagram
System Memory Map
6.2.4
This chip supports only little-endian data format and provides 4G-byte addressing space. Figure 6.2-2
describes the memory space definition.
The memory space from 0x0000_0000 to 0x1FFF_FFFF is for SDRAM and external devices. The
memory space from 0x3C00_0000 to 0x3C00_3FFF is for embedded 16 Kbytes SRAM. The memory
space for On-Chip Controllers and Peripherals is from 0xB000_0000 to 0xB00A_3FFF while the
memory space from 0xFFFF_0000 to 0xFFFF_41FF is for 16.5 Kbytes internal Boot ROM.
This chip provides the shadow memory function. The memory space from 0x8000_0000 to
0x9FFF_FFFF is the shadow memory space for memory space from 0x0000_0000 to 0x1FFF_FFFF.
The memory space from 0xBC00_0000 to 0xBC00_3FFF is the shadow memory space for memory
space from 0x3C00_0000 to 0x3C00_3FFF. If the DMA of On-Chip Controller wants to access this 16
Kbytes embedded SRAM, it’s necessary to use memory space from 0xBC00_0000 to 0xBC00_3FFF
The reserved memory space is un-accessible. Chip’s behavior is undefined and unpredictable while
accessing to reserved memory space.
Jan. 28, 2019
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0x7FFF_FFFF
0xFFFF_FFFF
0xFFFF_4200
0xFFFF_0000
Reserved
Internal Boot ROM
(IBR, 16.5 KB)
Reserved
Reserved
EBI
0x602F_0000
0x6000_0000
0xE02F_0000
0xE000_0000
EBI
Reserved
Reserved
0x3C00_4000
0x3C00_0000
0xBC00_4000
0xBC00_0000
0xB00B_0000
0xB004_0000
0xB000_0000
Internal SRAM (16 KB)
Reserved
Internal SRAM (16 KB)
Reserved
On-Chip APB Peripherals
On-Chip AHB Peripherals
Reserved
SDRAM
0x2000_0000
0xA000_0000
SDRAM
0x8000_0000
0x0000_0000
Figure 6.2-2 NUC980 System Memory Map Diagram
Jan. 28, 2019
Page 88 of 246
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The addressing space assigned to each on-chip controller or peripheral described in Table 6.2-1. The
detailed register definition, addressing space, and programming details will be described in the
following sections.
Addressing Space
Token
Modules
SDRAM, External Devices and SRAM Memory Space
0x0000_0000 – 0x1FFF_FFFF
0x6000_0000 – 0x602F_FFFF
0x3C00_0000 – 0x3C00_3FFF
SDRAM_BA
EXDEV_BA
SRAM_BA
SDRAM Memory Space
External Devices Memory Space
SRAM Memory Space (16 KB)
Internal Boot ROM (IBR) Memory Space (0xFFFF_0000 ~ 0xFFFF_41FF)
0xFFFF_0000 – 0xFFFF_41FF
IBR_BA
Internal Boot ROM (IBR) Memory Space (16.5 KB)
AHB Modules Memory Space (0xB000_0000 – 0xB003_FFFF)
0xB000_0000 – 0xB000_01FF
0xB000_0200 – 0xB000_02FF
0xB000_2000 – 0xB000_2FFF
0xB000_4000 – 0xB000_4FFF
0xB000_8000 – 0xB000_8FFF
0xB000_9000 – 0xB000_9FFF
0xB001_0000 – 0xB001_0FFF
0xB001_2000 – 0xB001_2FFF
0xB002_4000 – 0xB002_4FFF
0xB001_5000 – 0xB001_5FFF
0xB001_6000 – 0xB001_6FFF
0xB001_7000 – 0xB001_7FFF
0xB001_8000 – 0xB001_8FFF
0xB001_9000 – 0xB001_9FFF
0xB001_C000 – 0xB001_EFFF
0xB002_0000 – 0xB002_0FFF
0xB002_2000 – 0xB002_2FFF
0xB001_4000 – 0xB001_4FFF
SYS_BA
System Global Control Registers
Clock Control Registers
CLK_BA
SDIC_BA
GPIO_BA
PDMA0_BA
PDMA1_BA
EBI_BA
SDRAM (SDR/DDR/DDR2) Control Registers
GPIO Control Registers
PDMA 0 Control Registers
PDMA 1 Control Registers
EBI Control Registers
EMAC0_BA
CAP0_BA
HSUSBH_BA
HSUSBD_BA
USBH_BA
SDH_BA
Ethernet MAC 0 Control Registers
Capture Sensor Interface 0 Control Registers
High Speed USB 2.0 Host Control Registers
High Speed USB 2.0 Device Control Registers
USB 2.0 Host Control Registers
SD/SDIO Host Control Registers
Flash Memory Interface (FMI) Control Registers
Cryptographic Accelerator Control Registers
I2S Interface Control Registers
FMI_BA
CRYPTO_BA
I2S_BA
EMAC1_BA
CAP1_BA
Ethernet MAC 1 Control Registers
Capture Sensor Interface 1 Control Registers
APB Modules Memory Space (0xB004_0000 ~ 0xB00A_FFFF)
0xB004_0000 – 0xB004_00FF
0xB004_0100 – 0xB004_01FF
0xB004_1000 – 0xB004_1FFF
0xB004_2000 – 0xB004_2FFF
0xB004_3000 – 0xB004_3FFF
0xB005_0000 – 0xB005_0FFF
WDT_BA
WWDT_BA
RTC_BA
AIC_BA
Watch-Dog Timer Control Registers
Windowed Watch-Dog Timer Control Registers
Real Time Clock (RTC) Control Registers
Advance Interrupt Control Registers
ADC Control Registers
ADC_BA
TMR_BA01
Timer 0 and Timer 1 Control Registers
Jan. 28, 2019
Page 89 of 246
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0xB005_1000 – 0xB005_1FFF
0xB005_2000 – 0xB005_2FFF
0xB005_8000 – 0xB005_8FFF
0xB005_9000 – 0xB005_9FFF
0xB006_0000 – 0xB006_0FFF
0xB006_1000 – 0xB006_1FFF
0xB006_2000 – 0xB006_2FFF
0xB007_0000 – 0xB007_0FFF
0xB007_1000 – 0xB007_1FFF
0xB007_2000 – 0xB007_2FFF
0xB007_3000 – 0xB007_3FFF
0xB007_4000 – 0xB007_4FFF
0xB007_5000 – 0xB007_5FFF
0xB007_6000 – 0xB007_6FFF
0xB007_7000 – 0xB007_7FFF
0xB007_8000 – 0xB007_8FFF
0xB007_9000 – 0xB007_9FFF
0xB008_0000 – 0xB008_0FFF
0xB008_1000 – 0xB008_1FFF
0xB008_2000 – 0xB008_2FFF
0xB008_3000 – 0xB008_3FFF
0xB009_0000 – 0xB009_0FFF
0xB009_1000 – 0xB009_1FFF
0xB00A_0000 – 0xB00A_0FFF
0xB00A_1000 – 0xB00A_1FFF
0xB00A_2000 – 0xB00A_2FFF
0xB00A_3000 – 0xB00A_3FFF
TMR_BA23
TMR_BA45
PWM0_BA
PWM1_BA
QSPI0_BA
SPI0_BA
Timer 2 and Timer 3 Control Registers
Timer 4 and Timer 5 Control Registers
PWM 0 Control Registers
PWM 1 Control Registers
QSPI 0 Control Registers
SPI 0 Control Registers
SPI1_BA
SPI 1 Control Registers
UART0_BA
UART1_BA
UART2_BA
UART3_BA
UART4_BA
UART5_BA
UART6_BA
UART7_BA
UART8_BA
UART9_BA
I2C0_BA
UART 0 Control Registers
UART 1 Control Registers
UART 2 Control Registers
UART 3 Control Registers
UART 4 Control Registers
UART 5 Control Registers
UART 6 Control Registers
UART 7 Control Registers
UART 8 Control Registers
UART 9 Control Registers
I2C 0 Control Registers
I2C1_BA
I2C 1 Control Registers
I2C2_BA
I2C 2 Control Registers
I2C3_BA
I2C 3 Control Registers
SC0_BA
Smart Card 0 Control Registers
Smart Card 1 Control Registers
CAN 0 Control Registers
CAN 1 Control Registers
CAN 2 Control Registers
CAN 3 Control Registers
SC1_BA
CAN0_BA
CAN1_BA
CAN2_BA
CAN3_BA
Table 6.2-1 Address Space Assignments for On-Chip Controllers
Jan. 28, 2019
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6.2.5
Power-On Setting
After power on reset, Power-On setting registers are latched to configure this chip. Table 6.2-2
describes the definition of each power-on setting bit.
Power-On Setting Pin
Description
Power-on Setting Register Bit
USB0_ID
USB Port 0 Role Selection
0 = USB Port 0 act as a USB host.
1 = USB Port 0 act as a USB device.
USBID (SYS_PWRON[16])
PG[1:0]
Boot Source Selection
00 = Boot from USB.
01 = Boor from SD0/eMMC.
10 = Boot from NAND Flash.
11 = Boot from SPI Flash.
BTSSEL (SYS_PWRON[1:0])
PG.2
PG.3
PG.4
PG.5
QSPI0_CLK Frequency Selection
0 = QSPI0_CLK frequency is 30 MHz.
1 = QSPI0_CLK frequency is 50 MHz.
QSPI0CKSEL
(SYS_PWRON[2])
Watchdog Timer (WDT) Enabled/Disabled Selection
0 = After power-on, WDT Disabled.
WDTON (SYS_PWRON[3])
JTAGSEL (SYS_PWRON[4])
1 = after power-on WDT Enabled.
JTAG Interface Selection
0 = Pin PA[6:2] used as JTAG interface.
1 = Pin PG[15:11] used as JTAG interface.
UART 0 Debug Message Output ON/OFF Selection
0 = UART 0 debug message output ON and pin PF[12:11] used as
the UART0 functionality.
URDBGON (SYS_PWRON[5])
1 = UART 0 debug message output OFF and pin PF[12:11] used as
the GPIO functionality.
NAND Flash Page Size selection
00 = NAND Flash page size is 2KB.
01 = NAND Flash page size is 4KB.
10 = NAND Flash page size is 8KB.
11 = Ignore Power-On Setting.
NPAGESEL
(SYS_PWRON[7:6])
PG[7:6]
Jan. 28, 2019
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PG[9:8]
Miscellaneous Configuration
When BTSSEL = 01, Boot from SD/eMMC, the MISCCFG defines
the GPC or GPF used as the booting source.
11 = GPC group used as the booting source.
Others = GPF group used as the booting source.
When BTSSEL = 10, Boot from NAND Flash, the MISCCFG
defines the ECC type.
00 = No ECC
01 = ECC is BCH T12
10 = ECC is BCH T24
11 = Ignore power-on setting
MISCCFG (SYS_PWRON[9:8])
When BTSEL = 11, Boot from SPI Flash, the MISCCFG defines the
SPI Flash type and data width.
00 = SPI-NAND Flash with 1-bit mode.
01 = SPI-NAND Flash with 4-bit mode.
10 = SPI-NOR Flash with 4-bit mode.
11 = SPI-NOR Flash with 1-bit mode.
Table 6.2-2 Power-On Setting Bit Description
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6.2.6
Register Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
SYS Base Address:
SYS_BA = 0xB000_0000
SYS_PDID
SYS_BA+0x000
R
Product Identifier Register
Power-on Setting Register
0x1030_D016[1]
0xXXXX_XXXX[2
SYS_PWRON
SYS_BA+0x004 R/W
]
SYS_LVRDCR
SYS_BA+0x020 R/W
SYS_BA+0x030 R/W
SYS_BA+0x040 R/W
SYS_BA+0x044 R/W
SYS_BA+0x050 R/W
SYS_BA+0x054 R/W
SYS_BA+0x058 R/W
SYS_BA+0x05C R/W
SYS_BA+0x060 R/W
SYS_BA+0x064 R/W
SYS_BA+0x068 R/W
SYS_BA+0x06C R/W
SYS_BA+0x070 R/W
SYS_BA+0x074 R/W
SYS_BA+0x078 R/W
SYS_BA+0x07C R/W
SYS_BA+0x080 R/W
SYS_BA+0x084 R/W
SYS_BA+0x088 R/W
SYS_BA+0x08C R/W
SYS_BA+0x090 R/W
SYS_BA+0x094 R/W
SYS_BA+0x098 R/W
SYS_BA+0x09C R/W
Low Voltage Reset & Detect Control Register
Miscellaneous Function Control Register
0x0000_0001
0x0000_0200
0x0000_0000
0x0001_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_00XX
0x0XXX_XX00
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
SYS_MISCFCR
SYS_MISCIER
Miscellaneous Interrupt Enable Register
SYS_MISCISR
Miscellaneous Interrupt Status Register
SYS_WKUPSER0
SYS_WKUPSER1
SYS_WKUPSSR0
SYS_WKUPSSR1
SYS_AHBIPRST
SYS_APBIPRST0
SYS_APBIPRST1
SYS_RSTSTS
System Wakeup Source Enable Register 0
System Wakeup Source Enable Register 1
System Wakeup Source Status Register 0
System Wakeup Source Status Register 1
AHB IP Reset Control Register
APB IP Reset Control Register 0
APB IP Reset Control Register 1
Reset Source Active Status Register
SYS_GPA_MFPL
SYS_GPA_MFPH
SYS_GPB_MFPL
SYS_GPB_MFPH
SYS_GPC_MFPL
SYS_GPC_MFPH
SYS_GPD_MFPL
SYS_GPD_MFPH
SYS_GPE_MFPL
SYS_GPE_MFPH
SYS_GPF_MFPL
SYS_GPF_MFPH
GPIOA Low Byte Multiple Function Control Register
GPIOA High Byte Multiple Function Control Register
GPIOB Low Byte Multiple Function Control Register
GPIOB High Byte Multiple Function Control Register
GPIOC Low Byte Multiple Function Control Register
GPIOC High Byte Multiple Function Control Register
GPIOD Low Byte Multiple Function Control Register
GPIOD High Byte Multiple Function Control Register
GPIOE Low Byte Multiple Function Control Register
GPIOE High Byte Multiple Function Control Register
GPIOF Low Byte Multiple Function Control Register
GPIOF High Byte Multiple Function Control Register
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SYS_GPG_MFPL
SYS_GPG_MFPH
SYS_BA+0x0A0 R/W
SYS_BA+0x0A4 R/W
GPIOG Low Byte Multiple Function Control Register
GPIOG High Byte Multiple Function Control Register
DDR I/O Driving Strength Control Register
GPIOB Low Byte Driving Strength Control Register
Power-On-reset Disable Control Register
0x0000_0000
0xXXXX_X000
0x0000_0000
0x4444_4444
0x0000_00XX
0x0000_04B0
0x0000_0000
SYS_DDR_DSCTL SYS_BA+0x0F0 R/W
SYS_GPBL_DSCTL SYS_BA+0x0F4 R/W
SYS_PORDISCR
SYS_RSTDEBCTL SYS_BA+0x10C R/W
SYS_REGWPCTL
SYS_BA+0x1FC R/W
SYS_BA+0x100 R/W
Reset Pin De-bounce Control Register
Register Write-protection Control Register
Note: [1] Dependents on part number.
Note: [2] Dependents on power-on setting.
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6.2.7
Register Description
Product Identifier Register (SYS_PDID)
Register
Offset
R/W Description
Product Identifier Register
Reset Value
SYS_PDID
SYS_BA+0x000
R
0x1030_D016
31
23
15
7
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
PRDNUML6
PRDNUML4
PRDNUML2
PRDNUML5
PRDNUML3
PRDNUML1
14
6
1
0
Bits
Description
Reserved
[31:24]
Reserved.
Product Number Letter 6
0 = D.
1 = F.
2 = G.
3 = H.
[23:20]
[19:16]
PRDNUML6
PRDNUML5
Product Number Letter 5
0 = A.
1 = B.
Product Number Letter 4
[15:12]
[11:8]
[7:4]
PRDNUML4
PRDNUML3
PRDNUML2
PRDNUML1
0xD
Product Number Letter 3
0x0
Product Number Letter 2
0x1
Product Number Letter 1
[3:0]
0x6
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Power-on Setting Register (SYS_PWRON)
Register
Offset
R/W Description
Reset Value
SYS_PWRON SYS_BA+0x004 R/W Power-on Setting Register
0xXXXX_XXXX
31
30
Reserved
22
29
28
20
12
27
19
11
26
USERID
18
25
24
23
Reserved
15
21
DRAMSIZE
13
17
TICMOD
9
16
USBID
8
Reserved
14
6
10
Reserved
MISCCFG
7
5
4
3
2
1
0
NPAGESEL
URDBGON
JTAGSEL
WDTON
QSPI0CKSEL
BTSSEL
Bits
Description
Reserved
[31:29]
[28:24]
[23]
Reserved.
User ID (Read Only)
USERID
A user defined ID.
Reserved
Reserved.
DRAM Size
000 = Reserved.
001 = 2 MB
010 = Reserved.
011 = 8 MB
[22:20]
DRAMSIZE
100 = 16 MB
101 = 32 MB
110 = 64 MB
111 = 128 MB
[19:18]
[17]
Reserved
TICMOD
Reserved.
TIC Mode Enable Bit
0= TIC interface Disabled.
1= TIC interface Enabled.
USB ID Pin Status
[16]
USBID
0= USB port 0 used as a USB device.
1= USB port 0 used as a USB host.
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Miscellaneous Configuration
When pin nRESET transited from low to high, the value of pin PG[9:8] latched to
MISCCFG.
When BTSSEL = 01, Boot from SD/eMMC, the MISCCFG defines the SD0/eMMC0 or
SD1/eMMC1 used as the booting source.
11 = SD0/eMMC0 (GPC group) used as the booting source.
Others = SD1/eMMC1 (GPF group) used as the booting source.
When BTSSEL = 10, Boot from NAND Flash, the MISCCFG defines the ECC type.
00 = ECC is BCH T8.
[9:8]
MISCCFG
01 = ECC is BCH T12.
10 = ECC is BCH T24.
11 = Ignore power-on setting.
When BTSEL = 11, Boot from SPI Flash, the MISCCFG defines the SPI Flash type and
data width.
00 = SPI-NAND Flash with 1-bit mode.
01 = SPI-NAND Flash with 4-bit mode.
10 = SPI-NOR Flash with 4-bit mode.
11 = SPI-NOR Flash with 1-bit mode.
NAND Flash Page Size Selection
When pin nRESET transited from low to high, the value of pin PG[7:6] latched to
NPAGESEL.
00= NAND Flash page size is 2KB.
01= NAND Flash page size is 4KB.
10= NAND Flash page size is 8KB.
11= Ignore power-on setting.
[7:6]
NPAGESEL
UART 0 Debug Message Output ON/OFF Selection
When pin nRESET transited from low to high, the value of pin PG.5 latched to URDBGON.
0= UART 0 debug message output ON.
[5]
[4]
[3]
URDBGON
JTAGSEL
WDTON
1= UART 0 debug message output OFF.
JTAG Interface Selection
When pin nRESET transited from low to high, the value of pin PG.4 latched to JTAGSEL.
0 = Pin PA[6:2] used as JTAG interface.
1 = Pin PG[15:11] used as JTAG interface.
Watchdog Timer (WDT) ON/OFF Selection
When pin nRESET transited from low to high, the value of pin PG.3 latched to WDTON.
0 = After power-on, WDT Disabled.
1 = after power-on WDT Enabled.
QSPI0_CLK Frequency Selection
When pin nRESET transited from low to high, the value of pin PG.2 latched to
QSPI0CKSEL.
[2]
QSPI0CKSEL
0 = QSPI0_CLK frequency is 37.5 MHz.
1 = QSPI0_CLK frequency is 75 MHz.
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Boot Source Selection
When pin nRESET transited from low to high, the value of pin PG[1:0] latched to BTSSEL.
00= Boot from USB.
[1:0]
BTSSEL
01= Boot from SD/eMMC.
10= Boot from NAND Flash.
11= Boot from SPI Flash.
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Low Voltage Reset & Detect Control Register (SYS_LVRDCR)
Register
Offset
R/W
Description
Reset Value
SYS_LVRDCR SYS_BA+0x020 R/W
Low Voltage Reset & Detect Control Register
0x0000_0001
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
24
16
Reserved
Reserved
9
LVD_SEL
1
8
Reserved
LVD_EN
0
Reserved
LVR_EN
Bits
Description
Reserved
[31:10]
Reserved.
Low Voltage Detect Threshold Selection
0 = Low voltage detection level is 2.6V.
1 = Low voltage detection level is 2.8V.
[9]
LVD_SEL
Low Voltage Detect Enable Bit
[8]
LVD_EN
Reserved
LVR_EN
0 = Low voltage detect function Disabled.
1 = Low voltage detect function Enabled.
[7:1]
[0]
Reserved.
Low Voltage Reset Enable Bit
0 = Low voltage reset function Disabled.
1 = Low voltage reset function Enabled.
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Miscellaneous Function Control Register (SYS_MISCFCR)
Register
Offset
R/W
Description
Reset Value
SYS_MISCFCR SYS_BA+0x030 R/W
Miscellaneous Function Control Register
0x0000_0200
31
23
15
7
30
22
29
21
13
5
28
20
12
27
19
26
18
25
17
24
16
Reserved
Reserved
14
Reserved
6
11
10
Reserved
2
9
HDSPUEN
1
8
GPIOLBEN
4
USRHDSEN
3
WDTRSTEN
0
Reserved
Bits
Description
Reserved
[31:13]
Reserved.
GPIO Pin Loop-back Enable Bit
[12]
GPIOLBEN
0 = GPIO input status didn’t reflect pin status if the GPIO configured as functional pin.
1 = GPIO input status did reflect pin status even if the GPIO configured as functional pin.
User Configurable USB Host Device Role Selection Enable Bit
0 = USB host/device role selection decided by HDS pin.
[11]
[10]
[9]
USRHDSEN
Reserved
1 = USB host/device role selection decided by USBID (SYS_PWRON[16]).
Reserved.
HDS Pin Internal Pull-up Enable Bit
HDSPUEN
0 = HDS pin internal pull-up resister Disabled.
1 = HDS pin internal pull-up resister Enabled.
WatchDog Timer Reset Connection Enable Bit
This bit is used to enable the function that connect watch-dog timer reset to nRESET pin. If
this bit is enabled, the watch-dog timer reset is connected to nRESET pin internally
[8]
WDTRSTEN
Reserved
0 = Watch-dog timer reset not connected to nRESET pin internally.
1 = Watch-dog timer reset connected to nRESET pin internally.
[7:0]
Reserved.
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Miscellaneous Interrupt Enable Register (SYS_MISCIER)
Register
Offset
R/W Description
Reset Value
SYS_MISCIER SYS_BA+0x040 R/W Miscellaneous Interrupt Enable Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
Reserved
USBIDC_IEN
LVD_IEN
Bits
Description
Reserved
[31:2]
Reserved.
USB0_ID Pin Status Change Interrupt Enable Bit
0 = HDS status change interrupt Disabled.
1 = HDS status change interrupt Enabled.
[1]
[0]
USBIDC_IEN
LVD_IEN
Low Voltage Detect Interrupt Enable Bit
0 = Low voltage detect interrupt Disabled.
1 = Low voltage detect interrupt Enabled.
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Miscellaneous Interrupt Status Register (SYS_MISCISR)
Register
Offset
R/W Description
Reset Value
SYS_MISCISR SYS_BA+0x044 R/W Miscellaneous Interrupt Status Register
0x0001_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
Reserved
Reserved
17
USB0_IDS
9
16
Reserved
Reserved
IBR_RUN_F
8
1
0
USBIDC_IS
LVD_IS
Bits
Description
Reserved
[31:18]
Reserved.
USB0_ID Status
[17]
USB0_IDS
0 = USB port 0 used as a USB device port.
1 = USB port 0 used as a USB host port.
IBR Run Flag
[16]
[15:2]
[1]
IBR_RUN_F
Reserved
0 = CPU didn’t execute instruction in 0xFFFF_0000 yet.
1 = CPU executed instruction in 0xFFFF_0000.
Reserved.
USB0_ID Pin State Change Interrupt Status
USBIDC_IS
0 = USB0_ID state didn’t change.
1 = USB0_ID state changed from low to high or from high to low.
Low Voltage Detect Interrupt Status
0 = No low voltage event.
[0]
LVD_IS
1 = Low voltage event detected.
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System Wakeup Source Enable Register 0 (SYS_WKUPSER0)
Register
Offset
R/W
Description
Reset Value
SYS_WKUPSER0
SYS_BA+0x050 R/W
System Wakeup Source Enable Register 0
0x0000_0000
31
23
30
22
29
21
28
27
26
25
UR9WKEN
17
24
UR8WKEN
16
Reserved
20
UR4WKEN
12
19
UR3WKEN
11
18
UR2WKEN
10
UR7WKEN
15
UR6WKEN
14
UR5WKEN
13
UR1WKEN
9
UR0WKEN
8
Reserved
TMR5WKEN TMR4WKEN TMR3WKEN TMR2WKEN TMR1WKEN TMR0WKEN
7
6
5
4
3
2
1
0
EINT3WKEN EINT2WKEN EINT1WKEN EINT0WKEN GPIOWKEN
Reserved
Reserved
WDTWKEN
Bits
Description
Reserved
[31:26]
Reserved.
UART 9 Wake System Up Enable Bit
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
UR9WKEN
UR8WKEN
UR7WKEN
UR6WKEN
UR5WKEN
UR4WKEN
UR3WKEN
UR2WKEN
0 = UART 9 wake system up function Disabled.
1 = UART 9 wake system up function Enabled.
UART 8 Wake System Up Enable Bit
0 = UART 8 wake system up function Disabled.
1 = UART 8 wake system up function Enabled.
UART 7 Wake System Up Enable Bit
0 = UART 7 wake system up function Disabled.
1 = UART 7 wake system up function Enabled.
UART 6 Wake System Up Enable Bit
0 = UART 6 wake system up function Disabled.
1 = UART 6 wake system up function Enabled.
UART 5 Wake System Up Enable Bit
0 = UART 5 wake system up function Disabled.
1 = UART 5 wake system up function Enabled.
UART 4 Wake System Up Enable Bit
0 = UART 4 wake system up function Disabled.
1 = UART 4 wake system up function Enabled.
UART 3 Wake System Up Enable Bit
0 = UART 3 wake system up function Disabled.
1 = UART 3 wake system up function Enabled.
UART 2 Wake System Up Enable Bit
0 = UART 2 wake system up function Disabled.
1 = UART 2 wake system up function Enabled.
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UART 1 Wake System Up Enable Bit
[17]
UR1WKEN
0 = UART 1 wake system up function Disabled.
1 = UART 1 wake system up function Enabled.
UART 0 Wake System Up Enable Bit
[16]
UR0WKEN
Reserved
0 = UART 0 wake system up function Disabled.
1 = UART 0 wake system up function Enabled.
[15:14]
[13]
Reserved.
TIMER 5 Wake System Up Enable Bit
TMR5WKEN
0 = TIMER 5 wake system up function Disabled.
1 = TIMER 5 wake system up function Enabled.
TIMER 4 Wake System Up Enable Bit
[12]
[11]
[10]
[9]
TMR4WKEN
TMR3WKEN
TMR2WKEN
TMR1WKEN
TMR0WKEN
EINT3WKEN
EINT2WKEN
EINT1WKEN
EINT0WKEN
0 = TIMER 4 wake system up function Disabled.
1 = TIMER 4 wake system up function Enabled.
TIMER 3 Wake System Up Enable Bit
0 = TIMER 3 wake system up function Disabled.
1 = TIMER 3 wake system up function Enabled.
TIMER 2 Wake System Up Enable Bit
0 = TIMER 2 wake system up function Disabled.
1 = TIMER 2 wake system up function Enabled.
TIMER 1 Wake System Up Enable Bit
0 = TIMER 1 wake system up function Disabled.
1 = TIMER 1 wake system up function Enabled.
TIMER 0 Wake System Up Enable Bit
[8]
0 = TIMER 0 wake system up function Disabled.
1 = TIMER 0 wake system up function Enabled.
External Interrupt 3 Wake System Up Enable Bit
0 = External Interrupt 3 wake system up function Disabled.
1 = External Interrupt 3 wake system up function Enabled.
[7]
External Interrupt 2 Wake System Up Enable Bit
0 = External Interrupt 2 wake system up function Disabled.
1 = External Interrupt 2 wake system up function Enabled.
[6]
External Interrupt 1 Wake System Up Enable Bit
0 = External Interrupt 1 wake system up function Disabled.
1 = External Interrupt 1 wake system up function Enabled.
[5]
External Interrupt 0 Wake System Up Enable Bit
0 = External Interrupt 0 wake system up function Disabled.
1 = External Interrupt 0 wake system up function Enabled.
[4]
GPIO Wake System Up Enable Bit
[3]
GPIOWKEN
Reserved
0 = GPIO wake system up function Disabled.
1 = GPIO wake system up function Enabled.
[2:1]
Reserved.
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WDT Wake System Up Enable Bit
[0]
WDTWKEN
0 = WDT wake system up function Disabled.
1 = WDT wake system up function Enabled.
Jan. 28, 2019
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System Wakeup Source Enable Register 1 (SYS_WKUPSER1)
Register
Offset
R/W Description
Reset Value
SYS_WKUPSER1 SYS_BA+0x054 R/W System Wakeup Source Enable Register 1
0x0000_0000
31
23
30
29
21
28
27
19
26
18
25
17
24
16
Reserved
22
Reserved
14
20
SDHWKEN
12
USBDWKEN USBHWKEN EMAC1WKEN EMAC0WKEN
11 10
CAN3WKEN CAN2WKEN CAN1WKEN CAN0WKEN
15
13
9
8
LVDWKEN
7
Reserved
5
6
4
3
2
1
0
RTCWKEN
Reserved
I2C3WKEN
I2C2WKEN
I2C1WKEN
I2C0WKEN
Bits
Description
Reserved
[31:21]
Reserved.
SDH Wake System Up Enable Bit
[20]
SDHWKEN
0 = SDH wake system up function Disabled.
1 = SDH wake system up function Enabled.
USB Device Wake System Up Enable Bit
[19]
[18]
[17]
[16]
USBDWKEN
USBHWKEN
EMAC1WKEN
EMAC0WKEN
0 = USB device wake system up function Disabled.
1 = USB device wake system up function Enabled.
USB Host Wake System Up Enable Bit
0 = USB host wake system up function Disabled.
1 = USB host wake system up function Enabled.
Ethernet MAC 1 Wake System Up Enable Bit
0 = Ethernet MAC 1 wake system up function Disabled.
1 = Ethernet MAC 1 wake system up function Enabled.
Ethernet MAC 0 Wake System Up Enable Bit
0 = Ethernet MAC 0 wake system up function Disabled.
1 = Ethernet MAC 0 wake system up function Enabled.
Low Voltage Detect Wake System Up Enable Bit
0 = Low Voltage Detect wake system up function Disabled.
1 = Low Voltage Detect wake system up function Enabled.
[15]
LVDWKEN
Reserved
[14:12]
[11]
Reserved.
CAN 3 Wake System Up Enable Bit
CAN3WKEN
0 = CAN 3 wake system up function Disabled.
1 = CAN 3 wake system up function Enabled.
Jan. 28, 2019
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CAN 2 Wake System Up Enable Bit
[10]
[9]
CAN2WKEN
CAN1WKEN
CAN0WKEN
0 = CAN 2 wake system up function Disabled.
1 = CAN 2 wake system up function Enabled.
CAN 1 Wake System Up Enable Bit
0 = CAN 1 wake system up function Disabled.
1 = CAN 1 wake system up function Enabled.
CAN 0 Wake System Up Enable Bit
[8]
0 = CAN 0 wake system up function Disabled.
1 = CAN 0 wake system up function Enabled.
RTC Wake System Up Enable Bit
[7]
RTCWKEN
Reserved
I2C3WKEN
0 = RTC wake system up function Disabled.
1 = RTC wake system up function Enabled.
[6:4]
[3]
Reserved.
I2C 3 Wake System Up Enable Bit
0 = I2C 3 wake system up function Disabled.
1 = I2C 3 wake system up function Enabled.
I2C 2 Wake System Up Enable Bit
[2]
[1]
[0]
I2C2WKEN
I2C1WKEN
I2C0WKEN
0 = I2C 2 wake system up function Disabled.
1 = I2C 2 wake system up function Enabled.
I2C 1 Wake System Up Enable Bit
0 = I2C 1 wake system up function Disabled.
1 = I2C 1 wake system up function Enabled.
I2C 0 Wake System Up Enable Bit
0 = I2C 0 wake system up function Disabled.
1 = I2C 0 wake system up function Enabled.
Jan. 28, 2019
Page 107 of 246
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System Wakeup Source Status Register 0 (SYS_WKUPSSR0)
Register
Offset
R/W Description
Reset Value
SYS_WKUPSSR0 SYS_BA+0x058 R/W System Wakeup Source Status Register 0
0x0000_0000
31
30
29
21
28
27
26
25
UR9WKST
17
24
UR8WKST
16
Reserved
23
UR7WKST
15
22
UR6WKST
14
20
UR4WKST
12
19
UR3WKST
11
18
UR2WKST
10
UR5WKST
13
UR1WKST
9
UR0WKST
8
Reserved
TMR5WKST TMR4WKST TMR3WKST TMR2WKST TMR1WKST TMR0WKST
7
6
5
4
3
2
1
0
EINT3WKST EINT2WKST EINT1WKST EINT0WKST GPIOWKST
Reserved
Reserved
WDTWKST
Bits
Description
Reserved
[31:26]
Reserved.
UART 9 Wake System Up Status
0 = UART 9 didn’t wake system up.
1 = UART 9 wake system up.
[25]
UR9WKST
UR8WKST
UR7WKST
UR6WKST
UR5WKST
UR4WKST
UR3WKST
UR2WKST
UART 8 Wake System Up Status
0 = UART 8 didn’t wake system up.
1 = UART 8 wake system up.
[24]
[23]
[22]
[21]
[20]
[19]
[18]
UART 7 Wake System Up Status
0 = UART 7 didn’t wake system up.
1 = UART 7 wake system up.
UART 6 Wake System Up Status
0 = UART 6 didn’t wake system up.
1 = UART 6 wake system up.
UART 5 Wake System Up Status
0 = UART 5 didn’t wake system up.
1 = UART 5 wake system up.
UART 4 Wake System Up Status
0 = UART 4 didn’t wake system up.
1 = UART 4 wake system up.
UART 3 Wake System Up Status
0 = UART 3 didn’t wake system up.
1 = UART 3 wake system up.
UART 2 Wake System Up Status
0 = UART 2 didn’t wake system up.
1 = UART 2 wake system up.
Jan. 28, 2019
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UART 1 Wake System Up Status
0 = UART 1 didn’t wake system up.
1 = UART 1 wake system up.
[17]
UR1WKST
UART 0 Wake System Up Status
0 = UART 0 didn’t wake system up.
1 = UART 0 wake system up.
[16]
UR0WKST
Reserved
[15:14]
[13]
Reserved.
TIMER 5 Wake System Up Status
0 = TIMER 5 didn’t wake system up.
1 = TIMER 5 wake system up.
TMR5WKST
TIMER 4 Wake System Up Status
0 = TIMER 4 didn’t wake system up.
1 = TIMER 4 wake system up.
[12]
[11]
[10]
[9]
TMR4WKST
TMR3WKST
TMR2WKST
TMR1WKST
TMR0WKST
EINT3WKST
EINT2WKST
EINT1WKST
EINT0WKST
TIMER 3 Wake System Up Status
0 = TIMER 3 didn’t wake system up.
1 = TIMER 3 wake system up.
TIMER 2 Wake System Up Status
0 = TIMER 2 didn’t wake system up.
1 = TIMER 2 wake system up.
TIMER 1 Wake System Up Status
0 = TIMER 1 didn’t wake system up.
1 = TIMER 1 wake system up.
TIMER 0 Wake System Up Status
0 = TIMER 0 didn’t wake system up.
1 = TIMER 0 wake system up.
[8]
External Interrupt 3 Wake System Up Status
0 = External Interrupt 3 didn’t wake system up.
1 = External Interrupt 3 wake system up.
[7]
External Interrupt 2 Wake System Up Status
0 = External Interrupt 2 didn’t wake system up.
1 = External Interrupt 2 wake system up.
[6]
External Interrupt 1 Wake System Up Status
0 = External Interrupt 1 didn’t wake system up.
1 = External Interrupt 1 wake system up.
[5]
External Interrupt 0 Wake System Up Status
0 = External Interrupt 0 didn’t wake system up.
1 = External Interrupt 0 wake system up.
[4]
GPIO Wake System Up Status
0 = GPIO didn’t wake system up.
1 = GPIO wake system up.
[3]
GPIOWKST
Reserved
[2:1]
Reserved.
Jan. 28, 2019
Page 109 of 246
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WDT Wake System Up Status
0 = WDT didn’t wake system up.
1 = WDT wake system up.
[0]
WDTWKST
Jan. 28, 2019
Page 110 of 246
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System Wakeup Source Status Register 1 (SYS_WKUPSSR1)
Register
Offset
R/W Description
Reset Value
SYS_WKUPSSR1 SYS_BA+0x05C R/W System Wakeup Source Status Register 1
0x0000_0000
31
23
30
29
21
28
Reserved
20
27
19
26
18
25
17
24
ADCWKST
16
22
Reserved
14
SDHWKST
12
USBDWKST USBHWKST EMAC1WKST EMAC0WKST
11 10
CAN3WKST CAN2WKST CAN1WKST CAN0WKST
15
13
9
8
LVDWKST
7
Reserved
5
6
4
3
2
1
0
RTCWKST
Reserved
I2C3WKST
I2C2WKST
I2C1WKST
I2C0WKST
Bits
Description
Reserved
[31:25]
Reserved.
ADC Wake System Up Status
0 = ADC didn’t wake system up.
1 = ADC wake system up.
[24]
ADCWKST
Reserved
SDHWKST
[23:21]
[20]
Reserved.
SDH Wake System Up Status
0 = SDH didn’t wake system up.
1 = SDH wake system up.
USB Device Wake System Up Status
0 = USB device didn’t wake system up.
1 = USB device wake system up.
[19]
[18]
[17]
[16]
USBDWKST
USBHWKST
EMAC1WKST
EMAC0WKST
USB Host Wake System Up Status
0 = USB host didn’t wake system up.
1 = USB host wake system up.
Ethernet MAC 1 Wake System Up Status
0 = Ethernet MAC 1 didn’t wake system up.
1 = Ethernet MAC 1 wake system up.
Ethernet MAC 0 Wake System Up Status
0 = Ethernet MAC 0 didn’t wake system up.
1 = Ethernet MAC 0 wake system up.
Low Voltage Detect Wake System Up Status
0 = Low Voltage Detect didn’t wake system up.
1 = Low Voltage Detect wake system up.
[15]
LVDWKST
Reserved
[14:12]
Reserved.
Jan. 28, 2019
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CAN 3 Wake System Up Status
0 = CAN 3 didn’t wake system up.
1 = CAN 3 wake system up.
[11]
[10]
[9]
CAN3WKST
CAN2WKST
CAN1WKST
CAN0WKST
CAN 2 Wake System Up Status
0 = CAN 2 didn’t wake system up.
1 = CAN 2 wake system up.
CAN 1 Wake System Up Status
0 = CAN 1 didn’t wake system up.
1 = CAN 1 wake system up.
CAN 0 Wake System Up Status
0 = CAN 0 didn’t wake system up.
1 = CAN 0 wake system up.
[8]
RTC Wake System Up Status
0 = RTC didn’t wake system up.
1 = RTC wake system up.
[7]
RTCWKST
Reserved
I2C3WKST
[6:4]
[3]
Reserved.
I2C 3 Wake System Up Status
0 = I2C 3 didn’t wake system up.
1 = I2C 3 wake system up.
I2C 2 Wake System Up Status
0 = I2C 2 didn’t wake system up.
1 = I2C 2 wake system up.
[2]
[1]
[0]
I2C2WKST
I2C1WKST
I2C0WKST
I2C 1 Wake System Up Status
0 = I2C 1 didn’t wake system up.
1 = I2C 1 wake system up.
I2C 0 Wake System Up Status
0 = I2C 0 didn’t wake system up.
1 = I2C 0 wake system up.
Jan. 28, 2019
Page 112 of 246
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AHB IP Reset Control Register (SYS_AHBIPRST)
Register
Offset
R/W Description
Reset Value
SYS_AHBIPRST SYS_BA+0x060 R/W AHB IP Reset Control Register
0x0000_0000
31
30
22
14
6
29
21
13
28
Reserved
20
27
26
25
24
SDHRST
16
23
CRYPTORST
15
19
USBDRST
11
18
USBHRST
10
17
EMAC1RST
9
Reserved
Reserved
FMIRST
12
EMAC0RST
8
VCAP1RST
3
VCAP0RST
2
Reserved
1
I2SRST
0
7
5
4
GPIORST
SDICRST
PDMA1RST
PDMA0RST
EBIRST
CPURST
Reserved
CHIPRST
Bits
Description
Reserved
[31:25]
Reserved.
SDIO Controller Reset Enable Bit
0 = SDIO controller reset Disabled.
1 = SDIO controller reset Enabled.
[24]
SDHRST
Cryptographic Accelerator Reset Enable Bit
0 = Cryptographic Accelerator reset Disabled.
1 = Cryptographic Accelerator reset Enabled.
[23]
CRYPTORST
Reserved
FMIRST
[22:21]
[20]
Reserved.
FMI Controller Reset Enable Bit
0 = FMI controller reset Disabled.
1 = FMI controller reset Enabled.
USB Device Controller Reset Enable Bit
0 = USB device controller reset Disabled.
1 = USB device controller reset Enabled.
[19]
[18]
[17]
USBDRST
USBHRST
EMAC1RST
USB Host Controller (EHCI/OHCI) Reset Enable Bit
0 = USB host controller (EHCI/OHCI) reset Disabled.
1 = USB host controller (EHCI/OHCI) reset Enabled.
Ethernet MAC 1 Reset Enable Bit
0 = Ethernet MAC 1 reset Disabled.
1 = Ethernet MAC 1 reset Enabled.
Ethernet MAC 0 Reset Enable Bit
0 = Ethernet MAC 0 reset Disabled.
1 = Ethernet MAC 0 reset Enabled.
[16]
EMAC0RST
Reserved
[15:12]
Reserved.
Jan. 28, 2019
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Capture Sensor Interface 1 Reset Enable Bit
0 = Capture sensor interface 1 reset Disabled.
1 = Capture sensor interface 1 reset Enabled.
[11]
VCAP1RST
Capture Sensor Interface 0 Reset Enable Bit
0 = Capture sensor interface 0 reset Disabled.
1 = Capture sensor interface 0 reset Enabled.
[10]
[9]
VCAP0RST
Reserved
I2S
Reserved.
I2S Controller Reset Enable Bit
0 = I2S controller reset Disabled.
1 = I2S controller reset Enabled.
[8]
GPIO Reset Enable Bit
0 = GPIO reset Disabled.
1 = GPIO reset Enabled.
[7]
[6]
[5]
[4]
GPIORST
SDRAM Controller Reset Enable Bit
0 = SDRAM controller reset Disabled.
1 = SDRAM Controller reset Enabled.
SDICRST
PDMA1 Reset Enable Bit
0 = PDMA1 reset Disabled.
1 = PDMA1 reset Enabled.
PDMA1RST
PDMA0RST
PDMA0 Reset Enable Bit
0 = PDMA0 reset Disabled.
1 = PDMA0 reset Enabled.
CPU Pulse Reset Enable Bit
This bit is used to generate a reset pulse to Arm926EJ-S™ CPU.
When set this bit high, reset controller generates a 6 system clock long reset pulse to
Arm926EJ-S™ CPU. After the reset completed, this bit will be clear to low automatically.
[2]
CPURST
0 = CPU pulse reset Disabled.
1 = CPU pulse reset Enabled.
[1]
[0]
Reserved
CHIP
Reserved.
Chip Reset Enable Bit
0 = Chip reset Disabled.
1 = Chip reset Enabled.
Jan. 28, 2019
Page 114 of 246
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APB IP Reset Control Register 0 (SYS_APBIPRST0)
Register
Offset
R/W Description
Reset Value
SYS_APBIPRST0 SYS_BA+0x064 R/W APB IP Reset Control Register 0
0x0000_0000
31
30
29
Reserved
21
28
27
26
Reserved
18
25
UART9RST
17
24
UART8RST
16
23
UART7RST
15
22
UART6RST
14
20
UART4RST
12
19
UART3RST
11
UART5RST
13
UART2RST
10
UART1RST
9
UART0RST
8
Reserved
TIMER5RST TIMER4RST TIMER3RST TIMER2RST TIMER1RST TIMER0RST
7
6
5
4
3
2
1
0
Reserved
AICRST
Reserved
Bits
Description
Reserved
[31:26]
Reserved.
UART 9 Reset Enable Bit
0 = UART 9 reset Disabled.
1 = UART 9 reset Enabled.
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
UART9RST
UART8RST
UART7RST
UART6RST
UART5RST
UART4RST
UART3RST
UART2RST
UART 8 Reset Enable Bit
0 = UART 8 reset Disabled.
1 = UART 8 reset Enabled.
UART 7 Reset Enable Bit
0 = UART 7 reset Disabled.
1 = UART 7 reset Enabled.
UART 6 Reset Enable Bit
0 = UART 6 reset Disabled.
1 = UART 6 reset Enabled.
UART 5 Reset Enable Bit
0 = UART 5 reset Disabled.
1 = UART 5 reset Enabled.
UART 4 Reset Enable Bit
0 = UART 4 reset Disabled.
1 = UART 4 reset Enabled.
UART 3 Reset Enable Bit
0 = UART 3 reset Disabled.
1 = UART 3 reset Enabled.
UART 2 Reset Enable Bit
0 = UART 2 reset Disabled.
1 = UART 2 reset Enabled.
Jan. 28, 2019
Page 115 of 246
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UART 1 Reset Enable Bit
0 = UART 1 reset Disabled.
1 = UART 1 reset Enabled.
[17]
UART1RST
UART 0 Reset Enable Bit
0 = UART 0 reset Disabled.
1 = UART 0 reset Enabled.
[16]
UART0RST
Reserved
[15:14]
[13]
Reserved.
TIMER 5 Reset Enable Bit
0 = TIMER 5 reset Disabled.
1 = TIMER 5 reset Enabled.
TIMER5RST
TIMER 4 Reset Enable Bit
0 = TIMER 4 reset Disabled.
1 = TIMER 4 reset Enabled.
[12]
[11]
[10]
[9]
TIMER4RST
TIMER3RST
TIMER2RST
TIMER1RST
TIMER 3 Reset Enable Bit
0 = TIMER 3 reset Disabled.
1 = TIMER 3 reset Enabled.
TIMER 2 Reset Enable Bit
0 = TIMER 2 reset Disabled.
1 = TIMER 2 reset Enabled.
TIMER 1 Reset Enable Bit
0 = TIMER 1 reset Disabled.
1 = TIMER 1 reset Enabled.
TIMER 0 Reset Enable Bit
0 = TIMER 0 reset Disabled.
1 = TIMER 0 reset Enabled.
[8]
TIMER0RST
Reserved
AICRST
[7:5]
[4]
Reserved.
AIC Reset Enable Bit
0 = AIC reset Disabled.
1 = AIC reset Enabled.
[3:0]
Reserved
Reserved.
Jan. 28, 2019
Page 116 of 246
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APB IP Reset Control Register 1 (SYS_APBIPRST1)
Register
Offset
R/W Description
Reset Value
SYS_APBIPRST1 SYS_BA+0x068 R/W APB IP Reset Control Register 1
0x0000_0000
31
23
15
7
30
22
14
29
21
13
28
20
27
PWM1RST
19
26
PWM0RST
18
25
Reserved
17
24
ADCRST
16
Reserved
Reserved
12
11
CAN3RST
3
10
CAN2RST
2
9
8
Reserved
SMC1RST
5
SMC0RST
4
CAN1RST
1
CAN0RST
0
6
Reserved
SPI1RST
SPI0RST
QSPI0RST
I2C3RST
I2C2RST
I2C1RST
I2C0RST
Bits
Description
Reserved
[31:28]
Reserved.
PWM1 Reset Enable Bit
0 = PWM1 reset Disabled.
1 = PWM1 reset Enabled.
[27]
PWM1RST
PWM0 Reset Enable Bit
0 = PWM0 reset Disabled.
1 = PWM0 reset Enabled.
[26]
PWM0RST
Reserved
ADCRST
[25]
Reserved.
ADC Reset Enable Bit
0 = ADC reset Disabled.
1 = ADC reset Enabled.
[24]
[23:14]
[13]
Reserved
SMC1RST
Reserved.
SMC 1 Reset Enable Bit
0 = SMC 1 reset Disabled.
1 = SMC 1 reset Enabled.
SMC 0 Reset Enable Bit
0 = SMC 0 reset Disabled.
1 = SMC 0 reset Enabled.
[12]
[11]
[10]
SMC0RST
CAN3RST
CAN2RST
CAN 3 Reset Enable Bit
0 = CAN 3 reset Disabled.
1 = CAN 3 reset Enabled.
CAN 2 Reset Enable Bit
0 = CAN 2 reset Disabled.
1 = CAN 2 reset Enabled.
Jan. 28, 2019
Page 117 of 246
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CAN 1 Reset Enable Bit
0 = CAN 1 reset Disabled.
1 = CAN 1 reset Enabled.
[9]
CAN1RST
CAN 0 Reset Enable Bit
0 = CAN 0 reset Disabled.
1 = CAN 0 reset Enabled.
[8]
[7]
[6]
CAN0RST
Reserved
SPI1RST
Reserved.
SPI 1 Reset Enable Bit
0 = SPI 1 reset Disabled.
1 = SPI 1 reset Enabled.
SPI 1 Reset Enable Bit
0 = SPI 0 reset Disabled.
1 = SPI 0 reset Enabled.
[5]
[4]
[3]
[2]
[1]
[0]
SPI0RST
QSPI0RST
I2C3RST
I2C2RST
I2C1RST
I2C0RST
QSPI 0 Reset Enable Bit
0 = QSPI 0 reset Disabled.
1 = QSPI 0 reset Enabled.
I2C 3 Reset Enable Bit
0 = I2C 3 reset Disabled.
1 = I2C 3 reset Enabled.
I2C 1 Reset Enable Bit
0 = I2C 2 reset Disabled.
1 = I2C 2 reset Enabled.
I2C 1 Reset Enable Bit
0 = I2C 1 reset Disabled.
1 = I2C 1 reset Enabled.
I2C 0 Reset Enable Bit
0 = I2C 0 reset Disabled.
1 = I2C 0 reset Enabled.
Jan. 28, 2019
Page 118 of 246
Rev 1.00
NUC980
Reset Source Active Status Register (SYS_RSTSTS)
Register
Offset
R/W Description
Reset Value
SYS_RSTSTS SYS_BA+0x06C R/W Reset Source Active Status Register
0x0000_00XX
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
26
18
10
25
17
9
24
16
8
Reserved
Reserved
Reserved
5
3
2
1
0
Reserved
WDTRSTS
CPURSTS
CHIPRSTS
LVRRSTS
PINRSTS
PORRSTS
Bits
Description
Reserved
[31:5]
Reserved.
Chip Reset by Watchdog Timer Status
[5]
[4]
WDTRSTS
CPURSTS
0 = No reset from watchdog timer.
1 = Watchdog timer had issued reset signal to reset the chip.
CPU Reset by CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) Status
0 = No CPU reset from CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]).
1 = CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) has been high to reset the
CPU.
Chip Reset by CHIP (AHBIPRST[0]) Status
0 = No reset from CHIP (AHBIPRST[0]).
[3]
[2]
[1]
[0]
CHIPRSTS
LVRRSTS
PINRSTS
PORRSTS
1 = CHIP (AHBIPRST[0]) has been high to reset CPU.
Chip Reset by LVRD Status
0 = No reset from LVRD.
1 = LVRD had issued reset signal to reset the chip.
Chip Reset by NRESET Pin Status
0 = No reset from nRESET pin.
1 = nRESET pin had issued reset signal to reset the chip.
Chip Reset by POR Status
0 = No reset from POR.
1 = POR had issued reset signal to reset the chip.
Jan. 28, 2019
Page 119 of 246
Rev 1.00
NUC980
GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPA_MF
PL
SYS_BA+0x070 R/W GPIOA Low Byte Multiple Function Control Register
0x0XXX_XX00
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPA7
MFP_GPA5
MFP_GPA3
MFP_GPA1
MFP_GPA6
MFP_GPA4
MFP_GPA2
MFP_GPA0
1
0
Bits
Description
MFP_GPA7
MFP_GPA6
MFP_GPA5
MFP_GPA4
MFP_GPA3
MFP_GPA2
MFP_GPA1
MFP_GPA0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PA.7 Multi-function Pin Selection
Pin PA.6 Multi-function Pin Selection
Pin PA.5 Multi-function Pin Selection
Pin PA.4 Multi-function Pin Selection
Pin PA.3 Multi-function Pin Selection
Pin PA.2 Multi-function Pin Selection
Pin PA.1 Multi-function Pin Selection
Pin PA.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 120 of 246
Rev 1.00
NUC980
GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPA_MF
PH
SYS_BA+0x074 R/W GPIOA High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPA15
MFP_GPA13
MFP_GPA11
MFP_GPA9
MFP_GPA14
MFP_GPA12
MFP_GPA10
MFP_GPA8
1
0
Bits
Description
MFP_GPA15
MFP_GPA14
MFP_GPA13
MFP_GPA12
MFP_GPA11
MFP_GPA10
MFP_GPA9
MFP_GPA8
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PA.15 Multi-function Pin Selection
Pin PA.14 Multi-function Pin Selection
Pin PA.13 Multi-function Pin Selection
Pin PA.12 Multi-function Pin Selection
Pin PA.11 Multi-function Pin Selection
Pin PA.10 Multi-function Pin Selection
Pin PA.9 Multi-function Pin Selection
Pin PA.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 121 of 246
Rev 1.00
NUC980
GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPB_MF
PL
SYS_BA+0x078 R/W GPIOB Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPB7
MFP_GPB5
MFP_GPB3
MFP_GPB1
MFP_GPB6
MFP_GPB4
MFP_GPB2
MFP_GPB0
1
0
Bits
Description
MFP_GPB7
MFP_GPB6
MFP_GPB5
MFP_GPB4
MFP_GPB3
MFP_GPB2
MFP_GPB1
MFP_GPB0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PB.7 Multi-function Pin Selection
Pin PB.6 Multi-function Pin Selection
Pin PB.5 Multi-function Pin Selection
Pin PB.4 Multi-function Pin Selection
Pin PB.3 Multi-function Pin Selection
Pin PB.2 Multi-function Pin Selection
Pin PB.1 Multi-function Pin Selection
Pin PB.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 122 of 246
Rev 1.00
NUC980
GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPB_MF
PH
SYS_BA+0x07C R/W GPIOB High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
MFP_GPB13
MFP_GPB11
MFP_GPB9
MFP_GPB12
MFP_GPB10
MFP_GPB8
1
0
Bits
Description
Reserved
[31:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Reserved.
MFP_GPB13
MFP_GPB12
MFP_GPB11
MFP_GPB10
MFP_GPB9
MFP_GPB8
Pin PB.13 Multi-function Pin Selection
Pin PB.12 Multi-function Pin Selection
Pin PB.11 Multi-function Pin Selection
Pin PB.10 Multi-function Pin Selection
Pin PB.9 Multi-function Pin Selection
Pin PB.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 123 of 246
Rev 1.00
NUC980
GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPC_MF
PL
SYS_BA+0x080 R/W GPIOC Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPC7
MFP_GPC5
MFP_GPC3
MFP_GPC1
MFP_GPC6
MFP_GPC4
MFP_GPC2
MFP_GPC0
1
0
Bits
Description
MFP_GPC7
MFP_GPC6
MFP_GPC5
MFP_GPC4
MFP_GPC3
MFP_GPC2
MFP_GPC1
MFP_GPC0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PC.7 Multi-function Pin Selection
Pin PC.6 Multi-function Pin Selection
Pin PC.5 Multi-function Pin Selection
Pin PC.4 Multi-function Pin Selection
Pin PC.3 Multi-function Pin Selection
Pin PC.2 Multi-function Pin Selection
Pin PC.1 Multi-function Pin Selection
Pin PC.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 124 of 246
Rev 1.00
NUC980
GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPC_MF
PH
SYS_BA+0x084 R/W GPIOC High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPC15
MFP_GPC13
MFP_GPC11
MFP_GPC9
MFP_GPC14
MFP_GPC12
MFP_GPC10
MFP_GPC8
1
0
Bits
Description
MFP_GPC15
MFP_GPC14
MFP_GPC13
MFP_GPC12
MFP_GPC11
MFP_GPC10
MFP_GPC9
MFP_GPC8
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PC.15 Multi-function Pin Selection
Pin PC.14 Multi-function Pin Selection
Pin PC.13 Multi-function Pin Selection
Pin PC.12 Multi-function Pin Selection
Pin PC.11 Multi-function Pin Selection
Pin PC.10 Multi-function Pin Selection
Pin PC.9 Multi-function Pin Selection
Pin PC.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 125 of 246
Rev 1.00
NUC980
GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPD_MF
PL
SYS_BA+0x088 R/W GPIOD Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPD7
MFP_GPD5
MFP_GPD3
MFP_GPD1
MFP_GPD6
MFP_GPD4
MFP_GPD2
MFP_GPD0
1
0
Bits
Description
MFP_GPD7
MFP_GPD6
MFP_GPD5
MFP_GPD4
MFP_GPD3
MFP_GPD2
MFP_GPD1
MFP_GPD0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PD.7 Multi-function Pin Selection
Pin PD.6 Multi-function Pin Selection
Pin PD.5 Multi-function Pin Selection
Pin PD.4 Multi-function Pin Selection
Pin PD.3 Multi-function Pin Selection
Pin PD.2 Multi-function Pin Selection
Pin PD.1 Multi-function Pin Selection
Pin PD.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 126 of 246
Rev 1.00
NUC980
GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPD_MF
PH
SYS_BA+0x08C R/W GPIOD High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPD15
MFP_GPD13
MFP_GPD11
MFP_GPD9
MFP_GPD14
MFP_GPD12
MFP_GPD10
MFP_GPD8
1
0
Bits
Description
MFP_GPD15
MFP_GPD14
MFP_GPD13
MFP_GPD12
MFP_GPD11
MFP_GPD10
MFP_GPD9
MFP_GPD8
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PD.15 Multi-function Pin Selection
Pin PD.14 Multi-function Pin Selection
Pin PD.13 Multi-function Pin Selection
Pin PD.12 Multi-function Pin Selection
Pin PD.11 Multi-function Pin Selection
Pin PD.10 Multi-function Pin Selection
Pin PD.9 Multi-function Pin Selection
Pin PD.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 127 of 246
Rev 1.00
NUC980
GPIOE Low Byte Multiple Function Control Register (SYS_GPE_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPE_MFP
L
SYS_BA+0x090 R/W GPIOE Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPE7
MFP_GPE5
MFP_GPE3
MFP_GPE1
MFP_GPE6
MFP_GPE4
MFP_GPE2
MFP_GPE0
1
0
Bits
Description
MFP_GPE7
MFP_GPE6
MFP_GPE5
MFP_GPE4
MFP_GPE3
MFP_GPE2
MFP_GPE1
MFP_GPE0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PE.7 Multi-function Pin Selection
Pin PE.6 Multi-function Pin Selection
Pin PE.5 Multi-function Pin Selection
Pin PE.4 Multi-function Pin Selection
Pin PE.3 Multi-function Pin Selection
Pin PE.2 Multi-function Pin Selection
Pin PE.1 Multi-function Pin Selection
Pin PE.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 128 of 246
Rev 1.00
NUC980
GPIOE High Byte Multiple Function Control Register (SYS_GPE_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPE_MFP
H
SYS_BA+0x094 R/W GPIOE High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
MFP_GPE11
MFP_GPE9
MFP_GPE12
MFP_GPE10
MFP_GPE8
1
0
Bits
Description
Reserved
[31:20]
[19:16]
[15:12]
[11:8]
[7:4]
Reserved.
MFP_GPE12
MFP_GPE11
MFP_GPE10
MFP_GPE9
MFP_GPE8
Pin PE.12 Multi-function Pin Selection
Pin PE.11 Multi-function Pin Selection
Pin PE.10 Multi-function Pin Selection
Pin PE.9 Multi-function Pin Selection
Pin PE.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 129 of 246
Rev 1.00
NUC980
GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPF_MFP
L
SYS_BA+0x098 R/W GPIOF Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPF7
MFP_GPF5
MFP_GPF3
MFP_GPF1
MFP_GPF6
MFP_GPF4
MFP_GPF2
MFP_GPF0
1
0
Bits
Description
MFP_GPF7
MFP_GPF6
MFP_GPF5
MFP_GPF4
MFP_GPF3
MFP_GPF2
MFP_GPF1
MFP_GPF0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PF.7 Multi-function Pin Selection
Pin PF.6 Multi-function Pin Selection
Pin PF.5 Multi-function Pin Selection
Pin PF.4 Multi-function Pin Selection
Pin PF.3 Multi-function Pin Selection
Pin PF.2 Multi-function Pin Selection
Pin PF.1 Multi-function Pin Selection
Pin PF.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 130 of 246
Rev 1.00
NUC980
GPIOF High Byte Multiple Function Control Register (SYS_GPF_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPF_MFP
H
SYS_BA+0x09C R/W GPIOF High Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
MFP_GPF11
MFP_GPF9
MFP_GPF12
MFP_GPF10
MFP_GPF8
1
0
Bits
Description
Reserved
[31:20]
[19:16]
[15:12]
[11:8]
[7:4]
Reserved.
MFP_GPF12
MFP_GPF11
MFP_GPF10
MFP_GPF9
MFP_GPF8
Pin PF.12 Multi-function Pin Selection
Pin PF.11 Multi-function Pin Selection
Pin PF.10 Multi-function Pin Selection
Pin PF.9 Multi-function Pin Selection
Pin PF.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 131 of 246
Rev 1.00
NUC980
GPIOG Low Byte Multiple Function Control Register (SYS_GPG_MFPL)
Register
Offset
R/W Description
Reset Value
SYS_GPG_MF
PL
SYS_BA+0x0A0 R/W GPIOG Low Byte Multiple Function Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPG7
MFP_GPG5
MFP_GPG3
MFP_GPG1
MFP_GPG6
MFP_GPG4
MFP_GPG2
MFP_GPG0
1
0
Bits
Description
MFP_GPG7
MFP_GPG6
MFP_GPG5
MFP_GPG4
MFP_GPG3
MFP_GPG2
MFP_GPG1
MFP_GPG0
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PG.7 Multi-function Pin Selection
Pin PG.6 Multi-function Pin Selection
Pin PG.5 Multi-function Pin Selection
Pin PG.4 Multi-function Pin Selection
Pin PG.3 Multi-function Pin Selection
Pin PG.2 Multi-function Pin Selection
Pin PG.1 Multi-function Pin Selection
Pin PG.0 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 132 of 246
Rev 1.00
NUC980
GPIOG High Byte Multiple Function Control Register (SYS_GPG_MFPH)
Register
Offset
R/W Description
Reset Value
SYS_GPG_MF
PH
SYS_BA+0x0A4 R/W GPIOG High Byte Multiple Function Control Register
0xXXXX_X000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
MFP_GPG15
MFP_GPG13
MFP_GPG11
MFP_GPG9
MFP_GPG14
MFP_GPG12
MFP_GPG10
MFP_GPG8
1
0
Bits
Description
MFP_GPG15
MFP_GPG14
MFP_GPG13
MFP_GPG12
MFP_GPG11
MFP_GPG10
MFP_GPG9
MFP_GPG8
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
Pin PG.15 Multi-function Pin Selection
Pin PG.14 Multi-function Pin Selection
Pin PG.13 Multi-function Pin Selection
Pin PG.12 Multi-function Pin Selection
Pin PG.11 Multi-function Pin Selection
Pin PG.10 Multi-function Pin Selection
Pin PG.9 Multi-function Pin Selection
Pin PG.8 Multi-function Pin Selection
[3:0]
Jan. 28, 2019
Page 133 of 246
Rev 1.00
NUC980
DDR I/O Driving Strength Control Register (SYS_DDR_DSCTL)
Register
Offset
R/W Description
Reset Value
SYS_DDR_DS
CTL
SYS_BA+0x0F0 R/W DDR I/O Driving Strength Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
DATA_DS
ADDR_DS
CTRL_DS
CLK_DS
Bits
Description
Reserved
[31:8]
Reserved.
DDR Data I/O Driving Strength Selection
This bit controls the driving strength for DDR I/O used as data.
00 = Reserved.
[7:6]
[5:4]
[3:2]
[1:0]
DATA_DS
ADDR_DS
CTRL_DS
CLK_DS
01 = Reduced Strength.
10 = Reserved.
11 = Full Strength.
DDR Address I/O Driving Strength Selection
This bit controls the driving strength for DDR I/O used as address.
00 = Reserved.
01 = Reduced Strength.
10 = Reserved.
11 = Full Strength.
DDR Control I/O Driving Strength Selection
This bit controls the driving strength for DDR I/O used as control signals.
00 = Reserved.
01 = Reduced Strength.
10 = Reserved.
11 = Full Strength.
DDR Clock I/O Driving Strength Selection
This bit controls the driving strength for DDR I/O used as clock.
00 = Reserved.
01 = Reduced Strength.
10 = Reserved.
11 = Full Strength.
Jan. 28, 2019
Page 134 of 246
Rev 1.00
NUC980
GPIOB Low Byte Driving Strength Control Register (SYS_GPBL_DSCTL)
Register
Offset
R/W Description
Reset Value
SYS_GPBL_DS
CTL
SYS_BA+0x0F4 R/W GPIOB Low Byte Driving Strength Control Register
0x4444_4444
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
DS_GPB7
DS_GPB5
DS_GPB3
DS_GPB1
DS_GPB6
DS_GPB4
DS_GPB2
DS_GPB0
1
0
Bits
Description
Pin PB.7 Driving Strength Selection
This field controls the pin PB.7 driving strength
000 = Pin PB.7 driving strength is 2.2mA.
001 = Pin PB.7 driving strength is 6.5mA.
010 = Pin PB.7 driving strength is 8.7mA.
011 = Pin PB.7 driving strength is 13.0mA.
100 = Pin PB.7 driving strength is 15.2mA.
101 = Pin PB.7 driving strength is 19.5mA.
110 = Pin PB.7 driving strength is 21.7mA.
111 = Pin PB.7 driving strength is 26.1mA.
Others = Reserved.
[31:28]
DS_GPB7
Pin PB.6 Driving Strength Selection
This field controls the pin PB.6 driving strength
000 = Pin PB.6 driving strength is 2.2mA.
001 = Pin PB.6 driving strength is 6.5mA.
010 = Pin PB.6 driving strength is 8.7mA.
011 = Pin PB.6 driving strength is 13.0mA.
100 = Pin PB.6 driving strength is 15.2mA.
101 = Pin PB.6 driving strength is 19.5mA.
110 = Pin PB.6 driving strength is 21.7mA.
111 = Pin PB.6 driving strength is 26.1mA.
Others = Reserved.
[27:24]
DS_GPB6
Jan. 28, 2019
Page 135 of 246
Rev 1.00
NUC980
Pin PB.5 Driving Strength Selection
This field controls the pin PB.5 driving strength
000 = Pin PB.5 driving strength is 2.2mA.
001 = Pin PB.5 driving strength is 6.5mA.
010 = Pin PB.5 driving strength is 8.7mA.
011 = Pin PB.5 driving strength is 13.0mA.
100 = Pin PB.5 driving strength is 15.2mA.
101 = Pin PB.5 driving strength is 19.5mA.
110 = Pin PB.5 driving strength is 21.7mA.
111 = Pin PB.5 driving strength is 26.1mA.
Others = Reserved.
[23:20]
[19:16]
[15:12]
[11:8]
DS_GPB5
DS_GPB4
DS_GPB3
DS_GPB2
Pin PB.4 Driving Strength Selection
This field controls the pin PB.4 driving strength
000 = Pin PB.4 driving strength is 2.2mA.
001 = Pin PB.4 driving strength is 6.5mA.
010 = Pin PB.4 driving strength is 8.7mA.
011 = Pin PB.4 driving strength is 13.0mA.
100 = Pin PB.4 driving strength is 15.2mA.
101 = Pin PB.4 driving strength is 19.5mA.
110 = Pin PB.4 driving strength is 21.7mA.
111 = Pin PB.4 driving strength is 26.1mA.
Others = Reserved.
Pin PB.3 Driving Strength Selection
This field controls the pin PB.3 driving strength
000 = Pin PB.3 driving strength is 2.2mA.
001 = Pin PB.3 driving strength is 6.5mA.
010 = Pin PB.3 driving strength is 8.7mA.
011 = Pin PB.3 driving strength is 13.0mA.
100 = Pin PB.3 driving strength is 15.2mA.
101 = Pin PB.3 driving strength is 19.5mA.
110 = Pin PB.3 driving strength is 21.7mA.
111 = Pin PB.3 driving strength is 26.1mA.
Others = Reserved.
Pin PB.2 Driving Strength Selection
This field controls the pin PB.2 driving strength
000 = Pin PB.2 driving strength is 2.2mA.
001 = Pin PB.2 driving strength is 6.5mA.
010 = Pin PB.2 driving strength is 8.7mA.
011 = Pin PB.2 driving strength is 13.0mA.
100 = Pin PB.2 driving strength is 15.2mA.
101 = Pin PB.2 driving strength is 19.5mA.
110 = Pin PB.2 driving strength is 21.7mA.
111 = Pin PB.2 driving strength is 26.1mA.
Others = Reserved.
Jan. 28, 2019
Page 136 of 246
Rev 1.00
NUC980
Pin PB.1 Driving Strength Selection
This field controls the pin PB.1 driving strength
000 = Pin PB.1 driving strength is 2.2mA.
001 = Pin PB.1 driving strength is 6.5mA.
010 = Pin PB.1 driving strength is 8.7mA.
011 = Pin PB.1 driving strength is 13.0mA.
100 = Pin PB.1 driving strength is 15.2mA.
101 = Pin PB.1 driving strength is 19.5mA.
110 = Pin PB.1 driving strength is 21.7mA.
111 = Pin PB.1 driving strength is 26.1mA.
Others = Reserved.
[7:4]
DS_GPB1
Pin PB.0 Driving Strength Selection
This field controls the pin PB.0 driving strength
000 = Pin PB.0 driving strength is 2.2mA.
001 = Pin PB.0 driving strength is 6.5mA.
010 = Pin PB.0 driving strength is 8.7mA.
011 = Pin PB.0 driving strength is 13.0mA.
100 = Pin PB.0 driving strength is 15.2mA.
101 = Pin PB.0 driving strength is 19.5mA.
110 = Pin PB.0 driving strength is 21.7mA.
111 = Pin PB.0 driving strength is 26.1mA.
Others = Reserved.
[3:0]
DS_GPB0
Jan. 28, 2019
Page 137 of 246
Rev 1.00
NUC980
Power-On-reset Disable Control Register (SYS_PORDISCR)
Register
Offset
R/W Description
Reset Value
SYS_PORDISC
R
SYS_BA+0x100 R/W Power-On-reset Disable Control Register
0x0000_00XX
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
POR_DIS_CODE
4
3
1
0
POR_DIS_CODE
Bits
Description
Reserved
[31:16]
Reserved.
Power-on-reset Disable Code (Write-protection Bits)
When powered on, the Power-On-Reset (POR) circuit generates a reset signal to reset
whole chip function. However, after power is ready, the POR circuit would consume a few
power. To minimize the POR circuit power consumption, user to disable POR circuit by
writing 0x5AA5 to this field.
[15:0]
POR_DIS_CODE
The POR circuit will become active again when this field is set to other value or chip is
reset by other reset source, including /RESET pin, Watchdog, LVR reset and the software
chip reset function.
This field is protected. It means that before programming it, user has to write “59h”, “16h”
and “88h” to address 0xB000_01FC continuously to disable the register protection. Refer
to the register REGWRPROT at address SYS_BA+0x1FC for detail.
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Reset Pin De-bounce Control Register (SYS_RSTDEBCTL)
Register
Offset
R/W Description
Reset Value
SYS_RSTDEB
CTL
SYS_BA+0x10C R/W Reset Pin De-bounce Control Register
0x0000_04B0
31
RSTDEBEN
23
30
22
14
6
29
21
13
5
28
20
12
4
27
Reserved
19
26
18
10
2
25
17
9
24
16
8
Reserved
15
7
11
3
DEBCNT
DEBCNT
1
0
Bits
Description
RSTDEBEN
Reserved
Reset Pin De-bounce Enable Bit
0 = Reset pin de-bounce Disabled. (Default)
1 = Reset pin de-bounce Enabled.
[31]
[31:16]
Reserved.
Power-on-reset Disable Code (Write-protection Bits)
This 16-bit external RESET De-bounce Counter can specify the external RESET de-
bounce time up to around 5.46ms (0xFFFF) @ XIN=12 MHz.
[15:0]
DEBCNT
The default external RESET de-bounce time is 0.1ms (0x04B0) @ XIN = 12 MHz.
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Register Write-protection Control Register (SYS_REGWPCTL)
Some of the system control registers need to be protected to avoid inadvertent write and disturb the
chip operation. These system control registers are protected after the power-on reset till user to
disable register protection. For user to program these protected registers, a register protection disable
sequence needs to be followed by a special programming. The register protection disable sequence is
writing the data “59h”, “16h” “88h” to the register REGWRPROT address at 0xB000_01FC
continuously. Any different data value, different sequence or any other write to other address during
these three data writing will abort the whole sequence.
After the protection is disabled, user can check the protection disable bit at address 0xB000_01FC
bit0, 1 is protection disable, and 0 is protection enable. Then user can update the target protected
register value and then write any data to the address “0xB000_01FC” to enable register protection.
This register is write for disable/enable register protection and read for the REGWPCTL status
Register
Offset
R/W Description
Reset Value
SYS_REGWPC
TL
SYS_BA+0x1FC R/W Register Write-protection Control Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
1
0
REGWPCTL
Bits
Description
Reserved
[31:8]
Reserved.
Register Write Protection Code
Some registers have write-protection function. Writing these registers has to disable the
protected function by writing the sequence value “59h”, “16h”, “88h” to this field. After this
sequence is completed, the REGWPCTL bit will be set to 1 and write-protection registers
can be normal write.
[7:0]
REGWPCTL
REGWPCTL[0]
Register Write Protection Disable Index
0 = Write-protection Enabled for writing protected registers. Any write to the protected
register is ignored.
1 = Write-protection Disabled for writing protected registers.
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Register Write-protection Disable Indicator (Read Only)
0 = Write-protection Enabled for writing protected registers. Any write to the protected
register is ignored.
1 = Write-protection Disabled for writing protected registers.
The protected registers are:
SYS_PDID: Product Identifier Register, address 0xB000_0000.
SYS_PWRON: Power-On Setting Register, address 0xB000_0004.
SYS_MISCFCR: Miscellaneous Function Control Register, address 0xB000_0030.
SYS_AHBIPRST: AHB IP Reset Control Register, address 0xB000_0060.
SYS_APBIPRST0: APB IP Reset Control Register 0, address 0xB000_0064.
SYS_APBIPRST1: APB IP Reset Control Register 1, address 0xB000_0068.
SYS_PORDISCR: Power-On-Reset Disable Control Register, address 0xB000_0100.
SYS_RSTDEBCTL: Reset Pin De-bounce Control Register, address 0xB000_010C.
WDT_CTL: WDT Control Register, address 0xB004_0000
[0]
REGWPCTL
WDT_ALTCTL: WDT Alternative Control Register, address 0xB004_0004
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates all clocks for Video, Audio, CPU, system bus and all functionalities.
This chip includes two PLL modules. The clock source for each functionality comes from the PLL, or
from the external crystal input directly. For each clock there is a bit on the CLKEN register to control
the clock ON or OFF individually, and the divider setting is in the CLK_DIVCTL register. The register
can also be used to control the clock enable or disable for power control.
6.3.2
Features
Supports two PLLs, up to 500 MHz, for high performance system operation
External 12 MHz high speed crystal input for precise timing operation
External 32.768 kHz low speed crystal input for RTC function and low speed clock source
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6.3.3
Block Diagram
6.3.3.1 Clock Controller Top View
XTALIN12M
(12 MHz)
ADC_CLK
ADC_SW_DIV
ADO_SW_DIV
APLLFOUT
ADivCLK[7:0]
UDivCLK[7:0]
ECLKI2
APLL1to8
UPLL1to8
APLL
S
SD0_CLK
SD1_CLK
SEN0_CLK
UPLLFOUT
SD0_SW_DIV
SD1_SW_DIV
SEN0_SW_DIV
UPLL
XTALIN32K
(32.768 kHz)
PCLK0
PCLK1
÷4096
PCLK2
SEN1_CLK
ECLKUART0
ECLKUART1
ECLKUART2
ECLKUART3
ECLKUART4
ECLKUART5
ECLKUART6
ECLKUART7
ECLKUART8
ECLKUART9
÷512
SEN1_SW_DIV
UART0_SW_DIV
UART1_SW_DIV
UART2_SW_DIV
UART3_SW_DIV
UART4_SW_DIV
UART5_SW_DIV
UART6_SW_DIV
UART7_SW_DIV
UART8_SW_DIV
UART9_SW_DIV
ECLKTMR0
TMR0_SW_DIV
TMR1_SW_DIV
TMR2_SW_DIV
TMR3_SW_DIV
TMR4_SW_DIV
TMR5_SW_DIV
ECLKTMR1
ECLKTMR2
ECLKTMR3
ECLKTMR4
ECLKTMR5
ECLKWDT
WDT_SW_DIV
ECLKQSPI0
ECLKSPI0
ECLKSPI1
QSPI0_SW_DIV
SPI0_SW_DIV
SPI1_SW_DIV
ECLKWWDT
WWDT_SW_DIV
USB_CLK
(48 MHz)
USB_SW_DIV
RMII0_REFCLK (50 MHz)
EMCA0_RXCLK
EMCA0_TXCLK
EMAC0_CLK_DIV
(
÷2, ÷20)
ECLKUART8
ECLKUART9
RMII1_REFCLK (50 MHz)
SMC0_SW_DIV
SMC1_SW_DIV
EMAC1_RXCLK
EMAC1_TXCLK
EMAC1_CLK_DIV
(
÷2, ÷20)
SYS_CLK
SYS_SW_DIV
CPUCLK, HCLK1, HCLK2, HCLK3, HCLK4, PCLK, HCLKSRAM
DDR_CLK, DRAM_CLK,
,
HCLKI2S, HCLKLCD, HCLKUSBH, HCLKUSBD, HCLKEMAC0, HCLKEMAC1 ...
PCLKSPI0, PCLKSPI1, PCLKADC, PCLKI2C, PCLPWM, PCLKSMC0, PCLKSMC1 ...
CPU_HCLK
HCLK4
HCLK3
EMAC0_MDCLK
EMAC1_MDCLK
EMC0_MDCLK_DIV
EMC1_MDCLK_DIV
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-1 Clock Controller Block Diagram
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6.3.3.2 ADC Controller Clock Divider
XTALIN12M
APLLFout
CLK_SW4
(4-to-1)
(MUX)
ADC_SrcCLK
ADC_CLK
CLK_DIVn
(÷ (ADC_N+1))
UPLLFout
ADC_S
ADC_N
ADC
(CLK_DIVCTL7[20:19]) (CLK_DIVCTL7[31:24])
(CLK_PCLKEN1[24])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-2 ADC Controller Clock Divider Block Diagram
6.3.3.3 SD Card Host Controller Clock Divider
X = 0 and m = 3
X = 1 and m = 9
XTALIN12M
APLLFout
CLK_SW4
(4-to-1)
(MUX)
SDx_SrcCLK
SDx_CLK
CLK_DIVn
(÷ (SDx_N+1))
UPLLFout
SDx_S
(CLK_DIVCTLm[4:3])
SDx_N
SDx
(CLK_DIVCTLm[15:8]) (CLK_HCLKEN[x*8+22])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-3 SD Card Host Controller Clock Divider Block Diagram
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6.3.3.4 Timer Clock Divider
M = 0, x = 0, 1, 4, 5
M = 1, x = 2, 3
XTALIN12M
PCLKm
CLK_SW4
(4-to-1)
(MUX)
TIMERx_SrcCLK
ECLKETMRx
PCLKm/4096
XTALIN32K
TMRxSEL
(CLK_DIVCTL8[x*2+17 : x*2+16])
TMRxCKEN
(CLK_PCLKEN0[x+8])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-4 Timer Clock Divider Clock Diagram
6.3.3.5 Ethernet MAC Controller Clock Divider
x
= 0, 1
RMIIx_REFCLK
(50 MHz)
÷ 2
EMACx_RXCLK
EMACx_TXCLK
25 MHz
2.5 MHz
CLK_SW4
(2-to-1)
(MUX)
EMACx_SrcCLK
÷ 20
OPMOD
(EMACx_MCMDR[20])
EMACx
(CLK_HCLKEN[x+16])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-5 Ethernet MAC Controller Clock Divider Block Diagram
6.3.3.6 I2S Controller Clock Divider
XTALIN12M
APLLFout
ECLKI2
I2S_SrcCLK
CLK_SW4
(4-to-1)
(MUX)
CLK_DIVn
S
(÷ (I2S_N+1))
UPLLFout
I2S_S
I2S_N
I2S
(CLK_DIVCTL1[20:19]) (CLK_DIVCTL1[31:24])
(CLK_HCLKEN[24])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-6 I2S Controller Clock Divider Block Diagram
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6.3.3.7 Reference Clock Output Divider
XT1_IN
APLLFout
ACLKOut
CLK_SW4
(4-to-1)
(MUX)
CKO_SrcCLK
CKO_CLK
CLK_DIVn
(÷ (CKO_N+1))
UCLKout
UPLLFout
CKO_S
CKO_N
CKO
(CLK_DIVCTL9[20:19]) (CLK_DIVCTL9[31:24])
(CLK_HCLKEN[15])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-7 Reference Clock Output Divider Block Diagram
6.3.3.8 Smart Card Host Controller Clock Divider
x = 0, 1
ECLKSMCx
CLK_DIVn
(÷ (SMCx_N+1))
XTALIN12M
SMCx_N
(CLK_DIVCTL6[x*4+27:x*4+24])
SMCx
(CLK_PCLKEN1[x+12])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-8 Smart Card Host Controller Clock Divider Block Diagram
6.3.3.9 CMOS Sensor Clock Divider
X = 0 and m = 3
X = 1 and m = 2
XTALIN12M
CLK_DIVn
APLLFout
÷ (SENSORx_SDIV+1)
ACLKOut
CLK_SW4
SENx_SrcCLK
SENx_CLK
SENSORx_SDIV
(CLK_DIVCTLm[18:16])
CLK_DIVn
(÷ (SENSORx_N+1))
(4-to-1)
(MUX)
UCLKout
CLK_DIVn
÷ (SENSORx_SDIV+1)
UPLLFout
SENSORx_S
SENSORx_N
SENSOR (CLK_HCLKEN[27]) &
VCAPx (CLK_HCLKEN[x*5+26])
(CLK_DIVCTLm[20:19]) (CLK_DIVCTLm[27:24])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-9 CMOS Sensor Controller Divider Block Diagram
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6.3.3.10 UART Clock Divider
m = 4, x = 0, 1, 2, 3
m = 5, x = 4, 5, 6, 7
m = 6, x = 8, 9
XT1_IN
(12 MHz)
APLLFout
CLK_SW4
(4-to-1)
(MUX)
UARTX_SrcCLK
ECLKUARTx
CLK_DIVn
(÷ (UARTX_N+1))
UPLLFout
X32_IN
(32.768 kHz)
UARTX_S
(CLK_DIVCTLm)
UARTX_N
(CLK_DIVCTLm)
UARTx
(CLK_PCLKEN0[x+16])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-10 UART Clock Divider Block Diagram
6.3.3.11 USB 1.1 Host 48 MHz Clock Divider
USBPHY0_480M
CLK_SW2
USB11_SrcCLK
USB_CLK
48MZ
CLK_DIVn
(÷ 10)
(2-to-1)
(MUX)
USBPHY1_480M
USBID
(SYS_PWRON[16])
USBH
(CLK_HCLKEN[18])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-11 USB 1.1 Host Controller 48 MHz Clock Divider Block Diagram
6.3.3.12 Watchdog Timer Clock Divider
XTALIN12M
XT1_IN/512
CLK_SW4
WDT_SrcCLK
ECLKWDT
(4-to-1)
(MUX)
PCLK2/4096
XTALIN32K
WDT_S
(CLK_DIVCTL8[9:8])
WDT
(CLK_PCLKEN0[0])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-12 Watchdog Timer Clock Divider Block Diagram
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6.3.3.13 Windowed Watchdog Timer Clock Divider
XTALIN12M
XT1_IN/512
CLK_SW4
WWDT_SrcCLK
ECLKWWDT
(4-to-1)
(MUX)
PCLK2/4096
XTALIN32K
WWDT_S
(CLK_DIVCTL8[11:10])
WWDT
(CLK_PCLKEN0[1])
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-13 Windowed Watchdog Timer Clock Divider Block Diagram
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6.3.3.14 CPU_HCLK Clock Generator
DRAM (CLK_HCLKEN[10])
HCLK (CLK_HCLKEN[1])
APLLFOUT
APLL
DDR_CLK
ADivCLK[7:0]
÷ 2
÷ 2
APLL
1to8
DRAM_CLK
HCLK
UPLLFOUT
SRAM (CLK_HCLKEN[8])
HCLKSRAM
UPLL
HCLK1 (CLK_HCLKEN[2]) |
HCLK3 (CLK_HCLKEN[3]) |
HCLK4 (CLK_HCLKEN[4])
UDivCLK[7:0]
UPLL
1to8
HCLK2
HCLK3
XT1_IN
HCLK3 (CLK_HCLKEN[3])
SYSDIVEN2,
SYSTEM_S[4:3]
SYS_SW_DIV
EMAC1 (CLK_HCLKEN[17])
HCLKEMAC1
EMAC1_MDCLK
÷ (MDCLK_N+1)
SYS_CLK
CPU_HCLK Clock Generator
CPUDIVEN2
USBH (CLK_HCLKEN[18])
USBD (CLK_HCLKEN[19])
HCLKUSBH
HCLKUSBD
HCLKFMI
÷ 1 or ÷2
÷ 2
FMI
(CLK_HCLKEN[20])
CPUCLK
NAND (CLK_HCLKEN[21])
CRYPTO(CLK_HCLKEN[23])
VCAP1 (CLK_HCLKEN[31])
HCLKNAND
HCLKCRYPTO
HCLKVCAP1
CPU
(CLK_HCLKEN[0])
HCLK1 (CLK_HCLKEN[2])
HCLK1
HCLKPDMA0
HCLKPDMA1
HCLKPIC
PDMA0(CLK_HCLKEN[12])
PDMA1(CLK_HCLKEN[13])
EBI
(CLK_HCLKEN[ 9])
HCLKEBI
GPIO (CLK_HCLKEN[11])
HCLKGPIO
PIC
(CLK_HCLKEN[7])
÷ 2
HCLK4 (CLK_HCLKEN[4])
HCLK4
PCLK0
PCLK0 (CLK_HCLKEN[5])
EMAC0 (CLK_HCLKEN[16])
÷ (MDCLK_N+1)
HCLKEMAC0
PCLKI2
C0
I2C0CKEN(CLK_PCLKEN1[0])
I2C2CKEN(CLK_PCLKEN1[2])
EMAC0_MDCLK
PCLKI2
C2
SDH
2S
(CLK_HCLKEN[30])
(CLK_HCLKEN[24])
HCLKSDH
PCLKQSPI0
PCLKSPI1
QSPI0CKEN(CLK_PCLKEN1[4])
SPI1CKEN(CLK_PCLKEN1[6])
I
HCLKI2
S
VCAP0 (CLK_HCLKEN[26])
PCLK2 (CLK_HCLKEN[14])
HCLKVCAP0
PCLK2
PCLKTIMER0
PCLKTIMER1
TMR0CKEN(CLK_PCLKEN0[8])
TMR1CKEN(CLK_PCLKEN0[9])
PCLKTIMER4
PCLKTIMER5
PCLKUART0
PCLKUART2
PCLKUART4
PCLKUART6
PCLKUART8
PCLKRTC
TMR4CKEN(CLK_PCLKEN0[12])
TMR5CKEN(CLK_PCLKEN0[13])
UART0CKEN(CLK_PCLKEN0[16])
UART2CKEN(CLK_PCLKEN0[18])
RTCCKEN(CLK_PCLKEN0[2])
WDTCKEN(CLK_PCLKEN0[0])
PCLKWDT
PCLKWWDT
PCLKCAN0
PCLKCAN1
PCLKCAN2
PCLKCAN3
WWDTCKEN(CLK_PCLKEN0[1])
CAN0CKEN(CLK_PCLKEN1[8])
UART4CKEN(CLK_PCLKEN0[20])
UART6CKEN(CLK_PCLKEN0[22])
CAN1CKEN(CLK_PCLKEN1[9])
CAN2CKEN(CLK_PCLKEN1[10])
UART8CKEN(CLK_PCLKEN0[24])
CAN3CKEN(CLK_PCLKEN1[11])
SMC0CKEN(CLK_PCLKEN1[12])
SMC1CKEN(CLK_PCLKEN1[13])
PCLKSMC0
PCLKSMC1
PCLKPWM0
PCLKPWM1
PCLK1
PCLK1 (CLK_HCLKEN[6])
PWM0CKEN(CLK_PCLKEN1[26])
PWM1CKEN(CLK_PCLKEN1[27])
PCLKI2
C1
I2C1CKEN(CLK_PCLKEN1[1])
I2C3CKEN(CLK_PCLKEN1[3])
PCLKI2
C3
PCLKSPI0
SPI0CKEN(CLK_PCLKEN1[5])
UART5CKEN(CLK_PCLKEN0[21])
PCLKUART5
PCLKUART7
PCLKUART9
PCLKTIMER2
PCLKTIMER3
PCLKUART1
PCLKUART3
TMR2CKEN(CLK_PCLKEN0[10])
TMR3CKEN(CLK_PCLKEN0[11])
UART1CKEN(CLK_PCLKEN0[17])
UART3CKEN(CLK_PCLKEN0[19])
UART7CKEN(CLK_PCLKEN0[23])
UART9CKEN(CLK_PCLKEN0[25])
ADCCKEN(CLK_PCLKEN1[24])
PCLKADC
Note: Before clock switching, both the pre-selected and
newly selected clock sources must be turned on and stable.
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-14 CPU_HCLK Clock Generator Block Diagram
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6.3.4
Functional Description
6.3.4.1 Power Management
This chip provides four power management scenarios, including Power-down, Idle and Normal
Operating modes, to manage the power consumption. The peripheral clocks can be Enabled /
Disabled individually by controlling the corresponding bit in CLKSEL control register. User can turn-off
the unused modules’ clock for power saving.
6.3.4.2 Normal Operating Mode
In this mode, CPU runs normally and clocks of all functionalities are on. The clock frequency of CPU,
DRAM, AHB peripherals and APB peripherals are 300 MHz, 150 MHz, 150 MHz and 75 MHz,
respectively.
6.3.4.3 Idle Mode
When CPU is not busy, user can put Arm926EJ-S™ processor into a low-power state by the wait for
interrupt instruction:
MCR p15, 0, <Rd>, c7, c0, 4
This instruction switches the Arm926EJ-S™ processor into a low-power state until either an interrupt
(IRQ or FIQ) or a debug request occurs.
In this mode, the clocks of all functionalities are on. The clock frequency of DRAM, AHB peripherals
and APB peripherals are 150 MHz, 150 MHz and 75 MHz.
6.3.4.4 Power-down Mode
To reduce power consumption further, user could put the chip into Power-down mode by clearing
XTAL_EN (CLK_PMCON[0]) to 0 before waiting for interrupt instruction:
MCR p15, 0, <Rd>, c7, c0, 4
In this mode, all clocks (clocks for all functionalities, CPU and the HXT (Ext. Crystall Osc. 12 MHz)
stop, except LXT (Ext. Crystal Osc. 32.768 kHz), with SRAM retention.
The mechanisms shown below could wake chip up from Power-down mode:
EINT0, EINT1, EINT2 or EINT3 (External Interrupt) pin toggled.
GPIO pin toggled.
Timer 0/1/2/3/4/5 timeout or capture interrupt is active.
WDT time-out interrupt is active.
RTC alarm or relative alarm interrupt is active.
UART 0/1/2/3/4/5/6/7/8/9
– UARTx_nCTS pin toggleed (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9).
– UARTx_RXD pin goes low level (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9).
– Received data FIFO reached threshold.
– Received data FIFO threshold time-out.
– RS-485 address match (AAD Mode).
I2C slave mode address match.
EMAC 0/1 received a Magic Packet.
HSUSBD detected a VBUS change event or USB bus RESET/RESUME event.
USB 1.1 host controller detected a connect/dis-connect/remote-wakeup event.
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CANx_RXD pin goes low level (x is 0, 1, 2 or 3).
SDH detected card pulg/un-plug event or SDIO card interrupt.
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6.3.5
Registers Map
R: read only, W: write only, R/W: both read and write
Register
Offset
R/W
Description
Reset Value
CLK Base Address:
CLK_BA = 0xB000_0200
CLK_PMCON
CLK_BA+0x000 R/W
Power Management Control Register
AHB Devices Clock Enable Control Register
APB Devices Clock Enable Control Register 0
APB Devices Clock Enable Control Register 1
Clock Divider Control Register 0
Clock Divider Control Register 1
Clock Divider Control Register 2
Clock Divider Control Register 3
Clock Divider Control Register 4
Clock Divider Control Register 5
Clock Divider Control Register 6
Clock Divider Control Register 7
Clock Divider Control Register 8
Clock Divider Control Register 9
APLL Control Register
0xFFFF_FF03
0x0000_4527
0x0000_000X
0x0000_0000
0x0000_00XX
0x0000_0000
0x0000_1500
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0500
0x0000_0000
0x1000_0018
0xX000_0018
CLK_HCLKEN CLK_BA+0x010 R/W
CLK_PCLKEN0 CLK_BA+0x018 R/W
CLK_PCLKEN1 CLK_BA+0x01C R/W
CLK_DIVCTL0 CLK_BA+0x020 R/W
CLK_DIVCTL1 CLK_BA+0x024 R/W
CLK_DIVCTL2 CLK_BA+0x028 R/W
CLK_DIVCTL3 CLK_BA+0x02C R/W
CLK_DIVCTL4 CLK_BA+0x030 R/W
CLK_DIVCTL5 CLK_BA+0x034 R/W
CLK_DIVCTL6 CLK_BA+0x038 R/W
CLK_DIVCTL7 CLK_BA+0x03C R/W
CLK_DIVCTL8 CLK_BA+0x040 R/W
CLK_DIVCTL9 CLK_BA+0x044 R/W
CLK_APLLCON CLK_BA+0x060 R/W
CLK_UPLLCON CLK_BA+0x064 R/W
UPLL Control Register
CLK_PLLSTBC
CLK_BA+0x080 R/W
NTR
PLL Stable Counter and Test Clock Control Register
0x0000_1800
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6.3.6
Register Description
Power Management Control Register (CLK_PMCON)
The chip clock source is from an external crystal. The crystal oscillator can be control on/off by the
register XTAL_EN. When turn off the crystal, the chip into power down state. To avoid outputting an
unstable clock to system, clock controller implements a pre-scalar counter. After the clock counter
count pre-scalar x 256 crystal cycle, the clock controller starts to output the clock to system.
Register
Offset
R/W Description
Reset Value
CLK_PMCON
CLK_BA+0x000 R/W Power Management Control Register
0xFFFF_FF03
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
PRESCALE
PRESCALE
1
0
Reserved
SEN1_OFF_S SEN0_OFF_S
Reserved
XIN_CTL
XTAL_EN
Bits
Description
Reserved
[31:24]
Reserved.
Pre-scalar Counter
[23:8]
[7:6]
PRESCALE
Reserved
Assume the crystal is stable after the Pre-Scalar x 256 crystal cycles. Clock controller
wouldn’t output clock to system before the counter reaching (pre-scalar x 256).
Reserved.
Sensor 1 Clock Level on Clock Off State
0 = Sensor 1 clock keep on low level.
1 = Sensor 1 clock keep on high level.
[5]
SEN1_OFF_ST
Sensor Clock Level on Clock Off State
0 = Sensor 0 clock keep on low level.
1 = Sensor 0 clock keep on high level.
[4]
SEN0_OFF_ST
Reserved
[3:2]
Reserved.
Pre-scalar Counter Enable Bit
Crystal pre-divide control for Wake-up from power down mode The chip will delay 256 x
pre-scalar cycles after the reset signal to wait the Crystal to stable
[1]
[0]
XIN_CTL
XTAL_EN
0 = The pre-scalar counter Disabled (assume the crystal is stable).
1 = The pre-scalar counter Enabled.
Crystal (Power-down) Control
0 = Crystal off (Power-down mode).
1 = Crystal on (Normal operating mode).
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AHB Devices Clock Enable Control Register (CLK_HCLKEN)
Register
Offset
R/W Description
Reset Value
CLK_HCLKEN CLK_BA+0x010 R/W AHB Devices Clock Enable Control Register
0x0000_4527
31
VCAP1
23
30
SD1
22
29
Reserved
21
28
Reserved
20
27
SENSOR
19
26
VCAP0
18
25
Reserved
17
24
I2S
16
CRYPTO
15
SD0
14
NAND
13
FMI
USBD
11
USBH
10
EMAC1
9
EMAC0
8
12
CKO
7
PCLK2
6
PDMA1
5
PDMA0
4
GPIO
3
SDIC
2
EBI
SRAM
0
1
TIC
PCLK1
PCLK0
HCLK4
HCLK3
HCLK1
HCLK
CPU
Bits
Description
CMOS Sensor Interface Controller 1 Clock Enable Bit
0 = CMOS sensor interface controller 1 clock Disabled.
1 = CMOS sensor interface controller 1 clock Enabled.
[31]
VCAP1
SD Card Controller 1 Clock Enable Bit
0 = SD card controller 1 clock Disabled.
1 = SD card controller 1 clock Enabled.
[30]
SD1
[29:28]
Reserved
Reserved.
CMOS Sensor Reference Clock Output Enable Bit
0 = CMOS sensor reference clock output Disabled.
1 = CMOS sensor reference clock output Enabled.
[27]
SENSOR
Note1: The reference clock output for CMOS sensor interface 0 only Enabled when both
VCAP0 and SENSOR Enabled.
Note2: The reference clock output for CMOS sensor interface 1 only Enabled when both
VCAP1 and SENSOR Enabled.
CMOS Sensor Interface Controller 0 Clock Enable Bit
0 = CMOS sensor interface controller 0 clock Disabled.
1 = CMOS sensor interface controller 0 clock Enabled.
[26]
[25]
[24]
VCAP0
Reserved
I2S
Reserved.
I2S Controller Clock Enable Bit
0 = I2S controller clock Disabled.
1 = I2S controller clock Enabled.
Crypto Engine Clock Enable Bit
0 = Crypto engine clock Disabled.
1 = Crypto engine clock Enabled.
[23]
CRYPTO
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SD Card Controller 0 Clock Enable Bit
0 = SD card controller 0 clock Disabled.
1 = SD card controller 0 clock Enabled.
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
SD0
NAND Engine Clock Enable Bit
0 = NAND controller clock Disabled.
1 = NAND controller clock Enabled.
NAND
FMI
FMI Controller Clock Enable Bit
0 = FMI controller clock Disabled.
1 = FMI controller clock Enabled.
USB Device Controller Clock Enable Bit
0 = USB device controller clock Disabled.
1 = USB device controller clock Enabled.
USBD
USBH
EMAC1
EMAC0
CKO
USB Host Controller Clock Enable Bit
0 = USB host controller clock Disabled.
1 = USB host controller clock Enabled.
Ethernet MAC Controller 1 Clock Enable Bit
0 = Ethernet MAC controller 1 clock Disabled.
1 = Ethernet MAC controller 1 clock Enabled.
Ethernet MAC Controller 0 Clock Enable Bit
0 = Ethernet MAC controller 0 clock Disabled.
1 = Ethernet MAC controller 0 clock Enabled.
Reference Clock Output Enable Bit
0 = Reference clock output Disabled.
1 = Reference clock output Enabled.
Internal APB-2 Bus Clock Enable Bit
0 = Internal APB-2 bus clock Disabled.
1 = Internal APB-2 bus clock Enabled.
PCLK2
PDMA1
PDMA0
GPIO
SDIC
PDMA 1 Clock Enable Bit
0 = PDMA 1 clock Disabled.
1 = PDMA 1 clock Enabled.
PDMA 0 Clock Enable Bit
0 = PDMA 0 clock Disabled.
1 = PDMA 0 clock Enabled.
GPIO Clock Enable Bit
0 = GPIO clock Disabled.
1 = GPIO clock Enabled.
SDIC Clock Enable Bit
0 = DDR clock Disabled.
1 = DDR clock Enabled.
EBI Controller Clock Enable Bit
0 = EBI controller clock Disabled.
1 = EBI controller clock Enabled.
EBI
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SRAM Controller Clock Enable Bit
0 = SRAM controller clock Disabled.
1 = SRAM controller clock Enabled.
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
SRAM
TIC
TIC Clock Enable Bit
0 = TIC clock Disabled.
1 = TIC clock Enabled.
Internal APB-1 Bus Clock Enable Bit
0 = Internal APB-1 bus clock Disabled.
1 = Internal APB-1 bus clock Enabled.
PCLK1
PCLK0
HCLK4
HCLK3
HCLK1
HCLK
CPU
Internal APB-0 Bus Clock Enable Bit
0 = Internal APB-1 bus clock Disabled.
1 = Internal APB-1 bus clock Enabled.
Internal AHB-4 Bus Clock Enable Bit
0 = Internal AHB-4 bus clock Disabled.
1 = Internal AHB-4 bus clock Enabled.
Internal AHB-3 Bus Clock Enable Bit
0 = Internal AHB-3 bus clock Disabled.
1 = Internal AHB-3 bus clock Enabled.
Internal AHB-1 Bus Clock Enable Bit
0 = Internal AHB-1 bus clock Disabled.
1 = Internal AHB-1 bus clock Enabled.
Internal AHB Bus Clock Enable Bit
0 = Internal AHB bus clock Disabled.
1 = Internal AHB bus clock Enabled.
Arm926EJ-S™ CPU Clock Enable Bit
0 = Arm926EJ-S™ CPU clock Disabled.
1 = Arm926EJ-S™ CPU clock Enabled.
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APB Devices Clock Enable Control Register 0 (CLK_PCLKEN0)
Register
Offset
R/W Description
Reset Value
CLK_PCLKEN0 CLK_BA+0x018 R/W APB Devices Clock Enable Control Register 0
0x0000_000X
31
23
30
22
29
21
28
20
27
19
26
18
25
24
Reserved
UART9CKEN UART8CKEN
17 16
UART7CKEN UART6CKEN UART5CKEN UART4CKEN UART3CKEN UART2CKEN UART1CKEN UART0CKEN
15
14
13
TMR5CKEN
5
12
TMR4CKEN
4
11
TMR3CKEN
3
10
TMR2CKEN
2
9
8
Reserved
TMR1CKEN
1
TMR0CKEN
0
7
6
Reserved
Reserved
RTCCKEN
WWDTCKEN WDTCKEN
Bits
Description
Reserved
[31:26]
Reserved.
UART 9 Clock Enable Bit
0 = UART 9 clock Disabled.
1 = UART 9 clock Enabled.
[25]
UART9CKEN
UART8CKEN
UART7CKEN
UART6CKEN
UART5CKEN
UART4CKEN
UART3CKEN
UART2CKEN
UART 8 Clock Enable Bit
0 = UART 8 clock Disabled.
1 = UART 8 clock Enabled.
[24]
[23]
[22]
[21]
[20]
[19]
[18]
UART 7 Clock Enable Bit
0 = UART 7 clock Disabled.
1 = UART 7 clock Enabled.
UART 6 Clock Enable Bit
0 = UART 6 clock Disabled.
1 = UART 6 clock Enabled.
UART 5 Clock Enable Bit
0 = UART 5 clock Disabled.
1 = UART 5 clock Enabled.
UART 4 Clock Enable Bit
0 = UART 4 clock Disabled.
1 = UART 4 clock Enabled.
UART 3 Clock Enable Bit
0 = UART 3 clock Disabled.
1 = UART 3 clock Enabled.
UART 2 Clock Enable Bit
0 = UART 2 clock Disabled.
1 = UART 2 clock Enabled.
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UART 1 Clock Enable Bit
0 = UART 1 clock Disabled.
1 = UART 1 clock Enabled.
[17]
UART1CKEN
UART 0 Clock Enable Bit
0 = UART 0 clock Disabled.
1 = UART 0 clock Enabled.
[16]
UART0CKEN
Reserved
[15:14]
[13]
Reserved.
Timer 5 Clock Enable Bit
0 = Timer 5 clock Disabled.
1 = Timer 5 clock Enabled.
TMR5CKEN
Timer 4 Clock Enable Bit
0 = Timer 4 clock Disabled.
1 = Timer 4 clock Enabled.
[12]
[11]
[10]
[9]
TMR4CKEN
TMR3CKEN
TMR2CKEN
TMR1CKEN
Timer 3 Clock Enable Bit
0 = Timer 3 clock Disabled.
1 = Timer 3 clock Enabled.
Timer 2 Clock Enable Bit
0 = Timer 2 clock Disabled.
1 = Timer 2 clock Enabled.
Timer 1 Clock Enable Bit
0 = Timer 1 clock Disabled.
1 = Timer 1 clock Enabled.
Timer 0 Clock Enable Bit
0 = Timer 0 clock Disabled.
1 = Timer 0 clock Enabled.
[8]
TMR0CKEN
Reserved
[7:3]
[2]
Reserved.
RTC Clock Enable Bit
0 = RTC clock Disabled.
1 =RTC clock Enabled.
RTCCKEN
Windowed Watch-dog Clock Enable Bit
0 = Windowed Watch-dog clock Disabled.
1 = Windowed Watch-dog clock Enabled.
[1]
[0]
WWDTCKEN
WDTCKEN
Watch-dog Clock Enable Bit
0 = Watch-dog clock Disabled.
1 = Watch-dog clock Enabled.
Note: If WDT default Enabled (WDTON(SYS_PWRON[3])=1), this bit is read-only and read
back value is always 1.
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APB Devices Clock Enable Control Register 1 (CLK_PCLKEN1)
Register
Offset
R/W Description
Reset Value
CLK_PCLKEN1 CLK_BA+0x01C R/W APB Devices Clock Enable Control Register 1
0x0000_0000
31
23
15
7
30
22
14
29
21
13
28
20
12
27
26
25
Reserved
17
24
ADCCKEN
16
Reserved
PWM1CKEN PWM0CKEN
19
11
18
Reserved
10
CAN2CKEN
2
9
8
Reserved
SMC1CKEN SMC0CKEN CAN3CKEN
CAN1CKEN
1
CAN0CKEN
0
6
5
4
3
Reserved
SPI1CKEN
SPI0CKEN
QSPI0CKEN
I2C3CKEN
I2C2CKEN
I2C1CKEN
I2C0CKEN
Bits
Description
[31:26]
Reserved
Reserved.
PWM 1 Clock Enable Bit
0 = PWM 1 clock Disabled.
1 = PWM 1 clock Enabled.
[27]
PWM1CKEN
PWM 0 Clock Enable Bit
0 = PWM 0 clock Disabled.
1 = PWM 0 clock Enabled.
[26]
PWM0CKEN
Reserved
[25]
Reserved.
ADC Controller Clock Enable Bit
0 = ADC controller clock Disabled.
1 = ADC controller clock Enabled.
[24]
ADCCKEN
Reserved
[23:14]
[13]
Reserved.
Smart Card Interface 1 Clock Enable Bit
0 = Smart Card interface 1 clock Disabled.
1 = Smart Card interface 1 clock Enabled.
SMC1CKEN
Smart Card Interface 0 Clock Enable Bit
0 = Smart Card interface 0 clock Disabled.
1 = Smart Card interface 0 clock Enabled.
[12]
[11]
[10]
SMC0CKEN
CAN3CKEN
CAN2CKEN
CAN 3 Clock Enable Bit
0 = CAN 3 clock Disabled.
1 = CAN 3 clock Enabled.
CAN 2 Clock Enable Bit
0 = CAN 2 clock Disabled.
1 = CAN 2 clock Enabled.
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CAN 1 Clock Enable Bit
0 = CAN 1 clock Disabled.
1 = CAN 1 clock Enabled.
[9]
CAN1CKEN
CAN 0 Clock Enable Bit
0 = CAN 0 clock Disabled.
1 = CAN 0 clock Enabled.
[8]
[7]
[6]
CAN0CKEN
Reserved
Reserved.
SPI 1 Clock Enable Bit
0 = SPI 1 clock Disabled.
1 = SPI 1 clock Enabled.
SPI1CKEN
SPI 0 Clock Enable Bit
0 = SPI 0 clock Disabled.
1 = SPI 0 clock Enabled.
[5]
[4]
[3]
[2]
[1]
[0]
SPI0CKEN
QSPI0CKEN
I2C3CKEN
I2C2CKEN
I2C1CKEN
I2C0CKEN
QSPI 0 Clock Enable Bit
0 = QSPI 0 clock Disabled.
1 = QSPI 0 clock Enabled.
I2C 3 Clock Enable Bit
0 = I2C 3 clock Disabled.
1 = I2C 3 clock Enabled.
I2C 2 Clock Enable Bit
0 = I2C 2 clock Disabled.
1 = I2C 2 clock Enabled.
I2C 1 Clock Enable Bit
0 = I2C 1 clock Disabled.
1 = I2C 1 clock Enabled.
I2C 0 Clock Enable Bit
0 = I2C 0 clock Disabled.
1 = I2C 0 clock Enabled.
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Clock Divider Control Register 0 (CLK_DIVCTL0)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL0 CLK_BA+0x020 R/W Clock Divider Control Register 0
0x0000_00XX
31
23
15
7
30
22
14
29
21
13
5
28
20
27
19
11
3
26
18
10
2
25
17
9
24
Reserved
16
Reserved
CPUDIV2EN
12
Reserved
4
8
SYSDIV2EN
0
6
1
Reserved
SYSTEM_S
Reserved
Bits
Description
[31:17]
Reserved
Reserved.
CPU Clock Divided by 2 Enable Bit
This field defines if CPUCLK for Arm926EJ-S™ CPU is SYS_CLK devided by 2 or not.
0 = The frequency of CPUCLK is equal to SYS_CLK.
[16]
CPUDIV2EN
Reserved
1 = The frequency of CPUCLK is SYS_CLK devided by 2.
[15:9]
[8]
Reserved.
System Clock Divided by 2 Enable Bit
This field defines if SYS_CLK is SYSTEM_SrcCLK devided by 2 or not.
0 = The frequency of SYS_CLK is equal to SYSTEM_SrcCLK.
1 = The frequency of SYS_CLK is SYSTEM_SrcCLK devided by 2.
SYSDIV2EN
Reserved
[7:5]
Reserved.
System Clock Source Selection
This field selects which clock is used to be the source of system clock SYS_CLK.
00 = SYSTEM_SrcCLK is from XIN.
[4:3]
[2:0]
SYSTEM_S
Reserved
01 = Reserved.
10 = SYSTEM_SrcCLK is from APLLFout.
11 = SYSTEM_SrcCLK is from UPLLFout.
Reserved.
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Clock Divider Control Register 1 (CLK_DIVCTL1)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL1 CLK_BA+0x024 R/W Clock Divider Control Register 1
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
I2S_N
I2S_S
22
Reserved
14
17
Reserved
9
Reserved
Reserved
6
1
0
Bits
Description
I2S Controller Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for I2S
controller.
[31:24]
[23:21]
I2S_N
The actual clock divide number is (I2S_N + 1). So,
ECLKi2s = I2S_SrcCLK / (I2S_N + 1).
Reserved
Reserved.
I2S Controller Clock Source Selection
This field selects which clock is used to be the source of engine clock for I2S controller.
00 = I2S_SrcCLK is from XIN.
[20:19]
[18:0]
I2S_S
01 = Reserved.
10 = I2S_SrcCLK is from ACLKOut.
11 = I2S_SrcCLK is from UCLKOut.
Reserved
Reserved.
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Clock Divider Control Register 2 (CLK_DIVCTL2)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL2 CLK_BA+0x028 R/W Clock Divider Control Register 2
0x0000_1500
31
23
15
7
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
24
16
Reserved
SENSOR1_N
Reserved
14
SENSOR1_S
SENSOR1_SDIV
9
8
0
Reserved
SPI1_S
SPI0_S
QSPI0_S
6
1
Reserved
USB_S
Reserved
Bits
Description
[31:28]
[27:24]
[23:21]
Reserved
Reserved.
Sensor 1 Clock Divider
This field defines the clock divide number for clock divider to generate the sensor 1 clock.
The actual clock divide number is (SENSOR1_N + 1). So,
SENSOR1_N
Reserved
SEN1_CLK = SEN1_SrcCLK / (SENSOR1_N + 1).
Reserved.
Sensor 1 Clock Source Selection
This field selects which clock is used to be the source of sensor 1 clock.
00 = SEN1_SrcCLK is from XIN.
[20:19]
SENSOR1_S
01 = Reserved.
10 = SEN1_SrcCLK is from ACLKOut.
11 = SEN1_SrcCLK is from UCLKOut.
Sensor 1 Source Clock Divider
This field defines the source clock divide number for clock divider of APLL and UPLL output. This
field only takes effect while the SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b10 (APLL) or 2’b11
(UPLL).
[18:16]
[15:14]
SENSOR1_SDIV
If SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b10,
ACLKOut = APLLFout ÷ (SENSOR1_SDIV + 1).
If SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b11,
UCLKOut = UPLLFout ÷ (SENSOR1_SDIV + 1).
Reserved
Reserved.
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SPI 1 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for SPI 1.
00 = SPI1_SrcCLK is from XIN.
[13:12]
SPI1_S
01 = SPI1_SrcCLK is from PCLK0.
10 = SPI1_SrcCLK is from ACLKOut.
11 = SPI1_SrcCLK is from UCLKOut.
SPI 0 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for SPI 0.
00 = SPI0_SrcCLK is from XIN.
[11:10]
SPI0_S
01 = SPI0_SrcCLK is from PCLK1.
10 = SPI0_SrcCLK is from ACLKOut.
11 = SPI0_SrcCLK is from UCLKOut.
QSPI 0 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for QSPI 0.
00 = QSPI0_SrcCLK is from XIN.
[9:8]
[7:5]
QSPI0_S
Reserved
01 = QSPI0_SrcCLK is from PCLK0.
10 = QSPI0_SrcCLK is from ACLKOut.
11 = QSPI0_SrcCLK is from UCLKOut.
Reserved.
USB 1.1 Engine Clock Source Selection
This field selects which clock is used to be the source of 48 MHz clock for USB 1.1 host
controller.
00 = Reserved.
[4:3]
[2:0]
USB_S
01 = Reserved.
10 = USB11_SrcCLK is from 480 MHz outputted by USB PHY 0.
11 = USB11_SrcCLK is from 480 MHz outputted by USB PHY 1.
Reserved
Reserved.
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Clock Divider Control Register 3 (CLK_DIVCTL3)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL3 CLK_BA+0x02C R/W Clock Divider Control Register 3
0x0000_0000
31
23
15
7
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
24
16
Reserved
SENSOR0_N
Reserved
14
SENSOR0_S
SD0_N
SENSOR0_SDIV
9
8
0
6
1
Reserved
SD0_S
Reserved
Bits
Description
[31:28]
[27:24]
[33:21]
Reserved
Reserved.
Sensor 0 Clock Divider
This field defines the clock divide number for clock divider to generate the sensor 0 clock.
The actual clock divide number is (SENSOR0_N + 1). So,
SENSOR0_N
Reserved
SEN0_CLK = SEN0_SrcCLK / (SENSOR0_N + 1).
Reserved.
Sensor 0 Clock Source Selection
This field selects which clock is used to be the source of sensor 0 clock.
00 = SEN0_SrcCLK is from XIN.
[20:19]
SENSOR0_S
01 = Reserved.
10 = SEN0_SrcCLK is from ACLKOut.
11 = SEN0_SrcCLK is from UCLKOut.
Sensor 0 Source Clock Divider
This field defines the source clock divide number for clock divider of APLL and UPLL output.
This field only takes effect while the SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b10 (APLL) or
2’b11 (UPLL).
[18:16]
SENSOR0_SDIV
If SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b10,
ACLKOut = APLLFout ÷ (SENSOR0_SDIV + 1).
If SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b11,
UCLKOut = UPLLFout ÷ (SENSOR0_SDIV + 1).
SD Card Controller 0 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for SD
card controller 0.
[15:8]
[7:5]
SD0_N
The actual clock divide number is (SD0_N + 1). So,
SD0_CLK = SD0_SrcCLK / (SD0_N + 1).
Reserved
Reserved.
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SD Card Controller 0 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for SD card controller 0.
00: SD0_SrcCLK = XIN.
[4:3]
[2:0]
SD0_S
01: SD0_SrcCLK = Reserved.
10: SD0_SrcCLK = ACLKOut.
11: SD0_SrcCLK = UCLKOut.
Reserved
Reserved.
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Clock Divider Control Register 4 (CLK_DIVCTL4)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL4 CLK_BA+0x030 R/W Clock Divider Control Register 4
0x0000_0000
31
23
15
7
30
UART3_N
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
Reserved
17
24
16
8
UART3_S
UART2_S
UART1_S
UART0_S
UART2_N
14
Reserved
9
UART1_N
6
Reserved
1
0
UART0_N
Reserved
Bits
Description
UART3_N
UART3 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for UART3.
The actual clock divide number is (UART3_N + 1). So,
[31:29]
ECLKuart3 = UART3_SrcCLK / (UART3_N + 1).
UART3 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART3 controller.
00 = UART3_SrcCLK is from XIN.
[28:27]
UART3_S
01 = UART3_SrcCLK is from LXT.
10 = UART3_SrcCLK is from ACLKOut.
11 = UART3_SrcCLK is from UCLKOut.
[26:24]
[23:21]
Reserved
UART2_N
Reserved.
UART2 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for UART2.
The actual clock divide number is (UART2_N + 1). So,
ECLKuart2 = UART2_SrcCLK / (UART2_N + 1).
UART2 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART2 controller.
00 = UART2_SrcCLK is from XIN.
[20:19]
UART2_S
01 = UART2_SrcCLK is from LXT.
10 = UART2_SrcCLK is from ACLKOut.
11 = UART2_SrcCLK is from UCLKOut.
[18:16]
[15:13]
Reserved
UART1_N
Reserved.
UART1 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for UART1.
The actual clock divide number is (UART1_N + 1). So,
ECLKuart1 = UART1_SrcCLK / (UART1_N + 1).
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UART1 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART1 controller.
00 = UART1_SrcCLK is from XIN.
[12:11]
UART1_S
01 = UART1_SrcCLK is from LXT.
10 = UART1_SrcCLK is from ACLKOut.
11 = UART1_SrcCLK is from UCLKOut.
[10:8]
[7:5]
Reserved
UART0_N
Rserved
UART0 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for UART0.
The actual clock divide number is (UART0_N + 1). So,
ECLKuart0 = UART0_SrcCLK / (UART0_N + 1).
UART0 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART0 controller.
00 = UART0_SrcCLK is from XIN.
[4:3]
[2:0]
UART0_S
Reserved
01 = UART0_SrcCLK is from LXT.
10 = UART0_SrcCLK is from ACLKOut.
11 = UART0_SrcCLK is from UCLKOut.
Reserved.
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Clock Divider Control Register 5 (CLK_DIVCTL5)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL5 CLK_BA+0x034 R/W Clock Divider Control Register 5
0x0000_0000
31
23
15
7
30
UART7_N
22
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
Reserved
17
24
16
8
UART7_S
UART6_S
UART5_S
UART4_S
UART6_N
14
Reserved
9
UART5_N
6
Reserved
1
0
UART4_N
Reserved
Bits
Description
UART7 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART7.
[31:29]
[28:27]
UART7_N
UART7_S
The actual clock divide number is (UART7_N + 1). So,
ECLKuart7 = UART7_SrcCLK / (UART7_N + 1).
UART7 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART7 controller.
00 = UART7_SrcCLK is from XIN.
01 = UART7_SrcCLK is from LXT.
10 = UART7_SrcCLK is from ACLKOut.
11 = UART7_SrcCLK is from UCLKOut.
[26:24]
[23:21]
Reserved
UART6_N
Reserved.
UART6 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART6.
The actual clock divide number is (UART6_N + 1). So,
ECLKuart6 = UART6_SrcCLK / (UART6_N + 1).
UART6 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART6 controller.
00 = UART6_SrcCLK is from XIN.
[20:19]
[18:16]
UART6_S
Reserved
01 = UART6_SrcCLK is from LXT.
10 = UART6_SrcCLK is from ACLKOut.
11 = UART6_SrcCLK is from UCLKOut.
Reserved.
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UART5 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART5.
[15:13]
[12:11]
UART5_N
UART5_S
The actual clock divide number is (UART5_N + 1). So,
ECLKuart5 = UART5_SrcCLK / (UART5_N + 1).
UART5 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART5 controller.
00 = UART5_SrcCLK is from XIN.
01 = UART5_SrcCLK is from LXT.
10 = UART5_SrcCLK is from ACLKOut.
11 = UART5_SrcCLK is from UCLKOut.
[10:8]
[7:5]
Reserved
UART4_N
Reserved.
UART4 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART4.
The actual clock divide number is (UART4_N + 1). So,
ECLKuart4 = UART4_SrcCLK / (UART4_N + 1).
UART4 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART4 controller.
00 = UART4_SrcCLK is from XIN.
[4:3]
[2:0]
UART4_S
Reserved
01 = UART4_SrcCLK is from LXT.
10 = UART4_SrcCLK is from ACLKOut.
11 = UART4_SrcCLK is from UCLKOut.
Reserved.
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Clock Divider Control Register 6 (CLK_DIVCTL6)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL6 CLK_BA+0x038 R/W Clock Divider Control Register 6
0x0000_0000
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
SMC1_N
SMC0_N
Reserved
UART9_S
UART8_S
UART9_N
6
Reserved
1
0
UART8_N
Reserved
Bits
Description
Smart Card 1 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for Smart
card controller.
[30:28]
SMC1_N
The actual clock divide number is (SMC1_N + 1). So,
ECLKsmc1 = XIN12M / (SMC1_N + 1).
Smart Card 0 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for Smart
card controller.
[27:24]
[23:16]
[15:13]
SMC0_N
Reserved
UART9_N
The actual clock divide number is (SMC0_N + 1). So,
ECLKsmc0 = XIN12M / (SMC0_N + 1).
Reserved.
UART9 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART9.
The actual clock divide number is (UART9_N + 1). So,
ECLKuart9 = UART9_SrcCLK / (UART9_N + 1).
UART9 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART9 controller.
00 = UART9_SrcCLK is from XIN.
[12:11]
[10:8]
UART9_S
Reserved
01 = UART9_SrcCLK is from LXT.
10 = UART9_SrcCLK is from ACLKOut.
11 = UART9_SrcCLK is from UCLKOut.
Reserved.
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UART8 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for
UART8.
[7:5]
UART8_N
The actual clock divide number is (UART8_N + 1). So,
ECLKuart8 = UART8_SrcCLK / (UART8_N + 1).
UART8 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for UART8 controller.
00 = UART8_SrcCLK is from XIN.
[4:3]
[2:0]
UART8_S
Reserved
01 = UART8_SrcCLK is from LXT.
10 = UART8_SrcCLK is from ACLKOut.
11 = UART8_SrcCLK is from UCLKOut.
Reserved.
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Clock Divider Control Register 7 (CLK_DIVCTL7)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL7 CLK_BA+0x03C R/W Clock Divider Control Register 7
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
ADC_N
ADC_S
22
Reserved
14
17
Reserved
9
Reserved
Reserved
6
1
0
Bits
Description
ADC Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for ADC.
The actual clock divide number is (ADC_N + 1). So,
[31:24]
[23:21]
ADC_N
ADC_CLK = ADC_SrcCLK / (ADC_N + 1).
Reserved
Reserved.
ADC Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for ADC controller.
00 = ADC_SrcCLK is from XIN.
[20:19]
[18:0]
ADC_S
01 = Reserved.
10 = ADC_SrcCLK is from APLLFOut.
11 = ADC_SrcCLK is from UPLLFOut.
Reserved
Reserved.
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Clock Divider Control Register 8 (CLK_DIVCTL8)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL8 CLK_BA+0x040 R/W Clock Divider Control Register 8
0x0000_0500
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
Reserved
Reserved
TMR5SEL
TMR1SEL
WWDTSEL
TMR4SEL
16
8
TMR3SEL
TMR2SEL
TMR0SEL
WDTSEL
1
0
MDCLKDIV
Bits
Description
TMR5SEL
Timer 5 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 5 controller.
00: TIMER5_SrcCLK = XIN.
[27:26]
[25:24]
[23:22]
[21:20]
01: TIMER5_SrcCLK = PCLK0.
10: TIMER5_SrcCLK = PCLK0/4096.
11: TIMER5_SrcCLK = 32.768 kHz.
Timer 4 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 4 controller.
00: TIMER4_SrcCLK = XIN.
TMR4SEL
TMR3SEL
TMR2SEL
01: TIMER4_SrcCLK = PCLK0.
10: TIMER4_SrcCLK = PCLK0/4096.
11: TIMER4_SrcCLK = 32.768 kHz.
Timer 3 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 3 controller.
00: TIMER3_SrcCLK = XIN.
01: TIMER3_SrcCLK = PCLK1.
10: TIMER3_SrcCLK = PCLK1/4096.
11: TIMER3_SrcCLK = 32.768 kHz.
Timer 2 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 2 controller.
00: TIMER2_SrcCLK = XIN.
01: TIMER2_SrcCLK = PCLK1.
10: TIMER2_SrcCLK = PCLK1/4096.
11: TIMER2_SrcCLK = 32.768 kHz.
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Timer 1 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 1 controller.
00: TIMER1_SrcCLK = XIN.
[19:18]
[17:16]
[11:10]
TMR1SEL
TMR0SEL
WWDTSEL
01: TIMER1_SrcCLK = PCLK0.
10: TIMER1_SrcCLK = PCLK0/4096.
11: TIMER1_SrcCLK = 32.768 kHz.
Timer 0 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for Timer 0 controller.
00: TIMER0_SrcCLK = XIN.
01: TIMER0_SrcCLK = PCLK0.
10: TIMER0_SrcCLK = PCLK0/4096.
11: TIMER0_SrcCLK = 32.768 kHz.
WWDT Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for WWDT controller.
00: WWDT_SrcCLK = XIN.
01: WWDT_SrcCLK = XIN/512.
10: WWDT_SrcCLK = PCLK2/4096.
11: WWDT_SrcCLK = 32.768 kHz.
WDT Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for WDT controller.
00: WDT_SrcCLK = XIN.
[9:8]
[7:0]
WDTSEL
01: WDT_SrcCLK = XIN/512.
10: WDT_SrcCLK = PCLK2/4096.
11: WDT_SrcCLK = 32.768 kHz.
MII Management Interface Clock
This field defines the clock divide number for clock divider to generate the clock for MII
management interface.
MDCLKDIV
The actual clock divide number is (MDCLK_N + 1). So,
MDCLK = HCLK / (MDCLK_N + 1).
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Clock Divider Control Register 9 (CLK_DIVCTL9)
Register
Offset
R/W Description
Reset Value
CLK_DIVCTL9 CLK_BA+0x044 R/W Clock Divider Control Register 9
0x0000_0000
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
CKO_N
CKO_S
SD1_N
SD1_S
22
Reserved
14
17
Reserved
9
6
1
0
Reserved
Reserved
Bits
Description
Reference Clock Out Divide
This field defines the clock divide number for clock divider to generate the reference clock output
The actual clock divide number is (CKO_N + 1). So,
[31:24]
[23:21]
CKO_N
CKO_CLK = CKO_SrcCLK / (CKO_N + 1).
Reserved
Reserved.
Reference Clock Out Source Selection
This field selects which clock is used to be the source of reference clock output.
00 = CKO_SrcCLK is from XIN.
[20:19]
CKO_S
01 = CKO_SrcCLK is from LXT.
10 = CKO_SrcCLK is from ACLKOut.
11 = CKO_SrcCLK is from UCLKOut.
[18:16]
[15:8]
Reserved
SD1_N
Reserved.
SD Card Controller 1 Engine Clock Divider
This field defines the clock divide number for clock divider to generate the engine clock for SD
card controller 1.
The actual clock divide number is (SD1_N + 1). So,
SD1_CLK = SD1_SrcCLK / (SD1_N + 1).
[7:5]
Reserved
Reserved.
SD Card Controller 1 Engine Clock Source Selection
This field selects which clock is used to be the source of engine clock for SD card controller 1.
00 = SD1_SrcCLK is from XIN.
[4:3]
[2:0]
SD1_S
01 = Reserved.
10 = SD1_SrcCLK is from ACLKOut.
11 = SD1_SrcCLK is from UCLKOut.
Reserved
Reserved.
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APLL Control Register (CLK_APLLCON), UPLL Control Register (CLK_UPLLCON)
Register
Offset
R/W Description
Reset Value
CLK_APLLCON CLK_BA+0x060 R/W APLL Control Register
CLK_UPLLCON CLK_BA+0x064 R/W UPLL Control Register
0x1000_0018
0xX000_0018
31
PLL_STB
23
30
RESETN
22
29
BYPASS
21
28
PD
20
27
19
11
26
18
25
17
9
24
16
8
FRAC
FRAC
15
14
OUT_DV
6
13
5
12
4
10
IN_DV
2
7
3
1
0
IN_DV
FB_DV
Bits
Description
PLL_STB
PLL Stable Flag
0 = PLL is not stable.
[31]
[30]
[29]
[28]
1 = PLL is stable (500us after PLL setting changed).
Reset Mode Enable Bit
RESETN
BYPASS
PD
0 = PLL is in reset mode.
1 = PLL is in normal operation mode (Default).
Bypass Mode Enable Bit
0 = PLL is in normal operation mode (Default).
1 = PLL is in bypass mode.
Power Down Mode Enable Bit
0 = PLL is in normal operation mode.
1 = PLL is in power down mode (Default).
PLL VCO Output Clock Feedback Divider Fraction Part
Set the fraction part (X) of feedback divider factor.
[27:16]
FRAC
Write a non-zero value to this field enables the fraction mode automatically. Please keep
this field in 0x0 if don’t want to use the PLL fraction mode.
The X = FRAC[11:0] / 212.
PLL Output Divider
[15:13]
[12:7]
OUT_DV
IN_DV
Set the output divider factor (P) from 1 to 8.
The P = OUT_DV[2:0] + 1.
Reference Input Divider
Set the reference divider factor (M) from 1 to 64.
The M = IN_DV[5:0] + 1.
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PLL VCO Output Clock Feedback Divider Integer Part
Set the feedback divider factor (N) from 1 to 128.
The N = FB_DV[6:0] + 1.
[6:0]
FB_DV
The formula to calculate the PLL output frequency shown below:
푁
퐹푝푙푙표푢푡 = 12 MHz ×
푀 × 푃
푁
퐹
푣푐표
= 12 MHz ×
푀
200 MHz < 퐹 < 500 푀퐻푧
푣푐표
12 푀퐻푧
퐹
푣푐표
퐹푝푓푑
=
=
푀
푁
N
1
2
3
4
5
6
Fpfd Range
11.0 ≤ Fpfd ≤ 80
7.0 ≤ Fpfd ≤ 80
5.0 ≤ Fpfd ≤ 80
4.0 ≤ Fpfd ≤ 80
3.5 ≤ Fpfd ≤ 80
3.0 ≤ Fpfd ≤ 80
2.5 ≤ Fpfd ≤ 80
3.5 ≤ Fpfd ≤ 80
3.0 ≤ Fpfd ≤ 80
2.5 ≤ Fpfd ≤ 80
7 ~ 8
9 ~ 10
11 ~ 40
41 ~ 128
Table 6.3-1 The Mapping of N and Fpfd Range
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PLL Stable Counter and Test Clock Control Register (CLK_PLLSTBCNTR)
Register
Offset
R/W Description
Reset Value
CLK_PLLSTBCNTR
CLK_BA+0x080 R/W PLL Stable Counter and Test Clock Control Register
0x0000_1800
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
PLLSTBCNT
PLLSTBCNT
1
0
Bits
Description
Reserved
[31:24]
[15:0]
Reserved.
PLLSTBCNT
PLL Stable Counter
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6.4 Advanced Interrpt Controller
6.4.1 Overview
An interrupt can temporarily change the sequence of program execution to react to some specific
events, such as power failure, watchdog timer timeout, transmit/receive requests from Ethernet MAC
Controller, and so on. There are two interrupt types the CPU can process. The first type is the Fast
Interrupt Request (FIQ) for servicing timing-critical events, and the second type is the Interrupt
Request (IRQ) for servicing other general-purpose events. An FIQ interrupt occurrs when the signal
nFIQ to the CPU is asserted, and a IRQ interrupt occurrs when the signal nIRQ to the CPU is
asserted.
A FIQ interrupt has higher priority than an IRQ interrupt to be processed by CPU. An IRQ service
routine in-process can be interrupted by a new coming FIQ interrupt; however, a FIQ service routine
in-process cannot be interrupted by a new coming IRQ interrupt.
The Advanced Interrupt Controller (AIC) can process up to 64 interrupt sources. Currently, 62 interrupt
sources are supported in the system. AIC assigns every interrupt source a unique source number. For
example, the watchdog timer interrupt is assigned to source number 1, and window WDT interrupt is
assigned to source number 2.
Every interrupt source can be configured to have one of eight priority levels, numbered from 0 to 7.
Interrupt sources with priority level 0 have the highest priority, and interrupt sources with priority level
7 have the lowest priority. For those interrupt sources with the same priority levels, an interrupt source
with a lower source number will have higher priority.
An interrupt request generated by an interrupt source with priority level 0 will become a FIQ interrupt
to the CPU. An interrupt request generated by an interrupt source with priority levels from 1 to 7 will
become a IRQ interrupt to the CPU.
Each interrupt source can be configured as disabled or enabled. An interrupt request from a disabled
interrupt source is always ignored by AIC, no matter what its source number and priority level are.
AIC supports four trigger types for every interrupt source: high-level trigger, low-level trigger, rising-
edge trigger, and falling-edge trigger.
6.4.2
Features
AMBA APB interface
62 interrupt sources
Configurable 8 priority levels for each interrupt source
Configurable 4 trigger types for each interrupt source
Configurable disabled/enabled status for each interrupt source
Readable on the current logic value of each interrupt source
Arbitration of interrupt requests from two or more interrupt sources
Easy programming of interrupt service routines
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6.5 SDRAM Interface Controller
6.5.1 Overview
The SDRAM Controller support SDR, DDR, Low-Power DDR and DDR2 type SDRAM. The memory
device size type can be from 16M bit and up to 1G bits. Only 16-bit data bus width is supported. The
total system memory size can be from 2M bytes and up to 256M bytes for different SDRAM
configuration.
The SDRAM controller interface to three isolated AHB. All these AHB masters can access the memory
independent. Except the memory access, the masters of AHB also could access the SDRAM control
registers.
For performance and function issue, the SDRAM controller also supports the proprietary Enhanced-
AHB. The EAHB add the down-count address mode, byte-enable signal and explicit burst access
number. The explicit access number function is reached by modify the HBURST signal to EHBURST
and it represent the access number. The maximum EAHB access number is 16. The SDRAM
controller also builds a BIST module to test the external memory device.
An internal arbiter is used to schedule the access from the masters and the BIST request, the BIST
request with the highest priority and the then the AHB3 master, AHB2 master and AHB1 master.
The SDRAM controller uses 3 pipe queues to improve the SDRAM command and data bus efficiency.
The request in queue0 is the SDRAM active data access request. Simultaneous, the requests in
queue1 can request the controller to issue the ACTIVE or PRECHARGE command to reduce the
access latency for the later command. The queue1 also can issue the READ or WRITE command to
close the SDRAM command when advance pipe queue
The SDRAM refresh rate is programmable. The Refresh and Power-on control module generate the
refresh request signal and SDRAM power on sequence. The SDRAM controller also supports software
reset, SDRAM self-refresh and auto power down function.
6.5.2
Features
Built-in 128MB/ 64MB/ 16MB SDRAM Memory in LQFP package
Clock speed up to 150 MHz
Support 16-bit data bus width
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6.6 External Bus Interface
6.6.1 Overview
This chip is equipped with an external bus interface (EBI) for external device use. To save the
connections between an external device and a chip, EBI is operating at address bus and data bus
multiplex mode. The EBI supports three chip selects that can connect three external devices with
different timing setting requirements.
6.6.2
Features
Supports up to three memory banks
Supports dedicated external chip select pin with polarity control for each bank
Supports accessible space up to 1 Mbytes for each bank, actually external addressable
space is dependent on package pin out
Supports 8-/16-bit data width
Supports Timing parameters individual adjustment for each memory block
Supports LCD interface i80 mode
Supports PDMA mode
Supports variable external bus base clock (MCLK) which based on HCLK
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
Supports address bus and data bus separate mode
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6.7 General Purpose I/O
6.7.1 Overview
This chip has up to 104 General-Purpose I/O (GPIO) pins and can be shared with other function pins
depending on the chip configuration. These 104 pins are arranged in 7 ports named as PA, PB, PC,
PD, PE, PF and PG. PA, PC, PD and PG has 16 pins on port. PB has 14 pins on port. PE and PF has
13 pins on port. Each of the 104 I/O pins is independent and can be easily configured by user to meet
various system configurations and design requirements.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output
or Open-drain output. After reset, all 104 I/O pins are configured in General-Purpose I/O Input mode.
6.7.2
Features
Three I/O modes:
–
–
–
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode in PB.0~PB.7
Supports independent pull-up and pull-down control
Enabling the pin interrupt function will also enable the wake-up function
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6.8 Peripheral DMA Controller
6.8.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer.
The PDMA controller can transfer data from one address to another without CPU intervention. This
has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications.
The PDMA controller has a total of 20 channels and each channel can perform transfer between
memory and peripherals or between memory and memory.
6.8.2
Features
Supports 2 PDMA controller, PDMA0 and PDMA1
Supports 10 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word or
no increment
Supports software and UART, SPI, I2C and Timer request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of the
descriptor link list table
Supports single and burst transfer type
Supports time-out function from channel 0 to channel 9
Supports stride function from channel 0 to channel 5
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6.9 Timer Controller (TMR)
6.9.1 Overview
The timer controller includes six 32-bit timers, Timer0 ~ Timer5, allowing user to easily implement a
timer control applications. The timer can perform functions, such as frequency measurement, delay
timing, clock generation, and event counting by external input pins, and interval measurement by
external capture pins.
6.9.2
Features
Six sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent Clock Source for each Timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function to count input event from pin TMx_ECNT (x = 0~5)
Supports toggle output to pin TMx_TGL (x = 0~5)
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports event capture from external pin TMx_EXT (x = 0~5) for interval measurement
Supports event capture from RTC 1Hz signal for RTC clock calibration
Supports event capture from external pin TMx_EXT (x = 0~5) to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Supports time-out interrupt or capture interrupt to trigger ADC and PDMA.
Supports Inter-Timer trigger that Timer 0 can trigger Timer 1, Timer 2 can trigger Timer 3,
and Timer4 can trigger Timer5.
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6.10 Pulse Width Modulation (PWM)
6.10.1 Overview
This chip has 2 PWM controllers, PWM0 and PWM1. Each PWM controller has 4 independent PWM
outputs.
PWM0 has 4 independent PWM outputs, CH0~CH3, or 2 complementary PWM pairs, (CH0, CH1),
(CH2, CH3) with 2 programmable dead-zone generators. PWM1 has 4 independent PWM outputs,
CH4~CH7, or 2 complementary PWM pairs, (CH4, CH5), (CH6, CH7) with 2 programmable dead-zone
generators. Each PWM pair has one prescaler, one clock divider, two clock selectors, two 16-bit PWM
counters, two 16-bit comparators, and one dead-zone e generator. They are all driven by APB system
clock (PCLK) in chip. Each PWM channel can be used as a timer and issue interrupt independently.
Two channels PWM Timers in one pair share the same prescaler. The Clock divider provides each
PWM channel with 5 divided clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock
signal from clock divider which receives clock from 8-bit prescaler. The 16-bit down-counter in each
channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-
bit comparator compares PWM counter value with threshold value in register CMR (PWM_CMR[15:0])
loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM
clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is
enabled, two outputs of the corresponding PWM channel pair will be replaced by the output of Dead-
Zone generator. The Dead-Zone generator is used to control off-chip power device.
To prevent PWM driving output pin with unsteady waveform, 16-bit down-counter and 16-bit
comparator are implemented with double buffering feature. User can feel free to write data to counter
buffer register and comparator buffer register without generating glitch. When 16-bit down-counter
reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches
zero, if counter is set as periodic mode, it is reloaded automatically and start to generate next cycle.
User can set PWM counter as one-shot mode instead of periodic mode. If counter is set as one-shot
mode, counter will stop and generate one interrupt request when it reaches zero. The value of
comparator is used for pulse width modulation. The counter control logic changes the output level
when down-counter value matches the value of compare register.
6.10.2 Features
8 PWM channels with a 16-bit down counter and an interrupt each
4 complementary PWM pairs, (CH0, CH1), (CH2, CH3), (CH4, CH5), (CH6, CH7), each
with a programmable dead-zone generator
Internal 8-bit prescaler and a clock divider for each PWM paired channel
Independent clock source selection for each PWM channel
Internal 16-bit down counter and 16-bit comparator for each independent PWM channel
PWM down-counter supports One-shot or Periodic mode
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6.11 Watchdog Timer
6.11.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.11.2 Features
20-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 220) and the time-out interval is 0.48828125ms ~ 32s if
WDT_CLK = 32.768 kHz
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
Supports to force WDT enabled after chip powered on or reset by setting WDTON
(SYS_PWRON [3])
Supports WDT time-out wake-up function only if WDT clock source is selected as LXT.
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6.12 Windowed Watchdog Timer (WWDT)
6.12.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.12.2 Features
6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the
WWDT time-out window period flexible.
Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter
period of WWDT counter.
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6.13 Real Time Clock (RTC)
6.13.1 Overview
The Real Time Clock (RTC) controller provides the real time clock and calendar information. The clock
source of RTC controller is from an external 32.768 kHz low-speed crystal which connected at pins
X32_IN and X32_OUT (refer to pin Description). The RTC controller provides the real time clock (hour,
minute, second) in RTC_TIME (RTC Time Loading Register) as well as calendar information (year,
month, day) in RTC_CAL (RTC Calendar Loading Register). It also offers RTC alarm function that
user can preset the alarm time in RTC_TALM (RTC Time Alarm Register) and alarm calendar in
RTC_CALM (RTC Calendar Alarm Register). The data format of RTC time and calendar message are
all expressed in BCD (Binary Coded Decimal) format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic RTC
Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second
which are selected by RTC_TICK (RTC_TICK[2:0] Time Tick Register). When real time and calendar
message in RTC_TIME and RTC_CAL are equal to alarm time and calendar settings in RTC_TALM
and RTC_CALM, the ALMIF (RTC_INTSTS [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC
alarm interrupt signal is generated if the ALMIEN (RTC_INTEN [0] Alarm Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or Power-
down mode if the corresponding interrupt enable bit (ALMIEN or TICKIEN) is set to 1 before chip
enters Idle or Power-down mode.
Real Time Clock (RTC) block can operate with independent power supply (RTC_VDD) while the
system power is off.
6.13.2 Features
Supports real time counter and calendar counter for RTC time and calendar check.
Supports time (hour, minute, second) and calendar (year, month, day) alarm and alarm
mask settings.
Selectable 12-hour or 24-hour time scale.
Supports Leap Year indication.
Supports Day of the Week counter.
Supports frequency compensation mechanism for 32.768 kHz clock source.
All time and calendar message expressed in BCD format.
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64,
1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.
Supports RTC Time Tick and Alarm match interrupt.
Supports chip wake-up from Idle or Power-down mode while alarm or relative alarm
interrupt is generated.
Supports 64 bytes spare registers to store user’s important information.
Supports power on/off control mechanism to control system core power.
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6.14 UART Interface Controller (UART)
6.14.1 Overview
The chip provides ten channels of Universal Asynchronous Receiver/Transmitters (UART). The UART
controller performs Normal Speed UART and supports flow control function. The UART controller
performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial
conversion on data transmitted from the CPU. Each UART controller channel supports ten types of
interrupts. The UART controller also supports IrDA SIR, LIN and, RS-485 function modes and auto-
baud rate measuring function.
6.14.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485
Address Match (AAD mode) wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement and baud rate compensation function
– Support 9600 bps for UART_CLK is selected LXT.
Supports break error, frame error, parity error and receive/transmit buffer overflow
detection function
Fully programmable serial-interface characteristics
– Programmable number of data bit, 5-, 6-, 7-, 8- bit character
– Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
– Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
– Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART1 /UART2 with LIN function)
– Supports LIN master/slave mode
– Supports programmable break generation function for transmitter
– Supports break detection function for receiver
Supports RS-485 function mode
– Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
Supports PDMA transfer function
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6.15 Smart Card Host Interface
6.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.15.2 Features
ISO 7816-3 T = 0, T = 1 compliant
EMV2000 compliant
Three ISO 7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 267 ETU)
One 24-bit timer and two 8-bit timers for Answer to Reset (ATR) and waiting times
processing
Supports auto direct / inverse convention function
Supports transmitter and receiver error retry and error number limiting function
Supports hardware activation sequence process, and the time between PWR on and CLK
start is configurable
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detected the card removal
Supports UART mode
– Full duplex, asynchronous communications
– Separates receiving / transmitting 4 bytes entry FIFO for data payloads
– Supports programmable baud rate generator
– Supports programmable receiver buffer trigger level
– Programmable transmitting data delay time between the last stop bit leaving the TX-
FIFO and the de-assertion by setting EGT (SCn_EGT[7:0])
– Programmable even, odd or no parity bit generation and detection
– Programmable stop bit, 1- or 2- stop bit generation
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6.16 I²C Serial Interface Controller
6.16.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision detection
and arbitration that prevents data corruption if two or more masters attempt to control the bus
simultaneously.
There are four sets of I2C controllers which support Power-down wake-up function.
6.16.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the I2C bus include:
Supports up to three I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows
Programmable clocks allow for versatile rate control
Supports 7-bit addressing and 10-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Power-down wake-up function
Supports setup/hold time programmable
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6.17 Serial Peripheral Interface (SPI)
6.17.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full
duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The
chip contains up to one set of SPI controllers performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device. Each SPI controller can be configured as a master or a slave device and supports
the PDMA function to access the data buffer.
6.17.2 Features
Up to two sets of SPI controllers
Supports Master or Slave mode operation
Master mode up to 100 MHz and Slave mode up to 30 MHz (when chip works at VDD =
2.7~3.6V)
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports one data channel half-duplex transfer
Supports receive-only mode
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6.18 Quad Serial Peripheral Interface (QSPI)
6.18.1 Overview
The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction
interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data
received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a
peripheral device.
The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access
the data buffer.
6.18.2 Features
Supports Master or Slave mode operation
Master mode up to 100 MHz and Slave mode up to 100 MHz (when chip works at VDD =
2.7~3.6V)
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports Byte or Word Suspend mode
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
Supports one data channel half-duplex transfer
Supports receive-only mode
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6.19 I²S Controller (I²S)
6.19.1 Overview
The I2S controller consists of I2S and PCM protocols to interface with external audio CODEC. The I2S
and PCM interface supports 8, 16, 18, 20 and 24-bit left/right precision in record and playback. When
operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each
left/right-channel sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding
zeros. When operating in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and
left-channel sample is stored in LSB of a 32-bit word.
The following are the property of the DMA.
When 16-bit precision, the DMA always 8-beat incrementing burst (FIFO_TH = 0) or 4-
beat incrementing burst (FIFO_TH = 1).
When 24/20/18-bit precision, the DMA always 16-beat incrementing burst (FIFO_TH = 0)
or 8-beat incrementing burst (FIFO_TH = 1).
Always bus lock when 4-beat or 8-beat or 16-beat incrementing burst.
When reach eighth, quarter, middle and end address of destination address, a DMA_IRQ
is triggered to CPU automatically.
An AHB master port and an AHB slave port are offered in I2S controller.
6.19.2 Features
Support I2S interface record and playback
– Left/right channel
– 8, 16, 20, 24-bit data precision
– Mater and slave mode
Support PCM interface record and playback
– Two slots
– 8, 16, 20, 24-bit data precision
– Master mode
Use DMA to playback and record data, with interrupt
Support two addresses for left/right channel data and different slots
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6.20 Ethernet MAC Controller (EMAC)
6.20.1 Overview
This chip provides 2 Ethernet MAC Controller (EMAC) for Network application.
The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM
function for recognizing Ethernet MAC addresses; Transmit-FIFO, Receive-FIFO, TX/RX state
machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status
controller.
The EMAC supports RMII (Reduced MII) interface to connect with external Ethernet PHY.
6.20.2 Features
Supports IEEE Std. 802.3 CSMA/CD protocol
Supports Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol
Supports both half and full duplex for 10 Mbps or 100 Mbps operation
Supports RMII interface
Supports MII Management function to control external Ethernet PHY
Supports pause and remote pause function for flow control
Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes)
reception
Supports 16 entries CAM function for Ethernet MAC address recognition
Supports Magic Packet recognition to wake system up from power-down mode
Supports 256 bytes transmit FIFO and 256 bytes receive FIFO
Supports DMA function
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6.21 High Speed USB 2.0 Device Controller (HSUSBD)
6.21.1 Overview
The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains
both the AHB master interface and AHB slave interface. CPU programs the USB controller registers
through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data
to memory or read data from memory through the AHB master interface. The USB device controller is
complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control
endpoint. These endpoints could be configured to BULK, INTERRUPT or ISOCHRONOUS. The USB
device controller has a built-in DMA to relieve the load of CPU.
6.21.2 Features
USB Specification reversion 2.0 compliant
Supports 12 configurable endpoints in addition to Control Endpoint
Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT
direction
Three different operation modes of an in-endpoint － Auto Validation mode, Manual
Validation mode, Fly mode
Supports DMA operation
4096 Bytes Configurable RAM used as endpoint buffer
Supports Endpoint Maximum Packet Size up to 1024 bytes
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6.22 USB 2.0 Host Controller (USBH)
6.22.1 Overview
This chip is equipped with a USB 2.0 HS/FS Host Controller (USBH) that supports Enhanced Host
Controller Interface (EHCI) and Open Host Controller Interface (OpenHCI, OHCI) Specification, a
register-level description of a host controller, to manage the devices and data transfer of Universal
Serial Bus (USB).
The USBH supports an integrated Root Hub with eight USB ports (two ports with on-chip USB 2.0 high
speed transceiver and up to six USB 1.1 Host Lite ports), a DMA for real-time data transfer between
system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing data
transfer, collecting status and activity of USB bus, providing power control and detecting over current
of attached USB devices.
6.22.2 Features
Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
Supports Enhanced Host Controller Interface (EHCI) Specification Revision 1.0
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB
devices.
Supports Control, Bulk, Interrupt, Isochronous and Split transfers.
Supports an integrated Root Hub.
Supports a port routing logic to route full/low speed device to OHCI controller.
Supports a USB host port with on-chip USB2.0 high speed transceiver shared with USB
device (dual-role function).
Supports a USB host only port with on-chip USB2.0 high speed transceiver.
Supports up to six USB 1.1 Host Lite ports.
Supports port power control and port over current detection.
Supports DMA for real-time data transfer.
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6.23 Controller Area Network (CAN)
6.23.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0
part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the
physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.23.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
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6.24 Flash Memory Interface (FMI)
6.24.1 Overview
The Flash Memory Interface (FMI) in this chip has DMA unit and FMI unit. The DMA unit provides a
DMA (Direct Memory Access) function for FMI to exchange data between system memory (ex.
SDRAM) and shared buffer (128 bytes), and the FMI unit control the interface of SD0/eMMC0 or
NAND Flash. The interface controller can support SD0/eMMC0 and NAND-type Flash and the FMI is
cooperated with DMAC to provide a fast data transfer between system memory and cards.
6.24.2 Features
Supports single DMA channel and address in non-word boundary.
Supports hardware Scatter-Gather function.
Supports 128Bytes shared buffer for data exchange between system memory and Flash
device. (Separate into two 64 bytes ping-pong FIFO).
Supports SD0/eMMC0 Flash device.
Supports SLC and MLC NAND type Flash.
Adjustable NAND page sizes. (2048B+spare area, 4096B+spare area and 8192B+spare
area).
Supports up to 8bit/12bit/24bit hardware ECC calculation circuit to protect data
communication.
Supports programmable NAND timing cycle
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6.25 Secure Digital Host Controller (SDH)
6.25.1 Overview
The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a
DMA (Direct Memory Access) function for SD to exchange data between system memory and shared
buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SD Host Controller can
support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory
and cards.
6.25.2 Features
AMBA AHB master/slave interface compatible, for data transfer and register read/write.
Supports single DMA channel.
Supports hardware Scatter-Gather function..
Using single 128 Bytes shared buffer for data exchange between system memory and
cards.
Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).
Interface with DMAC for register read/write and data transfer.
Supports SD/SDHC card.
Completely asynchronous design for Secure Digital with two clock domains, HCLK and
Engine clock, note that frequency of HCLK should be higher than the frequency of
peripheral clock.
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6.26 Cryptographic Accelerator (CRYPTO)
6.26.1 Overview
The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG)
core and supports AES, SHA, HMAC, RSA and ECC algorithms.
The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation.
The AES accelerator is an implementation fully compliant with the AES (Advance Encryption
Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB, OFB,
CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode.
The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224, SHA-256,
SHA-384, and SHA-512 and corresponding HMAC algorithms.
The ECC accelerator is an implementation fully compliant with elliptic curve cryptography by using
polynomial basis in binary field and prime filed.
The RSA accelerator is an implementation fully compliant with 1024 and 2048 bit RSA cryptography.
6.26.2 Features
PRNG
– Supports 64 bits, 128 bits , 192 bits, and 256 bits random number generation
AES
– Supports FIPS NIST 197
– Supports SP800-38A and addendum
– Supports 128, 192, and 256 bits key
– Supports both encryption and decryption
– Supports ECB, CBC, CFB, OFB , CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode
– Supports key expander
SHA
– Supports FIPS NIST 180, 180-2
– Supports SHA-160, SHA-224, SHA-256, SHA-384, and SHA-512
HMAC
– Supports FIPS NIST 180, 180-2
– Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-384, and
HMAC-SHA-512
ECC
– Supports both prime field GF(p) and binary filed GF(2m)
– Supports NIST P-192, P-224, P-256, P-384, and P-521
– Supports NIST B-163, B-233, B-283, B-409, and B-571
– Supports NIST K-163, K-233, K-283, K-409, and K-571
– Supports point multiplication, addition and doubling operations in GF(p) and GF(2m)
– Supports modulus division, multiplication, addition and subtraction operations in GF(p)
RSA
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– Supports both encryption and decryption
– Supports up to 2048 bits
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6.27 Capture Sensor Interface Controller (CAP)
6.27.1 Overview
The Image Capture Interface is designed to capture image data from a sensor. After capturing or
fetching image data, it will process the image data, and then FIFO output them into frame buffer.
6.27.2 Features
8-bit RGB565 sensor
8-bit YUV422 sensor
Supports CCIR601 YCbCr color range scale to full YUV color range
Supports 4 packaging format for packet data output: YUYV, Y only, RGB565, RGB555
Supports YUV422 planar data output
Supports the CROP function to crop input image to the required size for digital application
Supports the down scaling function to scale input image to the required size for digital
application
Supports frame rate control
Supports field detection and even/odd field skip mechanism
Supports packet output dual buffer control through hardware buffer controller
Supports negative/sepia/posterization color effect
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6.28 Analog to Digitial Converter (ADC)
6.28.1 Overview
The NuMicro® NUC980 series contains one 12-bit Successive Approximation Register analog-to-
digital converter (SAR A/D converter) with 9 input channels.
6.28.2 Features
Resolution: 12-bit resolution
DNL: +/-1.5 LSB, INL: +/-3 LSB
Data Rate up to 200kSPS
Analog Input Range: VREF to AGND, can be rail-to-rail
Analog Supply: 2.7-3.6V
Digital Supply: 1.2V
9 Single-Ended analog inputs
Auto Power Down
Low Power Consumption: 2170uW (at 200k SPS), < 1uA
Jan. 28, 2019
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7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
Core DC Power Supply
MIN.
MAX
UNIT
-0.3
-0.3
-0.3
+1.5
+4.6
+4.6
V
V
V
VVDD12−VVSS
VVDD33−VVSS
I/O DC Power Supply
I/O DC Power Supply for SDR Type SDRAM
MVDD − MVSS (1)
I/O DC Power Supply for DDR,DDR2 Type
SDRAM
-0.3
+2.3
V
MVDD - MVVSS(2)
VIN
TA
Input Voltage
VVSS-0.3
+5
+85
+150
200
200
20
V
Operating Temperature
-40
°C
TST
IDD
ISS
Storage Temperature
-55
°C
Maximum Current into CORE_VDD
Maximum Current out of CORE_VSS
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
30
IIO
200
200
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
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7.2 DC Electrical Characteristics
7.2.1 NUC980 Series DC Electrical Characteristics
(VDD33-VSS=3.3V, TA = 25°C, FOSC = 12 MHz unless otherwise specified.)
Specification
Parameter
Sym.
Test Conditions
MIN. TYP. Max.
Unit
Core Operation voltage
I/O Operation Voltage
VDD12
VDD33
1.14
2.97
1.2
3.3
1.32
3.63
V
V
Memory I/O Operation Voltage
for DDR or DDR2
MVDD (1)
1.70
1.8
1.90
V
Memory I/O Operation Voltage
for SDR Type SDRAM
MVDD (2)
VBAT33
2.97
2.0
3.3
3.3
3.63
3.63
V
V
V
Battery Operation Voltage
USB Operation Voltage (1)
VUSB0_VDD12
VUSB1_VDD12
1.14
2.97
1.2
3.3
1.32
3.63
USB Operation Voltage (2)
Power Ground
V
V
VUSB0_VDD33
VUSB1_VDD33
VSS
-0.3
AVSS
Analog Operating Voltage
Analog Reference Voltage
AVDD33
AVref
2.97
0
3.3
3.63
V
V
AVDD33
IVDD12
150
50
mA
mA
mA
mA
mA
mA
uA
VDD12 = 1.2V
MVDD = 1.8V
IMVDD_1
VDD33 = 3.3V
IUSB0_VDD12_1
IUSB1_VDD12_1
IUSB0_VDD33_1
IUSB1_VDD33_1
IVBAT33_1
7.5
7.5
35
TA = 25°C, FOSC = 12 MHz
Current Consumption of
Normal Operating Mode 1
Frequency
300/150 MHz.
of
CPUCLK/DDR_CLK
is
All IPs on, all GPIO are input with pull-up.
35
100
132
44
IVDD12
mA
mA
mA
mA
mA
mA
uA
VDD12 = 1.2V
MVDD = 1.8V
IMVDD_2
VDD33 = 3.3V
IUSB0_VDD12_2
IUSB1_VDD12_2
IUSB0_VDD33_2
IUSB1_VDD33_2
IVBAT33_2
7.5
7.5
35
TA = 25°C, FOSC = 12 MHz
Current Consumption of
Normal Operating Mode 2
Frequency
264/132 MHz.
of
CPUCLK/DDR_CLK
is
All IPs on, all GPIO are input with pull-up.
35
100
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Specification
Parameter
Sym.
Test Conditions
MIN. TYP. Max.
Unit
ISTDBY_VDD12
ISTDBY_MVDD
3
6
mA
mA
µA
µA
µA
µA
µA
µA
µA
VDD12 = 1.2V
MVDD = 1.8V
ISTDBY_VDD33
5
VDD33 = 3.3V
ISTDBY_USB0_VDD33
ISTDBY_USB1_VDD33
ISTDBY_USB0_VDD12
ISTDBY_USB1_VDD12
ISTDBY_AVDD33
0
VUSB0_VDD33 = 3.3V
VUSB1_VDD33 = 3.3V
VUSB0_VDD12 = 1.2V
VUSB1_VDD12 = 1.2V
AVDD33 = 3.3V
Current Consumption of
Power Down Mode
0
2.5
2.5
25
100
ISTDBY_VBAT33
VBAT33 = 3.3V
System Power Off & RTC
VBAT33 Power only
IVBAT33
10
uA
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7.2.2
NUC980 Series GPIO Characteristics
(VDD33-VSS=3.3 V, TA = 25°C, FOSC = 12 MHz unless otherwise specified.)
Input Leakage Current
VVDD33 = 3.63V
ILK1
-10
-
-
-
10
µA
PA, PB, PC, PD, PE, PF, PG
0V < VIN < VVDD33
Input Low Voltage
VIL1
0.8
V
VDD33 = 3.63V
PA, PB, PC, PD, PE, PF, PG
(TTL input)
Input High Voltage
VIH1
VIL2
VIH2
VHY
ISR21
2.0
-
-
V
V
VDD33 = 3.63V
PA, PB, PC, PD, PE, PF, PG
(TTL input)
Input Low Voltage
0.3*VDD33
PA, PB, PC, PD, PE, PF, PG,
(Schmitt input)
Input High Voltage
0.7*VDD33
V
PA, PB, PC, PD, PE, PF, PG,
(Schmitt input)
Hysteresis voltage
0.2*VDD33
V
PA, PB, PC, PD, PE, PF, PG
(Schmitt input)
Source Current
V
DD33 = 3.63V
8
mA
PA, PB, PC, PD, PE, PF, PG,
(Push-pull Mode)
VIN=VDD33-0.4
Sink Current
V
DD33 = 3.63V
PA, PB, PC, PD, PE, PF, PG
(Push-pull Mode)
ISK1
8
mA
VIN=VSS+0.4
Input Pull-up Resistance
VDD33=3.63V, apply GPIO pin Vin= 0V and
measure the input current
kΩ
kΩ
RPU
-
-
-
-
82
91
PA, PB, PC, PD, PE, PF, PG,
HDS
Reverse the current to Resistor value, R=V/I
VDD33=3.63V, apply GPIO pin Vin= 3.63V
and measure the input current
Input Pull-down Resistance
PA, PB, PC, PD, PE, PF, PG
RPD
Reverse the current to Resistor value, R=V/I
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7.3 AC Electrical Characteristics
7.3.1
External 12MHz High Speed Crystal
Symbol
VHXT
TA
Parameter
Min.
Typ.
Max
Unit
V
Test Conditions
Operation Voltage
Temperature
2.97
3.3
3.63
VHXT = VDD33
-40
-
85
-
-
°C
fHXT
Clock Frequency
Operating Current
-
-
12
0.8
MHz
mA
-
IHXT
-
TA=25OC, AVDD33=3.3V
Note: Guaranteed by characterization results, not tested in production.
7.3.1.1 Typical Crystal Application Circuits
Crystal
12 MHz
ESR (ohm)
< 50
C1, C2
15 pf
XT1_IN
XT1_OUT
12 MHz
Crystal
C1
C2
Vss
Vss
Figure 7.3-1 Typical HXT Crystal Application Circuit
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7.3.2
External 32.768 kHz Low Speed Crystal
Symbol
VLXT
Parameter
Min.
2.97
-40
Typ.
3.3
-
Max
3.63
85
Unit Test Conditions
Operation Voltage
Temperature
V
°C
VLXT = VBAT33
TA
-
-
fLXT
ILXT
Clock Frequency
Operating Current
-
32.768
1.6
-
kHz
uA
TA=25OC, VBAT33=3.3V
Note: Guaranteed by characterization results, not tested in production.
7.3.2.1 Typical Crystal Application Circuits
Crystal
C1
C2
32.768 kHz
15 pf
15 pf
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Figure 7.3-2 Typical LXT Crystal Application Circuit
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7.3.3
Power Sequence & nRESET Timing
7.3.3.1 Power up Sequence
Power up Sequence & nRESET Timing Case 1
When TVDD33 ≥ TMVDD ≥ TVDD12 (the time of delay gap between < 0.5mS is prefer).
Note:
1.
2.
The time of delay gap is meaning that timing between TVDD33 with TVDD12
.
If the time of delay gap < 0.5mS will be effective to prevent that transient phenomenon by power-on.
Figure 7.3-3 Power up Sequence & nRESET timing Case 1
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Power up Sequence & nRESET Timing Case 2
When TVDD12 ≥ TMVDD ≥ TVDD33, it is acceptable as the below figure. (the time of delay gap between <
1mS is prefer)
Note:
1.
2.
The time of delay gap is meaning that timing between TVDD12 with TVDD33
.
The time of delay gap < 1mS is prefer although NUC980 has that protection of latchup prevention.
Figure 7.3-4 Power up Sequence & nRESET timing Case 2
7.3.3.2 Power down Sequence,
Power down sequence between AVDD33/VDD33, VDD12 and MVDD is don’t care.
Note:
1.
2.
3.
TVDD12 represents VDD12 powered time.
TMVDD represents MVDD powered time.
T
VDD33 represents VDD33/AVDD33 powered.
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7.3.4
nRESET PIN characteristics
Symbol Parameter
Min.
-
Typ.
-
Max.
unit
V
Test Conditions
Negative going threshold
0.3*VDD33
VDD33 = 3.3V
VILR
(Schmitt input), nRESET
Positive going threshold
(Schmitt Input), nRESET
0.7*VDD33
-
-
V
VDD33 = 3.3V
VIHR
VDD33=3.63V, apply nRESET pin Vin=
3.63V and measure the input current
-
-
84
KΩ
RRST Internal nRESET pin pull up resistor
tFR1 nRESET input filtered time
Reverse the current to Resistor value,
R=V/I
32
uS
VDD33 = 3.3V
Note: Guaranteed by characterization and design results, not tested in production.
7.3.5
PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
12
fPLL_IN
fPLL_OUT
TS
PLL input clock
MHz
MHz
µs
25
500
200
PLL multiplier output clock
PLL stable time[*1]
100
Jitter
IDD12
150
ps
Cycle-to-cycle Jitter[*2]
Power consumption
Peak to peak @ 300M
VDD12=1.2V@500MHz
3
mA
Note: Guaranteed by characterization and design results, not tested in production.
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7.3.6
EBI Timing
Symbol
TtACS
Parameter
Min
Typ
Max
Unit
Test Condition
Address Setup Time to EBI_nCS
Falling Edge
[1]
-
0
-
THCLK
THCLK
THCLK
THCLK
THCLK
-
EBI_nCS Setup Time to
EBI_nWE or EBI_nOE Falling
Edge
[1]
[1]
[1]
[1]
TtCOS
-
1
-
-
32
8
-
-
-
-
EBI_nWE or EBI_nOE Active Low
Time
TtACC
1
0
1
EBI_nCS Hold Time from
EBI_nWE or EBI_nOE Rising
Edge
TtCOH
-
EBI_DATA Read Setup Time to
EBI_nOE Rising Edge
TSU_EBI_RD
-
-
Notes:
1. THCLK is the period of EBI’s operating clock.
Table 7.3-1 EBI Characteristics
EBI_ADDR[9:0]
EBI_nCS[4:0]
TtACS
TtCOS
TtCOH
EBI_nWE,
EBI_nBE[1:0]
TtACC+2
EBI_DATA[15:0
(Write)]
Valid Data
TtCOS
TtCOH
EBI_nOE
TtACC+2
TSU_EBI_RD
EBI_DATA[15:0
(Read)]
Valid Data
Figure 7.3-5 External Bus Interface Timing Diagram
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7.3.7
I2C Interface Timing
Symbol
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
4.7
4
Max
Min
1.3
Max
tLOW
SCL low period
-
-
µs
µs
µs
µs
µs
µs
ns
µs
ns
ns
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
SCL high period
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
4.7
4
-
0.6
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
100
0[4]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
-
Data hold time
3.45[5]
1000
300
400
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
-
tf
SCL/SDA fall time
-
Cb
Capacitive load for each bus line
-
-
Notes:
1. Guaranteed by characteristic, not tested in production
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Table 7.3-2 I2C Interface Characteristics
Repeated
START
STOP
START
STOP
I2C_SDA
I2C_SCL
TBUF
TLOW
TR
TF
THIGH
THD_STA
TSU_STA
TSU_STO
TSU_DAT
THD_DAT
Figure 7.3-6 I2C Interface Timing Diagram
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7.3.8
SPI Interface Timing
7.3.8.1 SPI Master Mode Timing
Specificaitons
Test Conditions
Symbol
Parameter
Min
-
Typ
-
Max
100
Unit
FSPICLK
SPI clock frequency
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1/ TSPICLK
tCLKH
tCLKL
tDS
ns
ns
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
Data output valid time
TSPICLK / 2
TSPICLK / 2
1.8
3.8
-
-
-
-
-
-
ns
ns
ns
tDH
tV
1.1
Note:
Table 7.3-3 SPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
SPIx_CLK
tV
Data Valid
SPIx_MOSI
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
SPIx_M
IS
O
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
SPIx_MOSI
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
SPIx_MISO
Figure 7.3-7 SPI Master Mode Timing Diagram
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7.3.8.2 SPI Slave Mode Timing
Test Conditions
Specificaitons
Symbol Parameter
Min
Typ
Max
Unit
FSPICLK
2.7 V ≤ VDD ≤ 3.6 V, CL = 30
pF
SPI clock frequency
1/ TSPICLK
-
-
30
MHz
tCLKH
tCLKL
Clock output High time
Clock output Low time
TSPICLK / 2
ns
ns
TSPICLK / 2
1 TSPICLK
2.7 V ≤ VDD ≤ 3.6 V, CL = 30
pF
tSS
Slave select setup time
-
-
ns
+ 2ns
tSH
tDS
tDH
Slave select hold time
Data input setup time
Data input hold time
1 TSPICLK
-
-
-
-
-
-
ns
ns
ns
1
3
2.7 V ≤ VDD ≤ 3.6 V, CL = 30
pF
tV
Data output valid time
-
-
10
ns
Note:
Table 7.3-4 SPI Slave Mode Characteristics
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SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPIx_SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
SPIx_CLK
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPIx_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
Data Valid
(SPIx_MOSI)
SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPIx_SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
SPIx_CLK
CLKPOL=1
TXNEG=1
RXNEG=0
tV
(SPIx_MISO)
SPI data output
Data Valid
tDH
Data Valid
tDS
(SPIx_MOSI)
SPI data input
Data Valid
Data Valid
Figure 7.3-8 SPI Slave Mode Timing Diagram
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7.3.9
QSPI Interface Timing
7.3.9.1 QSPI Master Mode Timing
Specificaitons
Test Conditions
Symbol
Parameter
Min
-
Typ
-
Max
100
Unit
FSPICLK
SPI clock frequency
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
1/ TSPICLK
tCLKH
tCLKL
tDS
ns
ns
Clock output High time
Clock output Low time
Data input setup time
Data input hold time
Data output valid time
TSPICLK / 2
TSPICLK / 2
1.8
3.8
-
-
-
-
-
-
ns
ns
ns
tDH
tV
1.5
Note:
Table 7.3-5 QSPI Master Mode Characteristics
tCLKH
tCLKL
CLKP=0
CLKP=1
QSPIx_CLK
tV
Data Valid
QSPIx_MOSI
Data Valid
CLKP=0, TX_NEG=1, RX_NEG=0
or
CLKP=1, TX_NEG=0, RX_NEG=1
tDS
tDH
QSPIx_M
I
SO
Data Valid
tV
Data Valid
Data Valid
Data Valid
Data Valid
QSPIx_MOSI
CLKP=0, TX_NEG=0, RX_NEG=1
or
CLKP=1, TX_NEG=1, RX_NEG=0
tDS
tDH
Data Valid
QSPIx_MISO
Figure 7.3-9 QSPI Master Mode Timing Diagram
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7.3.9.2 QSPI Slave Mode Timing
Specificaitons
Test Conditions
Symbol
Parameter
Min
Typ
Max
30
Unit
FSPICLK
1/ TSPICLK
SPI clock frequency
-
-
MHz
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tCLKH
Clock output High time
Clock output Low time
TSPICLK / 2
TSPICLK / 2
ns
ns
tCLKL
1 TSPICLK
+ 2ns
tSS
Slave select setup time
-
-
ns
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
tSH
tDS
Slave select hold time
Data input setup time
Data input hold time
Data output valid time
1 TSPICLK
-
-
-
-
-
ns
ns
ns
ns
2.1
4.1
-
-
-
tDH
tV
11.5
2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF
Note:
Table 7.3-6 QSPI Slave Mode Characteristics
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SSACTPOL=1
SSACTPOL=0
tSS
tSH
QSPIx_SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=1
RXNEG=0
QSPIx_CLK
CLKPOL=1
TXNEG=0
RXNEG=1
tV
QSPI data output
(QSPIx_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
QSPI data input
Data Valid
(QSPIx_MOSI)
SSACTPOL=1
SSACTPOL=0
tSS
tSH
QSPIx_SS
tCLKH
tCLKL
CLKPOL=0
TXNEG=0
RXNEG=1
Q Ix_CLK
SP
CLKPOL=1
TXNEG=1
RXNEG=0
tV
(QSPIx_MISO)
QSPI data output
Data Valid
tDH
Data Valid
tDS
(QSPIx_MOSI)
QSPI data input
Data Valid
Data Valid
Figure 7.3-10 QSPI Slave Mode Timing Diagram
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7.3.10 I2S Interface Timing
Symbol
Parameter
I2S_BITCLK Period
Min
50
Typ
Max
Unit
ns
Test Condition
TP_I2S_BITCLK
TH_I2S_BITCLK
TL_I2S_BITCLK
-
-
-
-
-
-
-
-
-
I2S_BITCLK High Time
I2S_BITCLK Low Time
25
ns
25
ns
I2S_BITCLK Rising to Valid
I2S_WS or I2S_DATAO Delay
TDLY_I2S_DO
THD_I2S_DO
TSU_I2S_DI
THD_I2S_DI
-
-
-
-
-
6
-
ns
ns
ns
ns
-
I2S_WS or I2S_DATAO Hold Time
from I2S_BITCLK Rising
1
5
3
I2S_DATAI Setup Time to
I2S_BITCLK Rising
-
-
-
I2S_DATAI Hold Time from
I2S_BITCLK Rising
-
Table 7.3-7 I2S Interface Characteristics
TP_I2S_BITCLK
TL_I2S_BITCLK TH_I2S_BITCLK
I2S_BITCLK
I2S_DATAI
TSU_I2S_DI
THD_I2S_DI
I2S_WS
I2S_DATAO
TDLY_I2S_DO
THD_I2S_DO
Figure 7.3-11 I2S Interface Timing Diagram
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7.3.11 Ethernet Interface Timing
7.3.11.1 RMII Interface Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
20.0 +/- 50
ppm
TP_RMII_REFCLK
RMII_REFCLK Period
-
-
ns
-
TH_RMII_REFCLK
TL_RMII_REFCLK
RMII_REFCLK High Time
RMII_REFCLK Low Time
8.0
8.0
10.0
10.0
12.0
12.0
ns
ns
-
-
RMII_REFCLK Rising to Valid
RMII_TXEN, RMII_TXDATA0 and
RMII_TXDATA1 Delay
TDLY_RMII_TX
TSU_RMII_RX
THD_RMII_RX
-
-
-
-
17.3
ns
ns
ns
-
-
-
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Setup Time to
RMII_REFCLK Rising
5
2
-
-
RMII_CRSDV, RMII_RXDATA0
and RMII_RXDATA1 Hold Time
from RMII_REFCLK Rising
Table 7.3-8 RMII Interface Characteristics
TP_RMII_REFCLK
TH_RMII_REFCLK
TL_RMII_REFCLK
RMIIx_REFCLK
RMIIx_TXEN
RMIIx_TXDATA0
RMIIx_TXDATA1
TDLY_RMII_TX
RMIIx_CRSDV
RMIIx_RXDATA0
RMIIx_RXDATA1
TSU_RMII_RX
THD_RMII_RX
Figure 7.3-12 RMII Interface Timing Diagram
Jan. 28, 2019
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7.3.11.2 Ethernet PHY Management Interface Timing
Symbol
Parameter
Min
400
200
200
Typ
Max
Unit
ns
Test Condition
TP_RMII_MDC RMII_MDC Period
TH_RMII_MDC RMII_MDC High Time
TL_RMII_MDC RMII_MDC Low Time
-
-
-
-
-
-
-
-
-
ns
ns
RMII_MDC Falling to Valid
TDLY_RMII_MDIOWR
-
-
-
-
10
-
ns
ns
ns
-
-
-
RMII_MDIO Delay
RMII_MDIO Setup Time to
TSU_RMII_MDIORD
10
10
RMII_MDC Rising
RMII_MDIO Hold Time from
THD_RMII_MDIORD
-
RMII_MDC Rising
Table 7.3-9 Ethernet PHY Management Interface Characteristics
TP_RMII_MDC
TH_RMII_MDC
TL_RMII_MDC
RMIIx_MDC
RMIIx_MDIO
(Write)
TDLY_RMII_MDIOWR
RMIIx_MDIO
(Read)
TSU_RMII_MDIORD
THD_RMII_MDIORD
Figure 7.3-13 Ethernet PHY Management Interface Timing Diagram
Jan. 28, 2019
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7.3.12 NAND Interface Timing
Symbol
TH_NAND_nWE
TL_NAND_nWE
Parameter
Min
Typ
13.34[1]
40[2]
Max
Unit
ns
Test Condition
NAND_nWE High Time
NAND_nWE Low Time
-
-
-
-
-
-
ns
NAND_nRE Falling to Valid
NAND_DATA Delay
TDLY_DATA_OUT
THD_DATA_OUT
TSU_DATA_IN
-
-
-
-
-
35[3]
ns
ns
ns
ns
-
-
-
-
NAND_DATA Hold Time from
NAND_nRE Rising
-
30[3]
NAND_DATA Setup Time to
NAND_nWE Rising
20[3]
10[3]
-
-
NAND_DATA Hold Time from
NAND_nWE Rising
THD_DATA_IN
Notes:
1. NAND controller operating clock is 150 MHz and HI_WID (FMI_NANDTMCTL[15:8]) is 0x1.
2. NAND controller operating clock is 150 MHz and LO_WID (FMI_NANDTMCTL[7:0]) is 0x5.
3. NAND controller operating clock is 150 MHz.
Table 7.3-10 NAND Interface Characteristics
NAND_nCS0
NAND_nCS1
NAND_ALE
NAND_CLE
NAND_nRE
THD_DATA_OUT
TDLY_DATA_OUT
NAND_DATA[7:0]
(Read)
TL_NAND_nWE
TH_NAND_nWE
NAND_nWE
THD_DATA_IN
TSU_DATA_IN
NAND_DATA[7:0]
(Write)
Figure 7.3-14 NAND Interface Timing Diagram
Jan. 28, 2019
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7.3.13 SD Interface Timing
7.3.13.1 Default Mode Timing
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
SD_CLK Period
TP_SD_CLK
40
-
-
ns
-
(Data Transfer Mode)
SD_CLK Period
TP_SD_CLK_ID
2,500
-
-
ns
(Identification Mode)
TH_SD_CLK
TL_SD_CLK
SD_CLK High Time
SD_CLK Low Time
-
-
20
20
-
-
ns
ns
-
-
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
5
5
-
-
-
-
-
-
ns
ns
ns
-
-
-
SD_DATA Hold
SD_CLK Rising
Time
from
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
14
Valid SD_DATA Delay
Table 7.3-11 SD Interface Default Mode Characteristics
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
Figure 7.3-15 SD Interface Default Mode Timing Diagram
Jan. 28, 2019
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7.3.13.2 High-Speed Mode Timing
Symbol
TP_SD_CLK
TH_SD_CLK
TL_SD_CLK
Parameter
SD_CLK Period
Min
20
7
Typ
Max
Unit
ns
Test Condition
-
-
-
-
-
-
-
-
-
SD_CLK High Time
SD_CLK Low Time
ns
7
ns
SD_DATA Setup Time to
SD_CLK Rising
TSU_SD_IN
6
2
-
-
-
-
-
-
ns
ns
ns
ns
-
-
-
-
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_IN
SD_CLK Falling to
TDLY_SD_OUT
-
14
-
Valid SD_DATA Delay
SD_DATA Hold Time from
SD_CLK Rising
THD_SD_OUT
2.5
Table 7.3-12 SD Interface High-Speed Mode Characteristics
TP_SD_CLK
TL_SD_CLK
TH_SD_CLK
SDx_CLK
SDx_CMD
SDx_DATA[3:0]
(Input Mode)
TSU_SD_IN
THD_SD_IN
SDx_CMD
SDx_DATA[3:0]
(Output Mode)
TDLY_SD_OUT
THD_SD_OUT
Figure 7.3-16 SD Interface High-Speed Mode Timing Diagram
Jan. 28, 2019
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7.3.14 Capture Sensor Interface Timing
Symbol
Parameter
VCAP_PCLK Period
Min
Typ
-
Max
Unit
ns
Test Condition
TP_VCAP_PCLK
TH_VCAP_PCLK
TL_VCAP_PCLK
20
-
-
-
-
-
-
-
VCAP_PCLK High Time
VCAP_PCLK Low Time
10.0
10.0
ns
-
ns
VCAP_HSYNC, VCAP_VSYNC,
VCAP_FIELD and VCAP_DATA
Setup Time to VCAP_PCLK Rising
TSU_VCAP_IN
4
1
-
-
-
-
ns
ns
-
-
VCAP_HSYNC, VCAP_VSYNC,
VCAP_FIELD and VCAP_DATA
Hold Time from VCAP_PCLK
Rising
THD_VCAP_IN
Table 7.3-13 Capture Sensor Interface Characteristics
TP_VCAP_PCLK
TH_VCAP_PCLK
TL_VCAP_PCLK
VCAP_PCLK
VCAP_HSYNC
VCAP_VSYNC
VCAP_FIELD
VCAP_DATA
TSU_VCAP_IN
THD_VCAP_IN
Figure 7.3-17 Capture Sensor Interface Timing Diagram
Jan. 28, 2019
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7.4 Analog Characteristics
7.4.1 12-bit SARADC
Symbol
Parameter
Min.
Typ.
12
Max.
Unit
Test Conditions
-
DNL
INL
EO
Resolution
-
-
-
-
-
-
-
-
-
-
-
-
Bit
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
±1
LSB VREF is external AVref pin
LSB VREF is external AVref pin
LSB VREF is external AVref pin
LSB VREF is external AVref pin
LSB VREF is external AVref pin
-1.2
+3.7
-6.6
4.2
EG
Gain Error (Transfer Gain)
Absolute Error
EA
-
Monotonic
Guaranteed
FADC
TADC
FS
ADC Clock Frequency
Conversion Time
Sample Rate
-
-
-
20
-
16
MHz
Clock
SPS
V
200k
3.63
AVDD33
IDDA1
IDDA2
IDDA3
ILK
Supply Voltage
2.97
3.3
1.2
1.0
0.4
0.1
-
Supply Current (Avg.)
Supply Current (Avg.)
Supply Current (Avg.)
Leakage Current
-
-
mA
mA
mA
uA
V
ADC channel 1 high speed mode
ADC channel 1 low speed mode
-
-
-
AVREF
VIN
Reference Voltage
Analog Input Voltage
Analog Input Impedance
Capacitance
2
0
-
AVDD33
AVref
2
-
V
MΩ
pF
RIN
-
CIN
-
25.6
VBG no trim for VREF output, the
accuracy is 6% typically at
100ppm/℃
VBG
Band-gap 2.5V voltage output
2.5
V
Jan. 28, 2019
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7.4.2
Low Voltage Detection (LVD) and Low Voltage Reset (LVR)
Symbol
AVDD33
ILVDR
Parameter
Operation Voltage
Min.
Typ.
3.3
21
Max
Unit
V
Test Conditions
2.0
3.63
-
-
Operating Current
Quiescent Current
Temperature
uA
LVR_EN (SYS_LVRDCR[0]) = 0,
LVD_EN (SYS_LVRDCR[8]) = 0
ILK
TA
-
0.1
0.5
uA
-40
-
85
-
°C
V
V
V
V
V
V
2.295
2.475
2.115
0.045
0.045
0.045
2.55
2.75
2.35
0.05
0.05
0.05
2.805
3.025
2.585
0.055
0.055
0.055
LVD_SEL (SYS_LVRDCR[9]) = 0
VTH_LVD
VTH_LVR
VHY_LVD
VHY_LVR
LVD Threshold Voltage
LVR Threshold Voltage
LVD Hysteresis
LVD_SEL (SYS_LVRDCR[9]) = 1
-
LVD_SEL (SYS_LVRDCR[9]) = 0
LVD_SEL (SYS_LVRDCR[9]) = 1
-
LVR Hysteresis
Note: Guaranteed by characterization results, not tested in production.
7.4.3
3.3V Power-On Reset (POR33)
Symbol
TA
VPOR33
IPOR33
Parameter
Temperature
Min
Typ
25
Max
Unit
°C
Test Condition
-40
85
-
-
Reset Voltage
-
-
1.83
5
V
AVDD33 rising from 0V to 3.3V
Vin > reset voltage
Quiescent current
-
nA
Note: Guaranteed by characterization results, not tested in production.
7.4.4
1.2V Power-On Reset (POR12)
Symbol
TA
VPOR12
IPOR12
Parameter
Temperature
Min
Typ
25
Max
Unit
°C
Test Condition
-
-40
85
-
Reset Voltage
-
-
0.76
10
V
VDD12 rising from 0V to 1.2V
Vin > reset voltage
Quiescent current
-
nA
Note: Guaranteed by characterization results, not tested in production.
Jan. 28, 2019
Page 231 of 246
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7.4.5
USB 2.0 PHY
7.4.5.1 Low/Full-Speed DC Electrical Specifications
Symbol
VOL
Parameter
Output Low (Driven)
Min
-
Typ
Max
0.3
-
Unit
V
Test Condition
-
1.5K RPU on DP to 3.6v
VOH
VDI
Output High (Driven)
2.8
0.2
0.8
-
-
V
15K RPD on DP, DM to GND
Differential Input Sensitivity
Differential Common-Mode Range
Single-Ended Input Low
Single-Ended Input High
Pull-Up Resistor
-
-
V
|VUSB0_DP–VUSB0_DM|
VCM
VIL
-
-
2.5
0.8
-
V
V
-
-
VIH
2.0
1.35
-
V
kΩ
RPU
1.5
1.65
kΩ
kΩ
Ω
RPD_DP
RPD_DM
ZDRV
D+ Pull-Down Resistor
D- Pull-Down Resistor
Driver Output Resistance
13.5
13.5
28
15
15
-
16.5
16.5
44
Steady state drive[1]
Pin to GND
Transceiver Low-Speed
Donwstream Port Capacitance
CIN
CIN
CIN
200
50
600
150
pF
pF
pF
Transceiver Low-Speed
Upstream Port Capacitance
Pin to GND
Transceiver Full-Speed
Capacitance
50
Note:
1.
2.
Driver output resistance doesn’t include series resistor resistance.
Guaranteed by characterization results, not tested in production.
7.4.5.2 High-Speed DC Electrical Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
High Speed Differential Input
Signal Level
VHSDI
150
-
-
mV
|VUSB0_DP–VUSB0_DM
|
|
High Speed Squelch Detection
Threshold
VHSQ
100
-50
125
-
150
500
mV
mV
|VUSB0_DP–VUSB0_DM
High Speed Common Mode
Voltage Range
VHSCM
VHSOH
VHSOL
VCHIRPJ
VCHIRPK
High Speed Data Signaling High
High Speed Data Signaling Low
Chirp J Level
300
-10
400
440
10
mV
mV
mV
mV
0
-
700
-900
1100
-500
Chirp K Level
-
High Speed Driver Output
Resistance
Ω
RHSDRV
40.5
45
49.5
Note: Guaranteed by characterization results, not tested in production.
Jan. 28, 2019
Page 232 of 246
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7.4.5.3 USB Low-Speed Driver AC Electrical Characteristics
Symbol
TLRISE
Parameter
Min
75
Typ
Max
300
300
Unit
ns
Test Condition
Rise Time
Fall Time
-
-
CL=200pF, 10% to 90% of |VOH-VOL
|
|
TLFALL
75
ns
CL=200pF, 10% to 90% of |VOH-VOL
Excluding the first transition from idle
state
VLCR
Crossover Voltage
1.3
-
2.0
V
Note: Guaranteed by characterization results, not tested in production.
7.4.5.4 USB Full-Speed Driver AC Electrical Characteristics
Symbol
VFRISE
Parameter
Min
4
Typ
Max
20
Unit
ns
Test Condition
Rise Time
Fall Time
-
-
CL=50pF, 10% to 90% of |VOH-VOL
|
VFFALL
4
20
ns
CL=50pF, 10% to 90% of |VOH-VOL|
Excluding the first transition from idle
state
VFCR
Crossover Voltage
1.3
-
2.0
V
Note: Guaranteed by characterization results, not tested in production.
7.4.5.5 USB High-Speed Driver AC Electrical Characteristics
Symbol
VHRISE
Parameter
Min
500
500
Typ
Max
900
900
Unit
ps
Test Condition
CL<10pF
High Speed Driver Rise Time
High Speed Driver Fall Time
-
-
VHFALL
ps
CL<10pF
Note: Guaranteed by characterization results, not tested in production.
Jan. 28, 2019
Page 233 of 246
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8 PACKAGE DIMENSIONS
8.1 LQFP216 (24x24x1.4mm footprint 2.0mm)
Jan. 28, 2019
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8.2 LQFP128 (14x14x1.4mm footprint 2.0mm)
Jan. 28, 2019
Page 235 of 246
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8.3 LQFP64-EP (10x10x1.4mm footprint 2.0 mm)
Jan. 28, 2019
Page 236 of 246
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Jan. 28, 2019
Page 237 of 246
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8.4
Thermal Characteristics
8.4.1
Thermal Performance of LQFP under Forced Convection
θ ja (℃/W)
θ jc (℃/W)
θ jb (℃/W)
PKG Type
PCB condition
0 m/s
42.5
39.8
35.9
28.5
-
1 m/s
35.9
33.5
29
2m/s
33.8
31.7
27.2
21
JEDEC 1S1P (2-layers)
JEDEC 2S2P (4-layers)
JEDEC 1S1P (2-layers)
JEDEC 2S2P (4-layers)
JEDEC 1S1P (2-layers)
JEDEC 2S2P (4-layers)
9.2
9
35.16
32.08
22
LQFP 216L
24mmx24mm
16.5
14.3
-
LQFP64-EP
10x10mm
22.5
-
15.56
-
-
LQFP 128L
14mmx14mm
38.5
33.8
32
9.9
-
Table 8.4-1 Thermal Performance of LQFP
8.4.2
Thermal Performance Terminology
The major thermal dissipation paths can be illustrated as following
TJ: the maximum junction temperature;
TA: the ambient or environment temperature;
TC: the top center of compound surface temperature;
TB: the bottom center of PCB surface temperature;
P: total input power
Figure 8.4-1 Junction to Ambient Thermal Resistance
Jan. 28, 2019
Page 238 of 246
Rev 1.00
NUC980
Figure 8.4-2 Junction to Case Thermal Resistance
8.4.3
Simulation Conditions
Input Power
Top Die: 0.6W
Bottom die: 0.6 W
Test Board (PCB)
Control Condition
FR4 Cu=1-OZ
PCB size = 3”x4.5”
PCB thickness= 1.6mm
Air Flow = 0, 1, 2, 3 m/s
Table 8.4-2 Thermal Characteristics Simulation Conditions
Jan. 28, 2019
Page 239 of 246
Rev 1.00
NUC980
8.5
PCB Reflow Profile Suggestion
8.5.1 Profile Setting Consideration
Figure 8.5-1 PCB Reflow Profile Diagram
Sn-Pb Eutestic Assembly
Large Body Small Body
Pb-Free Eutestic Assembly
Large Body Small Body
< 3°C/second
Profile Feature
Average ramp-up rate (TL to TP)
Preheat
< 3°C/second
100°C
150°C
150°C
200°C
•
•
•
Temperature Min (Tsmin)
Temperature Max (Tsmax
Time (min to max) (ts)
)
60-120 seconds
60-180 seconds
Time maintained above:
183°C
217°C
•
•
Temperature (TL)
Time (tL)
60-150 seconds
60-150 seconds
Peak Temperature (Tp)
225+0/-5°C
245+5/-5°C
Time within 5°C of actual Peak
Temperature (tp)
10-20 seconds
10-30 seconds
Ramp-down Rate
Time 25°C to Peak Temperature
Notes:
3°C/second max.
6 minutes max.
3°C/second max.
8 minutes max.
1. All temperatures refer to topside of the package, measured on the package body surface.
2. Depends on other parts on board density and follower solder paste manufacturer’s guideline.
Table 8.5-1 PCB Reflow Profile Parameters
Jan. 28, 2019
Page 240 of 246
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NUC980
8.5.2 Profile Suggestion
Figure 8.5-2 Profile Suggestion for NUC980 series
Reheat time
Dwell time
150°C-200°C: 105+/-15sec
Over 220°C: 70+5/-10 sec
240+10/-5°C
Peak Temp
Up: 3 +0/-2°C/sec
Ramp Up/Dwon Rate
Down: 2+0/-1°C/sec
Table 8.5-2 Profile Parameters for NUC980 Series
Jan. 28, 2019
Page 241 of 246
Rev 1.00
NUC980
8.6
PKG Baking and Vacuumed
The moisture-sensitivity caution label (see Figure 8.6-1) is applied to the outside of the sealed
moisture-barrier bag. This label contains detailed information specific to the device (moisture-
sensitivity level, shelf life, etc.).
Figure 8.6-1 Cautions for PKG Baking
Jan. 28, 2019
Page 242 of 246
Rev 1.00
NUC980
9
ABBREVIATIONS
Acronym
Description
ADC
AES
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Interrupt Controller
Advanced Peripheral Bus
Advanced High-Performance Bus
Advanced Microprocessor Bus Architecture
Bose–Chaudhuri–Hocquenghem
Bit Per Second
AIC
APB
AHB
AMBA
BCH
BPS
CAN
CSMA/CD
DDR
DDR2
DMA
EBI
Controller Area Network
Carrier Sense Multiple Access with Collision Detection
Double Data Rate
Double Data Rate 2
Direct Memory Access
External Bus Interface
ECC
ECC
EHCI
EMAC
eMMC
ETU
Elliptic Curve Cryptography
Error Correcting code
Enhance Host Controller Interface
Ethernet MAC Controller
Embedded Multimedia Card
Elementary time unit
FIFO
FIQ
First In, First Out
Fast Interrupt
FMI
Flash Memory Interface
GPIO
HCLK
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
HMAC
keyed-Hash Message Authentication Code
High Speed USB 2.0 Device Controller
HSUSBD
HXT
I2C
12 MHz External High Speed Crystal Oscillator
Inter-Integrated Circuit
Inter-IC Sound
I2S
LIN
Local Interconnect Network
Low Power DDR
LPDDR
LSB
Least Significant Bit
Jan. 28, 2019
Page 243 of 246
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NUC980
LVD
Low Voltage Detect
LVR
Low Voltage Reset
LXT
32.748 kHz External Low Speed Crystal Oscillator
Multi-Level Cell NAND flash
Memory Management Unit
Most Significant Bit
MLC
MMU
MSB
OHCI
PCLK
PCM
PDMA
PLL
Open Host Controller Interface
The Clock of Advanced Peripheral Bus
Pulse Code Modulation
Peripheral Direct Memory Access
Phase-Locked Loop
PMBus
PRNG
PWM
RMII
RSA
Power Management Bus
Pseudo Random Number Generator
Pulse Width Modulation
Reduced Media Independent Interface
Rivest、Shamir and Adleman Cryptography
Real Time Clock
RTC
SC
Smart Card
SD
Secure Digital
SDHC
SDIC
SDIO
SDR
SHA
Secure Digital High Capacity
SDRAM Interface Controller
Secure Digital Input Output
Single Data Rate
Secure Hash Algorithm
SLC
Single Level Cell NAND flash
System Management Bus
Serial Peripheral Interface
Samples per Second
SMBus
SPI
SPS
TMR
UART
USB
Timer Controller
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 9‑1 List of Abbreviations
Jan. 28, 2019
Page 244 of 246
Rev 1.00
NUC980
10 REVISION HISTORY
Date
Revision
1.00
Description
2019.01.28
1.
Initial version.
Jan. 28, 2019
Page 245 of 246
Rev 1.00
NUC980
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Jan. 28, 2019
Page 246 of 246
Rev 1.00
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SI9137DB
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